Application Note
Contents
1. A20M Recognized Ignored Recognized Recognized Recognized Recognized Access Cached Cached Cached Cached Cached Cached to System Memory Access Not cached Not cached Cached unless Cached unless Cached unless Cached unless to KEN 1 during KEN 1 KEN during KEN 1 during SMM access during access access access Memory Table 2 System Management Mode Page 6 of 12 October 12 1995 Fax 40012 Low Power Halt All of the processors listed in Table 3 except the standard version of Intel 486DX2 DX4 and the Intel Pentium P5 offer a low power halt function This is accessed through the HLT in struction The IBM 486DX2 DX4 also offers hardware entry through the SUSP pin The IBM processors must enable this function before it can be used and Intel processors always have this function enabled The IBM processors stop the internal clocks during low power halt The exter nal clock on the Intel Pentium P54C cannot be stopped the during this state it must return to nor mal state before stopping the external clock Table 3 summarizes the low power halt feature 000 1486DxX2 Intel Pentium BLSX2 SX3 IBM 486DX2 DX4 1486DX4 Std SL Enhanced P5 60 or P54C 90 or 66 MHz 100MHz HLT HLT instruction instruction Entry HLT instruction HW SUSP HLT instruction SW HLT instruction Exit RESET PWI HW RESET or INTR or NMI deassert SUSP SW RESET SMI INTR or NM2. 66 76 mW f 40 50 MHz 1 75 100 mA P 259 345 mW 1 13 18 mA P 63 90 mW 1 35 45 mA P 175 225 mW f 50 66 MHz External Clock Off Note f indicates internal operation frequency Information obtained from databooks Table 8 CPU Power Dissipation in Low Power State Conclusion This paper described five power saving features available on X86 processors It explained how to use each feature and discussed advantages and disadvantages of certain processors When selecting a processor for a system the designer should consider the benefits of power manage ment and decide which features are needed For more information please consult the references listed below Page 11 of 12 October 12 1995 Fax 40012 References 1 IBM 486 DX2 Addendum to the IBM Blue Lightning 486 DX2 Databook August 11 1995 2 Intel 486 Microprocessor Family Databook 1994 3 Enhanced Am486 Microprocessor Family Datasheet May 1995 4 IBM 486 DX4 Addendum to the IBM Blue Lightning 486 DX2 Databook September 12 1995 5 IBM Blue Lightning 486 DX2 Databook 1994 6 IBM Blue Lightning Microprocessor Datasheet February 7 1994 7 Penttum Family User s Manual 1994 IBM Corporation 1995 All rights reserved IBM and the IBM logo are registered trademarks of International Business Machines Corporation IBM Mi croelectronics is a trademark of the IBM Corp All other product and company
3. names are trademarks registered trademarks of their respective holders 1995 IBM Corp This document may contain preliminary information and is subject to change by IBM without notice IBM makes no representations or warranties that the use of the information or applications herein shall be free of third party intellectual property claims and assumes no responsibility or liability from any use of the informa tion contained herein Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in physical harm or injury to persons NO WARRANTIES OF ANY KIND INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE OFFERED IN THIS DOCUMENT All performance data contained in this publication was obtained in a specific environment and is presented as an illustration The results obtained in other operating environments may vary Page 12 of 12 October 12 1995 Fax 40012
4. saves the CPU state to the header area in SMRAM It resets some architected registers disables INTR and NMI interrupts enters Real addressing mode and begins executing the service routine The locations of the header and service routine are specified by each processor The service routine is developed by the system designer and installed in SMRAM at boot up The last instruction in the routine causes the processor to exit the routine refresh the CPU state from SMRAM and resume executing in the mode it was in prior to receiving the SMM Page 2 of 12 October 12 1995 Fax 40012 1 1486DX4 PERRA ee 4 Standard SL P5 P54C Enhanced 60 or 66 90 or 100 MHz Numbers in the heading of this and the following tables designate entries in the References Sec tion at the end of this document interrupt For the IBM 486SX2 and 486SX3 processors the PWIRET instruction performs this function All other processors studied use the RSM instruction to exit SMM mode Figure 1 illustrates the transi tion to and from SMM mode U Below is a technique to put the CPU into a low power state Flush the cache if using Intel CPU or early revisions of IBM 486DX2 DX4 Intel CPUs may cache accesses to SMM memory so the cache must be flushed upon SMM entry and exit Rev 4 1 and earlier of IBM 486DX2 DX4 does not snoop the bus during halt Enter SMM mode SMM routine enables INTR or NMI then executes HLT to enter low pow
5. I RESET RESET SRESET SRESET SMI INTR or SMI INTR or RESET INIT SMI INTR or NMI Enable MSR1000 13 1 HW CCR2 7 1 Always Always Always enabled SW CCR2 3 1 enabled enabled Internal OFF OFF ON ON ON Clocks Table 3 Low Power Halt Adjustable Core Clock Multiplier This feature allows the speed of the CPU core clock to be adjusted with respect to the ex ternal bus clock It is available on the IBM 486SX2 IBM 486SX3 Intel DX4 and 100MHz ver sion of the Intel Pentium P54C The other processors in Table 4 operate the core at a fixed ratio 2x for 486DX2 amp 3x for 486DX4 CPUs 1x for Intel Pentium P5 1 5x for 9OMHz Intel Pentium P540 The IBM 486SX2 and 486SX3 are capable of running the core at 1x or 2x The 486SX3 can also run the core at 3x The default is 1x and it is controlled by writing a configuration regis ter after RESET The Intel DX4 operates the core at 2x or 3x The default is 3x and it is con trolled by tying the CLKMUL pin at RESET The 100MHz version of the Intel Pentium P54C operates the core at 1 5x or 2x with a maximum internal frequency of 1OOMHz It is controlled by tieing the BF pin at RESET Table 4 shows the core clock multiplier for each processor Page 7 of 12 October 12 1995 Fax 40012 IBM 000 1486DX2 Intel Pentium BLSX2 SX3 1486DX4 486DX2 486DX4 Standard SL P5 60 or P54C 90 or Enhanc
6. Low Power Halt 3 Adjustable Core Clock Multiplier 4 Dynamic Frequency Shift 5 Additional Features The first feature controls system power and the other features control the processor only Table 1 on the following page shows the power management pins on each processor System Management Mode System Management Mode SMM is an X86 operating environment which allows the processor to manage power through software which runs transparent to the operating system and applications programs SMM mode is intended for use only by system firmware not by applications Many things can be done in SMM mode An idle processor can be put into a low power state or shutdown as described earlier This is an ideal application for portable PCs where clos ing the lid can trigger an SMM interrupt to prepare for shutdown The concept can be extended to desktop systems where the processor can be powered down if it has been idle for some time SMM mode can also manage I O devices Devices can be powered down when not in use and powered up when they are needed When instructions are directed to an offline device SMM software suspends activity to this device powers up the device and reissues the instruction stream SMM mode is entered through a dedicated hardware interrupt and uses a separate mem ory space SMRAM which holds the CPU state and interrupt service routine When an SMM in terrupt occurs the processor finishes the current instruction and then
7. Power Management Features of X86 Microprocessors Authors Jack R Smith and Sebastian Fee Ventrone ni Application Note Introduction This paper describes techniques to control power consumption in X86 based computers The IBM 486 series Intel 486 series and Intel Pentium series microprocessors are studied and their power management features are compared Each processor studied has the ability to manage power in one or more ways The proces sors are similar in this respect but there are vast differences in the ways they perform this task IBM announced a new feature on 486DX2 DX4 to reduce these differences Background on Power Management X86 power management allows the microprocessor to regulate the amount of electrical power consumed by the system Using power management the microprocessor can control its own power as well as the power consumed by system logic memory and peripheral devices Power management is important to customers for the following reasons 1 it reduces the cost of operating office systems 2 it extends battery life in portable systems and 3 it conforms to appli cable international energy standards The original Thinkpad portable computer contained an Intel 386SX microprocessor In 1986 IBM developed a Thinkpad based on the IBM 386SLC processor that has an on chip cache and a faster clock However a major drawback of the original 386SLC design was its power consumption The original 386SLC consum
8. SET or INIT or RESET or RESET Enable Always HW Always enabled Always Always enabled Always enabled Enabled CCRI 1 1 enabled CCR1 2 0 SMAR 3 0 gt 0 SW CCRI 1 1 CCR1 2 1 SMAR 3 0 gt 0 Header 00060000h Defined by 0003FE00h 0003FE00h 0003FE00h 0003FE00h Location 0006014Ch SMAR 0003FFFFh 0003FFFFh 0003FFFFh 0003FFFFh relocatable relocatable relocatable relocatable Service Bootstrap Defined by 00038000h 00038000h 00038000h 00038000h Routine address at SMAR relocatable relocatable relocatable relocatable Location FFFFFFFOh During System Management Mode SMM INTR Disabled Disabled Disabled Disabled Disabled Disabled Enabled by Enabled by Enabled by Enabled by Enabled by STI instruction STI STI STI STI instruction instruction instruction instruction NMI Disabled Disabled 1 Disabled 1 Disabled 1 Disabled 1 Disabled 1 event latched event latched event latched event latched event latched Enabled by Enabled by IRET Enabled by Enabled by IRET Enabled by IRET CCR3 1 instruction IRET instruction instruction instruction SMM INO PWI is NO SMI is 1 event latched 1 event 1 event latched 1 event latched Interrupt output during output during latched SMM mode SMM mode HALT YES if IF 1 YES YES if INTR or YES if INTR YES if INTR or YES if INTR or or MSR1000 NMI enabled or NMI NMI enabled NMI enabled 5 1 enabled Warm None NO NO NO INIT INIT Reset
9. ating system to ensure proper operation The traditional method is used today The SMM method will be used in future systems All of the processors listed in Table 1 above except the standard version of the Intel 486DX2 DX4 implement SMM mode All come with SMM enabled at power up except IBM 486DX2 DX4 which must configure SMM before it can be used All processors listed in Table 1 offer a hardware interrupt The IBM processors also offer a software interrupt The hardware interrupt on IBM 486SX2 and 486SX3 is PWI and all other processors listed in Table 1 use SMI The pin is bidirectional on IBM processors and unidirectional on Intel processors On IBM processors the system drives the pin to enter SMM mode and then the CPU drives the pin when it is in SMM mode Intel processors do this differently For Intel processors SMI as an input only and SMIACT is an output asserted when SMM mode is active Since In tel processors have separate interrupt and acknowledge pins they can process nested SMM interrupts Another pinout difference between IBM and Intel processors is memory address strobes IBM processors have two address strobes ADS for normal accesses PWI _ADS or SMADS for SMM accesses Intel processors have one address strobe ADS and the SMIACT signal differentiates normal accesses from SMM accesses Page 4 of 12 October 12 1995 Fax 40012 All processors listed in Table 1 except Intel Pentium P5 support I O instruction re
10. ch consumes much more power than any other processor in Table 8 when the external clock is running Page 9 of 12 October 12 1995 Fax 40012 V 3 3V V 3 45V V 3 6V 1 0 73A P 2 63W f 75MHz SX3 V 4 2V 1 1 16A P 4 87W f 100MHz SX3 Va55 0V 1 0 78A 1 P 3 88W f 50MHz 000 1486DX2 BLSX2 SX3 IBM 486DX2 DX4 Standard SL Enhanced 1 0 46A 1 P 1 52W f 50MHz 1 0 98A 1 P 4 88W f 66MHz Note f indicates internal operation frequency T1486DX4 1 0 83A 1 P 2 85W f 75MHz 1 1 17A 2 P 4 04W f 100MHz Intel Pentium P5 60 or 66MHz P54C 90 or 1 2 37 2 60A 1 P 11 85 13 0W 60 66MHz 100MHz 1 1 18A 1 P 3 9W f 100MHz Table 7 CPU Power Dissipation Under Normal Conditions Values in table 7 are the BAPCo 93 ratings in all cases except 1 value listed in Intel databook 2 DOS edit prompt with menu pulled down Page 10 of 12 October 12 1995 Fax 40012 000 1486DX2 Intel Pentium BLSX2 8X3 i ee p Standard SL Enhanced B86DX4 5 60 or P54C 90 or 66MHz 1OOMHz Enter HLT when HLT when No low power STPCLK STPCLK No low STPCLK Low MSR1000 13 CCR2 3 1 or state power Power 1 SUSP when state State CCR2 7 1 External Clock On 1 424 470 mA P 1400 1550 mW 90 100 MHz 1 20 23 mA P
11. dditional Features Table 6 shows some additional power management features The primary one is the abil ity to stop the external clock Stop clock is available on all processors except the standard ver sion of Intel 486DX2 DX4 and Intel s Pentium P5 It is accessed through the HLT instruction on IBM processors and the STPCLK pin on Intel processors The IBM 486DX2 DX4 can also stop clocks using the SUSP pin Page 8 of 12 October 12 1995 Fax 40012 000 1486DX2 Intel Pentium BLSX2 8X3 3 ea 4 Standard SL F86DX4 p5 60 or P54C 90 or Enhanced 66MHz 1OOMHz Stop External Yes Yes No Yes Yes No Yes Clock ALT HLT or STPCLK STPCLK STPCLK SUSP Tri state Outputs No Yes Yes Yes Yes No No amp Power Down UP UP UP UP Cache Low Power Yes No No No No No No MSR1004 28 FPU powers down No Yes No No No No No when idle CPU powers down No No No Yes Yes No No when idle CPU CPU reduces core reduces clock to 1X core clock when idle to 1X when and waiting idle and for read data waiting for from read data memory or from YO memory or Yo Power Supply 3 0V 4 2V 3 3V or 5 0V 5 0V 3 3V or 3 45V 5 0V 3 3V 5 0V Table 6 Additional Features Power Saving Comparison Tables 7 and 8 give numeric values for power dissipation in the normal and low power states Most notable in the low power state is the Intel Pentium P54C whi
12. ed 66MHz 1OOMHz Multiple 1X 2X or 3x 2X 3X 2X 2X 2X 2 5X or 3X 1X 1 5X or 2X Default is 1X Write Default is 3X Tie Default is 1 5X MSR1002 26 24 CLKMUL at Tie BF at RESET after RESET RESET 2X CLKMUL V 2 5X CLKMUL BREQ 3X CLKMUL V or floating Table 4 Core Clock Multiplier Dynamic Frequency Shift This feature is available on all IBM processors Intel SL Enhanced 486DX2 Intel DX4 and Intel Pentium P54C It allows the system to vary the frequency of the external clock after power up The IBM 486SX2 and 486SX3 activate this feature through the DFS_REQ pin or a configuration bit The IBM 486DX2 DX4 always has this feature ready for use and Intel proces sors activate this through the STPCLK pin Table 5 shows how to use dynamic frequency shift on each processor 000 1486DX2 Intel Pentium BLSX2 SX3 BL486DxX2 1486DX4 IDXA4 Std SL Enhanced P5 60 or P54C 90 or 100 66MHz MHz HW Assert DFS_REQ Change Assert STPCLK Assert STPCLK Assert STPCLK wait for DFS_RDY then frequency then change then change then change change frequency of CLK2 lof clock any frequency of frequency of CLK frequency of SW Set MSR1002 27 wait time CLK CLK for MSR1002 28 then change frequency of CLK2 Enable HW MSR1000 10 1 Always Always enabled Always enabled Always enabled MSR1000 29 1 enabled SW Always enabled Table 5 Dynamic Frequency Shift A
13. ed more power than the Intel 386SX Several engineering discussions were held to solve this problem and it was determined that power could be significantly reduced by implementing an efficient shutdown procedure The new shutdown procedure became known as the IBM power management architec ture and is implemented in current versions of the IBM 386SLC 486SLC2 and Blue Lightning processors The core of the new architecture is a new mode of operation System Management Mode which is accessed through a chip input PWI or SMI When the input is asserted the processor finishes the current instruction saves the state of the CPU to memory and enters Sys tem Management Mode Ifthe processor is using an on chip write back cache it must be flushed before removing power from the processor When power is returned the processor restores the state of the CPU and resumes processing in the mode it was in prior to receiving the PWI inter rupt In addition to System Management Mode IBM added to the 386SLC a low power halt Page 1 of 12 October 12 1995 Fax 40012 function and a dynamic frequency shift protocol Low power halt allows the processor to turn off its internal clocks during the halt state to achieve minimum standby power Dynamic frequency shift allows the system to reduce the external clock frequency at certain times which reduces power consumption An X86 microprocessor can manage power in the following ways 1 System Management Mode 2
14. er state Stop external clock to processor When the processor is needed start the external clock interrupt the halt state and exit SMM Below is a technique to shutdown the CPU Flush the cache if write back 2 Enter SMM mode SMM routine copies header CPU state to another memory location and sets an SMM indicator bit in memory Disconnect power to CPU Page 3 of 12 Date Issued 10 12 95 Fax 40012 After power is returned the CPU resets BIOS reads the SMM indicator bit from mem ory determines that the CPU was in SMM mode before shutdown and gives an SMM interrupt The CPU enters SMM mode The SMM routine reads the original CPU state from the other memory location puts it into the header in SMRAM and exits SMM mode SMM provides a faster but more risky means of shutting down the CPU than the traditional method SMM is con trolled by processor microcode and runs independent of the operating system The traditional Save state Reset registers Disable interrupts PEROS E Enter Real mode instruction instruction instruction instruction MM interr S instruction gt le upt SMM e instruction lt Service e S f Routine a Instruction lt e Restore State return PWIRET or RSM Figure 1 SMM Execution Flow method uses standard interrupt protocol assert INTR pin execute power management routine return via IRET instruction and relies on the oper
15. start during SMM This function is enabled through a configuration register IBM SX2 and SX3 or bits in the SMM header IBM 486DX2 DX4 Intel DX4 Intel Pentium P54C Table 2 on the following page lists the SMM features on each processor For some time the pinout differences made SMM incompatible from processor to proces sor Recently IBM announced a new feature to clear this up On the 3 3 volt version of the Blue Lightning 486DX2 DX4 the SMM hardware interface can be made functionally compatible with Intel SL Enhanced 486DX2 DX4 by setting a configuration bit If bit 3 in configuration register CCR3 is set IBM s SMI pin is compatible with Intel s SMI pin and the SMADS pin is com patible with Intel s SMIACT pin If this bit is reset the chip operates as it did before The soft ware interrupt is not available when CCR3 3 is set Page 5 of 12 October 12 1995 Fax 40012 000 l486DX2 Intel Pentium BLSX2 SX3 IBM 1486DX4 486DX2 Dx4 Std SL Enhanced P5 60 or 66MHz P54C 90 or 100MHz Entry HW HW Assert SMI Assert SMI 1 Assert SMI 1 Assert SMI 1 Assert Assert SMI 1 cycle cycle cycle cycle PWI 2 cycles 12cycles SW SW SMINT PWIBP instruction instruction Exit PWIRET RSM RSM instruction RSM RSM instruction RSM instruction instruction instruction or RESET instruction RESETor INIT RE
Download Pdf Manuals
Related Search