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USER`S MANUAL ERRATA

1. 6 8 6 3 Instruction Set SYMDOIS ertet e et ate 6 8 6 4 Instruction Notation Conventions 6 9 6 5 Opcode Quick nnn nens 6 10 6 6 Condition 0 2 44 1 1 0 ennt enne 6 12 8 1 S3C84H5X F84H5X Set 1 Register values after 8 2 8 2 S3C84H5X F84H5X Set 1 Bank 0 Register values after RESET 8 3 8 3 S3C84H5X F84H5X Set 1 Bank 1 Register values after RESET 8 4 9 1 S3C84H5X F84H5X Port Configuration Overview 9 1 9 2 Port Data Register 9 2 13 1 PWM Control and Data Registers sse 13 2 13 2 PWM output stretch Values for Extension Data Register PWMDATAL 1 0 13 3 15 1 Commonly Used Baud Rates Generated by 16bit BRDATA 15 7 17 1 Watch Timer Control Register WTCON Set 1 Bank 1 RW 17 2 19 1 Descriptions of Pins Used to Read Write the Flash 19 4 19 2 Comparison of S3F84H5X and S3C84H5X 19 4 S3C84H5X F84H5X UM REV 1 10 MICROCONTROLLER List of Tables Table Title
2. Setting the Register Pointers Using the RPs to Calculate the Sum of a Series of Addressing the Common Working Register Standard Stack Operations Using PUSH Chapter 9 Ports Using the Timer A ius d itd dd de tl dd dE don a d dabo c Edd E A E Chapter11 98 bit Timer To generate 38 kHz 1 signal through 2 0 To generate one pulse signal through 2 0 Timer A ote dee e tre di du eii d etie ri Pa redu dado Using the Timer Bac nk iride dn aov ag iacu ee de Chapter 12 16 bit Timer 1 0 1 Using 1 0 iui etam idit Chapter 13 10 Bit PWM Pulse Width Modulation Programming the PWM Module to Sample Chapter 14 Serial I O Interface Chapter 16 A D Converter Configuring A D ener 17 Watch Timer Using the Watch Timer iiec iacente S3C84H5X F84H5X_UM_REV 1 10 MICROCONTROLLER Page Number IURE 11 10 xvii List of Register Descriptions R
3. Pao 1 0 P2 0 TBPWM T1CKO Configration Bits Input mode T1CKO input oja Alternative function mode 1 input 1 0 Push pull output mode Alternative function mode TBPWM mode 4 20 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 CONTROL REGISTER P2PUR Port 2 Pull up Resistor Control Register FAH Set1 RESET Value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W 7 2 7 Pull up Resistor Enable Disable Pull up resistor disable Pull up resistor enable 6 P2 6 Pull up Resistor Enable Disable Pull up resistor disable Pull up resistor enable 5 P2 5 Pull up Resistor Enable Disable E Pull up resistor disable Pull up resistor enable 4 P1 4 Pull up Resistor Enable Disable Pull up resistor disable Pull up resistor enable 3 P2 3 Pull up Resistor Enable Disable EN Pull up resistor disable Pull up resistor enable 2 P2 2 Pull up Resistor Enable Disable ES Pull up resistor disable Pull up resistor enable 1 P2 1 Pull up Resistor Enable Disable EN Pull up resistor disable Pull up resistor enable 0 P2 0 Pull up Resistor Enable Disable Pull up resistor disable Pull up resistor enable ELECTRONICS 4 2 CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 P3CONL Port 3 Control Register Low Byte EFH Set1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode on
4. 7 1 7 2 Sub System Oscillator Circuit Crystal Oscillator 7 1 7 3 System Clock Circuit 7 2 7 4 System Clock Control Register 2 404 4 00 00 7 3 7 5 Oscillator Control Register OSCCON 7 4 7 6 STOP Control Register 7 4 9 1 Port 0 Low Byte Control Register 9 3 9 2 Port 1 High Byte Control Register 9 5 9 3 Port 1 Low Byte Control Register 9 6 9 4 Port 1 Interrupt Pending Register 8 9 7 9 5 Port 1 Interrupt Enable Register P1INT 9 8 9 6 Port 2 High Byte Control Register 9 9 9 7 Port 2 Low Byte Control Register 2 9 10 9 8 Port 2 Pull up Control Register 9 11 9 9 Port Low Byte Control Register 9 12 10 1 Basic Timer Control Register 10 2 10 2 Basic Timer Block Diagram 10 4 Timer A Control Register 11 3 Timer A Functional Block Diagram 11 4 11 3 Timer B Functional Block Diagram
5. ELECTRONICS 6 11 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes Binary Mnemonic Description Flags Set 0000 F Always false 1000 T Always true 0111 1 C 1 1111 1 NC No carry C 0 0110 1 Z Zero Z 1 1110 1 NZ Not zero Z 0 1101 PL Plus 5 0 0101 Minus 5 1 0100 Overflow V 1 1100 NOV No overflow 0 0110 1 EQ Equal Z 1 1110 1 NE Not equal Z 0 1001 GE Greater than or equal 5 0 0001 Less than S XOR V 1 1010 GT Greater than Z OR S XOR V 0 0010 LE Less than or equal 7 V 1 1111 1 UGE Unsigned greater than or equal C 0 0111 1 ULT Unsigned less than C 1 1011 UGT Unsigned greater than 0 AND Z 0 1 0011 ULE Unsigned less than or equal C OR Z 1 NOTES 1 indicate condition codes which are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is s
6. 3 7 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 3 9 Indexed Addressing to Program or Data 3 9 3 10 Direct Addressing for Load 3 10 3 11 Direct Addressing for Call and Jump 3 11 3 12 Indirect 0 0 11 21 11 3 12 3 13 Relative Addressing 3 13 3 14 Immediate Addressing sse eee 3 14 4 1 Register Description Format 4 4 S3C84H5X F84H5X_UM_REV 1 10 MICROCONTROLLER xi List of Figures Continued Figure Title Page Number Number 5 1 S3C8 Series Interrupt nenne 5 2 5 2 S3C84H5X F84H5X Interrupt Structure 5 4 5 3 ROM Vector Address Area 5 5 5 4 Interrupt Function 5 8 5 5 System Mode Register 5 10 5 6 Interrupt Mask Register 5 11 5 7 Interrupt Request Priority Groups sse 5 12 5 8 Interrupt Priority Register 5 13 5 9 Interrupt Request Register 5 14 6 1 System Flags Register FLAGS 6 6 7 1 Main Oscillator Circuit Crystal or Ceramic Oscillator
7. 4 21 PSCONL Port Control Register Low Byte 4 22 PP Register Page Polnter ir ecce eter tatit tere Tui e Da ede agg ec Mea ieu ae EROR 4 23 PWMCON PWM Control 4 24 RPO Register Pointer cer CEP EIE REA GERE PEDES 4 25 RP1 Register Pointer T deci Avi deed 4 25 SIOCON Serial Module Control 4 26 SIOPS SIO Register 4 27 SPH Stack Pointer High enne nnne nns 4 27 SPL Stack Pointer Low Byte irais tiai iinitan ada iani entente nnne nnns 4 27 STOPCON Stop Control Register 4 28 SYM System Mode nnne nennen nnns intent 4 29 T1CONO Timer 1 0 Control nenas 4 30 1 Timer 1 1 Control 02002400 entente nnne nnne nenas 4 31 TACON Timer A Control 4 32 TBCON Timer B Control Register ssessssssssssssseseeeeee ener entente 4 33 TINTPND Timer A Timer 1 Interrupt Pending 4 34 UARTCON UART Register pde dL lel eI E ial avin 4 35 UARTPND UART Pending and parity control
8. Set if the bit rotated from the most significant bit position bit 7 was 1 Z Setifthe result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 10 R 4 11 IR Given Register 00H OAAH register 01H 02H and register 02H 17H 0 RLC 00H gt Register OOH RLC 01H gt Register 01H 54H 1 02H register 02H 2 0 In the first example if the general register OOH has the value 10101010 the statement RLC OOH rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of the register OOH leaving the value 55H 01010101B The MSB of the register OOH resets the carry flag to 1 and sets the overflow flag ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET RR Rotate Right RR Operation Flags Format Examples dst lt dst 0 dst 7 lt dst 0 dst lt dst n 1 n 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag au Lr C Setifthe bit rotated from the
9. 5 6 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INTERRUPT STRUCTURE ENABLE DISABLE INTERRUPT INSTRUCTIONS El DI Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an El instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing e interrupt mask register IMR enables un masks or disables masks interrupt levels interrupt priority register IPR controls the relative priorities of interrupt levels e interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source e The system mode register SYM enables disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register i RW Function Description
10. 2 15 4 Bit Working Register Addressing 2 16 8 Bit Working Register Addressing 2 18 System and User 4 52 55 0 5650 2059 3 0 12 8021 28250 2 20 Chapter 3 Addressing Modes 3 1 Register Addressing Mode 22 2 1 0 eee ener nnen nennen nnne 3 2 Indirect Register Addressing Mode eene 3 3 Indexed Addressing Mode X nan nannten nans 3 7 3 10 Indirect Address Mode 3 12 Relative Address 3 13 Immediate Mode IM 3 14 S3C84H5X F84H5X_UM_REV 1 10 MICROCONTROLLER Table of Contents Continued Chapter 4 Control Registers ecu Chapter 5 Interrupt Structure LL Interrupt TYDES einat S3C84H5X F84H5X Interrupt Structure Interrupt Vector Addresses Enable Disable Interrupt Instructions El D
11. N REF r DAP SIZE 3 8 X 3 8 2 E UUUUUUWUWU 49 r ke 3 20 0 10 a E S 5 8 F 1 0 35 62 62 r1 4 Yi ie 1 Qu ie 22777 227 o 22 INDEX v 8 SN Lo 4050 10 3 S mx 0 0 0 05 0 20 0 05 32x i p 920 REF 32x 1 1 0101 1 00 Figure 21 2 32 ELP 0505 Package Dimensions O ELECTRONICS 22 S3C84H5X F84H5X ERRATA REV 1 10 USER S MANUAL ERRATA 31 DEVELOPMENT TOOLS Chapter 22 OVERVIEW Samsung provides a powerful and easy to use development support system on a turnkey basis The development support system is composed of a host system debugging tools and supporting software For a host system any standard computer that employs Win95 98 2000 XP as its operating system can be used A sophisticated debugging tool is provided both in hardware and software the powerful in circuit emulator OPENice i500 and SK 1200 for the S3C7 S3C9 and S3C8 microcontroller families Samsung also offers supporting software that includes debugger an assembler and a program for setting options Target Boards Target boards are available for all the S3C8 S3F8 series microcontrollers All the required target system cables and adapters are included on the device specific target board TB84H5 is a specific target
12. Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst r opc dst 2 8 jump taken rA RA 8 no jump r OtoF Example Given R1 02H and LOOP is the label of a relative address SRP 0COH DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In the example the working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements the register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 El _ Enable Interrupts Operation Flags Format Example SYM 0 1 The El instruction sets bit zero of the system mode register SYM 0 to 1 This allows interrupts to be serviced as they occur assuming they have the highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when the El instruction is executed No flags are affected Bytes Cycles Opcode Hex opc 1 4 Given SYM OOH If the SYM register contains the value that is if interrupts are currently disabled the statement EI sets the S
13. Figure 22 4 44 Pin Connector Pin Assignment for TB84H5 ELECTRONICS 28 S3C84H5X F84H5X ERRATA REV 1 10 29 J102 Not used 1 Not used Not used 2 Not used Not used 3 Not used Not used 4 Not used Not used 5 Not used Not used 6 A Not used INTO TAOUT P1 0 7 P3 3 INT1 BUZ TACK P1 4 8 U P3 2 INT2 TACAP P1 2 2 P3 1 INT3 T1OUT1 P1 3 0 VDD U AD3 P0 3 VSS o AD2 P0 2 Xout S AD1 PO 1 Xin Fs ADO PO 0 TEST m AVss XTin AVref XTout P2 7 TxD nRESET P2 6 RxD TBPWM T1CKO P2 0 P2 5 SCK PWM T1CAPO P2 1 P2 4 SO T1OUTO ADA P2 2 P2 3 AD7 SI Figure 22 5 42 Pin Connector Pin Assignment for TB84H5 Target Board Target System J101 201090000 Ulg pt 201090000 Ulg pt Figure 22 6 TB84H5 Adapter Cable for 44pin Connector Package USER S MANUAL ERRATA ELECTRONICS USER S MANUAL ERRATA S3C84H5X F84H5X_ERRATA_REV 1 10 Third Parties for Development Tools SAMSUNG provides a complete line of development tools for SAMSUNG s microcontroller With long experience in developing MCU systems our third parties are leading companies in the tool s technology SAMSUNG In circuit emulator solution covers a wide range of capabilities and prices from a low cost ICE to a complete system with an OTP MTP programmer In Circuit Emulator for SAM8 family e OPENice i500 e SmartKit SK 1200 OTP MTP Programmer e SPW uni AS pro e US pro e GW PRO2 8 gang programmer Development
14. sese nennen 11 5 11 4 Timer B Control Register 11 6 Timer B Data Registers TBDATAH 11 6 Timer B Output Flip Flop Waveforms in Repeat 11 8 xii S3C84H5X F84H5X UM REV 1 10 MICROCONTROLLER List of Figures Concluded Figure Title Page Number Number 12 1 Timer 1 0 1 Control Register T1 CONO 12 4 12 2 Timer A Timer 1 0 1 Pending Register 12 5 12 3 Timer 1 0 1 Functional Block nne 12 6 13 1 10 Bit PWM Basic Waveform 13 3 13 2 10 Bit Extended PWM nnne 13 4 13 3 PWM Control Register PWMCON ennemis 13 5 13 4 PWM Functional Block 1 13 6 14 1 Serial I O Interface Control Register 14 2 14 2 SIO Pre scaler Register SIOPS 14 3 14 3 SIO Functional Block Diagram 14 3 14 4 Serial Timing Transmit Receive Mode Tx at falling SIOCON 4 0 14 4 14 5 Serial I O Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 14 4 14 6 Serial I
15. P1INTPND Port 1 Interrupt Pending Register EAH RESET Value 0 0 0 0 Read Write R W R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for S8C84H5X F84H5X 3 P1 3 INT3 Interrupt Pending Bit EN Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending 2 P1 2 INT2 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending 1 P1 1 INT1 Interrupt Pending Bit EX Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending 0 P1 0 INTO Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending ELECTRONICS 4 1 N CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 Port 1 Interrupt Enable EBH Set1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 3 s Interrupt Enable Disble Selection Bit Interrupt Disable EN Interrupt Enable Falling edge Interrupt Enable Rising edge 5 4 P1 2 s Interrupt Enable Disble Selection Bit ojx Interrupt Disable 1 0 Interrupt Enable Falling edge EVES Interrupt Enable Rising edge 3 3 P1 1 s Interrupt Enable Disble Selection Bit Interrupt Disable Interrupt Enable Falling edge Interrupt Enable Rising edge 1 0 P1 0 s Interrupt Ena
16. sse 21 4 21 5 28 SOP 375 Package Dimensions sss 21 5 22 1 Development System Configuration ssssssssseeeene enne 22 2 22 2 SSF84H5X Target Board Configuration sese 22 3 22 3 DIP Switehifor Smar OPOR s iecore c ect 22 5 22 4 44 Pin Connector Pin Assignment for 22 6 22 5 42 Pin Connector Pin Assignment for 22 7 22 6 TB84H5 Adapter Cable for 44pin Connector 22 7 xiv S3C84H5X F84H5X UM REV 1 10 MICROCONTROLLER List of Tables Table Title Page Number Number 1 1 S3C84H5X F84H5X Pin Descriptions 3250 325 2850 1 8 1 2 S3C84H5X F84H5X Pin Descriptions 30 5 1 10 2 1 S3C84H5X F84H5X Register Type 2 4 4 1 Set 1 Reglslers on edu e t ep 4 1 4 2 Set 1 Bank 0 enne nnns nennen nnns 4 2 4 3 Set 1 Bank 1 4 3 5 1 Interrupt Vectors 3 era e diee ba Ht eesti dt Y ec eee 5 6 5 2 Interrupt Control Register 1 enne 5 7 5 3 Interrupt Source Control and Data 5 9 6 1 Instruction Group Summary ieta ae aa aa eene at Aa aa snnt enean 6 2 6 2 Flag Notation
17. 32x oa 20 Figure 21 2 32 ELP 0505 Package Dimensions 21 2 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 32 SDIP 400 9 10 0 20 27 88 MAX 27 48 10 20 2 CJ LI LI LI LI LI LI LI LI LI LI LI LI LI LI n n n n AH 1 0 45 0 10 1 37 L 1 00 0 10 gt H NOTE Dimensions are in millimeters Figure 21 3 32 SDIP 400 Package Dimensions ELECTRONICS N 9 e 0 51 MIN 5 08 MAX 3 30 0 30 MECHANICAL DATA 21 3 MECHANICAL DATA S3C84H5X F84H5X_UM_REV 1 10 30 SDIP 400 8 94 0 2 27 88 27 48 0 2 3 81 0 2 5 08 0 56 0 1 lt 1 30 1 12 0 1 1 778 4 gt 4 gt gt e 0 51 MIN 3 30 0 3 NOTE Dimensions are in millimeters Figure 21 4 30 Pin SDIP Package Dimensions 21 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 10 45 0 3 7 70 t0 2 0 10 0 15 0 05 18 02 17 62 t0 2 0 41t01 Je NOTE Dimensions are in millimeters Figure 21 5 28 SOP 375 Package Dimensions ELECTRONICS MECHANICAL DATA 21 5 S3C84H5X F84H5X UM REV 1 10 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system on a turnkey basis The development support system is composed of a host system debugging tools and supporting software For a host system any standard compu
18. da pea ee ve 6 35 DECW Decrement forro EE 6 36 DI Disable Interrupts ss tea re dereud e ee diu v pe 6 37 DIV Divide Unsigned 6 38 DJNZ Decrement and Jump if 6 39 Enable Interr pts iii cri eame eti 6 40 ENTER ETE axe et e e t a evn 6 41 EXIT cum 6 42 IDLE 116 uite ee Hatte dida He eal Pede te t Lg eO ie 6 43 INC et 6 44 INCW Incremernt WOFd x deve rie pe n dcc dae cet 6 45 IRET Interrupt Return icc erre ERE He GER te ei rein ideis 6 46 JP ay ed yu pd 6 47 JUMp Relative rM 6 48 LD 6 49 LD Eoad EE 6 50 LDB Eoad Bit n ndr eit ted a a 6 51 S3C84H5X F84H5X_UM_REV 1 10 MICROCONTROLLER List of Instruction Descriptions Continued Instruction Full Register Name Page Mnemonic Number LDC LDE Load Memory 6 52 LDC LDE LEoad Memoty eere E tette ET 6 53 LDCD LDED Load Memory and Decrement sss enne 6 54 LDCI LDEI Load Memory and 6 55 LDCPD LDEPD Load Memory with 6
19. 0 0 0 0 0 0 0 0 R W R W R W R R W R W R W Register addressing mode only Not used for the S3C84H5X F84H5X must keep always 0 A D Input Pin Selection Bits End of Conversion Bit Read only E A D conversion opration is in progress A D conversion opration is complete Clock Source Selection Bits S rots me Start or Enable Bit EN Disable operation Start operation CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 BTCON Basic Timer Control Register D3H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Watchdog Timer Function Disable Code for System Reset Disable watchdog timer function Other Vaules Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Bits 0 0 fxx 4096 3 of mice 2 22 02 Basic Timer Counter Clear Bit 1 EN No effect Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer 2 EN No effect Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following the write operation the BTCON 1 value is automatically cleared to 0 2 When you write 1 to 0 the corresponding frequency divider is cleared to Immediately following the write operation the 0
20. senem 4 37 WTCON Watch Timer Control Register essen nennen nnns nnns 4 38 S3C84H5X F84H5X UM REV 1 10 MICROCONTROLLER xix List of Instruction Descriptions Instruction Full Register Name Page Mnemonic Number ADC Add wih Cary rc 6 14 ADD eor MET 6 15 AND Logical AND x tie ees ER Econ ERE Aa ee ead 6 16 BAND tete 6 17 ER 6 18 BITC Bit Gomplement ba te 6 19 BITR Bit Reset Her 6 20 BITR BICROSOL 6 20 BITS Bit SOL AT i 6 21 BOR BIt Oia Given fons Lom 6 22 BTJRF Bit Test Jump Relative on 6 23 BTJRT Bit Test Jump Relative on 6 24 BXOR XOR ee ati A aa RR 6 25 CALL Gall Procedute sitire e TRE eoe Ha eiie bier 6 26 CCF Complement Carry 6 27 CLR GI fep 6 28 COM rene E 6 29 CP Compare m 6 30 Compare Increment and Jump on Equal 6 31 CPIJNE Compare Increment and Jump on 6 32 DA Decimal AGUS s 6 33 DA Decimal AdJUSL E Et Pe eei 6 34 DEC Decrement 2 oec ee He
21. of the S3C84H5X F84H5X s 256 byte register pages is called prime register area Prime registers can be accessed using any of the seven addressing modes see Chapter 3 Addressing Modes The prime register area on page 0 is immediately addressable following a reset In order to address prime registers on pages you must set the register page pointer PP to the appropriate source and destination values Bank 1 CPU and system control General purpose 1 Figure 2 5 Set 1 Set 2 Prime Area Register ELECTRONICS 2 9 ADDRESS SPACES S3C84H5X F84H5X_UM_REV 1 10 WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as one that consists of 32 8 byte register groups or slices Each slice comprises of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any one time to form a 16 byte working register block Using the register pointers you can move this 16 byte register block anywhere in the addressable register file except for the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces e working register slice is 8 bytes eight 8 bit w
22. Chapter 13 10 bit PWM Pulse width Modulation 05282522 22 00038101 2 13 1 Function Descriptor eed ame 13 1 Un 13 1 PWM Control Register 13 5 Chapter 14 Serial I O Interface E 14 1 Programming Procedure siete met et cim e 14 1 Serial I O Control Registers SIOCON 14 2 SIO Prescaler Register SIOPS 14 3 viii S3C84H5X F84H5X UM REV 1 10 MICROCONTROLLER Table of Contents Continued Chapter 15 UART Overview mn 15 1 Programming Procedure 15 1 UART Control Register 15 2 UART Interrupt Pending Register nennen tentent 15 4 UART Data Register nennen nennen nennen nns 15 5 UART Baud Rate Data Register BRDATAH BRDATAL sess 15 6 Baud Rate ade aena earrainean aiaa rss 15 6 s lere 15 8 UART Mode 0 Function 15 9 UART Mode 1 Function Description 15 10
23. NOTE LDEPD instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET LDCPI LDEPI Memory with Pre Increment LDCPI LDEPI Operation Flags Format Examples NOTE dst src dst src rr 1 dst lt src These instructions are used for block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 2 14 F3 Irr r Given RO 7FH R6 21H and R7 LDCPI RR6 RO RR6 lt bRR6 1 the contents of RO is loaded into program memory location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH LDEPI RR6 RO RR6 lt bRR6 1 the contents of RO is loaded into external data memory location 2200H 21FFH 1H RO 7FH R6 22H R7 00H LDEPI instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS 6 57 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 L DW Load
24. SDIP ELECTRONICS 4 S3C84H5X F84H5X ERRATA REV 1 10 6 PIN ASSIGNMENT PAGE 1 7 Vss Xour XIN TEST XTout nRESET 5 2 4 SCK P2 5 RxD P2 6 TxD P2 7 28 SOP ADO P0 0 AD1 PO 1 AD2 P0 2 O O S3C84H5X S3F84H5X Top View 1 2 3 4 5 6 7 8 9 USER S MANUAL ERRATA VDD P1 3 TTOUT1 INTS SCLK P1 2 TACAP INT2 SDAT P1 1 TACK BUZ INT1 P1 0 TAOUT INTO AVss P1 5 AD6 T1CAP1 P1 4 AD5 T1CK1 P2 3 AD7 SI P2 2 ADA T1OUTO P2 1 T1CAPO PWM P2 0 T1CKO TBPWM Figure 1 5 S3C84H5X F84H5X Pin Assignment 28 pin SOP ELECTRONICS USER S MANUAL ERRATA S3C84H5X F84H5X_ERRATA_REV 1 10 7 SYSTEM AND USER STACK PAGE 2 20 Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least significant byte 5 7 5 is stored in the SPL register D9H After a reset the SP value is undetermined Because only internal memory space is implemented in the S3C84H5X F84H5X the SPL must be initialized to an 8 bit value in the range 00H FFH The SPH register must be initialized to OFFH at the initial part of the program 8 SYSTEM AND USER STACK PAGE 2 21 PROGRAMMING TIP Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the i
25. SWAP 02H gt Register 02H 03H register 03H 4AH In the first example if the general register OOH contains the value 3EH 00111110B the statement SWAP swaps the lower and the upper four bits nibbles in the OOH register leaving the value 11100011 ELECTRONICS 6 83 INSTRUCTION SET TCM Test Complement under Mask TCM Operation Flags Format Examples 6 84 dst src NOT dst AND src S3C84H5X F84H5X_UM_REV 1 10 This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and the source operands are unaffected C Unaffected TUSON Always cleared to 0 Unaffected Unaffected opc dst src opc src dst dst src Given TCM TCM TCM TCM TCM Set if the result is 0 cleared otherwise Set if the result bit 7 is set cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst src 2 4 62 r r 6 63 r Ir 3 6 64 R R 6 65 R IR 3 6 66 R IM RO OC7H R1 02H R2 12H register 00H 2BH register 01H 02H register 02H 23H RO R1 RO R1 00H 01H 00H 01H 00H 3
26. Timer B Data High Byte Register TBDATAH D1H Set 1 Bank 0 R W Reset Value FFh Timer B Data Low Byte Register TBDATAL D2H Set 1 Bank 0 R W Reset Value FFh Figure 11 5 Timer B Data Registers TBDATAH TBDATAL 11 6 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 8 BIT TIMER A B TIMER B PULSE WIDTH CALCULATIONS tLOW 1 To generate the above repeated waveform consisted of low period time t and high period time When T FF 0 tLow TBDATAL 1 x 1 fx lt TBDATAL lt 100H where fx The selected clock TBDATAH 1 x 1 fx lt TBDATAH lt 100H where fx The selected clock When T FF 1 ti ow TBDATAH 1 x 1 fx OH lt TBDATAH lt 100H where fx The selected clock TBDATAL 1 x 1 fx lt TBDATAL lt 100H where fx The selected clock To make tj ow 24 us and tyigy 15 us foge 4 MHz fx 4 MHz 4 1 MHz When T FF 0 ti ow 24 us TBDATAL 1 TBDATAL 1 x tus TBDATAL 23 15 us TBDATAH 1 TBDATAH 1 x 1 5 TBDATAH 14 When T FF 1 15 us TBDATAL 1 fx TBDATAL 1 x tus TBDATAL 14 24 us TBDATAH 1 fx TBDATAH 1 x tus TBDATAH 23 ELECTRONICS 8 S3C84H5X F84H5X_UM_REV 1 10 Timer B Clock T FF 0 TBDATAL 01 FFH TBDATAH 00H T FF 0 TBDATAL TBDATAH 01 T FF 0 TBDAT
27. nRESET TEST Xin Xout External clock input pins for timer 1 0 Capture input pins for timer 1 0 Timer 1 0 16 bit PWM mode output or counter match toggle output pins External clock input pins for timer 1 1 Capture input pins for timer 1 1 Timer 1 1 16 bit PWM mode output or counter match toggle output pins System reset pin Pull down resistor connected internally Power input pins Main oscillator pins NOTE Pin numbers shown in parentheses are for the 28 pin SOP package ELECTRONICS 1 9 PRODUCT OVERVIEW S3C84H5X F84H5X_UM_REV 1 10 Table 1 2 S3C84H5X F84H5X Pin Descriptions 30 SDIP Pin Pin Pin Circuit Pin Share Name Type Description Type Number Pins Bit programmable port input or output mode ADCO ADC1 selected by software input or push pull output ADC2 ADC3 Software assignable pull up resistor Alternately can be used as ADO ADS P1 0 P1 5 Bit programmable port input or output mode INTO INT3 selected by software input or push pull output TAOUT TACK Software assignable pull up resistor Alternatively 1 1 used INTO INT3 TACK T1CAP1 AD5 TACAP T1CAP1 T1CK1 T10UT1 AD5 AD6 T1OUT1 AD6 BUZ 2 0 2 7 lO Bit programmable port input or output mode ADC6 ADC7 selected by software input or push pull output SO SCK RxD Software assignable pull up TxD Alternately can be used as ADC4 ADC7 SI T1CAP1 T1CAPO
28. 01H register 01H 1BH SPH OD8H OOH SPL OD9H OFBH and stack register OFBH 55H POP 00H gt Register 00H gt Register OOH 55H SP 00FCH 01H register 01H 55H SP 00FCH In the first example the general register contains the value 01H The statement POP loads the contents of the location OOFBH 55H into the destination register and then increments the stack pointer by one The register OOH then contains the value 55H and the SP points to the location OOFCH ELECTRONICS 6 63 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example dst src dst lt src IR lt IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 92 R IR Given Register 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02 000 gt Register 00H 41H register 02H 6FH register 42H 6FH 2 If the general register contains the value 42H and the register 42H the value 6FH the statement POPUD 02H 900H loads the contents of the register 42H into the destination register
29. Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode AD7 7 6 P2 2 ADA T1OUTO Configuration Bits 0 0 Input mode 0 4 Alternative function mode T1OUTO 1 0 Push pull output mode 1 1 Alternative function mode AD4 7 6 P2 1 PWM T1CAPO Configuration Bits 0 0 Input mode T1CAPO 0 1 Alternative function mode 1 1 0 Push pull output mode 1 1 Alternative function mode PWM 7 6 P2 0 TBPWM T1CKO Configuration Bits 0 0 Input mode T1CKO 0 1 Alternative function mode T1CKO 1 0 Push pull output mode 1 1 Alternative function mode TBPWM Figure 9 7 Port 2 Low Byte Control Register P2CONL 9 10 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 PORTS Port 2 Pull up Control Register P2PUR FAH Set1 R W Reset value 00 7 P2 7 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 6 P2 6 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 5 P2 5 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 4 P2 4 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 3 P2 3 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 2 P2 2 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 1 P2 1
30. Clear the PWM counter when write 2 5 Counter Enable Bit Stop counter 1 Start Resume countering 1 PWM Overflow Interrupt Enable Bit 8 Bit Overflow Disable interrupt 1 Enable interrupt 0 PWM Overflow Interrupt Pending Bit No interrupt pending when read Clear pending bit when write Interrupt is pending when read NOTE PWMCON 3 is not auto cleared You must pay attention when clear pending bit refer to page 13 7 4 24 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 CONTROL REGISTER RPO Register Pointer 0 D6H Set1 RESET Value 1 1 0 0 0 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RPO points to address COH in register set 1 selecting the 8 byte working register slice COH C7H 2 0 Not used for the S3C84H5X F84H5X RP1 Register Pointer 1 D7H Set 1 RESET Value 1 1 0 0 1 Read Write R W R W R W R W R W E Addressing Mode Register addressing only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select tw
31. Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 10 OF Example The following diagram shows an example of how to use the NEXT instruction Before After Address Data Address Data 1P 1P Address Data 43 Address H 0120 44 Address L 45 Address Address H Address L Address H 120 130 Routine Memory 6 60 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET NOP Operation NOP Operation No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to affect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 FF Example When the instruction NOP is executed in a program no operation occurs Instead there happens a delay in instruction execution time which is of approximately one machine cycle per each NOP instruction encountered ELECTRONICS 6 61 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 OR Logical OR OR Operation Flags Format Examples dst src dst lt dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a O is stored C Unaffected
32. Interrupt mask register IMR R W _ Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels 0 7 Interrupt priority register R W Controls the relative processing priorities of the interrupt levels The seven levels of S3C84H5 F84Hb5are organized into three groups A B and C Group A is IRQO and IRQ1 group B is IRQ2 IRQ3 and IRQ4 and group C is IRQ5 IRQ6 and IRQ7 Interrupt request register This register contains a request pending bit for each interrupt level System mode register SYM R W _ This register enables disables fast interrupt processing dynamic global interrupt processing NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended ELECTRONICS 5 7 INTERRUPT STRUCTURE S3C84H5X F84H5X_UM_REV 1 10 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system level control points in the interrupt structure are e Global interrupt enable and disable by El and DI instructions or by direct manipulation of SYM 0 e Interrupt level enable disable settings IMR register e Interrupt level priority settings IPR register e Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be s
33. P1 3 T10UT1 INT3 SCLK P1 2 TACAP INT2 SDAT P1 1 TACK BUZ INT1 P1 0 TAOUT INTO AVss AVREF P1 5 AD6 T1CAP1 P1 4 AD5 T1CK1 P2 3 AD7 SI P2 2 ADA T1OUTO P2 1 T1CAPO PWM P2 0 T1CKO TBPWM P0 2 AD2 Figure 1 4 S3C84H5X F84H5X Pin Assignment 30 SDIP 1 6 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 PIN ASSIGNMENT Vss XIN TEST XTIN XTour nRESET SO P2 4 SCK P2 5 RxD P2 6 TxD P2 7 0 0 AD1 PO 1 AD2 P0 2 1 2 3 4 5 6 7 8 9 O S3C84H 5X S3F84H 5X Top View 28 SOP PRODUCT OVERVIEW VDD P1 3 T10UT1 INT3 SCLK P1 2 TACAP INT2 SDAT P1 1 TACK BUZ INT1 P1 0 TAOUT INTO AVss AV REF P1 5 AD6 T1CAP1 P1 4 AD5 T1CK1 P2 3 AD7 SI P2 2 ADA T1OUTO P2 1 T1CAPO PWM P2 0 T1CKO TBPWM Figure 1 5 S3C84H5X F84H5X Pin Assignment 28 pin SOP ELECTRONICS 1 7 PRODUCT OVERVIEW S3C84H5X F84H5X_UM_REV 1 10 PIN DESCRIPTIONS Table 1 1 S3C84H5X F84H5X Pin Descriptions 32SOP 32SDIP 28SOP Circuit 0 Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up resistor Alternately can be used as ADO AD3 P1 0 P1 5 Bit programmable port input or output mode INTO INT3 selected by software input or push pull output TAOUT TACK Software assignable pull up resistor TACAP Alternatively can be used as 0 T1CK1 TAOUT
34. The DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H RO C lt 0 lt 0 Bits 4 7 3 bits 0 3 1 R1 1 lt 31 0 leave the value 31 BCD the address 27H R1 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 DEC Decrement DEC Operation Flags Format Examples dst dst lt dst 1 The contents of the destination operand are decremented by one Unaffected Set if the result is 0 cleared otherwise Set if result is negative cleared otherwise Set if arithmetic overflow occurred cleared otherwise Unaffected Unaffected TOS YN Bytes Cycles opc dst 2 4 4 Given R1 03H and register 10H DEC R1 gt R1 02H DEC R1 gt Register 03H OFH INSTRUCTION SET Opcode Addr Mode Hex dst 00 R 01 IR In the first example if the working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC 1 decrements the value 10H contained in the destination register by one leaving the value OFH ELECTRONICS 6 35 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 DECW Decrement Word DECW Operation Flags Format Examples NOTE dst dst dst 1 The contents of the
35. Z Setif the result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Always cleared to O D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 42 r r 6 43 r Ir opc src dst 3 6 44 R R 45 R IR opc dst src 3 6 46 R IM Given RO 15H R1 2AH R2 01H register 08H register 01H 37H and register 08H 8AH OR RO R1 gt 1 2 RO R2 gt RO 37H R2 01H register 01H 37H OR 00H 01H gt Register OOH registerO1H 37H OR 01H OOH gt Register OOH 08H register 01H OR 00H 02H gt Register OOH OAH In the first example if the working register RO contains the value 15H and the register R1 the value 2AH the statement OR RO R1 logical ORs the RO and R1 register contents and stores the result in the destination register RO Other examples show the use of the logical OR instruction with various addressing modes and formats ELECTRONICS S3C84H5X F84H5X UM REV 1 10 INSTRUCTION SET POP Pop from Stack POP Operation Flags Format Examples dst dst SP lt SP 1 The contents of the location addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one No flags are affected Bytes Cycles Opcode Addr Mode Hex dst 451 2 8 50 R 8 51 IR Given Register OOH
36. 00000000b LD BTCON 1010001 1b Disable Watch dog LD P2CONL 03H Enable TBPWM output LD TBDATAH 80h LD TBDATAL 80h LD TBCON 11101110b Enable interrupt fxx 256 Repeat Duration 6 605ms 10 MHz x tal EI ELECTRONICS 14 S3C84H5X F84H5X ERRATA REV 1 10 USER S MANUAL ERRATA 20 PROGRAMMING TIP OF TIMER 1 PAGE 12 7 ORG 0000h VECTOR J OCA4h TIM1 INT ORG 0100h INITIAL LD SYM 00h Disable Global Fast interrupt LD IMR 00001000b Enable 2 interrupt LD SPH 11111111b Set stack area LD SPL 00000000b LD BTCON 1010001 1b Disable Watch dog SB1 LD T1CONO 01000110b Enable interrupt fxx 64 Interval Interval 1 536 ms 10 MHz x tal LDW T1DATAHO 00FO0h 00 T1 DATALO FOh SBO EI 15 ELECTRONICS USER S MANUAL ERRATA S3C84H5X F84H5X_ERRATA_REV 1 10 21 PROGRAMMING TIP OF PWM PAGE 14 5 ORG 0000H VECTOR INT_SIO ORG 0100H INITIAL LD BTCON 10100010B Watch dog disable LD 00011000B non divided CPU clock LD SPH 0FFH It must be initialized to OFFH LD SPL 00 LD 2 10101111B SIO setting LD P2CONL 00101010B LD SIOCON 00100110B Enable SlO Interrupt LD SIOPS 20 setting baud rate EI ELECTRONICS 16 S3C84H5X F84H5X ERRATA REV 1 10 USER S MANUAL ERRATA 22 UART BAUD RATE DATA REGISTER PAGE 15 7 Table 15 1 Commonly Used Baud Rates Generated by 16 bit BRDATA BRD
37. 51 2 5 SCK 1 3 PRODUCT OVERVIEW PIN ASSIGNMENT Vss Xour XIN TEST XTIN XTour nRESET 0 SO P2 4 SCK P2 5 RxD P2 6 TxD P2 7 ADO P0 0 AD1 P0 1 AD2 P0 2 1 2 3 4 5 6 7 8 9 O S3C84H5X S3F84H5X Top View 32 SOP 32 SDIP O S3C84H5X F84H5X_UM_REV 1 10 VDD P1 3 T1OUT1 INT3 SCLK P1 2 TACAP INT2 SDAT P1 1 TACK BUZ INT1 P1 0 TAOUT INTO P3 3 P3 2 AVss AV REF P1 5 AD6 T1CAP1 P1 4 AD5 T1CK1 P2 3 AD7 SI P2 2 ADA T1OUTO P2 1 T1CAPO PWM P2 0 T1CKO TBPWM Figure 1 2 S3C84H5X F84H5X Pin Assignment 32 SOP SDIP 1 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 PRODUCT OVERVIEW P2 5 SCK 32 P2 6 RxD 30 P24 SO 27 nRESET 26 XTOUT TxD P2 7 ADO PO 0 AD1 P0 1 AD2 P0 2 AD3 P0 3 1 2 0 PWM T1CAPO P2 1 AD4 T1OUTO P2 2 TEST XIN XOUT S3F84H5X Vss 32ELP 0505 Vdd P1 3 T10UT1 INT3 SCLK P1 2 TACAP INT2 SDAT P1 1 TACK BUZ INT1 WN AD7 SI P2 3 9 ADS T1CK1 P1 4 1 1 1 5 C INTO TAOUT P1 0 7 Figure 1 3 S3C84H5X F84H5X Pin Assignment 32 ELP ELECTRONICS 1 5 PRODUCT OVERVIEW PIN ASSIGNMENT Vss Xour XIN TEST XTIN XTout nRESET P3 0 P3 1 SO P2 4 SCK P2 5 RxD P2 6 TxD P2 7 ADO P0 0 AD1 P0 1 S3C84H5X S3F84H5X Top View 30 SDIP O S3C84H5X F84H5X_UM_REV 1 10 VDD
38. Figure 2 15 8 Bit Working Register Addressing Example ELECTRONICS 2 19 ADDRESS SPACES S3C84H5X F84H5X_UM_REV 1 10 SYSTEM AND USER STACK The S3C8 series microcontrollers use the system stack for data storage subroutine calls and returns The PUSH and POP instructions are used to control system stack operations The S3C84H5X F84H5X architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAGS register are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 15 High Address Top of gt stack Stack contents Stack contents after a call after an instruction interrupt Low Address Figure 2 16 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack po
39. Hex dst src dst opc src 2 4 r IM 4 r8 r R src opc dst 2 4 9 R r dst src 2 4 C7 r Ir 4 D7 Ir r opc src dst 3 6 E4 R R E5 R IR opc dst src 3 6 E6 R IM D6 IR IM opc src dst 3 6 F5 IR R opc dst src 3 6 87 r x r src dst x 3 6 97 x r r ELECTRONICS 6 49 INSTRUCTION SET LD Load LD Examples Continued S3C84H5X F84H5X UM REV 1 10 Given RO 01H R1 OAH register 01H register 01H 20H register 02H 02H LOOP and register OFFH LD R0 410H LD RO 01H LD 01H RO LD R1 RO LD RO R1 LD 00H 01H LD 02H 00H LD 00H O0AH LD 00H 10H LD 00H 02H LD RO LOOP R1 LD 4LOOP RO R1 14 RO 10H RO 20H register 01H 20H Register 01H 01H RO 01H R1 20H RO 01H RO 01H R1 OAH register 01H OAH Register 00H 20H register 01H 20H Register 02H 20H register 00H 01H Register OOH OAH Register 01H register 01H 10H Register 01H register 01H 02 register 02H 02H RO OFFH R1 0AH Register 31H OAH RO 01H R1 OAH ELECTRONICS S3C84H5X F84H5X UM REV 1 10 INSTRUCTION SET LDB Load Bit LDB LDB Operation Flags Format Examples dst src b dst b src 4610 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specifi
40. STOP Control Register STOPCON E5H Set 1 Bank 0 R W STOP Control bits Other values Disable STOP instruction 10100101 Enable STOP instruction Figure 7 6 STOP Control Register STOPCON 7 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 RESET and POWER DOWN RESET AND POWER DOWN SYSTEM RESET OVERVIEW During a power on reset the voltage at Vpp goes to High level and the RESET pin is forced to Low level The RESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This procedure brings S3C84H5X F84H5X into a known operating status To allow time for internal CPU clock oscillation to stabilize the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance The minimum required oscillation stabilization time for a reset operation is 1 millisecond Whenever a reset occurs during normal operation that is when both Vpp and RESET are High level the RESET pin is forced Low and the reset operation starts All system and peripheral control registers are then reset to their default hardware values In summary the following sequence of events occurs during a reset operation e Interrupt is disabled e The watchdog function basic timer is enabled e Ports 0 3 are set to input mode e Peripheral control and data registers are disabled and reset to their default hardware values e The program counter PC is loaded with the p
41. and sources The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are eight possible interrupt levels IRQ0 IRQ7 also called level 0 level 7 Each interrupt level directly corresponds to an interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3C84H5X F84H5X interrupt structure recognizes eight interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given
42. gt R1 05H If the value of the working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET BITS Bit set BITS Operation Flags Format Example dst b dst b 1 The BITS instruction sets the specified bit within the destination without affecting any other bit in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst b 1 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITS R1 3 gt R1 OFH If the working register R1 contains the value 07H 00000111 the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001111 ELECTRONICS 6 21 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 BOR Bit or BOR BOR Operation Flags Format Examples dst src b dst b src dst 0 lt 4510 OR src b or dst b lt dst b OR src 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffec
43. the Timer A interrupt request is generated the counter value is reset and counting resumes Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TAOUT pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the Timer A data register TADATA In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at and then continues incrementing from OOH Although you can use the match signal to generate a timer A overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TAOUT pin is held to Low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to 256 Capture Mode In capture mode a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the Timer A data register You can select rising or falling edges to trigger this operation Timer A also gives you capture input source the signal edge at the TACAP pin You select the capture input by setting the value of the Timer A capture input selection bit in the port 1 control register P1 CONL set 1 bank 0 E9H When P1CONL 5
44. 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer Input Clock Selection Bits 20 2 0 5 4 Timer A Operating Mode Selection Bits 0 0 Interval mode TAOUT mode Capture mode capture on rising edge counter running OVF can occur Capture mode capture on falling edge counter running OVF can occur PWM mode OVF interrupt can occur 3 Timer Counter Clear Bit 3 No effect 1 Clear the timer A counter Auto clear bit 2 Ti 3 er A Overflow Interrupt Enable Bit Disable overflow interrupt 1 Enable overflow interrupt Ti 3 er A Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer Start Stop Bit Stop Timer A 1 Start Timer 4 32 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 CONTROL REGISTER TBCON Timer B Control Register DOH Set 1 RESET VALUE 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer Input Clock Selection Bits opa 5 4 Timer Interrupt Time Selection Bits Elapsed time for low data value fo Elapsed time for high data value 1 EN Elapsed time for low and high data values 1 Not Used 3 Ti 3 er B Interrupt Enable Bit Disable Interrupt 1 Enable Interrupt 2 Ti 3 er B Start Stop Bit Stop timer B Start
45. 000001 10B in the register R1 ELECTRONICS 6 17 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 BCP Bit Operation Flags Format Example dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison Unaffected Set if the two bits are the same cleared otherwise Cleared to Undefined Unaffected Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst b 0 src 3 6 17 Rb NOTE In the second byte of the instruction format the destination address is four bits the bit address 0 is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 01H BCP R1 01H 1 gt R1 register 01H 01H If the destination working register R1 contains the value 07H 00000111B and the source register 01H contains the value 01H 00000001B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register 0D5H ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET BITC Complement BITC Operation Flags Format Example dst b
46. 1 External clock SCK 0 Clear pending condition when write 1 Interruptis pending Data direction control bit 0 MSB first mode SlOinterrupt enable bit 1 LSB first mode 0 Disable SIO interrupt 1 Enable 510 interrupt SIO mode selection bit 0 Rececive only mode 1 Transmit receive mode SIO shift operation enable bit 0 Disable shifter and clock counter Shift clock edge selction bit 1 Enable shfter and clock counter 0 Tx falling edges Rx at rising edges 1 Tx rising edges Rx at falling edges 10 counter clear and shift start bit 0 No action 1 Clear 3 bit counter and start shifting Figure 14 1 Serial I O Interface Control Register 5 14 2 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 SERIAL INTERFACE SIO PRESCALER REGISTER SIOPS The control register for serial I O interface module SIOPS is located in Set 1 Bank 1 at FOH The value stored in the SIO prescaler registers SIOPS lets you determine the SIO clock rate baud rate as follows Baud rate Input clock Xin 4 SIOP 1 or external input clock SIO Pre Scaler Registers SIOPS FOH Seti Bank1 R W 3 Bit Counter 51 0 Clear Pending SIOCON 1 SIOCON 7 sven Interrupt Enable Shift Clock Source Select SIOCON 4 SIOCON 2 Edge Select Shift Enable SIOCON 5 1 Mode Select CLK g Bit SIO Shift Buffer XN2 gt 0581 SIODATA Prescaler X SIOCON 6 Prescale
47. 1 10 PROGRAMMING To generate a one pulse signal through P2 0 This example sets Timer B to the one shot mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 40us width pulse The program parameters are e Timer B is used in one shot mode 4 e Oscillation frequency is 4 MHz fx 1 4 clock 1 us TBDATAH 40 us 1 us 40 TBDATAL 1 e Set P2 0 to TBPWM mode ORG START LD LD LD PULSE_OUT LD 11 10 0100H TBDATAH 40 1 TBDATAL 1 TBCON 00010001B P2CONL 03H TBCON 00000101B Reset address Set 40 us Set any value except 00H Clock Source lt fxx 4 Disable Timer B interrupt Select one shot mode for Timer B Stop Timer B operation Set Timer B output flip flop T FF high Set P2 0 to TBPWM mode Start Timer B operation to make the pulse at this point After the instruction is executed 0 75 us is required before the falling edge of the pulse starts ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 PROGRAMMING Using the Timer INITIAL MAIN TAMC_INT TAOV_INT ORG VECTOR VECTOR ORG 0000h OCOh TAMC INT OC2h TAOV INT 0100h 5 111111116 SPL 00000000b BTCON 1010001 1b P1CONL 0ABH TADATA 80h TACON 01001010b MAIN ROUTINE JR T MAIN Interrupt service routine IRET Interrupt service routine IRET ELECTRONICS Set
48. 4 is 00 or 01 the TACAP input or normal input is selected When P1CONL 5 4 is set to 1X normal push pull output is selected Both kinds of timer A interrupts can be used in capture mode the timer A overflow interrupt is generated whenever a counter overflow occurs the timer A match capture interrupt is generated whenever the counter value is loaded into the Timer A data register By reading the captured data value in TADATA and assuming a specific value for the timer A clock frequency you can calculate the pulse width duration of the signal that is being input at the TACAP pin 11 2 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 8 BIT TIMER A B TIMER A CONTROL REGISTER TACON You use the timer A control register TACON to e Select the timer A operating mode interval timer capture mode and PWM mode Select the timer A input clock frequency e Clear the timer A counter TACNT e Enable the timer A overflow interrupt or timer A match capture interrupt e Clear timer A match capture interrupt pending conditions TACON is located in set 1 Bank 1 at address E1H and is read write addressable using Register addressing mode A reset clears TACON to This sets timer A to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer A interrupts You can clear the timer A counter at any time during normal operation by writing a 1 to TACON 3 The timer A overflow interrupt TAOVF
49. 6 3 6 3 6 Opcode Hex 72 73 74 75 76 Addr Mode dst src r r r Ir R R R IR R IM Given RO OC7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM TM TM TM TM RO R1 RO R1 00H 01H 00H 01H 00H 54H gt gt 0 7 1 02H Z 0 RO R1 02H register 02H 23H Z 0 Register 2BH register 01H 02H 2 0 Register 2BH register 01H 02H register 02H 23H Z 0 Register 00H 2BH Z 1 In the first example if the working register RO contains the value 11000111B and the register R1 the value 02H 00000010B the statement TM RO R1 tests bit one in the destination register for 0 value Because the mask value does not match the test bit the 7 flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 85 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 WEI Wate tor Interrupt WFI Operation The CPU is effectively halted before an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including a fast interrupt Flags No flags are affected Format Bytes Cycles Opcode Hex 1 4n 3F n 1 2 3 Example The following sample program structure shows the sequence of operations that follow a WFI st
50. 7 1 CLOCK CIRCUIT S3C84H5X F84H5X_UM_REV 1 10 CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and Idle mode affect the system clock as follows e n Stop mode the main oscillator is halted Stop mode is released and the oscillator is started by a reset operation or an external interrupt with RC delay noise filter and can be released by internal interrupt too when the sub system oscillator is running and watch timer is operating with sub system clock e idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or by an external or internal interrupt Stop Release Y 2 Main Ststem S ub system Oscillator fx Watch Timer Circuit Circuit Selector 1 a B X N a 5 0 i e OSCCON 2 v STOP OSC 1 8 1 4096 Basic Timer inst Timer Counter N Watch Timer 50 256 STPCON 2 2 gt A D Converter OSCCON 3 1 1 1 2 1 8 1 16 System Clock CLKCON 4 3 Selector 2 IDLE Instruction Figure 7 3 System Clock Circuit Diagram 7 2 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 CLOCK CIRCUIT SYSTEM CLOCK CONTROL REGISTE
51. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst src Load LDB dst src Load bit LDE dst src Load external data memory LDC dst src Load program memory LDED dst src Load external data memory and decrement LDCD dst src Load program memory and decrement LDEI dst src Load external data memory and increment LDCI dst src Load program memory and increment LDEPD dst src Load external data memory with pre decrement LDCPD dst src Load program memory with pre decrement LDEPI dst src Load external data memory with pre increment LDCPI dst src Load program memory with pre increment LDW dst src Load word POP dst Pop from stack POPUD dst src Pop user stack decrementing POPUI dst src Pop user stack incrementing PUSH src Push to stack PUSHUD dst src Push user stack decrementing PUSHUI dst src Push user stack incrementing NOTE LDE LDED LDEI LDEPP and instructions can be used to read write the data from the 64 Kbyte data memory 6 2 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Log
52. MSB LVR on off control bit Not used 0 Disable 1 Enable NOTE The value of unused bits of O3CH 03DH 03EH must be logic 1 Figure 2 2 Smart Option ELECTRONICS 2 3 ADDRESS SPACES S3C84H5X F84H5X_UM_REV 1 10 REGISTER ARCHITECTURE In the S3C84H5X F84H5X implementation the upper 64 byte area of register files is expanded two 64 byte areas called set 1 and set 2 The upper 32 byte area of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and the lower 32 byte area is a single 32 byte common area In case of S3C84H5X F84H5X the total number of addressable 8 bit registers is 334 Of these 334 registers 13 bytes are for CPU and system control registers 49 bytes are for peripheral control and data registers 16 bytes are used as a shared working registers and 256 registers are for general purpose use You can always address set 1 register location regardless of which of the 2 register pages is currently selected The set 1 locations however can only be addressed using direct addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SBO and SB1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3C84H5X F84H5X Register Type Summary Registe
53. O Timing Receive Only 14 5 15 1 UART Control Register 15 3 15 2 UART Interrupt Pending Register 15 4 15 3 UART Data Register 15 5 15 4 UART Baud Rate Data Register BRDATAH BRDATAL 15 6 15 5 UART Functional Block 15 8 15 6 Timing Diagram for UART Mode 0 15 9 15 7 Timing Diagram for UART Mode 1 15 10 15 8 Timing Diagram for UART Mode 2 15 12 15 9 Connection Example for Multiprocessor Serial Data Communications 15 14 16 1 A D Converter Control Register 16 2 16 2 A D Converter Data Register ADDATAH ADDATAL 16 3 16 3 A D Converter Circuit 16 3 16 4 A D Converter Timing Diagram enne nnne 16 4 16 5 Recommended A D Converter Circuit for Highest Absolute Accuracy 16 5 17 1 Watch Timer Circuit Diagram eene enne tnn nnne 17 3 18 1 Low Voltage Reset a e P icr 18 2 S3C84H5X F84H5X UM REV 1 10 MICROCONTROLLER xiii List of Figures Conclude
54. Operation A D Input Pin Selection bits A D Input pin Clock Selection bit Conversion Clock End of Conversion bit realy only 0 Conversion not complete 1 Conversion complete Figure 16 1 A D Converter Control Register ADCON 16 2 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 A D CONVERTER Conversion Data Register High Byte ADDATAH F8H Set 1 Bank 0 Read only 5 4 3 2 4 LSB Conversion Data Register Low Byte ADDATAL Set 1 Bank 0 Read only x x x x 1 Figure 16 2 A D Converter Data Register ADDATAH ADDATAL ADCON 4 6 Select one input pin of the assigned ud To ADCON 3 1 1 EOC Flag M Clock Selector ADCON 0 ADC Enable Analog Comparator Successive Approximation Logic Input Pins ADCO ADC7 P0 0 P0 3 L P1 4 P1 5 P2 2 P2 3 ADCON 0 A D Conversion enable 10 bit result is loaded into A D Conversion Data Register hi Conversion Result 10 bit D A ADDATAH Converter ADDATAL To Data bus Figure 16 3 A D Converter Circuit Diagram ELECTRONICS 16 3 A D CONVERTER S3C84H5X F84H5X_UM_REV 1 10 INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain within the range AVss to Vpop Different reference voltage levels are
55. Page Number Number 20 1 Absolute Maximum 20 2 20 2 Input Output Capacitance 1 20 2 20 3 0 Electrical Characteristics iier 20 3 20 4 A C Electrical Characteristics nennen 20 5 20 5 Main Oscillator Frequency been oi d dia 20 6 20 6 Main Oscillator Clock Stabilization Time te4 sse 20 6 20 7 Sub Oscillator Frequency 20 7 20 8 Subsystem Oscillator crystal Stabilization Time 40 7 5 20 7 20 9 Data Retention Supply Voltage in Stop Mode 20 8 20 10 UART Timing Characteristics in Mode 0 10 20 10 20 11 A D Converter Electrical 20 11 20 12 LVR Low Voltage Reset Circuit Characteristics 20 12 22 1 Components of TB84L15 i ete t tl Poe He etd 22 4 22 2 Power Selection Settings for 5 22 4 22 3 Clock Source Selection Setting sese 22 5 22 4 PWM Enable Disable 22 6 xvi S3C84H5X F84H5X UM REV 1 10 MICROCONTROLLER List of Programming Tips Description Chapter 2 Address Spaces Using the Page Pointer for RAM
56. Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 0 P2 0 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable Figure 9 8 Port 2 Pull up Control Register P2PUR ELECTRONICS 9 11 PORTS S3C84H5X F84H5X_UM_REV 1 10 PORT 3 Port is 8 bit I O port that can be used for general purpose digital I O The pins are accessed directly writing or reading the port data register at location E3H in set 1 bank 0 0 3 can serve as inputs outputs push pull Port 3 Control Register P3CONL Port has two 8 bit control registers for P3 4 P3 7 and PSCONL for 0 3 3 A reset clears the P3CONH and P3CONL registers to configuring all pins to input mode You use control registers settings to select input or output mode push pull Open drain and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 3 control registers must also be enabled in the associated peripheral module Port Control Register Low Byte PSCONL Set1 Reset value 00 7 6 P3 3 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 5 4 P3 2 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0
57. REGISTER SIOPS sio Prescaler Register FOH Set1 Bank1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Baud rate Input clock fxx SIOPS 1 x4 input clock SPH stack Pointer High Byte Set 1 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address 5 15 5 8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset NOTE SPH must be initialized to at the start of a program SPL stack Pointer Low Byte D9H Set 1 RESET Value X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The low byte stack pointer value is the lower eight bits of the 16 bit stack pointer address 7 5 The upper byte of the stack pointer value is located in register SPH D8H The SP value is undefined following a reset ELECTRONICS 4 27 CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 STOPCON Stop Control Register E5H RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP
58. Stand alone Samsung OTP MTP FLASH Programmer for After Service 00 e Small size and Light for the portable use e Support all of SAMSUNG OTP MTP FLASH devices Em e HEX file download via USB port from PC e Very fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second e Internal large buffer memory 118M Bytes e Driver software run under various O S Windows 95 98 2000 XP e Full function regarding OTP MTP programmer Read Program Verify Blank Protection e Two kind of Power Supplies User system power or USB power adapter e Support Firmware upgrade ELECTRONICS SEMINIX TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http www seminix com 22 9 DEVELOPMENT TOOLS S3C84H5X F84H5X_UM_REV 1 10 OTP MTP PROGRAMMER WRITE Continued US pro SEMINIX Portable Samsung OTP MTP FLASH Programmer TEL 82 2 539 7891 e Portable Samsung OTP MTP FLASH Programmer FAX 82 2 539 7819 e Small size and Light for the portable use e E mail e Support all of SAMSUNG OTP MTP FLASH sales seminix com devices e URL e Convenient USB connection to any IBM compatible http www seminix com PC or Laptop computers e Operated by USB power of PC e PC based menu drive software for simple operation e Very fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second e Support Samsung standard Hex or Intel Hex format e Driver software run under va
59. T1OUTO P2 1 T1CAPO PWM P2 0 T1CKO TBPWM AD3 P0 3 Figure 19 4 Pin Assignment 28 pin SOP ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 MTP Table 19 1 Descriptions of Pins Used to Read Write the Flash ROM Main Chip During Programming 30 32 pin lO Serial data pin output when reading Input 18 32 ELP when writing Input and push pull output port 28 30 pin 26 28 pin P1 3 SCLK 31 32 pin Serial clock pin input only pin 19 32 ELP 29 30 pin 27 28 pin can be assigned TEST Power supply pin for flash ROM cell writing 24 32 indicates that MTP enters into the writing mode When 12 5 V is applied MTP is in writing mode and when 5 V is applied MTP is in reading mode Option nRESET nRESET 27 ioe ELP VDD VSS Vpp Vss 32 1 32 pin Logic power supply pin 20 21 32 ELP 30 1 30 pin 28 1 28 pin Table 19 2 Comparison of S3F84H5X and S3C84H5X Features Program Memory 16 Kbyte Flash ROM 16K byte mask ROM Operating Voltage Vpp 2 5V to 5 5 V LVR off 2 5V to 5 5 V LVR off LVR to 5 5 V LVR on LVR to 5 5 V LVR on MTP Programming Mode 5 V Vpp 12 5 V _ 5 Pin Configuration 32 SDIP SOP ELP 30 SDIP 28 SOP EPROM Programmability User Program multi time Programmed at the factory ELECTRONICS 19 5 S3C84H5X F84H5X_UM_REV 1 10 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter S3C84H5X F84H5X electrical characteristics are presented in tables and graphs The informatio
60. T1OUTO T1CKO SO SCK RxD TxD T1CKO PWM TBPWM PWM TBPWM P3 0 P3 3 Bit programmable port input or output mode selected by software input or push pull N channel open drain output Software assignable pull up 1 10 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 PRODUCT OVERVIEW Table 1 2 S3C84H5X F84H5X Pin Descriptions Continued Pin Pin Pin Circuit Pin Share Name Type Description Type Number Pins INTO INT3 Input pins for external interrupt D 5 26 29 1 0 1 3 Alternatively used as general purpose digital input output port 1 ADCO ADC7 Analog input pins for A D converter module E 14 17 3 Alternatively used as general purpose digital 20 23 2 2 2 3 input output port 0 and port 2 P1 4 P1 5 AVss A D converter reference voltage and ground 24 25 RxD Serial data RxD pin for receive input and E 2 6 transmit output mode 0 TxD Serial data TxD pin for transmit output and shift clock output mode 0 TACK a External clock input pins for timer A TACAP Capture input pins for timer TAOUT Pulse width modulation output pins for timer A TBOUT Carrier frequency output pins for timer T1CKO a External clock input pins for timer 1 0 T1CAPO Ep Capture input pins for timer 1 0 T1OUTO Timer 1 0 16 bit PWM mode output or D 5 20 P2 2 counter nes toggle output pins T1CK1 External clock input pins for timer 1 1 1 Capture input
61. TACK TACAP T1CAP1 T1CK1 T1CAP1 AD5 T1OUT1 AD5 AD6 T1OUTl1 AD6 BUZ 2 0 2 7 Bit programmable port input or output mode 10 13 18 21 selected by software input or push pull output 16 19 SO SCK RxD Software assignable pull up 8 11 TxD Alternately can be used as ADC4 ADC7 SI T1CAP 1 T1CAPO T1OUTO T1CKO0 SO SCK RxD TxD T1CKO PWM TBPWM PWM TBPWM 0 3 Bit programmable port input or output mode G 8 9 26 27 selected by software input or push pull N channel open drain output Software assignable pull up NOTE Pin numbers shown in parentheses are for the 28 pin SOP package 1 8 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 PRODUCT OVERVIEW Table 1 1 S3C84H5X F84H5X Pin Descriptions Continued Pin Pin Pin Circuit Pin Share Name Type Description Type Number Pins INTO INT3 ADCO ADC7 AVREF AVSS xD D Input pins for external interrupt 28 31 P1 0 P1 3 Alternatively used as general purpose digital 24 27 input output port 1 Analog input pins for A D converter module 3 Alternatively used as general purpose digital P2 2 P2 3 input output port 0 port1 and port 2 P1 4 P1 5 A D converter reference voltage and ground Serial data RxD pin for receive input and transmit output mode 0 Serial data TxD pin for transmit output and shift clock output mode 0 TACK TACAP TAOUT TBOUT T1CKO T1CAPO T1OUTO T1CK1 T1CAP1 T1OUT1
62. TB8 and UARTCON 2 8 will be a parity selection bit for transmit and receive data respectively The UARTCON 3 TB8 is for settings of the even parity generation TB8 0 or the odd parity generation TB8 0 in the transmit mode The UARTCON 2 RB8 is also for settings of the even parity checking 8 0 or the odd parity checking RB8 1 in the receive mode The parity enable generation checking functions are not available in UART mode 0 and 1 If you don t want to use a parity mode UARTCON 2 RB8 UARTCON 3 TB8 are a normal control bit as the 9 gata bit in this case PEN must be disable 0 in mode 2 Also it is needed to select the 9th data bit to be transmitted by writing TB8 to or 1 The receive parity error flag RPE will be set to 0 or 1 depending on parity error whenever the 8 data bit of the receive data has been shifted UART DATA REGISTER UDATA UART Data Register UDATA F5H Set1 Bank 0 R W Reset Value FFH Transmit or Receive data Figure 15 3 UART Data Register UDATA ELECTRONICS 15 5 S3C84H5X F84H5X_UM_REV 1 10 UART BAUD RATE DATA REGISTER BRDATAH BRDATAL The value stored in the UART baud rate register BRDATAH BRDATAL lets you determine the UART clock rate baud rate UART Baud Rate Data Register BRDATAH EEH Set1 Bank 1 R W Reset Value FFH BRDATAL EFH Set1 Bank 1 R W Reset Value FFH Brud rate data Figure 15 4 UAR
63. The S3C8 series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you can access any location in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space LSB n Even address Rn 1 Figure 2 9 16 Bit Register Pair ELECTRONICS 2 13 S3C84H5X F84H5X UM REV 1 10 ADDRESS SPACES Special Purpose Registers Bank 1 Control Registers Register Pointers Each register pointer RP can independently point to one of the 2
64. The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS S3C84H5X F84H5X UM REV 1 10 INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI Operation Flags Format Example dst src dst lt src IR lt IR 1 The POPUI instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 93 R IR Given Register 00H 01H and register 01H 70H POPUI 02H Q00H gt Register OOH 02H register 01H 70H register 02H 70H If the general register contains the value 01H and the register 01H the value 70H the statement POPUI 02H 00H loads the value 70H into the destination general register 02H The user stack pointer the register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 PUSH Push to Stack PUSH Operation Flags Format Examples src SP SP 1 SP lt src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affec
65. UART Mode 2 Function Descriptor erini aniei eaaa nnnm 15 11 Serial Communication for Multiprocessor Configurations 15 13 Chapter 16 A D Converter A 16 1 F nction 92161 16 1 A D Converter Control Register 16 2 Internal Reference Voltage 16 4 5 16 4 Internal A D Conversion 16 5 17 Watch Timer OVOIVIGW x io discat die 17 1 Watch Timer Control Register WTCON 17 2 Watch Timer Circuit Diagram 17 8 Chapter 18 Low Voltage Reset E 18 1 S3C84H5X F84H5X UM REV 1 10 MICROCONTROLLER Table of Contents Continued Chapter 19 MTP Overview EX 19 1 Chapter 20 Electrical Data OVSIVIOW ud ite eit ea aree e 20 1 Chapter 21 Mechanical Data chaste dor cub aco ein D aa 21 1 Chapter 22 Development Tools OI E nc ots vat aoe ta ees eee 22 1 ee an dae a
66. are appended to the register name for bit addressing S3C84H5X F84H5X UM REV 1 10 Name of individual bit or related bits Register ID FLAGS System Flags Register Bit Identifier RESET Value Read Write Bit Addressing Mode 7 Read only W Write only R W Read write Not used Type of addressing that must be used to address the bit 1 bit 4 bit or 8 bit 4 4 Register location Register address in the internal Register name hexadecimal register file D5H Set 1 4 9 2 3 x x 0 0 R W R W R W R W R W R R W Register addressing modg only R W Carry Flag C Operation does not generate a carry or borrow conditidn EN Operation generates carry out or borrow into high ord drbit7 Zero Flag Z EN Operation result is a non zero value a Operation result is zero Sign Flag S Operation generates positive number MSB 0 Operation generates negative number MSB 1 Description of the effect of specific bit settings RESETvalue notation Not used Undetermined value 0 Logic zero 1 Logic one Bit number MSB Bit 7 LSB Bit 0 Figure 4 1 Register Description Format ELECTRONICS S3C84H5X F84H5X UM REV 1 10 CONTROL REGISTER ADCON A D Converter Control Register F7H Set1 Bit Identifier RESET Value Read Write Addressing Mode ELECTRONICS _ 5 4 3 2
67. are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RPO point to the lower slice and RP1 point to the upper slice see Figure 2 6 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 7 RPO points to the upper slice and RP1 to the lower slice Because a register pointer can point to either of the two 8 byte slices in the working register block you can flexibly define the working register area to support program requirements PROGRAMMING TIP Setting the Register Pointers SRP 70H RPO 70H lt 78H SRP1 48H RPO lt nochange RP1 lt 48H SRPO 0A0H RPO lt nochange CLR RPO RPO lt OOH lt nochange LD RP1 0F8H RPO lt nochange RP1 lt OF8H Register File Contains 32 8 Byte Slices 00001X XxX ix 8 Byte Slice 16 Byte Contiguous Working 00000XXX 8 Byte Slice Register block Figure 2 7 Contiguous 16 Byte Working Register Block ELECTRONICS 2 11 ADDRESS SPACES S3C84H5X F84H5X_UM_REV 1 10 ee 8 Byte S
68. bank 0 addressing The upper two 32 byte areas bank 0 and bank 1 of set 1 contains 64 mapped system and peripheral control registers The lower 32 byte area contains 16 system registers DOH DFH and 16 byte common working register area You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations COH FFH is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 For S3C84H5X F84H5X the set 2 address range COH FFH is accessible on pages 0 1 The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 locations In order to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode The set 2 register area is commonly used for stack operations 2 8 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes 00
69. be assigned a value of 0 or 1 by writing the TB8 bit UARTCON 3 When receiving the 9th data bit that is received is written to the RB8 bit UARTCON 2 while the stop bit is ignored The baud rate for mode 2 is fosc 16 x 16bit BRDATA 1 clock frequency lt In parity enable mode PEN 1 gt The 9th data bit to be transmitted can be an automatically generated parity of 0 or 1 depending on a parity generation by means of TB8 bit UARTCON 3 When receiving the received 9th data bit is treated as a parity for checking receive data by means of the RB8 bit UARTCON 2 while the stop bit is ignored The baud rate for mode 2 is fosc 16 x 16bit BRDATA 1 clock frequency Mode 2 Transmit Procedure 1 Select the baud rate generated by 16bit BRDATA 2 Select mode 2 9 bit UART by setting UARTCON bits 6 and 7 to 10B Also select the 9th data bit to be transmitted by writing TB8 to 0 or 1 and set PEN bit of UARTPND register to 0 if you don t use a parity mode If you want to use the parity enable mode select the parity bit to be transmitted by writing TB8 to 0 1 and set PEN bit of UARTPND register to 1 3 Write transmission data to the shift register UDATA F5H to start the transmit operation Mode 2 Receive Procedure 1 Select the baud rate to be generated by 16bit BRDATA 2 Select mode 2 and set the receive enable bit RE in the UARTCON register to 1 3 If you don t use a parity mode set P
70. board for the development of application systems using 84 5 Programming Socket Adapter When you program S3F84H5X s flash memory by using an emulator or OTP MTP writer you need a specific programming socket adapter for SSF84H5X 23 ELECTRONICS USER S MANUAL ERRATA S3C84H5X F84H5X_ERRATA_REV 1 10 Development System Configuration IBM PC AT or Compatible Emulator SK 1200 RS 232 USB or I 500 RS 232 RS 232C USB Target d i Application a a System Probe Adapter M Target S Board Chip Figure 22 1 Development System Configuration ELECTRONICS 24 S3C84H5X F84H5X ERRATA REV 1 10 USER S MANUAL ERRATA TB84H5 Target Board The TB84H5 target board can be used for development of S3F84H5X and 53 84 5 together But you should be careful to set the memory size to program internal flash memory The TB84H5 target board is operated as target CPU with Emulator SK 1200 OPENIce 1 500 To User Vcc 8419 8 84 REV X OFF ___ ON 200X XX XX RESET IDLE STOP e WODE CO In Circuit Emulator EB SK 1200 OPENIce 1 500 WERE ve 80 JP10 5 RA 5008 9 8008 0 D J1
71. chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 1 4 Example The statement STOP halts all microcontroller operations ELECTRONICS 6 81 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 SU subtract SUB dst src Operation dst lt dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand Flags Set if a borrow occurred cleared otherwise Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise 9 Always set to 1 Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst sr
72. counter 1 0 T1CNTH1 L1 a 16 bit comparator and two 16 bit reference data register T1IDATAHO LO T1DATAH1 L1 O pins for capture input 1 T1CAP1 or match output T1OUT1 e Timer 1 0 overflow interrupt IRQ2 vector C6H and match capture interrupt IRQ2 vector generation e Timer 1 1 overflow interrupt IRQ2 vector CAH and match capture interrupt IRQ2 vector C8H generation 0 control register 1 CONO set 1 Bank 1 read write e Timer 1 1 control register TI CON1 set 1 E9H Bank 1 read write e Timer 1 ELECTRONICS 12 1 16 BIT TIMER 1 0 1 S3C84H5X F84H5X_UM_REV 1 10 FUNCTION DESCRIPTION Timer 1 0 1 Interrupts IRQ2 Vectors C4H C6H C8H and CAH The timer 1 0 module can generate two interrupts the timer 1 0 overflow interrupt T1OVFO and the Timer 1 0 match capture interrupt T1INTO T1OVFO is interrupt level IRQ2 vector C6H T1INTO also belongs to interrupt level IRQ2 but is assigned the separate vector address C4H A timer 1 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer 1 0 match capture interrupt T1INTO pending condition is also cleared by hardware when it has been serviced The timer 1 1 module can generate two interrupts the timer 1 1 overflow interrupt T1OVF1 and the timer 1 1 match capture interrupt 11 1 T1OVF1 is interrupt level IRQ2 vector T1IN
73. data memory location 1104H RO 98H 11H contents of RO is loaded into program memory location 1105H 1105H 11H 11H contents of RO is loaded into external data memory location 1105H 1105H lt 11H NOTE TheLDC and the LDE instructions are not supported by masked ROM type devices ELECTRONICS 6 53 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 LDCD LDED Load Memory and Decrement LDCD LDED Operation Flags Format Examples NOTE dst src dst src dst lt src r lt 17 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD refers to program memory and LDED refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 10 E2 r Irr Given R6 10H R7 33H R8 12H program memory location 1033H and external data memory location 1033H ODDH LDCD R8 RR6 contents of program memory location 1033H is loaded into R8 and RR6 is decremented by one R8 R6 10H R7 32H R
74. destination location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst 451 2 8 80 RR 81 IR Given RO 12H R1 R2 register and register 21H DECW RRO gt RO 12H R1 33H DECW R2 gt Register OFH register 31H 20H In the first example the destination register RO contains the value 12H and the register R1 the value 34H The statement DECW RRO addresses RO and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To avoid this problem it is recommended to use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET DI Disable Interrupts DI Operation Flags Format Example SYM 0 lt 0 Bit zero of the system mode control register 0 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interr
75. e 10 bit A D conversion data output register ADDATAH ADDATAL FUNCTION DESCRIPTION To initiate an analog to digital conversion procedure at first you must configure 2 2 2 3 P1 4 P1 5 to analog input before A D conversions because the P0 0 P0 3 P2 2 P2 3 P1 4 P1 5 pins be used alternatively as normal data I O or analog input pins To do this you load the appropriate value to the POCONL P2CONL P1CONH for ADCO ADCY register And you write the channel selection data in the A D converter control register ADCON to select one of the eight analog input pins ADCn 0 7 and set the conversion start or enable bit ADCON 0 10 bit conversion operation can be performed for only one analog input channel at a time The read write ADCON register is located in set 1 bank 0 at address F7H During a normal conversion ADC logic initially sets the successive approximation register to 200H the approximate half way point of an 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 6 4 in the ADCON register To start the A D conversion you should set the enable bit ADCON 0 When a conversion is completed ADCON 3 the end of conversion EOC bit is automatically set to 1 and the re
76. errors we recommend using load instruction except for LDB when manipulating UARTPND values 3 Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only 4 Parity error bit RPE will be refreshed whenever 8th receive data bit has been shifted ELECTRONICS 4 37 CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 WTCON Watch Timer Control Register F8H Set1 Bank1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Watch Timer Clock Selection Bit 0 Main system clock divided by 256 fxx 256 Sub system clock fxt 6 Watch Timer Interrupt Enable Bit Disable watch timer interrupt 1 5 4 Buzzer Signal Selection Bits Fo 0 5 kHz buzzer BZOUT signal output 1 kHz buzzer BZOUT signal output Enable watch timer interrupt 1 0 2 kHz buzzer BZOUT signal output 4 kHz buzzer BZOUT signal output 3 2 Watch Timer Speed Selection Bits Fo o nssmem Fo r p5smma Pio otessinewal 1 Watch Timer Enable Bit Disable watch timer Clear frequency dividing circuits Enable watch timer 0 Watch Timer Interrupt Pending Bit IN Interrupt is not pending Clear pending bit when write Interrupt is pending 4 38 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 series interrupt structure has three basic components levels vectors
77. generation e Timer A control register TACON set 1 bank1 E1H read write ELECTRONICS 11 1 8 S3C84H5X F84H5X_UM_REV 1 10 FUNCTION DESCRIPTION Timer A Interrupts IRQ1 Vectors COH and C2H The timer A module can generate two interrupts the timer A overflow interrupt and the timer A match capture interrupt TAINT is interrupt level IRQ1 vector C2H TAINT also belongs to interrupt level IRQ1 but is assigned the separate vector address COH Timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced Timer A match capture interrupt TAINT pending condition is also cleared by hardware when it has been serviced Interval Timer Function The timer A module can generate an interrupt the timer A match interrupt TAINT TAINT belongs to interrupt level IRQ1 and is assigned the separate vector address COH When the timer A match interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware In interval timer mode a match signal is generated and is toggled when the counter value is identical to the value written to the timer A reference data register TADATA The match signal generates a timer A match interrupt TAINT vector COH and clears the counter If for example you write the value 10H to TADATA and OAH to TACON the counter will increment until it reaches 10H At this point
78. is interrupt level IRQ1 and has the vector address C2H When a timer A overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware To enable the timer A match capture interrupt IRQ1 vector COH you must write TACON 1 to 1 To generate the exact time interval you should write TACON 3 and 0 to 1 which cleared counter and interrupt pending bit When interrupt service routine is served the pending condition must be cleared by software by writing a 0 to the interrupt pending bit TINTPND O or TINTPND 1 Timer A Control Register E1H Set 1 Bank 1 R W Reset 00H ve e 8 2 Timer input clock selection bit Timer A start stop bit 00 fxx 1024 0 Stop timer 01 fxx 256 1 Start timer 10 fxx 64 11 External clock TACK Timer A match capture interrupt Timer A operating mode selection bit enable bit 00 Interval mode TAOUT mode 0 Disable interrupt 01 Capture mode capture on rising edge 1 Enable interrupt counter running OVF can occur 10 Capture mode capture on falling edge Timer A overflow interrupt enable bit counter running OVF can occur 0 Disable overflow interrupt 11 PWM mode OVF interrupt and match 1 Enable overflow interrrupt interrupt can occur Timer A counter clear bit 0 No effect 1 Clear the timer A counter when write NOTE When th counter clear bit 3 is set the 8 b
79. is received the serial interrupt will be generated only if RB8 1 To enable this feature you set the MCE bit in the UARTCON registers When the MCE bit is 1 serial data frames that are received with the 9th bit 0 do not generate an interrupt In this case the 9th bit simply separates the address from the serial data Sample Protocol for Master Slave Interaction When the master device wants to transmit a block of data to one of several slaves on a serial line it first sends out an address byte to identify the target slave Note that in this case an address byte differs from a data byte In an address byte the 9th bit is 1 and in a data byte it is O The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave then clears its MCE bit and prepares to receive incoming data bytes The MCE bits of slaves that were not addressed remain set and they continue operating normally while ignoring the incoming data bytes While the MCE bit setting has no effect in mode 0 it can be used in mode 1 to check the validity of the stop bit For mode 1 reception if MCE is 1 the receive interrupt will be issue unless a valid stop bit is received ELECTRONICS 15 13 S3C84H5X F84H5X UM REV 1 10 Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications Set all S8C84H5X F84H5X devices masters
80. least significant bit position bit zero was 1 Z Setif the result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 EO R 4 E1 IR Given Register 00H 31H register 01H 02H and register 02H 17H RR 00H gt Register 98H 1 RR 01H gt Register 01H 02H register 02H 8BH 1 In the first example if the general register contains the value 31H 00110001B the statement RR 00H rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and the overflow flag are also set to 1 ELECTRONICS 6 73 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 RRC Rotate Right through Carry RRC Operation Flags Format Examples dst dst 7 lt C lt dst 0 dst lt dst n 1 0 6 The contents of the destination operand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag and the initial value of the carry flag replaces bit 7 MSB Set if the bit rotated from the least significa
81. level is 128 The actual number of vectors used for S3C8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware S3C84H5X F84H5X uses sixteen vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each vector can have several interrupt sources In the S3C84H5X F84H5X interrupt structure there are sixteen possible interrupt sources When service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE S3C84H5X F84H5X UM REV 1 10 INTERRUPT TYPES The three components of the S3C8 interrupt structure described before levels vectors and sources are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source 54 Type 2 One level IRQn one vector V4 multiple sources S Sh Type 3 One level IRQn mu
82. lt dst The contents of the destination location are complemented one s complement All 1s are changed to 05 and vice versa Flags C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 60 R 4 61 IR Examples Given R1 07H and register 07H OF1H COM R1 R1 COM 3 R1 OF8H 07H register 07H OEH In the first example the destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and logic zeros to logic ones leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of the destination register 07H 11110001B leaving the new value OEH 00001110B ELECTRONICS 6 29 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 CP Compare CP dst src Operation dst src Flags Format Examples The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison C Setif a borrow occurred src dst cleared otherwise Z Setif the result is 0 cleared otherwise S Setifthe result is negative cle
83. memory locations 0103H 4 0104H 0105H 6DH 1104 88H External data memory locations 0103H 0104H 2 0105H LDC RO RR2 LDE RO RR2 LDC RR2 RO LDE RR2 RO LDC RO 01H RR2 LDE RO 01H RR2 LDC 01H RR2 RO LDE 01H RR2 RO LDC RO 1000H RR2 LDE RO 1000H RR2 LDC R0 1104H LDE R0 1104H LDC 1105H RO LDE 1105H RO 7 and 1104H 98H RO lt contents of program memory location 0104H RO 1AH R2 01H R3 04H RO lt contents of external data memory location 0104H RO 2AH R2 01H R3 04H 11H contents of RO is loaded into program memory location 0104H RR2 RO R2 no change 11H contents of RO is loaded into external data memory location 0104H RR2 RO R2 R3 no change RO lt contents of program memory location 0105H 01H RR2 RO 6DH R2 01H R3 04H RO lt contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H R3 04H 11H contents of RO is loaded into program memory location 0105H 01H 0104H 11H contents of RO is loaded into external data memory location 0105H 01H 0104H RO lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H R3 04H RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H R3 04H RO lt contents of program memory location 1104H RO 88H RO lt contents of external
84. modes You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 0 control registers must also be enabled in the associated peripheral module Port 0 Control Register Low Byte POCON E6H Set1 BankO R W Reset value 00H 7 6 5 4 3 2 41 ois 7 6 PO 3 ADC3Configuration Bits 0 0 Input mode 01 mode with pull up 1 0 Push pull output mode 1 1 Alternative function mode AD3 input 5 4 PO 2 AD2 Configuration Bits 0 0 Input mode 01 mode with pull up 1 0 Push pull output mode 1 1 Alternative function mode ADC2 input 3 2 1 ADC1 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 Alternative function mode ADC1 input 1 0 PO 0 ADCO Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 Alternative function mode ADCO input Figure 9 1 Port 0 Low Byte Control Register POCON ELECTRONICS 9 3 PORTS S3C84H5X F84H5X_UM_REV 1 10 PORT 1 Port 1 is a 6 bit I O port with individually configurable pins that you can use two ways e General purpose digital I O e Alternative function INTO INT3 TAOUT TACK TACAP T1OUT1 T1CK1 T1CAP1 AD5 AD6 BUZ Port 1 is accessed directly by writing or reading
85. o Basic imer convoi register eroon 24 o o o o o o o me oaa o o o o o o System fags register ruaas osa x x x x x o meo aia 081111 0 101 1 1 memor ais om 1 1 1 mteruptrequestregser zm System mode register Sw ze o o x x o 9 Register page porter Fe 8 2 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 RESET and POWER DOWN Table 8 2 S3C84H5X F84H5X Set 1 Bank 0 Register values after RESET omm eww e Te 7 6 8 2 1 0 Port 0 data Port dataregister EH Port 1 data register e e rb Port2dataregister Pa 2 eHjojojojofjofofofo Port 3 data register Ps 22 Location E4H is not mapped Be 1 0 Location is mapped Port corral register nigh bye PicoNH 232 E 9 9 Port control register byte PIOONL 288 EH Port pending register PUNTPND 234 0 0 0 Port interrupt control register PINT 235 een o Port control register high bye P2CONH 234 EcH o o 9 Port 2
86. pending bit selection bits 0 No interrupt pending 00 fosc 64 0 Clear pending condition when write 01 fosc 8 1 Interrupt pending 10 fosc 2 11 fosc 1 PWM OVF interrupt enable bit 0 Disable interrupt Not used for 1 Enable interrupt S3C84H5X F84H5X PWM counter enable bit 0 Stop counter 1 Start resume countering PWMDATA reload interval selection bit 0 reload from 10bit up counter overflow 1 reload from 8bit PWM counter clear bit up counter overflow 0 No effect 1 Clear the PWM counter Figure 13 3 PWM Control Register ELECTRONICS 13 5 10 PWM PULSE WIDTH MODULATION S3C84H5X F84H5X UM REV 1 10 fosc 8 fosc fosc 64 fosc 2 PWMCON 6 7 2 bit Extend bit 8 bit up counter PWMDATAL PWMDATAH 2 bit 8 bit Counter Counter PWMCON 2 1 When 8 bit 4 P2 1 PWM Extension Control Logic Extension Data Buffer 8 bit Data Bank1 PWMDATAH Bank1 PWMDATAL 1 0 PWMCON 3 clear 8 bit up counter overflow DATA BUS 7 0 Figure 13 4 PWM Functional Block Diagram 13 6 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 10 BIT PWM PULSE WIDTH MODULATION PROGRAMMING TIP Programming the PWM Module to Sample Specifications 1 lt lt Interrupt Vector Address gt gt ORG 0000H VECTOR ODAH INT_PWM 1 lt lt Initialize System and Peripherals gt g
87. pins for timer 1 1 T1OUT1 Timer 1 1 16 bit PWM mode ou or E 29 P1 3 counter na toggle output pins TEST Pull down resistor connected internally J a s voos e BEET 1 ELECTRONICS 1 11 PRODUCT OVERVIEW S3C84H5X F84H5X_UM_REV 1 10 PIN CIRCUITS Pull Up Resistor Schmitt Trigger Figure 1 6 Pin Circuit Type B nRESET P Channel Data Out Output N Channel Disable Figure 1 7 Pin Circuit Type C 1 12 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 PRODUCT OVERVIEW Pull up Enable Data Pin Circuit Output Type C Disable Figure 1 8 Pin Circuit Type D Pull up Pin enable Circuit Type C Port Data Alternative output Output Disable Noise Normal Input Figure 1 9 Pin Circuit Type D 5 P1 0 P1 3 ELECTRONICS 1 13 PRODUCT OVERVIEW S3C84H5X F84H5X_UM_REV 1 10 Pull up Resistor Typical Value 50kQ2 Pull up Enable Port Data Alternative output Output Disable O Figure 1 10 Pin Circuit Type E P2 2 P2 3 P1 4 1 5 1 14 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 Open Drain Data Output Disable PRODUCT OVERVIEW lt P Channel Pull up Enable N Channel Figure 1 11 Pin Circuit Type P3 0 P3 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C84H5X F84H5X microcontroller has two types of address space e Internal program memory ROM e Internal register fil
88. register IMR set 1 DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W 00 IRQ2 IRQ5 RQ6 Interrupt level enable bit 0 Disable IRQ interrupt 1 Enable IRQ interrupt Figure 5 6 Interrupt Mask Register IMR ELECTRONICS 5 11 INTERRUPT STRUCTURE S3C84H5X F84H5X UM REV 1 10 INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR set 1 bank 0 FFH is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt sources are active the source with th
89. same result as in the second example ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET CCF Complement Carry Flag CCF Operation Flags Format Example C lt NOT C The carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero If C 0 the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex opc 1 4 EF Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register 0D5H changing its value from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 CLR Clear CLR dst Operation dst lt Flags Format Examples The destination location is cleared to 0 No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 BO R 4 B1 IR Given Register 4FH register 01H 02H and register 02H CLR 00H gt Register OOH OOH CLR 01H gt Register 01H 02H register 02H 00H In Register addressing mode the statement CLR OOH clears the destination register value to OOH In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to OOH ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET COM Complement COM dst Operation dst
90. tcp means CPU clock period Figure 20 7 Waveform for UART Timing Characteristics 20 10 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ELECTRICAL DATA Table 20 11 A D Converter Electrical Characteristics TA 25 C to 85 Vpp Vss 0 V Symbol Test Conditions E linearity CPU clock 10 MHz error 5 12 V Differential linearity AVsg OV error orso Offset error of EOB 0 5 2 bottom Conversion time 1 tcon 10 bit 1 20 us 50 x 4 9 fosc 10 MHz Analog input VIAN AVss V voltage Analog input RAN 2 1000 MO impedance Analog reference voltage Analog input lADIN Vpp 5 current conversion time 20 Analog block lapc AVngr 5 current 2 conversion time 20 AV REF 2 3V conversion time 2 us 5V power down mode NOTES 1 Conversion time is the time required from the moment a conversion operation starts until it ends lapc is operating current during A D conversion 2 3 is the main oscillator clock 4 AVref must be tied to Vdd ELECTRONICS 20 11 ELECTRICAL DATA S3C84H5X F84H5X_UM_REV 1 10 Table 20 12 LVR Low Voltage Reset Circuit Characteristics Ta 25 LVR Voltage Level Vi vn LVR is enabled by smart option 2 5 2 8 25 Main Oscillator Freq
91. technology based on Samsung s latest CPU architecture The 53 84 5 is a microcontroller with a 16K byte mask programmable ROM embedded The SSF84H5X is a microcontroller with a 16K byte Flash ROM embedded Using a proven modular design approach Samsung engineers have successfully developed the S3C84H5X F84H5X by integrating the following peripheral modules with the powerful SAMB core e Five programmable I O ports 32 SOP SDIP ELP 22pins 30 SDIP 20pins 28 SOP 18pins including ports shared with segment common drive outputs e Four bit programmable pins for external interrupts e One 8 bit basic timer for oscillation stabilization and watchdog function system reset e Two 8 bit timer counter and Two 16 bit timer counter with selectable operating modes e One asynchronous UART and One synchronous SIO e One 10 bit PWM output e 10 bit 8 channel A D converter e Watch timer for real time The 53 84 5 84 5 is versatile microcontroller for home appliances and ADC applications etc They are currently available in 32 SOP SDIP ELP 30 SDIP 28 SOP package ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU e SAM8RC CPU core Memory e 272 bytes internal register file e 16 internal multi time program memory Oscillation Sources e Main clock oscillator Crystal Ceramic e clock divider 1 1 1 2 1 8 1 16 Instruction Set e 78 instructions e IDLE and STOP instructions added for power down mod
92. the addition of low order operands be carried into the addition of high order operands Flags C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise g Always cleared to 0 T Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 12 r r 6 13 r Ir opc src dst 3 6 14 R R 15 R IR opc dst src 3 6 16 R IM Examples Given R1 10H R2 03H C 1 register 01H 20H register 02H 03H register OAH ADC R1 R2 gt R1 14H R2 03H ADC R1 R2 gt R1 1BH R2 03H ADC 01H 02H gt Register 01H 24H register 02H ADC 01 002 gt Register 01H 2BH register 02H 03H ADC 01 811 gt Register 01H 32H In the first example the destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in the register R1 6 14 ELECTRONICS S3C84H5X F84H5X_UM_REV 1
93. the destination operand is not the result of a valid addition or subtraction of BCD digits Instruction Carry Bits 4 7 H Flag Bits 0 3 Number Added Carry Before DA Value Hex Before DA Value Hex to Byte After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 ADD 0 A F 0 0 9 60 1 ADC 0 9 0 66 1 0 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 06 0 1 7 0 0 9 60 1 1 6 1 6 66 1 Flags Set if there was a carry from the most significant bit cleared otherwise see table Z Set if result is 0 cleared otherwise S Set if result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 40 R 4 41 IR ELECTRONICS 6 33 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 DA Decimal Adjust DA Example Continued Given The working register RO contains the value 15 BCD the working register R1 contains 27 BCD and the address 27H contains 46 BCD ADD R1 RO lt 0 Bits 4 7 3 bits 0 3 C R1 lt 3CH DA R1 1 lt 3CH 06 If an addition is performed using the BCD values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using the standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100
94. the port 1 data register P1 at location E1H in set 1 bank 0 Port 1 Control Register P1CONH P1CONL Port 1 has two 6 bit control registers P1CONH for 1 4 1 5 and P1CONL for 1 0 1 3 A reset clears the P1CONH and P1CONL registers to configuring all pins to input modes You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 1 control registers must also be enabled in the associated peripheral module Port 1 Interrupt Enable Pending and Edge Selection Registers P1INTPND To process external interrupts at the port 1 pins three additional control registers are provided the port 1 interrupt enable register P1INT EAH SET1 BANK 0 the port 1 interrupt pending bits P1INTPND EBH SET1 BANK 0 The port 1 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the P1INTPND1 3 0 register at regular intervals When the interrupt enable bit of any port 1 pin is 1 a rising or falling edge at that pin will generate an interrupt request The corresponding P1INTPND1 bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request
95. timer B 1 Timer Mode Selection Bit One shot mode 1 Repeating mode 0 Timer Output flip flop Control Bit T FF is low 1 T FF is high NOTE is selected clock for system ELECTRONICS 4 3 CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 TINTPND rimer A Timer 1 Interrupt Pending Register EOH Set1 1 RESET VALUE 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for the S3C84H5X F84H5X must keep always 0 5 Timer 1 1 Overflow Interrupt Pending Bit o No interrupt pending o Clear pending bit when write Interrupt pending 4 Timer 1 1 Match Capture Interrupt Pending Bit No interrupt pending 0 Clear pending bit when write 1 Interrupt pending 3 Timer 1 0 Overflow Interrupt Pending Bit EN No interrupt pending ES Clear pending bit when write Interrupt pending 2 Timer 1 0 Match Capture Interrupt Pending Bit No interrupt pending ES Clear pending bit when write Interrupt pending 1 Timer A Overflow Interrupt Pending Bit No interrupt pending EI Clear pending bit when write Interrupt pending 0 Timer Match Capture Interrupt Pending Bit No interrupt pending ES Clear pending bit when write Interrupt pending 4 34 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 CONTROL REGISTER UARTCON UART Control Register F6H Set1 RESET Value 0 0 0 0 0 0 0 0 Read Wr
96. used in capture mode the timer 1 1 overflow interrupt is generated whenever a counter overflow occurs the timer 1 1 capture interrupt is generated whenever the counter value is loaded into the timer 1 data register By reading the captured data value in TI DATAH1 T1DATAL1 and assuming a specific value for the timer 1 1 clock frequency you can calculate the pulse width duration of the signal that is being input at the T1CAP1 pin 12 2 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 16 BIT TIMER 1 0 1 PWM Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the T1OUTO T1OUT1 pin As in interval timer mode match signal is generated when the counter value is identical to the value written to the timer 1 0 1 data registers In PWM mode however the match signal does not clear the counter but can generate a match interrupt Instead it runs continuously overflowing at FFFFH and then continuous increasing from OOOOH Whenever an overflow occur an overflow T1OVFO 1 interrupt can be generated Although you can use the match or overflow interrupts in the PWM mode these interrupts are not typically used in PWM type applications Instead the pulse at the T1OUTO T1OUT1 pin is held to low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to high level for as long as the data value is greater than gt the counter value O
97. value is located in register SPL D9H The SP value is undefined following a reset NOTE SPH must be initialized to at the start of a program 12 PORTS PAGE 9 4 PORT 1 Port 1 is a 6 bit I O port with individually configurable pins that you can use two ways e General purpose digital I O e Alternative function INTO INT3 TAOUT TACK TACAP T1OUT1 T1CK1 T1CAP1 AD5 AD6 BUZ ELECTRONICS 8 S3C84H5X F84H5X ERRATA REV 1 10 13 PORTS PAGE 9 6 Port 1 Control Register Low Byte P1CONL E9H Set1 R W Reset value 00H MSB 7 6 5 4 3 2 0 7 6 P1 3 T1OUT1 INT3 Configuration Bits 0 0 Input mode Interrupt input INT3 0 1 Input mode with pull up Interrupt input INT3 1 0 Push pull output mode 1 1 Alternative function mode T1OUT1 output 5 4 P1 2 TACAP INT2 Configuration Bits 0 0 Input mode Interrupt input INT2 TACAP 0 1 Input mode with pull up Interrupt input INT2 TACAP 1 0 Push pull output mode 1 1 Alternative function mode Not used 3 2 P1 1 TACK BUZ INT1 Configuration Bits 0 0 Input mode Interrupt input INT1 TACK 01 Input mode with pull up Interrupt input INT1 TACK 1 0 Push pull output mode 1 1 Alternative function mode BUZ output 1 0 P1 0 TAOUT INTO Configuration Bits 0 0 Input mode Interrupt input INTO 0 1 Input mode with pull up Interrupt input 1 0 Push pull out
98. 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag as shown in the figure below Set if the bit rotated from the most significant bit position bit 7 was 1 Z Setif the result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 90 R 4 91 IR Given Register 00H OAAH register 01H 02H and register 02H 17H RL 00H gt Register 00H 55 1 RL 01H gt Register 01H 02H register 02H 2EH 0 In the first example if the general register OOH contains the value 10101010B the statement RL rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and the overflow flags ELECTRONICS 6 71 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 Rotate Left through Carry RLC Operation Flags Format Examples dst dst 0 lt lt dst 7 dst 1 lt dst n n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C and the initial value of the carry flag replaces bit zero 7 0
99. 0 cycles if the divide by zero is attempted otherwise it takes 26 cycles Given RO 10H R1 03H R2 40H register 40H 80H DIVRRO R2 gt RO R1 40H DIVRRO R2 RO R1 20H DIVRRO 20H RO R1 80H In the first example the destination working register pair RRO contains the values 10H RO and R1 and the register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET DJNZ Decrement and Jump if Non Zero DJNZ r dst Operation 1 If r 0 lt PC dst The working register being used as counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement NOTE In case of using DJNZ instruction the working register being used as a counter should be set at the one of location to OCFH with SRP SRPO or 1 instruction
100. 01 J102 20 220 42SDIP 44QFP 1 1 1 44 s 8 3 eM 50 150 5 5 40 85 S5 60 L 1 7 9 70 18k 58 C16 10 10 35 80 30 90 100 110 120 Swi 15 15 30 25 1234 JP1 2 20 25 21 2222 23 N SMDS2 SMDS 2 Figure 22 2 53 4 5 Target Board Configuration 25 ELECTRONICS USER S MANUAL ERRATA S3C84H5X F84H5X_ERRATA_REV 1 10 Table 22 1 Components of TB84H5 Symbols Usage Description CN1 100 pin connector Connection between emulator and TB84H5 target board J101 J102 50 pin connector Connection between target board and user application system RESET Push button Generation low active reset signal to S3F84H5X EVA chip VCC GND POWER connector External power connector for TB84H5 IDLE STOP LED STOP IDLE Display Indicate the status of STOP or IDLE of SSF84H5X EVA chip on TB84H5 target board Table 22 2 Power Selection Settings for TB84H5 To User Vcc Settings Operating Mode To User VoD SMDS2 or SK 1200 supplies Vpp to the target board ff 9 evaluation chip and the target system To User VoD SMDS2 or SK 1200 supplies Vpp only to the target board Off n evaluation chip The target system must have a power supply of its own SMDS2 or SK 1200 IDLE LED This LED is ON when the evaluation chip 53 8410 is in idle mode STOP LED This LED is ON when the eval
101. 1 8 devices programming at one time 5 oem e Fast programming speed 1 2Kbyte sec ados e PC based control operation mode or Stand alone 2 Full Function regarding program inix Read Program Verify Protection Blank ww semini can e Data back up even at power break After setup in Design Lab it can be moved to the factory site Key Lock protecting operator s mistake Good Fail quantity displayed and memorized Buzzer sounds after programming User friendly single menu operation PC Operation status displayed in LCD panel ELECTRONICS 32 USER S MANUAL S3C84H5X F84H5X 8 BIT CMOS MICROCONTROLLERS July 2007 REV 1 10 Confiden 5 Copyright 2007 Samsun g Electronics Inc All Rights s Reserved Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any l
102. 1 10 WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real time and watch time measurement and interval timing for the system clock To start watch timer operation set biti and bit 6 of the watch timer mode register WTCON 1and 6 to 1 After the watch timer starts and elapses a time the watch timer interrupt is automatically set to 1 and interrupt requests commence in 1 955 ms or 0 125 0 25 and 0 5 second intervals The watch timer can generate a steady 0 5 kHz 1 kHz 2 kHz or 4 kHz signal to the BUZZER output BZOUT By setting WTCON 3 WTCON 2 to 110 the watch timer will function in high speed mode generating an interrupt every 1 955 ms High speed mode is useful for timing events for program debugging sequences e Real time and Watch time measurement e Using a main system or subsystem clock source e Buzzer output frequency generator e Timing tests in high speed mode ELECTRONICS 17 1 S3C84H5X F84H5X_UM_REV 1 10 WATCH TIMER CONTROL REGISTER WTCON R W Reset v v v v j ttt Table 17 1 Watch Timer Control Register WTCON Set 1 Bank 1 F8H R W Bit Name Values Function Address WTCON 7 0 Select 256 as the watch timer clock fx Main clock F8H Select subsystem clock as watch timer clock WTCON 6 Disable watch timer interrupt Enable watch timer interrupt WTCON 5 4 0 0 5 kHz buzzer BZOUT signal output 1 1 kHz
103. 10 ADD ADD Operation Flags Format Examples Add dst src dst lt dst src INSTRUCTION SET The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed 7 5 V Set if there is carry from the most significant bit of the result cleared otherwise Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Set if arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise Always cleared to Set if a carry from the low order nibble occurred Bytes Cycles dst src 2 4 6 src dst 3 6 opc dst src 3 6 Opcode Addr Mode Hex dst src 02 r r 03 r Ir 04 R R 05 R IR 06 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register OAH ADD ADD ADD ADD ADD R1 R2 R1 R2 01 02 01H 02H 01H 25H gt R1 15H R2 03H gt R1 1CH R2 03H gt Register 01H 24H register 02H gt Register 01H 2BH register 02H 03H Register 01H 46H In the first example the destination working register R1 contains 12H and the source working register R2 contains 03H The statement ADD R1 R2 adds 03H to 12H leaving the value 15
104. 1CAP1 input 0 1 Input mode with pull up T1CAP1 input 1 0 Push pull output mode Alternative function mode AD6 P1 4 T1CK1 AD5 Configration Bits Fo Input mode T1CK1 input ERE Input mode with pull up T1CK1 input ERES Push pull output mode Alternative function mode AD5 4 15 CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 P1CONL Port 1 Control Register Low Byte E9H Set1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 3 T10UT1 INT3 Configration Bits 810 Input mode Interrupt input INT3 2011 Input mode with pull up Interrupt input Push pull output mode Alternative function mode T1OUT1 mode 5 4 P1 2 TACAP INT2 Configration Bits lolo Input mode Interrupt input INT2 TACAP Input mode with pull up Interrupt input INT2 TACAP ro Push pulloutputmede CS 3 2 P1 1 TACK BUZ INT1 Configration Bits o 0 Input mode Interrupt input INT1 TACK 1 Input mode with pull up Interrupt input 1 TACK aja Push pull output mode Alternative function mode BUZ out mode 1 0 P1 0 TAOUT INTO Configration Bits Fo Input mode Interrupt input INTO Input mode with pull up Interrupt input INTO EZFJ Push pull output mode Alternative function mode TAOUT mode 4 16 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 CONTROL REGISTER
105. 27 Rb NOTE In the second byte of the 3 byte instruction format the destination the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H 00000111 and register 01H 0000001 1B BXOR R1 01H 1 gt R1 06H register 01H BXOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example the destination working register R1 has the value 07H 00000111B and the source register 01H has the value 03H 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of the register 01H the source with bit zero of R1 the destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of the source register 01H is unaffected ELECTRONICS 6 25 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 CALL Call Procedure CALL Operation Flags Format Examples dst SP lt SP 1 SP lt PCL SP lt SP 1 SP lt PCH PC lt dst The contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back
106. 32 pin SOP SDIP ELECTRONICS 19 1 S3C84H5X F84H5X_UM_REV 1 10 P2 5 SCK 32 1 P2 6 RxD 30 1 24 50 26 1 2 7 ADO P0 0 AD1 P0 1 AD2 P0 2 AD3 P0 3 TBPWM T1CKO P2 0 PWM T1CAPO P2 1 AD4 T10UTO P2 2 TEST XIN XOUT S3F84H5X Vss 32ELP 0505 Vdd P1 3 T10UT1 INT3 SCLK P1 2 TACAP INT2 SDAT P1 1 TACK BUZ INT1 1 2 3 4 5 6 7 8 AD7 SI P2 3 9 ADS T1CK1 P1 4 6 1 1 1 5 C INTO TAOUT P1 0 Figure 19 2 Pin Assignment 32 pin ELP 19 2 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 Vss Xour XIN TEST XTIN XTour nRESET 0 P3 1 SO P2 4 SCK P2 5 RxD P2 6 TxD P2 7 ADO PO 0 AD1 PO 1 ELECTRONICS S3C84H5X S3F84H5X Top View 30 SDIP O MTP P1 3 T1OUT1 INT3 SCLK P1 2 TACAP INT2 SDAT P1 1 TACK BUZ INT1 P1 0 TAOUT INTO AVss AV REF P1 5 AD6 T1CAP1 P1 4 AD5 T1CK1 P2 3 AD7 SI P2 2 ADA4 T1OUTO P2 1 T1CAP0 PWM P2 0 T1CKO TBPWM P0 2 AD2 Figure 19 3 Pin Assignment 30 pin SDIP Vss XIN TEST XTIN XTour nRESET SO P2 4 SCK P2 5 RxD P2 6 TxD P2 7 ADO PO 0 AD1 PO 1 AD2 P0 2 O S3C84H5X S3F84H5X Top View 28 SOP O S3C84H5X F84H5X_UM_REV 1 10 VDD P1 3 T1OUT1 INTSS SCLK P1 2 TACAP INT2 SDAT P1 1 TACK BUZ INT1 P1 0 TAOUT INTO AVss AV REF P1 5 AD6 T1CAP1 P1 4 AD5 T1CK1 P2 3 AD7 SI P2 2 ADA4
107. 4 gt gt 0C7H R1 02H22 1 RO R1 02H register 02H 23H 7 0 Register OOH 2BH register 01H 02H 2 1 Register OOH 2BH register 01H 02H register 02 23H Z 1 Register OOH 2BH Z 0 In the first example if the working register RO contains the value 0C7H 11000111B and the register R1 the value 02H 00000010B the statement TCM RO R 1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 Test under Mask Operation Flags Format Examples dst src dst AND src INSTRUCTION SET This instruction tests selected bits in the destination operand for a logic zero value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and the source operands are unaffected C T O lt YN Unaffected Set if the result is 0 cleared otherwise Set if the result bit 7 is set cleared otherwise Always reset to 0 Unaffected Unaffected opc dst src opc src dst dst src Bytes Cycles 2 4
108. 4 8 byte slices of the register file other than set 2 After a reset RPO points to locations COH C7H and 1 to locations 8 that is to the common working register area NOTE In the S3C84H5X F84H5X microcontroller pages 0 1 are implemented Pages 0 1 contain all of the addressable registers in the internal register file Page 0 All Addressing Modes Register Addressing Only Can be pointed by Register Pointer Figure 2 10 Register File Addressing 2 14 General Purpose Register Page 0 Indirect Register Indexed Addressing Modes ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESS SPACES COMMON WORKING REGISTER AREA After a reset register pointers RPO and RP1 automatically select two 8 byte register slices in set 1 locations as the active 16 byte working register block RPO COH C7H This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages Following a hardware reset register pointers RPO and RP1 point to the common working register area locations COH CFH 7799 1000 Figure 2 11 Common Working Register Area ELECTRONICS 2 15 ADDRESS SPACES S3C84H5X F84H5X_UM_R
109. 5 T1CK1 P2 3 AD7 SI P2 2 ADA T1OUTO P2 1 T1CAPO PWM P2 0 T1CKO TBPWM Figure 1 2 S3C84H5X F84H5X Pin Assignment 32 SOP SDIP ELECTRONICS S3C84H5X F84H5X ERRATA REV 1 10 4 PIN ASSIGNMENT PAGE 1 5 x 9 o o o2 90 2 522620270 15 E 415 L PT IRSE N t e 1 2 0 1 2 1 ADA T1OUTO P2 2 TxD P2 7 1 TEST ADOIPO 0 2 XIN AD1 P0 1 3 XOUT AD2 P0 2 4 S3F84H5X Vss 3 5 32ELP 0505 Vdd 6 7 8 Ne 80020 620006 Ya lt 5 lt oe 5 2 8 E lt 2 USER S MANUAL ERRATA P1 3 T1OUT1 INT3 SCLK P1 2 TACAP INT2 SDAT P1 1 TACK BUZ INT1 Figure 1 3 S3C84H5X F84H5X Pin Assignment 32 pin ELP ELECTRONICS USER S MANUAL ERRATA S3C84H5X F84H5X_ERRATA_REV 1 10 5 PIN ASSIGNMENT PAGE 1 6 Vss 1 VDD 2 P1 3 T10UT1 INT3 SCLK XIN 3 P1 2 TACAP INT2 SDAT TEST 4 P1 1 TACK BUZ INT1 XTIN 5 S3C84H5X P1 0 TAOUT INTO XTour 6 S3F84H5X AVss nRESET 7 AVREF P3 0 8 Top View P1 5 AD6 T1CAP1 P3 1 9 P1 4 AD5 T1CK1 SO P2 4 P2 3 AD7 SI SCK P2 5 30 SDIP P2 2 ADA T1OUTO RxD P2 6 P2 1 T1CAPO PWM TxD P2 7 P2 0 T1CKO TBPWM ADO P0 0 O P0 3 AD3 AD1 P0 1 P0 2 AD2 Figure 1 4 S3C84H5X F84H5X Pin Assignment 30
110. 55 LDCPD LDEPD Load Memory with 6 56 LDCPI LDEPI Load Memory with 6 57 LDW Load a oT o 6 58 MULT Multiply Unsigned 6 59 DH 6 60 MEE 6 61 Eogical OR aa 6 62 Pop from Stack n cmi 42 0840 i 6 63 POPUD Pop User Stack 6 64 POPUI Pop User Stack Incrementing sse 6 65 PUSH Puslito Stack uie e Te et 6 66 PUSHUD Push User Stack 6 67 PUSHUI Push User Stack Incrementing 6 68 RCF Reset Catry Lid aet ar mle 6 69 6 70 Rotate ie Ge 6 71 Rotate Left through 6 72 Rotate RIOM Em 6 73 RRC Rotate Right through Carty esses eene nnns nennen nes 6 74 SBO Select Bank e ae od deg doo e EU eai og 6 75 SB1 Select Em 6 76 SBC Subtract with Carry ad ara eave ca oh eee 6 77 SCF Set Garry Flag erri dices eased 6 78 SRA Shift Right Arithimetic 6 79 SRP SRPO SRP1 S
111. 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide e No special I O instructions I O control data registers are mapped directly into the register file e Decimal adjustment included in binary coded decimal BCD operations e 16 bit word data can be incremented and decremented e Flexible instructions for bit addressing rotate and shift operations DATA TYPES The CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Chapter 2 Address Spaces ADDRESSING MODES There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Chapter 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 Table 6 1
112. 79 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 SRP SRPO SRP1 set Register Pointer SRP SRPO SRP1 Operation Flags Format Examples NOTE src src src If src 1 1 and src 0 Othen RPO 3 7 lt src 3 7 If src 1 src 0 1 then RP1 3 7 src 3 7 If src 1 Oandsrc 0 Othen RPO 4 7 lt src 4 7 RPO 3 lt 0 RP1 4 7 lt src 4 7 RP1 3 lt 1 The source data bits one and zero LSB determine whether to write one or both of the register pointers RPO and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected RPO 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src opc src 2 4 31 IM The statement SRP 40H sets the register pointer 0 RPO at the location OD6H to 40H and the register pointer 1 RP1 at the location OD7H to 48 H The statement SRPO 50H would set RPO to 50H and the statement SRP1 68H would set RP1 to 68H Before execute the STOP instruction You must set the STPCON register as 10100101b Otherwise the STOP instruction will not execute ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET STOP Stop Operation STOP Operation The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on
113. AL TBDATAH 00H 1 TBDATAL TBDATAH 00 Timer Clock 1 TBDATAL TBDATAH 1FH T FF 0 TBDATAL TBDATAH 1 1 TBDATAL 7 TBDATAH 7 T FF 0 TBDATAL 7 TBDATAH 7 Figure 11 6 Timer B Output Flip Flop Waveforms in Repeat Mode 11 8 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 8 BIT TIMER A B PROGRAMMING TIP To generate 38 kHz 1 3duty signal through P2 0 This example sets Timer B to the repeat mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 38 kHz 1 3 Duty carrier frequency The program parameters are 8 795 us 17 59 4 37 9 kHz 1 3 Duty e Timer B is used in repeat mode e Oscillation frequency is 16 MHz 0 0625 us fx fxx 4 4MHz 0 25 us e TBDATAH 8 795 us 0 25 us 35 18 TBDATAL 17 59 5 0 25 us 70 36 e Set P4 3 to TBPWM mode ORG 0100H Reset address START DI LD TBDATAL 35 1 Set 17 5 us LD TBDATAH 70 1 Set 8 75 us LD TBCON 00100111B Clock Source lt fxx 4 Disable Timer B interrupt Select repeat mode for Timer B Start Timer B operation Set Timer B Output flip flop T FF high LD P1CONLH 0C0H Set P1 4 to TBPWM mode This command generates 38 kHz 1 3 duty pulse signal through P1 4 ELECTRONICS 11 9 8 S3C84H5X F84H5X_UM_REV
114. ARTPND 0 flag must be cleared by software in the interrupt service routine UART Pending Register UARTPND Set1 Bank 0 R W Reset Value 00H we s ene s ne we Jus Not used Not used UART transmit interrupt pending flag must keep always 0 must keep 0 Not pending always 0 0 Clear pending bit when write UART parity enable disable 1 Interrupt pending 0 Disable 1 Enable UART receive parity error UART receive interrupt pending flag 0 No error 0 Not pending 1 Parity error 0 Clear pending bit when write 1 Interrupt pending NOTES 1 In order to clear a data transmit or receive interrupt pending flag you must write a to the appropriate pending bit A 0 has no effect To avoid errors we recommend using load instruction except for LDB when manipulating UARTPND values Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only Parity error bit RPE will be refreshed whenever 8th receive data bit has been shifted Figure 15 2 UART Interrupt Pending Register UARTPND 15 4 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 UART In mode 2 9 bit UART data by setting the parity enable bit PEN of UARTPND register to 1 the 9 data bit of transmit data will be an automatically generated parity bit Also the 9 data bit of the received data will be treated as a parity bit for checking the received data In parity enable mode PEN 1 UARTCON 3
115. ATAL waon hom o o 7 m o hom o 1 m waon hom o n 9 meon hom o ws em 17 ELECTRONICS USER S MANUAL ERRATA S3C84H5X F84H5X_ERRATA_REV 1 10 23 A D CONVERTER PAGE 16 5 Analog ADCO Input Pin ADC7 S3C84H5X F84H5X NOTE 1 The symbol signifies an offset resistor with a value of from 50 to 100 2 Avref must be tied to Vdd Figure 16 5 Recommended A D Converter Circuit for Highest Absolute Accuracy ELECTRONICS 18 S3C84H5X F84H5X ERRATA REV 1 10 USER S MANUAL ERRATA 24 PROGRAMMING TIP OF WATCH TIMER PAGE 17 4 ORG 0000h VECTOR OD6h WT_INT ORG 0100h INITIAL DI LD IMR 00010000b Enable IRQ3 interrupt LD SPH 11111111b Set stack area LD SPL 0FFh LD BTCON 10100011b Disable Watch dog LD WTCON 11001110b 0 5 kHz buzzer 1 955ms duration interrupt Interrupt enable fxt 32 768Hz EI 25 TOOL PROGRAM MODE PAGE 19 2 x 02 te 2 NNN oF Ee 85888585 TxD P27 1 24 1 TEST 0 23 XIN AD1 FO 1 22 XOUT AD2 P0 2 3 TBPWM T1CKO P2 0 1 2 1 32ELP 0505 20 vdd P1 3 T10UT1 INT3 SCLK 18 P1 2 TACAP INT2 SDAT S3F84H5X 21 Vss O amp uU ADA T1TOUTO P2 2 17 O P11 TACK BUZ INT1 e e cr w uw m 560528505 E e
116. Alternative function mode TBPWM Figure 9 7 Port 2 Low Byte Control Register P2CONL ELECTRONICS 10 S3C84H5X F84H5X ERRATA REV 1 10 15 O PORTS PAGE 9 13 ue Programming Tip Using the Timer A INITIAL 11 ORG VECTOR VECTOR ORG 0000h OCOh TAMC INT OC2h TAOV INT 0100h SYM 00h IMR 0000001 0b SPH 11111111b SPL 00000000b BTCON 10100011b P1CONL 0ABH TADATA 80h TACON 01001010b USER S MANUAL ERRATA Disable Global Fast interrupt gt SYM Enable IRQ1 interrupt Set stack area Disable watch dog Enable TAOUT output Match interrupt enable 6 55 ms duration 10 MHz x tal ELECTRONICS USER S MANUAL ERRATA 16 PORTS PAGE 9 14 PROGRAMMING TIP Using Ports ORG 0100h INITIAL LD SPH 11111111b LD SPL 00000000b LD BTCON 1010001 1b LD CLKCON 18H LD POCON 0AAH LD P1CONH Z0AAH LD P1CONL ZOAAH LD P2CONH 0AAH LD P2CONL 0AAH LD P3CONL 0AAH ELECTRONICS S3C84H5X F84H5X_ERRATA_REV 1 10 Disable Watch dog PORTO PUSH PULL OUTPUT PORT1 PUSH PULL OUTPUT PORT1 PUSH PULL OUTPUT PORT2 PUSH PULL OUTPUT PORT2 PUSH PULL OUTPUT PORT3 PUSH PULL OUTPUT 12 S3C84H5X F84H5X ERRATA REV 1 10 USER S MANUAL ERRATA 17 FUNCTION DESCRIPTION PAGE 11 2 Capture Mode In capture mode a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the Timer A data register You can select rising or falling edges
117. CON 4 is 1 In mode 1 and 2 reception starts whenever an incoming start bit 0 is received and the receive enable bit UARTCON 4 is set to 1 PROGRAMMING PROCEDURE To program the UART modules follow these basic steps 1 Configure P2 6 and P2 7 to alternative function RXD P2 6 TXD P2 7 for UART module by setting the P1CONH register to appropriatly value Load an 8 bit value to the UARTCON control register to properly configure the UART module For parity generation and check in UART mode 2 set parity enable bit UARTPND 5 to 1 For interrupt generation set the UART interrupt enable bit UARTCON 1 or UARTCON O to 1 When you transmit data to the UART buffer write transmit data to UDATA the shift operation starts When the shift operation transmit receive is completed UART pending bit UARTPND 1 or UARTPND O is set to 1 and an UART interrupt request is generated ELECTRONICS 15 1 UART CONTROL REGISTER UARTCON S3C84H5X F84H5X_UM_REV 1 10 The control register for the UART is called UARTCON at address F6H It has the following control functions Operating mode and baud rate selection Multiprocessor communication and interrupt control Serial receive enable disable control 9th data bit location for transmit and receive operations mode 2 Parity generation and check for transmit and receive operations mode 2 UART transmit and receive interrupt control A reset cl
118. Control Bits 10100101 Enable stop instruction Other values Disable stop instruction NOTE Before execute the STOP instruction You must set this STPCON register as 10100101b Otherwise the STOP instruction will not be executed ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 CONTROL REGISTER SYM System Mode Register DEH Set 1 RESET Value 0 0 0 X X 0 0 Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Not used But you must keep always 0 4 2 Fast Interrupt Level Selection Bits 1 Fast Interrupt Enable Bit ES Disable fast interrupt processing Enable fast interrupt processing 0 Global Interrupt Enable Bit EN Disable global interrupt processing Enable global interrupt processing NOTE Following a reset you enable global interrupt processing by executing an El instruction not by writing a 1 to SYM O ELECTRONICS 4 29 CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 T1CONO Timer 1 0 Contro Register Bank1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer 1 0 Input Clock Selection Bits Fo o v mms opi oe a 1 0 1 extemalclockfalingedge 11 0 externalclockrisingedge 4 3 Timer 1 0 Operating Mode Selection Bits fo Interval mode EJES Capture mode Capture on rising edge OVF can occur Capture
119. E to a complete system with an OTP MTP programmer In Circuit Emulator for SAM8 family e OPENice i500 e SmartKit SK 1200 OTP MTP Programmer e SPW uni e AS pro e US pro e GW PRO2 8 gang programmer Development Tools Suppliers Please contact our local sales offices or the 3rd party tool suppliers directly as shown below for getting development tools 8 bit In Circuit Emulator OPENice i500 System TEL 82 31 223 661 1 FAX 82 331 223 6613 E mail openice aijisystem com URL http www aijisystem com lt 2 y 5 1200 Seminix TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http www seminix com 22 8 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 DEVELOPMENT TOOLS OTP MTP PROGRAMMER WRITER SPW uni SEMINIX Single OTP MTP FLASH Programmer e TEL 82 2 539 7891 e FAX 82 2 539 7819 e Download Upload and data edit function e Email e PC based operation with USB port m am e Full function regarding OTP MTP FLASH MCU i so e URL programmer Read Program Verify Blank Protection e Fast programming speed 4Kbyte sec Support all of SAMSUNG OTP MTP FLASH MCU devices Low cost NOR Flash memory SST Samsung NAND Flash memory SLC New devices will be supported just by adding device files or upgrading the software http Awww seminix com AS pro On board programmer for Samsung Flash MCU e Portable amp
120. ELECTRONICS USER S MANUAL ERRATA This document contains the corrections of errors typos and omissions in the following document Samsung 8 bit CMOS S3C84H5X F84H5X Microprocessor User s Manual Document Number 02 1 10 S3 C84H5X F84H5X 072007 Publication July 2007 S3C84H5X F84H5X ERRATA REV 1 10 USER S MANUAL ERRATA ERRATA VER 1 1 Samsung 8 bit CMOS S3C84H5X F84H5X Microprocessor User s Manual Document Number 02 1 10 S3 C84H5X F84H5X 072007 Publication July 2007 1 PRODUCT OVERVIEW PAGE 1 1 e Five programmable ports 32 SOP SDIP ELP 22pins 30 SDIP 20pins 28 SOP 18pins including ports shared with segment common drive outputs The S8C84H5X F84H5X is versatile microcontroller for home appliances and ADC applications etc They are currently available in 32 SOP SDIP ELP 30 SDIP 28 SOP package 2 FEATURES PAGE 1 2 Ports Total 22 bit programmable pins 32 SOP SDIP ELP Package Type e 32 pin SOP SDIP ELP 30 SDIP 1 ELECTRONICS USER S MANUAL ERRATA 3 PIN ASSIGNMENT PAGE 1 4 S3C84H5X F84H5X_ERRATA_REV 1 10 Vss TEST XTIN XTour nRESET P3 0 P3 1 SO P2 4 SCK P2 5 RxD P2 6 TxD P2 7 ADO PO 0 AD1 PO 1 AD2 P0 2 os OaRwWONMAOCPPONOARWNM O S3C84H5X S3F84H5X Top View 32 SOP 32 SDIP O VDD P1 3 T1OUT1 INT3 SCLK P1 2 TACAP INT2 SDAT P1 1 TACK BUZ INT1 P1 0 TAOUT INTO P3 3 P3 2 AVss AV REF P1 5 AD6 T1CAP1 P1 4 AD
121. EN bit of UARTPND register to 0 to disable parity mode If you want to use the parity enable mode select the parity type to be check by writing TB8 to 0 or 1 and set PEN bit of UARTPND register to 1 Only 8 bits BitO to Bit7 of received data are available for data value 4 The receive operation starts when the signal at the RxD pin goes to low level ELECTRONICS 15 11 S3C84H5X F84H5X_UM_REV 1 10 Tx Clock Write to Shift Register UARTDATA shi JL TxD start Bit DO 01 02 03 04 05 06 07 2 Stop Bit TIP TB8 or Parity bit Transmit RB8 or Parity bit Flows mum __ Shift RIP Figure 15 8 Timing Diagram for UART Mode 2 Operation 15 12 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 UART SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3C8 series multiprocessor communication features let a master SSC84H5X F84H5X send multiple frame serial message to slave device in a multi SSC84H5X F84H5X configuration It does this without interrupting other slave devices that may be on the same serial line This feature can be used only in UART mode 2 with the parity disable mode In mode 2 9 data bits are received The 9th bit value is written to RB8 UARTCON 2 The data receive operation is concluded with a stop bit You can program this function so that when the stop bit
122. EV 1 10 PROGRAMMING TIP Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations using working register addressing mode only Examples 1 LD 0C2H 40H Invalid addressing mode Use working register addressing instead SRP 0C0H LD R2 40H R2 C2H lt the value in location 40H Example 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead SRP 0COH ADD R3 45H R3 C3H lt R3 45H 4 BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8 byte slice of working register soace The address information stored in a register pointer serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address e high order bit of the 4 bit address selects one of the register pointers 0 selects RPO 1 selects RP1 e five high order bits in the register pointer select an 8 byte slice of the register space e The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 11 the result of this operation is that the five high order bits from the register pointer are concatenated with t
123. H in the register R1 ELECTRONICS 6 15 INSTRUCTION SET AND Logical AND AND Operation Flags Format Examples dst src dst lt dst AND src S3C84H5X F84H5X_UM_REV 1 10 The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation causes a 1 bit to be stored whenever the corresponding bits in the two operands are both logic ones otherwise a 0 bit value is stored The contents of the source are unaffected TOS YN Unaffected Set if the result is 0 cleared otherwise Always cleared to 0 Unaffected Unaffected dst src src dst opc dst src Set if the result bit 7 is set cleared otherwise Bytes Cycles 4 6 Opcode Addr Mode Hex dst src 52 r r 53 r Ir 54 R R 55 R IR 56 R IM Given R1 12H R2 03H register 01H 21H register 02H register OAH AND AND AND AND AND R1 R2 R1 R2 01 02 01H 02H 01H 25H 23 R1 R1 Register 01H Register 01H Register 01H 21H 02H R2 03H 02H 2 03H 01H register 02H register 02H 03H 03H In the first example the destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination oper
124. I System Level Interrupt Control Registers Interrupt Processing Control entente nnne nnn tnn ens Peripheral Interrupt Control Registers System Mode Register SYM Interrupt Mask Register nennen nn Interrupt Priority Register 1 nennen nennen terrens nnn sitne ens Interrupt Request Register 2 2 22 1 10 0 Interrupt Pending Function Interrupt Source Polling Sequence Interrupt Service Routines Generating interrupt Vector Addresses Nesting of Vectored Interrupts Chapter 6 Instruction Set vi Overview Data eode eee eid REgister Addressing Addressing e E n Ua REB d E ing arse ee Flags Register FLAGS Fag DESCniptlOns ce get caveats e to i Instruction Set Notation EE Instruction Descriptions S3C84H5X F84H5X_UM_REV 1 10 MICROCONTROLLER Table of Contents Continued Part Hardware Descriptions Chapter 7 Clock Circuit Overview System clock Circuit Clock Status During Power Down Modes System Clock Control Register CLKCON Chapter 8 RESET and Power Down System RESE l rab erect re I e Se eau Normal Mode Reset Opera
125. ICS 6 75 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 SB1 Select Bank 1 SB1 Operation Flags Format Example BANK lt 1 The 581 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting the bank 1 register addressing in the set 1 area of the register file NOTE Bank 1 is not implemented in some KS88 series microcontrollers No flags are affected Bytes Cycles Opcode Hex opc 1 4 5F The statement SB1 sets FLAGS 0 to 1 selectin the bank 1 register addressing if bank 1 is implemented in the microcontrooler s internla register file ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET SBC Subtract with Carry SBC Operation Flags Format Examples dst src dst lt dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands Set if a borrow occurred src gt dst cleared otherwise Set if the result is 0 cleared otherwise Z S Set if the result is negative cleared otherw
126. IRQ6 IRQ7 gt IRQ5 3 Interrupt Subgroup B Priority Control Bit gt IRQ4 IRQ4 2 Interrupt Group Priority Control IRQ2 gt IRQ4 1 IRQ3 IRQ4 gt IRQ2 0 Interrupt Group Priority Control Bit IRQO gt IRQ1 IRQ1 gt IRQO ELECTRONICS 4 11 CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 IRQ Interrupt Request Register DCH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R R R R R R R R Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Request Pending Bit Not pending Pending 6 Inte rupt Level 6 IRQ6 Request Pending Bit Not pending Pending 5 Inte rupt Level 5 IRQ5 Request Pending Bit Not pending Pending 4 Inte rupt Level 4 IRQ4 Request Pending Bit Not pending Pending rupt Level 3 IRQ3 Request Pending Bit Not pending Pending BB 2 Inte rupt Level 2 IRQ2 Request Pending Bit Not pending 1 Inte rupt Level 1 IRQ1 Request Pending Bit Not pending B Pending 0 Inte rupt Level 0 Request Pending Bit Not pending Be Pending 4 12 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 CONTROL REGISTER OSCCON oscillator Control Register F2H Set1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for the
127. JNZ CPIJE and JR Program Memory Next OPCODE Program Memory Address Used Value Current Instruction OPCODE Signed fF Displacement Value Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELECTRONICS 3 13 ADDRESSING MODES S3C84H5X F84H5X_UM_REV 1 10 IMMEDIATE MODE IM In Immediate IM addressing mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD RO0 0AAH Figure 3 14 Immediate Addressing 3 14 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 CONTROL REGISTER CONTROL REGISTERS OVERVIEW Control register descriptions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part Il of this manual The locations and read write characteristics of all mapped registers in the S3C84H5X F84H5X register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Registers Re
128. L OUTPUT PORT1 PUSH PULL OUTPUT PORT1 PUSH PULL OUTPUT PORT2 PUSH PULL OUTPUT PORT2 PUSH PULL OUTPUT PORT3 PUSH PULL OUTPUT ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 BASIC TIMER BASIC TIMER OVERVIEW BASIC TIMER BT You can use the basic timer BT in two different ways e Asa watchdog timer to provide an automatic reset mechanism in the event of a system malfunction e Tosignal the end of the required oscillation stabilization interval after a reset or a Stop mode release The functional components of the basic timer block are e Clock frequency divider fxx divided by 4096 1024 or 128 with multiplexer 8 bit basic timer counter BTCNT set 1 bank 0 read only e Basic timer control register BTCON set 1 read write BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using register addressing mode A reset clears BTCON to 00H This enables the watchdog function and selects a basic timer clock frequency of 15 4096 To disable the watchdog function write the signature code 1010B to the basic timer register control bits BTCON 7 BTCON A The 8 bit basic timer counter set 1 bank 0 FDH can be cleared at any time during normal operation by writin
129. M Oscillation n Stabilzation Stop gt 2 Data Retention Mode gt 5 Execution of STOP Instrction NOTE is the same as 4096 x 16 x 1 fosc Figure 20 4 Stop Mode Release Timing initiated by RESET 20 8 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ELECTRICAL DATA Oscillation Stabilization Time 311 Stop Mode _ Idle Mode lt Data Retention Mode A Normal Execution of Operating Mode STOP Instruction Interrupt twAIT is the same as 4096 x 16 x BT clock Figure 20 5 Stop Mode Main Release Timing Initiated by Interrupts Oscillation Stabilization Time 31 Stop Idle Mode Data Retention Mode gt 4 VDDDR lt Normal Execution of Operating Mode STOP Instruction Interrupt 0 2 VDD Y NOTE When the case of select the fxx 128 for basic timer input clock before enter the stop mode tWAIT 128 x 16 x 1 32768 62 5 ms Figure 20 6 Stop Mode Sub Release Timing Initiated by Interrupts ELECTRONICS 20 9 ELECTRICAL DATA S3C84H5X F84H5X_UM_REV 1 10 Table 20 10 UART Timing Characteristics in Mode 0 10 MHz Ta 25 C to 85 2 5V to 5 5 V Load capacitance 80 pF Serial port clock High Low level width NOTES 1 All timings are in nanoseconds ns and assume a 10 MHz CPU clock frequency 2 The unit
130. Opcode Addr Mode Hex dst dst 1 4 rE r r OtoF opc dst 2 4 20 R 4 21 IR Given RO 1BH register 00H OCH and register 1BH OFH INCRO RO 1CH INCOOH gt Register 00H INC RO RO 1BH register 01H 10H In the first example if the destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The second example shows the effect an INC instruction has on the register at the location assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of the register 1BH from OFH to 10H ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET INCW Increment Word INCW Operation Flags Format Examples NOTE dst dst lt dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 AO RR 1 Given RO R1 02H register 02H OFH register OFFH INCW RRO gt RO R1 03H INCW R1 gt Register 02H 10H regis
131. Push pull output mode 1 1 2 N channel open drain output 3 2 P3 1 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 1 0 P3 0 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output Figure 9 9 Port 3 Low Byte Control Register P3CONL 9 12 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 PORTS Programming Tip Using the Timer ORG 0000h VECTOR 0 0 INT VECTOR 0C2h TAOV INT ORG 0100h INITIAL LD SYM 00h Disable Global Fast interrupt gt SYM LD IMR 0000001 0b Enable IRQ1 interrupt LD SPH 11111111b Set stack area LD SPL 00000000b LD BTCON 1010001 1b Disable watch dog LD P1CONL 0ABH Enable TAOUT output 5 1 LD TADATA 80h LD TACON 01001010b Match interrupt enable 6 55 ms duration 10 MHz x tal SBO EI MAIN MAIN ROUTINE JR T MAIN TAMC_INT Interrupt service routine IRET TAOV INT Interrupt service routine IRET END ELECTRONICS 9 13 PORTS PROGRAMMING TIP Using Ports ORG INITIAL MAIN XOR JR END 0100h SPH 11111111b SPL 00000000b BTCON 1010001 1b CLKCON 18H POCON 0AAH P1CONH Z0AAH P1CONL 0AAH P2CONH 0AAH P2CONL 0AAH P3CONL 0AAH P1 03FH P2 0FFH P3 0FH T MAIN S3C84H5X F84H5X_UM_REV 1 10 Disable Watch dog PORTO PUSH PUL
132. Q4 WTCON F8H bank 1 SIO receive transmit IRQ5 SIOCON SIODATA F1H F2H bank 1 PWM overflow PWMCON bank 1 UART receive transmit IRQ7 UARTCON F6H bank 0 UDATA UARTPND F5H F4H bank 0 BRDATAH BRDATAL EEH EFH bank 1 ELECTRONICS 5 9 INTERRUPT STRUCTURE S3C84H5X F84H5X_UM_REV 1 10 SYSTEM MODE REGISTER SYM The system mode register SYM set 1 DEH is used to globally enable and disable interrupt processing see Figure 5 5 A reset clears SYM 0 to 0 The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate SYM 0 directly to enable and disable interrupts during the normal operation it is recommended to use the El and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W Global interrupt enable bit 0 Disable all interrupts processing 1 Enable all interrupts processing Not used for the S3C84H5 F84H5 Fast interrupt level selection bits Fast interrupt enable bit 0 Disable fast interrupts processing 1 Enable fast interrupts processing 0 0 40 Figure 5 5 System Mode Register SYM 5 10 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INTERRUPT STRUCTURE INTERRUPT MASK REGISTER IMR The interrupt mask
133. R CLKCON The system clock control register is located in set 1 address D4H It is read write addressable and has the following functions e Oscillator frequency divide by value After the main oscillator is activated and the fxx 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed fxx 8 fxx 2 or fxx 1 XTIN S3C84H5X S3F84H5X XT OUT 32 768 kHz Figure 7 4 System Clock Control Register CLKCON ELECTRONICS 7 3 CLOCK CIRCUIT S3C84H5X F84H5X_UM_REV 1 10 Oscillator Control Register OSCCON F2H Set 1 Bank 0 R W Not used must keep always 0 Not used must keep always 0 System clock selection bit 0 Main oscillator select 1 Subsystem oscillator select Subsystem oscillator control bit 0 Subsystem oscillator RUN 1 Subsystem oscillator STOP Mainsystem oscillator control bit 0 Mainsystem oscillator RUN 1 Mainsystem oscillator STOP NOTE When the CPU is operated with fxt sub oscillation clock it is possible to use the stop instruction but in this case before using stop instruction you must select fxx 128 for basic timer counter input clock Then the oscillation stabilization time is 62 5 1 32768 x 128 x 16 ms 100 ms Here the warm up time is from the time that the stop release signal activates to the time that basic timer starts counting Figure 7 5 Oscillator Control Register OSCCON
134. R6 10H R7 34H R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by RR6 lt 1 R8 ODDH R6 10H R7 34H LDEI instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS 6 55 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 LDCPD LDEPD Load Memory with Pre Decrement LDCPD dst src LDEPD dst src Operation 1 dst lt src These instructions are used for block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes Irr an even number for program memory and an odd number for external data memory Flags No flags are affected Format opc src dst Examples Given RO 77H R6 LDCPD RR6 RO LDEPD RR6 RO Bytes Cycles Opcode Addr Mode Hex dst src 2 14 F2 Irr r and R7 OOH RR6 lt RR6 1 TTH the contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 RR6 lt RR6 1 TTH the contents of RO is loaded into external data memory location 2FFFH 3000H 1H
135. R6 lt RR6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 32H LDED instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS S3C84H5X F84H5X UM REV 1 10 INSTRUCTION SET LDCI LDEI Load Memory and Increment LDCI LDEI Operation Flags Format Examples NOTE dst src dst src dst lt src rr m 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Ir an even number for program memory and odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 10 r Irr Given R6 10H R7 33H R8 12H program memory locations 1033H 1034H external data memory locations 1033H ODDH and 1034H OD5H LDCI R8 RR6 contents of program memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8
136. ROUTINE JR T MIAN AND WTCON 11111110b pending clear IRET ELECTRONICS S3C84H5X F84H5X UM REV 1 10 LOW VOLTAGE RESET LOW VOLTAGE RESET OVERVIEW The S8C84H5X F84H5X be reset in four ways e external power on reset e by the external reset input pin pulled low e by the digital watchdog timing out by the Low Voltage reset circuit LVR During an external power on reset the voltage VDD is High level and the nRESET pin is forced Low level The nRESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This brings the S3C84H5X F84H5X into a known operating status To ensure correct start up the user should take that reset signal is not released before the VDD level is sufficient to allow MCU operation at the chosen frequency The nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal CPU clock oscillation to stabilize The minimum required oscillation stabilization time for a reset is approximately 6 55 ms z218 fosc fosc 10MHz When a reset occurs during normal operation with both VDD and nRESET at High level the signal at the nRESET pin is forced Low and the reset operation starts All system and peripheral control registers are then set to their default hardware reset values see Table 8 1 The MCU provides a watchdog timer function in order to ensure graceful
137. RQ2 interrupt LD SPH 11111111b Set stack area LD SPL 00000000b LD BTCON 1010001 1b Disable Watch dog SB1 LD T1CONO 01000110b Enable interrupt fxx 64 Interval Interval 1 536 ms 10 MHz x tal LDW T1DATAHO 00FO0h T1DATAHO 00h T1DATALO FOh SBO EI MAIN MAIN ROUTINE JR T TIM1 INT Interrupt service routine IRET END ELECTRONICS 12 7 S3C84H5X F84H5X_UM_REV 1 10 10 BIT PWM PULSE WIDTH MODULATION 10 BIT PWM PULSE WIDTH MODULATION OVERVIEW This microcontroller has the 10 bit PWM circuit The operation of all PWM circuit is controlled by a single control register PWMCON The PWM counter is a 10 bit incrementing counter It is used by the 10 bit PWM circuits To start the counter and enable the PWM circuits you set PWMCON 2 to 1 If the counter is stopped it retains its current count value when re started it resumes counting from the retained count value When there is a need to clear the counter you set PWMCON 3 to 1 You can select a clock for the PWM counter by set PWMCON 6 7 Clocks which you can select are 64 FUNCTION DESCRIPTION PWM The 10 bit PWM circuits have the following components 8 bit comparator and extension cycle circuit 8 bit reference data register PWMDATAH 7 0 2 bit extension data register PWMDATAL 1 0 PWM output pins P2 1 PWM PWM Counter To determine the PWM module s base operating frequency the upper 8 bits of counter is compa
138. S3C84H5X F84H5X must keep always 0 3 Main System Oscillator Control Bit Main System Oscillator RUN 1 Main System Oscillator STOP 2 Sub System Oscillator Control Bit Sub system oscillator RUN 1 Sub system oscillator STOP 1 Not used for the S3C84H5X F84H5X must keep always 0 0 System Clock Selection Bit Main oscillator select 1 Subsystem oscillator select ELECTRONICS 4 1 CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 POCON Port 0 Contro Register High Byte E6H Set1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P0 3 AD3 Configration Bits Input mode Input mode with pull up Push pull output mode Alternative function mode AD3 input Input mode Input mode with pull up Push pull output mode Alternative function mode AD2 input Input mode Push pull output mode Input mode with pull up Alternative function mode AD1 input 1 Input mode Input mode with pull up Push pull output mode 4 14 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 CONTROL REGISTER P1CONH Port 1 Control Register High Byte E8H Set1 Bit Identifier RESET Value Read Write Addressing Mode 7 4 ELECTRONICS _ 5 4 3 2 4 0 0 0 0 0 0 0 0 0 R W R W R W R W Register addressing mode only Not used for the S3C84H5X F84H5X must keep always 0 P1 5 T1CAP1 AD6 Configration Bits Input mode T
139. SBUF SIOCON 00001000B SIOCON 11111110 Data transmit routine 1 byte transmission Shift start 8 bit transmit Pending bit clear S3C84H5X F84H5X_UM_REV 1 10 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 UART UART OVERVIEW The UART block has a full duplex serial port with programmable operating modes There is one synchronous mode and three UART Universal Asynchronous Receiver Transmitter modes e Shift Register with baud rate of fxx 16 x 16bit BRDATA 1 e 8 bit UART mode variable baud rate fxx 16 16bit BRDATA 1 e 9 bit UART mode variable baud rate fxx 16 x 16bit BRDATA 1 UART receive and transmit buffers are both accessed via the data register UDATA is at address F5H Writing to the UART data register loads the transmit buffer reading the UART data register accesses a physically separate receive buffer When accessing a receive data buffer shift register reception of the next byte can begin before the previously received byte has been read from the receive register However if the first byte has not been read by the time the next byte has been completely received the first data byte will be lost Overrun error In all operating modes transmission is started when any instruction usually a write operation uses the UDATA register as its destination address In mode 0 serial data reception starts when the receive interrupt pending bit UARTPND 1 is 0 and the receive enable bit UART
140. Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols Symbol Description dst src PC FLAGS RP Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register D5H Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET Table 6 4 Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6 6 r Working register only Rn 0 15 rb Bit b of working register 0 15 b 0 7 Bit 0 LSB of working register Rn 0 15 Ir Working register pair RRp p 0 2 4 14 R Register or working register reg Rn reg 0 255 n 0 15 Rb Bit b of register or working register reg b reg 0 255 b 0 7 RR Register pair or working register pair reg or RRp reg 0 254 even number only where p 0 2 14 Indirect addressing mode addr addr 0 254 even number only Ir Indirect working register only Rn 0 15 IR Indirect register or indirect working register Rn or reg reg 0 255 0 15 Irr Indirect working register pair only RRp p 0 2 14 IRR Indirect re
141. T Baud Rate Data Register BRDATAH BRDATAL BAUD RATE CALCULATIONS The baud rate is determined by the baud rate data register 16bit BRDATA Mode 0 baud rate fxx 16 x 16Bit BRDATA 1 Mode 1 baud rate 16 x 16Bit BRDATA 1 Mode 2 baud rate fxx 16 16Bit BRDATA 1 15 6 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 UART Table 15 1 Commonly Used Baud Rates Generated by 16bit BRDATA Baud Rate Oscillation Clock E memo o 7 7 8400 o 9 3 FP _ o 9 a eom fom o o 9 4 ason w asm Jeme l 0 e M Hase Jeme 6 o 3 EM Homo o o Ww ELECTRONICS 15 7 S3C84H5X F84H5X_UM_REV 1 10 BLOCK DIAGRAM 5 88 Internal Data Bus 1 1 16 UDATA F Y 50 RxD 2 6 Yvvvi CLK MS1 xD Generator Zero Detector Write to Eric UDATA Start Tx Control Tx Clock TIP Fall TxD P2 7 Shift Interrupt LA ME Clock RIE gt Rx Clock RIP Receive Rx Control Shift Transition etector Bit Detector D RxD P2 6 88 Internal Data Bus Figure 15 5 UART F
142. T1 also belongs to interrupt level IRQ2 but is assigned the separate vector address C8H A timer 1 1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer 1 1 match capture interrupt T1INT1 pending condition is also cleared by hardware when it has been serviced Interval Mode match The timer 1 0 module can generate an interrupt the timer 1 0 match interrupt T1INTO T1INTO belongs to interrupt level IRQ2 and is assigned the separate vector address C4H In interval timer mode a match signal is generated and T1OUTO is toggled when the counter value is identical to the value written to the Timer 1 reference data registers T1DATAHO and T1DATALO The match signal generates a timer 1 0 match interrupt T11NTO vector C4H and clears the counter value The timer 1 1 module can generate an interrupt the timer 1 1 match interrupt T1INT1 T1INT1 belongs to interrupt level IRQ2 and is assigned the separate vector address C8H In interval timer mode a match signal is generated and T1OUTI1 is toggled when the counter value is identical to the value written to the Timer 1 reference data register TIDATAH1 and T1DATAL1 The match signal generates a timer 1 1 match interrupt T1INT1 vector C8H and clears the counter value Capture Mode In capture mode for timer 1 0 a signal edge that is detected at the T1CAPO pin opens a gate and loads the current counter value into the timer 1 da
143. Tools Suppliers Please contact our local sales offices or the 3rd party tool suppliers directly as shown below for getting development tools 8 bit In Circuit Emulator OPENice 1500 System e TEL 82 31 223 6611 e FAX 82 331 223 6613 E mail openice aijisystem com e URL http www aijisystem com R SK 1200 Seminix TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http www seminix com ELECTRONICS 30 S3C84H5X F84H5X_ERRATA_REV 1 10 USER S MANUAL ERRATA OTP MTP PROGRAMMER WRITER SPW uni SEMINIX Single OTP MTP FLASH Programmer e Download Upload and data edit function e PC based operation with USB port e Full function regarding OTP MTP FLASH MCU programmer Read Program Verify Blank Protection e Fast programming speed 4Kbyte sec Support all of SAMSUNG OTP MTP FLASH MCU devices Low cost NOR Flash memory SST Samsung NAND Flash memory SLC New devices will be supported just by adding device files or upgrading the software TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http Awww seminix com 31 AS pro On board programmer for Samsung Flash MCU e Portable amp Stand alone Samsung OTP MTP FLASH Programmer for After Service e Small size and Light for the portable use e Support all of SAMSUNG OTP MTP FLASH devices e file download via USB from PC e Very fast pr
144. UAL ERRATA 28 ELECTRICAL DATA PAGE 20 11 Table 20 11 A D Converter Electrical Characteristics 25 to 85 C Vss 0 V Parameter Symbol win um Total accuracy Total accuracy 5 12 V Integral linearity CPU clock 10 MHz error 5 12 V Differential AVss OV linearity error Offset error of top Offset error of bottom 10 bit conversion 50 x Alfosc note 3 reference voltage Analog input current Analog block current note 2 conversion time 20 conversion time 20 us Vpp 5 V when power down mode NOTES 1 Conversion time is the time required from the moment a conversion operation starts until it ends is operating current during A D conversion 2 3 is the main oscillator clock 4 AVref must be tied to Vdd 21 ELECTRONICS USER S MANUAL ERRATA S3C84H5X F84H5X_ERRATA_REV 1 10 29 ELECTRICAL DATA PAGE 20 13 53 84 5 F84H5X Figure 20 9 The Circuit Diagram to Improve EFT Characteristics NOTE To improve EFT characteristics we recommend using capacitor between Vdd and Vss Test and Vss Reset and Vss closely from S3C84H5X F84H5X And you d better also put External crystal closely from S3C84H5X F84H5X 30 ELECTRICAL DATA PAGE 21 2 0 75 0 05
145. Word LDW Operation Flags Format Examples dst src dst lt src The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 C4 RR RR C5 RR IR opc dst src 4 8 C6 RR IML Given R4 06H R5 1CH R6 05H R7 02H register register 01H 02H register 02H 03H and register 03H OFH LDW RR6 RR4 gt R6 O6H R7 1CH R4 O6H R5 1CH LDW 00H 02H gt Register 03H register 01H OFH register 02H register OFH LDW RR2 R7 gt R2 03H R3 OFH LDW 04 001 gt Register 04H register 05H OFH LDW RR6 1234H R6 12H R7 34H LDW 02H Z0FEDH Register 02H OFH register 03H OEDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H and 03H into the destination word OOH and 01H This leaves the value 03H in the general register and the value OFH in the register 01H Other examples show how to use the LDW instruction with various addressing modes and formats ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 MULT Multiply Unsigned MULT Operation Flags Format Examples dst src dst lt dst x src INSTRUCTION SET The 8 bit destination operand the even numbered register of the regi
146. YM register to 01H enabling all interrupts SYM O is the enable bit for global interrupt processing ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET ENTER Enter ENTER Operation SP SP 2 lt IP lt PC lt lt 2 This instruction is useful when implementing threaded code languages The contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows an example of how to use an ENTER statement Before After Address Data Address Data Address Address 0040 Enter 0110 40 Enter Address H 41 Address H Address L 42 Address L 0022 Address H 0020 43 Address H 110 i 20 IPH 00 Boune 21 IPL 50 22 22 Data Stack Stack ELECTRONICS 6 41 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 EXIT Exit EXIT Operation IP lt 5 lt 5 2 lt IP 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter
147. _UM_REV 1 10 16 BIT TIMER 1 0 1 Timer A Timer 1 Pending Register TINTPND EOH Set 1 Bank 1 R W Not used must keep always 0 Timer 1 1 overflow interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Timer 1 1 match capture interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Timer A match capture pending bit interrupt 0 No interrupt pending 1 Interrrupt pending Timer A overflow pending iiferupt 0 No interrupt pending 1 Interrrupt pending Timer 1 0 match capture interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Timer 1 0 overflow interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Figure 12 2 Timer A Timer 1 0 1 Pending Register TINTPND ELECTRONICS 16 BIT TIMER 1 0 1 S3C84H5X F84H5X_UM_REV 1 10 BLOCK DIAGRAM T1CON 7 5 1024 9 Overflow 256 fxx 64 gt fxx 8 gt M fxx 1 gt U T1CK Data Bus 16 bit Up Counter i Read Only T1OUT T1PWM Data Bus NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bit is located at TINTPND register Figure 12 3 Timer 1 0 1 Functional Block Diagram 12 6 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 16 BIT TIMER 1 0 1 PROGRAMMING TIP Using the Timer 1 0 ORG 0000h VECTOR OCAh TIM1 INT ORG 0100h INITIAL LD SYM 00h Disable Global Fast interrupt LD IMR 00001000b Enable I
148. able interrupts El Enable interrupts IDLE Enter Idle mode NOP No operation RCF Reset carry flag SBO Set bank 0 SB1 Set bank 1 SCF Set carry flag SRP src Set register pointers SRPO src Set register pointer 0 SRP1 src Set register pointer 1 STOP Enter Stop mode ELECTRONICS 6 5 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits which describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 can be tested and used with conditional jump instructions Two other flag bits FLAGS 3 and FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether register bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then two write will simultaneously occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H Set 1 R W 7 B Bank address status
149. ag is cleared to logic zero regardless of its previous value C Cleared to 0 No other flags are affected Bytes Cycles Opcode Hex 1 4 Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero ELECTRONICS 6 69 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 RET Return RET Operation Flags Format Example PC lt SP SP lt SP 2 The RET instruction is normally used to return to the previously executed procedure at the end of the procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement to be executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex opc 1 10 AF Given SP SP 101AH and PC 1234 RET gt PC 101AH SP OOFEH The RET instruction pops the contents of the stack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in the location OOFEH 1AH into the PC s low byte and the instruction at the location 101AH is executed The stack pointer now points to the memory location OOFEH ELECTRONICS S3C84H5X F84H5X UM REV 1 10 INSTRUCTION SET RL Rotate Left RL Operation Flags Format Examples dst lt dst 7 dst 0 lt dst 7 dst n 1 lt dst n n
150. age Vin Vpp Current All input pins except Vin and XT our Input Low Leakage Vin OV Current All input pins except and Xin and Leakage Current All output pins Current All output pins ELECTRONICS 20 3 ELECTRICAL DATA S3C84H5X F84H5X_UM_REV 1 10 Table 20 3 D C Electrical Characteristics Concluded TA 25 C to 85 C 2 5V to 5 5 V Parameter Symb Conditions win Typ Mex 50 10 Pull up Resistor Rp Vpop 5 Vy 25 0 25 All pins except nRESET gt 5 Vin OV 150 250 480 25 RESETB only RUN mode 10 MHz CPU clock Vpp 2 5 to 3 3 V RUN mode 4 MHz CPU clock Idle mode 10 MHz CPU clock 2 5 to 3 3 V Idle mode 4 MHz CPU clock 1503 Sub operating main osc stop 32768 Hz crystal oscillator 1504 Sub idle mode main osc stop 32768 Hz crystal oscillator Ipp5 3 Vpp 4 5V to 5 5 V 25 Stop mode NOTES Supply current does not include current drawn through internal pull up resistors or external output current loads and include a power consumption of subsystem oscillator and are the current when the main system clock oscillation stop and the subsystem clock is used Ipps is the current when the main and subsystem clock oscillation stop All currents Ipps include the curr
151. ailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part Il If you are not yet familiar with the S3C8 series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6 Later you can reference the information in Part as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the S3C84H5X F84H5X microcontroller Also included in Part Il are electrical mechanical and development tools data It has 17 chapters Chapter 7 Clock Circuit Chapter 16 A D Converter Chapter 8 RESET and Power Down Chapter 17 Watch Timer Chapter 9 Ports Chapter 18 LCD Controller Driver Chapter 10 Basic Timer Chapter 19 Low Voltage RESET Chapter 11 8 bit Timer A B Chapter 20 Embedded Flash Memory Chapter 12 16 bit Timer 1 0 1 Interface Chapter 13 10 bit PWM Chapter 21 Electrical Data pulse width modulation Chapter 22 Mechanical Data Chapter 14 Serial I O Interface Chapter 23 Development Tools Chapter 15 UART S3C84H5X F84H5X UM REV 1 10 MICROCONTROLLER iii Table of Contents Part Progra
152. al crystal oscillator Operating Temperature Range e 25 C to 85 C Operating Voltage Range e LVRon LVR to 5 5 V 8 2 e LVR off 2 5 V to 5 5 V 8MHz e LVRoff on 4 5 V to 5 5 V 10MHz Package Type e 32 pin SOP SDIP ELP 30 SDIP 285 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 BLOCK DIAGRAM P0 0 P0 3 ADO AD3 Xin gt 4 XTin gt XTout nRESET OSC RESETB P1 0 P1 5 INTO INT3 BUZ AD5 AD6 TAOUT TACAP TACK 100 1 1 1 Port 0 Port 1 8 Bit Basic Timer Port and Interru pt Control P1 0 TAOUT 4 P1 2 TACAP P1 1 TACK P2 0 TBPWM 8 Bit Timer Counter A B P2 2 T10UTO P2 0 T1CK0 gt P2 1 T1CAPO P1 3 T10UT1 4 P1 4 T1CK1 P1 5 T1CAP1 16 Bit Timer Counter 10 11 SAMB88RC CPU P2 7 TxD P2 6 RxD 4 16K Byte ROM 528 Byte RAM P2 1 PWM ELECTRONICS Figure 1 1 S3C84H5X F84H5X Block Diagram PRODUCT OVERVIEW 2 0 2 7 T1CKO0 T1CAPO T1OUTO AD4 AD7 TBPWM PWM SI SO SCK RxD TxD P3 0 P3 4 ADCO ADG7 P0 0 P0 3 P1 4 P1 5 P2 2 P2 3 AV REF AVSS P2 4 SO 4 2 3
153. and slaves to UART mode 2 with parity disable 2 Write the MCE bit of all the slave devices to 1 The master device s transmission protocol is First byte the address identifying the target slave device 9th bit 2 1 Next bytes data 9th bit 0 4 When the target slave receives the first byte all of the slaves are interrupted because the 9th data bit is 1 The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive incoming data The other slaves continue operating normally Full Duplex Multi S3C84H5X F84H5xX Interconnect RxD RxD TxD RxD TxD RxD Master Slave 1 Slave 2 2 Slave S3C84H5X S3C84H5X S3C84H5X S3C84H5X F84HSX F84H5X F84H5X F84H5X Figure 15 9 Connection Example for Multiprocessor Serial Data Communications 15 14 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 A D CONVERTER A D CONVERTER OVERVIEW The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10 bit digital values The analog input level must lie between the and AVss values The A D converter has the following components e Analog comparator with successive approximation logic e D A converter logic resistor string type ADC control register ADCON set 1 bank 0 F7H read write but ADCON 3 is read only e Eight multiplexed analog data input pins ADCO ADC7
154. and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 16 2F Example The diagram below shows an example of how to use an EXIT statement Before After Address Data Address Data IP 0050 IP 0043 Address Data Address Data PC 0110 50 PCLold 60 51 0022 22 0020 201 IPH 00 211 IPL 150 22 Data 140 Stack Stack 6 42 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 INSTRUCTION SET IDLE Operation IDLE Operation See description The IDLE instruction stops the CPU clock while allowing the system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 1 4 6F Example The instruction IDLE stops the CPU clock but it does not stop the system clock ELECTRONICS 6 43 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 INC Increment INC Operation Flags Format Examples dst dst lt dst 1 The contents of the destination operand are incremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles
155. and value 12H leaving the value 02H in the register R1 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET BAND _ Bit AND BAND BAND Operation Flags Format Examples dst src b dst b src 4610 lt 4810 AND src b or dst b lt dst b AND 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or the source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst b 0 src 3 6 67 Rb src 1 dst 3 6 67 Rb NOTE In the second byte of the 3 byte instruction formats the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bitin length Given R1 07H and register 01H 05H BAND R1 01H 1 gt R1 06H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example the source register 01H contains the value 05H 00000101B and the destination working register R1 contains 07H 00000111B The statement BAND R1 01H 1 ANDS the bit 1 value of the source register 0 with the bit 0 value of the register R1 destination leaving the value 06H
156. ansmit interrupt Enable Transmit Interrupt NOTES 1 In mode 2 if the MCE UARTCON 5 bit is set to 1 then the receive interrupt will not be activated if the received gth data bit is 0 In mode 1 if 1 then the receive interrupt will not be activated if a valid stop bit was not received In mode 0 the MCE UARTCON 5 bit should be 0 2 descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit 3 Parity enable bits PEN are located in the UARTPND register at address F4H bank 0 4 Parity enable and parity error check can be available 9 bit UART mode Mode 2 only 4 36 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 CONTROL REGISTER UARTPND Pending and parity control F4H Set1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W 7 6 Not used for the 53084 5 84 5 keep always 0 5 UART parity enable disable PEN 4 UART receive parity error RPE 3 2 Not used for the S38C84H5X F84H5X must keep always 0 1 UART receive interrupt pending flag 0 Not pending ES Clear pending bit when write Interrupt pending 0 UART transmit interrupt pending flag EJ Not pending ES Clear pending bit when write Interrupt pending NOTES 1 In order to clear a data transmit or receive interrupt pending flag you must write a O to the appropriate pending bit 2 To avoid programming
157. any interrupt requests that may be issued are not recognized by the CPU ELECTRONICS 4 CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 IPH instruction Pointer High Byte DAH Set 1 RESET VALUE X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address IP 15 IP8 The lower byte of the IP address is located the IPL register DBH IPL instruction Pointer Low Byte DBH Set 1 RESET VALUE X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address 7 4 The upper byte of the IP address is located in the IPH register DAH 4 10 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 CONTROL REGISTER IPR Interrupt Priority Register FFH Set1 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 and 1 Priority Control Bits for Interrupt Groups A B and C Group priority undefined 6 Interrupt Subgroup C Priority Control Bit IRQ6 gt IRQ7 IRQ7 gt IRQ6 Be 5 Interrupt Group C Priority Control Bit IRQ5 gt IRQ6 IRQ7 1
158. ard is operated as target CPU with Emulator SK 1200 OPENIce 1 500 peye 8419 8 84 5 222 9 hoe 658 In Circuit Emulator Pye 1200 1 500 80 JP10 CO 8008 0 J101 J102 atatia 9 42SDIP 44 1 160 150 apy 5 140 L 1 19 C16 10 001 100 Connector 90 100110120 swi 15 JP1 1234 SMDs2 SMDS2 Figure 22 2 S3F84H5X Target Board Configuration ELECTRONICS 22 3 DEVELOPMENT TOOLS S3C84H5X F84H5X_UM_REV 1 10 Table 22 1 Components of TB84H5 Symbols Usage Description CN1 100 pin connector Connection between emulator and TB84H5 target board J101 J102 50 pin connector Connection between target board and user application system RESET Push button Generation low active reset signal to S3F84H5X EVA chip VCC GND POWER connector External power connector for TB84H5 IDLE STOP LED STOP IDLE Display Indicate the status of STOP or IDLE of SSF84H5X EVA chip on TB84H5 target board Table 22 2 Power Selection Settings for TB84H5 To User Vcc Settings Operating Mode To User VoD SMDS2 or SK 1200 supplies Vpp to the target board ff 9 evaluation chip and the target system To User VoD SMDS2 or SK 1200 supplies Vpp only to the target board Of
159. area of the internal 16 Kbyte ROM see Figure 5 3 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H 16 Kbyte 0100H 4 RESET Address FFH Interrupt Vector address Area Figure 5 3 ROM Vector Address Area ELECTRONICS 5 5 INTERRUPT STRUCTURE S3C84H5X F84H5X UM REV 1 10 Table 5 1 Interrupt Vectors Vector Address Request Reset Clear Value Value Level Level xp may 3 zo oo 9 28 DAH 7V 26 ias V m4 De Wacmemenp ma v ma b ia v zo m DM S me Pooma o v mo mmea e WmeAmaheaue f 9 1o BM io NOTES 1 Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so on 2 If two or more interrupts within the same level contend the interrupt with the lowest vector address usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware
160. ared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 A2 r r 6 r Ir opc src dst 3 6 A4 R R 6 5 R IR opc dst src 3 6 AG R IM 1 Given R1 02H and R2 03H CP R1 R2 gt Set the C and S flags The destination working register R1 contains the value 02H and the source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative the C and the S flag values are 1 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example the destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in the working register R3 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET Compare Increment and Jump on Equal Operation Flags Format Example dst src RA If dst src 0 PC lt PC relr 1 The source operand is compared to subtracted from the destination operand If the result is 0 the relative address is added to the program counter and control
161. atement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed 6 86 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 Logical Exclusive OR XOR Operation Flags Format Examples dst src dst lt dst XOR src INSTRUCTION SET The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in 1 bit being stored whenever the corresponding bits in the operands are different Otherwise a bit is stored C Unaffected Z Setif the result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Bytes Cycles Opcode Hex dst src 2 4 B2 6 B3 src dst 3 6 B4 5 dst src 3 6 Addr Mode dst src r r r Ir R R R IR R IM Given RO OC7H R1 02H R2 18H register 00H 2BH register 01H 02H register 02H 23H XOR XOR XOR XOR XOR RO R1 RO R1 00H 01H 00H 01H 00H 54H RO OC5H R1 02H RO OE4H R1 02H register 02H 23H Register 29H register 01H 02H Register OOH 08H register 01H 02H register 02H 23H Register OOH 7FH In the
162. ble Disble Selection Bit fol x Interrupt Disable ERE Interrupt Enable Falling edge EX Interrupt Enable Rising edge 4 18 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 CONTROL REGISTER P2CONH Port 2 Control Register High Byte ECH Set1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 7 TxD Configration Bits Input mode 2011 Alternative function mode Not used 2 Push pull output mode Alternative function mode TxD output 5 4 P2 6 RxD Configration Bits Lo afo 3 2 P2 5 SCK Configration Bits o mumodeiSCKmu 0 1 Atematvetuncion mode Notused 7112 Push pull outpumode S 1 0 P2 4 SO Configration Bits fo Input mode 2011 Alternative function mode Not used Push pull output mode Alternative function mode SO output ELECTRONICS 4 19 CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 P2CONL Port 2 Control Register Low Byte EDH Set1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 3 AD7 SI Configration Bits Input mode 5 input Alternative function mode Not used 3 2 P2 1 PWM T1CAPO Configration Bits Fo
163. buzzer BZOUT signal output 1 0 2kHz buzzer BZOUT signal output 4 kHz buzzer BZOUT signal output WTCON 3 2 Set watch timer interrupt to 0 5 2011 Set watch timer interrupt to 0 25 10 Set watch timer interrupt 0 125 5 Set watch timer interrupt to 1 955 ms WTCON 1 Disable watch timer clear frequency dividing circuits Enable watch timer WTCON O Interrupt is not pending clear pending bit when write Interrupt is pending NOTE Main system clock frequency fx is assumed to be 9 8304 MHz 17 2 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 WATCH TIMER WATCH TIMER CIRCUIT DIAGRAM BUZZER Output BZOUT WTCON 4 WTINT fw 64 0 5 kHz WTCON 3 fw 32 1 kHz fw 16 2 kHz WTCON 2 fw 8 4 kHz Enable Disable Circuit Frequency Clock 7 Selector Dividing 32768 Hz Circuit 256 fx Main System Clock 9 8304MHz fxT Subsystem Clock 32768 Hz fw Watch timer Figure 17 1 Watch Timer Circuit Diagram ELECTRONICS 17 3 WATCH TIMER S3C84H5X F84H5X_UM_REV 1 10 PROGRAMMING TIP Using the Watch Timer INITIAL MAIN WT_INT ORG 0000h VECTOR OD6h WT_INT ORG 0100h DI LD 000100006 Enable IRQ3 interrupt LD SPH 11111111b Set stack area LD SPL 4OFFh LD BTCON 10100011b Disable Watch dog LD WTCON 11001110b 0 5 kHz buzzer 1 955ms duration interrupt Interrupt enable fxt 32 768Hz EI MAIN
164. c dst src 2 4 22 r r 6 23 r Ir opc src dst 3 6 24 R R 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 register 01H 21H register 02H register OAH SUB R1 R2 gt R1 R2 03H SUB R1 R2 gt R1 08H R2 03H SUB 01 02 Register 01H register 02H 03H SUB 01H 02H gt Register 01H 17H register 02H SUB 01H 90H gt Register 01H 91H C S and V 1 SUB 01H 65H gt Register 01H OBCH 1 0 In the first example if he working register R1 contains the value 12H and if the register R2 contains the value 03H the statement SUB R1 R2 subtracts the source value 03H from the destination value 12H and stores the result OFH in the destination register R1 6 82 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET SWAP Swap Nibbles SWAP Operation swapped Flags Format Examples dst dst 0 3 lt gt dst 4 7 The contents of the lower four bits and the upper four bits of the destination operand 7 43 0 C Undefined Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 FO R 4 F1 IR Given Register 00H register 02H 03H register 03 OA4H SWAP 00H gt Register OOH
165. control register byte PacoNL 235 o o o Location is not mapped 22 Port 3 control register byte PSCONL 239 ern o o jo o jo o j o 0 Location FOH F1H is not mapped UART pending regse o o o UART contolregster UARTCON o o v AD converter contol resister 26 Fm o o AD converter data 248 FH o o o o o AD brie ADDATAL 249 Fen o o oo Por 2 enable contol register o o o o Location is not mapped Location FCH is factory use only Basic timer counter register Brent 253 FDH 0 0 0 0 0 0 O O Location FEH is not mapped merui prory reger eR 5 55151555 ELECTRONICS 8 3 and POWER DOWN S3C84H5X F84H5X_UM_REV 1 10 Table 8 3 S3C84H5X F84H5X Set 1 Bank 1 Register values after RESET O e er Ret Deel nx 7 s 5 3 2 1 0 Timer A 1 interrupt pending TINTPND 224 o o o 0 0 0 0 Timer A control register TACON 25 E1H 0 0 0 oO T
166. cted LDC refers to program memory and LDE to data memory The assembler makes Irr or rr values an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 10 C3 r Irr Opc src dst 2 10 D3 Irr r opc dst src XS 3 12 E7 r XS rr opc src dst XS 3 12 F7 XS rr r opc dst src XL XL 4 14 A7 r XL rr opc src dst XL XL 4 14 B7 XL rr r dst 0000 DA 4 14 0000 DA 4 14 7 opc 4510001 DA DA 4 14 AT r DA opc 0001 DA DA 4 14 B7 DA r 1 The source src or the working register pair rr for formats 5 and 6 cannot use the register pair 0 1 2 Forthe formats 3 and 4 the destination XS rr and the source address XS rr are both one byte 3 Forthe formats 5 and 6 the destination XL rr and the source address XL rr are both two bytes 4 The and the source values for the formats 7 and 8 are used to address program memory The second set of values used in the formats 9 and 10 are used to address data memory 5 LDEinstruction can be used to read write the data of 64 Kbyte data memory 6 52 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 LDC LDE Load Memory LDC LDE Continued Examples Given RO 11H R1 INSTRUCTION SET 34H R2 01H R3 04H Program
167. d Figure Title Page Number Number 19 1 Pin Assignment 32 SOP SDIP 19 1 19 2 Pin Assignment 32 4 19 2 19 3 Pin Assignment 30 00 19 3 19 4 Pin Assignment 28 0222 1200 00 19 4 20 1 Input Timing for External Interrupts Ports 2 20 5 20 2 Input TIMING for RESET dob cai e pea eaa E res 20 5 20 3 Clock Timing Measurement at in caia 20 7 20 4 Stop Mode Release Timing initiated by 20 8 20 5 Stop Mode Main Release Timing Initiated by Interrupts 20 9 20 6 Stop Mode Sub Release Timing Initiated by 20 9 20 7 Waveform for UART Timing 20 10 20 8 Operating Voltage Range sse eene entente 20 12 20 9 The Circuit Diagram to Improve EFT 20 13 21 1 32 SOP 450A Package Dimensions 21 1 21 2 32 ELP 0505 Package 21 2 21 3 32 SDIP 400 Package Dimensions sse nene 21 3 21 4 30 Pin SDIP Package Dimensions
168. dressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support indexed addressing mode for internal program memory and for external data memory when implemented Register File RPO or RP1 Value used in points to Instruction OPERAND start of working register block Program Memory midi 4 Base Address Address wo Operan dsi src X gt INDEX Instruction Point to One of the Example Woking Register 1 of 8 Sample Instruction LD RO BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES S3C84H5X F84H5X UM REV 1 10 INDEXED ADDRESSING MODE Continued 3 8 Register File MSB Points to or RP1 RPO or RP1 Selected RP points to start of ki Program Memory 2 i NEXT 2 Bits 4 bit Wo
169. dst The specified bit within the source operand is tested If it is a O the relative address is added to the program counter and control passes to the statement whose address is currently in the program counter Otherwise the instruction following the BTJRF instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode note Hex dst src src 6 0 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRF SKIP R1 3 gt PC jumps to SKIP location If the working register R1 contains the value 07H 00000111 the statement BTJRF SKIP R1 3 tests bit 3 Because it is 0 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 BTJRT Test Jump Relative on True BTJRT Operation Flags Format Example dst src b If src b is 1 then lt PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC Otherwise the instruction following the BTJRT instruction is executed No flags a
170. dst b lt NOT dst b This instruction complements the specified bit within the destination without affecting any other bit in the destination C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc 48611010 2 4 57 rb NOTE the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITC R1 1 gt R1 05H If the working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101B in the register R1 Because the result of the complement is not the zero flag Z in the FLAGS register 0D5H is cleared ELECTRONICS 6 19 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 BITR Bit Reset BITR Operation Flags Format Example dst b dst b lt 0 The BITR instruction clears the specified bit within the destination without affecting any other bit in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst b 0 2 4 77 rb NOTE the second byte of the instruction format the destination address is four bits the bit address 0 is three bits and the LSB address value is one bit in length Given R1 07H BITR R1 1
171. e RAM A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the register file The S8C84H5X F84H5X has an internal 16 Kbyte mask programmable ROM 16 Kbyte Flash ROM and 272 byte RAM ELECTRONICS 2 1 ADDRESS SPACES S3C84H5X F84H5X_UM_REV 1 10 PROGRAM MEMORY ROM Program memory ROM stores program codes or table data The 53084 5 84 5 has 16 Kbytes of internal mask programmable program memory The program memory address range is therefore OH 3FFFH see Figure 2 1 The first 256 bytes of the ROM OH OFFH are reserved for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you use the vector address area to store a program code be careful not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H Decimal 16 383 Internal Program S3F84H5X 16Kbyte Memory Figure 2 1 Program Memory Address Space 2 2 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESS SPACES Smart Option Smart option is the ROM option for starting condition of the chip The ROM addresses used by smart option are from 003CH to The default value of ROM is ROM Address 003CH MSB Not used ROM Address 003DH MSB Not used ROM Address 003EH MSB Not used ROM Address 003FH
172. e appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed ELECTRONICS 5 3 INTERRUPT STRUCTURE S3C84H5X F84H5X UM REV 1 10 Levels Vectors Sources Reset Clear BEH IRQO Timer B underflow Timer match capture H W S W IRQ1 C2H Timer A overflow S W Timer 1 0 match capture H W S W C6H Timer 1 0 overflow H W S W C8H Timer 1 1 match capture H W S W CAH Timer 1 1 overflow H W S W CEH P1 0 external interrupt S W DOH P1 1 external interrupt S W D2H P1 2 external interrupt S W D4H P1 3 external interrupt S W D6H Watch timer S W D8H SIO receive transmit S W DAH PWM overflow interrupt S W DCH UART data receive S W DEH UART data transmit S W NOTES 1 Within a given interrupt level the lower vector address has high priority For example DCH has higher priority than DEH within the level IRQ5 the priorities within each level are set at the factory External interrupts are triggered by a rising or falling edge depending on the corresponding control register setting Figure 5 2 S3C84H5X F84Hb5XInterrupt Structure 5 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INTERRUPT STRUCTURE INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the 53084 5 84 5 interrupt structure are stored in the vector address
173. e following conditions must be met Interrupt processing must be globally enabled El 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The PON CPU then initiates an interrupt machine cycle that completes the following processing sequence Reset clear to the interrupt enable bit in the SYM register 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC status flags setting SYM O to 1 It allows the CPU to process the next interrupt request ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INTERRUPT STRUCTURE GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM 00H FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence oN gt Push the program counter s lo
174. e highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 GroupA IRQO IRQ1 GroupB IRQ2 IRQ3 IRQ4 GroupC IRQ5 IRQ6 IRQ7 B21 B22 C21 IRQO IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B C A The setting 101B would select the relationship C gt B gt A The functions of the other IPR bit settings are as follows e PR 5controls the relative priorities of group C interrupts e Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C e PR 0O controls the relative priority setting of IRQO and IRQ1 interrupts 5 12 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INTERRUPT STRUCTURE Interrupt Priority Register IPR FFH Set 1 Bank 0 R W
175. e mode was entered There are two ways to release idle mode 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to 00B If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the CLKCON 4 and CLKCON 3 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt IRET occurs the instruction immediately following the one that initiated idle mode is executed 8 6 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 PORTS I O PORTS OVERVIEW The S8C84H5X F84H5X microcontroller has five bit programmable I O ports This gives a total of 22 I O pins Each port can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special instructions are required Table 9 1 gives you a general overview of the S3C84H5X F84Hb5X I O port functions Table 9 1 S3C84H5X F84H5X Port Configuration Overview Configuration Options Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up resistor Al
176. ears the UARTCON value to So if you want to use UART module you must write appropriate value to UARTCON ELECTRONICS S3C84H5X F84H5X UM REV 1 10 UART UART Control Register UARTCON F6H Set1 Bank 0 R W Reset Value yoo ps e s e e o Operating mode and Transmit interrupt enable bit baud rate selection bits 0 Disable see table below 1 Enable Multiprocessor communication 0 Received interrupt enable bit enable bit mode 2 only 0 Disable 0 Disable 1 Enable 1 Enable If parity disable mode PEN 0 Serial data receive enable bit location of the 9th data bit that was received in 0 Disable UART mode 2 0 or 1 1 Enable If parity enable mode PEN 1 i parity ranle moade PEN 0 Even odd parity 2 bit location of the 9th data bit to be transmitted in UART mode 2 0 Even parity check for the received data If parity enable mode PEN 1 1 Odd parity check for the received data Even odd parity selection bit for transmit data in UART mode 2 0 Even parity bit generation for transmit data 1 Odd parity bit generation for transmit data 2 MS1 MSO Mode Description Baud Rate 0 Shiftregister fxx 16 x 16bit BRDATA 1 1 8 bit UART 16 x 16bit BRDATA 1 2 S9 bitUART fxx 16 x 16bit BRDATA 1 NOTES 1 In mode 2 if the UARTCON 5 bit is set to 1 then the receive interrupt will not be act
177. ed bit of the destination No other bits of the destination are affected The source is unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 48651010 src 3 6 47 Rb opc src b 1 dst 3 6 47 Rb NOTE In the second byte of the instruction format the destination the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given RO 06H and general register 05H LDB R0 00H 2 gt RO LDB 00H 0 RO gt RO 07H register 05H 06H register 04H In the first example the destination working register RO contains the value 06H and the source general register the value 05H The statement LD 2 loads the bit two value of the register into bit zero of the RO register leaving the value 07H in the register RO In the second example is the destination register The statement LD 00H 0 RO0 loads bit zero of the register RO to the specified bit bit zero of the destination register leaving 04H in the general register ELECTRONICS 6 51 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 LDC LDE Load Memory LDC LDE Operation Flags Format 1 2 3 4 5 6 T 8 9 10 NOTES dst src dst src dst lt src This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffe
178. egister Full Register Name Page Identifier Number ADCON A D Converter Control 2 4404 0 4 5 BTCON Basic Timer Control 22200440 4 6 System Clock Control Register 2 04 4 0 0 4 7 FLAGS System Flags Register i rte ee rea dot ea OR ties 4 8 IMR Interrupt Mask Register sorina oiiaii nennen 4 9 IPH Instruction Pointer High 4 10 IPL Instruction Pointer Low nennen 4 10 IPR Interrupt Priority Register 4 11 Interrupt Request 4 12 OSCCON Oscillator Control Register 4 13 Port 0 Control Register High 4 14 Port 1 Control Register High 4 15 P1CONL Port 1 Control Register Low 44 0000 4 16 P1INTPND Port 1 Interrupt Pending 4 17 Port 1 Interrupt Enable 11er cede eee a eee dede 4 18 P2CONH Port 2 Control Register High 4 19 P2CONL Port 2 Control Register Low Byte 4 20 P2PUR Port 2 Pull up Resistor Control
179. ent consumption of LVR circuit Except the case that LVR is disabled Ipps is the same regardless of LVR on or LVR off oof ONS 20 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ELECTRICAL DATA Table 20 4 A C Electrical Characteristics TA 25 C to 85 C 2 5V to Symbol Conditions Interrupt Input tinTH 5 High Low Width Ports 2 RESETB Input Input Low Width NOTE User must keep more large value then min value Figure 20 1 Input Timing for External Interrupts Ports 2 Figure 20 2 Input Timing for RESET ELECTRONICS 20 5 ELECTRICAL DATA S3C84H5X F84H5X_UM_REV 1 10 Table 20 5 Main Oscillator Frequency fosc1 TA 25 C 85 C 2 5V to 5 5 V Osciator Clock Test Condition min Max Unit 1 10 MHz Main Crystal or Vpp 2 5V to 5 5 V External Clock Main System Table 20 6 Main Oscillator Clock Stabilization Time TA 25 C 85 2 5V to 5 5 V Main Crystal fosc gt 400 kHz Main Ceramic Oscillation stabilization occurs when Vpp is equal to the minimum oscillator voltage range External Clock input High and Low width Main System Oscillator lWAIT when released by 000000 released a reset 1 T Stabilization NOTES 1 fosc is the oscillator frequency 2 The d
180. es Instruction Execution Time 400 ns at 10 MHz fosc minimum Interrupts e 16 interrupt sources with 16 vectors e 8 level 16 vector interrupt structure Ports e Total 22 bit programmable pins 32 SOP SDIP ELP Total 20 bit programmable pins 30 SDIP Total 18 bit programmable pins 28SOP Timers and Timer Counters e programmable 8 bit basic timer BT for oscillation stabilization control or watchdog timer function e 8 bit timer counter Timer A with three operating modes Interval mode capture mode and PWM mode 8 bit timer Timer B with carrier frequency or PWM generator e Two 16 bit timer counter Timer 10 11 with three operating modes Interval mode Capture mode and PWM mode Watch Timer e Real time and interval time measurement e Four frequency output to pin S3C84H5X F84H5X UM REV 1 10 A D Converter e 10 bit resolution e _Ejight analog input channels e 20 conversion speed at 10MHz clock Asynchronous UART e One Asynchronous UART Programmable baud rate generator Supports serial data transmit receive operations with 8 bit 9 bit in UART PWM Module 10 bit programmable PWM output Serial I O e One synchronous serial module e Selectable transmit and receive rates Built in RESET Circuit LVR e Low Voltage check to make system reset Vive 2 8V smart option Oscillation Frequency e 1MHz to 10MHz extern
181. et but after an ADD instruction Z would probably be used Following a CP instruction you would probably want to use the instruction EQ 2 For operations using unsigned numbers the special condition codes UGE ULT UGT and ULE must be used 6 12 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This Chapter contains detailed information and programming examples for each instruction in the S3C8 series instruction set Information is arranged in a consistent format for improved readability and for quick reference The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Flag settings that may be affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS 6 13 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 ADC with Carry ADC dst src Operation dst lt dst src c The source operand along with the carry flag setting is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction lets the carry value from
182. et Register 6 80 STOP Stop cte e d e ardet Hebe duet 6 81 SUB REPRE 6 82 SWAP Swap Nibbles ic itd 6 83 TCM Test Complement under Mask cccccececeeeeeeeeceeseeceeeeeaaeeeeaaeseeeeeeeaeeesaeeeseneeeeaees 6 84 Test nder 6 85 WFI Wate Tor 6 86 XOR Logical Exclusive 6 87 xxii S3C84H5X F84H5X_UM_REV 1 10 MICROCONTROLLER S3C84H5X F84H5X_UM_REV 1 10 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 SERIES MICROCONTROLLERS Samsung s S3C8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes The major CPU features are e Efficient register oriented architecture e Selectable CPU clock sources e Idle and Stop power down mode released by interrupt or reset e Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum of four CPU clocks can be assigned to specific interrupt levels S3C84H5X F84H5X MICROCONTROLLER The S8C84H5X F84H5X single chip CMOS microcontrollers are fabricated using the highly advanced CMOS process
183. f n evaluation chip The target system must have a power supply of its own SMDS2 or SK 1200 IDLE LED This LED is ON when the evaluation chip 53 8410 is in idle mode STOP LED This LED is ON when the evaluation chip 53 8410 is in stop mode 22 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 DEVELOPMENT TOOLS 00 0 1 2 7 NOTE Smart option is determined DIP switch Figure 22 3 DIP Switch for Smart Option Address Switch Function 3EH 0 Not used Not used 1 Not used Not used 2 Not used Not used ON LVR disable 3FH 7 OFF LVR enable Table 22 3 Clock Source Selection Setting JP10 When to use the external clock from socket Y2 When to use the internal clock from an emulator ELECTRONICS 22 5 DEVELOPMENT TOOLS S3C84H5X F84H5X_UM_REV 1 10 Table 22 4 PWM Enable Disable Setting Jumper Setting Description mmo PWM is disabled during no run JP1 ee PWM is always enabled whether run or not 1 0 INT1 BUZ TACK P1 1 INT2 TACAP P1 2 1 3 VDD VSS XOUT XIN TEST Xtin Xtout nRESET TBPWMY T1CKO P2 0 T1CAPO PWM P2 1 T1OUTO AD4 P2 2 AD5 T1CK1 P1 4 P3 0 T1CAP1 AD6 P1 5 P0 3 AD3 SI AD7 P2 3 P0 2 AD2 SO P2 4 P0 1 AD1 SCK P2 5 P0 0 ADO Rx P2 6 Avss TX P2 7 Avref Not used Not used Not used Not used Not used Not used No
184. first example if the working register RO contains the value 7 and if the register R1 contains the value 02H the statement RO R1 logically exclusive ORs the R1 value with the RO value and stores the result 0C5H in the destination register RO ELECTRONICS 6 87 S3C84H5X F84H5X_UM_REV 1 10 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The clock frequency generated for the Main clock of S3C84H5X F84H5X by an external crystal can range from 1 MHz to 10 MHz The maximum CPU clock frequency is 10 MHz The and pins connect the external oscillator or clock source to the on chip clock circuit Also the subsystem clock frequency for the Watch timer by an external crystal can range from 30kHz to 35kHz The XTn and XT o1 pins connect the external oscillator or clock source to the on chip clock circuit SYSTEM CLOCK CIRCUIT The system clock circuit has the following components e External crystal or ceramic resonator oscillation source or an external clock source e Oscillator stop and wake up functions e Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 e System clock control register CLKCON e Oscillator control register OSCCON and STOP control register STPCON XIN XTIN S3C84H5X 53 84 5 53 84 5 S3F84H5X Xour XTOUT 32 768 kHz Figure 7 1 Main Oscillator Circuit Figure 7 2 Sub System Oscillator Circuit Crystal or Ceramic Oscillator Crystal Oscillator ELECTRONICS
185. flag BA Fast interrupt status flag FS Carry flag C _ Zero flag 2 Sign flag S Half carry flag H Overflow flag V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET FLAG DESCRIPTIONS FIS BA Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations have been performed it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero In operations that test register bits and in shift and rotate operations the Z flag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is cleared to after a logic operation has been performed Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD opera
186. flow fxx 256 gt TBUF TBCON 1 Repeat Control TBCON 3 TBCON 4 5 Timer B Data Timer B Data Low Byte Register High Byte Register Data Bus Data Bus NOTE Incase of setting TBCON 5 4 at 10 the value of the TBDATAL register is loaded into the 8 bit counter when the operation of the timer B starts And then if a underflow occurs in the counter the value of the TBDATAH register is loaded into the value of the 8 bit counter However if the next borrow occurs the value of the TBDATAL register is loaded into the value of the 8 bit counter To output TBPWM as carrier wave you have to set P4CONL 7 6 as 11 Figure 11 3 Timer B Functional Block Diagram ELECTRONICS 11 5 8 S3C84H5X F84H5X_UM_REV 1 10 TIMER B CONTROL REGISTER TBCON Timer B Control Register TBCON DOH Set 1 Bank 0 R W Timer input clock selection bit Timer B output flip flop 00 fxx 4 control bit 01 fxx 8 0 T FF is low 10 fxx 64 1 T FF is high 11 fxx 256 Timer B mode selection bit Timer B interrupt time selection bit 0 One shot mode 00 Elapsed time for low data value 1 Repeating mode 01 Elapsed time for high data value 10 Elapsed time for low and high data value Timer start stop bit 11 Invaild setting 0 Stop timer B 1 Start timer B Timer B interrupt enable bit 0 Disable interrupt 1 Enable interrupt Figure 11 4 Timer B Control Register TBCON
187. g a 1 to BTCON 1 To clear the frequency dividers write a 1 to BTCON O ELECTRONICS 10 1 BASIC TIMER S3C84H5X F84H5X_UM_REV 1 10 Basic Timer Control Register BTCON D3H Set 1 R W e e s Watchdog timer enable bit Divider clear bit 1010B Disable watchdog function 0 No effect Other value Enable watchdog function 1 Clear divider Basic timer counter clear bit 0 No effect 1 Clear BTCNT Basic timer input clock selection bit 00 fxx 4096 01 fxx 1024 10 fxx 128 11 fxx 1 Not used Figure 10 1 Basic Timer Control Register BTCON 10 2 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by setting BTCON 7 BTCON 4 to any value other than 1010 1010B value disables the watchdog function A reset clears BTCON to automatically enabling the watchdog timer function A reset also selects the CPU clock as determined by the current CLKCON register setting divided by 4096 as the BT clock The CPU is reset whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occurring To do this the BTCNT value must be cleared by writing a 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise
188. generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first bit conversion is always 1 2 AVper CONVERSION TIMING The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to step up A D conversion Therefore total of 50 clocks is required to complete a 10 bit conversion With a 10 MHz CPU clock frequency one clock cycle is 400 ns 4 fxx If each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bits step up time 10 clock 50 clocks 50 clock x 400 ns 20 us at 10 MHz 1 clock time 4 fxx ADCON O 1 b 50 Clock i Conversion Start 0000000000 Valid Data Previous ADDATAH 8 Bit ADDATAL 2 Bit Value 16 Set time 10 clock 40 Clock Figure 16 4 A D Converter Timing Diagram 16 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 A D CONVERTER INTERNAL A D CONVERSION PROCEDURE 1 2 Analog input must remain between the voltage range of and AVper Configure P0 0 P0 3 P1 4 P1 5 P2 2 P2 3 for analog input before A D conversions To do this you load the appropriate value to the POCONL P1CONH and 2 for ADCO ADC7 registers Before the conversion operation starts you must first select one of the eight input pins ADCO ADC7 writing the appropria
189. gister Name Mnemonic Decimal Re 24 w Imempreesngse ma rR Register page poime mw ELECTRONICS 4 1 CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 Table 4 2 Set 1 Bank 0 Registers Mnemonic Decimal RW Potiiemprconoregster RW Pon Zoona regter se RW Port 2 control register e ES P2CONL Location FOH F1H is not mapped Location F3H is not mapped converter data register High Byte ADDATAH AID converter data register Low Byte ADDATAL 249 R Location FBH is not mapped Basic imer counter regs Fo R Location FEH is not mapped 4 2 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 CONTROL REGISTER Table 4 3 Set 1 Bank 1 Registers Register Name Mnemonic Decimal Hex Timer A control register 225 Timer A data register 226 E2H Timer A counter register 227 E3H Timer 1 0 data register High Byte 228 E4H Timer data register Low Byte 229 Timer Tm control register 232 Timer 1 1 control register 233 Timer counter Fine oun rego Low ye n UART baud data register High Bye BRDATAH 2398 RW Location F6 F7H is not mapped ELECTRONICS 4 3 CONTROL REGISTERS Bit number s that is
190. gister pair or indirect working or reg reg 0 254 even only register pair where p 0 2 14 X Indexed addressing mode reg Rn reg 0 255 n 0 15 XS Indexed short offset addressing mode addr RRp addr range 128 to 127 where p 0 2 14 XL Indexed long offset addressing mode addr RRp addr range 0 65535 where 2 14 DA Direct addressing mode addr addr range 0 65535 RA Relative addressing mode addr addr a number from 127 to 128 that is an offset relative to the address of the next instruction IM Immediate addressing mode data data 0 255 IML Immediate long addressing mode data data 0 65535 ELECTRONICS 6 9 INSTRUCTION SET Table 6 5 OPCODE Quick Reference S3C84H5X F84H5X_UM_REV 1 10 OPCODE MAP LOWER NIBBLE HEX 0 1 2 3 4 5 6 7 U 0 DEC DEC ADD ADD ADD ADD ADD BOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb P 1 RLC RLC ADC ADC ADC ADC ADC BCP R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b R2 P 2 INC INC SUB SUB SUB SUB SUB BXOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb E 3 JP SRP 0 1 SBC SBC SBC SBC SBC BTJR IRR1 IM r1 r2 r1 Ir2 R2 R1 IR2 R1 r2 b RA R 4 DA DA OR OR OR OR OR LDB R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb 5 POP POP AND AND AND AND AND BITC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b N 6 COM COM TCM TCM TCM TCM TCM BAND R1 IR1 r1
191. hat is the settings before the interrupt occurred IRET Bytes Cycles Opcode Normal Hex opc 1 12 BF IRET Bytes Cycles Opcode Fast Hex opc 1 6 BF In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupt are enabled When an interrupt occurs the program counter and the instruction pointer are swapped This causes the PC to jump to the address 100H and the IP to keep the return address The last instruction in the service routine is normally a jump to IRET at the address FFH This loads the instruction pointer with 100H again and causes the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H OH FFH 100H Interrupt Service Routine JP to FFH FFFFH In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last tow instruction The IRET cannot be immediately proceeded by an instruction which clears the interrupt status as with a reset of the IPR register ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET JP Jump JP cc dst Conditional JP dst Unconditional Operation If cc is true lt dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP ins
192. hat the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 13 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address The three low order bits of the complete address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 3 1 selects RP1 and the five high order bits in 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address 10101011 Selects RPO or RP1 Address These address 1 working register address addressing Register pointer Three low order bits provides five high order bits 4 4111 8 bit physical address Figure 2 14 8 Bit Working Register Addressing 2 18 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESS SPACES RPO Selects RP1 R11 8 bit address Register 110011011 form instruction address LD R11 Specifies working register addressing
193. he instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory Next Instruction LSB Must be Zero uen urren Instruction gt OPCODE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESSING MODES RELATIVE ADDRESS MODE RA In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT D
194. he three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 12 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC is 0 which selects RPO The five high order bits stored RPO 01110B concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B 2 16 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESS SPACES Selects RPO or RP1 Address OPCODE _ 4 4 4 bit address Register pointer provides three provides five low order bits high order bits Together they create 8 bit register address Figure 2 12 4 Bit Working Register Addressing RPO RP1 Selects RPO R6 OPCODE Register Instructi 01110 address 0110 1110 76 Figure 2 13 4 Bit Working Register Addressing Example ELECTRONICS 2 17 ADDRESS SPACES S3C84H5X F84H5X_UM_REV 1 10 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100B This 4 bit value 1100B indicates t
195. i ad 22 1 Programming Socket 22 1 IDEE LED Le edt ceti etre 22 4 SOP ELTE 22 4 OTP MTP Programmer 2 ener enne ennt 56 22 9 S3C84H5X F84H5X UM REV 1 10 MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 S3C84H5X F84H5X Block Diagram sse 1 3 1 2 S3C84H5X F84H5X Pin Assignment 32 SOP SDIP sess 1 4 1 3 S3C84H5X F84H5X Pin Assignment 32 pin 1 5 1 4 S3C84H5X F84H5X Pin Assignment 30 pin SDIP 1 6 1 5 S3C84H5X F84H5X Pin Assignment 28 pin 1 7 1 6 Pin Circuit Type B nRESET 1 12 1 7 Pin Circuit Type eee ege heeds dde naive Hare de nd 1 12 1 8 Circuit 1 13 1 9 Pin Circuit Type D 5 1 0 1 3 nennen nens 1 13 1 10 Pin Circuit Type 2 2 3 1 4 1 5 1 14 1 11 Pin Circuit Type G 3 0 3 4 nnne 1 15 2 1 Program Memory Address 2 2 2 2 SMart ODptlon oue m fo tef iod o Pee ee 2 3 2 3 Internal Register File Organization 2 5 2 4 Register Page Pointer nennen nen
196. ic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONICS 6 3 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src Bit XOR TCM dst src Test complement under mask dst src Test under mask 6 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Mnemonic Operands Instruction Rotate and Shift Instructions RL dst Rotate left RLC dst Rotate left through carry RR dst Rotate right RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nibbles CPU Control Instructions CCF Complement carry flag Dis
197. icense under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3C84H5X F84H5X 8 Bit CMOS Microcontrollers User s Manual Revision 1 10 Publication Number 02 1 10 S3 C84H5X F84H5X 072007 Copyright 2006 2007 Samsung Electronics Co Ltd Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirec
198. imer A counter register 227 ESH 0 jo o o 0 0 0 0 Timer 1 0 control register 292 EBH o o o o 0 0 0 Timer 1 1 control register 233 E9H 0 Timer 1 0 counter register high byte TICNTHO 234 EAH 0 0 0 0 0 0 010 Timer 1 0 counter register low byte TICNTLO 235 o o 0 0 0 0 Timer 1 1 counter register high byte TICNTH1 236 o o o o o 0 0 Timer 1 1 counter register low byte 237 EDH 0 O O JO UART baud rate data register low 1 1 1 1 1 1 1 1 SIO pre scalar register SIOPS 240 FOH 0 0 0 0 0 0 0 SIO data register SIODATA 241 FIH O oO o Serial control register SIOCON 242 F2H 0 0 0 0 PWM data register High PWMDATAH 243 FH 0 0 O JO PWM data register LOW PWMDATAL 244 o 0 0 0 PWM control register PWMCON 245 FSH 0 0 0 o Location F6H F7H is not mapped Watoh timer control register WTCON 248 0 0 0 o 0 Location F9H FFH are not mapped 8 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 RESET and POWER DOWN POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operat
199. in Each data frame has three components e Start bit 0 e 8 data bits LSB first e Stop bit 1 When receiving the stop bit is written to the RB8 bit in the UARTCON register The baud rate for mode 1 is variable Mode 1 Transmit Procedure 1 Select the baud rate generated by 16bit BRDATA 2 Select mode 1 8 bit UART by setting UARTCON bits 7 and 6 to 01 3 Write transmission data to the shift register UDATA F5H The start and stop bits are generated automatically by hardware Mode 1 Receive Procedure 1 Select the baud rate to be generated by 16bit BRDATA 2 Select mode 1 and set the RE Receive Enable bit in the UARTCON register to 1 3 The start bit low 0 condition at the RxD P1 4 pin will cause the UART module to start the serial data receive operation 7 1 11071 Write to Shift Register UDATA 1 wo Transmit TIP id B0 A TO RIP Figure 15 7 Timing Diagram for UART Mode 1 Operation 15 10 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 UART UART MODE 2 FUNCTION DESCRIPTION In mode 2 11 bits are transmitted through the TxD pin or received through the RxD pin Each data frame has four components e Start bit 0 e 8 data bits LSB first e Programmable 9th data bit or parity bit e Stop bit 1 lt In parity disable mode PEN 0 gt The 9th data bit to be transmitted can
200. inter SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least significant byte SP7 SPO is stored in the SPL register After a reset the SP value is undetermined Because only internal memory space is implemented in the S3C84H5X F84Hb5X the SPL must be initialized to an 8 bit value in the range 00H FFH The SPH register must be initialized to OFFH at the initial part of the program When the SPL register contains the only stack pointer value that is when it points to a system stack in the register file you can use the SPH register as a general purpose data register However if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations the value in the SPL register will overflow or underflow to the SPH register overwriting any other data that is currently stored there To avoid overwriting data in the SPH register you can initialize the SPL value to FFH instead of 00H 2 20 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESS SPACES PROGRAMMING TIP Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD SPH 0FFH You must initialize SPH to OFFH LD SPL 0FFH SPL lt Normally the SPL is set t
201. into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR opc dst 2 14 D4 IA Given 35H R1 21H 1A47H SP 0002H CALL 3521H gt SP 0000H Memory locations OOOOH 0001 4AH where 4AH is the address that follows the instruction CALL RRO gt SP 0000 0000 1AH 0001H 49H CALL 40H gt SP 0000H 0000H 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to the memory location OOOOH The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and the stack pointer are the same as in the first example the statement CALL RRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and the stack pointer are the same as in the first example if the program address 0040H contains 35H and the program address 0041H contains 21H the statement CALL 40H produces the
202. ion of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current is reduced to less than 3 except for the current consumption of LVR Low voltage Reset circuit All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset or by interrupts NOTE Do not use stop mode if you are using an external clock source because Xy input must be restricted internally to Vgg to reduce current leakage Using RESET to Release Stop Mode Stop mode is released when the RESET signal is released and returns to high level all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained A reset operation automatically selects a slow clock 1 16 because CLKCON 3 and CLKCON 4 are cleared to 00 After the programmed oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H and 0101H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the SSC84H5X F84H5X interrupt structure that can be u
203. ion provides the operand s 16 bit memory address Jump JP and CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Used Upper Address Byte Lower Address Byte or 1 lt _ LSB Selects Program OPCODE Memory or Data Memory Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H ldentical operation to LDC example except that external program memory is accessed Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS 3 11 ADDRESSING MODES S3C84H5X F84H5X UM REV 1 10 INDIRECT ADDRESS MODE IA In Indirect Address IA mode t
204. is waiting When the CPU acknowledges the interrupt request application software must the clear the pending condition by writing 0 to the corresponding P1INTPND1 bit 9 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 PORTS Port 1 Control Register High Byte P1 CONH E8H Set1 R W Reset value 00 7 4 Not used must keep always 0 3 2 P1 5 T1CAP1 AD6 Configuration Bits 0 0 Input mode T1CAP1 input 0 1 Input mode with pull up T1 CAP1 input 10 Push pull output mode 1 1 Alternative function mode AD6 1 0 P1 4 T1CK1 AD5 Configuration Bits 0 0 2 Input mode T1CK1 input 0 1 Input mode with pull up T1CK1 input 1 0 Push pull output mode 1 1 Alternative function mode AD5 Figure 9 2 Port 1 High Byte Control Register PI CONH ELECTRONICS 9 5 9 6 PORTS S3C84H5X F84H5X_UM_REV 1 10 Port 1 Control Register Low Byte P1CONL Seti R W Reset value 00H 7 6 P1 3 T1OUT1 INT3 Configuration Bits 0 0 Input mode Interrupt input 0 1 Input mode with pull up Interrupt input 1 0 Push pull output mode 1 1 Alternative function mode T1OUT1 output 5 4 P1 2 TACAP INT2 Configuration Bits 0 0 Input mode Interrupt input INT2 TACAP 01 Input mode with pull up Interrupt input INT2 TACAP 1 0 Push pull output mode 1 1 Alternative function mode Not used 3 2 P1 1 TACK BUZ INT1 Co
205. ise V Set if arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise Always set to 1 T Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 32 r r 6 33 r Ir opc src dst 3 6 34 R R 6 35 R IR opc dst src 3 6 36 R IM Given R1 10H R2 C 1 register 01H 20H register 02H and register 03H OAH SBC R1 R2 gt R1 OCH R2 03H SBC R1 R2 gt R1 05H R2 register OAH SBC 01 02 gt Register 01H 1CH register 02H 03H SBC 01H Q02H gt Register 01H 15H register 02H 03H register 58 01H 8AH gt Register 01H 95H C S and V 1 In the first example if the working register R1 contains the value 10H and the register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in the register R1 ELECTRONICS 6 77 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 SCF set Carry Flag SCF Operation C lt 1 The carry flag C is set to logic one regardless of its previous value Flags Setto 1 No other flags are affected Forma
206. it counter is cleared and it also is cleared automatically Figure 11 1 Timer A Control Register TACON ELECTRONICS 11 3 8 S3C84H5X F84H5X_UM_REV 1 10 BLOCK DIAGRAM TACON 2 Overflow 7 6 Data Bus TACON O f xx 1024 10 256 gt 8 bit Up Counter fxx 64 Read Only 8 bit Comparator a TACK TINTPND O M TAOUT TAPWM U M TACON 5 4 Timer A Data Register TACON 5 4 Read Write Data Bus NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bit is located at TINTPND register Figure 11 2 Timer A Functional Block Diagram 11 4 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 8 BIT TIMER A B 8 BIT TIMER B OVERVIEW The S3C84H5X F84H5X micro controller has an 8 bit timer called timer B Timer B which can be used to generate the carrier frequency of a remote controller signal Also it can be used as the programmable buzz signal generator that makes a sound with a various frequency from 200Hz to 20kHz These various frequencies can be used to generate a melody sound Timer B has two functions Asanormal interval timer generating a timer B interrupt at programmed time intervals e To generate a programmable carrier pulse for a remote control signal at P2 0 BLOCK DIAGRAM TBCON 6 7 TBCON 2 PG trigger signal 0 4 f xx 8 gt CLK 8 Bit TBPWM P2 0 64 9 Down Counter Je Under
207. ite R W R W R W R W R W R W R W R W 7 6 Operating mode baud rate selection bits 0 Mode 0 Shift Register fxx 16 16bit BRDATA 1 1 Mode 1 8 bit UART fxx 16 16bit BRDATA 1 Mode 2 9 bit UART fxx 16 16bit BRDATA 1 5 Multiprocessor communication enable bit for mode 2 only 0 Disable 1 Enable 4 Serial data receive enable bit opm 0 3 If Parity disable mode PEN 0 location of the 9 data bit to be transmitted UART mode 2 0 1 If Parity enable mode PEN 1 even odd parity selection bit for transmit data in UART mode 2 0 Even parity bit generation for transmit data 1 Odd parity bit generation for transmit data 2 If Parity disable PEN 0 location of the 97 data bit that was received in UART mode 2 1 If Parity enable mode PEN 1 even odd parity selection bit for receive data in UART mode 2 0 Even parity check for the received data 1 Odd parity check for the received data A result of parity error will be saved in RPE bit of the UARTPND register after parity checking of the received data ELECTRONICS 4 35 CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 UARTCON UART Control Register Continued F6H Set1 Bit Identifier RESET Value Read Write 1 Receive interrupt enable bit lo Disable Receive interrupt Enable Receive interrupt 0 Transmit interrupt enable bit Disable Tr
208. ivated if the received 9th data bit is 0 In mode 1 if UARTCON 5 1 then the receive interrut will not be activated if a valid stop bit was not received The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit Parity enable bits PEN is located in the UARTPND register at address 4 Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only Figure 15 1 UART Control Register UARTCON ELECTRONICS 15 3 S3C84H5X F84H5X_UM_REV 1 10 UART INTERRUPT PENDING REGISTER UARTPND The UART interrupt pending register UARTPND is located at address F4H It contains the UART data transmit interrupt pending bit 0 and the receive interrupt pending bit UARTPND 1 In mode 0 of the UART module the receive interrupt pending flag UARTPND 1 is set to 1 when the 8th receive data bit has been shifted In mode 1 or 2 the UARTPND 1 bit is set to 1 at the halfway point of the stop bit s shift time When the CPU has acknowledged the receive interrupt pending condition the UARTPND 1 flag must be cleared by software in the interrupt service routine In mode 0 of the UART module the transmit interrupt pending flag UARTPND O is set to 1 when the 8th transmit data bit has been shifted In mode 1 or 2 the UARTPND O bit is set at the start of the stop bit When the CPU has acknowledged the transmit interrupt pending condition the U
209. le In this operation SIOCON 2 must be set to 1 to enable the data shifter For interrupt generation set the serial interrupt enable bit SIOCON 1 to 1 When you the transmit data to the serial buffer write data to SIODATA and set SIOCON 3 to 1 the shift operation starts When the shift operation transmit receive is completed the SIO pending bit SIOCON 0 is set to 1 and an SIO interrupt request is generated ELECTRONICS 14 1 SERIAL INTERFACE S3C84H5X F84H5X_UM_REV 1 10 SERIAL I O CONTROL REGISTERS SIOCON The control registers for serial interface SIOCON is located in Set1 Bank 1 at F2H It has the control settings for SIO module e Clock source selection internal or external for shift clock e Interrupt enable e Edge selection for shift operation e Clear 3 bit counter and start shift operation e Shift operation transmit enable e Mode selection transmit receive or receive only e Data direction selection MSB first or LSB first A reset clears the SIOCON value to 00H This configures the corresponding module with an internal clock source at the SCK selects receive only operating mode and clears the 3 bit counter The data shift operation and the interrupt are disabled The selected data direction is MSB first SIO CONTROL REGISTERS SIOCON F2H Set 1 Bank 1 R W Reset 00H SIO shift clock select bit SIO Interrupt pending bit 0 Internal clock P S clock 0 No interrupt pending
210. lice Register File Contains 32 8 Byte Slices FOH RO 16 byte Non contiguous working register block 11110 00000XXX Figure 2 8 Non Contiguous 16 Byte Working Register Block PROGRAMMING TIP Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80 85 using the register pointer The register addresses from 80H through 85H contain the values 10H 11H 12H 13H 14H and 15 H respectively SRPO 80H RPO lt 80H ADD RO R1 RO lt RO R1 ADC RO R2 RO lt RO R2 C ADC RO R3 RO lt RO R3 C ADC RO R4 RO lt RO R4 C ADC RO R5 RO lt RO R5 C The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H 80H lt 80H 81H ADC 80H 82H 80H lt 80H 82H ADC 80H 83H 80H lt 80H 83H ADC 80H 84H 80H lt 80H 84H ADC 80H 85H 80H lt 80H 85H Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rather than 36 cycles ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESS SPACES REGISTER ADDRESSING
211. ltiple vectors V4 V multiple sources S4 S 4 Sham In the S8C84H5X F84H5Xmicrocontroller two interrupt types are implemented Levels Typet IRQn 91 1 Type2 IRQn S2 S3 Sn 1 52 53 Sn 1 50 2 NOTES Sn m 1 The numberof SnandVn valueisexpandable 2 IntheS3C84H5X F 84H5Ximplementation interrupttypes 1and3areused Figure 5 1 S3C8 Series Interrupt Types 5 2 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INTERRUPT STRUCTURE 53 84 5 4 5 INTERRUPT STRUCTURE The S8C84H5X F84H5X microcontroller supports sixteen interrupt sources All of the interrupt sources have a corresponding interrupt vector address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from th
212. ly 7 6 P3 3 Configration Bits 01 Push pull output mode N channel open drain output 5 4 2 Configration Bits 0222 a fo output mode 3 3 P3 1 Configration Bits a 0 0 1 0 P3 0 Configration Bits 022 Push pull output mode N channel open drain output 4 22 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 CONTROL REGISTER PP Register Page Pointer DFH RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Destination Register Page Selection Bits EXESES Destination page 0 3 0 Source Register Page Selection Bits Source page 0 NOTE the S3C84H5X F84H5X microcontroller the internal register file is configured as one page Pages 0 The pages 0 are used for the general purpose register file and data register ELECTRONICS 4 23 CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 PWMCON PWM Control Register F5H Set1 Bank1 RESET Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W 7 6 PWM Input Clock Selection Bits Not used for S3C84H5X F84H5X 5 4 5 MDATA Reload Interval Selection Bit Reload from 10 bit up counter overflow 1 Reload from 8 bit up counter overflow 3 P M Counter Clear Bit No effect 1
213. mming Model Chapter 1 Product Overview S3C8 Series Microcontrollers 1 1 S3C84HbX F84LH5X Microcontroller eic e EE reed cane 1 1 REPE EET 1 2 Block Diagram snide t ieget tee 1 3 Pin ASSIQDITIe Leto ie 1 4 hiec 1 6 1 7 Piri Descriptioris iet tie E ed x cen tun 1 8 PINGICUNS Sera m MXN 1 12 Chapter 2 Address Spaces eA Ts E ede ate aden 2 1 Program Memory ROM adonde da nani Tae die eA ev a Ave ae ae 2 2 Register 2 4 Register Page Pointer PP 2 6 Register 2 8 Register Bela neni aia Salida le te eae 2 8 Prime Register Spacen 2 o CER rie edo Pee e ena eve Pee f Lene eae eaaet ete 2 9 Working ie aee ee texte ete deuce eee He re 2 10 Using the Register erue 2 11 Register Addressing ever 2 13 Common Working Register Area
214. mode Capture on falling edge OVF can occur 1 PWM mode 2 Timer 1 0 Counter Enable Bit No effect 1 Clear the timer 1 0 counter Auto clear bit Timer 1 0 Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer 1 0 Overflow Interrupt Enable Disable overflow interrupt 1 Enable overflow interrupt 4 30 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 CONTROL REGISTER 1 Timer 1 1 Control Register Bank1 Bit Identifier RESET VALUE Read Write Addressing Mode 7 5 ELECTRONICS _ 5 4 3 2 4 o 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only Timer 1 1 Input Clock Selection Bits opi opea 1 0 1 extemalclockfalingedge 1 1 0 exteralclockrisingedge Timer 1 1 Operating Mode Selection Bits Ears Interval mode Capture mode Capture on rising edge OVF can occur Capture mode Capture falling edge OVF can occur 1 PWM mode Ti 3 er 1 1 Counter Enable Bit No effect 1 Clear the timer 1 1 counter Auto clear bit Timer 1 1 Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt Timer 1 1 Overflow Interrupt Enable Disable overflow interrupt 1 Enable overflow interrupt 4 31 CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 Timer A Control Register E1H Set1 Bank1 RESET VALUE 0 0
215. n is arranged in the following order e Absolute maximum ratings e Input output capacitance e D C electrical characteristics e electrical characteristics e Oscillation characteristics e Oscillation stabilization time e Data retention supply voltage in stop mode e UART timing characteristics mode 0 A D converter electrical characteristics ELECTRONICS 20 1 ELECTRICAL DATA S3C84H5X F84H5X_UM_REV 1 10 Table 20 1 Absolute Maximum Ratings Ta 25 Parameter Symbot Conditions Uni Yoo 636 68 Durs vo 95 mV E A Output Current Low One I O pin active Operating T Table 20 2 Input Output Capacitance TA 25 C to 85 C Vpp 0 V Parameter Symbol Conditions min Typ Unit Input Capacitance f 1 MHz unmeasured pins 10 pF are tied to Vas Output Capacitance Capacitance 20 2 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ELECTRICAL DATA Table 20 3 D C Electrical Characteristics TA 25 C to 85 2 5V to 5 5 V Symbol Conditions Operating VDD fx 0 8MHz fxt 32 8kHz 2 5 Voltage LVR off fx 20 8MHz fxt 32 8kHz LV LVR on All Port and nRESET Xin and All Ports and nRESET Vpp 2 5V to 5 5 V Xin and Output High Voltage Vpp 5 0 V lon 2 All Ports Output Low Voltage Vpp 5 0 V Io 16 mA Ports 0 and 4 Vpp 5 0 V Io 4mA Ports 1 2 and 3 Input High Leak
216. n has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Set 1 R wo RQO IRQ2 IRQ3 IRQ5 IRQ4 Interrupt level 4 request pending bit 0 IRQ interrupt is not pending 1 IRQ interrupt is pending Figure 5 9 Interrupt Request Register IRQ 5 14 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INTERRUPT STRUCTURE INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared in the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by applicatio
217. n software In the S3C84H5X F84H5X interrupt structure the timer B underflow interrupt IRQO belongs to this category of interrupts in which pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register In the S3C84H5X F84H5X interrupt structure pending conditions for IRQ3 IRQ4 IRQ5 IRQ6 and IRQ7 must be cleared in the interrupt service routine ELECTRONICS 5 15 INTERRUPT STRUCTURE S3C84H5X F84H5X UM REV 1 10 INTERRUPT SOURCE POLLING SEQUENCE The gt interrupt request polling and servicing sequence is as follows A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks the interrupt level of source The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced th
218. nable Disable Selection Bit OX Disable Interrupt 10 Enable Interrupt Falling Edge 11 Enable Interrupt Rising Edge 5 4 P1 2s Interrupt Enable Disable Selection Bit OX Disable Interrupt 10 Enable Interrupt Falling Edge 11 Enable Interrupt Rising Edge 3 2 P1 1 s Interrupt Enable Disable Selection Bit OX Disable Interrupt 10 Enable Interrupt Falling Edge 11 Enable Interrupt Rising Edge 1 0 P1 0 s Interrupt Enable Disable Selection Bit OX Disable Interrupt 10 Enable Interrupt Falling Edge 11 Enable Interrupt Rising Edge Figure 9 5 Port 1 Interrupt Enable Register P1INT PORT 2 Port 2 is an 8 bit I O port with individually configurable pins Port 2 pins are accessed directly by writing or reading the port 2 data register P2 at location E2H set 1 bank 0 2 0 2 7 can serve as digital inputs outputs push pull or you can configure the following alternative functions e General purpose digital I O e Alternative function ADC4 ADC7 SI 1 1 1 Port 2 Control Register P2CONH P2CONL Port 2 has two 8 bit control registers 2 for P2 4 P2 7 and P2CONL for 2 0 2 3 A reset clears the P2CONH P2CONL registers to configuring all pins to input mode You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port plea
219. ne pulse width is equal to TIMER 1 0 1 CONTROL REGISTER T1CONO T1CON1 You use the timer 1 0 1 control register T1CON1 to e Select the timer 1 0 1 operating mode Interval timer Capture mode PWM mode e Select the timer 1 0 1 input clock frequency e Clear the timer 1 0 1 counter TTCNTHO LO T1CNTH1 L1 e Enable the timer 1 0 1 overflow interrupt e Enable the timer 1 0 1 match capture interrupt T1CONO is located in set 1 and Bank 1 at address E8H and is read write addressable using Register addressing mode T1CON1 is located in set 1 and Bank 1 at address E9H and is read write addressable using Register addressing mode A reset clears T1 CONO T1CON1 to OOH This sets timer 1 0 1 to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer 1 0 1 interrupts To disable the counter operation please set T1CON 0 1 7 5 to 111B You can clear the timer 1 0 1 counter at any time during normal operation by writing a 1 to T1 CON 0 1 3 The timer 1 0 overflow interrupt T1OVFO is interrupt level IRQ2 and has the vector address C6H And the timer 1 1 overflow interrupt T1OVF1 is interrupt level IRQ2 and has the vector address CAH To generate the exact time interval you should write 1 to T1CON 0 1 2 and clear appropriate pending bits of the TINTPND register To detect match capture or overflow interrupt pending condition when T1INTO T1INT1 o
220. nen nenne 2 6 2 5 Set 1 Set 2 Area 2 9 2 6 8 Byte Working Register Areas 2 10 2 7 Contiguous 16 Byte Working Register 2 11 2 8 Non Contiguous 16 Byte Working Register Block 2 12 2 9 16 Bit Register Pall oed edm 2 13 2 10 Register File Addressing 2 14 2 11 Common Working Register 24 2 15 2 12 4 Bit Working Register Addressing 2 17 2 13 4 Bit Working Register Addressing Example 2 17 2 14 8 Bit Working Register 00 2 18 2 15 8 Bit Working Register Addressing 2 19 2 16 Stack Operations iia tede itte retis ic eret RUE ete e bu d 2 20 3 1 Register Addressing 3 2 3 2 Working Register 00 3 2 3 3 Indirect Register Addressing to Register 1 3 3 3 4 Indirect Register Addressing to Program Memory 3 4 3 5 Indirect Working Register Addressing to Register File 3 5 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 3 7 Indexed Addressing to Register File
221. nfiguration Bits 0 0 Input mode Interrupt input INT1 TACK 0 1 Input mode with pull up Interrupt input INT1 TACK 1 0 Push pull output mode 1 1 Alternative function mode BUZ output 1 0 P1 0 TAOUT INTO Configuration Bits 0 0 Input mode Interrupt input INTO 0 1 Input mode with pull up Interrupt input 1 0 Push pull output mode 1 1 Alternative function mode TAOUT output Figure 9 3 Port 1 Low Byte Control Register P1CONL ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 PORTS Port 1 Interrupt Pending Register P1INTPND Set1 R W Reset value 00H 7 4 Not used for S3C84H5X F84H5X 3 P1 3 INT3 Interrupt Pending bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 2 P1 2 INT2 Interrupt Pending bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 1 P1 1 INT1 Interrupt Pending bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 0 P1 0 INTO Interrupt Pending bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending Figure 9 4 Port 1 Interrupt Pending Register P1INTPND ELECTRONICS 9 7 PORTS S3C84H5X F84H5X_UM_REV 1 10 Port 1 Interrupt Enable Register Set1 R W Reset value 00H 7 6 P1 3 s Interrupt E
222. nt bit position bit zero was 1 Z Setifthe result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 CO R 4 C1 IR Given Register register 01H 02H register 02H 17H and C 0 RRC 00H gt Register RRC 01H gt Register 01H 2AH 1 02H register 02H 1 In the first example if the general register OOH contains the value 55H 01010101 the statement RRC rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2 001010108 in the destination register OOH The sign flag and the overflow flag are both cleared to 0 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET SBO Select Bank 0 SBO Operation BANK lt 0 SBO instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting the bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SBO clears FLAGS 0 to 0 selecting the bank 0 register addressing ELECTRON
223. nternal register file using PUSH and POP instructions LD SPH 0FFH You must initialize SPH to OFFH LD SPL 0FFH SPL lt Normally the SPL is set to OFFH by the initialization routine ELECTRONICS 6 S3C84H5X F84H5X ERRATA REV 1 10 USER S MANUAL ERRATA 9 CONTROL REGISTERS PAGE 4 16 P1CONL Port 1 Control Register Low Byte E9H Set1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 3 T10UT1 INT3 Configration Bits ERES Input mode Interrupt input INT3 2011 Input mode with pull up Interrupt input Push pull output mode Alternative function mode T1OUT1 mode 10 CONTROL REGISTERS PAGE 4 20 P2CONL Port 2 Control Register Low Byte EDH Set1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 3 AD7 SI Configuration Bits 7 ELECTRONICS USER S MANUAL ERRATA S3C84H5X F84H5X_ERRATA_REV 1 10 11 CONTROL REGISTERS PAGE 4 27 SPH stack Pointer High Byte D8H Set 1 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address SP15 SP8 The lower byte of the stack pointer
224. o 8 byte register slices at one time as active working register space After a reset RP1 points to address C8H in register set 1 selecting the 8 byte working register slice 2 0 Not used for the S3C84H5X F84H5X ELECTRONICS 4 25 CONTROL REGISTERS SIOCON serial 1 0 Module Control Registers Bit Identifier RESET Value Read Write 4 26 S3C84H5X F84H5X UM REV 1 10 F2H Set1 Bank1 7 6 5 A 3 2 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W SIO Shift Clock Selection Bit 0 Interval clock P S Clock 1 External clock Data Direction Control Bit 0 MSB first mode LSB first mode SIO Mode Selection Bit Receive only mode Transmit Receive mode Shift Clock Edge Selection Bit 0 Tx at falling edges Rx at rising edges 1 Tx at rising edges Rx falling edges SIO Counter Clear and Shift Start Bit No action Clear 3 bit counter and start shifting SIO Shift Operation Enable Bit Disable shift and clock counter Enable shift and clock counter SIO Interrupt Enable Bit 0 Disable SIO interrupt 1 Enable SIO interrupt SIO Interrupt Pending Bit 0 No interrupt pending 1 Interrupt pending Clear pending bit when write ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 CONTROL
225. o OFFH by the initialization routine PUSH PP Stack address OFEH lt PP PUSH RPO Stack address OFDH lt RPO PUSH RP1 Stack address OFCH lt RP1 PUSH R3 Stack address OFBH lt POP R3 lt Stack address OFBH POP RP1 RP1 lt Stack address OFCH POP RPO RPO lt Stack address OFDH POP PP PP lt Stack address OFEH ELECTRONICS 2 21 S3C84H5X F84H5X_UM_REV 1 10 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in SAM8RCinstructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are e Register R e Indirect Register IR e Indexed X e Direct Address DA e Indirect Address 1 e Relative Address RA e Immediate IM ELECTRONICS 3 1 ADDRESSING MODES S3C84H5X F84H5X UM REV 1 10 REGISTER ADDRESSING MODE R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differ
226. o program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON 18 2 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 MTP MTP OVERVIEW SSF84H5X single chip CMOS microcontroller is the MTP Multi Time Programmable version of the S3C84H5X microcontroller It has an on chip Half Flash ROM instead of masked ROM The Half Flash ROM is accessed by serial data format The Half Flash ROM can be rewritten up to 100 times The SSF84H5X is fully compatible with the 3 84 5 in function D C electrical characteristics and in pin configuration Because of its simple programming requirements the 4 5 is ideal for use as an evaluation chip for the S3C84H5X VDD P1 3 T1OUT1 INT3 SCLK P1 2 TACAP INT2 SDAT P1 1 TACK BUZ INT1 S3C84H5X P1 0 TAOUT INTO P3 3 S3F84H5X AVss Top AV REF Vss Xour XIN TEST XTIN XTour nRESET 0 P3 1 SO P2 4 32 SOP P1 5 AD6 T1 CAP1 SCK P2 5 32 SDIP P1 4 AD5 T1CK1 RxD P2 6 P2 3 AD7 SI TxD P2 7 P2 2 AD4 T1OUTO ADO PO 0 Q 2 1 1 AD1 P0 1 P2 0 T1CKO TBPWM AD2 P0 2 AD3 P0 3 Figure 19 1 Pin Assignment
227. ogram and verify time OTP 2Kbytes per second MTP 10Kbytes per second e Internal large buffer memory 118M Bytes e Driver software run under various O S Windows 95 98 2000 XP e Full function regarding OTP MTP programmer Read Program Verify Blank Protection e Two kind of Power Supplies User system power or USB power adapter e Support Firmware upgrade SEMINIX TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http www seminix com ELECTRONICS USER S MANUAL ERRATA S3C84H5X F84H5X_ERRATA_REV 1 10 OTP MTP PROGRAMMER WRITE Continued US pro SEMINIX Portable Samsung OTP MTP FLASH Programmer TEL 82 2 539 7891 e Portable Samsung OTP MTP FLASH Programmer FAX 82 2 539 7819 e Small size and Light for the portable use e E mail e Support all of SAMSUNG OTP MTP FLASH sales seminix com devices e URL e Convenient USB connection to any IBM compatible http www seminix com PC or Laptop computers e Operated by USB power of PC e PC based menu drive software for simple operation e Very fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second e Support Samsung standard Hex or Intel Hex format e Driver software run under various O S Windows 95 98 2000 XP e Full function regarding OTP MTP programmer Read Program Verify Blank Protection e Support Firmware upgrade GW PRO2 SEMINIX Gang Programmer for OTP MTP FLASH MCU e TEL 82 2 539 789
228. ondition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See the list of condition codes at the beginning of this chapter The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement Flags No flags are affected Format Bytes Cycles Opcode Addr Mode note Hex dst cc opc dst 2 6 ccB RA cc 0to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits in length Example Given The carry flag 1 and LABEL X 1FF7H JR C LABEL X gt 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL_X will pass control to the statement whose address is currently in the program counter Otherwise the program instruction following the JR will be executed 6 48 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET LD Load LD dst src Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode
229. or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during the normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter is always broken by a clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt In Stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of fxx 4096 for reset or at the rate of the preset clock source for an external interrupt When 4 overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summary the following events occur when stop mode is released 1 During stop mode a power on reset or an interrupt occurs to trigger the Stop mode release and oscillation starts 2 power on reset occurred the basic timer counter will increase at the rate of fxx 4096 If an external interrupt is used to release stop mode the BTCNT value increases at the rate of the preset clock source Clock oscillation stabiliza
230. orking registers RO R7 R8 R15 e One working register block is 16 bytes sixteen 8 bit working registers RO R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file other than set 2 The base addresses for the two selected 8 byte register slices are contained in register pointers RPO and RP1 After a reset RPO and RP1 always point to the 16 byte common area in set 1 COH CFH Slice 32 11111XXX Slice 31 RP1 Registers R8 R15 Each register pointer points to one 8 byte slice of the register space selecting a total 16 byte working register block 00000XXX RPO Registers RO R7 Figure 2 6 8 Byte Working Register Areas Slices 2 10 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESS SPACES USING THE REGISTER POINTERS Register pointers RPO and RP1 mapped to addresses D6H and 7 in set 1 are used to select two movable 8 byte working register slices in the register file After a reset RP point to the working register common area RPO points to addresses COH C7H points to addresses C8H CFH To change a register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction see Figures 2 6 and 2 7 With working register addressing you can only access those two 8 bit slices of the register file that
231. output resolution at high frequencies 13 2 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 10 BIT PWM PULSE WIDTH MODULATION Table 13 2 PWM output stretch Values for Extension Data Register PWMDATAL 1 0 PWMDATAL Bit Bit1 Bit0 Stretched Cycle Number 00 PWM Data 4 MHz 00000000B 00 000000018 Register Values xxxxxx00B PWMDATAH PWMDATAL 10000000B 00 11111111B 00 Figure 13 1 10 Bit PWM Basic Waveform ELECTRONICS 13 3 10 PWM PULSE WIDTH MODULATION S3C84H5X F84H5X UM REV 1 10 PWM Clock 4 MHz 00000010B 01 PWMDATA ede 00001001B astm _ 7 xxxxxx01 B Extended waveform Figure 13 2 10 Bit Extended PWM Waveform 13 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 10 BIT PWM PULSE WIDTH MODULATION PWM CONTROL REGISTER PWMCON The control register the PWM module PWMCON is located at register address FSH PWMCON is used the 10 bit PWM modules Bit settings in the PWMCON register control the following functions e PWM counter clock selection e PWM data reload interval selection e PWM counter clear e PWM counter stop start or resume operation e PWM counter overflow 10 bit counter overflow interrupt control A reset clears all PWMCON bits to logic zero disabling the entire PWM module PWM Control Register PWMCON Reset 00H PWM input clock PWM OVF interrupt
232. passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst RA 3 12 C2 r Ir Given R1 02H R2 03H and register 02H CPIJE R1 R2 SKIP gt R2 04H PC jumps to SKIP location In this example the working register R1 contains the value 02H the working register R2 the value and the register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 00000010B to 02H 00000010B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location addressed by the CPIJE instruction must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example dst src RA If dst src 0 lt RA relr 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program counter and con
233. peration completed 1 Subtraction operation completed 2 Half Carry Flag No carry out of bit 3 or no underflow into bit 3 by addition or subtraction 1 Addition generated carry out of bit 3 or subtraction generated underflow into bit 0 jeo carryout of BES or o unde ow me BES by adaon oraren 1 Fast Interrupt Status Flag FIS Interrupt return IRET in progress when read 1 Fast interrupt service routine in progress when read 0 Bank Address Selection Flag Bank 0 is selected 1 Bank 1 is selected 4 8 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 CONTROL REGISTER IMR Interrupt Mask Register DDH Set 1 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Enable Bit Disable mask 1 Enable un mask 6 Interrupt Level 6 IRQ6 Enable Bit Disable mask Enable un mask 5 Interrupt Level 5 IRQ5 Enable Bit Disable mask 1 Enable un mask 4 Interrupt Level 4 IRQ4 Enable Bit Disable mask 1 Enable un mask 3 Interrupt Level 3 Enable Bit Disable mask 1 Enable un mask 2 Interrupt Level 2 IRQ2 Enable Bit Disable mask 1 Enable un mask 1 Interrupt Level 1 IRQ1 Enable Bit Disable mask Enable un mask 0 Interrupt Level 0 IRQO Enable Bit Disable mask 1 Enable un mask NOTE When an interrupt level is masked
234. put mode 1 1 Alternative function mode TAOUT output Figure 9 3 Port 1 Low Byte Conirol Register P1CONL USER S MANUAL ERRATA LSB ELECTRONICS USER S MANUAL ERRATA S3C84H5X F84H5X_ERRATA_REV 1 10 13 O PORTS PAGE 9 8 PORT 2 Port 2 is an 8 bit port with individually configurable pins Port 2 pins are accessed directly by writing or reading the port 2 data register P2 at location E2H in set 1 bank 0 2 0 2 7 can serve as digital inputs outputs push pull or you can configure the following alternative functions e General purpose digital I O e Alternative function ADC4 ADC7 SI T1CAP0 T1OUTO T1CKO TBPWM PWM 14 O PORTS PAGE 9 10 Port 2 Control Register Low Byte P2CONL EDH Set1 R W Reset value 00 7 6 P2 3 AD7 SI Configuration Bits 0 0 Input mode SI 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode AD7 7 6 P2 2 ADA T1OUTO Configuration Bits 0 0 Input mode 0 1 Alternative function mode 1 0 Push pull output mode 1 1 Alternative function mode AD4 7 6 P2 1 PWM T1CAPO Configuration Bits 0 0 Input mode 1 0 1 Alternative function mode 1 1 0 Push pull output mode 1 1 Alternative function mode PWM 7 6 P2 0 TBPWM T1CKO Configuration Bits 00 Input mode T1CKO 0 1 Alternative function mode T1CKO 1 0 Push pull output mode 1 1
235. r 08 Value used in OPERAND MEM Sample Instruction Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES S3C84H5X F84H5X UM REV 1 10 INDIRECT REGISTER ADDRESSING MODE Continued Register File MSB Points to or RP1 or RP1 Selected RP points to start of working register oe ee Program Memory 4 bit Working Register Address Register Next 2 bit Point Pair 022000 References either Register Pair Program Memory or 1 of 4 Data Memory 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data memory Value used in Instruction OPERAND Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory Please note however that you cannot access locations in set 1 using indexed addressing mode In short offset Indexed ad
236. r TTOVFO T1OVF1 is disabled the application program should poll the pending bit TINTPND register bank 1 address EOH When 1 is detected a timer 1 0 1 match capture or overflow interrupt is pending When the sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the interrupt pending bit If interrupts match capture or overflow are enabled the pending bit is cleared automatically by hardware ELECTRONICS 12 3 16 BIT TIMER 1 0 1 S3C84H5X F84H5X_UM_REV 1 10 Timer 1 Control Register T1CONO E8H Set 1 Bank 1 R W T1CON1 Set 1 Bank 1 R W we 2 Timer 1 clock source selection bit Timer 1 overflow interrupt enable bit n 0 Disable overflow interrupt 010 fxx 64 1 Enable overflow interrrupt 011 fxx 8 100 fxx Timer 1 match capture interrupt enable bit 101 External clock falling edge 0 Disable interrupt 110 External clock rising edge 1 Enable interrrupt 111 Counter sto Timer 1 counter clear bit 0 No effect 1 Clear counter Auto clear bit Timer 1 operating mode selection bit 00 Interval mode 01 Capture mode capture on rising edge OVF can occur 10 Capture mode capture on falling edge OVF can occur 11 PWM mode NOTE Interrupt pending bits are located in TINTPND register Figure 12 1 Timer 1 0 1 Control Register 1 1 ELECTRONICS S3C84H5X F84H5X
237. r Type Number of Bytes General purpose registers including 16 byte common 272 working register area expanded 2 separately addressable register pages 1Page occupies 172 byte prime register area and the 64 byte set 2 area CPU and system control registers Mapped clock peripheral I O control and data registers Total Addressable Bytes 2 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 Set1 Bank 1 ADDRESS SPACES Bank 0 System and Peripheral Control Registers Register Addressing Mode System and Peripheral Control Registers Register Addressing Mode General Purpose Register Register Addressing Mode Page 0 Set 2 General Purpose Data Registers Indirect Register Indexed Mode and Stack Operations Prime Data Registers All Addressing Modes Figure 2 3 Internal Register File Organization ELECTRONICS 2 5 ADDRESS SPACES S3C84H5X F84H5X_UM_REV 1 10 REGISTER PAGE POINTER PP The S3C8 series architecture supports the logical expansion of the physical 256 byte internal register file using an 8 bit data bus into as many as 2 separately addressable register pages Page addressing is controlled by the register page pointer DFH In the S3C84H5X F84H5X microcontroller a paged register file expansion is implemented for data registers and the register page pointer must be changed to address other pages After a rese
238. r Value LSB MSB 8 1 SIOPS 1 First SIOPS F4H Mode Select Figure 14 3 SIO Functional Block Diagram ELECTRONICS 14 3 SERIAL INTERFACE S3C84H5X F84H5X_UM_REV 1 10 Transmit IRQS Set SIOCON 3 Figure 14 4 Serial I O Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 A Yon so 7 Transmit IRQS 3 Complete Set SIOCON 3 Figure 14 5 Serial I O Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 14 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 SERIAL INTERFACE Shift Clock Data Input Data Output IRQS Start 2 Figure 14 6 Serial I O Timing Receive Only Mode PROGRAMMING SIO ORG 0000H VECTOR INT_SIO ORG 0100H INITIAL LD BTCON 10100010B Watch dog disable LD 00011000B non divided CPU clock LD SPH 0FFH It must be initialized to OFFH LD SPL 00 LD P2CONH 10101111B SIO setting LD P2CONL 00101010B LD SIOCON 00100110B Enable SlIO Interrupt LD SIOPS 420 Setting baud rate EI ELECTRONICS 14 5 SERIAL INTERFACE 527 PROGRAMMING TIP SIO Continued MAIN SUB_SIO INT_SIO LD OR RET AND IRET SUB_SIO MAIN SIODATA TRAN
239. r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb 7 PUSH PUSH R2 IR2 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b B 8 DECW DECW PUSHUD PUSHUI MULT MULT MULT LD RR1 IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 r1 x r2 B 9 RL RL POPUD POPUI DIV DIV DIV LD R1 IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 r2 x r1 L A INCW INCW CP CP CP CP CP LDC RR1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 Irr2 xL E B CLR CLR XOR XOR XOR XOR XOR LDC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 Irr2 xL C RRC RRC CPIJE LDC LDW LDW LDW LD R1 IR1 1 2 r1 Irr2 RR2 RR1 IRZ RR1 RR1 IML r1 Ir2 H D SRA SRA CPIJNE LDC CALL LD LD R1 IR 1 Irr r2 RA IR1 IM Ir1 r2 E E RR RR LDCD LDCI LD LD LD LDC R1 IR1 r1 Irr2 r1 Irr2 R2 R1 R2 IR1 R1 IM r1 Irr2 xs X F SWAP SWAP LDCPD LDCPI CALL LD CALL LDC R1 IR1 2 1 IRR1 IR2 R1 DA1 r2 Irr1 xs ELECTRONICS S3C84H5X F84H5X UM REV 1 10 INSTRUCTION SET Table 6 5 OPCODE Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX 8 9 U 0 LD LD DJNZ JR LD JP INC NEXT r1 R2 r2 R1 r1 RA cc RA r1 IM cc DA r1 PI 1 i ENTER 2 3 4 580 5 581 6 IDLE I 7 i i STOP 8 DI B 9 EI L A RET E B IRET C RCF H D 1 sc E E CCF X F LD LD DJNZ JR LD JP INC NOP r1 R2 r2 R1 r1 RA cc RA r1 IM cc DA r1
240. re affected Bytes Cycles Opcode Addr Mode note Hex dst src opc src 1 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 O7H BTJRT SKIP R1 1 If the working register R1 contains the value 07H 00000111 the statement BTJRT SKIP R1 1 tests bit one the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location addressed by the BTJRT instruction must be within the allowed range of 127 to 128 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET BXOR Bit xor BXOR BXOR Operation Flags Format Examples dst src b dst b src 4510 lt 4540 XOR src b or dst b lt dst b XOR 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or the source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Cleared to V Undefinsed D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst b 0 src 3 6 27 Rb src b 1 dst 3 6
241. recovery from software malfunction If watchdog timer is not refreshed before an end of counter condition overflow is reached the internal reset will be activated The S8C84H5X F84H5X has a built in low voltage reset circuit that allows detection of power voltage drop of external Vpp input level to prevent a MCU from malfunctioning in an unstable MCU power level This voltage detector works for the reset operation of MCU This Low Voltage reset includes an analog comparator and Vref circuit The value of a detection voltage is 2 8V The on chip Low Voltage Reset features static reset when supply voltage is below a reference voltage value Typical 2 8 V Thanks to this feature external reset circuit can be removed while keeping the application safety As long as the supply voltage is below the reference value there is an internal and static RESET The MCU can start only when the supply voltage rises over the reference voltage When you calculate power consumption please remember that a static current of LVR circuit should be added a CPU operating current in any operating modes such as Stop Idle and normal RUN mode ELECTRONICS 18 1 LOW VOLTAGE RESET S3C84H5X F84H5X_UM_REV 1 10 Watchdog nRESET nRESET E Internal System nRESET When the Vpop level is lower than 2 8V NOTES 1 The target of voltage detection level is 2 8 V at 5 V 2 BGR is Band Gap voltage Reference Figure 18 1 Low Voltage Reset Circuit NOTE T
242. red to the PWM data PWMDATAH 7 0 In order to achieve higher resolutions the lower 2 bits of the PWMDATAL counter can be used to modulate the stretch cycle To control the stretching of the PWM output duty cycle at specific intervals the lower 2 bits of PWMDATAL counter value is compared with the PWMDATAL 1 0 ELECTRONICS 10 PWM PULSE WIDTH MODULATION S3C84H5X F84H5X UM REV 1 10 PWM Data and Extension Registers PWM duty data registers located in Set 1 Bank1 at address F3H F4H determine the output value generated by each 10 bit PWM circuit To program the required PWM output you load the appropriate initialization values into the 8 bit reference data register PWMDATAH 7 0 and the 2 bit extension data register PWMDATAL 1 0 To start the PWM counter or to resume counting you set PWMCON 2 to 1 A reset operation disables all PWM output The current counter value is retained when the counter stops When the counter starts counting resumes at the retained value PWM Clock Rate The timing characteristics of PWM output is based on the fosc clock frequency The PWM counter clock value is determined by the setting of PWMCON 6 7 Table 13 1 PWM Control and Data Registers PWM data registers PWMDATAH 7 0 Set 1 Bank 1 8 bit PWM basic cycle frame value PWMDATAL 1 0 Set 1 Bank 1 2 bit extension stretch value PWM control registers PWMCON Set 1 Bank 1 PWM counter stop star
243. rious O S Windows 95 98 2000 XP e Full function regarding OTP MTP programmer Read Program Verify Blank Protection e Support Firmware upgrade GW PRO2 SEMINIX Gang Programmer for OTP MTP FLASH MCU e TEL 82 2 539 7891 8 devices programming at one time 5 poem e Fast programming speed 1 2Kbyte sec ados e PC based control operation mode or Stand alone 2 T T Full Function regarding program inix Read Program Verify Protection Blank ww semini cam e Data back up even at power break After setup in Design Lab it can be moved to the factory site Key Lock protecting operator s mistake Good Fail quantity displayed and memorized Buzzer sounds after programming User friendly single menu operation PC Operation status displayed in LCD panel 22 10 ELECTRONICS
244. rking dst src Register Register Address OPCODE Point to Working Pair block 16 Bit address added to p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in 16 Bits Instruction LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed Sample Instructions Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESSING MODES INDEXED ADDRESSING MODE Continued Register File n dui RPO or RP1 or RP1 Selected RP points Program Memory to start of working OFFSET register OFFSET NEXT 2 Bits as gt Register Register Address OPCODE Point to Working Pair block Register Pair 16 Bit address added to p Program Memory offset LSB Selects or Data Memory 16 Bits 16 Bits OPERAND Value used in 16 Bits Instruction Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 9 Indexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES S3C84H5X F84H5X_UM_REV 1 10 DIRECT ADDRESS MODE DA In Direct Address DA mode the instruct
245. rogram reset address in the ROM 0100H e When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed NORMAL MODE RESET OPERATION In normal masked ROM mode the TEST pin is tied to Vss A reset enables access to the 16 Kbyte on chip ROM NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON ELECTRONICS 8 1 POWER DOWN S3C84H5X F84H5X_UM_REV 1 10 HARDWARE RESET VALUES Table 8 1 8 2 and 8 3 list the reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values e 0 shows the reset bit value as logic one or logic zero respectively e An x means that the bit value is undefined after a reset Adash means that the bit is either not used not mapped but read 0 is the bit value Table 8 1 S3C84H5X F84H5X Set 1 Register values after RESET ECCE S Dee 7 8 8 4 3 2 Hmeenmiegse econ o o o o
246. s from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 3 2 Program Memory Register File 8 bit Register File Address dst OPERAND Point to One OPCODE Register in Register One Operand File Instruction Example Value used in Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Point to RPO ot 1 RPO or RP1 9 4 Selected RP points to start of working Program Memory register orking Register dst block OPCODE Point to the OPERAND LA Working Register Two Operand 1 of 8 Instruction Example Sample Instruction ADD R1 R2 Where 1 and R2 are registers in the currently selected working register area Figure 3 2 Working Register Addressing ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address ano
247. se remember that any alternative peripheral I O function you configure using the port 2 control registers must also be enabled in the associated peripheral module Port 2 Pull up control Registers P2PUR Using the port 2 pull up control register 2 FA SET1 BANKO you can configure pull up resistors to individual port 0 pins 9 8 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 PORTS Port 2 Control Register High Byte P2CONH Seti R W Reset value 00 7 6 P2 7 TxD Configuration Bits 0 0 Input mode 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode TxD output 5 4 P2 6 RxD Configuration Bits 0 0 Input mode 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode RxD output 3 2 P2 5 SCK Configuration Bits 0 0 Input mode 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode output 1 0 P2 4 SO Configuration Bits 0 0 Input mode 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode SO output Figure 9 6 Port 2 High Byte Control Register P2CONH ELECTRONICS 9 9 PORTS S3C84H5X F84H5X_UM_REV 1 10 Port 2 Control Register Low Byte P2CONL EDH Set1 R W Reset value 00 7 6 P2 3 AD7 SI Configuration Bits 0 0 Input mode SI 0 1
248. sed to release Stop mode are e External interrupts 1 0 1 3 INTO INT3 Please note the following conditions for Stop mode release e lf you release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged e If you use an external interrupt for Stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the appropriate control and clock settings before entering Stop mode e When the Stop mode is released by external interrupt the CLKCON 4 and CLKCON 3 bit pair setting remains unchanged and the currently selected clock value is used e The external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed ELECTRONICS 8 5 POWER DOWN S3C84H5X F84H5X_UM_REV 1 10 How to into Stop Mode There are two steps to enter into Stop mode 1 Handling STOPCON register to appropriate value 10100101B 2 Writing Stop instruction keep the order IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6 In idle mode CPU operations are halted while some peripherals remain active During idle mode the internal clock signal is gated away from the CPU but all peripherals timers remain active Port pins retain the mode input or output they had at the time idl
249. stack area Disable watch dog Enable TAOUT output Match interrupt enable 6 55 ms duration 10 MHz x tal 8 BIT TIMER A B 11 11 8 S3C84H5X F84H5X_UM_REV 1 10 PROGRAMMING TIP Using the Timer ORG 0000h VECTOR OBEh TBUN INT ORG 0100h INITIAL DI LD IMR 00000001b Enable IRQO interrupt LD SPH 00000000b Set stack area LD SPL 211111111b LD BTCON 1010001 1b Disable Watch dog LD P2CONL 03H Enable TBPWM output LD TBDATAH 80h LD TBDATAL 80h LD TBCON 11101110b Enable interrupt fxx 256 Repeat Duration 6 605ms 10 MHz x tal EI MAIN MAIN ROUTINE JR T MAIN TBUN_INT Interrupt service routine IRET END 11 12 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 16 BIT TIMER 1 0 1 16 BIT TIMER 1 0 1 OVERVIEW The S8C84H5X F84H5X has two 16 bit timer counters The 16 bit timer 1 0 1 is 16 bit general purpose timer counter Timer 1 0 1 has three operating modes one of which you select using the appropriate T1CONO T1CON1 setting is e Interval timer mode Toggle output at T1OUTO T1OUT 1 e Capture input mode with a rising or falling edge trigger at the 1 T1CAP1 pin e PWM mode T1PWMO T1PWM1 PWM output shares their output port with T1OUTO T1OUT1 pin Timer 1 0 1 has the following functional components e Clock frequency divider fxx divided by 1024 256 64 8 1 with multiplexer e External clock input pin T1CKO T1CK1 e A 16 bit
250. ster pair is multiplied by the source operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers Set ifthe result is gt 255 cleared otherwise Given Register 20H register 01H register 02H MULT MULT MULT 00H 02H 00H 01H gt 00H 30H Set if MSB of the result is 1 cleared otherwise Z Set if the result is 0 cleared otherwise V Cleared D Unaffected H Unaffected Bytes Cycles Opcode Hex opc src dst 3 22 84 22 85 22 86 Register OOH 01H register 01H register 02 09 Register OOH OOH register 01H Register OOH O6H register 01H OOH Addr Mode dst src RR R RR IR RR IM 09H register O3H 06H In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register of the register pair OOH 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair OOH 01H ELECTRONICS 6 59 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 NEXT Next NEXT Operation lt IP IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two
251. sult is dumped into the ADDATAH ADDATAL registers where it can be read The ADC module enters an idle state Remember to read the contents of ADDATAH and ADDATAL before another conversion starts Otherwise the previous result will be overwritten by the next conversion result NOTE Because the ADC does not use sample and hold circuitry it is important that any fluctuations in the analog level at the ADCO ADCT7 input pins during a conversion procedure be kept to an absolute minimum Any change in the input level perhaps due to circuit noise will invalidate the result ELECTRONICS 16 1 S3C84H5X F84H5X_UM_REV 1 10 A D CONVERTER CONTROL REGISTER ADCON The A D converter control register ADCON is located in set1 bank 0 at address F7H ADCON is read write addressable using 8 bit instructions only But the EOC bit ADCON 3 is read only ADCON has four functions Bits 6 4 select an analog input pin ADCO ADC7 e Bit indicates the end of conversion status of the A D conversion e Bits 2 1 select a conversion speed e Bit O starts the A D conversion Only one analog input channel can be selected at a time You can dynamically select any one of the eight analog input pins ADCO ADC7 by manipulating the 3 bit value for ADCON 6 ADCON 4 A D Converter Control Register ADCON F7H Set 1 Bank 0 R W ADCON 3 bit is read only Not used Start or Enable bit must keep always 0 0 Disable Operation 1 Start
252. t ORG 0100H RESET DI Disable interrupt LD BTCON 10100011B Watchdog disable LD P2CONL 00001 100B Configure P2 1 PWM output LD PWMCON 00000110B fog 64 counter interrupt enable LD PWMDATAH 80H LD PWMDATAL 0 Enable interrupt lt lt Main loop gt gt MAIN JR t MAIN lt lt Interrupt Service Routines gt gt INT_PWM PWM interrupt service routine AND PWMCON 11111110B Pending bit clear ELECTRONICS 13 7 S3C84H5X F84H5X UM REV 1 10 SERIAL INTERFACE SERIAL INTERFACE OVERVIEW Serial module SIO can interface with various types of external devices that require serial data transfer The components of each SIO function block are 8 bit control register SIOCON Clock selection logic 8 bit data buffer SIODATA 8 bit presale SIOPS 3 bit serial clock counter Serial data I O pins SI SO External clock input pin SCK SIO module can transmit or receive 8 bit serial data at a frequency determined by its corresponding control register settings To ensure flexible data transmission rates you can select an internal or external clock source PROGRAMMING PROCEDURE To program the SIO module follow these basic steps 1 2 Configure the pins at port 2 SO SCK SI by loading the appropriate value to the Register Load an 8 bit value to the SIOCON control register to properly configure the serial modu
253. t Bytes Cycles Opcode Hex 1 4 Example The statement SCF sets the carry flag to 1 6 78 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET SRA shift Right Arithmetic SRA Operation Flags Format Examples dst dst 7 lt dst 7 C lt dst 0 dst n lt dst n 1 n 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into the bit position 6 C Setifthe bit shifted from the LSB position bit zero was 1 Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Always cleared to D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst 451 2 4 00 R 4 D1 IR Given Register 00H 9AH register 02H register OBCH and 1 SRA 00H gt Register OOH SRA 02H gt Register 02H OCD 0 register 0 In the first example if the general register OOH contains the value 10011010B the statement SRA 00 shifts the bit values in the register OOH right one bit position Bit zero 0 clears the C flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value OCDH 11001101B in the destination register ELECTRONICS 6
254. t resume and PWM counter clock settings PWM Function Description The PWM output signal toggles to Low level whenever the 8 bit counter matches the reference data register PWMDATAH If the value in the PWMDATAH register is not zero an overflow of the 8 bits of counter causes the PWM output to toggle to High level In this way the reference value written to the reference data register determines the module s base duty cycle The value in the lower 2 bits of PWMDATAL counter is compared with the extension settings in the 2 bit extension data register PWMDATAL 1 0 This lower 2 bits of counter value together with extension logic and the PWM module s extension data register is then used to stretch the duty cycle of the PWM output The stretch value is one extra clock period at specific intervals or cycles see Table 12 2 If for example the value in the extension PWMDATAH register is 00 and PWMDATAL register is 01B the 2nd cycle will be one pulse longer than the other 3 cycles If the base duty cycle is 50 the duty of the 2nd cycle will therefore be stretched to approximately 5196 duty For example if you write 10B to the extension data register all odd numbered pulses will be one cycle longer If you write 11H to the extension data register all pulses will be stretched by one cycle except the 4th pulse PWM output goes to an output buffer and then to the corresponding PWM output pin In this way you can obtain high
255. t the page pointer s source value lower nibble and the destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing Register Page Pointer PP DFH Set 1 R W we Ts 21516 Destination register page selection bits Source register page selection bits 0000 Destination Page 0 0000 Source Page 0 NOTE hardware reset operation writes the 4 bit destination and source values shown above tho the register page pointer These values should be modified to other page Figure 2 4 Register Page Pointer PP 2 6 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESS SPACES Programming Tip Using the Page Pointer for RAM clear LD SRP LD RAMCLO CLR DJNZ CLR LD LD RAMCL1 CLR DJNZ CLR ELECTRONICS PP 00H 0COH RO 0FFH RO RO RAMCLO RO PP 10H RO 0FFH RO RO RAMCL1 GRO Destination lt 0 Source lt 0 0 RAM clear starts RO 00H Destination 1 Source lt 0 Page 1 RAM clear starts RO 00H 2 7 ADDRESS SPACES S3C84H5X F84H5X_UM_REV 1 10 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file locations COH FFH The upper 32 byte area of this 64 byte space EOH FFH is expanded two 32 byte register banks bank 0 and bank 1 The set register bank instructions SBO or SB1 are used to address one bank or the other A hardware reset operation always selects
256. t used Not used Not used Not used Not used Not used P3 3 P3 2 P3 1 IUUUUU gt 2 0 o UUUUUUUU Figure 22 4 44 Connector Pin Assignment for TB84H5 22 6 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 DEVELOPMENT TOOLS Not used Not used Not used Not used Not used Not used INTO TAOUT P1 0 INT1 BUZ TACK P1 1 INT2 TACAP P1 2 Not used Not used Not used Not used Not used Not used P3 3 P3 2 P3 1 P3 0 AD3 P0 3 AD2 P0 2 AD1 PO 1 Xin ADO PO 0 TEST AVss XTin AVref XTout P2 7 TxD nRESET P2 6 RxD 1 2 0 2 5 5 PWM T1CAPO P2 1 P2 4 SO T1OUTO AD4A P2 2 2 5 WD INTS T1OUT1 P1 3 VDD VSS Xout 1351008 Figure 22 5 42 Connector Pin Assignment for TB84H5 Target Board Target System J101 2 2 5 5 5 5 5 5 2 S S Figure 22 6 TB84H5 Adapter Cable for 44pin Connector Package ELECTRONICS 22 7 DEVELOPMENT TOOLS S3C84H5X F84H5X_UM_REV 1 10 Third Parties for Development Tools SAMSUNG provides a complete line of development tools for SAMSUNG s microcontroller With long experience in developing MCU systems our third parties are leading companies in the tool s technology SAMSUNG In circuit emulator solution covers a wide range of capabilities and prices from a low cost IC
257. ta registers T1DATAHO T1DATALO for rising edge or falling edge You can select rising or falling edge to trigger this operation The timer 1 0 also gives you capture input source the signal edge at the T1CAPO pin You select the capture input by setting the value of the timer 1 0 capture input selection bit in the port 0 control register high POCONH set 1 E6H Both kinds of timer 1 0 interrupts 1 T1INTO can be used in capture mode the timer 1 0 overflow interrupt is generated whenever a counter overflow occurs the timer 1 0 capture interrupt is generated whenever the counter value is loaded into the timer 1 data register By reading the captured data value in T1DATAHO T1DATALO and assuming a specific value for the timer 1 0 clock frequency you can calculate the pulse width duration of the signal that is being input at the T1CAPO pin In capture mode for Timer 1 1 a signal edge that is detected at the T1CAP1 pin opens a gate and loads the current counter value into the timer 1 data register T1DATAH1 T1DATAL1 for rising edge or falling edge You can select rising or falling edges to trigger this operation The timer 1 1 also gives you capture input source the signal edge at the T1CAP1 pin You select the capture input by setting the value of the timer 1 1 capture input selection bit in the port 0 control register low POCONL set 1 bank0 E7H Both kinds of timer 1 1 interrupts T1OVF1 T1INT1 can be
258. te value to the ADCON register When conversion has been completed 50 clocks have elapsed the EOC ADCON 3 flag is set to 1 so that a check can be made to verify that the conversion was successful The converted digital value is loaded to the output register ADDATAH 8 bit and ADDATAL 2 bit then the ADC module enters an idle state The digital conversion result can now be read from the ADDATAH and ADDATAL register Analog ADCO Input Pin ADC7 S3C84H5X F84H5X NOTE 1 The symbol signifies an offset resistor with a value of from 50 to 100 2 Avref must be tied to Vdd Figure 16 5 Recommended A D Converter Circuit for Highest Absolute Accuracy ELECTRONICS 16 5 S3C84H5X F84H5X_UM_REV 1 10 PROGRAMMING TIP Configuring A D Converter ADO CHK ADS POCON 11111111 P1CONH 00001111B P2CONL 11110000B ADCON 00000001B ADCON 00001000B 2 ADO_CHK ADOBUFH ADDATAH ADOBUFL ADDATAL ADCON 00110001 ADCON 00001000B Z AD3 CHK ADSBUFH ADDATAH ADSBUFL ADDATAL 0 A D Input MODE P1 4 P1 5 A D Input MODE 2 2 2 3 A D Input MODE Channel ADCO fxx Conversion start A D conversion end EOC check No 8 bit Conversion data 2 bit Conversion data Channel ADCS fxx Conversion start A D conversion end EOC check No 8 bit Conversion data 2 bit Conversion data ELECTRONICS S3C84H5X F84H5X_UM_REV
259. ted Bytes Cycles Opcode Addr Mode Hex dst src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4 OAAH SPH OOH and SPL OOH PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register OAAH stack register OFFH OAAH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value OOOOH and the general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of the register 40H into the location OFFFFH and adds this new value to the top of the stack ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET PUSHUD Push User Stack Decrementing PUSHUD Operation Flags Format Example dst src IR lt IR 1 dst lt src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 451 src 3 8 82 IR R Given Register 00H 03H register 01H 05H and register 02H PUSHUD 000 01 gt Register 02H register 01H 05H register 02 05 If the
260. ted C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst b 0 src 3 6 07 Rb src b 1 dst 3 6 07 Rb NOTE Inthe second byte of the 3 byte instruction format the destination or the source address is four bits the bit address is three bits and the LSB address value is one bit Given R1 07H and register 01H BOR R1 01H 1 gt R1 07H register 01H 03H BOR 01H 2 R1 gt Register 01H 07H R1 07 In the first example the destination working register R1 contains the value 07H 00000111B and the source register 01H the value 03H 00000011B The statement BOR R1 01H 1 logically ORs bit one of the register 01H source with bit zero of R1 destination This leaves the same value 07H in the working register R1 In the second example the destination register 01H contains the value 00000011B and the source working register R1 the value 07H 00000111B The statement BOR 01H 2 R1 logically ORs bit two of the register 01H destination with bit zero of R1 source This leaves the value in the register 01H ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET Test Jump Relative on False BTJRF Operation Flags Format Example dst src b If src b is 0 then PC lt PC
261. ter 00H In the first example the working register pair RRO contains the value 1AH in the register RO and 02H in the register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value in the register R1 In the second example the statement NCW R1 uses Indirect Register IR addressing mode to increment the contents of the general register 03H from OFFH to 00H and the register 02H from OFH to 10H A system malfunction may occur if you use a Zero Z flag FLAGS 6 result together with an INCW instruction To avoid this problem it is recommended to use the INCW instruction as shown in the following example LOOP INCW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS 6 45 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 Interrupt Return IRET Operation Flags Format Example NOTE IRET Normal RET Fast FLAGS lt SP lt SP lt SP 1 FLAGS lt FLAGS lt FIS 0 SP lt SP 2 SYM 0 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings t
262. ter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to S3C84H5X F84H5X with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack operations Chapter 3 Addressing Modes contains detailed descriptions of the addressing modes that are supported by the S3C8 series CPU Chapter 4 Control Registers contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the S3C84H5X F84H5X interrupt structure in detail and further prepares you for additional information presented the individual hardware module descriptions in Part Il Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3C8 series microcontrollers Several summary tables are presented for orientation and reference Det
263. ter that employs Win95 98 2000 XP as its operating system can be used A sophisticated debugging tool is provided both in hardware and software the powerful in circuit emulator OPENice i500 and SK 1200 for the S3C7 S3C9 and S3C8 microcontroller families Samsung also offers supporting software that includes debugger an assembler and a program for setting options Target Boards Target boards are available for all the S3C8 S3F8 series microcontrollers All the required target system cables and adapters are included on the device specific target board TB84H5 is a specific target board for the development of application systems using 84 5 programming socket adapter When you program S3F84H5X s flash memory by using an emulator or OTP MTP writer you need a specific programming socket adapter for SSF84H5X ELECTRONICS 22 1 DEVELOPMENT TOOLS Development System Configuration IBM PC AT or Compatible Emulator SK 1200 RS 232 USB or 1 500 5 232 S3C84H5X F84H5X_UM_REV 1 10 Target Application System Probe Adapter TB84H5 Target Board EVA Chip Figure 22 1 Development System Configuration ELECTRONICS S3C84H5X F84H5X UM REV 1 10 DEVELOPMENT TOOLS TB84H5 Target Board The TB84H5 target board can be used for development of S3F84H5X and 53 84 5 together But you should be careful to set the memory size to program internal flash memory The TB84H5 target bo
264. ternately 0 0 0 3 can be used as ADO AD3 Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up resistor Alternatively P1 0 P1 5 can be used as INTO INT3 TAOUT TACK TACAP T1OUT1 T1CK1 T1CAP1 AD5 AD6 BUZ Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately P2 0 P2 7 be used ADCA4 ADC7 SI T1CAPO T1OUTO T1CKO SO SCK RxD TxD TBPWM PWM Bit programmable port input or output mode selected by software input or push pull N channel open drain output Software assignable pull up ELECTRONICS 9 1 PORTS S3C84H5X F84H5X_UM_REV 1 10 PORT DATA REGISTERS Table 9 2 gives you an overview of the register locations of all seven S3C84H5X F84H5X I O port data registers Data registers for ports 0 1 2 and 3 have the general format shown in Table 9 2 Table 9 2 Port Data Register Summary 9 2 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 PORTS PORT 0 Port 0 is an 4 bit I O port that you can use two ways e General purpose digital I O e Alternative function ADO AD3 Port 0 is accessed directly by writing or reading the port 0 data register PO at location in set 1 bank 0 Port 0 Control Register POCON Port 0 has one 8 bit control registers POCON for 0 A reset clears the POCON registers to configuring all pins to input
265. ther register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations COH FFH set 1 using the Indirect Register addressing mode Program Memory Register File BbtRegster ADDRESS OPCODE Point to One gt Register Register File Instruction Example Address of Operand used by Instruction Value used in OPERAND Instruction Execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES S3C84H5X F84H5X UM REV 1 10 INDIRECT REGISTER ADDRESSING MODE Continued Register File Program Memory Example REGISTER Instruction dst References OPCODE Points to Program Register Pair 16 Bit Memory Address Points to Program Memory Program Memory Sample Instructions Value used in OPERAND CALL RR2 Instruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File MSB Points to RPO or RP1 gt RPO Selected RP points Program Memory to start fo hi working register 4 bit block Working mm dst sc e Register Point to the ADDRESS Address Working Registe
266. tion Hardware Reset Values Power Down Modes Stop Mode Idle Mode Chapter 9 Ports OVEINVIEW ELLE Port Data Registers Port 0 Chapter 10 Basic Timer EER Basie EET Basic Timer Control Register Basic Timer Function Description S3C84H5X F84H5X_UM_REV 1 10 MICROCONTROLLER vii Table of Contents Continued Chapter 11 8 Bit Timer A B 11 1 e a Dae Te RG end Aa sade an Sa 11 1 Function DescriptiOn 11 2 Timer A Control Register 11 3 Block Diagrarm i ag EE ERE TR 11 4 8 Bit Timer EE 11 5 OVSOIVIOWu i odio 11 5 sore 9 11 5 Timer Control Register 22 2 0 2 4 0 0 00 11 6 Timer B Pulse Width 11 7 Chapter 12 16 Bit Timer 1 0 1 nti itat iu 12 1 Function E 12 2 Timer 1 0 1 Control Register 1 2 20000 00 000 12 3 je acu nee 12 6
267. tion interval begins and continues until bit 4 of the basic timer counter overflows When a BTONT 4 overflow occurs normal CPU operation resumes ELECTRONICS 10 3 BASIC TIMER S3C84H5X F84H5X_UM_REV 1 10 RESET or STOP Bits 3 2 Basic Timer Control Register v Write 1010xxxxB to disable Data Bus fxx 4096 Ed fxx 1024 8 Bit Up Counter Read Only fxx 128 R NOTE During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows Start the CPU nete Figure 10 2 Basic Timer Block Diagram 10 4 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 8 BIT TIMER A B 8 BIT TIMER A B 8 BIT TIMER A OVERVIEW The 8 bit timer A is an 8 bit general purpose timer counter Timer A has three operating modes you can select one of them using the appropriate TACON setting e Interval timer mode Toggle output at TAOUT pin e Capture input mode with a rising or falling edge trigger at the TACAP pin e PWM mode TAPWM Timer A has the following functional components e Clock frequency divider fxx divided by 1024 256 or 64 with multiplexer e External clock input pin TACK 8 0 counter TACNT 8 bit comparator and 8 bit reference data register e pins for capture or PWM or match output TAOUT e Timer A overflow interrupt IRQ1 vector C2H and match capture interrupt IRQ1 vector COH
268. tions so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and it cannot be addressed as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is normally not accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The flag is cleared to select bank 0 when the SBO instruction is executed and is set to 1 select bank 1 when the SB1 instruction is executed ELECTRONICS 6 7 INSTRUCTION SET INSTRUCTION SET NOTATION S3C84H5X F84H5X_UM_REV 1 10 Table 6 2 Flag Notation Conventions Flag Description lt Zero flag Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one
269. tly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24653 All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives Samsung Electronics Co Ltd San 24 Nongseo Dong Giheung Gu Yongin City Gyeonggi Do Korea 37 446 711 TEL 82 31 209 5238 FAX 82 31 209 6494 Home Page http www samsung com Printed in the Republic of Korea Preface The S8C84H5X F84H5X Microcontroller User s Manual is designed for application designers and programmers who are using the S3C84H5X F84H5X microcontroller for application development It is organized in two main parts Part Programming Model Part Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chap
270. to trigger this operation Timer A also gives you capture input source the signal edge at the TACAP pin You select the capture input by setting the value of the Timer A capture input selection bit in the port 1 control register P1 CONL set 1 bank 0 E9H When P1CONL 5 4 is 00 or 01 the TACAP input or normal input is selected When P1CONL 5 4 is set to 1X normal push pull output is selected Both kinds of timer A interrupts can be used in capture mode the timer A overflow interrupt is generated whenever a counter overflow occurs the timer A match capture interrupt is generated whenever the counter value is loaded into the Timer A data register 18 PROGRAMMING TIP OF TIMER A PAGE 11 11 ORG 0000h VECTOR 0COh TAMC INT VECTOR 0 2 INT ORG 0100h INITIAL DI LD SYM 00h Disable Global Fast interrupt gt SYM LD IMR 0000001 0b Enable IRQ1 interrupt LD SPH 11111111b Set stack area LD SPL 00000000b LD BTCON 1010001 1b Disable watch dog LD P1CONL 0ABH Enable TAOUT output SB1 LD TADATA 80h LD TACON 0100101 0b Match interrupt enable 6 55 ms duration 10 MHz x tal SBO EI 13 ELECTRONICS USER S MANUAL ERRATA S3C84H5X F84H5X_ERRATA_REV 1 10 19 PROGRAMMING TIP OF TIMER A PAGE 11 12 ORG 0000h VECTOR OBEh TBUN INT ORG 0100h INITIAL DI LD SYM 00h Disable Global Fast interrupt LD IMR 00000001b Enable IRQO interrupt LD SPH 11111111b Set stack area LD SPL
271. trol passes to the statement whose address is now in the program counter Otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst RA 3 12 D2 r Ir Given R1 02H R2 03H and register 04H CPIJNE R1 R2 SKIP gt R2 04H PC jumps to SKIP location The working register R1 contains the value 02H the working register R2 the source pointer the value 03H and the general register 03 the value The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location addressed by the CPIJNE instruction must be within the allowed range of 127 to 128 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 DA Decimal Adjust INSTRUCTION SET DA dst Operation dst lt DA dst The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if
272. truction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC Flags No flags are affected Format 1 Bytes Cycles Opcode Addr Mode 2 Hex dst cc opc dst 3 8 ccD DA dst 2 8 30 IRR NOTES 1 The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 In the first byte of the 3 byte instruction format conditional jump the condition code and the OPCODE are both four bits Examples Given The carry C 1 register 00 01H and register 01 20H Secs JP C LABEL_W gt LABEL_W 1000H PC 1000H JP 00 gt 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows unconditional JP The statement JP 00 replaces the contents of the PC with the contents of the register pair and 01H leaving the value 0120H ELECTRONICS 6 47 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 JR Jump Relative JR cc dst Operation If cc is true PC lt PC dst If the condition specified by the c
273. uation chip 53 8410 is in stop mode ELECTRONICS 26 S3C84H5X F84H5X ERRATA REV 1 10 USER S MANUAL ERRATA 0000 0 1 2 7 Low NOTE Smart option is determined by DIP switch Figure 22 3 DIP Switch for Smart Option Address Switch Function 0 Not used Not used 1 2 LVR disable 3FH 7 OFF LVR enable Table 22 3 Clock Source Selection Setting JP10 When to use the external clock from socket Y2 When to use the internal clock from an emulator 27 ELECTRONICS USER S MANUAL ERRATA S3C84H5X F84H5X_ERRATA_REV 1 10 Table 22 4 PWM Enable Disable Setting Jumper Setting Description mmo PWM is disabled during no run is always enabled whether run not J102 INTO TAOUT P1 0 1 Not used INT1 BUZ TACK P1 1 2 Not used INT2 TACAP P1 2 3 L3 Not used INTS T1OUT1 P1 3 4 L3 Not used VDD 5 L3 Not used VSS 6 A Not used XOUT 7 gt L3 Not used XIN 8 9 L3 Not used TEST 2 Not used L3 Not used Xtout 79 Not used nRESET Not used TBPWM T1CKO P2 0 S PS3 T1CAP0 PWM P2 1 P32 T1OUTO ADA P2 2 m L3 P3 1 ADS T1CK1 P1 4 E3 T1CAP1 AD6 P1 5 P0 3 AD3 SI AD7 P2 3 P0 2 AD2 SO P2 4 P0 1 AD1 SCK P2 5 P0 0 ADO Rx P2 6 Avss TX P2 7 L3
274. uency CPU Clock Supply Voltage V Minimum instruction clock 1 4 Oscillator clock Figure 20 8 Operating Voltage Range 20 12 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ELECTRICAL DATA S3C84H5X S3F84H5X Figure 20 9 The Circuit Diagram to Improve EFT Characteristics NOTE To improve EFT characteristics we recommend using capacitor between Vdd and Vss Test and Vss Reset and Vss closely from S3C84H5X F84H5X And you d better also put External crystal closely from S3C84H5X F84H5X ELECTRONICS 20 13 S3C84H5X F84H5X_UM_REV 1 10 MECHANICAL DATA 2 1 MECHANICAL DATA OVERVIEW The SSF84H5X is available in a 30 pin SDIP package Samsung 30 SDIP 400 and 32 SOP package 32 5 450 and 32 SDIP package Samsung 32 SDIP 400 and a 28 SOP package 28 SOP 375 Package dimensions are shown in Figures 21 1 and 21 2 12 00 0 3 8 34 0 2 0 2 4 0 1 0 20 0 05 19 90 02 e a 0 40 0 1 Jo 0 05 NOTE Dimensions millimeters Figure 21 1 32 SOP 450A Package Dimensions ELECTRONICS 21 1 MECHANICAL DATA S3C84H5X F84H5X_UM_REV 1 10 0 75 0 05 3 50 REF DAP SIZE 3 8 3 8 1 4 2 HHH 5 00 0 10 5 2 50 REF UUT e ET 4050 10 0 0 0 05 0 50 0 2050 05 32x
275. unctional Block Diagram 15 8 ELECTRONICS S3C84H5X F84H5X UM REV 1 10 UART UART MODE 0 FUNCTION DESCRIPTION In mode 0 UART is input and output through the RxD P2 6 pin and TxD P2 7 pin outputs the shift clock Data is transmitted or received in 8 bit units only The LSB of the 8 bit value is transmitted or received first Mode 0 Transmit Procedure 1 Select mode 0 by setting UARTCON 6 and 7 to 00B 2 Write transmission data to the shift register UDATA F5H to start the transmission operation Mode 0 Receive Procedure 1 Select mode 0 by setting UATCON 6 and 7 to 00B 2 Clear the receive interrupt pending bit UARTPND 1 by writing a 0 to UARTPND 1 3 Setthe UART receive enable bit UARTCON 4 to 1 4 The shift clock will now be output to the TxD P2 7 pin and will read the data at the RxD P2 6 pin A UART receive interrupt vector E4H occurs when UARTCON 1 is set to 1 Write to Shift Register UDATA IL JL JE JL IL JL dL d RxD Data Out DO D1 D2 D3 D4 D5 D6 07 Transmit TxD Shift Clock Write to UARTPND Clear RIP and set RE RE Shift RxD Data In DO D1 D2 D3 D4 D5 D6 D7 TxD Shift Clock _ _ Figure 15 6 Timing Diagram for UART Mode 0 Operation ELECTRONICS 15 9 S3C84H5X F84H5X UM REV 1 10 UART MODE 1 FUNCTION DESCRIPTION In mode 1 10 bits are transmitted through the TxD P2 7 pin or received through the RxD P2 6 p
276. upt pending bits but the CPU will not service them while interrupt processing is disabled No flags are affected Bytes Cycles Opcode Hex opc 1 4 8F Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value in the register and clears 5 0 to 0 disabling interrupt processing ELECTRONICS 6 37 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 DIV Divide Unsigned DIV Operation Flags Format Examples dst src dst src dst UPPER lt REMAINDER dst LOWER lt QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers Set if the V flag is set and the quotient is between 28 and 29 4 cleared otherwise Z Set if the divisor or the quotient 0 cleared otherwise Set if MSB of the quotient 1 cleared otherwise V Set if the quotient is gt 28 or if the divisor 0 cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM Execution takes 1
277. uration of the oscillator stabilization wait time tywaj 7 when it is released by an interrupt is determined by the settings in the basic timer control register BTCON 20 6 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 ELECTRICAL DATA 4 1 051 5 4 Figure 20 3 Clock Timing Measurement at X Table 20 7 Sub Oscillator Frequency fosco TA 25 85 Vpp 2 5 to 5 5 V Oscar clock Circut Test Condition win Max Unit Crystal XTOUT Crystal oscillation frequency 32 32 768 34 kHz R C1 100 pF C2 100 pF 330 0 1 C2 XTn and are connected j with R and C by soldering Table 20 8 Subsystem Oscillator crystal Stabilization Time TA 25 C Test Condition We NOTE Oscillation stabilization time is the time required for the oscillator to it s normal oscillation when stop mode is released by interrupts ELECTRONICS 20 7 ELECTRICAL DATA S3C84H5X F84H5X_UM_REV 1 10 Table 20 9 Data Retention Supply Voltage in Stop Mode TA 25 C to 85 2 5Vto 5 5 V Parameter Symbo Condiions Wm Um Data Retention Stop mode 2 5 5 5 V Supply Voltage Data Retention IpppR Stop mode Vpppg 2 7 V Supply Current NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads RESET TE
278. ure to include the necessary register file address register pointer information EI S Q Interrupt Request Register Polling RESET R Read only Cycle IRQO IRQ7 Interrupts Interrupt Priority Vector Register Interrupt Cycle Interrupt Mask Register Global Interrupt Control El DI or SYM 0 manipulation Figure 5 4 Interrupt Function Diagram 5 8 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INTERRUPT STRUCTURE PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral see Table 5 3 Table 5 3 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s in set1 Timer B underflow TBCON OH TBDATAH TBDATAL D1H D2H Timer A overflow TINTPND bank 1 Timer A match capture TACON E1H bank 1 TADATA E2H bank 1 TACNT bank 1 Timer 1 0 match capture IRQ2 T1DATAHO T1DATALO E5H bank 1 Timer 1 0 overflow T1DATAH1 T1DATAL1 E6H E7H bank 1 Timer 1 1 match capture T1CONO T1CON1 E8H bank 1 Timer 1 1 overflow T1CNTHO T1CNTLO EAH EBH bank 1 1 T1CNTL1 ECH EDH bank 1 TINTPND bank 1 P1 0 external interrupt IRQ3 P1CONL bank 0 P1 1 external interrupt EBH bank 0 P1 2 external interrupt P1INTPND EAH bank 0 P1 3 external interrupt F3H bank 0 Watch timer interrupt IR
279. user stack pointer the register OOH for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONICS 6 67 INSTRUCTION SET S3C84H5X F84H5X_UM_REV 1 10 PUSHUI Push user Stack Incrementing PUSHUI Operation Flags Format Example dst src IR lt IR 1 dst lt src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 451 src 3 8 83 IR R Given Register 00H register 01H 05H and register 2AH PUSHUI 000 01 gt Register 04H register 01H O5H register 04 05 If the user stack pointer the register OOH for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET Reset Carry Flag RCF Operation Flags Format Example RCF C 0 The carry fl
280. value is automatically cleared to 0 3 Thefxxis selected clock for system main OSC or sub OSC 4 6 ELECTRONICS S3C84H5X F84H5X_UM_REV 1 10 CONTROL REGISTER System Clock Control Register D4H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W Addressing Mode Register addressing mode only 7 5 Not used for the S3C84H5X F84H5X must keep always 0 4 3 CPU Clock System Clock Selection Bits note oppe SOS Gope SOS 2 0 Not used for the S3C84H5X F84H5X must keep always 0 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 ELECTRONICS 4 7 CONTROL REGISTERS S3C84H5X F84H5X UM REV 1 10 FLAGS System Flags Register D5H Set 1 RESET Value X X X X X X 0 0 Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only 7 Carry Flag C Operation does not generate a carry or underflow condition 1 Operation generates a carry out or underflow into high order bit 7 6 Zero Flag 2 Operation result is a non zero value Operation result is zero 5 Sign Flag Operation generates a positive number MSB 0 5 1 Operation generates a negative number 1 4 Overflow Flag Operation result is lt 127 or gt 128 1 Operation result is gt 127 lt 128 3 Decimal Adjust Flag D Add o
281. vse 7 4 2 2 4 H 0 IRQO gt IRQ1 1 IRQ1 gt IRQO Group priority D7 D4 D1 0 Undefined 1 gt gt Group 0 gt gt 0 IRQ2 gt IRQ3 IRQ4 1 1 IRQ3 IRQ4 gt IRQ2 0 gt gt Subgroup 1 gt gt 0 IRQ3 gt IRQ4 0 gt gt 1 IRQ4 gt 1 Undefined Group 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 0 0 0 0 1 1 1 1 5 OO Figure 5 8 Interrupt Priority Register IPR ELECTRONICS 5 13 INTERRUPT STRUCTURE S3C84H5X F84H5X UM REV 1 10 INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ set 1 DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to IRQ1 and so on A 0 indicates that no interrupt request is currently being issued for that level A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instructio
282. w byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location Branch to the service routine specified by the concatenated 16 bit vector address NOTE 16 bit vector address always begins at an even numbered ROM address within the range of NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR Execute an IRET Depending on the application you may be able to simplify the procedure above to some extent ELECTRONICS 5 17 S3C84H5X F84H5X_UM_REV 1 10 INSTRUCTION SET INSTRUCTION SET OVERVIEW The instruction set is specifically designed to support large register files that are typical of most S3C8 series microcontrollers There are
283. x wz gt K 2 o 2 525 9 zee 5 lt 9 2 Figure 19 2 Pin Assignment 32 19 ELECTRONICS USER S MANUAL ERRATA S3C84H5X F84H5X_ERRATA_REV 1 10 26 PIN DESCRIPTION FOR MTP PROGRAMMING Table 19 1 Descriptions of Pins Used to Read Write the Flash ROM Main Chip During Programming P1 2 SDAT 30 32 pin Serial data pin output when reading Input 18 32 ELP when writing Input and push pull output port 28 30 pin can be assigned 26 28 pin P1 3 SCLK 31 32 pin Serial clock pin input only pin 19 32 ELP 29 30 pin 27 28 pin TEST VPP 4 Power supply pin for flash ROM cell writing 24 32 ELP indicates that MTP enters into the writing mode When 12 5 V is applied MTP is in writing mode and when 5 V is applied MTP is in reading mode Option nRESET nRESET 7 27 32 ELP Vpp Vss Vpp Vss 32 1 32 pin Logic power supply pin 20 21 32 ELP 30 1 30 pin 28 1 28 pin 27 TOOL PROGRAM MODE PAGE 19 5 Table 19 2 Comparison of 53 4 5 and S3C84H5X Features Program Memory 16 Kbyte Flash ROM 16K byte mask ROM Operating Voltage Vpp 2 5V to 5 5 V LVR off 2 5 to 5 5 V LVR off LVR to 5 5 V LVR on LVR to 5 5 V LVR on MTP Programming Mode Vpp 5 V Vpp 12 5 V Pin Configuration 32 SDIP SOP ELP 30 SDIP 28 SOP EPROM Programmability User Program multi time Programmed at the factory ex TT ELECTRONICS 20 S3C84H5X F84H5X_ERRATA_REV 1 10 USER S MAN

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