DSP56309UMAD - Freescale Semiconductor
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1. Freescale Semiconductor Inc Updated Programming Sheets For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Updated Programming Sheets For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOW TO REACH US USA EUROPE LOCATIONS NOT LISTED Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 303 675 2140 or 1 800 441 2447 JAPAN Motorola Japan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 TECHNICAL INFORMATION CENTER 1 800 521 6274 HOME PAGE http Awww motorola com semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifi2. 64 GND connections Table 2 3 p 2 7 Change the note at the end of the table to the following Note The subsystem GND signals GNDg GNDa GNDp GNDc GNDy and GNDg are listed for the 144 pin TQFP package For the 196 ball MAP BGA package all grounds except GNDp and GNDp are connected together inside the package and referenced as GND Table 2 8 pp 2 11 to e Change BR signal State During Reset Stop or Wait to 2 12 Reset Output deasserted State during Stop Wait depends on BRH bit setting BRH 0 Output deasserted BRH 1 Maintains last state that is if asserted remains asserted e Change BB signal State During Reset Stop or Wait to Ignored input For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Modified Signal Definitions Area to Change Table 2 11 pp 2 17 to 2 21 Table 2 12 pp 2 22 to 2 25 Table 2 13 pp 2 26 to 2 28 Table 2 14 pp 2 29 to 2 30 Table 2 15 p 2 31 Change Description Change the title of the third column to State During Reset 2 Add the following notes to the end of the table Notes 1 Inthe Stop state the signal maintains the last state as follows If the last state is input the signal is an ignored input If the last state is output these lines are tri stated 2 The Wait processing state does not affect the signal state Change State During Reset or Stop for all signals to Ignored input Change the signal descript
3. C MB MA Reset o o o o lo o o o lo o o o o o i i lolo o o l gt After reset these bits reflect the corresponding value of the mode input that is MODD MODC MODB or MODA respectively SEN Stack Extension Enable ATE Address Tracing Enable MS Memory Switch Mode WRP Extended Stack Wrap Flag APD Address Priority Disable SD Stop Delay EOV Extended Stack Overflow Flag ABE Asynch Bus Arbitration Enable EBD External Bus Disable EUN Extended Stack Underflow Flag BRT Bus Release Timing MD Operating Mode D XYS Stack Extension Space Select TAS TA Synchronize Select MC Operating Mode C BE Burst Mode Enable MB Operating Mode B CDP1 Core DMA Priority 1 MA Operating Mode A CDP0 Core DMA Priority 0 Reserved bit Read as zero write to zero for future compatibility Figure 4 3 Operating Mode Register OMR SCI Receive Register SRX Description Area to Change Change Description Section 8 6 4 1 p Change the beginning of the fourth paragraph from In Synchronous mode to In 8 20 Asynchronous mode Updated Programming Sheets Use the following examples to replace Figure D 2 and Figure D 21 in the DSP56309 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Updated Programming Sheets Application Date Prog
4. Freescale Semiconductor Inc Addendum fe OTOROLA diaitaldna DSP MAD D M g rh a eae intelligence everywhere igita na DSP56309 User s Manual Addendum PONIEN 1 introduction 1 Introduction 1 2 Modified Signal This document provides updated information for revision 0 of the DSP56309 User s Manual Definitions cccee 1 DSP56309UM D The updates include the following 3 Operating Mode ps AET Register OMR Layout Modified signal definitions and Definition 3 New Operating Mode Register OMR layout and bit definitions 4 SCI Receive Register e Updated SCI Receive Register SRX description SRX Description 3 Updated OMR and Timer Registers TLR TCPR TCR programming sheets 5 Updated Programming YA cssssccsussorsscezestes 3 2 Modified Signal Definitions Area to Change Change Description Table 2 1 p 2 3 Change Ground GND to Ground GND Add Note 5 as follows 5 The number of Ground signals listed are for the 144 pin TQFP package For the 196 ball MAP BGA package there are 66 GND connections Figure 2 1 p 2 4 Change HA10 to HA10 Change HRW to HRW Change AAO AA3 to AAO AA3 Change TMS to TMS Change Grounds to Grounds At the bottom of the figure add the following note 4 The GND signals are listed for the 144 pin TQFP package For the 196 ball MAP BGA package all grounds except GNDp and GNDp are connected together and referenced as GND There are
5. cally disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA Motorola and the Stylized M Logo are registered in the U S Patent and Trademark Office dig
6. ion for PB14 to Port B14 When the HI08 is configured as GPIO through the HPCR this signal is individually programmed through the HDDR Change the title for the third column to State During Reset Change State During Reset for all signals to Ignored input Add notes that state Notes 1 Inthe Stop state the signal maintains the last state as follows If the last state is input the signal is an ignored input If the last state is output these lines are tri stated 2 The Wait processing state does not affect the signal state For all signals delete the middle paragraph in the signal description ESSIO does not support keeper circuits For all signals change PCRO to PCRC and PRRO to PRRC Change the title for the third column to State During Reset Change State During Reset for all signals to Ignored input Add notes that state Notes 1 Inthe Stop state the signal maintains the last state as follows If the last state is input the signal is an ignored input If the last state is output these lines are tri stated 2 The Wait processing state does not affect the signal state For all signals delete the middle paragraph in the signal description ESSI1 does not support keeper circuits For all signals change PCR1 to PCRD and PRR1 to PRRD Change the title for the third column to State During Reset Change State During Reset for all signals to Ignored input Add notes that state Notes 1 Inthe Stop state the signa
7. ital dna is a trademark of Motorola Inc All other product or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 1998 2002 DSP56309UMAD D For More Information On This Product Go to www freescale com
8. l maintains the last state as follows If the last state is input the signal is an ignored input If the last state is output these lines are tri stated 2 The Wait processing state does not affect the signal state For all signals delete the middle paragraph in the signal description The SCI does not support keeper circuits For all signals change PCR to PCRE and PRR to PRRE Change the title for the third column to State During Rese Change State During Reset for all signals to Ignored input Add notes that state Notes 1 Inthe Stop state the signal maintains the last state as follows If the last state is input the signal is an ignored input If the last state is output these lines are tri stated 2 The Wait processing state does not affect the signal state For all signals delete the middle paragraph in the signal description The triple timer module does not support keeper circuits pe For More Information On This Product Go to www freescale com 3 4 5 Freescale Semiconductor Inc Operating Mode Register OMR Layout and Definition Operating Mode Register OMR Layout and Definition Area to Change Change Description Figure 4 3 p 4 17 Replace with the following Stack Control Status SCS Extended Operating Mode EOM Chip Operating Mode COM 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEN WRP EOV EUN XYSJATE APD ABE BRT TAS BE cpPit o MS SD EBD MD M
9. rammer Sheet 2 of 5 Central Processor Bus Release Timing Bit 12 Chip Operating Mode Bits 3 0 0 Fast Bus Release mode Refer to the operating modes Asynchronous Bus Arbitration Enable Bit 13 1 Slow Bus Release mode table in Rapier a 0 Synchronization disabled 1 Synchronization enabled External Bus Disable Bit 4 0 Enables external bus Address Attribute Priority Disable Bit 14 1 Disables external bus 0 Priority mechanism enabled 1 Priority mechanism disabled Stop Delay Mode Bit 6 0 Delay is 128K clock cycles Address Trace Enable Bit 15 1 Delay is 16 clock cycles 0 Address Trace mode disabled z 1 Address Trace mode enabled Memory Switeh Mods Bit 4 0 Memory switching disabled Stack Extension X Y Select Bit 16 1 Memory switching enabled 0 Mapped to X memory 1 Mapped to Y memory Core DMA Priority Bits 9 8 Stack Extension Undedlow Flag Bit 17 CPD 1 0 Description ack Extension Underflow Flag Bi o0 Compare SRICP to 0 No stack underflow r PE EN 1 Stack underflow LAA priority Stack Extension Overflow Flag Bit 18 DMA has higher priority than core 0 No stack overflow 1 Stack overflow DMA has same priority as core Stack Extension Wrap Flag Bit 19 DMA has lower 0 No stack extension wrap priority than core 1 Stack extension wrap sticky bit 7 Cache Burst Mode Enable Bit 10 Stack Extension Enable Bit 20 0 Burst Mode disabled 0 S
10. tack extension disabled 1 Burst Mode enabled 1 Stack extension enabled 23 22 21 20 19 18 17 1615 14 13 12 11 10 9 8 7 6 5 43 2 Color EA T AT EA Gaal E e e e TA Synchronize Select Bit 11 0 Not synchronized 1 Synchronized Operating Mode Register Reserved Program as 0 Reset 00030X X latched from levels on Mode pins Figure D 2 Operating Mode Register OMR For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Updated Programming Sheets Application Date Programmer Sheet 3 of 3 23 22 21 20 19 18 17 16 15 1413121110 9 8 7 6 5 4 3 2 1 0 Timer Reload Value Timer Load Register TLRO X FFFF8E Write Only Reset xxxxxx value indeterminate after reset TLR1 X FFFF8A Write Only TLR2 X FFFF86 Write Only 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Value Compared to Counter Value Timer Compare Register TCPRO X FFFF8D Read Write Reset xxxxxx value indeterminate after reset TCPR1 X FFFF89 Read Write TCPR2 X FFFF85 Read Write 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Timer Count Value Timer Count Register TCRO X FFFF8C Read Only Reset 000000 TCR1 X FFFF88 Read Only TCR2 X FFFF84 Read Only Figure D 21 Timer Load Compare Count Registers TLR TCPR TCR For More Information On This Product Go to www freescale com
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