SFPFMC User Manual
Contents
1. 50 000 ajn Not Present 4 Not Presen g Figure 7 2 TDR result from channel 0 RX side 15 May 14 Page 11 Copyright 2014 Design Gateway Co Lid All rights reserved AB15 SFPEMC user manual doc DG File Control Setup Measure Calibrate Utilities Help osan 2014 IEN CN s Param PTR Ca On RA Rise Time 35 ps AHR e More 7 oT Y 10 Ohmidiv TER as jiotPrsent 4 rotresent LS Opsal Figure 7 3 TDR result from channel 1 Tx side le Contra setup Measure Calibrate Utilities Help 09 Jan 2014 14 05 m TOR Cal On RT Rise Time 35 ps Mire 7 4 Y 10 Ohmidiv PE sino 0 f Not Prese Present NotPresen J Figure 7 4 TDR result from channel 1 Rx side 15 May 14 Page 12 Copyright 2014 Design Gateway Co Ltd All rights reserved AB15 SFPEMC user manual doc DG File Control Setup Measure Calibrate Utilities Help Ogan 2014 14140 PTD Cal On Rd Rise Time 35 ps AHR e More 7 oT Y 10 Ohmidiv gene peo JrotPresent 4 rotresent LS Oped Figure 7 5 TDR result from channel 2 Tx side LE st Control setup Measure Calibrate Utilities Help 09 Jan 2014 13 58 a NUMDEr Averages TDR Cal On kti Rise Time 35 ps More 7 oh 4 paces Reactance 629 7185 pi Y 10 Ohmidiv PE i000 0 f Not Prese Present NotPresen J Figure 7 6 TDR result from channel 2 Rx side 15 May 14 Page 13 Copyright 2014 Design2. Gateway Co Ltd All rights reserved AB15 SFPEMC user manual doc Elle Control Setup Measure Calibrate Utilities Help OB Jon 2014 1425 _s param IDR Cal On RA Rise Time 35 ps More 7 oT Y 10 Ohmidiv PENA EA f jno Present Not Presen g 2 200 0 ps div Figure 7 7 TDR result from channel 3 Tx side E e Control setup Measure Calibrate Utilities Help 09 Jan 2014 14 29 Mumper Averages TDR Cal On kti Rise Time 35 ps Mire 7 oh 4 Y 10 Ohmidiv PE i000 0 f Not Prese Present Not Presen J Figure 7 8 TDR result from channel 3 Rx side 15 May 14 Page 14 Copyright 2014 Design Gateway Co Lid All rights reserved AB15 SFPEMC user manual doc DG 8 Board Performance This session is going to give an example of loopback Bit Error Rate BER test to insist that overall performance is not dominated by SFPFMC board KC705 evaluation board and SFP in Figure 4 1 are used in the test with MAP200 Variable Optical Attenuator VOA Figure 8 1 shows the testing diagram We use IBERT Xilinx IP Core to generate PRBS 2 1 as a data pattern MAP 200 SERIES Attenuator TX CHO RX IN CH1 CH2 OUT CH3 IBERT Xilinx IP Core PRBS 31 SFPFMC FMC HPC KC705 Board Figure 8 1 Bit Error Rate testing diagram According to the BER result in Figure 8 2 minimum optical input power
3. AB15_SFPFMC_user_manual doc DG SFPEMC User Manual Rev1 0 15 May 14 1 Introduction Thank you for choosing SFPFMC board Part Number AB15 SFPFMC SFPFMC board is compliant with FMC standard HPC and provides four SFP channels so user can build and evaluate multi channel 10 Gb Ethernet system by connecting SFPFMC to FPGA board The board includes voltage translator to support both 1 8V and 2 5V interface with FPGA Low jitter differential oscillator at 312 5 MHz is mounted on the board to support 10 Gb Ethernet DESIGN GATEWAY amp Company Limited ANU FMC HPC ie Figure 1 1 SFPFMC Board Connection 15 May 14 Page 1 Copyright 2014 Design Gateway Co Lid All rights reserved AB15_SFPFMC_user_manual doc 2 Board Appearance CH3 CH2 CH1 CHO EEFIN EEE f se CORTE T UT ssa ditik Bottom view Top view i Figure 2 1 Both views of SFPFMC Board 61 00003 t 7 33922 34 24998 9 05 _ _ _ _ 9 085 13 995 22 8 9 Figure 2 2 SFPFMC board size mm unit Board specification 4 ch SFP connector which can support up to 10 Gbps 4 bit DIPSW for general input 4 bit LED for general output 256 byte C EEPROM 312 5 MHz oscillator for 10 Gb Ethernet NN 15 May 14 Page 2 Copyright 2014 Design Gateway Co Lid All rights reserved AB15_SFPFMC_user_manual doc 3 Block Diagram Fixed Oscillator 312 5 MHz Tx
4. FaultO_FMC TxFaultO_SFP TxDisableO_ FMC TxDisableO_SFP RSOO_FMC ModABSO_FMC RxLosO_FMC I CO_FMC o RSOO_SFP D T 5 ModABSO_SFP gt F RxLosO_SFP D 2 PCO_SFP p gt lt TXP NO RXP NO Connection through Voltage Translator Direct Connection Connection through Voltage Translator Direct Connection Connection through Voltage Translator Direct Connection I C Bus Address LED 3 0 C Bus Address 256 Byte ti EEPROM a LED 3 0 6 4 bit LED Oo c gt 2 a lt mm IPLock 4 bit DIPSW Figure 3 1 SFPFMC Block Diagram 15 May 14 Page 3 Copyright 2014 Design Gateway Co Lid All rights reserved AB15 SFPEMC user manual doc DG The interface between FMC HPC and SFP connector can be split into two groups i e control status and data The control status signals are connected through voltage translator for compatible to many voltage levels of FMC on each FPGA board The data differential signals are direct connected to transceiver pin of FPGA There are four channel of SFP connector available on the board The signals of each SFP are independent controlled Refer to SFF 8431 Specification Rev 4 1 the description of each control status signals are follows condition related
5. LAO6 P Voltage Translator LAO5 P Voltage Translator LAO4 N Voltage Translator LAO4 P Voltage Translator D11 H11 JO CO IN O OINI CLOCK GBTCLKO_M2C_P CLK_P GBTCLKO_M2C_N CLK_N IPLOCK PGA Direct PGA Direct OR LA29 P IPLO Voltage Translator LA29 N IPL1 Voltage Translator Table 5 1 FMC HPC Pin assignment of AB15 SFPFMC 15 May 14 Page Copyright 2014 Design Gateway Co Lid All rights reserved AB15_SFPFMC_user_manual doc 6 Hardware circuit The circuit diagram of the hardware on FMCSFP board is described as follows 6 1 SFP 3 3V VeeT 1 messes TD SFPO N a TxFahl TD SFPO P RACE TxDis_SFPO i MOD DEF 2 SA SED P MOD DEF 1 TS mS MOD DEF 0 6 MODABS SFPO RS SEPOS TU DEF a RSO SFPO MODABS sFPO ee RD SFPO P pe LOS _SFPO LOS SEPO gt Se gt E RD SFPO N gt Li LN VeeR SFP Connector R75 R76 Omit Omit 0 Ohm 0 Ohm Figure 6 1 SFP connector circuit diagram The details of control status signal are described in Table 3 1 Table 6 1 FMC Signal Description for SFP group 15 May 14 Copyright 2014 Design Gateway Co Lid All rights reserved Page 8 AB15 SFPEMC user manual doc 6 2 EEPROM e Figure 6 2 EEPROM circuit diagram To write read EEPROM the interface is compatible with both 400 kHz and 100 kHz IC bus modes 2 lower bits of 7 bit device address can be set from GAO and GA1 value Bit7 to bit3 are f
6. guarantee transfer soeed performance DesignGateway is exempted from any misoperation under user s original environment Inquiry URL http www design gateway com Email sales design gateway com 10 Revision Histor 15 May 2014 Initial Release 15 May 14 Page 16 Copyright 2014 Design Gateway Co Lid All rights reserved AB15 SFPEMC user manual doc DESIGN GATEWAY c oO L I M I T E D Design Gateway Co Ltd E mail sales design gateway com URL www design gateway com 15 May 14 Page 17 Copyright 2014 Design Gateway Co Ltd All rights reserved
7. ixed to be 10100 value Table 6 2 FMC Signal Description for EEPROM group 6 3 LED DI D2 D3 D4 gt fa fa Ta E77 R78 R79 RS 49 9 49 9 49 9 49 9 Figure 6 3 LED circuit diagram LED signal are active high User set 1 to turn on the LED and set 0 to turn off the LED Four LEDs are available for user to show operation status 15 May 14 Page 9 Copyright 2014 Design Gateway Co Lid All rights reserved AB15_SFPFMC_user_manual doc 6 4 DIPSW Figure 6 4 4 bit DIPSW circuit diagram High logic is generated to FPGA when switch is ON and low logic is generated when switch is OFF 15 May 14 Page 10 Copyright 2014 Design Gateway Co Lid All rights reserved AB15 SFPFMC_user_manual doc DG 7 Board Characteristic SFPFMC board is a controlled impedance board at 100 ohm in order to minimize reflection between FPGA board and SFP transceiver From Figure 7 1 to Figure 7 8 is measured from Agilent 54754A Differential amp Single ended TDR TDT Module which shows characteristic impedance of each differential signal The characteristic impedance varies between 95 to100 Ohm E File Control setup Measure Calibrate Utilities Help 09 Jan 2014 14 21 TOR Cal On RV Rise Time 35 ps Y 10 Ohmidiv 1 25 0 Wav 99 250 a c Devon Asoo Figure T 1 TDR result from channel 0 Le side TOR Cal On RT Rise Time 35 ps 7 ol 1 Y 10 Ohmidiv 25 0 div 25 0 mi PE 50 000 0 2750 000
8. to laser operation or safety assembly on the board to force low value as default value RxLos Out Asse relev rt high to indicate an optical signal level below that specified in the ant standard Table 3 1 SFP Control Status signal description Otherwise the interface of 256 byte IC EEPROM 4 LEDs and IPLock are also connected through voltage translator while 4 bit DIPSW are direct connected 15 May 14 Page 4 Copyright 2014 Design Gateway Co Lid All rights reserved AB15 SFPEMC user manual doc DG 4 Board Connection to FPGA SFPFMC board supports both 1 8V and 2 5V I Os to communicate FMC HPC interface on Xilinx evaluation kit Differential TX and RX signal of SFP on the board are directly connected to the transceiver pins of FPGA Moreover the low jitter oscillator is fed to reference clock of transceiver bank Therefore user can build 10 Gb Ethernet FPGA system with SFPFMC board To support 10 Gb Ethernet high end FPGA model must be selected such as Kintex 7 Virtex 7 and some model of Virtex 6 The examples of supported Xilinx board to evaluate 10 Gb Ethernet are KC705 ZC 706 VC707 and VC 709 evaluation board For SFP user can use either fiber optic or copper type depending on the operating distance and budget cost Figure 4 1 shows the example of SFP transceiver for longer distance 10 km Figure 4 2 shows LC LC duplex single mode patch cord which uses to connect to fiber spool Figure 4 1 SFP Transcei
9. to operate at BER 10 or less for each channel is listed below Channel 0 requires minimun optical input power at 14 25 dBm Channel 1 requires minimun optical input power at 14 88 dBm Channel 2 requires minimun optical input power at 14 78 dBm Channel 3 requires minimun optical input power at 14 53 dBm Ch3 Ch2 Ch1 N O O BER 14 l l 19 18 5 18 17 5 17 16 5 16 15 5 15 14 5 14 Average Received Power dBm Figure 8 2 BER plot from each channel According to Figure 8 2 there are two points that should be taken into consideration First SFPFMC board need at least 14 25 dBm input optical power to operate at BER 10 or less The 14 25 dBm is less than minimum input optical power stated in SFP specification Therefore this performance can be dominated by SFP performance Second althought Channel 1 and Channel 2 s BER curve are better than the others TDR results in Figure 7 1 to Figure 7 8 do not relate BER result Signal may be distorted in signal traces between FPGA and SFPFMC board 15 May 14 Page 15 Copyright 2014 Design Gateway Co Lid All rights reserved AB15_SFPFMC_user_manual doc DG 9 Disclaimer The manufacturer of the product limits liability in following situation or use Any damage to the FPGA evaluation board Any damage to SFP transceiver DesignGateway does not
10. ver SFP transceiver Vendor Finisar Coperation Product Number FTLX1471D3BNL URL http www finisar com products optical modules sfp plus FTLX1471D3BNL Figure 4 2 Fiber optic cable Fiber Optic Cable Vendor Fibertronics Inc Product Number PC KK9D3YV01M URL http www fiberopticcableproducts com 15 May 14 Page 5 Copyright 2014 Design Gateway Co Lid All rights reserved AB15 SFPEMC user manual doc DG 5 Pin Assignment Pin assignment of SFPFMC is listed as follows FMC HPC Pin FMC SFP Board Connection definition signal name SFP Channel 0 SFP Channel 1 A26 FPGA Direct FPGA Direct FPGA Direct FPGA Direct Voltage Translator Voltage Translator G16 Voltage Translator D17 Voltage Translator G15 Voltage Translator Voltage Translator H16 Voltage Translator SFP Channel 2 A22 FPGA Direct FPGA Direct FPGA Direct FPGA Direct Voltage Translator 2 2 NOo ID N Oo SJ Voltage Translator Voltage Translator Voltage Translator Voltage Translator Voltage Translator H14 Voltage Translator CO DO DOD NO 0o 01 AA O Q3 15 May 14 Page 6 Copyright 2014 Design Gateway Co Ltd All rights reserved AB15 SFPEMC user manual doc FMC HPC Pin SFP Board definition signal name SFP Channel 3 DPO C2M P FPGA Direct DPO C2M N FPGA Direct DPO M2C P FPGA Direct DPO M2C N FPGA Direct LA07 P Voltage Translator Connection LAO6_N Voltage Translator LAO5 N Voltage Translator
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