iCEcube2 Tutorial - Lattice Semiconductor
Contents
1. INFO Schematic is from file C SbtTools examples blinkyquck startquck start Implmnt quck start srs Ez Lag v Noa Figure 12 Double clicking on a block will reveal its HDL code in HDL Analyst P amp R Flow This section goes through the post synthesis physical implementation flow Select Implementation In order to ensure that the synthesized design can be successfully imported into iCEcube2 exit the Synplify Pro GUI Return to the iCEcube2 Navigator and Double click on Select Implementation See Figure 13 This will tell iCEcube2 which synthesis implementation to process for place and route If you have different synthesis implementations you will be able to select the synthesis implementation you wish to place and route Since we only have one implementation select OK when the Select Synthesis Implementation dialog box appears ICEcube2 Tutorial www latticesemi com 16 ME SiliconBlue iCEcube2 Output x ak Project Name quick_start 8 x Output Project New Project Open Project Close Project Synthesis Tool 4 Add Synthesis Files De ign Files Constraint Files ef Launch Synthesis Too 4 P amp R Flow 4 e Select Implementation quick 5 rt quick start scf Add P amp R Files Run All gt Import P amp R Input Files Figure 13 Select Synthesis Implementation Importing Physical Constraints esi Implementation Synthesis Implementation Selection Please select the implementation as input t2. C SbtToolsfexamples blinky Gu blinky iceman65 cb284 pcf blinky syn sdc di quick_start File name blinky_iceblink40_vq100 pcf Files of type Constraint sdc scf pcf clb mtd Figure 15 Add pcf file Import Place amp Route Input Files The next step is to import the files for Place and Route Double click on Import P amp R Input Files in the Project Navigator See Figure 16 Once completed you will see a green check next to Import P amp R Input Files See Figure 17 iCEcube2 Tutorial www latticesemi com 18 is LATTICE BEE sEHICONDUETOR YW SiliconBlue iCEcube2 Output File View Tool Window Help 0p o zctcuH Project Name quick start 4 Project New Project Open Project Close Project 4 Synthesis Tool 4 Add Synthesis Files Design Files Constraint Files ef Launch Synthesis Tool 4 P amp R Flow 4 ef Select implementation quick s quick start edf quick start scf 4 AddP amp R Files Design Files IP Design Files Constraint Files Run All gt Import P amp R Input Files 4 Output Files Reports Bitmap Simulation Netlist 4 Device Operating Condition 4 Device Info DeviceFamily iCE40 Device HX1K Device Package VQ100 Power Grade 4 Operating Condition Core Voltage V 114 Temperature C 70 Figure 16 Import P amp R Input files Me SiliconBlue iCEcube2 gt Ele View Tool Window Hep l a x OPAC Project Name quick_start ax Output 4 Proje
3. 9 Aug 2012 syntmp Directory 11 32 26 9 Aug 2012 synwork Directory 11 32 22 9 Aug 2012 quck start edf Edif Netlist 11 32 27 9 Aug 2012 quck start fse fse File 11 32 26 9 Aug 2012 quck start htm htm File 11 32 27 9 Aug 2012 quck start map map File 11 32 27 9 Aug 2012 FSM Compiler quck start sap sap File 11 32 22 9 Aug 2012 Resource Sharing Igi I quck start scf scf File 11 32 27 9 Aug 2012 rz quck start srd Netlist 11 32 27 9 Aug 2012 Netlist RTL 11 32 20 9 Aug 2012 Retiming LJ start Netlist Gate 11 32 27 9 Aug 2012 f srr File 11 32 27 9 Aug 2012 Netlist RTL 11 32 20 9 Aug 2012 quck start szr szr File 11 32 27 9 Aug 2012 quck start scck rpt rpt File 11 32 22 9 Aug 2012 quck start synplify sdc sdc File 11 32 27 9 Aug 2012 tpt icetest areasrr areastr File 11 32 27 9 Aug 2012 rpt icetest areasrrhtm htm File 11 32 27 9 Aug 2012 run options txt bt File 11 32 20 9 Aug 2012 scratchproject prs prs File 11 32 20 9 Aug 2012 Auto Constrain PDPPP Pipelining B quk_start_syn pr Informaten 8x Return Code 1 2 Run Time 00 00 01 Job flow Mapping Flow completed on quck start syn quck start Impimnt Job flow Synthesis completed on quck start syniquck start Impimnt p S TCL Script Messages as je J ca Aca Figure 9 Open the SDC file to View Timing Constraints Synplify Pro E 2011 039811 CISTO E m rst x ID Bie dt View Project Import Run Analysis HDL Analyst Options Windo
4. C iSbtTools examples blinky quck q cai qu TCOL Script Messages cz CM v r Figure 11 Hierarchical RTL View in HDL Analyst If you double click on one of the blocks it will take you to the RTL for that block See Figure 12 15 www latticesemi com iCEcube2 Tutorial ssa LATTICE EEE SEHICONDUCTOA E Synplify Pro E 2011038 9P1 1 e File Edit View Project Import Run Analysis HDL Analyst Options Window Tech Sypport Web Help DtecDoew 5 o4 4 v 60907 9o0953789222239392393595353794 V Sheet 1 of 1 top level of module icetest RTL View quck start Implmnt quck start sre begin OD BOL TOP EDGE cvnto 4 OD BOR J TOP EDGE ovn OD BIT J RIGET EDGE do 10D_BI8_3 RIGHT EDGE do OD B2R BOTTOM EDGE co 4 OD B2 BOTTOM EDGE o 2 838 LEFT EDGE 4 D B3T EFT EDGE 0 UCi caEzonc cogmgusukuns oddgusc YE EX RE BE Sn UN yuyai i RA gt X GURBES L1 sel of entity work clock divider 1hz is unconnected ini 95 Coll 1 Total 5 a Pack start_sy pr ET sbtrooiefexamples binky binky syn sdc quacstart ses C binky vhd Information x Job flow Mapping Flow completed on quck start ayn quck start Impimnt ob flow Synthesis completed on quck start syn quck start Impimnt Note Opening local project RIL file C SbrITools examples blinky quck_start qucek_start_Implment quck start srs Opening cbject source file c sbrtocls examples blinky blinky vhd B TC Script Messages
5. Import P amp R Input Files Information regarding placement P Run Router eeeceeseceeeceusesessscesses seeeesesseeeseeseesceceeeeeescessesseesss e g Clock Summary 4 Output Files re Place complete Bitmap Simulation Netlist 4 Device Operating Condition 4 Device Info DeviceFamily iCE40 Device HXIK Device Package VQ100 Power Grade 4 Operating Condition TTHTTTTTTTTITTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTITIT Core Voltage V 1 14 eset Temperature C 70 Figure 18 Place complete View Floorplanner At this point since placement has been completed you can view the placement of the design by opening the Floorplanner You can open the Floorplanner by going to the menu and selecting Tool gt Floorplanner or you can also select the Floorplanner Icon See Figure 19 iCEcube2 Tutorial www latticesemi com 20 is LATTICE BEE sEHICONDUETOR W SiliconBiue iCEcube2 UR File Edt View 4 Project ax New Project Logic Instance 3 T T Open Project 4 INMUXbfv2110 S8 CARRY L Close Project IN MUXbfv2120 SB CARRY L 4 Synthesis Tool gt IN MUX bfv2 130 SB CARRYL g FI 4 Add Synthesis Files IN MUX bfv 1 6 0 SB CARRY L oorplanner Icon Design Files INMUX bfv170 SB_CARRY_L p Constraint Files 4h IN MUX bfv 1 8 0 SB CARRY L 4 IN MUX bfv 19 0 SB e Launch Synthesis Tool sd A IN MUX bfv 2 5 0 SB CARRY L 4 P amp R Flow IN MUX bfv 2 6 0 SB CARRY L 4
6. blinky whd blinky cm225 pcf blinky_iceblink40_vq100 pcf blinky iceman 5 cb284 pcf a blinky_syn sdc File name blinky vhd Files of type All Files Back Finish cancel Figure 4 New Project Wizard Add Files dialog box After successfully setting up your project you will return to the following iCEcube2 Project Navigator screen shown in Figure 5 ICEcube2 Tutorial www latticesemi com 10 is LATTICE BOS sERICONDUETOR W SiliconBlue iCEcube2 Output _ File View Tool Window Help JG Project Name qukk start 8x 4 Project New Project Open Project Close Project 4 Synthesis Tool 4 Add Synthesis Files 4 Design Files blinky vhd 4 Constraint Files blinky_syn sdc P Launch Synthesis Tool 4 P amp R Flow Add PAR Files 4 Output Files Reports Bitmap Simulation Netlist 4 Device Operating Condition 4 Device Info DeviceFamily iCE40 Device HX1K Device Package VQ100 Power Grade 4 Operating Condition Core Voltage V 114 Temperature C 70 now set Figure 5 iCEcube2 Project Navigator View after Completing Project Set up Synthesizing the design Device information operating conditions are Output Synthesis input files are now added to the project After a successful project setup Double Click on the Synthesis Launch Synthesis Tool icon in the project navigator window See Figure 6 This will bring up the Synopsys Synp
7. 012 y 5y ube0 log es og File 2 ug 2012 Q quck start Implmnt e constraint Directory 11 22 05 9 Aug 2012 outputs Directory 11 22 05 9 Aug 2012 Frequency MHz Auto Constran FSM Compiler Resource Sharing Pipelining Retiming DD auck start syn pri informato mx License checkout synplifypro abt License synplifypro abt node locked Licensed Vendor abt n TCLSoipt Messages cz Y Ka Figure 7 Synplify Pro Graphical User Interface Hit the Run Button to synthesis your design Once synthesis is complete you will see a Done message See Figure 8 ICEcube2 Tutorial www latticesemi com 12 is LATTICE BHE sruicoNbDucTOR B File Edit View Project Import Run Analysis HOL Analyst Options Window Web Help 8 x Bseitusmisimg PAR AYVBBH Zw Ov ssFO SBAS BW dd RR 9 EJ po ra pa Nav Done 0 errors 9 warnings 24 notes ProjectFiles Design Hierarchy Implementation Directory quck s n 1 Blue jCE40 7 Wsbtr xamples blinky guck quck Impimn y quck start syn C SbtTools examples blinky quck_start quck_start_syn prj SIE cto Start VHOL Name Size Type Modified blinky vhd work gt WARNINGS 4 gt NOTES 6 e backup Is Directory 11 32 20 9 Aug 2012 e Constraint 3 coreip Directory 11 32 20 9 Aug 2012 blinky_syn sdc dm Directory 11 32 20 9 Aug 2012 quck start Impimnt 3 sbt Directory 11 22 05 9 Aug 2012 g Directory 11 22 05 9 Aug 2012 iceCube0 log
8. 144 bytes log File 11 29 51 9 Aug 2012 constraint Directory 11 22 05 9 Aug 2012 e outputs Directory 11 22 05 9 Aug 2012 synlog Directory 11 32 27 9 Aug 2012 syntmp Directory 11 32 26 9 Aug 2012 synwork Directory 11 32 22 9 Aug 2012 quck start edf 107 kB Edif Netlist 11 32 27 9 Aug 2012 quck start fse 0 bytes fse File 11 32 26 9 Aug 2012 quck start htm 365 bytes htm File 11 32 27 9 Aug 2012 quck start map 28 bytes map File 11 32 27 9 Aug 2012 quck start sap 2kB sap File 11 32 22 9 Aug 2012 quck start scf 2 kB scf File 11 32 27 9 Aug 2012 quck start srd 16 kB Netlist 11 32 27 9 Aug 2012 FSM Compiler Resource Sharing Pipelining quck start 6 kB Netlist RTL 11 32 20 9 Aug 2012 quck start srm 114 kB Netlist Gate 11 32 27 9 Aug 2012 quck stert srr 34 kB str File 11 32 27 9 Aug 2012 quck start srs 6 kB Netlist RTL 11 32 20 9 Aug 2012 quck start szr 18 kB szr File 11 32 27 9 Aug 2012 quck start scck rpt 811 bytes rpt File 11 32 22 9 Aug 2012 quck start synplifysdc 1kB sdc File 11 32 27 9 Aug 2012 tpt icetest areasrr 8 kB areasrr File 11 32 27 9 Aug 2012 3 rpticetest areasrmhtm 10 kB htm File 11 32 27 9 Aug 2012 B run options 1kB bt File 11 32 20 9 Aug 2012 B scratchproject prs 1kB prs File 11 32 20 9 Aug 2012 Retiming d i B a u B DI D qua start syn prj Informaton 6x Return Code 1 Run Time 00 00 01 Job flow Mapping Flow completed on quck
9. 2 software Synopsys Synplify Pro and the Aldec Active HDL software constitute the iCEcube2 Tool Suite Note The Aldec Active HDL tool is available only in Windows environments Verilog VHDL SD Design Files nplify Pro gen Timing Constraints Post Synthesized VHDL or Verilog Netlists EDIF Netlist Timing Constraints Post P amp R SS Verilog or gt VHDL Netlist SDF 3 Party Simulation Figure 1 The iCEcube2 Design Flow iCEcube2 Tutorial www latticesemi com 6 is LATTICE BRS siNICONDUETOR Design Flow The following steps provide an overview of the design flow using the iCEcube2 Tool Suite 1 Create a new project in the iCEcube2 Project Navigator and specify a target device and its operating conditions Add your HDL Verilog or VHDL design files and your Constraint files to the project 2 Synthesize your design using the Synplify Pro design software This software has been provided as part of the iCEcube2 Tool Suite and can be invoked from the iCEcube2 Project Navigator Within the Synopsys design environment assign your Logic Synthesis Timing and Pin constraints 3 Perform Placement and Routing using the iCEcube2 place and route tools iCEcube2 also supports physical implementation tools such as floor planning allowing users to manually place logic cells and lOs 4 Perform timing simulation of your design using the Aldec Active HDL simulation tool or any industry standa
10. To launch the power estimator go to the menu and select Tool gt gt Power Estimator You can alternatively select the power estimator icon Figure 22 There are multiple tabs in the Power Estimator tool including Summary IO and Clock Domain On the Summary tab change the Core Vdd to 1 2V and make sure all IO voltages are at 2 5V Then hit calculate The estimator will update with power information for both static and dynamic power For more information on using the IO and Clock Domain tabs please refer to the detailed section on the Power Estimator tool in the iCEcube2 software userguide 23 www latticesemi com iCEcube2 Tutorial ssa LAT TICE BRR SEMICONDUCTOR Y Power Estimator Core Vdd V i Dynamic Power Breakdown IO Voltage Core Power mW 2 11817 Left Bank IO Voltage v IO Power mW 4 25 Right Bank IO Voltage V 2 5 ertum pm HE Static Power mW 0 3204 Top Bank IO Voltage V Dynamic Power mW 6 36817 Bottom Bank IO Voltage V Total Power mW 6 68857 Figure 22 Power Estimator Programming the Device In order to program a device you will need to generate a programming file In the project navigator double click on Bitmap Expand the Bitmap section in the Output Files The section is now populated with hex and bin files The hex files are used for programming the external SPI Flash on Lattice iCE evaluation kit The iCE40 configures itself from the SPI Flash You are now r
11. ct New Project Open Project Close Project Synthesis Tool 4 Add Synthesis Files Design Files Constraint Files ef Launch Synthesis Tool 4 PER Flow 4 ef Select Implementation quick s MENTE RENEA DEAK FR Ce IP STEN oid AM spe ai quick start edf i quick start scf 4 Add P amp R Files Design Files IP Design Files 4 Constraint Files blinky iceblink4O vq100 pcf Run All f import PAR Input Files gt Run Placer 4 Output Files Reports Bitmap Simulation Netlist 4 Device Operating Condition 4 Device Info DeviceFamily iCE40 Device HX1K Device Package VQ100 Power Grade 4 Operating Condition Core Voltage v 1 14 Temperature C 70 edif parser succeed Figure 17 Successful Import of P amp R Input Files 19 www latticesemi com iCEcube2 Tutorial A LATTICE NsrwicoNDUCTOR Place the Design Double click on Run Placer Once placement is complete a green check will appear and the Output window will show information about the placement of the design See Figure 18 ME SificonBlue iCEcube2 Jose file View Tool Window Help Ae SAE Project Name quick start 8x Output 4 Project New Project Open Project Close Project 4 Synthesis Tool 4 Add Synthesis Files Design Files Constraint Files e Launch Synthesis Tool 4 P amp R Flow 4 ef Select Implementation quick s quick start edf quick start scf 4 Add P amp R Files Design Files IP Design Files 4 Constraint Files blinky iceblink40 vq100 pcf Run All
12. d party programmer user manual for instructions e he iCEblink and iCEman evaluation Boards which not only serves as a vehicle to evaluate ICE FPGAs but also includes an integrated device programmer This programmer can be used to program devices on the evaluation boards or it can be used iCEcube2 Tutorial www latticesemi com 4 is LATTICE BRS sENICONDUETOR to program devices in a target system Please visit Lattice Semiconductor website Nttp www latticesemi com for additional information on the Evaluation Boards Digilent USB cables The iCE Programming hardware iCEcable iCEprog Programmer base module and iCEsab socket adaptor Refer to lattice website http www latticesemi com for more details on programming hardware www latticesemi com iCEcube 2 Tutorial ssa LAT TICE EEE SEHICONDUCTOA Overview ICEcube2 Tool Suite The iCEcube2 Tool Suite is comprised of several integrated components running under either the Microsoft Windows or the Red Hat Linux environments Please refer to Platform Requirements for additional information on supported operating systems The Figure 1 below depicts the design flow using the iCEcube2 Tool Suite The components in blue signify functionality supported by Lattice Semiconductor s proprietary iCEcube2 software and the components in purple indicate the functionality supported by Synopsys Synplify Pro synthesis tools and the Aldec Active HDL simulation tool The iCEcube
13. eady to program an iCE40 FPGA device with the generated bitmap Invoke the programmer from the Programming icon which is now enabled in the Project Navigator Alternately you may invoke it from the Tool gt Programmer menu item To program the Lattice iCEblink40 board select iCEblink40 from the Programming Options dropdown menu and select M25P10A for the External Serial Flash PROM See Figure 23 For more details on programming the iCEblink40 evaluation kit refer to Evaluation Kit s User s Guide Click on the image file settings button to ensure you latest hex file is selected as shown in Figure 24 Additional details on programming a device are provided in a separate section Programming the Device in section CEcube2 Physical Implementation Tools of the iCEcube2 software usage guide ICEcube2 Tutorial www latticesemi com 24 is LATTICE BEE sEHICONDUETOR Ej Programmer Programming Options Programming Hardware iCE Cable iCEblink40 External SPI Serial Flash PROM Image Image Type Single Image Multiple Images Figure 23 Programmer Graphical User Interface ColdBoot WarmBoot Setup Programming File and Address Format Start Address Hex 0 Raw Hexadecimal Ter life bilmap hex P Intel MC5 85 hexadecmal Save Project Load Project Figure 24 Image File Settings 25 www latticesemi com iCEcube2 Tutorial
14. ef Select Implementation quick 5 d IN MUX bfv 2 7 0 SB CARRY L quick start edf d INMUX bfv280 SB CARRY L quick start scf QE Divider to 1HzCOUN SB OFF 4 Add PAR Files 4h DIVIDE 32MHz uni C SB CARRY Design Files 4h DIVIDE 32MHz COUN 58 CARRY IP Design Files PMOO LEFT ROTATE SB LUT4 m 8 OMDE_32MHz unl_C B_LUTS Divider to 1Hz COUN SB_LUT4 DIVIDE 32MHz COUN SB 4 Constraint Files blinky iceblink4O vq100 pcf Hin tesa ra 1 posit amp DIVIDE 32MHz COUN SB DFFSR LA Import P amp R Input Files Divider to 1Hz un2 c SB LUT4 im Run Placer gt 4 DIVIDE32MHz unl C SB CARRY D gt Run Router A DIVIDE 32MHz unl C SB CARRY D gt Generate Bitmap 8 PMOD RIGHT ROTATE SB_DFFR 4 Output Files 4h Divider to lHz un2 c B CARRY Reports DIVIDE 32MHz unl SB LUT4 Bitmap PMOD_RIGHT ROTATE SB_LUTS Divider_to_1Hz un2_c SB CARRY _ 4 DIVIDE 32MHz COUN SB CARRY i 4 Device Operating Condition DIVIDE 32MH COUN SB DFFSR 4 Device Info PMOD LEFTROTATE 6 SB_DFFR DeviceFamily 1CE40 4h DIVIDE 32MHz COUN SB CARRY Device HX1K 4 DIVIDE_32MHz COUN SB CARRY Device Package VQ100 PMOOD RIGHT ROTATE SB DFFR a Power Grade 4 DIVIDE 32MHz unl C SB CARRY 4 Operating Condition C m E b Core Voltage V 1 14 Loge GIO Gobal RAM Net Grow Temperature C 70 World View 8x E LI Figure 19 Floorplanner View the Package Viewer You can also see how pins were
15. emperature C Figure 2 Create a New Project The first step is to create a new design project and add the appropriate design files to your project You can create a new project by either selecting File gt New Project from the iCEcube2 menu or by clicking the Create a New Project icon as seen in Figure 2 The New Project Wizard GUI is displayed in Figure 3 ICEcube2 Tutorial www latticesemi com 8 is LATTICE BOS sruicoNbDucr oR YE New Project Project Project Name qucik start Project Directory C SbtTools examples blinky Device Device Family iCE40 Device Device Package VQ100 Operating Condition Ambient Temperature in degrees Celsius Range Best Commercial O Core Voltage V Voltage Tolerance Range Best 5 datasheetdefau v 1 26 IOBank Voltage V topBank 2 5 leftBank rv Perform timing analysis based on Best Q Worst Start From Synthesis Start From BackEnd F IF Generation Figure 3 New Project Setup Form This example is targeted for iCE40 family device Follow the following steps to setup the project properties 1 Project Name Field Specify a project name quick_start in the Project Name field 2 Project Directory Field Specify any directory where you want to place the project directory in the Project Directory field 3 Device Family Fields This section allows you to specify the Lattice iCE device family you are targeting For this example change the Device Fam
16. iCEcube2 Tutorial cas LAT TICE NEN SEMICONDUCTOR ssa LATTICE HE SERHICORNDUCTOR Copyright Information Copyright 2007 2012 Lattice Semiconductor Corporation All rights reserved All Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi com legal Synopsys and Synplify Pro are trademarks of Synopsys Inc Aldec and Active HDL are trademarks of Aldec Inc All other trademarks are the property of their prospective owners All specifications are subject to change without notice Notice of Disclaimer This software is provided to you as is without any express or implied warranty Contact Information Lattice Semiconductor Corporation 5555 N E Moore Court Hillsboro Oregon 97124 6421 United States of America Tel 1 503 268 8000 Fax 1 503 268 8347 www latticesemi com Revision History The following table lists the revision history of this document Version Revision Release iCEcube2 2010 03 iCEcube2 Tutorial www latticesemi com 2 is LATTICE BRR siniIcCONDUETOR www latticesemi com iCEcube 2 Tutorial ssa LATTICE HE SERHICORNDUCTOR Preface About this Document The iCEcube2 Tutorial provides ICE FPGA designers with an overview of the software tool and the design process using iCEcube2 This document covers the iCEcube2 tools for Project Setup Navigation and Physical Implementation on the iCE40 FGPA device For information on the S
17. ily to iCE40 4 Device Fields This section allows you to specify the Lattice device and package you are targeting For this example change the Device to HX1K and change the device package to the VQ100 9 www latticesemi com iCEcube2 Tutorial A LATTICE EE SEMICONDUCTOR 5 Operating Condition Fields This section allows you to specify the operating conditions of the device which will be used for timing and power analysis The IO Bank Voltage option shown in Figure 3 is not available for iCE65 family devices 6 Start From Synthesis This option allows you to start the flow from Synthesis using Synopsys oynplify Pro tool For current example select this option 7 Start From BackEnd This option allows the user to start from Post Synthesis flow 8 Click Next to go to the Add Files dialog box shown in Figure 4 You will be prompted to create a new project directory Click Yes 9 In the Add Files dialog box navigate to iCEcube2 installation directory gt examples blinky Highlight the following files blinky vhd blinky syn sdc Select each file and click gt gt to add the selected file or click gt gt gt to add all the files in the open directory files can be removed using and to your project Click Finish to create the project The SDC file is a Synopsys constraint file which contains timing constraint information FE Add Files Files to add Look in C SbtTools examples blinky blinky_syn sde
18. lify Pro synthesis tool s graphical user interface See Figure 7 11 www latticesemi com iCEcube2 Tutorial ssa LATTICE HEI SERHICONDUCTOA W Siconiive Licube OE to n D Sie Yew ke Window Help ieix J LC Project Mane quack start 5x o7 Proja New Project Open Frosect Chose Proyect 4 Synthesis Tool 4 Add Synthesis Fles Design F es blnicy hd Contra Files binky syn ide Double click on Launch b r gt p lt q Synthesis Tool Add PAR Files Output Fiet Reports Bfmao Serda Netin LI Device Operaeng Condon Dence info Devceramdy X E40 Deve WOK Dente Package vQIOO Power Grade Operating Condica Core Voltage V Lia Temper ature C 70 Figure 6 Launch Synthesis Tool Synplify Pro E 20110 TC s ex E B File Edit View Project Import Bun Analysis HDL Analyst Options Window Web Help ax Bt R See DAR MVORO Sm OS BE da td cl dad Er PR RR Synplify Pro Run Ready Search Solvitet ProjectFies Design Hierarchy Implementation Directory j k start quck start Implmnt S con Blue iCE40 ICEA0HX IK VQ100 n gt m gt C GbtTooks examples binky quck_start quck_start_Impimnt io C SbtTools examples blinky quck_start quck_start_syn prj VHDL Name Size Type Modified ii blinky vhd work st Directory 11 22 05 9 Aug 2012 Constraint g Directory 11 22 05 9 Aug 2012 Ell blinky syn sdc B icecubedlo 144 byt log Fil 11 29 51 9 Aug 2
19. o PER quick start Implent LATTICE BOR sruicoNbpucr oR Physical constraints such as pin assignments are stored in a PCF file Physical Constraint File Add the PCF file to your project In the iCEcube2 Project Navigator Right Click on Specify Additional Files Select Add Files See Figure 14 Note For information on importing physical constraints from iCEcube to iCEcube2 please refer to the Importing Physical Constraints from iCEcube to iCEcube2 section in the iCEcube2 software user guide 17 www latticesemi com iCEcube2 Tutorial A LATTICE NsrwicoNDUCTOR W SiliconBlue iCEcube2 Output om File View Tool Window Help m Project Name quick start ax Output 4 Project New Project Open Project Close Project 4 Synthesis Tool 4 Add Synthesis Files Design Files Constraint Files ef Launch Synthesis Tool 4 P amp R Flow ef Select Implementation quick s 4 Add P amp R Files Design Files IP Design Files Constraim ciae Run All Add Files gt Import P amp R Input Files Output Files Reports Bitmap Simulation Netlist 4 Devce Operating Condition 4 Device Info DeviceFamaly 1CE40 Device HX1K Device Package VQ100 Power Grade 4 Operating Condition Core Voltage V 1 14 Temperature C 70 Add files Figure 14 Specify Additional Files for Place and Route Navigate to the lt iCEcube2 Installation Directory gt examples blinky and Add blinky pcf file See Figure 15
20. ock Name Worst Slack ps FMAX MHZ Target Frequency MHZ Failing Path Fil Design Files CLK 32KHz 31247472 395 62 Constraint Files f Launch Synthesis Tool 2 CLK 32MHZ 26753 222 36 4 P amp R Flow 4 f Select Implementation quick s quick start edf 4 clock divider 32M 998315 quick start scf 4 Add P amp R Files Design Files IP Design Files 4 Constraint Files blinky iceblink4O vq100 pcf Run All e Import P amp R Input Files f Run Placer e Run Router lr i gt Generate Bitmap 4 Output Files Reports Start Point End Point Slack Delay Launch Clock Capture Clock Bitmap Simulation Netlist 4 Device Operating Condition 4 Device Info DeviceFamily Device 3 clock divider 1Hz 998599 Critical Path 1 1 Divider to 1Hz Divider to 1Hz 31247472 1947 CLK 32KHz R CLK 32KHzR Device Package VQ100 Power Grade 4 Operating Condition Core Voltage V 1 14 Temperature C 70 Ln1 Coll Figure 21 Timing Analysis Summary You can see from the timing analysis that our 32 KHz design is running at over 395 62 MHz and our 32 MHz clock is running at over 222 36 MHz worst case timing If we were not meeting timing the timing analyzer will allow you to see your failing paths and do a more in depth analysis For this tutorial we won t go into details on timing slack analysis See iCEcube2 software usage guide for details on timing analysis Perform Power Analysis iCEcube2 also comes with power estimator tool
21. placed for your design by selecting the Package Viewer You can select the package viewer by going to the menu and selecting Tool Package Viewer or you can also select the Package Vierwer Icon See Figure 20 21 www latticesemi com iCEcube2 Tutorial ssa LATTICE HSEHICONDUCTOR Edit View Tool Window Help De FE RE si rH os Q O Project Name quick start ax Output Package View 4 Project Port ax Package Pin Legend New Project Name Direction PIO Open Project PMOD B3T Output PIO GBIN cue Pet PMOD_B2R Output o o s o e e o o n e e A m e e e IC e o o o o u O SPLSUSPI SO SPL SCK SPL SS B 4 Synthesis Tool PMOD BOR Output e d d H E GND 4 Add Synthesis Files PMOD_B3B Output i EUH EA ia ig iaia Ge la i i r1 j i 5 B vcc Design Files PMOD BIT Output i rd i i i i dtd i i 4 L d i lll vccio vbDIo sPI Constraint Files PMOD B1B Output D a RE RR HG 3 CDONE CRESET_B DRESET_B Launch Synthesis Tool PMOD BOL Output 4 I O S S i rot ot bt 072 MI vPP VDDP 4 PAR Flow me se poppe be perp bee beet ee i Output 49 Seled Implementation quick s 2 SW3 7 n pack startad fl CLK 32 Input quick_start scf nm CLK 32 4 Add P amp R Files D sw Design Files IP Design Files 4 Constraint Files blinky_iceblink40_vq100 pcf Run All lt Import P amp R Input Files Run Placer 4 Run Router e Bitmap Input Input 4 buses es Reports B D Il SP E BRR eee o
22. rd HDL simulation tool The files necessary for simulation are automatically generated by the iCEcube2 Physical Implementation tools after the routing phase 5 Perform Static Timing Analysis using the iCEcube2 static timing analyzer 6 Generate the device programming and configuration files from the iCEcube2 Physical Implementation tools 7 Program your device using the device programming hardware provided by Lattice Tutorial This chapter provides a brief introduction to the iCEcube2 design flow The goal of this chapter is to familiarize the user with the fundamental steps needed to create a design project synthesize and implement the design generate the necessary device configuration files and program the target device Creating a Project otarting the iCEcube2 software for the first time you will see the following interface shown in Figure 2 www latticesemi com iCEcube 2 Tutorial as LATTICE SER BEE SEMICONDUCTOR 4 Project New Project Open Project Close Project 4 Synthesis Tool 4 Add Synthesis Files Design Files Constraint Files D gt Launch Synthesis Tool 4 P amp R Flow gt Select Implementation gt Add P amp R Files Run All D Import P amp R Input Files D Run Placer D Run Router gt Generate Bitmap IP Exporter 4 Output Files Reports Bitmap Simulation Netlist 4 Device Operating Condition 4 Device Info DeviceFamily Device Device Package Power Grade 4 Operating Condition Core Voltage V T
23. rk nQ iii ii ii dii di ii i i di s6 m Q ES Simulation Netlist 4 Device Operating Condition 4 Device Info DeviceFamily iCE40 Device HX1K 54 Device Package VQ100 Power Grade Core Voltage V 1 14 Temperature C 70 39 40 41 42 3 44 45 46 4 Operating Condition OOOOONNGGNOORNOOOUUGGNGON iCE40HX1K VQ100 Figure 20 Package Viewer Route the Design Double click on Route in the project navigation window Place and Route have been separated into different steps as to allow you to re route the design after making placement modifications in the floorplanner without having to re run the placer Perform Static Timing Analysis Now that you have routed the design you can perform timing analysis to check to see if the design is meets your timing requirements To launch the timing analyzer go to the menu and select Tool Timing Analysis You can also select the Timing Analysis Icon See Figure 21 ICEcube2 Tutorial www latticesemi com 22 is LATTICE HE sERICONDUETOR B File View Tool Window Help D ode e _Tming Analysis Icon Project Name quick start 5 Output Floor Planner icetest_sbt rpt Timing Analyzer 4 Project i Project Clock summary Clock Relationship Summary Datasheet Analyze Paths Timing Corner Generate timing report and sdf Full Screen Mode Open Project Close Project 4 Synthesis Tool Save Summary ze Columns 4 Add Synthesis Files Cl
24. start syn quck start Impimnt Job flow Synthesis completed on quck start syn quck start Impimnt cj a TCL Soipt Messages MO EA Ka Figure 8 Status showing synthesis has been completed View Timing Constraints Double Click on the blinky_syn sdc file under the Constraint folder See Figure 9 It will open the timing constraints for the project shown in Figure 10 13 www latticesemi com iCEcube2 Tutorial ssa LATTICE P File Edit View Project Import Run Analysis HDL Analyst Options Window Web Help Ji x i bseiun pis6mg E 00490 V 9 S 90 952728 5293 3 9 9 4X k EJ oo F9 fa F PI 3 3 Synplify Pro Done 0 errors 9 warnings 24 notes Search Solvtiet Project Files Design Hierarchy Implementation Directory quck start syn quck start Implmnt Sikcon Blue iCE40 ICES0HX IK VQ100 E BI quck start syn CASbtToole examples blinky quck start quck start syn prj Cvm an PV Vat vid IN VHDL Name Size Type Modified _ d blinkyvhd work WARNINGS 4 NOTES 6 3 backup Directory 11 32 20 9 Aug 2012 n Constraint coreip Directory 11 32 20 9 Aug 2012 E blinky syn sdc 9 dm Directory 11 32 20 9 Aug 2012 quck start Impimnt 3 sbt Directory 11 22 05 9 Aug 2012 B G Log Directory 11 22 05 9 Aug 2012 E iceCubed log 144 bytes log File 11 29 51 9 Aug 2012 A constraint Directory 11 22 05 9 Aug 2012 outputs Directory 11 22 05 9 Aug 2012 Open the SDC file H 16 68 synlog Directory 113227
25. w Tech Support Web Help m E D ge5s5iuug oO ws un uNYufg9e os9rw s 2 9 57H99 o 3333589 9 n r st Db Elo Pfafap 3 S CUK JKH n Divider_to_1Hz COUNTER neDivider_to_1H COUNTERI9 CIK 32KHz 0 032 31250 defauit_cikgroup_0 defauit_cikgroup_1 defauit_cikgroup_2 defauit_cikgroup_3 default cikgroup 4 CLK 32MHZ CLK 32MHZ Timing constraints Click on Project tab to return to project GUI L g Ote Monaten 5 Return Code 1 e Rum Time 00 00 01 Job flow Mapping Flow completed on quck start synaiquck start Impilmet Job flow Synthesis completed on quck start syniqock start Implast a o TA Sopt Messages oI v s Figure 10 View Timing Constraints iCEcube2 Tutorial www latticesemi com 14 is LATTICE HE sruicoNbucr oR Viewing Hierarchical View of Synthesis Results Under the HDL Analyst menu Select RTL gt Hierarchical View You will see a hierarchical RTL view of the design just synthesized See Figure 11 EEE UNE A eu L View Jquek start Impimnt quek start srs PU File Edit View Project mport Bun Analysis HDL Analyst Options Window Tech Support Web Help PX D s 5 2g PARP BOBYVRBoORwseOvevuyFeer amp BRQSQSsa Wa da i Instances 6 e Ports 1 H Nets 13 gt 53 Clock T P quek_start_sm 0r JSbtToois examples binky binky _syn sde quck_start srs Intormero mx me e PP p Iquck rt Impl low Xp quck Impimnt bs Opening local project ATL file
26. ynopsys Synplify Pro software please refer to the Synplify Pro documentation provided in the synpro doc directory in the iCEcube2 software installation icecube2 install dir synpro doc and on the Lattice website For information on the Aldec Active HDL design tool please refer to the Active HDL documentations available at icecube2 install dir gt Aldec Active HDL BOOKS or Active HDL product help which can be invoked from the help menu in the software tool For detailed information of the iCEcube2 development tools please refer to the iCEcube2 User Guide Software Version This tutorial is based on iCEcube2 Software Version 2012 06 For more information about acquiring the iCEcube2 software please visit the Lattice Semiconductor website http www latticesemi com Platform Requirements The iCEcube2 software can be installed on a platform satisfying the following minimum requirements A Pentium 4 computer 500 MHz with 256 MB of RAM 256MB of Virtual Memory and running one of the following Operating Systems e Windows 7 OS 32 bit 64 bit e Windows XP Professional e Red Hat Enterprise Linux WS v4 0 For installation help refer to iCEcube2 Install overview document please visit the software documentation webpage Programming Hardware Here are the following ways to program iCE FPGA devices e A third party programmer using the programming files generated by the iCecube2 Physical Implementation Tools Consult the thir
Download Pdf Manuals
Related Search