UM1653 User manual - STMicroelectronics
Contents
1. 37 Microcontroller 38 USB Full Speed 38 USB High Speed 39 Touch Screen schematic 39 TFT Connector schematic 40 Power schematic 40 Flash 41 Flash Signals 42 JTAG schematic o TR ey aie Re a ENSE Cadeau rp s 42 Topside of PCBs eg Rad Sees Re 43 Bottom side of PCB 43 DoclD025024 1 5 45 STM32 NAND driver blocks UM1653 1 1 6 45 STM32 NAND driver blocks This document describes how to connect a NAND Flash device to an STM32 family microcontroller and communicate using FSMC NAND driver library for STM32 is a generic library where STM32 can access NAND with some advanced features like garbage collection wear leveling bad block management ECC checking etc The library supports both FAT file system and USB MSC device Figure 1 Application architecture ECC Error correction code BBM2. SC H E E n eee eee eee 4 DoclD025024 1 43 45 Revision history UM1653 4 44 45 Revision history Table 58 Document revision history Date 28 Nov 2013 Revision 1 Initial release Changes DoclD025024 Rev 1 4 UM1653 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products
3. STM32F103ZET6 pos FX S Sd STM32F205ZET6 pir STM32F405ZGT6 TSMC INTS v1 G6 FSMC INT2 ws Es 8 x I S sun 086 OUT id PO FSMC D 8 vss_8 GND Son EX CN p E I FOMC 208 5 PD8_FSMC_D13 Pats HE ne un pe E 9912 076 48 06 vore SISPRPPRRPRROORRREPRRRODPPPREPRROS 47 Tt iil c5 x Sur Four rour 925 3 d For STM32F10xx o A Mount R1 R8 R11 8 58 888 5858 888 amp 8 2985584 332 883 22434454 Caw s g 226 g og gg PERO For STM32F2xxx 8 5 32 4 5 5 55 ui Mount R3 R9 2 2 85 z DNM R1 R8 R11 Z BE 5 Kono conv Tras 2 5 for on ow ce om oor itr foon toone Ee e toon foon inr 1 qw lt 4 CONN Trucs MS33224V1 Figure 14 USB Full Speed schematic R14 USB gt 5 1 5k USB5V FS 1 SHELL 2 USBDM SHELL 2 lt 3 USBDP SHELL H a 5710 SHELL M USB GND M USB TYPE PA9 FS VBUS USB 4 PA11_OTG_FS_DM_USB gt ER 1M em PA12 OTG FS DP USB VER PA10
4. 23 Table 23 24 Table 24 UpdateWearLevelCounter 24 Table 25 ConvertPhyAddress 24 Table 26 mrs 24 Table 27 58 _ _ s 25 Table28 25 29 GetParity essen LIRE ads 25 Table 30 SWAP uk ee oe Pe 25 Table 31 2 2 2 1 4 2 4 1 164 26 Table32 5 s 26 Table 33 WritePage 26 Table 34 27 Table 35 _ _ eee eee 27 Table 36 LBLK 1 2 1 27 Table 37 BitGount e 27 Table 38 5 2 28 Table 39 FSMC NON ONFI 28 Table 40 __
5. 619 819 E LONVN uno AA IGNVN Seu MS33230V1 41 45 DoclD025024 Rev 1 NAND evaluation board UM1653 42 45 Figure 20 NAND Flash Signals schematic PD14 FSMC DO 15 FSMC D1 FSMC 02 PD1 FSMC 03 FSMC 04 PE8 FSMC D5 PE9 FSMC D6 PE10 FSMC D7 PD11 FSMC ADDR A16 12 FSMC ADDR A17 PD4 FSMC NOE PD5 FSMC NWE PD7 FSMC NCE2 PG9 FSMC NCE3 PG6 FSMC INT2 PG7 FSMC INT3 PD6 FSMC NWAIT J3 GND 3V3 GND CON20 MS33231V1 Figure 21 JTAG schematic 4 JTAG JNTRST 3V3 JTCK DBA TAG_INTRST PA14 JTAG JTCK PB3 JTAG JTDO gt gt JTAG NRST NRST R15 R16 R17 R18 PATS JTAG JTMS PA13 JTAG JTMS 10k 10k 10k 10k PA15 JTAG JTDI J5 R23 1 3V3 0 2 3 PB4 JTAG JNTRST 24 4 Ok 5 PA15 JTAG JTDI 6 7 PA13 JTAG JTMS NRST 5 9 1 9 PA14 JTAG JTCK 10 4 11 12 4 13 PB3 JTAG JTDO 14 4 15 NRST R37 16 4 10k 17 DBGRQ R3 18 4 1 19 DBGACK 20 4 1 JTAG_CONN MS33232V1 DoclD025024 Rev 1 Ly UM1653 NAND evaluation board 3 3 NAND evaluation board images Figure 22 Top side of PCB 22211222 2544224 DEMO BOARD ONLY FOR EVALUATION PURPOSE Figure 23 Bottom side of PCB OG
6. 16 2 4 Bad block management 17 2 5 Look up table LUT 17 2 6 Pile s ica d EROR eee RC Rea uc eee cR 17 2 7 NAND driver files 19 2 7 1 drv c nand_drv h functions 19 2 7 2 fsmc if c fsmc if h functions 28 2 8 Supported Flash 34 3 NAND evaluation board 35 3 1 Working with evaluation boards 35 3 1 1 Running in USB Mass Storage mode STEVAL CCM006 7 8V1 36 3 1 2 Running in Standalone mode STEVAL CCMO006 7 8V2 37 3 2 5 es 38 3 3 evaluation board images 43 4 Revision 44 2 45 DoclD025024 Rev 1 Ky UM1653 List of tables List of tables Table 1 Spare area format for small 9 Table 2 Spare area format for large 9 Table 3 File system interface 5 17 Table 4 PEND a 19 5 NAND
7. FS ID USB gt AER 1 D3 GND VBUS 3 vo2 4 AR gt USBLC6 2P6 E MS33225V1 38 45 DoclD025024 Rev 1 UM1653 NAND evaluation board Figure 15 USB High Speed schematic R43 10K cas 4TuF HS ULPI 00 OTG HS D1 PB1 OTG HS ULP D2 12K PB10 OTG HS ULP D3 DATAS Reis 2 USBSV HS 1 li PB11 OTG HS ULPI D4 DATAS 4 RO is USB PB12 OTG HS ULP D5 DATAS DM USBDM PB13 HS ULPI D6 18 DATAS pp LZ PB5 OTG HS ULP D7 17 5 K im 2752 gt gt gt usB3300 N ba XTAL1 280 558 T T gage puo v2 RS 9 24MHz 5559 7 cas XTAL2 BERT she 5 lt MS33226V1 AGND AGND C31 C32 C33 C34 2pF 2pF 2pF 2pF a R57 gt AGND GND N I2 o I2 0 2 2 9 lt lt 1 2 n TSC XR 13 m z z 5 85 12 INO 2 lt 3V3 aaa 14 8 BEAD TSC YU 18 v 3 3 C37 dub STMPE811 vee La 100nF C39 C40 spar SD
8. Table 39 FSMC_NAND_NON_ONFI_Compliance Function name FSMC_NAND_NON_ONFI_Compliance Prototype void FSMC_NAND_NON_ONFI_Compliance void Selects the NON ONFI NAND Type amp sets the Required Parameter accordingly NAND may be SBLK_NAND or LBLK_NAND Behavior description Input parameter None Output parameter None Table 40 Function name FSMC NAND Init Prototype void Init void Configures the FSMC and GPIOs to interface with the NAND memory This Benavior description function must be called before any write read operation Input parameter None Output parameter None Table 41 FSMC NAND ReadID Function name FSMC NAND ReadID Prototype void FSMC NAND ReadID NAND IDTypeDef Behavior description Reads NAND memory s Manufacturer and Device ID Input parameter NAND_ID pointer to a NAND IDTypeDef structure Output parameter None 28 45 DoclD025024 Rev 1 Ky UM1653 NAND driver firmware modules 4 42 FSMC NAND WriteSmallPage Function name FSMC NAND WriteSmallPage Prototype uint32 t FSMC WriteSmallPage uinta t pBuffer NAND ADDRESS Address uint32 t NumPageToWrite Behavior description Writes one or several 512 Bytes Page size Input parameter pBuffer pointer on the Buffer containing data to be written Address First page address NumPag
9. Flash driver file code size 34 Document revision history 1 44 4 DoclD025024 1 UM1653 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 4 Application architecture 1 6 BOT protocol 7 block architecture 9 Flow of wear leveling mechanism for 1 12 Flow of wear leveling mechanism for STEVAL CCM007V1 008 1 13 Example of decomposition of a data 15 Flow chart for error detection and correction 16 Flow chart for bad block 17 Flow chart for File System 18 Evaluation board top side 35 Evaluation board bottom side 36 Demo running in Standalone mode
10. NAND VALID ADDRESS When the new address is valid NAND INVALID ADDRESS When the new address is invalid Table 46 EraseBlock Function name FSMC NAND EraseBlock Prototype uint32 t FSMC EraseBlock NAND ADDRESS Address Behavior description Erases complete block from NAND FLASH Input parameter Address Any address into block to be erased Output parameter New status of the NAND operation This parameter can be NAND TIMEOUT ERROR when the previous operation generate a Timeout error NAND READY when memory is ready for the next operation Ly DoclD025024 Rev 1 UM1653 NAND driver firmware modules 4 Table 47 FSMC_NAND Reset Function name FSMC_NAND Reset Prototype uint32 t FSMC NAND Reset void Behavior description Resets the NAND FLASH Input parameter None Output parameter NAND READY Table 48 GetStatus Function name GetStatus Prototype uint32 t FSMC_NAND_GetStatus void Behavior description Gets the NAND operation status Input parameter None Output parameter New status of the NAND operation This parameter can be NAND TIMEOUT ERROR when the previous operation generate a Timeout error NAND READY when memory is ready for the next operation Table 49 FSMC_SBLK_NAND_CopyBack Funct
11. STM32 TRAE Voltage Regulator Micro USB Port High Speed NAND Flash NAND Flash socket footprint USB High Speed PHY MS33245V1 Note The USB High Speed section is only present STEVAL CCM007V1 STEVAL CCM007V2 STEVAL CCMO008V1 STEVAL CCMOO08V2 3 1 1 Running in USB Mass Storage mode STEVAL CCMO006 7 8V1 The STEVAL CCMOO6V 1 STEVAL CCM007V1 STEVAL CCMO08V1 boards programmed for USB Full Speed by default To run USB High Speed you must program the board using proper firmware using available tool chain 1 Connect the mini USB cable between a jumper on the PCB and the Host for USB FS Demo J7 for USB HS Demo 2 device is detected as a USB mass storage device in Device Manager of Host PC amp amp Universal Serial Bus controllers Intel R ICH10 Family USB Enhanced Host Controller 3464 gt Intel R ICH10 Family USB Enhanced Host Controller 6 gt Intel R ICH10 Family USB Universal Host Controller 3464 gt Intel R ICH10 Family USB Universal Host Controller 3465 Intel R ICH10 Family USB Universal Host Controller 3466 gt Intel R ICH10 Family USB Universal Host Controller 3467 gt Intel R ICH10 Family USB Universal Host Controller 3468 gt Intel R ICH10 Family USB Universal Host Controller 3469 USB Root Hub gt USB Root Hub 3 The device appears as a Removable Drive on the Host PC 2 36 45 100250
12. v UM1653 yf i life augmented User manual STM32 Advanced NAND Flash Driver for SLC NAND Introduction The NAND driver library for STM32 is a generic library from which STM32 can access NAND with advanced features like garbage collection wear leveling bad block management ECC checking etc The NAND Flash driver supports dynamic NAND Flash detection based on the Device ID The driver automatically detects the mounted SLC NAND Flash and works accordingly described in more detail in Section 2 8 This solution runs on the STM32F1 STM32F2 amp STM32F4 series of microcontrollers using the FSMC interface The board can run in two modes USB Mass Storage mode and Standalone mode USB Mass Storage mode the Flash works as USB mass storage media s n Standalone mode the bmp images stored in the pics folder of the root directory are read using FatFS file system and displayed on the onboard TFT LCD Six evaluation boards are available for this SLC NAND FLASH Driver STEVAL CCMO006V1 USB mass storage mode demo using STM32F103ZET6 STEVAL CCMO006V2 Standalone mode demo using STM32F103ZET6 STEVAL CCMO007V1 USB Mass Storage mode Demo using STM32F205ZET6 STEVAL CCMO007V2 Standalone mode Demo using STM32F205ZET6 STEVAL CCMO008V1 USB Mass Storage mode Demo using STM32F405ZGT6 STEVAL CCMO008V2 Standalone mode Demo using STM32F405ZGT6 NAND is a non volatile Flash memory device where addr
13. Writes one sector at once Input parameter Memory Offset Memory Offset Writebuff Pointer to the data to be written Transfer Length Number of byte to write Output parameter Status of NAND Write This parameter can be NAND OK when the NAND Write is successful NAND FAIL when NAND fails to Write Function name Table 6 NAND Read NAND Read Prototype Behavior description uint16_t Read uint32 t Memory Offset uint8 t Readbuff uint16 t Transfer Length Reads sectors Input parameter Memory Offset Memory Offset Readbuff Pointer to store the read data Transfer Length Number of byte to read Output parameter Status of NAND Read This parameter can be NAND OK when the NAND Read is successful NAND FAIL when NAND fails to Read DoclD025024 Rev 1 19 45 NAND driver firmware modules UM1653 Table 7 NAND WriteECC Function name NAND WriteECC Prototype uint16 t WriteECC uint32 t Memory Offset uint8 t Writebuff uint16 t NumByte Behavior description Writes one sector amp copy rest Block during ECC Correctable Error Case Input parameter Memory Offset Memory Offset Writebuff Pointer to the data to be written Transfer Length Number of byte to write Output parameter Status of NAND Write This parameter can be NAND OK when the NAND Write is successful NAND
14. void SBLK NAND WritePage NAND ADDRESS Address Prototype uint8 t buff uint16 t len Behavior description Writes page amp Corresponding ECC in SPARE AREA in Small Block NAND Address The address of the page to write Input parameter buff The buffer to write in len The Number of page to write Output parameter None Table 33 LBLK NAND WritePage Function name LBLK NAND WritePage void LBLK NAND WritePage NAND ADDRESS Address Prototype uint8 t buff uint16 t len Write a page amp Corresponding ECC in SPARE AREA in Small Block Behavior description NAND Address The address of the page to write Input parameter buff The buffer to write in len The Number of page to write Output parameter None 4 26 45 DoclD025024 1 UM1653 NAND driver firmware modules 4 Table 34 ReadPage Function name ReadPage void NAND ReadPage NAND ADDRESS Address Prototype uint8 t buff uint16 t len Behavior description Reads a page considering Error correction code 1 bit per 512 Byte Input parameter Address The address of the page to read buff The buffer to read from len The number of page to read Output parameter None Table 35 SBLK NAND ReadPage Function name SBLK NAND ReadPage Prototype void SBLK NAND ReadPage NAND ADDRESS Address uint8 t buff uint16 t len Behavior descriptio
15. Bad block management LLD Low level driver MS33215V1 STM32 USB peripheral The STM32F embeds a USB peripheral that supports USB full speed and high speed The development of Endpoint and support suspend resume are configured by software The USB device provides a connection between the host and the function implemented by the microcontroller Data transfer between the host and the memory system is through a dedicated packet buffer memory accessed directly from the USB device The size of buffer memory is dependent on the number of endpoints used and the maximum packet size This dedicated memory is 512 bytes 4 DoclD025024 1 UM1653 STM32 NAND driver blocks 1 2 3 USB mass storage The USB device is provided to the host as a particular class which determines how the host cross reacts with the embedded system In our case the USB device must appear in the driver as a Mass Storage Class USB which defines that SCSI commands will be used with the protocol bulk only transport BOT Bulk only transport BOT A general BOT transaction is based on a simple basic state machine It begins with ready state idle state and if a CBW is received from the host three cases can be managed DATA OUT STAGE when direction flag is set to 0 Device shall prepare itself to receive an amount of data indicated dCBWDataTransferLength in the CBW block At the end of data transfer a CSW is returned with
16. CSW CMD FAILED 0x01 define CSW PHASE ERROR 0x02 Ij define SEND CSW DISABL define SEND CSW ENABLI pu LA define DIR IN define DIR OUT define BOTH DIR 2 FSMC The FSMC block is able to communicate with the synchronous and asynchronous memory Its main purpose is to e Translate the AHB protocol transactions of external devices e Respect the access time of external devices The FSMC provides a single access to an external device The FSMC has four blocks e AHB Interface Controller NOR Flash PSRAM Controller NAND Flash PC Card e Interface to external device The FSMC generates the appropriate signals to drive the NAND Flash memory The FSMC controller consists of two blocks of code error correction hardware They reduce the workload on the host processor when processing code error correction by the system software These two blocks are identical and are respectively associated with banks 2 and 3 The ECC algorithm used in the FSMC can perform 1 and 2 bit error detection DoclD025024 Rev 1 Ly UM1653 STM32 NAND driver blocks 1 4 4 NAND architecture NAND is a non volatile Flash memory device where address lines are multiplexed with data input output as well as with commands input s Flash consists of a number of blocks Each block consists of a number of pages typically 32 or 64 Pages be written individually one at a time When writing to a page bi
17. E EE p render Grist 19 Table 6 NAND a CEDE 19 Table 7 WriteECC 20 Table 8 NAND POsIWEIeBE CC x uo npe gn arene RE d xa er ete x mug EN d BR REO RU d 20 Table 9 NAND a Creo un 20 Table 10 0 1 2 1 20 Table 11 5 WearLeveling 21 Table 12 LBLK_NAND 21 Table 13 21 Table 14 5 5 21 Table 15 NAND 21 Table 16 WriteSpareArea 22 Table 17 NAND pex RE eb UR ba edo V e PA ee d 22 Table 18 1 22 Table 19 23 Table 20 NAND POosIWiite ione ai 23 Table21 SBLK_NAND rs 23 Table 22
18. FAIL when NAND fails to Write Table 8 NAND PostWriteECC Function name NAND PostWriteECC Prototype 16 t NAND PostWriteECC void Behavior description Copies whole block after writing corrected page in ECC Correction Input parameter None Output parameter Status of NAND Write Table 9 NAND CleanLUT Function name NAND CleanLUT Prototype 16 tNAND CleanLUT uint8 t ZoneNum Behavior description Input parameter Rebuilds the Look Up Table ZoneNbr Zone Number to Rebuild the Look Up Table Output parameter Status of NAND Build look up table This parameter can be NAND OK when the NAND Clean is successful NAND FAIL when NAND fails to clean look up table Table 10 NAND WearLeveling Function name Prototype NAND WearLeveling 16 t NAND WearLeveling uint8 t ZoneNumber Behavior description Builds the Look Up Table According to the Wear Count Input parameter ZoneNumber Zone Number Output parameter Status of NAND wear Leveling This parameter can be NAND OK when the NAND wear leveling is successful NAND FAIL when NAND fails to wear leveling 4 DoclD025024 1 UM1653 NAND driver firmware modules 3 Table 11 SBLK NAND WearLeveling Function name SBLK NAND WearLeveling Prototype 16 t SBLK WearLeveling
19. _ _ lille m mrs 28 Table41 s 28 Table 42 29 Table 43 _ _ 9 29 Table 44 FSMC_NAND_WriteSpareArea 30 Table 45 ReadSpareArea 30 Table 46 FSMC NAND 30 Table 47 FSMC_NAND rns 31 Table 48 _ _ 00 ccc eee eee nes 31 Ly DoclD025024 Rev 1 3 45 List of tables UM1653 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 4 45 FSMC SBLK 31 FSMC LBLK NAND CopyBack 32 32 FSMC NAND Addresslncrement 32 FSMC NAND ONFI 32 5 _5 _ _ 5 33 FSMC LBLK _ 33 Supported NAND Flash 34
20. disk drive disk_read Interface function for a logical page read disk_write Interface function for a logical page write disk_status Interface function for testing if unit is ready disk_ioctl Control device dependent features Ky DoclD025024 Rev 1 17 45 NAND driver firmware modules UM1653 Figure 9 Flow chart for File System MALConfig FSMC Clock Enable MAL Init NAND Init FAT FS not defined USB Disconnect Config Set USBClock USB Interrupts Config SB Init FAT FS not defined disk initialize NAND Read sector buff 512 disk write Write sector BYTE buff 512 NAND Post Write PreCopy old first pages PostCopy remaining Pages Assign LBA to New block MS32851V1 18 45 00 0025024 Rev 1 Ly 4 Table 4 NAND UM1653 NAND driver firmware modules 2 7 NAND driver files 2 7 1 nand_drv c nand_drv h functions Function name NAND_ Init Prototype uint16_t NAND Init void Behavior description Initializes NAND Interface Input parameter None Output parameter Status of NAND Initialization This parameter can be NAND OK when the NAND is OK NAND FAIL when NAND fails to initialize Table 5 NAND Write Function name NAND Write Prototype uint16 t Write uint32 t Memory Offset uint8 t Writebuff uint16 t Transfer Length Behavior description
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22. process is complete WE Write Enable The WE input controls write operations to I O port Commands data and address are latched on the rising edge of WE WP Write Protect Typically connected to Vcc but may also be connected to a GPIO DoclD025024 Rev 1 Ly UM1653 NAND driver firmware modules 2 2 1 2 2 4 NAND driver firmware modules The NAND driver library has the following modules Garbage collection Wear leveling Bad block management ECC check LUT FAT file system WW M A Garbage collection The Garbage Collection software copies the valid data into a new free area and erases the original invalid data Garbage Collection is performed when a virtual block is full or the number of free pages in the whole device is lower than a specified threshold value The basic operations involved in Garbage Collection are the following 1 The virtual blocks meeting the conditions are selected for erasure 2 valid physical pages are copied into a free area 3 selected physical blocks are erased As virtual blocks can contain more than one physical block the Garbage Collection may erase more than one physical block Wear leveling Wear leveling is a technique to increase the lifetime of NAND Flash memory The number of reliable write cycles in NAND Flash is 100 000 erase write cycles If some of the blocks are written repeatedly wearing of these blocks will happen earlier than o
23. to hardware or firmware The code size for the NAND Flash Driver files nand drv c amp fsmc nand if c is Table 57 NAND Flash driver file code size Code Size Flash RAM With Optimization High size 6 5 KB 5 Without Optimization 11 7 KB 5 34 45 00 0025024 Rev 1 Ky UM1653 NAND evaluation board 3 3 1 NAND evaluation board Working with evaluation boards The evaluation boards STEVAL CCMOO6V1 7 1 STEVAL 008 1 work in USB Mass Storage mode In this mode NAND Flash behaves as mass storage media The evaluation boards STEVAL CCMO06V2 STEVAL CCMO007V2 STEVAL CCMO008V2 work in Standalone mode In this mode the bmp images stored in the pics folder of root directory are displayed using the File System on the mounted TFT Figure 10 amp Figure 11 show the component layout to help the user locate the various components and sections on the board Figure 10 Evaluation board top side JTAG connector Touch screen controller TFT connector p E 8 STEVAL CCMOOBV2 9000000 1009009000 4 MS33246V1 3 DoclD025024 Rev 1 35 45 NAND evaluation board UM1653 Figure 11 Evaluation board bottom side RESET switch 0 A A 4 aw Mini USB Port Full Speed
24. uint8 t ZoneNumber Behavior description Builds the Look Up Table According to the Wear Count Input parameter ZoneNumber Zone Number Output parameter Status of SBLK NAND WearLeveling This parameter can be NAND OK when the NAND wear leveling is successful NAND FAIL when NAND fails to wear leveling Table 12 LBLK NAND WearLeveling Function name LBLK NAND WearLeveling Prototype 16 t LBLK NAND WearLeveling uint8 t ZoneNumber Behavior description Builds the Look Up Table According to the Wear Count Input parameter ZoneNumber Zone Number Output parameter Status of LBLK NAND WearLeveling This parameter can be NAND OK when the NAND wear leveling is successful NAND FAIL when NAND fails to wear leveling Table 13 NAND GetFreeBlock Function name Prototype NAND GetFreeBlock 16 t NAND GetFreeBlock void Behavior description Looks for a free Block for data exchange from Look Up Table Input parameter None Output parameter Logical Block Number of free Block Table 14 SBLK NAND ReadSpareArea Function name SBLK NAND ReadSpareArea Prototype SPARE AREA SBLK NAND ReadSpareArea uint32 t address Behavior description Input parameter Output parameter Page Number in multiple of 512 Byte per Page address Corresponding Page Number of Spare Area to be
25. 24 Rev 1 UM1653 NAND evaluation board 3 _ Devices with Removable Storage 4 Removable Disk D This drive can be used as Mass Storage Media Running in Standalone mode STEVAL CCMO006 7 8V2 The STEVAL CCMOO06V2 STEVAL CCM007V2 STEVAL CCMO08V2 boards run Standalone mode 1 2 3 By default TFT is mounted on J6 Connect mini USB cable between J4 on the PCB and the Host PC The bmp images stored in the pics folder of root directory are displayed on the TFT Figure 12 Demo running in Standalone mode DoclD025024 Rev 1 37 45 NAND evaluation board UM1653 3 2 Schematics Figure 13 Microcontroller schematic BL ef 0 Ohm R2 5 8 P LN 65 ge 22899 ge ga gg 88055 1 5 2888 22 Yw PESRE 95 f S chew 5 s diera gongen yi o 8 PE ono pez N 8 X L gt An M w M AQ Pete tur pro
26. AT 100 T i0uF E x AGND 8 ol AGND 3V3 y al R49 z R48 4 7K TSC YD SCLK 4 7K lt 22 8 SCLK R54 ____ 6 801 22 5 SDAT R5 PB7 12 1 SDA 54 3v3 RA 10 47 100nF AGND MS33227V1 Ly 00 0025024 Rev 1 39 45 NAND evaluation board UM1653 Figure 17 TFT Connector schematic 40 45 PG10 FSMC NE3 lt lt FSMC ADDR A0 PD5 FSMC NWE PD4 FSMC NOE NRST PD14 FSMC DO PD15 FSMC D1 FSMC 02 PD1 FSMC D3 PE7 FSMC D4 PES 05 9 06 PE10 FSMC 07 PE11 FSMC D8 PE12 FSMC D9 PE13 FSMC D10 PE14 FSMC D11 PE15 FSMC D12 PD8 FSMC D13 PD9 FSMC D14 PD10 FSMC D15 GND 5V0 3V3 GND GND 5V0 PE TSC_XL TSC_XR TSC_YD TSC_YU CONNECTOR20x2 MS33228V1 Figure 18 Power schematic D4 USB5V_FS 3 3 STPS1L30U U5 GND 1 8 2 NS T ZS C26 D5 T 3 VOUT VOUT 6 10uF 5 0 4 VOUT VOUT USB5V HS VIN NC STPS1L30U LD1117D33TR lol C48 C35 EE 10uF 100nF e o R45 D7 GND 3V3 gt i 2 lt 1k LED GREEN MS33229V1 DoclD025024 Rev 1 4 NAND evaluation board UM1653 Figure 19 NAND Flash schematic M daz ON ON 82 SN ONCE X ON ON Hz gt lt 0G ONSA 82 001 ON O
27. NSA 6109 Lon dM TE zon LS 3MNOOWSd S d _ ONSI Lad Whit LIN 9009 ONSA ge ON 19 91V OWS Fe ON ON ge ON ON ge SSA SSA Lr EAE TE any oN Zr NN ON ON HI xp ON 35 lt ONS 238 yo 8 BON ows vad ONSA 83d Y 291 I onsi 0138 10h on 9 4022 ON ON Cy t ule 0 oed lt 69 x ON ON ae ON on LEX in uio o 2 lt 1INMN OWSd lt 19d 2400 39001 zo 020 ZONVN uuo TONUN V Yas 99H SZISQNVN rc X NEES Foz dM ano i ME LONVN OWSA 7104 1d ONSI Stad ONSA Lad LS 3MN OWSd NC LIN 2 Lar YAV OWS gt Noo gan SHE LONVN TE on zi AD 3 6 lt LONVN vd OWSd Y g oWs vad nm OWS4 7 9d ONSI 63d 5 9WS4 0134 ON NOE N 7 0 lt Pura LES on zn uio o verd ang lt ONSI ead amp z1N OWS4 99d 3400 00
28. aOut MSC_BOT_Data_Out SCSI ProcessCmd No LBLK NAND WearLeveling SBLK NAND WearLeveling Small Block NAND SCSI Write10 SCSI ProcessWrite STORAGE Write NAND Write MS33219V1 The above figure gives an overview of the firmware flow with respect to the way the Wear Leveling Mechanism is implemented Let us consider a scenario in which the host is trying to send the data to the controller via USB and write it to the NAND Flash The corresponding CBW has to be decoded The function given below is called in such a case to write to the memory which uses the information provided from the CBW void SCSI Write10 Cmd uint8 t lun uint32 t LBA uint32 t BlockNbr This function has the following arguments the logical unit number Logical block address LBA and the block number The LBA passed from the host is sequential and maps to the address of the block in NAND Flash memory which comes out to be sequential A structure is used to store the address typedef struct uint16_t Zone uinti16 t Block uinti16 t Page NAND ADDRESS 3 DoclD025024 Rev 1 13 45 NAND driver firmware modules UM1653 2 3 2 3 1 14 45 NAND ADDRESS NAND GetAddress uint32 t Address The above function translates a logical address into a physical one and stores it in a structure element of type ADDRESS While writing to the NAND the wear level algorithm should return the block to be written of w
29. an be NAND OK when the NAND copy is successful NAND FAIL when NAND fails to copy Table 18 NAND CopyBack Function name Prototype NAND CopyBack 16 NAND ADDRESS Address NAND ADDRESS Address Dest uint16 t PageToCopy Behavior description Input parameter Copies pages from Source to Destination Source amp Destination address must have same page number Address Src Source Address Address Dest Destination Address PageToCopy Number of Page to copy Output parameter Status of NAND Copy This parameter can be NAND OK when the NAND copy is successful NAND FAIL when NAND fails to copy 4 DoclD025024 1 UM1653 NAND driver firmware modules 4 Table 19 NAND Format Function name NAND Format Prototype uint16_t NAND Format void Behavior description Format the entire NAND Flash Input parameter None Output parameter Status of NAND Format This parameter can be NAND OK when the NAND Format is successful NAND FAIL when NAND fails to Format Table 20 NAND PostWrite Function name NAND PostWrite Prototype uint16_t PostWrite void Behavior description NAND Post Write Input parameter None Output parameter Status of NAND Post Write This parameter can be NAND OK when the NAND Post Write is s
30. are programmed into the NAND Flash memory Later when the data packet is read from the NAND the ECC values are recalculated Data corruption is indicated when the values of the newly calculated ECC differ from those programmed into the NAND Flash Applying exclusive or to all four values of ECC two old and two new one can determine whether one or more bits have been corrupted If the result is 000 there is no corruption If the result is 111 then a single bit is wrong If two or more bits were damaged this code allows the detection of two errors and the correction of only one bit ECCeven old ECCodd old ECCeven new ECCodd new When the result shows that a bit has been corrupted the address of this bit can be identified by the application of exclusive or on both ECC odd values ECCodd old ECCodd new The erroneous bit position is identified by the position of the 1 in the exclusive or value For a package of several bytes As the size of data packets increases the Hamming algorithm becomes more efficient Each doubling of the data packet requires two additional bits in the ECC A data packet size of 512 bytes the size of a page of the NAND memory used requires 24 bits of ECC The extension of a 1 byte packet to a 512 byte packet requires only a change to the size of data partitions the algorithm remains the same DoclD025024 Rev 1 15 45 NAND driver firmware modules UM1653 2 3 2 16 45 Error de
31. ble Table 28 LBLK NAND BuildLUT Function name LBLK Prototype uint16 t LBLK BuildLUT uint8 t ZoneNbr Behavior description Builds the Look Up Table Input parameter ZoneNbr The Zone Number Output parameter Status of NAND Build Look Up Table This parameter can be NAND OK when the NAND Build Look Up Table is successful NAND FAIL when NAND fails to Build Look Up Table Table 29 GetParity Function name Prototype GetParity uint8 t GetParity uintG tin value Behavior description Calculate parity Input parameter in value 16 bit value Output parameter Status Table 30 Swap Function name Swap Prototype uint16 t Swap uint16 t in Behavior description Input parameter Output parameter Swaps a 16 bit in 16 bit value swapped value DoclD025024 Rev 1 25 45 NAND driver firmware modules UM1653 Table 31 WritePage Function name WritePage void NAND WritePage NAND ADDRESS Address Prototype uint8 t buff uint16 t len Behavior description Writes a page amp Corresponding SPARE AREA Address The address of the page to write Input parameter buff The buffer to write in len The Number of page to write Output parameter None Table 32 SBLK WritePage Function name SBLK NAND WritePage
32. ds the address for Small Block NAND Input parameter Addr NAND ADRESS to be sent Output parameter None Table 55 LBLK NAND SendAddress Function name FSMC LBLK NAND SendAddress Prototype void FSMC LBLK NAND SendAddress uint32 t row uint32 t column Behavior description Sends the row amp column address for Large Block NAND Input parameter row Row Address column Column address Output parameter None DoclD025024 Rev 1 33 45 NAND driver firmware modules UM1653 2 8 Supported NAND Flash Below is the list of supported NAND Flash in our firmware Table 56 Supported NAND Flash Supported NAND Capacity Tested Small block NAND 1 NAND128R3A 128 Mbits Y 2 NAND128W3A 128 Mbits Y 3 NAND256R3A 256 Mbits Y 4 NAND256W3A 256 Mbits Y 5 NAND512R3A 512 Mbits Y 6 NAND512W3A 512 Mbits Y 7 NANDO1GR3A 1 Gbits Y 8 NANDO1GW3A 1 Gbits Y 9 K9F5608U0A 256 MBits Y Large block NAND 1 NAND512R3B 512 Mbits N 2 NAND512W3B 512 Mbits N 3 NANDO01GR3B 1 Gbits Y 4 NANDO1GW3B 1 Gbits Y 5 NANDO2GR3B 2 Gbits N 6 NAND02GW3B 2 Gbits N 7 NANDOAGR3B 4 Gbits N 8 04 4 N 9 NANDO8GR3B 8 Gbits N 10 NAND08GW3B 8 Gbits N 11 H27U4G8F2DTR 1 Gbits Y 12 TC58NVGOS3BFTOO 4 Gbits Y The firmware supports other manufacturer s NAND Flash with same device ID without any change
33. e NAND memory status using the Read status command Input parameter None Output parameter The status of the NAND memory This parameter can be NAND BUSY when memory is busy NAND READY when memory is ready for the next operation NAND ERROR when the previous operation generates Error Table 52 FSMC NAND Addresslncrement Function name FSMC NAND Addresslncrement Prototype uint32 t FSMC NAND AddressIncrement NAND ADDRESS Address Behavior description Increments the NAND memory address Input parameter Output parameter Address address to increment The new status of the increment address operation It can be NAND VALID ADDRESS When the new address is valid address NAND INVALID ADDRESS When the new address is invalid address Table 53 FSMC NAND ONFI Compliance Function name FSMC NAND ONFI Compliance Prototype void FSMC NAND ONFI Compliance void Behavior description Selects the ONFI NAND Type amp sets the Required Parameter accordingly NAND may be SBLK NAND or LBLK NAND Input parameter None Output parameter None 3 DoclD025024 Rev 1 UM1653 NAND driver firmware modules 4 Table 54 FSMC SBLK SendAddress Function name 5 SBLK NAND SendAddress Prototype void FSMC SBLK NAND SendAddress NAND ADDRESS Addr Behavior description Sen
34. eToWrite Number of page to write Output parameter New status of the NAND operation This parameter can be NAND TIMEOUT ERROR when the previous operation generate a Timeout error NAND READY when memory is ready for the next operation New status of the increment address operation It can be NAND VALID ADDRESS When the new address is valid NAND INVALID ADDRESS When the new address is invalid Table 43 FSMC NAND ReadSmallPage Function name FSMC NAND ReadSmallPage Prototype uint32 t FSMC ReadSmallPage uint8 t pBuffer NAND ADDRESS Address uint32 t NumPageToRead Behavior description Sequential read from one or several 512 Bytes Page size Input parameter pBuffer pointer on the Buffer to fill Address First page address NumPageToRead Number of page to read Output parameter New status of the NAND operation This parameter can be NAND TIMEOUT ERROR when the previous operation generate a Timeout error NAND READY when memory is ready for the next operation New status of the increment address operation It can be NAND VALID ADDRESS When the new address is valid NAND INVALID ADDRESS When the new address is invalid DoclD025024 Rev 1 29 45 NAND driver firmware modules UM1653 30 45 Table 44 FSMC_NAND_WriteSpareArea Function name FSMC NAND WriteSpareArea Prototype uint32 t FSMC Wr
35. ess lines are multiplexed with data input output and commands input The NAND driver library has the following features 1 Supports both FAT file system and USB MSC device Supports SLC NAND with page size of 512 Bytes amp 2 KBytes Garbage collection Wear leveling Bad block management ECC check This document applies to the following microcontrollers e STM32L151xD STM32L152xD STM32L1562xD e STM32F405 415 STM32F407 417 STM32F427 437 STM32F429 439 lines e STM32F2 Series e STM32F103xC STM32F103xD and STM32F103xE STM32F103xF STM32F103xG STM32F101xC STM32F101xD and STM32F101xE STM32F101xF STM32F101xG STM32F100xC STM32F100xD STM32F100xE wn November 2013 DoclD025024 Rev 1 1 45 www st com Contents UM1653 Contents 1 STM32 NAND driver blocks 6 1 1 STM32 USB peripheral 6 1 2 USB mass storage 7 1 3 bue 8 1 4 NAND architecture 9 1 5 NAND pin eee 10 2 NAND driver firmware modules 11 2 1 Garbage collection 11 2 2 Wear leveling 11 2 3 ECC DTI 14 2 3 1 Hamming code for NAND Flash 14 2 3 2 Error detection and correction
36. hich the erase count is least To maintain the list of USED FREE and BAD blocks an array is maintained The previously fetched address for writing and the free block obtained with least erase counts are swapped in LUT and updated this ensures that the write takes place at the block with least erase count uint16 t GetFreeBlock void The above function is called to get the free block for swap The function returns the first free block it finds in the This implies that LUTT should have the free blocks arranged in the increasing order of erase count The LUTT is updated by the following function uint16 t NAND BuildLUT uint8 t ZoneNbr The above function arranges the bad block at the bottom of the array and the used and free blocks are located in the upper part of the array uint6 t WearLeveling void The above function sorts the free blocks in the ascending order based on the wear level count Now the free block used for writing in the NAND would be the one with the least erase count ECC Unlike NOR Flash memory that does not require error correction code NAND memory needs to ensure data integrity The disadvantage of the NAND configuration is that when a cell is read the sense amplifier detects a signal much lower than for the NOR configuration because many transistors are in series Therefore access to a cell is not straightforward and must necessarily go through all the cells in
37. ion name _ _ _ Prototype uint32 SBLK CopyBack NAND ADDRESS src NAND ADDRESS dest Behavior description Copies One Page from Source Address to Destination Address without utilizing external Memory Input parameter src Source Address dest Destination Address Output parameter The status of the NAND memory This parameter can be NAND BUSY when memory is busy NAND READY when memory is ready for the next operation NAND ERROR when the previous operation generates error DoclD025024 Rev 1 31 45 NAND driver firmware modules UM1653 32 45 Table 50 FSMC LBLK NAND CopyBack Function name FSMC LBLK NAND CopyBack Prototype uint32 t FSMC LBLK NAND CopyBack NAND ADDRESS src NAND ADDRESS dest Behavior description Copies One Page from Source Address to Destination Address without utilizing external Memory Input parameter src Source Address dest Destination Address Output parameter The status of the NAND memory This parameter can be NAND BUSY when memory is busy NAND READY when memory is ready for the next operation NAND ERROR when the previous operation generates error Table 51 FSMC NAND ReadStatus Function name FSMC NAND ReadStatus Prototype uint32 t FSMC NAND ReadStatus void Behavior description Reads th
38. is valid or not The Data Status informs if the page is valid or invalid e Wear Leveling Counter is the number of times the block has been erased The ECC is the error correction code calculated for each page NAND INTERFACE x8orx16 bus width e Multiplexed Address Data e Pinout compatibility for all densities SUPPLY VOLTAGE 1 8V device VCC 1 65 to 1 95V 3 0V device VCC 2 7 to 3 6V PAGE SIZE e x8 device 512 16 spare Bytes e x16 device 256 8 spare Words x8 device 2048 64 spare Bytes e x16 device 1024 32 spare Words NAND pin mapping 8 15 Data Input Outputs for x16 devices The I O pins are used to input data address command and output data during read operation 0 7 Data Input Outputs Address Inputs or Command Inputs for x8 and x16 devices ALE Address Latch Enable When active an address can be written CLE Command Latch Enable This pin should be LOW while writing commands to the command register CE Chip Enable The CE input enables the device Signal is active low If the signal is inactive the device will be in standby RE Read Enable The RE input is the serial data out control Signal is active low to out data RB Ready Busy open drain output The RB output provides the status of the device operation It is an open drain output hence should be connected to a GPIO with pull up a program erase or read operation is in process e HIGH the
39. iteSpareArea uint8 t pBuffer NAND ADDRESS Address uint32 t NumSpareAreaTowrite Behavior description Writes spare area information for specified page addresses Input parameter pBuffer pointer on the Buffer containing data to be written Address First page address NumSpareAreaTowrite Number of Spare Area to write Output parameter New status of the NAND operation This parameter can be NAND TIMEOUT ERROR when the previous operation generate a Timeout error NAND READY when memory is ready for the next operation New status of the increment address operation It can be NAND VALID ADDRESS When the new address is valid NAND INVALID ADDRESS When the new address is invalid Table 45 FSMC NAND ReadSpareArea Function name FSMC NAND ReadSpareArea Prototype uint32 t FSMC NAND ReadSpareArea uint8 t pBuffer NAND ADDRESS Address uint32 t NumSpareAreaToRead Behavior description Reads the spare area information from the specified page addresses Input parameter pBuffer pointer on the Buffer to fill Address First page address NumSpareAreaToRead Number of Spare Area to read Output parameter New status of the NAND operation This parameter can be NAND TIMEOUT ERROR when the previous operation generated a Timeout error NAND READY when memory is ready for the next operation New status of the increment address operation It can be
40. meter can be NAND OK when the NAND Update Wear Level is successful NAND FAIL when NAND fails to Update Wear Level Table 25 NAND ConvertPhyAddress Function name Prototype ConvertPhyAddress NAND ADDRESS ConvertPhyAddress uint32 t Address Behavior description Converts Memory Offset into Physical Address Input parameter Address Memory Offset in Multiple of 512B 0 512 512 1024 512 Output parameter Physical Address Table 26 NAND BuildLUT Function name NAND BuildLUT Prototype 16 t BuildLUT uint8 t Zone Behavior description Input parameter Output parameter Builds the Look Up Table ZoneNbr The Zone Number Status of NAND Build Look Up Table This parameter can be NAND OK when the NAND Build Look Up Table is successful NAND FAIL when NAND fails to Build Look Up Table 4 DoclD025024 1 UM1653 NAND driver firmware modules 4 Table 27 SBLK NAND BuildLUT Function name SBLK_NAND_BuildLUT Prototype uint16_t SBLK NAND BuildLUT uint8_t ZoneNumber Behavior description Builds the Look Up Table Input parameter ZoneNbr The Zone Number Output parameter Status of NAND Build Look Up Table This parameter can be NAND OK when the NAND Build Look Up Table is successful NAND FAIL when NAND fails to Build Look Up Ta
41. n Reads a page considering Error correction code 1 bit per 512 Byte in Small Block NAND Input parameter Output parameter Address The address of the page to read buff The buffer to read from len The number of page to read None Function name Table 36 LBLK NAND ReadPage LBLK NAND ReadPage Prototype void LBLK NAND ReadPage NAND ADDRESS Address uint8 t buff uint16 t len Behavior description Input parameter Reads a page considering Error correction code 1 bit per 512 Byte in Large Block NAND Address The address of the page to read buff The buffer to read from len The number of page to read Output parameter None Table 37 BitCount Function name BitCount Prototype uint8 t BitCount uint32 t num Behavior description Counts the number of 1 s in 32 bit Number Input parameter Output parameter num The number in which number of 1 s to be counted The number of one in 32 bit number DoclD025024 Rev 1 27 45 NAND driver firmware modules UM1653 2 7 2 fsmc nand if c fsmc nand if h functions Table 38 FSMC_SelectNANDType Function name FSMC_SelectNANDType Prototype void FSMC_SelectNANDType void Selects the NAND Type amp sets the Required Parameter accordingly NAND Behavior description nay SBLK_NAND or LBLK_NAND Input parameter None Output parameter None
42. read SPARE AREA after reading Table 15 LBLK NAND ReadSpareArea Function name LBLK NAND ReadSpareArea Prototype LBLK SPARE AREA LBLK NAND ReadSpareArea uint32 t address Behavior description Page Number in multiple of 512 Byte per Page Input parameter address Corresponding Page Number of Spare Area to be read Output parameter LBLK SPARE AREA after reading DoclD025024 Rev 1 21 45 NAND driver firmware modules UM1653 Table 16 WriteSpareArea Function name WriteSpareArea Prototype uint16 t WriteSpareArea uint32 t address uint8 t buff Behavior description Page Number in multiple of 512 Byte Input parameter address Corresponding Page Number of Spare Area to be read buff Pointer to the data to be written in SPARE AREA Output parameter Status of WriteSpareArea This parameter can be NAND OK when Write SPARE AREA is successful NAND FAIL when Write SPARE AREA fails to Write Table 17 NAND Copy Function name NAND Copy Prototype 16 1 NAND Copy ADDRESS Address Src NAND ADDRESS Address Dest uint16 t PageToCopy Behavior description Copies pages from source to destination Input parameter Address Src Source Address Address Dest Destination Address PageToCopy Number of Page to copy Output parameter Status of NAND Copy This parameter c
43. reate or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2013 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com Ly 00 0025024 Rev 1 45 45
44. series which reduces precision and makes code error correction required There are three error correction codes e The Hamming code can correct only one bit error s Reed Solomon code can correct more errors e The BCH code can correct many errors and is more efficient than Reed Solomon Hamming code for NAND Flash The Hamming code algorithm used by NAND Flash based applications calculates two values of ECC for a data packet Each bit in the values of ECC parity represents half of the bits of the data packet 4 DoclD025024 1 UM1653 NAND driver firmware modules 3 For one byte The trick is how the data bits are partitioned for each of the parity calculations To calculate ECC the data bits are first divided into halves quarters eighths and so on until you reach the bit unit Figure 6 Example of decomposition of a data packet Bit position Data packet MS33220V1 After the partition of the data packet the parity of each group is calculated to generate two values of ECC The results are concatenated to form the ECC values even 0 1 0 1 0 1 0 1 1 1 1 1 000 20717071 0717071 0707070 000 These ECC bits allow us to identify the error position when the data packet is analyzed at a later date Data packets require larger number of ECC values Each data packet of 2n bit ECC requires a value of n bits Based on this calculation both the data packet and the ECC values
45. tection and correction Figure 7 Flow chart for error detection and correction New ECC generated during read XOR previous ECC with new ECC All results zero Yes 24 bit data 0 12 bit data 1 All other 23 bit data 1 Correctable error Non Correctable error ECC Error MS33221V1 4 DoclD025024 1 UM1653 NAND driver firmware modules 2 4 Bad block management Bad blocks contain one or more invalid bits whose reliability is not guaranteed They may be present when the device is shipped or may develop during the lifetime of the device Figure 8 Flow chart for bad block management Block address Block 0 Increment block address Update bad block table MS33222V1 2 5 Look up table LUT The LUT is used to find the Application Block Number corresponding to the Logical address 5 1 All blocks are scanned and User data is read from the Spare area of each block of NAND Flash to build the LUT 2 6 File system The free file system used in the NAND library is FAT_FS_ELM from ChaN The NAND file system interface module ff_user_interface c allows interfacing of file systems with the NAND driver In standalone mode it displays the bmp images stored in the pics folder of NAND Flash This module should be ported to the selected file system Table 3 File system interface functions Function Description disk_initialize Initialize
46. the remaining data length and the STATUS field e DATA IN STAGE when direction flag is set to 1 Device shall prepare itself to send an amount of data indicated dCcBWDataTransferLength in the CBW block At the end of data transfer a CSW is returned with the remaining data length and the STATUS field e ZERO DATA no data stage is needed so CSW block is sent immediately after CBW The BOT transport protocol encapsulates SCSI commands and transfers them in three steps 1 Send the command block CBW 2 Transfer data 3 Return the status of the block CSW Figure 2 BOT protocol architecture Ready v Command transport CBW v i Data Out Data In vvv Status Transport MS33216V1 DoclD025024 Rev 1 7 45 STM32 NAND driver blocks UM1653 1 3 8 45 Bulk Only Transport State machine define BOT IDLE define BOT DATA OUT define BOT DATA IN define BOT DATA IN LAST define BOT CSW Send define BOT ERROR Idle state Data Out state Data In state Last Data In Last Command Status Wrapper e W FP o error state define BOT_CBW_SIGNATUR define BOT_CSW_SIGNATUR Lj 0x43425355 1st 4 bytes of CBW pkt 0x53425355 1st 4 bytes of CSW pkt define BOT CBW PACKET LENGTH 31 define CSW DATA LENGTH 13 CSW Status Definitions define CSW CMD PASSED 0x00 define
47. ther blocks To balance the erase cycles over all the blocks a wear leveling technique is introduced All new data is written to the empty blocks The memory controller selects the new empty block based on the number of write erase cycles it has experienced After the new data is written the controller updates the LUT to point to the position of the selected physical block The block containing the old data is erased and the number of write erase cycles increments DoclD025024 Rev 1 11 45 NAND driver firmware modules UM1653 Figure 4 Flow of wear leveling mechanism for STEVAL CCMO006V1 USB_Istr main CTR LP Set S A Write Memory 4 x MAL Config MAL Write MAL Init NAND Write v NAND Init Vv CleanLUT Yes Is another Zone requested NAND WearLeveling 12 45 No E e LBLK NAND WearLeveling SBLK NAND WearLeveling Small Block NAND Write in current Zone of NAND Flash MS33218V1 DoclD025024 Rev 1 4 UM1653 NAND driver firmware modules Figure 5 Flow of wear leveling mechanism for STEVAL CCM007V1 008V1 OTG FS IRQHandler main USBD_OTG_ISR_Handler DCD_HandleOutEP_ISR NAND Init USBD DataOutStage Is another Zone requested NAND CleanLUT WearLeveling USBD_MSC_Dat
48. ts can only be written from 1 to O erase operation is done by block Erase operation makes all the memory bits of all the pages in the block to logical 1 The small NAND Flash contains 528 byte pages 512 data area and 16 byte spare area The page size for 2K NAND is 2112 2048 data and 64 spare area The page size for 4K NAND is 4224 4096 data and 128 spare area The page size for 8K NAND is 8448 8192 data and 256 spare area Figure 3 NAND block architecture Physical zone Block 0 Page 0 Block 1 gt gt Data Page 1 Spare area Page m 2K Physical pages Physical block or Block N t Block N 1 Data Spare area 0x000 0x83F 0X000 0x200 0x20F 512 Physical page unit MS33217V1 The spare area contains information about the page and the code error correction For small page 512 16 Byte NAND Flash Table 1 Spare area format for small NAND Flash Logical Index Block Status Data Status Wear Leveling counter ECC For Large page 2048 64 Byte NAND Flash Table 2 Spare area format for large NAND Flash Block Status Data Status Logical Index Wear Leveling counter ECC DoclD025024 Rev 1 9 45 STM32 NAND driver blocks UM1653 1 5 10 45 e Logical Index contains the logical address of the block e Block Status returns the status of the block if it
49. uccessful NAND FAIL when NAND fails to Post Write Table 21 SBLK NAND PostWrite Function name SBLK PostWrite Prototype void SBLK NAND PostWrite void Behavior description Small Block NAND PostWrite Input parameter None Output parameter None Table 22 LBLK NAND PostWrite Function name LBLK NAND PostWrite Prototype void LBLK PostWrite void Behavior description Input parameter Output parameter Large Block NAND Post Write None None DoclD025024 Rev 1 23 45 NAND driver firmware modules UM1653 Table 23 NAND GarbageCollection Function name NAND GarbageCollection Prototype uint16 t GarbageCollection void Behavior description Erases Blocks every time the write operation is stopped Input parameter None Output parameter Status of NAND Garbage collection This parameter can be NAND OK when the NAND Garbage collection is successful NAND FAIL when NAND fails to Garbage collection Table 24 NAND UpdateWearLevelCounter Function name UpdateWearLevelCounter Prototype uint16_t NAND UpdateWearLevelCounter ADDRESS Address Behavior description Increments the value of Wear Level counter after every erase Input parameter Address Logical Address Output parameter Status of NAND Update Wear Level This para
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