Home

Freescale Semiconductor

Contents

1. A D NOTES gt Le 256x O 0 2010 1 DIMENSIONING AND TOLERANCING PER ASME D2 Y14 5M 1994 l 2 DIMENSIONS IN MILLIMETERS 3 DIMENSION b IS MEASURED AT THE MAXIMUM Z 0 35 C Z SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM C 4 PRIMARY DATUM C AND THE SEATING PLANE ARE MILLIMETERS DIM MIN MAX A 19 235 E E2 at oso 070 a2 112 12 A3 029 043 b 0o60 0 90 D 23 00BSC Di 19 05 REF D2 19 00 20 00 4x E 23 00BSC Al 0 20 El 19 05 REF E2 19 00 20 00 A2 TOP VIEW e 1 27 BSC 4 A3 B A1 A D1 c 15X e SEATING PLANE 40000000 0000bb06 U SIDE VIEW 0000000000000000 T 9000000000000000 R 9000000000000000 P 0000000000000000 IN 0000000000000000 m 0000000000000000 L 0000000000000000 k A oO J 000000000000000 JH 0000000000000000 c 0000000000000000 F 0000000000000000 E 0000000000000000 p 0000000000000000 c 9000000000000000 jB 23 45 6 7 8 9 10111213 14 15 16 17 256X Ob 0 30 M C A B BOTTOM VIEW Do0 C CASE 1130 01 ISSUE B Figure 65 Package Dimensions for the Plastic Ball Grid Array PBGA JEDEC Standard MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 67 Document Revision History 10 Document Revision History Table 28 lists significant
2. 50 MHz 66MHz 80 MHz Num Characteristic FFACTOR Unit Min Max Min Max Min Max R69 CLKOUT to HRESET high impedance 20 00 20 00 20 00 ns R70 CLKOUT to SRESET high impedance 20 00 20 00 20 00 ns R71 RSTCONF pulse width 340 00 515 00 425 00 17 000 jns R72 R73 Configuration data to HRESET rising 350 00 505 00 425 00 15 000 ns edge set up time R74 Configuration data to RSTCONF rising 350 00 350 00 350 00 ns edge set up time R75 Configuration data hold time after 0 00 0 00 0 00 ns RSTCONF negation R76 Configuration data hold time after 0 00 0 00 0 00 ns HRESET negation R77 HRESET and RSTCONF asserted to 25 00 25 00 25 00 ns data out drive R78 RSTCONF negated to data out high 25 00 25 00 25 00 ns impedance CLKOUT of last rising edge before chip 25 00 25 00 25 00 ns R79 tristates HRESET to data out high impedance R80 DSDI DSCK set up 60 00 90 00 75 00 3 000 ns R81 DSDI DSCK hold time 0 00 0 00 0 00 ns R82 SRESET negated to CLKOUT rising 160 00 242 00 200 00 8 000 ns edge for DSDI and DSCK sample MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 37 Bus Signal Timing F
3. All Frequencies Num Characteristic Unit Min Max 120 CLSN width high 40 00 ns 121 RCLKx rise fall time x 2 3 for all specs in this table 15 00 ns 122 RCLKx width low 40 00 ns 123 RCLKx clock period i 80 00 120 00 ns 124 RXDx setup time 20 00 ns 125 RXDx hold time 5 00 ns 126 RENA active delay from RCLKx rising edge of the last data bit 10 00 ns 127 RENA width low 100 00 ns 128 TCLKx rise fall time 15 00 ns 129 TCLKx width low 40 00 ns 130 TCLKx clock period 99 00 101 00 ns 131 TXDx active delay from TCLKx rising edge 10 00 50 00 ns 132 TXDx inactive delay from TCLKx rising edge 10 00 50 00 ns 133 TENA active delay from TCLKx rising edge 10 00 50 00 ns MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 54 Freescale Semiconductor CPM Electrical Characteristics Table 20 Ethernet Timing continued All Frequencies Num Characteristic Unit Min Max 134 TENA inactive delay from TCLKx rising edge 10 00 50 00 ns 138 CLKOUT low to SDACK asserted 2 20 00 ns 139 CLKOUT low to SDACK negated 2 20 00 ns The ratios SyncCLK RCLKx and SyncCLK TCLKx must be greater or equal to 2 1 2 SDACK is asserted whenever the SDMA writes the incoming frame destination address into memory 1 CLSN CTSx Input Lon 120
4. SPIMISO Output SPIMOSI Input Figure 60 SPI Slave CP 1 Timing Diagram 8 11 I C AC Electrical Specifications Table 24 provides the IC SCL lt 100 KHz timings Table 24 12C Timing SCL lt 100 KHz All Frequencies Num Characteristic Unit Min Max 200 SCL clock frequency slave 0 00 100 00 KHz 200 SCL clock frequency master 1 50 100 00 KHz 202 Bus free time between transmissions 4 70 us 203 Low period of SCL 4 70 us 204 High period of SCL 4 00 us 205 Start condition setup time 4 70 us 206 Start condition hold time 4 00 us 207 Data hold time 0 00 us 208 Data setup time 250 00 ns 209 SDL SCL rise time 1 00 us MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 61 CPM Electrical Characteristics Table 24 12C Timing SCL lt 100 KHZ CONTINUED All Frequencies Num Characteristic Unit Min Max 210 SDL SCL fall time 300 00 ns 211 Stop condition setup time 4 70 us 1 Table 25 provides the IC SCL gt 100 KHz timings Table 25 12C Timing SCL gt 100 KHz SCL frequency is given by SCL BRGCLK_frequency BRG register 3 pre_scaler 2 The ratio SyncClk BRGCLK pre_scaler must be greater or equal to 4 1 All Fr
5. nduy ONASY LI yndu 3419911 Figure 49 IDL Timing MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 51 Freescale Semiconductor CPM Electrical Characteristics 8 6 SCC in NMSI Mode Electrical Specifications Table 18 provides the NMSI external clock timing Table 18 NMSI External Clock Timing All Frequencies Num Characteristic Unit Min Max 100 RCLKx and TCLKx frequency 1 x 2 3 for all specs in this 1 SYNCCLK ns table 101 RCLKx and TCLKx width low 1 SYNCCLK 5 jns 102 RCLKx and TCLKx rise fall time 15 00 ns 103 TXDx active delay from TCLKx falling edge 0 00 50 00 ns 104 RTSx active inactive delay from TCLKx falling edge 0 00 50 00 ns 105 CTSx setup time to TCLKx rising edge 5 00 Ins 106 RXDx setup time to RCLKx rising edge 5 00 ns 107 RXDx hold time from RCLKx rising edge 2 5 00 ns 108 CDx setup time to RCLKx rising edge 5 00 Ins 1 The ratios SyncCLK RCLKx and SyncCLK TCLKx must be greater than or equal to 2 25 1 2 Also applies to CD and CTS hold time when they are used as an external sync signal Table 19 provides the NMSI internal clock timing Table 19 NMSI Internal Clock Timing All Frequencies Num Characteristic Unit Min Max 100 RCLKx and TCLKx frequency 1 x 2 3 for all specs in this table 0 00 SYNCCLK 3 MHz 102 RCLKx and TCLKx rise fall tim
6. 200 D 0 31 DP 0 3 valid hold time MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 12 Freescale Semiconductor Table 6 Bus Operation Timing 7 continued Bus Signal Timing Num Characteristic 50 MHz 66 MHz 80 MHz Min Max Min Max Min Max FFACT Cap Load default 50 pF Unit B22 CLKOUT rising edge to cs asserted GPCM ACS 00 5 00 11 75 7 58 14 33 6 25 13 00 0 250 50 00 ns B22a CLKOUT falling edge to CS asserted GPCM ACS 10 TRLX 0 1 8 00 8 00 8 00 50 00 ns B22b CLKOUT falling edge to CS asserted GPCM ACS 11 TRLX 0 EBDF 0 5 00 11 75 7 58 14 33 6 25 13 00 0 250 50 00 ns B22c CLKOUT falling edge to CS asserted GPCM ACS 11 TRLX 0 EBDF 1 7 00 14 00 11 00 18 00 9 00 16 00 0 375 50 00 ns B23 CLKOUT rising edge to CS negated GPCM read access GPCM write access ACS 00 TRLX 0 amp CSNT 0 2 00 8 00 2 00 8 00 2 00 8 00 50 00 ns B24 A 6 31 to CS asserted GPCM ACS 10 TRLX 0 3 00 6 00 4 00 0 250 50 00 ns B24a A 6 31 to CS asserted GPCM ACS 11 TRLX 0 8 00 E 13 00 11 00 0 500 50 00 ns B25 CLKOUT rising edge to OE WE 0 3 asserted 9 00 9 00
7. 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 81 2666 8080 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 800 441 2447 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Number MPC850EC Rev 2 07 2005 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation o
8. 7 58 14 33 6 25 13 00 0 250 50 00 ns B12a CLKOUT to TA BI negation 2 50 11 00 2 50 11 00 2 50 11 00 50 00 ns when driven by the memory controller or PCMCIA interface B13 CLKOUT to TS BB high Z 5 00 19 00 7 58 21 58 6 25 20 25 0 250 50 00 ns B13a CLKOUT to TA BI high Z 2 50 15 00 2 50 15 00 2 50 15 00 50 00 ns when driven by the memory controller or PCMCIA interface B14 CLKOUT to TEA assertion 2 50 10 00 2 50 10 00 2 50 10 00 50 00 ns B15 CLKOUT to TEA high Z 2 50 15 00 2 50 15 00 2 50 15 00 50 00 ns B16 TA BI valid to CLKOUT setup 9 75 9 75 9 75 50 00 ns time 3 B16a TEA KR RETRY valid to 10 00 10 00 10 00 50 00 ns CLKOUT setup time B16b BB BG BR valid to CLKOUT 8 50 850 850 50 00 ns setup time B17 CLKOUT to TA TEA BI BB 1 00 100 1 00 50 00 ns BG BR valid Hold time 5 B17a CLKOUTtoKR RETRY except 2 00 2 00 200 50 00 ns TEA valid hold time B18 D 0 31 DP O 3 valid to 6 00 6 00 6 00 50 00 ns CLKOUT rising edge setup time 7 B19 CLKOUT rising edge to 1 00 1 00 1 00 50 00 ns D 0 31 DP 0 3 valid hold time B20 D 0 31 DP O 3 valid to 400 400 400 50 00 ns CLKOUT falling edge setup time B21 CLKOUT falling edge to 200 200
9. MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 26 Freescale Semiconductor Bus Signal Timing TS A 6 31 CSx WE 0 3 D 0 31 DP 0 3 Figure 15 External Bus Write Timing GPCM Controlled TRLX 1 CSNT 1 MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 27 Bus Signal Timing Figure 16 provides CLKOUT A 6 31 CSx BS_A 0 3 BS_B 0 3 GPL_A 0 5 GPL_B 0 5 the timing for the external bus controlled by the UPM eg SE ER E e Sial y 64 SA a ie ns Se ene Figure 16 External Bus Timing UPM Controlled Signals MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 28 Freescale Semiconductor Bus Signal Timing Figure 17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM CLKOUT UPWAIT BS_A 0 3 BS_B 0 3 GPL_A 0 5 GPL_B 0 5 Figure 17 Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 18 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM CLKOUT UPWAIT BS_A 0 3 BS_B 0 3 GPL_A 0 5 GPL_B 0 5 Figure 18 Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MP
10. Table 16 Timer Timing All Frequencies Num Characteristic Unit Min Max 61 TIN TGATE rise and fall time 10 00 ns 62 TIN TGATE low time 1 00 clk 63 TIN TGATE high time 2 00 clk 64 TIN TGATE cycle time 3 00 clk 65 CLKO high to TOUT valid 3 00 25 00 ns MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 45 CPM Electrical Characteristics exor ANY NY Sf NS AL TIN TGATE Input TOUT Output E Figure 44 CPM General Purpose Timers Timing Diagram 8 5 Serial Interface AC Electrical Specifications Table 17 provides the serial interface timings as shown in Figure 45 to Figure 49 Table 17 SI Timing All Frequencies Num Characteristic Unit Min Max 70 LIRCLK L1TCLK frequency DSC 0 2 SYNCCLK 2 MHz 5 71 L1RCLK L1TCLK width low DSC 0 2 P 10 ns 71a L1RCLK L1TCLK width high DSC 0 3 P 10 ns 72 L1TXD L1STn L1RQ L1xCLKO rise fall time 15 00 ns 73 L1RSYNC L1TSYNC valid to L1xCLK edge Edge 20 00 ns SYNC setup time 74 L1xCLK edge to LIRSYNC L1TSYNC invalid 35 00 ns SYNC hold time 75 L1RSYNC L1TSYNC rise fall time 15 00 ns 76 L1RXD valid to L1xCLK edge L1RXD setup time 17 00 ns 77 L1xCLK edge to L1RXD invalid L1RXD hold time 13 00 ns 78 L1xCLK edge to L1STn valid 4
11. any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2005 e y oF 2 freescale semiconductor
12. z B O a Q gt 3 an 3 D zO O 20 202 All A9 A6 1 gt q a 00900 gt gt z E 2 3 a O 5O 0 50 20 0 Z ba H D28 O D26 D31 O MODCK1TEXP DP1 DP2 D30 00 0 N C RSTCONFWAITB DPO DP3 O Q4 MODCKHRESEBRESETPORESETXFC VDDSY O O DL EXTCLKEXTAL XTAL KAPWRVSSSYNWSSSYN 020 00000 0 WEI 70000000 0 oJ 00 0 0 o oR O000000 0 S E gt amp o o 010 000 E e is la le a lazi lez Nn WEO GPLA3 CS5 fe O O O O O O O O O 20 GPLA1 GPLA2 CS6 WR GPLAS5 O O CS4 CS7 CS2 GPLB4 BI OO0900 0 N C CS3 CS1 BDIP TA 4 5 gt ezi lt lt nr jazi iz hae jezi o a 3O o 707070 000000000 la e E gt 2 a El E 5 Q a 5 a w 5 c 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Figure 63 Pin Assignments for the PBGA Top View JEDEC Standard For more information on the printed circuit board layout of the PBGA package including thermal via design and suggested pad layout please refer to AN 1231 D Plastic Ball Grid Array Application Note available from your local Freescale sales office MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 65 Mechanical Data and Ordering Information Figure 64 shows the non JEDEC package dimensions of the PBGA A D NOTES gt lt 256x 0 20
13. 10 00 45 00 ns 78A L1SYNC valid to L1STn valid 10 00 45 00 ns 79 L1xCLK edge to L1STn invalid 10 00 45 00 ns 80 L1xCLK edge to L1TXD valid 10 00 55 00 ns 80A LITSYNC valid to L1TXD valid 10 00 55 00 ns 81 L1xCLK edge to L1TXD high impedance 0 00 42 00 ns MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 46 Freescale Semiconductor CPM Electrical Characteristics Table 17 SI Timing continued All Frequencies Num Characteristic Unit Min Max 82 L1RCLK L1TCLK frequency DSC 1 16 00 or MHz SYNCCLK 2 83 L1RCLK L1TCLK width low DSC 1 P 10 ns 83A L1RCLK L1TCLK width high DSC 1 P 10 ns 84 L1CLK edge to L1CLKO valid DSC 1 30 00 ns 85 L1RQ valid before falling edge of LITSYNC 1 00 LITCLK 86 L1GR setup time 42 00 ns 87 L1GR hold time 42 00 ns 88 L1xCLK edge to L1SYNC valid FSD 00 CNT 0 00 ns 0000 BYT 0 DSC 0 The ratio SyncCLK L1RCLK must be greater than 2 5 1 These specs are valid for IDL mode only Where P 1 CLKOUT Thus for a 25 MHz CLKO1 rate P 40 ns These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC whichever is later A OO N LIRCLK FE 0 CE 0 Input LIRCLK FE 1 CE 1 Input LIRSYNC Input 4 L1RxD Input L1STn Output Figure 45 Sl Receive Timing Diagram with Norma
14. A KH KY TS E ex AA P48 a mes Bus Signal Timing PCOE IORD ALE B18 D 0 31 a gt Figure 24 PCMCIA Access Cycles Timing External Bus Read MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 33 Bus Signal Timing Figure 25 provides the PCMCIA access cycle timing for the external bus write TS m gt 4 ke P48 lt P19 gt a P46 gt a 9 PCWE IOWR ALE 19 D 0 31 Figure 25 PCMCIA Access Cycles Timing External Bus Write Figure 26 provides the PCMCIA WAIT signals detection timing CLKOUT WAIT_B Figure 26 PCMCIA WAIT Signal Detection Timing MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 34 Freescale Semiconductor Bus Signal Timing Table 9 shows the PCMCIA port timing for the MPC850 Table 9 PCMCIA Port Timing 50 MHz 66 MHz 80 MHz Num Characteristic Unit Min Max Min Max Min Max P57 CLKOUT to OPx valid 19 00 19 00 19 00 ns P58 HRESET negated to OPx drive 1 18 00 26 00 22 00 ns P59 IP_Xx valid to CLKOUT rising edge 5 00 5 00 5 00 ns P60 CLKOUT rising edge to IP_Xx invalid 1 00 1 00 1 00 ns 1 OP2 and OP3 only Figure 27 provides the PCMCIA output port timing for the MPC850
15. AC Electrical Specifications Table 13 provides the parallel I O timings for the MPC850 as shown in Figure 38 Table 13 Parallel I O Timing All Frequencies Num Characteristic Unit Min Max 29 Data in setup time to clock high 15 ns 30 Data in hold time from clock high 7 5 ns 31 Clock low to data out valid CPU writes data control or direction 25 ns MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 41 CPM Electrical Characteristics CLKOUT DATA IN DATA OUT Figure 38 Parallel I O Data In Data Out Timing Diagram 8 2 IDMA Controller AC Electrical Specifications Table 14 provides the IDMA controller timings as shown in Figure 39 to Figure 42 Table 14 IDMA Controller Timing All Frequencies Num Characteristic Unit Min Max 40 DREQ setup time to clock high 7 00 ns 41 DREQ hold time from clock high 3 00 a ns 42 SDACK assertion delay from clock high 12 00 ns 43 SDACK negation delay from clock low 12 00 ns 44 SDACK negation delay from TA low 20 00 ns 45 SDACK negation delay from clock high 15 00 ns 46 TA assertion to falling edge of the clock setup time applies to external TA 7 00 ns CLKOUT Output 41 DREQ Input Figure 39 IDMA External Requests Timing Diagram MPC850 PowerQUICC Integrated Communications Proc
16. B7a CLKOUT to TSIZ 0 1 REG 5 00 7 58 625 0 250 50 00 ns RSV AT 0 3 BDIP PTR invalid B7b CLKOUT to BR BG FPZ 5 00 7 58 625 0 250 50 00 ns VFLS 0 1 VF O 2 IWP 0 2 LWP 0 1 STS invalid B8 CLKOUT to A 6 31 5 00 11 75 7 58 14 33 6 25 13 00 0 250 50 00 ns RD WR BURST D 0 31 DP 0 3 valid B8a CLKOUT to TSIZ 0 1 REG 5 00 11 75 7 58 14 33 6 25 13 00 0 250 50 00 ns RSV AT 0 3 BDIP PTR valid B8b CLKOUT to BR BG 5 00 11 74 7 58 14 33 6 25 13 00 0 250 50 00 ns VFLS 0 1 VF O 2 IWP 0 2 FRZ LWP 0 1 STS valid 4 MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 11 Bus Signal Timing Table 6 Bus Operation Timing 7 continued 50 MHz 66 MHz 80 MHz Cap Load Num Characteristic FFACT default Unit Min Max Min Max Min Max 50 pF B9 CLKOUT to A 6 31 RD WR 5 00 11 75 7 58 14 33 6 25 13 00 0 250 50 00 ns BURST D 0 31 DP 0 3 TSIZ 0 1 REG RSV AT 0 3 PTR high Z B11 CLKOUT to TS BB assertion 5 00 11 00 7 58 13 58 6 25 12 25 0 250 50 00 ns Bila CLKOUT to TA BI assertion 2 50 9 25 250 9 25 250 925 50 00 ns When driven by the memory controller or PCMCIA interface B12 CLKOUT to TS BB negation 5 00 11 75
17. BST4 in the corresponding word in the UPM B32a CLKOUT falling edge to BS 5 00 12 00 8 00 14 00 6 00 13 00 0 250 50 00 ns valid as requested by control bit BST1 in the corresponding word in the UPM EBDF 0 B32b CLKOUT rising edge to BS valid 1 50 8 00 1 50 8 00 1 50 8 00 50 00 ns as requested by control bit BST2 in the corresponding word in the UPM B32c CLKOUT rising edge to BS valid 5 00 12 00 8 00 14 00 6 00 13 00 0 250 50 00 ns as requested by control bit BST3 in the corresponding word in the UPM B32d CLKOUT falling edge to BS 9 00 14 00 13 00 18 00 11 00 16 00 0 375 50 00 ns valid as requested by control bit BST1 in the corresponding word in the UPM EBDF 1 B33 CLKOUT falling edge to GPL 1 50 6 00 1 50 6 00 1 50 6 00 50 00 ns valid as requested by control bit GxT4 in the corresponding word in the UPM MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 16 Freescale Semiconductor Table 6 Bus Operation Timing 7 continued Bus Signal Timing Num Characteristic 50 MHz 66 MHz 80 MHz Min Max Min Max Min Max FFACT Cap Load default 50 pF Unit B33a CLKOUT rising edge to GPL valid as requested by control bit GxT3 in the corresponding word in the UPM 5 00 12 00 8 00 14 00 6 00 13
18. CLKOUT Output Signals HRESET OP2 OP3 Figure 27 PCMCIA Output Port Timing Figure 28 provides the PCMCIA output port timing for the MPC850 CLKOUT Input Signals Figure 28 PCMCIA Input Port Timing MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 35 Bus Signal Timing Table 10 shows the debug port timing for the MPC850 Table 10 Debug Port Timing 50 MHz 66 MHz 80 MHz Num Characteristic Unit Min Max Min Max Min Max D61 DSCK cycle time 60 00 91 00 75 00 ns D62 DSCK clock pulse width 25 00 38 00 31 00 ns D63 DSCK rise and fall times 0 00 3 00 0 00 3 00 0 00 3 00 ns D64 DSDI input data setup time 8 00 8 00 8 00 ns D65 DSDI data hold time 5 00 5 00 5 00 ns D66 DSCK low to DSDO data valid 0 00 15 00 0 00 15 00 0 00 15 00 ns D67 DSCK low to DSDO invalid 0 00 2 00 0 00 2 00 0 00 2 00 ns Figure 29 provides the input timing for the debug port clock DSCK Figure 29 Debug Port Clock Input Timing Figure 30 provides the timing for the debug port DSCK DSDI DSDO Figure 30 Debug Port Timings MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 36 Freescale Semiconductor Table 11 shows the reset timing for the MPC850 Table 11 Reset Timing Bus Signal Timing
19. VIH 2 0 5 5 V MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 8 Freescale Semiconductor Power Considerations Table 5 DC Electrical Specifications continued Characteristic Symbol Min Max Unit Input low voltage VIL GND 0 8 V EXTAL EXTCLK input high voltage VIHC 0 7 VCC VCC 0 3 V Input leakage current Vin 5 5 V Except TMS TRST DSCK lin 100 yA and DSDI pins Input leakage current Vin 3 6V Except TMS TRST DSCK lin 10 yA and DSDI pins Input leakage current Vin OV Except TMS TRST DSCK lin 10 uA and DSDI pins Input capacitance Cin 20 pF Output high voltage IOH 2 0 mA VDDH 3 0V VOH 2 4 V except XTAL XFC and open drain pins Output low voltage VOL 0 5 V CLKOUT IOL 3 2 mA IOL 5 3 mA IOL 7 0 mA PA 14 USBOE PA 12 TXD2 IOL 8 9 mA TS TA TEA BI BB HRESET SRESET 1 A 6 31 TSIZO REG TSIZ1 D 0 31 DP 0 3 IRQ 3 6 RD WR BURST RSV IRQ2 IP_B O 1 IWP 0 1 VFLS O 1 IP_B2 lIOIS16_B AT2 IP_B3 IWP2 VF2 IP_B4 LWPO VFO IP_B5 LWP1 VF1 IP_B6 DSDI ATO IP_B7 PTR AT3 PA 15 USBRXD PA 13 RXD2 PA 9 L1TXDA SMRXD2 PA 8 L1 RXDA SMTXD2 PA 7 CLK1 TIN1 L1RCLKA BRGO1 PA 6 CLK2 TOUT1 TIN3 PA 5 CLK3 TIN2 L1TCLKA BRGO2 PA 4 CLK4 TOUT2 TIN4 PB 31 SPISEL PB 30 SPICLK TXD3 PB 29 SPIMOSI RXD3 PB 28 SPIMISO BRGOS PB 27 12CSDA BRGO1 PB 26 I2CSCL BRGO2 P
20. edge time 80 00 1210 100 0 ns The timings 139 and 140 describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT The timings 141 142 and 143 are specified to allow the correct function of the IRQ lines detection circuitry and has no direct relation with the total system interrupt latency that the MPC850 is able to support Figure 22 provides the interrupt detection timing for the external level sensitive lines CLKOUT IROx Figure 22 Interrupt Detection Timing for External Level Sensitive Lines Figure 23 provides the interrupt detection timing for the external edge sensitive lines CLKOUT IROx Ft x 143 gt KO Figure 23 Interrupt Detection Timing for External Edge Sensitive Lines MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 31 Bus Signal Timing Table 8 shows the PCMCIA timing for the MPC850 Table 8 PCMCIA Timing 50MHz 66MHz 80 MHz Num Characteristic FFACTOR Unit Min Max Min Max Min Max P44 A 6 31 REG valid to PCMCIA strobe 13 00 21 00 17 00 0 750 ns asserted P45 A 6 31 REG valid to ALE negation 18 00 28 00 23 00 1 000 ns P46 CLKOUT to REG valid 5 0
21. sizes 32 Kbytes to 256 Mbytes Selectable write protection On chip bus arbiter supports one external bus master Special features for burst mode support General purpose timers Four 16 bit timers or two 32 bit timers MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor Features Gate mode can enable disable counting Interrupt can be masked on reference match and event capture e Interrupts Eight external interrupt request IRQ lines Twelve port pins with interrupt capability Fifteen internal interrupt sources Programmable priority among SCCs and USB Programmable highest priority request e Single socket PCMCIA ATA interface Master socket interface release 2 1 compliant Single PCMCIA socket Supports eight memory or I O windows e Communications processor module CPM 32 bit Harvard architecture scalar RISC communications processor CP Protocol specific command sets for example GRACEFUL STOP TRANSMIT stops transmission after the current frame is finished or immediately if no frame is being sent and CLOSE RXBD closes the receive buffer descriptor Supports continuous mode transmission and reception on all serial channels Upto 8 Kbytes of dual port RAM Twenty serial DMA SDMA channels for the serial controllers including eight for the four USB endpoints Three parallel I O r
22. 0 13 00 8 00 16 00 6 00 14 00 0 250 ns P47 CLKOUT to REG Invalid 6 00 9 00 7 00 0 250 ns P48 CLKOUT to CE1 CE2 asserted 5 00 13 00 8 00 16 00 6 00 14 00 0 250 P49 CLKOUT to CE1 CE2 negated 5 00 13 00 8 00 16 00 6 00 14 00 0 250 ns CLKOUT to PCOE IORD PCWE 11 00 11 00 11 00 ns P50 E IOWR assert time CLKOUT to PCOE IORD PCWE 2 00 11 00 2 00 11 00 2 00 11 00 ns P51 TAO i IOWR negate time P52 CLKOUT to ALE assert time 5 00 13 00 8 00 16 00 6 00 14 00 0 250 ns P53 CLKOUT to ALE negate time 13 00 16 00 14 00 0 250 ns P54 PCWE IOWR negated to D O 31 3 00 6 00 4 00 0 250 ns invalid P55 WAIT_B valid to CLKOUT rising edge 8 00 8 00 8 00 ns CLKOUT rising edge to WAIT_B 2 00 2 00 2 00 ns P56 invalid 1 PSST 1 Otherwise add PSST times cycle time PSHT 0 Otherwise add PSHT times cycle time These synchronous timings define when the WAIT_B signal is detected in order to freeze or relieve the PCMCIA current cycle The WAIT_B assertion will be effective only if it is detected 2 cycles before the PSL timer expiration See PCMCIA Interface in the MPC850 PowerQUICC User s Manual MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 32 Freescale Semiconductor Figure 24 provides the PCMCIA access cycle timing for the external bus read CLKOUT gt
23. 00 0 00 0 00 ns J89 TCK low to TDO high impedance 20 00 20 00 20 00 ns J90 TRST assert time 100 00 100 00 100 00 ns J91 TRST setup time to TCK low 40 00 40 00 40 00 ns J92 TCK falling edge to output valid 50 00 50 00 50 00 ns 193 TCK falling edge to output valid out of high 50 00 50 00 50 00 ns impedance J94 TCK falling edge to output high impedance 50 00 50 00 50 00 ns J95 Boundary scan input valid to TCK rising edge 50 00 50 00 50 00 ns J96 TCK rising edge to boundary scan input invalid 50 00 50 00 50 00 ns MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 39 IEEE 1149 1 Electrical Specifications TCK TCK TMS TDI TDO Figure 35 JTAG Test Access Port Timing Diagram TCK TRST Figure 36 JTAG TRST Timing Diagram MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 40 Freescale Semiconductor CPM Electrical Characteristics TCK 392 gt joa J94 gt 322 a Output Signals Output Signals e J95 ml Le 396 e Input Signals Figure 37 Boundary Scan JTAG Timing Diagram 8 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module CPM of the MPC850 8 1 PIO
24. 00 0 250 50 00 ns B34 A 6 31 and D O 31 to CS valid as requested by control bit CST4 in the corresponding word in the UPM 3 00 6 00 4 00 0 250 50 00 ns B34a A 6 31 and D O 31 to CS valid as requested by control bit CST1 in the corresponding word in the UPM 8 00 13 00 11 00 0 500 50 00 ns B34b A 6 31 and D 0 31 to CS valid as requested by CST2 in the corresponding word in UPM 13 00 21 00 17 00 0 750 50 00 ns B35 A 6 31 to CS valid as requested by control bit BST4 in the corresponding word in UPM 3 00 6 00 4 00 0 250 50 00 ns B35a A 6 31 and D 0 31 to BS valid as requested by BST1 in the corresponding word in the UPM 8 00 13 00 11 00 0 500 50 00 ns B35b A 6 31 and D O 31 to BS valid as requested by control bit BST2 in the corresponding word in the UPM 13 00 21 00 17 00 0 750 50 00 ns B36 A 6 31 and D O 31 to GPL valid as requested by control bit GxT4 in the corresponding word in the UPM 3 00 6 00 4 00 0 250 50 00 ns B37 UPWAIT valid to CLKOUT falling edge 6 00 6 00 6 00 50 00 ns B38 CLKOUT falling edge to UPWAIT valid 1 1 00 1 00 1 00 50 00 ns B39 AS valid to CLKOUT rising edge 11 7 00 7 00 7 00 50 00 ns B40 A 6 31 TSIZ 0 1 RD WR BURST valid
25. 1 invalid GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 1 25 00 39 00 31 00 1 375 50 00 ns MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 15 Bus Signal Timing Table 6 Bus Operation Timing 7 continued 50 MHz 66 MHz 80 MHz Cap Load Num Characteristic FFACT default Unit Min Max Min Max Min Max 50 pF B31 CLKOUT falling edge to CS 1 50 6 00 1 50 6 00 1 50 6 00 50 00 ns valid as requested by control bit CST4 in the corresponding word in the UPM B31a CLKOUT falling edge to CS 5 00 12 00 8 00 14 00 6 00 13 00 0 250 50 00 ns valid as requested by control bit CST1 in the corresponding word in the UPM B31b CLKOUT rising edge toCS valid 1 50 8 00 1 50 8 00 1 50 8 00 50 00 ns as requested by control bit CST2 in the corresponding word in the UPM B31c CLKOUT rising edge to CS valid 5 00 12 00 8 00 14 00 6 00 13 00 0 250 50 00 ns as requested by control bit CST3 in the corresponding word in the UPM B31d CLKOUT falling edge to CS 9 00 14 00 13 00 18 00 11 00 16 00 0 375 50 00 ns valid as requested by control bit CST1 in the corresponding word in the UPM EBDF 1 B32 CLKOUT falling edge to BS 1 50 6 00 1 50 6 00 1 50 6 00 50 00 ns valid as requested by control bit
26. 10 F where D is the parameter value to the frequency required in ns F is the operation frequency in MHz Ds is the parameter value defined for 50 MHz CAP LOAD is the capacitance load on the signal in question FFACTOR is the one defined for each of the parameters in the table 2 Phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed value 3 If the rate of change of the frequency of EXTAL is slow i e it does not jump between the minimum and maximum values in one cycle or the frequency of the jitter is fast i e it does not stay at an extreme value for a long time then the maximum allowed jitter on EXTAL can be up to 2 a The timing for BR output is relevant when the MPC850 is selected to work with external bus arbiter The timing for BG output is relevant when the MPC850 is selected to work with internal bus arbiter 5 The setup times required for TA TEA and BI are relevant only when they are supplied by an external device and not when the memory controller or the PCMCIA interface drives them 8 The timing required for BR input is relevant when the MPC850 is selected to work with the internal bus arbiter The timing for BG input is relevant when the MPC850 is selected to work with the external bus arbiter 7 The D 0 31 and DP O 3 input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input signal is asserted 8 The D 0 31 and DP 0 3
27. 9 00 50 00 ns B26 CLKOUT rising edge to OE negated 2 00 9 00 2 00 9 00 2 00 9 00 50 00 ns B27 A 6 31 to CS asserted GPCM ACS 10 TRLX 1 23 00 36 00 29 00 1 250 50 00 ns B27a A 6 31 to CS asserted GPCM ACS 11 TRLX 1 28 00 43 00 36 00 1 500 50 00 ns B28 CLKOUT rising edge to WE 0 3 negated GPCM write access CSNT 0 9 00 9 00 9 00 50 00 ns B28a CLKOUT falling edge to WE 0 3 negated GPCM write access TRLX 0 1 CSNT 1 EBDF 0 5 00 12 00 8 00 14 00 6 00 13 00 0 250 50 00 ns B28b CLKOUT falling edge to CS negated GPCM write access TRLX 0 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 12 00 14 00 13 00 0 250 50 00 ns MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 13 Bus Signal Timing Table 6 Bus Operation Timing 7 continued 50 MHz 66 MHz 80 MHz Cap Load Num Characteristic FFACT default Unit Min Max Min Max Min Max 50 pF B28c CLKOUT falling edge to 7 00 14 00 11 00 18 00 9 00 16 00 0 375 50 00 ns WE 0 3 negated GPCM write access TRLX 0 1 CSNT 1 write access TRLX 0 CSNT 1 EBDF 1 B28d CLKOUT falling edge to CS 1400 18 00 16 00 0 375 50 00 ns negated GPCM w
28. 90 90 8 PB27 PC TCK PA7 PC7 PC4 PB24 PB23 O O PD5 la gt a O le e Sw un PD3 IRQ1 O O D8 O D23 D4 OOO D17 D9 O O D15 D2 O O 000 O O00 O O 2 VDDH D28 O O D26 MODCK1TEXP DP1 O 0 0 N C RSTCONFWAITB DPO DP3 WEI N C GPLAO o WE0 WE2 GPLA3 CS5 cso O Q GPLA1 GPLA2 CS6 WR GPLA5 TEA OOO CS4 CS7 CS2 GPLB4 BI OoOO00 0 N C CS3 BDIP TA O O O O O O O O O 0000000 0 0 0 O0O O0O0OOOOOO O O O O O O O O On ooooo S p gt cs E e is a a la a Nn O 7070 20 0 0 0 0 0 O O O20 p lazi z n la e pu lazi E a Q4 MODCKHRESEBRESETPORESETXFC VDDSY O DL EXTCLKEXTAL XTAL KAPWRVSSSYNWSSSYN a a ZO O a a k n 4 lazi zz A gt E k B Q a 5 a w 5 S Ss 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 62 Pin Assignments for the PBGA Top View non JEDEC Standard MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 64 Freescale Semiconductor Mechanical Data and Ordering Information Figure 63 shows the JEDEC pinout of the PBGA package as viewed from the top surface O0O0900 0 PC14 PB28 PB27 PC12 TCK PB24 PB23 mu gt o mu gt Q 5 Q NI PC15 PAI4 PA12 TMS TDI PCi la 5 N Q S O O O PAIS PB30 PC13 PB26 TRST N C O A8 A7 N C PB25 z 4 is el o la El
29. B 25 SMTXD1 TXD3 PB 24 SMRXD1 RXD3 PB 23 SMSYN1 SDACK1 PB 22 SMSYN2 SDACK2 PB 19 L1ST1 PB 18 RTS2 L1ST2 PB 17 L1ST3 PB 16 L1RQa L1ST4 PC 15 DREQO L1ST5 PC 14 DREQ1 RTS2 L1ST6 PC 13 L1ST7 RTS3 PC 12 L1RQa L1ST8 PC 11 USBRXP PC 10 TGATE1 USBRXN PC 9 CTS2 PC 8 CD2 TGATE1 PC 7 USBTXP PC 6 USBTXN PC 5 CTS3 L1TSYNCA SDACK1 PC 4 CD3 L1RSYNCA PD 15 PD 14 PD 13 PD 12 PD 11 PD 10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 2 BDIP GPL_B5 B5 BR E BR BG G FRZ IRQ6 Z IRQ6 CS 0 5 CS6 CE1 _B _B CS7 CE2 _ B _B WEO BS_ABO _ABO IORD WE1 BS_AB1 IOWR WE2 BS_AB2 PCOE WE3 BS _AB3 PCWE GPL_AO AO GPL_BO Bo OE GPL_A1 _A1 GPL_B1 B1 GPL_A 2 3VGPL_B 2 3 CS 2 3 UPWAITA GPL_A4 AS UPWAITB GPL_B4 GPL_A5 ALE_B DSCK AT1 OP2 MODCK1 STS OP3 MODCK2 DSDO 3 The MPC850 IBIS model must be used to accurately model the behavior of the Clkout output driver for the full and half drive setting Due to the nature of the Clkout output buffer IOH and IOL for Clkout should be extracted from the IBIS model at any output voltage level 5 Power Considerations The average chip junction temperature Ty in C can be obtained from the equation Ty Ta P e 0 101 where T Ambient temperature C MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 9 Bus Signal Timing 9 Package thermal resistance ju
30. C 1 DIMENSIONING AND TOLERANCING PER ASME D2 Y14 5M 1994 l I 2 DIMENSIONS IN MILLIMETERS 3 DIMENSION b IS MEASURED AT THE MAXIMUM ZA 0 35 C Z SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM C 4 PRIMARY DATUM C AND THE SEATING PLANE ARE MILLIMETERS DIM MIN MAX A 191 235 E E2 Ai 0 50 0 70 A2 112 122 A3 0 29 0 43 b 0 60 090 D 23 00BSC DI 19 05 REF D2 19 00 20 00 4x E 23 00BSC 0 20 El 19 05 REF E2 19 00 20 00 A2 TOP VIEW e 1 27 BSC 4 A3 B A1 A D1 c 15X e SEATING PLANE SIDE VIEW 00000000 0000000000000000 0000000000000000 000000000000000 000000000000000 000000000000000 000000000000000 000000000000000 000000000000000 00000000000000 00000000000000 oo 00000000 0000000000000000 0000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 PUOOOMTNTOICAFZZUDA 123456 9 1011 12 13 14 15 16 256X Ob 0 30 WM C A B 0 15 C BOTTOM VIEW Figure 64 Package Dimensions for the Plastic Ball Grid Array PBGA non JEDEC Standard MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 66 Freescale Semiconductor Mechanical Data and Ordering Information Figure 65 shows the JEDEC package dimensions of the PBGA
31. C850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 29 Bus Signal Timing Figure 19 provides the timing for the synchronous external master access controlled by the GPCM f A 6 31 _TSIZ 0 1 R W BURST CSx Figure 19 Synchronous External Master Access Timing GPCM Handled ACS 00 Figure 20 provides the timing for the asynchronous external master memory access controlled by the GPCM B40 A 6 31 TSIZ 0 1 i ex CSx Figure 20 Asynchronous External Master Memory Access Timing GPCM Controlled ACS 00 Figure 21 provides the timing for the asynchronous external master control signals negation AS fan B43 C CSx WE 0 3 OE GPLx BS 0 3 Figure 21 Asynchronous External Master Control Signals Negation Timing MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 30 Bus Signal Timing Table 7 provides interrupt timing for the MPC850 Table 7 Interrupt Timing 50 MHz 66MHz 80 MHz Num Characteristic Unit Min Max Min Max Min Max 139 IRQx valid to CLKOUT rising edge set up time 6 00 6 00 6 00 ns 140 IRQx hold time after CLKOUT 2 00 2 00 2 00 ns 141 IRQx pulse width low 3 00 3 00 3 00 ns 142 IRQx pulse width high 3 00 3 00 3 00 ns 143 IRQx edge to
32. Can be dynamically shifted between high frequency 3 3 V internal and low frequency 2 2 V internal operation e Debug interface Eight comparators four operate on instruction address two operate on data address and two operate on data The MPC850 can compare using the 4 lt and gt conditions to generate watchpoints Each watchpoint can generate a breakpoint internally e 3 3 V operation with 5 V TTL compatibility on all general purpose I O pins 3 Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC850 Table 2 provides the maximum ratings Table 2 Maximum Ratings GND 0V Rating Symbol Value Unit Supply voltage VDDH 0 3 to 4 0 V VDDL 0 3 to 4 0 V KAPWR 0 3 to 4 0 V VDDSYN 0 3 to 4 0 V Input voltage Vin GND 0 3 to VDDH 2 5 V V Junction temperature T 0 to 95 standard C 40 to 95 extended Storage temperature range Tstg 55 to 150 C 1 Functional operating conditions are provided with the DC electrical specifications in Table 5 Absolute maximum ratings are stress ratings only functional operation at the maxima is not guaranteed Stress beyond those listed may affect device reliability or cause permanent damage to the device CAUTION All inputs that tolerate 5 V cannot be more than 2 5 V greater than the supply voltage This restriction applies to power up a
33. Freescale Semiconductor Technical Data MPC850 Document Number MPC850EC Rev 2 07 2005 PowerQUICC Integrated Communications Processor Hardware Specifications This document contains detailed information on power considerations AC DC electrical characteristics and AC timing specifications for revision A B and C of the MPC850 Family 1 Overview The MPC850 is a versatile one chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications excelling particularly in communications and networking products The MPC850 which includes support for Ethernet is specifically designed for cost sensitive remote access and telecommunications applications It is provides functions similar to the MPC860 with system enhancements such as universal serial bus USB support and a larger 8 Kbyte dual port RAM In addition to a high performance embedded MPC8xx core the MPC850 integrates system functions such as a versatile memory controller and a communications processor module CPM that incorporates a specialized independent RISC communications processor referred to as the CP This separate processor off loads peripheral tasks from the embedded MPC8xx core Freescale Semiconductor Inc 2005 All rights reserved Contents E agin iat ede ep Raikes aoe 1 e Feat r s n A SRE Se 3 Electrical and Thermal Characteristics 7 Thermal Characteristics oooo
34. Timing Table 6 Bus Operation Timing i 50 MHz 66 MHz 80 MHz Cap Load Num Characteristic FFACT default Unit Min Max Min Max Min Max 50 pF B1 CLKOUT period 20 30 30 25 ns Bla EXTCLK to CLKOUT phase 0 90 0 90 0 90 0 90 0 90 0 90 50 00 ns skew EXTCLK gt 15 MHz and MF lt 2 Bib EXTCLK to CLKOUT phase 2 30 2 30 2 30 2 30 2 30 2 30 50 00 ns skew EXTCLK gt 10 MHz and MF lt 10 Bic CLKOUT phase jitter EXTCLK 0 60 0 60 0 60 0 60 0 60 0 60 50 00 ns gt 15 MHz and MF lt 2 2 Bid CLKOUT phase jitter 2 00 2 00 2 00 2 00 2 00 2 00 50 00 ns Ble CLKOUT frequency jitter MF lt 0 50 050 0 50 50 00 10 2 B1f CLKOUT frequency jitter 10 lt 2 00 2 00 2 00 x 50 00 MF lt 500 B1g CLKOUT frequency jitter MF gt 3 00 3 00 3 00 ae 50 00 500 Bih Frequency jitter on EXTCLK A 0 50 0 50 0 50 50 00 B2 CLKOUT pulse width low 8 00 1212 10 00 50 00 ns B3 CLKOUT width high 8 00 12 12 10 00 50 00 ns B4 CLKOUT rise time 400 400 4 00 50 00 ns B5 CLKOUT fall time 400 400 4 00 50 00 ns B7 CLKOUT to A 6 31 5 00 7 58 625 0 250 50 00 ns RD WR BURST D 0 31 DP 0 3 invalid
35. ale Semiconductor Bus Signal Timing cere _ O A O A O A CSx OE 18 gt a B19 gt D 0 31 DP 0 3 Figure 10 External Bus Read Timing GPCM Controlled TRLX 0 ACS 10 aa B8 j B220 nE A 6 31 Al yx CSx D 0 31 DP 0 3 Figure 11 External Bus Read Timing GPCM Controlled TRLX 0 ACS 11 MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 23 Bus Signal Timing CLKOUT A 6 31 CSx D 0 31 DP 0 3 Figure 12 External Bus Read Timing GPCM Controlled TRLX 1 ACS 10 ACS 11 MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 24 Freescale Semiconductor Bus Signal Timing Figure 13 through Figure 15 provide the timing for the external bus write controlled by various GPCM factors CLKOUT gt fF YF KK A 6 31 CSx WE 0 3 D 0 31 DP 0 3 Figure 13 External Bus Write Timing GPCM Controlled TRLX 0 CSNT 0 MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 25 Bus Signal Timing CLKOUT _ Ff NO A 6 31 CSx WE 0 3 D 0 31 DP 0 3 Figure 14 External Bus Write Timing GPCM Controlled TRLX 0 CSNT 1
36. an be updated with a 4 word line burst Least recently used LRU replacement algorithm Lockable one line granularity Memory management units MMUs with 8 entry translation lookaside buffers TLBs and fully associative instruction and data TLBs MMwUs support multiple page sizes of 4 Kbytes 16 Kbytes 256 Kbytes 512 Kbytes and 8 Mbytes 16 virtual address spaces and eight protection groups Advanced on chip emulation debug mode Data bus dynamic bus sizing for 8 16 and 32 bit buses Supports traditional 68000 big endian traditional x86 little endian and modified little endian memory systems Twenty six external address lines Completely static design 0 80 MHz operation System integration unit SIU Hardware bus monitor Spurious interrupt monitor Software watchdog Periodic interrupt timer Low power stop mode Clock synthesizer Decrementer time base and real time clock RTC from the PowerPC architecture Reset controller IEEE 1149 1 test access port JTAG Memory controller eight banks Glueless interface to DRAM single in line memory modules SIMMs synchronous DRAM SDRAM static random access memory SRAM electrically programmable read only memory EPROM flash EPROM etc Memory controller programmable to support most size and speed memory interfaces Boot chip select available at reset options for 8 16 or 32 bit memory Variable block
37. changes between revisions of this document Table 28 Document Revision History Revision Date Change 2 7 2005 Added footnote 3 to Table 5 previously Table 4 5 and deleted IOL limit 1 10 2002 Added MPC850DSL Corrected Figure 25 on page 34 0 2 04 2002 Updated power numbers and added Rev C 0 1 11 2001 Removed reference to 5 Volt tolerance capability on peripheral interface pins Replaced SI and IDL timing diagrams with better images Updated to new template added this revision table MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 68 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 69 Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 70 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 71 How to Reach Us Home Page www freescale com email support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 800 521 6274
38. e ns 103 TXDx active delay from TCLKx falling edge 0 00 30 00 ns 104 RTSx active inactive delay from TCLKx falling edge 0 00 30 00 ns 105 CTSx setup time to TCLKx rising edge 40 00 ns 106 RXDx setup time to RCLKx rising edge 40 00 ns 107 RXDx hold time from RCLKx rising edge 2 0 00 ns 108 CDx setup time to RCLKx rising edge 40 00 ns 1 The ratios SyncCLK RCLKx and SyncCLK TCLK1x must be greater or equal to 3 1 Also applies to CD and CTS hold time when they are used as an external sync signals MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 52 Freescale Semiconductor CPM Electrical Characteristics Figure 50 through Figure 52 show the NMSI timings RCLKx RXDx Input CDx Input CDx SYNC Input Figure 50 SCC NMSI Receive Timing Diagram TCLKx TXDx Output RTSx Output CTSx Input CTSx SYNC Input 3 Figure 51 SCC NMSI Transmit Timing Diagram MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 53 CPM Electrical Characteristics TCLKx TXDx Output RTSx Output CTSx Echo Input Figure 52 HDLC Bus Timing Diagram 8 7 Ethernet Electrical Specifications Table 20 provides the Ethernet timings as shown in Figure 53 to Figure 55 Table 20 Ethernet Timing
39. ee eee ee i B8a f B8b AL es Figure 4 Synchronous Output Signals Timing 9 Figure 5 provides the timing for the synchronous active pull up and open drain output signals CLKOUT TEA Figure 5 Synchronous Active Pullup and Open Drain Outputs Signals Timing MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 20 Freescale Semiconductor Bus Signal Timing Figure 6 provides the timing for the synchronous input signals CLKOUT pp Kf Figure 6 Synchronous Input Signals Timing Figure 7 provides normal case timing for input data gre JN AAA l 77 AS D 0 31 A O 0 Figure 7 Input Data Timing in Normal Case MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 21 Bus Signal Timing Figure 8 provides the timing for the input data controlled by the UPM in the memory controller D 0 31 DP 0 3 Figure 8 Input Data Timing when Controlled by UPM in the Memory Controller Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM factors CSx WE 0 3 D 0 31 DP 0 3 Figure 9 External Bus Read Timing GPCM Controlled ACS 00 MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 22 Freesc
40. egisters with open drain capability e Four independent baud rate generators BRGs Can be connected to any SCC SMC or USB Allow changes during operation Autobaud support option e Two SCCs serial communications controllers Ethernet IEEE 802 3 supporting full 10 Mbps operation HDLC SDLC all channels supported at 2 Mbps HDLC bus implements an HDLC based local area network LAN Asynchronous HDLC to support PPP point to point protocol AppleTalk Universal asynchronous receiver transmitter UART Synchronous UART Serial infrared IrDA Totally transparent bit streams Totally transparent frame based with optional cyclic redundancy check CRC MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 5 Features e QUICC multichannel controller QMC microcode features Up to 64 independent communication channels on a single SCC Arbitrary mapping of 0 31 channels to any of 0 31 TDM time slots Supports either transparent or HDLC protocols for each channel Independent TxBDs Rx and event interrupt reporting for each channel e One universal serial bus controller USB Supports host controller and slave modes at 1 5 Mbps and 12 Mbps Two serial management controllers SMCs UART Transparent General circuit interface GCI controller Can be connected to the time division multiplexed TDM c
41. equencies Num Characteristic Expression Unit Min Max 200 SCL clock frequency slave fSCL 0 BRGCLK 48 Hz 200 SCL clock frequency master fSCL BRGCLK 16512 BRGCLK 48 Hz 202 Bus free time between transmissions 1 2 2 fSCL S 203 Low period of SCL 1 2 2 fSCL Ss 204 High period of SCL 1 2 2 fSCL s 205 Start condition setup time 1 2 2 fSCL s 206 Start condition hold time 1 2 2 fSCL s 207 Data hold time 0 s 208 Data setup time 1 40 fSCL Ss 209 SDL SCL rise time 1 10 fSCL Ss 210 SDL SCL fall time 1 33 fSCL Ss 211 Stop condition setup time 1 2 2 2 fSCL Ss 1 The ratio SyncClk Brg_Clk pre_scaler must be greater or equal to 4 1 Figure 61 shows the IC bus timing Figure 61 I C Bus Timing Diagram SCL frequency is given by SCL BrgClk_frequency BRG register 3 pre_scaler 2 MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 62 Freescale Semiconductor Mechanical Data and Ordering Information 9 Mechanical Data and Ordering Information Table 26 provides information on the MPC850 derivative devices Table 26 MPC850 Family Derivatives Device Ethernet Support Number of SCCs ae a Peas MPC850 N A One N A N A MPC850DE Yes Two N A N A MPC850SR Yes Two N A Yes MPC850DSL Yes Two No No 1 Serial Communication Controller SCC 2 50 MHz ver
42. essor Hardware Specifications Rev 2 42 Freescale Semiconductor CPM Electrical Characteristics CLKOUT Output TS Output R W Output TA Output SDACK Figure 40 SDACK Timing Diagram Peripheral Write TA Sampled Low at the Falling Edge of the Clock MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 43 CPM Electrical Characteristics CLKOUT Output TS Output R W Output TA Output SDACK ft Figure 41 SDACK Timing Diagram Peripheral Write TA Sampled High at the Falling Edge of the Clock CLKOUT Output TS Output R W Output TA Output SDACK Figure 42 SDACK Timing Diagram Peripheral Read MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 44 Freescale Semiconductor CPM Electrical Characteristics 8 3 Baud Rate Generator AC Electrical Specifications Table 15 provides the baud rate generator timings as shown in Figure 43 Table 15 Baud Rate Generator Timing All Frequencies Num Characteristic Unit Min Max 50 BRGO rise and fall time 10 00 ns 51 BRGO duty cycle 40 00 60 00 52 BRGO cycle 40 00 ns BRGOn Figure 43 Baud Rate Generator Timing Diagram 8 4 Timer AC Electrical Specifications Table 16 provides the baud rate generator timings as shown in Figure 44
43. gt Ney Figure 53 Ethernet Collision Timing Diagram RCLKx RXDx Input RENA CDx Input Figure 54 Ethernet Receive Timing Diagram MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 55 CPM Electrical Characteristics TCLKx TxDx Output TENA RTSx Input RENA CDx Input NOTE 2 NOTES 1 Transmit clock invert TCI bit in GSMR is set 2 If RENA is deasserted before TENA or RENA is not asserted at all during transmit then the CSL bit is set in the buffer descriptor at the end of the frame transmission Figure 55 Ethernet Transmit Timing Diagram 8 8 SMC Transparent AC Electrical Specifications Figure 21 provides the SMC transparent timings as shown in Figure 56 Table 21 Serial Management Controller Timing All Frequencies Num Characteristic Unit Min Max 150 SMCLKx clock period 100 00 ns 151 SMCLKx width low 50 00 ns 151a SMCLKx width high 50 00 ns 152 SMCLKx rise fall time 15 00 ns 153 SMTXDx active delay from SMCLKx falling edge 10 00 50 00 ns 154 SMRXDx SMSYNx setup time 20 00 ns 155 SMRXDx SMSYNx hold time 5 00 ns 1 The ratio SyncCLK SMCLKx must be greater or equal to 2 1 MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 56 Freescale Semiconducto
44. hannel e One serial peripheral interface SPI Supports master and slave modes Supports multimaster operation on the same bus One ECO interprocessor integrated circuit port Supports master and slave modes Supports multimaster environment e Time slot assigner Allows SCCs and SMCs to run in multiplexed operation Supports T1 CEPT PCM highway ISDN basic rate ISDN primary rate user defined l or 8 bit resolution Allows independent transmit and receive routing frame syncs clocking Allows dynamic changes Can be internally connected to four serial channels two SCCs and two SMCs e Low power support Full high all units fully powered at high clock frequency Full low all units fully powered at low clock frequency Doze core functional units disabled except time base decrementer PLL memory controller real time clock and CPM in low power standby Sleep all units disabled except real time clock and periodic interrupt timer PLL is active for fast wake up Deep sleep all units disabled including PLL except the real time clock and periodic interrupt timer Low power stop to provide lower power dissipation MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 6 Freescale Semiconductor Electrical and Thermal Characteristics Separate power supply input to operate internal logic at 2 2 V when operating at or below 25 MHz
45. igure 31 shows the reset timing for the data bus configuration HRESET fe RSTCONF lt R73 gt Figure 31 Reset Timing Configuration from Data Bus Figure 32 provides the reset timing for the data bus weak drive during configuration HRESET RSTCONF D 0 31 OUT Weak peoo Figure 32 Reset Timing Data Bus Weak Drive during Configuration MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 38 Freescale Semiconductor Figure 33 provides the reset timing for the debug port configuration SRESET DSCK DSDI 7 IEEE 1149 1 Electrical Specifications Table 12 provides the JTAG timings for the MPC850 as shown in Figure 34 to Figure 37 Table 12 JTAG Timing Reo 2 S7 IEEE 1149 1 Electrical Specifications Figure 33 Reset Timing Debug Port Configuration 50 MHz 66MHz 80 MHz Num Characteristic Unit Min Max Min Max Min Max J82 TCK cycle time 100 00 100 00 100 00 ns J83 TCK clock pulse width measured at 1 5 V 40 00 40 00 40 00 ns J84 TCK rise and fall times 0 00 10 00 0 00 10 00 0 00 10 00 ns J85 TMS TDI data setup time 5 00 5 00 5 00 ns J86 TMS TDI data hold time 25 00 25 00 25 00 ns J87 TCK low to TDO data valid 27 00 27 00 27 00 ns J88 TCK low to TDO data invalid 0
46. input timings B20 and B21 refer to the falling edge of CLKOUT This timing is valid only for read accesses controlled by chip selects controlled by the UPM in the memory controller for data beats where DLT3 1 in the UPM RAM words This is only the case where data is latched on the falling edge of CLKOUT 2 The timing B30 refers to CS when ACS 00 and to WE 0 3 when CSNT 0 10 The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals 11 The AS signal is considered asynchronous to CLKOUT MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 18 Freescale Semiconductor Bus Signal Timing Figure 2 is the control timing diagram CLKOUT Outputs Outputs Inputs Inputs A Maximum output delay specification 8 Minimum output hold time c Minimum input setup time specification D Minimum input hold time specification Figure 2 Control Timing Figure 3 provides the timing for the external clock CLKOUT Figure 3 External Clock Timing MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 19 Bus Signal Timing Figure 4 provides the timing for the synchronous output signals CLKOUT Output Signals Output Signals Output Signals Y ces
47. l Clocking DSC 0 MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 47 CPM Electrical Characteristics LIRCLK FE 1 CE 1 Input L1RCLK FE 0 CE 0 Input LIRSYNC Input L1RXD Input L1ST 4 1 Output L1CLKO Output Figure 46 SI Receive Timing with Double Speed Clocking DSC 1 MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 48 Freescale Semiconductor CPM Electrical Characteristics LITCLK FE 0 CE 0 Input LITCLK FE 1 CE 1 Input LITSYNC Input L1TxD Output L1STn Output Figure 47 SI Transmit Timing Diagram MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 49 CPM Electrical Characteristics L1RCLK FE 0 CE 0 Input L1RCLK FE 1 CE 1 Input LIRSYNC Input L1TXD Output L1ST 4 1 Output L1CLKO Output Figure 48 SI Transmit Timing with Double Speed Clocking DSC 1 MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 50 Freescale Semiconductor CPM Electrical Characteristics nduy 4941 indyno 0411 indyno L p LSL1 indu axy indyno ax
48. n Timing 7 continued Bus Signal Timing Num Characteristic 50 MHz 66 MHz 80 MHz Min Max Min Max Min Max FFACT Cap Load default 50 pF Unit B29h WE 0 3 negated to D 0 31 DP 0 3 high Z GPCM write access TRLX 0 CSNT 1 EBDF 1 25 00 39 00 31 00 1 375 50 00 ns B29i CS negated to D O 31 DP 0 3 high Z GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 4 25 00 39 00 31 00 1 375 50 00 ns B30 CS WE 0 3 negated to A 6 31 invalid GPCM write access 3 00 6 00 4 00 0 250 50 00 ns B30a WE 0 3 negated to A 6 31 invalid GPCM write access TRLX 0 CSNT 1 CS negated to A 6 31 invalid GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 0 8 00 13 00 11 00 0 500 50 00 ns B30b WE 0 3 negated to A 6 31 invalid GPCM write access TRLX 1 CSNT 1 CS negated to A 6 31 Invalid GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 28 00 43 00 36 00 1 500 50 00 ns B30c WE 0 3 negated to A 6 31 invalid GPCM write access TRLX 0 CSNT 1 CS negated to A 6 31 invalid GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 4 5 00 8 00 6 00 0 375 50 00 ns B30d WE 0 3 negated to A 6 31 invalid GPCM write access TRLX 1 CSNT 1 CS negated to A 6 3
49. nction to ambient C W P Pine t Pro Piwr Lp X V pp Watts chip internal power P o Power dissipation on input and output pins user determined For most applications P lt 0 3 e P and can be neglected If P is neglected an approximate relationship between P and T is Pp K T 273 C 2 Solving equations 1 and 2 for K gives o e 2 K P T 273 C 6 P 8 where K is a constant pertaining to the particular part K can be determined from equation 3 by measuring P at equilibrium for a known T Using this value of K the values of P and T can be obtained by solving equations 1 and 2 iteratively for any value of T 5 1 Layout Practices Each V cc pin on the MPC850 should be provided with a low impedance path to the board s supply Each GND pin should likewise be provided with a low impedance path to ground The power supply pins drive distinct groups of logic on chip The Vcc power supply should be bypassed to ground using at least four 0 1 uF by pass capacitors located as close as possible to the four sides of the package The capacitor leads and associated printed circuit traces connecting to chip Vcc and GND should be kept to less than half an inch per capacitor lead A four layer board is recommended employing two inner layers as Vcc and GND planes All output pins on the MPC850 have fast rise and fall times Printed circuit PC trace interconnection length should be minimized in order to mi
50. nd normal operation that is if the MPC850 is unpowered voltage greater than 2 5 V must not be applied to its inputs 2 The MPC850 a high frequency device in a BGA package does not provide a guaranteed maximum ambient temperature Only maximum junction temperature is guaranteed It is the responsibility of the user to consider power dissipation and thermal management Junction temperature ratings are the same regardless of frequency rating of the device This device contains circuitry protecting against damage due to high static voltage or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level for example either GND or Vcc Table 3 provides the package thermal characteristics for the MPC850 MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 7 Thermal Characteristics 4 Thermal Characteristics Table 3 shows the thermal characteristics for the MPC850 Table 3 Thermal Characteristics Characteristic Symbol Value Unit Thermal resistance for BGA OJA 40 C W OJA 313 C W OJA 244 C W Thermal Resistance for BGA junction to case 8yc 8 C W 1 For more information on the design of thermal vias on multilayer b
51. nents and the relationships among those components 2 Kbyte System Interface Unit I Cache Embedded Tisttucton Instruction Memory Controller MPC8xx Bus MMU Core 1 Kbyte D Cache Unified Bus Bus Interface Unit System Functions Load Store Data Real Time Clock Bus MMU PCMCIA Interface y Communications Baud Rate Four Interrupt Dual Port Processor Generators Timers Controller RAM DA Module Channels Parallel I O 32 Bit RISC Communications Ports Processor CP and Program ROM a 2 Virtual UTOPIA nel 850SR amp DSL Timer Channels and Peripheral Bus a SCC3 SMC1 Time Slot Assigner Non Multiplexed Serial Interface Figure 1 MPC850 Microprocessor Block Diagram The following list summarizes the main features of the MPC850 e Embedded single issue 32 bit MPC8xx core implementing the PowerPC architecture with thirty two 32 bit general purpose registers GPRs Performs branch folding and branch prediction with conditional prefetch but without conditional execution MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 3 Features 2 Kbyte instruction cache and 1 Kbyte data cache Harvard architecture Caches are two way set associative Physically addressed Cache blocks c
52. nimize undershoot and reflections caused by these fast output switching times This recommendation particularly applies to the address and data busses Maximum PC trace lengths of six inches are recommended Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the Vcc and GND circuits Pull up all unused inputs or signals that will be inputs during reset Special care should be taken to minimize the noise levels on the PLL supply pins 6 Bus Signal Timing Table 6 provides the bus operation timing for the MPC850 at 50 MHz 66 MHz and 80 MHz Timing information for other bus speeds can be interpolated by equation using the MPC850 Electrical Specifications Spreadsheet found at http www mot com netcomm The maximum bus speed supported by the MPC850 is 50 MHz Higher speed parts must be operated in half speed bus mode for example an MPC850 used at 66 MHz must be configured for a 33 MHz bus The timing for the MPC850 bus shown assumes a 50 pF load This timing can be derated by 1 ns per 10 pF Derating calculations can also be performed using the MPC850 Electrical Specifications Spreadsheet MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 10 Freescale Semiconductor Bus Signal
53. oards and BGA layout considerations in general refer to AN 1231 D Plastic Ball Grid Array Application Note available from your local Freescale sales office 2 Assumes natural convection and a single layer board no thermal vias 3 Assumes natural convection a multilayer board with thermal vias 1 watt MPC850 dissipation and a board temperature rise of 20 C above ambient 4 Assumes natural convection a multilayer board with thermal vias 1 watt MPC850 dissipation and a board temperature rise of 13 C above ambient Ty Ta Pp e0ya Pp Voo e Ibp Pro where Pro is the power dissipation on pins Table 4 provides power dissipation information Table 4 Power Dissipation Pp Characteristic Frequency MHz Typical i Maximum 2 Unit Power Dissipation 33 TBD 515 mW All Revisions 40 TBD 590 mW 1 1 Mode 50 TBD 725 mW Typical power dissipation is measured at 3 3V 2 Maximum power dissipation is measured at 3 65 V Table 5 provides the DC electrical characteristics for the MPC850 Table 5 DC Electrical Specifications Characteristic Symbol Min Max Unit Operating voltage at 40 MHz or less VDDH VDDL 3 0 3 6 V KAPWR VDDSYN Operating voltage at 40 MHz or higher VDDH VDDL 3 135 3 465 V KAPWR VDDSYN Input high voltage address bus data bus EXTAL EXTCLK VIH 2 0 3 6 V and all bus control status signals Input high voltage all general purpose I O and peripheral pins
54. oommoorsor 8 Power Considerations 26 0000 060 sewn cance eee 9 Bus Signal Timing 0020000 10 IEEE 1149 1 Electrical Specifications 39 CPM Electrical Characteristics 41 Mechanical Data and Ordering Information 63 Document Revision History 68 Sy o oe 2 freescale semiconductor Overview The CPM of the MPC850 supports up to seven serial channels as follows e One or two serial communications controllers SCCs The SCCs support Ethernet ATM MPC850SR and MPC850DSL HDLC and a number of other protocols along with a transparent mode of operation One USB channel e Two serial management controllers SMCs e One PC port e One serial peripheral interface SPD Table 1 shows the functionality supported by the members of the MPC850 family Table 1 MPC850 Functionality Matrix Number of Ethernet Multi channel Number of Part SCCs Support ATM Support USB Support HDLC PCMCIA Slots Supported PP Support Supported MPC850 1 Yes Yes 1 MPC850DE 2 Yes Yes 1 MPC850SR 2 Yes Yes Yes Yes 1 MPC850DSL 2 Yes Yes Yes No 1 Additional documentation may be provided for parts listed in Table 1 MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor Features 2 Features Figure is a block diagram of the MPC850 showing its major compo
55. pecifications Table 23 provides the SPI slave timings as shown in Figure 59 and Figure 60 Table 23 SPI Slave Timing CPM Electrical Characteristics All Frequencies Num Characteristic Unit Min Max 170 Slave cycle time 2 toye 171 Slave enable lead time 15 00 ns 172 Slave enable lag time 15 00 ns 173 Slave clock SPICLK high or low time 1 teyc 174 Slave sequential transfer delay does not require deselect 1 toye 175 Slave data setup time inputs 20 00 ns 176 Slave data hold time inputs 20 00 ns 177 Slave access time 50 00 ns 178 Slave SPI MISO disable time 50 00 ns 179 Slave data valid after SPICLK edge 50 00 ns 180 Slave data hold time outputs 0 00 ns 181 Rise time input 15 00 ns 182 Fall time input 15 00 ns MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 59 CPM Electrical Characteristics SPISEL Input SPICLK CI 0 Input SPICLK CI 1 Input SPIMISO Output SPIMOSI Input Figure 59 SPI Slave CP 0 Timing Diagram MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 60 Freescale Semiconductor CPM Electrical Characteristics SPISEL Input SPICLK CI 0 Input SPICLK CI 1 Input
56. r CPM Electrical Characteristics SMCLKx SMTXDx Output NOTE Hiss SMSYNx Hiss SMRXDx Input NOTE 1 This delay is equal to an integer number of character length clocks Figure 56 SMC Transparent Timing Diagram 8 9 SPI Master AC Electrical Specifications Table 22 provides the SPI master timings as shown in Figure 57 and Figure 58 Table 22 SPI Master Timing All Frequencies Num Characteristic Unit Min Max 160 MASTER cycle time 4 1024 toye 161 MASTER clock SCK high or low time 2 512 toye 162 MASTER data setup time inputs 50 00 ns 163 Master data hold time inputs 0 00 ns 164 Master data valid after SCK edge 20 00 ns 165 Master data hold time outputs 0 00 ns 166 Rise time output 15 00 ns 167 Fall time output 15 00 ns MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 57 CPM Electrical Characteristics SPICLK CI 0 Output SPICLK CI 1 Output SPIMISO Input SPIMOSI Output SPICLK CI 0 Output SPICLK CI 1 Output SPIMISO Input SPIMOSI Output Figure 58 SPI Master CP 1 Timing Diagram MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 58 Freescale Semiconductor 8 10 SPI Slave AC Electrical S
57. r guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly
58. rite access TRLX 0 1 CSNT 1 ACS 10 or ACS 11 EBDF 1 B29 WE 0 3 negated to D O 31 3 00 6 00 4 00 0 250 50 00 ns DP 0 3 high Z GPCM write access CSNT 0 B29a WE 0 3 negated to D O 31 8 00 1300 11 00 0 500 50 00 ns DP 0 3 high Z GPCM write access TRLX 0 CSNT 1 EBDF 0 B29b CS negated to D O 31 3 00 6 00 4 00 0 250 50 00 ns DP 0 3 high Z GPCM write access ACS 00 TRLX 0 amp CSNT 0 B29c CS negated to D O 31 8 00 13 00 11 00 0 500 50 00 ns DP 0 3 high Z GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 0 B29d WE 0 3 negated to D O 31 28 00 43 00 36 00 1 500 50 00 ns DP 0 3 high Z GPCM write access TRLX 1 CSNT 1 EBDF 0 B29e CS negated to D 0 31 28 00 43 00 36 00 1 500 50 00 ns DP 0 3 high Z GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 B29f WE 0 3 negated to D 0 31 5 00 9 00 7 00 0 375 50 00 ns DP 0 3 high Z GPCM write access TRLX 0 CSNT 1 EBDF 1 B29g CS negated to D 0 31 5 00 9 00 7 00 0 375 50 00 ns DP 0 3 high Z GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 4 MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 14 Freescale Semiconductor Table 6 Bus Operatio
59. sion supports 64 time slots on a time division multiplexed line using one SCC Table 27 identifies the packages and operating frequencies available for the MPC850 Table 27 MPC850 Package Frequency Availability Package Type Frequency MHz Temperature Tj Order Number 256 Lead Plastic Ball Grid Array 50 0 C to 95 C XPC850ZT50BU ZT suffix XPC850DEZT50BU XPC850SRZT50BU XPC850DSLZT50BU 66 0 C to 95 C XPC850ZT66BU XPC850DEZT66BU XPC850SRZT66BU 80 0 C to 95 C XPC850ZT80BU XPC850DEZT80BU XPC850SRZT80BU 256 Lead Plastic Ball Grid Array 50 40 C to 95 C XPC850CZT50BU CZT suffix XPC850DECZT50BU XPC850SRCZT50BU XPC850DSLCZT50BU 66 XPC850CZT66BU XPC850DECZT66BU XPC850SRCZT66BU 80 XPC850CZT80B XPC850DECZT80B XPC850SRCZT80B 9 1 Pin Assignments and Mechanical Dimensions of the PBGA The original pin numbering of the MPC850 conformed to a Freescale proprietary pin numbering scheme that has since been replaced by the JEDEC pin numbering standard for this package type To support MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 63 Mechanical Data and Ordering Information customers that are currently using the non JEDEC pin numbering scheme two sets of pinouts JEDEC and non JEDEC are presented in this document Figure 62 shows the non JEDEC pinout of the PBGA package as viewed from the top surface O9O9090 0 OO90
60. to CLKOUT rising edge 7 00 7 00 7 00 50 00 ns B41 TS valid to CLKOUT rising edge setup time 7 00 7 00 7 00 50 00 ns MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications Rev 2 Freescale Semiconductor 17 Bus Signal Timing Table 6 Bus Operation Timing 7 continued 50 MHz 66 MHz 80 MHz Cap Load Num Characteristic FFACT default Unit Min Max Min Max Min Max 50 pF B42 CLKOUT rising edge to TS valid 2 00 2 00 2 00 50 00 ns hold time B43 AS negation to memory TBD TBD TBD 50 00 ns controller signals negation 1 The minima provided assume a 0 pF load whereas maxima assume a 50pF load For frequencies not marked on the part new bus timing must be calculated for all frequency dependent AC parameters Frequency dependent AC parameters are those with an entry in the FFactor column AC parameters without an FFactor entry do not need to be calculated and can be taken directly from the frequency column corresponding to the frequency marked on the part The following equations should be used in these calculations For a frequency F the following equations should be applied to each one of the above parameters For minima D FFACTOR x 1000 P D5p 20 x FFACTOR a F For maxima FFACTOR x 1000 7 Ds 20 x FFACTOR P8s CAP LOAD 50

Download Pdf Manuals

Related Search

Related Contents

  Henny Penny CLIMAPLUS LCG User's Manual  第56回 定時株主総会  SERVICE MANUAL - Hydraulics International  Kenmore 795.755494 Refrigerator User Manual  

Copyright © All rights reserved. Failed to retrieve file