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Synthesis and Verification Design Guide

1. CLKFX180 LOCKED dcmO0 locked PSDONE STATUS defparam DCMO DLL FREQUENCY MODE LOW defparam DCMO DUTY CYCLE CORRECTION TRUE defparam DCMO STARTUP WAIT TRUE defparam DCMO DFS FREQUENCY MODE LOW defparam DCMO CLKFX DIVIDE 1 defparam DCMO CLKFX MULTIPLY 1 defparam DCMO CLK FEEDBACK 1X defparam DCMO CLKOUT PHASE SHIFT NONE defparam DCMO PHASE SHIFT 0 defparam DCMO CLK FEEDBACK 1X defparam DCMO CLKIN DIVIDE BY 2 FALSE defparam DCMO CLKIN PERIOD 0 0 defparam DCMO DESKEW ADJUST SYSTEM SYNCHRONOUS defparam DCMO DFS FREQUENCY LOW defparam DCMO DLL FREQUENCY LOW BUFG CLK BUFO O clock out I clk0 endmodule DCM TEST Note Some synthesis tools may not support the use of a defparam statements See the Defparam Support Considerations section for details Synthesis and Verification Design Guide www xilinx com 259 1 800 255 7778 Z XILINX Chapter 6 Verifying Your Design Simulation CORE Generator Components The simulation flow for CORE Generator models is described in the CORE Generator Guide Design Hierarchy and Simulation Most FPGA designs are partitioned into levels of hierarchy for many advantageous reasons A few of the reasons are that hierarchy makes the design easier to read easier to re use allows partitioning for a multi engineer team and improves verification To im
2. Synthesis and Verification Design Guide www xilinx com 115 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X e Verilog example include path to virtex v module setreset CLK DIN1 DIN2 RESET GTSInput DOUT1 DOUT2 DOUT3 input CLK input DIN1 input DIN2 input RESET input GTSInput output DOUT1 output DOUT2 output DOUT3 reg DOUT1 STARTUP_VIRTEX_GSR startup_inst GSR RESET STARTUP_VIRTEX_GTS startup_2 GTS GTSInput always posedge CLK or posedge RESET begin if RESET DOUT1 lt 1 b0 else DOUT1 lt DIN1 end assign DOUT3 GTSInput 1 b0 1 b0 1 b2Z assign DOUT2 GTSInput 1 b0 DIN2 1 bZ endmodule Preset vs Clear The Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X and Spartan II Spartan 3 family flip flops are configured as either preset asynchronous set or clear asynchronous reset during startup Automatic assertion of the GSR net presets or clears each flip flop after the FPGA is configured You can assert the GSR pin at any time to produce this global effect You can also preset or clear individual flip flops with the flip flop s dedicated Preset or Clear pin When a Preset or Clear pin on a flip flop is
3. defparam DCMO DLL FREQUENCY MODE LOW defparam DCMO DUTY CYCLE CORRECTION TRUE defparam DCMO STARTUP WAIT TRUE defparam DCMO DFS FREQUENCY MODE LOW defparam DCMO CLKFX DIVIDE 1 defparam DCMO CLKFX MULTIPLY 1 defparam DCMO CLK FEEDBACK 1X defparam DCMO CLKOUT PHASE SHIFT NONE defparam DCMO PHASE SHIFT 0 defparam DCM1 DLL_FREQUENCY_MODE LOW defparam DCM1 DUTY_CYCLE_CORRECTION TRUE defparam DCM1 STARTUP_WAIT TRUE defparam DCM1 DFS_FREQUENCY_MODE LOW defparam DCM1 CLKFX_DIVIDE 1 defparam DCM1 CLKFX_MULTIPLY 1 defparam DCM1 CLK_FEEDBACK 1X defparam DCM1 CLKOUT_PHASE_SHIFT FIXED defparam DCM1 PHASE_SHIFT 0 synthesis translate_on endmodule DCM_TOP Synthesis and Verification Design Guide www xilinx com 111 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan Il 3 Virtex E Il II Pro II Pro X Using Dedicated Global Set Reset Resource The use of Global Set Reset Resource GSR in Virtex Virtex E Virtex II and Spartan II devices must be considered carefully Synthesis tools do not automatically infer GSRs for these devices however STARTUP_VIRTEX STARTUP_VIRTEX2 and STARTUP SPARTAN can be instantiated in your HDL code to access the GSR resources Xilinx recommends that for Virtex Virtex E and Spartan II designs you write the high fanout set r
4. These Xilinx simulation points are described in detail in the following sections The libraries required to support the simulation flows are described in detail in VHDL Verilog Libraries and Models The flows and libraries support functional equivalence of initialization behavior between functional and timing simulations Different simulation libraries are used to support simulation before and after running NGDBuild Prior to NGDBuild your design is expressed as a UNISIM netlist containing Unified Library components that represents the logical view of the design After NGDBuild your design is a netlist containing SIMPRIMs that represents the physical view of the design Although these library changes are fairly transparent there are two important considerations to keep in mind first you must specify different simulation libraries for pre and post implementation simulation and second there are different gate level cells in pre and post implementation netlists For Verilog within the simulation netlist there is the Verilog system task sdf annotate which specifies the name of the SDF file to be read If the simulator supports the sdf annotate system task the Standard Delay Format SDF file is automatically read when the simulator compiles the Verilog simulation netlist If the simulator does not support sdf annotate in order to get timing values applied to the gate level netlist you must manually specif
5. library IEEE use IEEE std logic 1164 a11l entity rom rtl is port ADDR in INTEGER range 0 to 1023 CLK in std logic DATA out STD LOGIC VECTOR 3 downto 0 end rom rtl www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Memory XILINX architecture XILINX of rom rtl is subtype ROM WORD is STD LOGIC VECTOR type ROM TABLE constant RO ROM WORD ROM WORD ROM WORD ROM WORD ROM WORD ROM WORD ROM WORD ROM WORD ROM WORD ROM WORD ROM WORD ROM WORD ROM WORD ROM WORD ROM WORD ROM WORD begin process is array ROM TABLE 0000 0001 0010 0100 1000 11901 LOLOT 51 001 1001 1010 1100 X001 1003 UETOT 1011 ULI CLK begin if clk event and clk 1 DATA lt ROM ADDR end if end process end XILINX 0 to 1023 ROM TABLE then Read from the ROM 3 downto 0 of ROM WORD E RTL Description of a ROM Verilog Example using Block SelectRAM Following is some incomplete Verilog that demonstrates the above inference rules This code is incomplete but demonstrates the rules for inferring Block RAM for ROMs ROM RTL V Block RAM ROM Hy module rom rtl A input 9 0 input CLK output reg 3 0 DATA Example DDR CLK ADDR 3 0 DATA
6. generic size integer 3 port Clk in std logic reset in std logic qout out std logic vector size 1 downto 0 end johnson architecture RTL of johnson is signal q std logic vector size 1 downto 0 begin REL process clk reset begin if reset 1 then q lt others gt 0 elsif clk event and clk 1 then for i in 1 to size 1 loop q i lt q i 1 end loop i q 0 lt not q size 1 end if end process gout lt q end RTL e Verilog example module johnson clk reset q parameter size 4 input clk reset output size 1 0 q reg size 1 0 q integer i always posedge clk or posedge reset if reset q lt 0 else begin for i 1 i lt size i it l1 qli lt q i 11 q 0 lt a size 1 end endmodule johnson 150 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Operators and Generate Modules Comparator XILINX Magnitude comparators gt or infer carry chain logic and result in fast implementations in Xilinx devices Equality comparator VHDL example Unsigned 8 bit greater or library ieee use ieee std logic 1164 all is implemented using LUTs qual comparator use ieee std logic unsigned all entity compar is port A B cmp end compar out std logic in std logic vector 7 downto 0 architecture archi of compar is begin when A gt
7. 104 wwWw xilinx com 1 800 255 7778 Synthesis and Verification Design Guide Using Advanced Clock Management 7 XILINX clk_buf0 BUFG port map I gt clkO0 dcm1 DCM port map CLKFB gt clock_with_ps CLKIN gt clock DSSEN gt low PSCLK gt low PSEN gt low PSINCDEC gt low RST gt low CLKO gt clkl LOCKED gt deml_locked clk_bufl BUFG port map I gt clkl O gt clock with ps end XILINX e Verilog example for LeonardoSpectrum module DCM_TOP clock_in clock_out clock_with_ps_out reset input clock in output clock out output clock with ps out output reset wire wire wire wire wire wire wire low high dcmO0 locked dcml locked reset Clk0 ediki assign low assign high assign reset 1 b0 IBUFG CLOCK_IN I clock in O clock 1 pDpls dcm0 locked amp dcoml locked O gt clock out int Synthesis and Verification Design Guide wwWw xilinx com 1 800 255 7778 105 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X DCM DCMO CLKFB clock out CLKIN clock DSSEN low PSCLK low PSEN low PSINCDEC low RST low CLKO0O ELKO CLK90 CLK180 CLK270 C
8. DATA Synthesis and Verification Design Guide wwWw xilinx com 1 800 255 7778 179 180 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X A memory is implemented using a case statement always posedge CLK begin case ADDR 9 5000000000 DATA 4 b0000 9 5000000001 DATA 4 b0001 9 5000000010 DATA 4 b0010 9 5000000011 DATA 4 b0100 9 5000000100 DATA 4 b1000 9 5000000101 DATA 4 b1000 9 5000000110 DATA 4 b1100 9 5000000111 DATA 4 b1010 9 5000001000 DATA 4 b1001 9 5000001001 DATA 4 b1001 9 5000001010 DATA 4 b1010 9 5000001011 DATA 4 b1100 9 5000001100 DATA 4 b1001 9 5000001101 DATA 4 b1001 9 5000001110 DATA 4 b1101 9 5000001111 DATA 4 b1111 endcase end endmodule Implementing FIFO FIFO can be implemented with FPGA RAMs Xilinx provides several Application Notes describing the use of FIFO when implementing FPGAs Please refer to the following Xilinx Application Notes for more information Xilinx XAPP175 High Speed FIFOs in Spartan II FPGAs application note v1 0 11 99 Xilinx XAPP131 170MHz FIFOs using the Virtex Block SelectRAM Feature v 1 2 9 99 Implementing CAM Content Addressable Memory CAM or associative memory is a storage device which can be addressed b
9. 0 0 0000 cece eee eee 53 Comparing Signals and Variables VHDL only 54 10 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 lt XILINX Using Signals VHDL esq vied epee ean vee c e y rr CA bed DE EM eel ed 55 Using Variables VEDE cites retten ox reti kara edid eio qs 56 Coding for Synthesis i4iceesecestk ceca ee e e Ce dr CE or e e ed 56 Omit the Wait for XX ns Statement 0 0 cen eect e eens 57 Omit the After XX ns or Delay Statement 2 2 06 6 6 0 57 Omit Initial Val esz 2i sessi etae eR Ep e e e ecto ad eed aed 57 Order and Group Arithmetic Functions 0 0 0 0 cece eee eee 57 Comparing If Statement and Case Statement 0 000 58 4 to 1 Multiplexer Design with If Construct 0 2 6 cece cece eee eee 59 4 to 1 Multiplexer Design with Case Construct 0 6 6 c cece ee eee 61 Implementing Latches and Registers 0 0 0 6c ccc eee 63 D Latch Inference ue oerte oe 63 Converting D Latch to D Register 2 6 n 64 Resource Sharing e peii gnenn egie enge tee doe Ace bep Re tecto s 65 Reducing Gate Count i4 cose e Wee i a tee debe ep Ed 67 Using Preset Pin or Clear Pin 6 nee 68 Register Inference is ed ob eee Reese die a ey ad eas 68 Using Clock Enable Pin Instead of Gated Clocks 0 0 00 cece eee eee 70 Chapter 4 Architecture Specific Coding Styles for Spartan II 8 Virtex V E II Il Pro Il Pro X Introduction ce
10. Synthesis and Verification Design Guide www xilinx com 249 1 800 255 7778 XILINX Chapter 6 Verifying Your Design Following is an example of the DCM instantiation Note the component declaration of the DCM as the parameters are defined in the generic section of the component declaration In order to use some of the DCM features these generic values must be modified library ieee use ieee std_logic_1164 all library unisim use unisim vcomponents all entity clock_gen is port clkin rst dll in std logic Clk clk not locked out std logic psen psclk psincdec in std logic psdone out std logic end clock gen architecture structural of clock gen is signal clk ibufg clk dcm clk dcm not std logic signal clk0 bufg cl1k180 bufg std logic signal GND std logic component IBUFG port I in std logic O out std logic end component component BUFG port I in std logic O out std logic end component component DCM generic DFS FREQUENCY MODE string LOW DLL FREQUENCY MODE string LOW DUTY CYCLE CORRECTION boolean TRUE CLKIN DIVIDE BY 2 boolean FALSE CLK FEEDBACK string 1X CLKOUT PHASE SHIF string NONE FACTORY JF bit vector X 00 STARTUP WAIT boolean FALSE DSS MODE string NONE PHASE SHIFT integer 0 CLKFX
11. CLKI DSSE PSINC DEC PSEN gt psen PSCLK PSDONI n gt psclk gt psdone RST gt rst dll CLKO gt clk dem CLKDV open CLKFX gt open CLK180 gt clk dcm not LOCKED locked SYSTEM SYNCHRONOUS gt psincdec Synthesis and Verification Design Guide wwWw xilinx com 1 800 255 7778 251 XILINX Chapter 6 Verifying Your Design U3 BUFG port map I gt clk_dcm O gt clk0_bufg U4 BUFG port map gt clk_dcm_not O gt clk180 bufg clk lt clk0 bufg clk_not lt clk180 bufg end structural Note Some synthesis tools may not support the use of a generic statements See the Generics Support Considerations section for details Simulating SRLs Most synthesis tools infer the SRL16 from behavioral VHDL For these designs no special simulation steps are needed for the SRLs However when the SRL component is instantiated the INIT attribute can be used to initialize the contents of the component Also to use the select lines of the SRL component instantiation is generally necessary Refer to Implementing Shift Registers Virtex E II II Pro II Pro X and Spartan 11 3 for more details on inferring SRLs correctly in the design Following is an example of passing the INIT attribute to the SRL for functional simulation Note f the synthesis tool being used can accept generics to pass attributes the
12. E EES ete Got TEET P E EA dell ae aa ela ee Gale iene acct Noreen 296 RTL to Post Place and Route 00 ccc cece eee 297 Implementing the Design and Running NetGen 000 e eee eee eee ee 297 Creating a DO File to Run RTL vs Post PAR Verification 000005 298 Running the DO File in Conformal FPGA 6 00 eee eee 298 Using CORE Generator Components with Conformal RTL vs Post PAR Verification298 Known Issues 4 2 hbk ede e ede bia aah Rd PE GR RE Reda PRX dg uua doe a REA 299 Synthesis and Verification Design Guide www xilinx com 17 1 800 255 7778 2 XILINX 18 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 XILINX Chapter 1 Introduction This chapter provides a general overview of designing Field Programmable Gate Arrays FPGAs with HDLs and also includes installation requirements and instructions It includes the following sections e Architecture Support e Overview of Hardware Description Languages e Advantages of Using HDLs to Design FPGAs e Designing FPGAs with HDLs e Xilinx Internet Websites e Vendor Support Sites Architecture Support The software supports the following architecture families in this release e Virtex II E e Virtex II PRO and Virtex II PRO X e Spartan II IIE 3 e CoolRunner XPLA3 II IIS e XC9500 XL XV Overview of Hardware Description Languages Hardware Descript
13. Emulating the Global GTS pulse in a VHDL Functional Simulation In most cases it is not necessary to emulate the global GTS pulse but if pre configuration behavior of the device I Os needs to be incorporated into the functional simulation you can use the following e Use the TOC cell to generate a one time GTS pulse at the beginning of the simulation as described in the Using VHDL Tristate On Configuration TOC section e Use the TOCBUF cell and control the emulated GTS signal in the test bench as described in the Using VHDL TOCBUF section Using VHDL Tristate On Configuration TOC The TOC cell which is modeled in the UNISIM library can be used to emulate the GTS pulse at the beginning of a functional simulation This is the same component that is automatically inserted into the back end netlist It generates a one time pulse at the beginning of the simulation that lasts for a default value of 100ns The pulse width is a generic that can be passed to the TOC model to change the pulse width Note The default pulse width in the UNISIM TOC model is 100 ns but the default pulse width in the back end netlist is 0 When using the TOC cell in a functional simulation the tpw switch can be used in NetGen to change the pulse width to match the functional simulation During implementation the signal connected to the output of the TOC component will automatically be mapped to the Global GTS network and will not be routed on loc
14. Specify whether paths in simulator commands should be described in VHDL or Verilog format For VHDL PathSeparator for Verilog PathSeparator Comment the following statement called PathSeparator by adding a at the start of the line 3 After the line List of dynamically loaded objects for Verilog PLI applications add the following statement Veriuser MODEL TECH libswiftpli sl DENALI mtipli so 4 After the line H Logic Modeling s SmartModel SWIFT software Sun4 Solaris 2 x add the following statements libsm MODEL TECH libsm sl libswift LMC HOME lib sun4Solaris lib libswift so www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Running Simulation XILINX Note Itis important to make the changes in the order in which the commands appear in the modelsim ini file The simulation may not work if the order recommended above is not followed After editing the modelsim ini file add the following environment variable to the MTI ModelSim SE setup script setenv MODELSIM path_to_modelsim ini_script modelsim ini If the MODELSIM environment variable is not set properly MTI might not use this INI file and then the initialization settings required for simulation will not be read by the simulator Set up the MTI ModelSim SE simulation environment by sourcing the MTI SE setup script from the terminal Running Simulation In
15. Technical Support Website Answers to questions tutorials Application notes software manuals and information on using Xilinx products can be found on the technical support website You can reach the support website at http www support xilinx com The following features can be accessed from the Xilinx support website Troubleshoot You can do an advanced search on the Answers Database to troubleshoot questions or issues you have with your design Software You can download the latest software service packs IP updates and product information from the Xilinx Support Website Library You can view the Software manuals from this website The manuals are provided in both HTML viewable through most HTML browsers and PDF The Databook CORE Generator documentation and data sheets are also available Design You can find helpful application notes that illustrate specific design solutions and methodologies Services You can open a support case when you need to have information from a Xilinx technical support person You can also find information about your hardware or software order Feedback We are always interested in how well we re serving our customers You can let us know by filling out our customer service survey questionnaire You can contact Xilinx technical support and application support for additional information and assistance in the following ways www xilinx com Synthesis and Verific
16. 2OUTI ENABLE X4976 Figure 3 7 Implementation of Clock Enable 74 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 XILINX Chapter 4 Architecture Specific Coding Styles for SpartanM I 3 Virtex M E II 1I Prol II Pro X Introduction This chapter includes coding techniques to help you improve synthesis results It includes the following sections Introduction Instantiating Components e Using Boundary Scan JTAG 1149 1 e Using Global Clock Buffers e Using Advanced Clock Management e Using Dedicated Global Set Reset Resource e Implementing Inputs and Outputs e Encoding State Machines e Implementing Operators and Generate Modules e Implementing Memory e Implementing Shift Registers Virtex E II II Pro II Pro X and Spartan IT 3 e Implementing Multiplexers e Using Pipelining e Design Hierarchy This chapter highlights the features and synthesis techniques in designing with Xilinx Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X Spartan II and Spartan 3 FPGAs Virtex Virtex E and Spartan II devices share many architectural similarities Virtex II Virtex II Pro Virtex II Pro X and Spartan 3 provide an architecture that is substantially different from Virtex Virtex E and Spartan II however many of the synthesis design te
17. BCLK dll out CLKDLL port map CLKIN gt ACLK ibufg CLKFB gt BCLK ibufg RST gt Q CLK2X gt OUTBCLK CLKO gt OPEN CLK90 gt OPEN CLK180 gt OPEN CLK270 gt OPEN CLKDV gt OPEN LOCKED gt BCLK_lock process ACLK 2x design RESET begin if RESET 1 then QOUT 00 elsif ACLK 2x design event and ACLK 2x design 1 then if ACLK lock 1 then QOUT lt DIN end if end if end process END RTL e Verilog example Verilog Example In this example ACLK s frequency is doubled used inside and outside the chip BCLK and OUTBCLK are connected in the board outside the chip module clock test ACLK DIN QOUT BCLK OUTBCLK BCLK LOCK RESET input ACLK BCLK input RESET input 1 0 DIN output 1 0 QOUT output OUTBCLK BCLK LOCK reg 1 0 QOUT IBUFG CLK ibufg A I ACLK O ACLK ibufg BUFG ACLK bufg I ACLK 2x O ACLK 2x design IBUFG CLK ibufg B I BCLK connected to OUTBCLK outside O BCLK ibufg 86 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Using Advanced Clock Management lt XILINX CLKDLL ACLK dll 2x 2x clock LKIN ACLK ibufg LKFB ACLK 2x design ST 1 b0 LK2X ACLK 2x LKO LK90 LK180 LK270 CLKDV LOCKED ACLK lock QC C R ei JG C C C
18. Instance The instance name used in the parent module Design File The name of the file that contains the module SDF File The SDF file associated with the module SubModule The sub module s contained within a given module Module Instance The sub module and instance names Module submodule Instance submodule_inst Design File submodule_sim v SDF File submodule_sim sdf SubModule NONE Synthesis and Verification Design Guide www xilinx com 261 1 800 255 7778 lt XILINX Chapter 6 Verifying Your Design Module design_top Design File design_top_timesim v SDF File design_top_timesim sdf SubModule submodule Module submodule Instance submodule_inst Note Hierarchy created by generate statements may not match the original simulation due to naming differences between the simulator and synthesis engines for generated instances RTL Simulation Using Xilinx Libraries Since Xilinx simulation libraries are VHDL 93 and Verilog 2001 compliant they can be simulated using any simulator that supports these language standards However certain delay and modelling information is built into the libraries which is required to correctly simulate the Xilinx hardware devices Xilinx recommends not changing data signals at clock edges even for functional simulation The simulators add a unit delay between the signals that change at the same simulator time If the data changes at the same time
19. Spartan IIE Spartan 3 e Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X Equivalency Checking Compatible Simulation Models There are two Xilinx verification libraries that are used along with the equivalency checking EC tools These are e UNISIM The UNISIM library contains the Xilinx primitives in RTL format This library is required if the design contains any Xilinx primitives for example an instantiation of a DCM or Block RAM These libraries are located at SXILINX verilog formality unisims SXILINX verilog verplex unisims e SIMPRIM The SIMPRIM library contains the Xilinx Primitives for back annotated Verification post NGDBuild post Map and post PAR Since the back annotated netlist is composed completely of these gate level primitives this library needs to be read before verifying a post NGDBuild post Map or post PAR design These libraries are located at SXILINX verilog formality simprims SXILINX verilog verplex simprims See the Setup for Synopsys Formality and Setup for Verplex Conformal FPGA sections for information on how to read these libraries into the equivalency checking tools Setup for Synopsys Formality and Verplex Conformal FPGA This section describes the information needed to set up Formality or Conformal FPGA for verifying Xilinx designs Setup for Synopsys Formality Following is a table of the enviro
20. This chapter describes the special considerations that should be taken when simulating designs for Virtex II Pro and Virtex II Pro X FPGAs The Virtex II Pro family is a platform FPGA for designs that are based on IP cores and customized modules The family incorporates RocketIO and PowerPC CPU cores in Virtex II Pro Series FPGA architecture The programable logic portion of the Virtex II Pro family is based on Virtex II While it is not bitstream or pin compatible it can be programmed using the same methods as Virtex II and Virtex II designs and can be implemented into Virtex II Pro devices In general for details specific to designing for Virtex II Pro and Virtex II Pro X see the Virtex II Pro Platform FPGA User Guide and the RocketIO User Guide Using SmartModels to Simulate Virtex ll Pro Designs SmartModels are an encrypted version to the actual HDL code These models allow the user to simulate the actual functionality without having access to the code itself The Xilinx Virtex II Pro family of devices gives the designer many new features such as IBM s PowerPC microprocessor and the RocketlIO However simulation of these new features requires the use of Synopsys SmartModels along with the user design This section gives the Virtex II Pro simulation flow It is assumed that the reader is familiar with the Xilinx FPGA simulation flow Synthesis and Verification Design Guide www xilinx c
21. e Larly Testing of Various Design Implementations HDLs allow you to test different implementations of your design early in the design flow You can then use the synthesis tool to perform the logic synthesis and optimization into gates Additionally Xilinx FPGAs allow you to implement your design at your computer Since the synthesis time is short you have more time to explore different architectural possibilities at the Register Transfer Level RTL You can reprogram Xilinx FPGAs to test several implementations of your design e Reuse of RTL Code You can retarget RTL code to new FPGA architectures with a minimum of recoding Designing FPGAs with HDLs If you are more familiar with schematic design entry you may find it difficult at first to create HDL designs You must make the transition from graphical concepts such as block diagrams state machines flow diagrams and truth tables to abstract representations of design components You can ease this transition by not losing sight of your overall design plan as you code in HDL To effectively use an HDL you must understand the syntax of the language the synthesis and simulator software the architecture of your target device and the implementation tools This section gives you some design hints to help you create FPGAs with HDLs Using Verilog 20 Verilog is popular for synthesis designs because it is less verbose than traditional VHDL and it is standardized as IEEE STD 1
22. e Names cannot be more than 256 characters long The following FPGA resource names are reserved and should not be used to name nets or components e Components Comps Configurable Logic Blocks CLBs Input Output Blocks IOBs Slices basic elements bels clock buffers BUFGs tristate buffers BUFIs oscillators OSC CCLK DP GND VCC and RST e CLB names such as AA AB SLICE R1C2 SLICE X1Y2 X1Y2 and R1C2 e Primitive names such as TDO BSCAN MO M1 M2 or STARTUP e Do not use pin names such as P1 and A4 for component names Donot use pad names such as PAD1 for component names Refer to the language reference manual for Verilog or VHDL for language specific naming restrictions Xilinx does not recommend using escape sequences for illegal characters Also if you plan to import schematics into your design use the most restrictive character set Matching File Names to Entity and Module Names Xilinx recommends the following practices in naming your HDL files e Ensure that the VHDL or Verilog source code file name matches the designated name of the entity VHDL or module Verilog specified in your design file This is less confusing and generally makes it easier to create a script file for the compilation of your design e If your design contains more than one entity or module each should be contained in a separate file with the appropriate file name e Itis a good idea to use the same name as your top level d
23. e The family option can be virtex virtexe virtex2 virtex2p spartan2 spartan2e or spartan3 e The Perl script runs the following commands ngdbuild p family coregen module edn netgen ecn conformal coregen module ngd coregen module for v www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Conformal FPGA and FPGA Compiler II Flow XILINX The output from NetGen is a Verilog representation of the core that is read in with the RTL design as part of the golden reference design You must run the core2formal p1 script on each CORE Generator module in the design RTL to Post Place and Route The second and final point at which most designers verify the functionality of their design is after place and route PAR This is the final transformation of the design The entire design has been mapped into primitive components and placed and routed on the FPGA By running an equivalence check between the golden RTL and the post PAR netlist you can verify that the optimizations and transformations done by the Xilinx implementation tools did not affect the functionality of the design The equivalence check includes the following steps 1 Implement the design with the Xilinx implementation tools and run NetGen to create a Verilog netlist Create a DO file for running the verification in Conformal FPGA Run the DO file If the two netlists are not equivalent use Conformal FPGA to debug the differences
24. e run do A script file used by the simulate script to run the complete simulation Once each of these files has been properly updated you can run the simulation by sourcing the setup and simulate files MTI amp ModelSim SE Windows Simulator Setup Although ModelSim SE supports the SWIFT interface some modifications must be made to the default ModelSim setup to enable this feature The ModelSim install directory contains an initialization file called modelsim ini In this initialization file users can edit GUI and Simulator settings to default to their preferences Parts of this modelsim ini file must be edited to work properly with the Virtex II Pro device simulation models Synthesis and Verification Design Guide www xilinx com 197 1 800 255 7778 XILINX 198 Chapter 5 Virtex Il Pro Considerations The following changes are needed in the modelsim ini file These changes can be made to the modelsim ini file located in the MODEL TECH directory An alternative to making these edits is to change the MODELSIM environment variable setting in the MTI setup script to point to the modelsim ini file located in the each example s design directory 1 After the lines Simulator resolution Set to fs ps ns us ms or sec with optional prefix of 1 10 or 100 Change the Statement that follows from Resolution ns to Resolution ps 2 After the lines Specify whether paths in simulato
25. q lt data ff 4 else if condl_ff 5 amp amp cond2 ff 5 q lt data ff 5 else if condl_ff 6 amp amp cond2_ff 6 q lt data ff 6 else if condl_ff 7 amp amp cond2_ff 7 q lt data ff 7 else if condl_ff 8 amp amp cond2 ff 8 q lt data ff 8 else q lt 1 b0 endmodule prior Implementing Memory Virtex E and Spartan II FPGAs provide distributed on chip RAM or ROM memory capabilities CLB function generators can be configured as e ROM ROMI6XI ROM32X1 e edge triggered single port RAM16X15 RAM32X1S RAM e dual port RAM16x1D RAM Level sensitive RAMs are not available for the Virtex E and Spartan II families Virtex II TI Pro II Pro X or Spartan 3 CLB function generators are much larger and can be configured as larger ROM and edge triggered single port and dual port RAM Available ROM primitive components in Virtex I II Pro II Pro X or Spartan 3 are e ROM16X1 e ROM32X1 Synthesis and Verification Design Guide www xilinx com 153 1 800 255 7778 154 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Available single port RAM primitives components in Virtex II II Pro II Pro X or Spartan 3 are RAMI16X15 RAM32X15 RAM64X1S RAM16X2S RAM32X2S RAM64X2S RAM16X4S RAM32X4S RAM128X1S RAM16X8S RAM32X8S Available dual port RAM primitive components in Virtex II II Pro II Pro X or
26. use IEEE std logic 1164 a11 inst ramb4 s4 name entity spblkrams is port CLK in std logic EN in std logic RST in std logic WE in std logic ADDR in std logic vector 11 downto 0 DI in std logic vector 15 downto 0 DORAMBA S4 out std logic vector 3 downto 0 DORAMBA S8 out std logic vector 7 downto 0 end architecture struct of spblkrams is component RAMBA S4 port DI in SI EN in S31 WE in S7 RST C ADDR in ID LOGIC V ID ULOGIC ID ULOGIC in STD ULOGIC LK in STD ULOGIC STD LOGIC VECTOR 9 downto 0 ECTOR 3 downto 0 DO out STD LOGIC VECTOR 3 downto 0 end component component RAMBA S8 port DI in S31 EN in SI WE in S1 RST G ADDR in ID LOGIC V ID ULOGIC ID ULOGIC in STD ULOGIC LK in STD ULOGIC STD LOGIC VECTOR 8 downto 0 ECTOR 7 downto 0 DO out STD LOGIC VECTOR 7 downto 0 i end component attribute INIT O0 attribute INIT O0 0 string 0 of INST RAMBA S4 label is IF1E1D1C1B1A191817161514131211100F0E0D0C0B0A0980706050403020100 attribute INIT O0 0 of INST RAMBA S8 label is IFIE1D1C1B1A191817161514131211100F0E0D0C0B0A0980706050403020100 Synthesis and Verification Design Guide wwWw xilinx com 1 800 255 7778 155 SZ XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex
27. 50 Chapter 3 General HDL Coding Styles module BUFG I O synthesis black box input I output O0 endmodule Understanding Synthesis Tools Naming Convention Some net and logic names are preserved and some are altered by the synthesis tools during the synthesis process This may result in a netlist that is hard to read or trace back to the original code This section discusses how different synthesis tools generate names from your VHDL Verilog codes This helps you corollate nets and component names appearing in the EDIF netlist It also helps corollate nets and names during your after synthesis design view of the VHDL Verilog source Note The following naming conventions apply to inferred logic The names of instantiated components and their connections and port names are preserved during synthesis FPGA Compiler II Naming Styles Register instance outputsignal_reg Output of register outputsignal_reg Output of clock buffer signal_BUFGed Output of tristate signal_tri Port names preserved Hierarchy notation _ e g hier 1 hier 2 Other inferred component and net names are machine generated LeonardoSpectrum Naming Styles Register instance reg outputsignal Output of register preserved except if the output is also an external port of the design In this case it is signal dupO Clock buffer ibuf driversignal ibuf Output of clock buffer ibuf driversignal int Tristate instance tri outp
28. All other trademarks are the property of their respective owners Xilinx Inc does not assume any liability arising out of the application or use of any product described or shown herein nor does it convey any license under its patents copyrights or maskwork rights or any rights of others Xilinx Inc reserves the right to make changes at any time in order to improve reliability function or design and to supply the best product possible Xilinx Inc will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products Xilinx provides any design code or information shown or described herein as is By providing the design code or information as one possible implementation of a feature application or standard Xilinx makes no representation that such implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation including but not limited to any warranties or representations that the implementation is free from claims of infringement as well as any implied warranties of merchantability or fitness for a particular purpose Xilinx Inc devices and products are protected under U S Patents Other U S and foreign patents pending Xilinx Inc does not represent that devices shown or products described h
29. During implementation the TOC is removed from the logical description and the global tristate net resource is used e Back annotation Phase In this phase the Xilinx VHDL netlist program assumes all registers are driven by the GTS net uses the X TOC simulation model for the TOC and rewires it to the GTS nets in the back annotated netlist For a non hierarchical netlist the GTS net is a fully wired net and the X TOC cell drives it For a hierarchical netlist the GTS net is not wired across hierarchical modules The GTS net in each hierarchical module is driven by an X TOC cell The TOC pulse width of the X TOC component can be controlled using the tpw switch for NetGen Synthesis and Verification Design Guide www xilinx com 239 1 800 255 7778 XILINX Chapter 6 Verifying Your Design Using VHDL TOCBUF A second method of emulating GTS in the functional simulation is to use the TOCBUF This component creates a buffer for the global GTS net and provides an input port on the buffer to drive GTS This port must be declared in the entity list and driven in RTL simulation This method is applicable when system level issues make your design s initialization synchronous to an off chip event In this case you provide a pulse that tristates the outputs at the start of simulation time and you possibly provide further pulses as simulation time progresses perhaps to simulate cycling power to the device During the place and ro
30. E Il II Pro II Pro X begin INST RAMBA S4 RAMBA S4 port map DI gt DI 3 downto 0 EN gt EN gt WE ST gt RST LK gt CLK DDR gt ADDR 9 downto 0 DO gt DORAMB4_S4 INST RAMBA S8 RAMBA S8 port map DI gt DI 7 downto 0 EN gt E WE gt WE RST gt RST CLK gt CLK ADDR gt ADDR 8 downto 0 DO gt DORAMBA S8 end struct XST library IEEE use IEEE std_logic_1164 all entity spblkrams is port DAVI CLK in std logic EN in std_logic RST in std_logic WE in std_logic ADDR in std logic vector 11 downto 0 DI in std_logic_vector 15 downto 0 DORAMBA S4 out std logic vector 3 downto 0 DORAMBA S8 out std logic vector 7 downto 0 end architecture struct of spblkrams is component RAMBA S4 generic INIT 00 string 0000000000000000000000000000000000000000000000000000000000000000 port DI in STD LOGIC VECTOR 3 downto 0 EN in STD ULOGIC WE in STD ULOGIC RST in STD ULOGIC C A LK in STD ULOGIC DDR in STD LOGIC VECTOR 9 downto 0 DO out STD LOGIC VECTOR 3 downto 0 end component 156 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Memory Z XILINX component RAMB4_S8 generic INIT_00 string 00000000000000000000000000000000000000000000
31. Synthesis and Verification Design Guide www xilinx com 271 1 800 255 7778 lt XILINX Chapter 6 Verifying Your Design outputs an X value signifying an unknown output If the two ports are writing data to the same address at the same time the model can write unknown data into memory Special care should be taken to avoid this situation as unknown results may occur from this action For the hardware documentation on collision checking refer to the Design Considerations chapter Using Block SelectRAM Memory section of the Virtex II Platform FPGA User Guide Hierarchy Considerations It is possible for the top level signals to switch correctly keeping the setup and hold times accounted for and at the same time have an error reported at the lowest level primitive in the design This can happen because as the signals travel down through the hierarchy to this low level primitive the delays they go through can reduce the differences between them to the point where they begin to violate the setup time To correct this problem follow these steps 1 Browse the design hierarchy and add the signals of the instance reporting the error to the top level waveform Ensure that the setup time is indeed being violated at the lower level 2 Step back through the structural design until a link between an RTL pre synthesis design path and this instance reporting the error can be determined 3 Constrain the RTL path using timing constra
32. To fully understand the simulation model you must first understand that there are differences in the way the DLL DCM is built in silicon the way TRACE reports their timing and the way the DLL DCM is modeled for simulation The DLL DCM simulation model attempts to replicate the functionality of the DLL DCM in the Xilinx silicon but it does not always do it exactly how it is implemented in the silicon In the silicon the DLL DCM uses a tapped delay line to delay the clock signal This accounts for input delay paths and global buffer delay paths to the feedback in order to accomplish the proper clock phase adjustment TRACE or Timing Analyzer reports the phase adjustment as a simple delay usually negative so that you can adjust the clock timing for static timing analysis As for simulation the DLL DCM simulation model itself attempts to align the input clock to the clock coming back into the feedback input Instead of putting the delay in the DLL or DCM itself the delays are handled by combining some of them into the feedback path as clock delay on the clock buffer component and clock net port delay The remainder is combined with the port delay of the CLKFB pin While this is different from the way TRACE or Timing Analyzer reports it and the way it is implemented in the silicon the end result is the same functionality and timing TRACE and simulation both use a simple delay model rather than an adjustable delay tap line similar to silicon
33. Using Dedicated Global Set Reset Resource lt XILINX The following VHDL Verilog examples show a STARTUP_VIRTEX instantiation using both GSR and GTS pins in Synplify In the examples STARTUP_VIRTEX_GSR and STARTUP_VIRTEX_GTS are instantiated together to get the GSR and GTS pins connected The resulting EDIF netlist has only one STARTUP_VIRTEX block with GTS and GSR connections The CLK pin of the STARTUP_VIRTEX are unconnected If all pins GSR GTS and CLK in the STARTUP block are needed use STARTUP_VIRTEX to port map the pins e VHDL example library IEEE virtex synplify use synplify attributes all use virtex components all use IEEE std logic 1164 a11 entity setreset is port CLK in std logic DIN1 in STD LOGIC DIN2 in STD LOGIC RESET in STD LOGIC GTSInput in STD LOGIC DOUT1 out STD LOGIC DOUT2 out STD LOGIC DOUT3 out STD LOGIC end setreset architecture RTL of setreset is begin u0 STARTUP VIRTEX GSR port map GSR gt RESET ul STARTUP VIRTEX GTS port map GTS GTSInput reset process process CLK RESET begin if RESET 1 then DOUT IL gt elsif CLK event and CLK 1 then DOUT1 lt DINI end if end process gtsprocess process GTSInput begin if GTSInput 0 then DOUT3 0 DOUT2 DIN2 else DOUTZ lt Z DOUT3 lt Z end if end process end RTL
34. always posedge clk begin addr_reg lt addr if we mem addr lt din end assign dout mem addr reg endmodule Synthesis and Verification Design Guide www xilinx com 165 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan Il 3 Virtex E Il II Pro II Pro X Implementing Distributed SelectRAM Distributed SelectRAM can be either instantiated or inferred The following sections describe and give examples of both instantiating and inferring distributed SelectRAM The following RAM Primitives are available for instantiation e Static synchronous single port RAM RAM16x1S RAM32x1S Additional single port RAM available for Virtex II II Pro II Pro X and Spartan 3 devices only RAM16X25 RAM16X4S RAM16X8S RAM32X1S RAM32X2S RAMS32X4S RAM32X8S RAM64X1S RAM64X2S and RAM128X15S e Static synchronous dual port RAM RAM16x1D RAM32x1D Additional dual port RAM is available for Virtex II II Pro II Pro X or Spartan 3 devices only RAM64X1D For more information on distributed SelectRAM refer to the Libraries Guide Instantiating Distributed SelectRAM in VHDL The following examples provide VHDL coding hints for FPGA Compiler II LeonardoSpectrum Synplify and XST e FPGA Compiler II and XST This example shows how to create a 16x4s RAM using xilinx RAM16x1S component library IEEE u
35. and later architectures have been updated to accept both the positive and negative inputs The following is an example of an instantiated differential I O in a Virtex E or Spartan ITE design module lvds ex data data op data on input data output data op data on Input side IBUF LVDS IO I data O data int Output side OBUF LVDS OPO I data int O data op wire data n int data int OBUF LVDS ONO I data n int O data on endmodule LUT For simulation the INIT attribute passed by the defparam statement is used to initialize contents of the LUT for functional simulation The following is an example of the defparam statement being used to initialize the contents of a LUT module lut ex LUT1 OUT LUT1 IN input 1 0 LUT1 IN output 1 0 LUT1 OUT LUT1 used as an inverter LUT1 UO O LUT1 OUT 0 IO LUT1 IN 0 defparam UO INIT 2 b01 LUT1 used as a buffer LUT1 U1 O LUT1 OUT 1 IO LUT1 IN 1 defparam U1 INIT 2 b10 endmodule Note Some synthesis tools may not support the use of a defparam statements See the Defparam Support Considerations section for details SRL16 For inferred SRL16s no attributes need to be passed to the simulator However if the SRL16 component is being instantiated and if non zero contents are desired for initialization the INIT attribute passed by the defparam statement is used to
36. component tenths port CLOCK in STD LOGIC CLK EN in STD LOGIC Q OUT out STD LOGIC VECTOR 9 downto 0 end component attribute black box of tenths component is true begin Verilog Attribute Examples The following are examples of attribute passing in Verilog Note that attribute passing in Verilog is synthesis tool specific e Attribute use in FPGA Compiler II syntax synopsys attribute name value Example BUFG CLOCKB I oscout O clkint synopsys attribute LOC BR or RAMB4_S4 U1 WE w EN en RST r CLK ck ADDR ad DI di DO do synopsys attribute INIT 00 AAAAAAAAAAAAAAAABBBBBBBBBBBBBBBB INIT 09 99999988888888887777777776666666 e Attribute use in LeonardoSpectrum syntax exemplar attribute object_name attribute_name attribute_value Examples RAMB4_S8 UO WE WE EN 1 b1 RST 1 b0 CLK CLK ADDR ADDR DI DIN DO DOUT exemplar attribute UO INIT 00 l1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A0908070605040 3020100 e Attribute use in Synplify syntax synthesis directive synthesis attribute namezszvalue Or synthesis directive synthesis attribute namezvalue Examples FDCE u2 D q1 CE ce C clk CLR rst Q qo synthesis rloc ri1c0 s0 or Synthesis and Verification Design Guide www xilinx com 49 1 800 255 7778 2 XILINX
37. cond2 end if end process process clk begin if clk event and clk 1 then if condl ff 1 1 and cond2 ff 1 1 then q lt data ff 1 elsif cond1 ff 2 1 and cond2 ff 2 1 then q lt data ff 2 elsif condl1 ff 3 1 and cond2 ff 3 q lt data ff elsif condl1 ff 4 1 and cond2_ff 4 q lt data ff elsif condl1 ff 5 1 and cond2 ff 5 1 then q lt data ff elsif condl1 ff 6 1 and cond2_ff 6 q lt data ff elsif cond1 ff 7 1 and cond2 ff 7 1 then q lt data ff elsif condl1 ff 8 1 and cond2_ff 8 q lt data ff else q lt 0 end if end if end process end RTL p then then ll p 1 then 117 then 152 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Memory Z XILINX e Verilog example module prior clk condl cond2 data q parameter size 8 input clk input l size data condl cond2 output q reg 1 size data ff condl_ff cond2_ff reg q always posedge clk begin data_ff data condl_ff condl cond2 ff cond2 end always posedge clk if cond1 ff 1 amp amp cond2 ff 1 q lt data ff 1 else if condl_ff 2 amp amp cond2 ff 2 q lt data ff 2 else if condl_ff 3 amp amp cond2 ff 3 q lt data ff 3 else if condl_ff 4 amp amp cond2 ff 4
38. end xilinx library IEEE use IEEE std_logic_1164 all use IEEE std logic unsigned all o o entity ram 16x4s is port o out std logic vector 3 downto 0 we in std logic Clk in std logic d in std logic vector 3 downto 0 a in std logic vector 3 downto 0 end ram 16x4s Synthesis and Verification Design Guide www xilinx com 169 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X architecture xilinx of ram_16x4s is component ram 16x1s generic init val port O D A3 string 0000 out std logic in std logic A2 Al AO in std_logic WE CLK in std_logic end component begin UO ram l6xls generic map FFFF port map O gt o 0 WE gt we CLK gt clk D gt d 0 AO gt a 0 Al gt a 1 A2 gt a 2 A3 gt a 3 U1 ram_16x1s generic map ABCD port map O gt o 1 WE gt we CLK gt clk D gt d 1 A0 gt a 0 Al gt a 1 A2 gt a 2 A3 gt a 3 U2 ram_l6xls generic map BCDE port map O gt o 2 WE gt we CLK gt clk D gt d 2 A0 gt a 0 A1 gt a 1 A2 gt a 2 A3 gt a 3 U3 ram_l6x1s generic map CDEF port map O gt o 3 WE gt we CLK gt clk D gt d 3 AO gt a 0 Al gt a 1 A2 gt a 2 A3 gt a 3 end
39. gt MUX OUT when 10 gt MUX OUT when 11 gt MUX OUT when others gt MUX OUT lt 0 A ll A ll ll D O D Pp end case end process End CASE PRO end BEHAV Synthesis and Verification Design Guide www xilinx com 61 1 800 255 7778 XILINX Chapter 3 General HDL Coding Styles e Verilog Example VLIUMMLMMlMlMMlllllllddd d MM M MI M NM I P gp Pg o ATT TT CASE EX V Example of a Case statement showing A mux created using parallel logic HDL Synthesis Design Guide for FPGAs VLIMMLMlMlMEll ll lll MM M P P P IM P P pP ATT TT module case ex A B C D SEL MUX OUT input A B C D input 1 0 SEL output MUX OUT reg MUX OUT always A or B or C or D or SEL begin case SEL 2 b00 MUX OUT 2 b01 MUX OUT 2 b10 MUX OUT 2 bl11 MUX OUT Mo l O QU default MUX OUT 0 endcase end endmodule One CLB P gt IBUF gt SEL 0 gt IBUF AL gt LUT4 IBUF B logic 0 IBUF c gt gt OBUF IBUF LUT4 gt gt MUX OUT D gt gt logic 0 L IBUF Ly SEL 1 X999t Figure 3 3 Case Ex Implementation 62 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Coding for Synthesis XILINX Implementing Latches and Registers Synthesizers infer latches from incomplete conditional expre
40. synthesis xc loc D8 output q n synthesis xc loc C8 synthesis attribute LOC d A5 synthesis attribute LOC q D8 synthesis attribute LOC q n C8 exemplar attribute d pin number A5 exemplar attribute q pin number D8 exemplar attribute q n pin number C8 wire d clk d 1lvds q reg q_lvds IBUF ul I d O d lvds synthesis xc props IOSTANDARD LVDS OBUF u2 I q l1vds O q synthesis xc props IOSTANDARD LVDS OBUF u3 I q l1vds n O q n synthesis xc props IOSTANDARD LVDS 130 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Inputs and Outputs Z XILINX synthesis attribute IOSTANDARD ul LVDS synthesis attribute IOSTANDARD u2 LVDS synthesis attribute IOSTANDARD u3 LVDS exemplar attribute ul IOSTANDARD LVDS exemplar attribute u2 IOSTANDARD LVDS exemplar attribute u3 IOSTANDARD LVDS always posedge clk q_lvds lt d_lvds assign q lvds n q lvds endmodule Reference Xilinx Answer Database in the Xilinx support website at http support xilinx com for more information In LeonardoSpectrum and Synplify you can instantiate the SelectIO components or use the attribute discussed in the Inputs section but make sure that the output and its inversion are declared and configured properly Virtex II Il Pro Il Pro X Spartan 3 IOBs Virtex II TI Pro II Pro X or Spartan
41. use IEEE std_logic_1164 all use IEEE std_logic_unsigned all library UNISIM use UNISIM all entity EX_ROC is port CLOCK ENABLE in std_logic CUP CDOWN out std_logic_vector 3 downto 0 end EX ROC architecture A of EX ROC is signal GSR std logic signal COUNT UP COUNT DOWN std logic vector 3 downto 0 component ROC port O out std logic end component begin Ul ROC port map O gt GSR UP COUNTER process CLOCK ENABLE GSR begin if GSR 1 then COUNT UP 0000 elsif CLOCK event AND CLOCK 1 then if ENABLE 1 then COUNT UP lt COUNT UP 0001 end if end if end process UP COUNTER DOWN COUNTER process CLOCK ENABLE GSR COUNT DOWN begin if GSR 1 OR COUNT DOWN 0101 then COUNT DOWN lt 1111 elsif CLOCK event AND CLOCK 1 then if ENABLE 1 then COUNT DOWN lt COUNT DOWN 0001 end if end if end process DOWN COUNTER CUP lt COUNT UP CDOWN lt COUNT DOWN end A 232 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulating VHDL Z XILINX The following figure shows the progression of the ROC model and its interpretation in the four main design phases 1 Behavioral 2 Synthesized PON OX D Q D Q CK CK E R S S ROC ROC GSR J O O Local Set 3
42. Accelerating FPGA Macros with One Hot Approach 00 000008 144 Summary of Encoding Styles enseres eemote e a eee eee ee 144 Initializing the State Machine 00 0 eee 145 Implementing Operators and Generate Modules 145 Adder and Subtractor 0 00 ccc cc ence e eare 145 Mu ltiplier d exei beeo Exe bed lan oU ee ERES EOPSd ober ewe 146 Counters tege asa hs a Aes EE ER XR a Ru RR ER ERE EAR RETE 148 Comparators peset iaa epe eben Pus Set eai ee tese Pe REA Hed 151 Encoder and Decoders 0 ccc een eee een 151 LeonardoSpectrum Priority Encoding HDL Example lees 152 Implementing Meimoty ccc cereo n I CC 269 SIRE RTS PERE nC 153 Implementing Block RAM ssssssssssse Ie 154 Instantiating Block SelectRAMTM 0 0 ccc ccc ee cece eee e nn 154 Instantiating Block SelectRAM in Virtex II II Pro II Pro X and Spartan 9 M aes ke nE EAA aa Mic pany ae id ee E RAE Sl eee a 160 Inferring Block SelectRAMIM 4 eeesiaenrtueeiee rir y bePEN a toad eiti cede 161 Implementing Distributed SelectRAM 1 0 0 eee eee 166 Implementing ROMS 2 06 cred eh RR RA He AA Fe Ee LOR HERE T RENT oe n 176 RTL Description of a Distributed ROM VHDL Example 000000005 176 RTL Description of a Distributed ROM Verilog Example sese 177 Implementing ROMs Using Block SelectRAM 00000 0000000 178 RTL Description of a ROM VHDL Examp
43. COUNT DOWN when GTS 0 else ZZZZ end A 238 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulating VHDL lt XILINX The following figure shows the progression of the TOC model and its interpretation in the four main design phases 1 Behavioral 2 Synthesized TOC Global Tri State TN A GTS User Tri State User Tri State Enable Enable Global Tri State GTS User Output i User Output den Output Buffer x Output Buffer X User Input L User Input lt Input Buffer Input Buffer 3 Implementation 4 Back Annotation TOC Global Tri State GTS Global Tri State GTS User Tri State Enable User Tri State Enable yo User Output vO User Output vO Pad Pad Output Buffer x Output Buffer X User Input L User Input L Input Buffer Input Buffer X8350 Figure 6 5 TOC Simulation and Implementation e Behavioral Phase In this phase the behavioral or RTL description of the output buffers is inferred from the coding style The TOC cell can be instantiated and connected to all tristate outputs in the design e Synthesized Phase In this phase the inferred I Os are mapped to a device and the TOC instantiation is carried from the RTL to the implementation tools This results in maintaining consistent global output tristate enable behavior between the RTL and the synthesized structural descriptions during simulation e Implemented Phase
44. Do not insert any carriage return between th lines above ee Et rv Ie E E E OE pn up 000000000 E n BUFG CLK BUFO OicLlock out I clk0 DCM DCM1 CLKFB clock with ps out CLKIN clock DSSEN low PSCLK low PSEN low PSINCDEC low RST low LKO c1k1 LK90 LK180 LK270 LK2X LK2X180 LKDV LKFX LKFX180 CKED dcm1 locked DONE TATUS EVER E IE Et dS uE o pn td Et Od 0 Y 0 Y C C 0 E n v Synthesis and Verification Design Guide www xilinx com 101 1 800 255 7778 SZ XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X 102 synthesis xc_props D jL FREQU ENCY MODE TRUE STARTUP WAIT 1 CLKFX_MULTIPLY 1 FIXED PHASE_SHIF TRUE DFS_FR 7 CL 0 Do not insert any carriage r LOW DUTY_CYCLE_CORR EQUENCY MODE LOW CLKFX_DIVID K FEEDBACK 1X CLKOUT PHASE SHIFT turn between th lines above BUFG CLK_BUF1 O clock with ps out I clkl The following synthesis tra defparam DCMO D defparam DCMO D defparam DCMO S defparam DCMO D defparam DCMO CI defparam DCMO C defparam DCMO C defparam DCMO C defparam
45. MUX OUT input A B C D input 1 0 SEL output MUX OUT reg MUX OUT always A or B or C or D or SEL begin if SEL 2 b00 UX_OUT A else if SEL 2 b01 UX_OUT B else if SEL 2 b10 UX_OUT C else if SEL 2 b11 UX_OUT D else UX_OUT 0 end endmodule 60 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Coding for Synthesis XILINX 4 to 1 Multiplexer Design with Case Construct The following VHDL and Verilog examples use a Case construct for the same multiplexer Figure 3 3 page 62 shows the implementation of these designs In these examples the Case implementation requires only one Virtex slice while the If construct requires two slices in some synthesis tools In this case design the multiplexer using the Case construct because fewer resources are used and the delay path is shorter When writing case statements make sure all outputs are defined in all branches e VHDL Example CASE EX VHD May 2001 library IEEE use IEEE std logic 1164 a11 use IEEE std logic unsigned all entity case ex is port SEL in STD LOGIC VECTOR 1 downto 0 A B C D in STD LOGIC MUX OUT out STD LOGIC end case ex architecture BEHAV of case ex is begin CASE PRO process SEL A B C D begin case SEL is when 00 gt MUX OUT when 01
46. Multi Pass Place and Route 0 eect eee e eens 41 Turns Engine Option UNIX only 6 cece cece 42 Reentrant Routing Option ssoi essei ra paa hh hh hn 42 Guide Option 4 eda bre aed dey ede NUR od ee ae as 43 Timing Simulation of Your Design 00 00 c cece eee eee 43 Timing Analysis Using TRACE ss sanese n eaae ena REE E E i E 43 Chapter 3 General HDL Coding Styles Naming and Labeling Styles otras cence eens 45 Using Xilinx Naming Conventions sssssseeeee e 45 Matching File Names to Entity and Module Names sssssesss 46 Naming Identifiers Types and Packages lsssseseesseeesese 46 Labeling Flow Control Constructs ssseesssssseees eee 46 Using Named and Positional Association 6 47 Passing Attributes oi eerEpeR E nde ead e esce see ERR eee ete be 48 VHDL Attribute Examples sese peer beh eyed eee tdeo ether meds 48 Verilog Attribute Examples 0 ccc n 49 Understanding Synthesis Tools Naming Convention 00 0c eee eee 50 Specifying Constants iioii err rr rr ER RELATA EE ER ER AE sys 51 Using Constants to Specify OPCODE Functions VHDL 000 51 Using Parameters to Specify OPCODE Functions Verilog 206 52 Choosing Data Type VHDL only isses 52 Declaring Ports is oto 8 ees ee rk Re ei eI I ET EC ae nes 53 Minimizing the Use of Ports Declared as Buffers
47. Simulating Verilog e Design Hierarchy and Simulation e RTL Simulation Using Xilinx Libraries e Timing Simulation e Debugging Timing Problems e Simulation Flows e IBIS e STAMP Increasing design size and complexity as well as recent improvements in design synthesis and simulation tools have made HDL the preferred design language of most integrated circuit designers The two leading HDL synthesis and simulation languages today are Verilog and VHDL Both of these languages have been adopted as IEEE standards The Xilinx implementation tools software is designed to be used with several HDL synthesis and simulation tools that provide a solution for programmable logic designs from beginning to end The Xilinx software provides libraries netlist readers and netlist writers along with the powerful place and route software that integrates with your HDL design environment on PC and UNIX workstation platforms Synthesis and Verification Design Guide www xilinx com 203 1 800 255 7778 Z XILINX Chapter 6 Verifying Your Design Adhering to Industry Standards The standards in the following table are supported by the Xilinx simulation flow Table 6 1 Standards Supported by Xilinx Simulation Flow Description Version VHDL Language IEEE STD 1076 1993 VITAL Modeling Standard IEEE STD 1076 4 2000 Verilog Language IEEE STD 1364 2001 Standard Delay Format SDF OVI 3 0 Std
48. architecture RTL of CLOCK TEST is component IBUFG port I in std logic O out std_logic end component 84 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Using Advanced Clock Management Z XILINX component BUFG port I in std logic O out std logic end component component CLKDLL port CLKIN in std logic CLKFB in std logic RST in std logic CLKO out std logic CLK90 out std logic CLK180 out std logic CLK270 out std logic CLKDV out std logic CLK2X out std logic LOCKED out std logic end component Clock signals signal ACLK ibufg std logic signal BCLK ibufg std logic signal ACLK 2x std logic signal ACLK 2x design std logic signal ACLK lock std logic begin ACLK ibufg inst IBUFG port map I gt ACLK O gt ACLK_ibufg BCLK ibufg inst IBUFG port map I gt BCLK O gt BCLK ibufg ACLK bufg BUFG port map I gt ACLK 2x O gt ACLK 2x design ACLK dll CLKDLL port map CLKIN gt ACLK ibufg CLKFB gt ACLK 2x design RST gt Q CLK2X gt ACLK 2x CLKO gt OPEN CLK90 gt OPEN CLK180 OPEN CLK270 OPEN CLKDV gt OPEN LOCKED gt ACLK_lock Synthesis and Verification Design Guide www xilinx com 85 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X
49. e Digital Phase Shifter DPS The DPS provides a clock shifted by a fixed or variable phase skew e Digital Frequency Synthesizer DFS The DFS produces a wide range of possible clock frequencies related to the input clock Table 4 2 CLKDLL and DCM Resources Virtex II II Pro TM Fuse MCE L PTOA p Spartan 3 CLKDLL 4 8 NA DCM N A N A 4 12 Using CLKDLL Virtex Virtex E and Spartan lI There are four CLKDLLs in each Virtex Spartan II device and eight in each Virtex E device There are also four global clock input buffers IBUFG in the Virtex E and Spartan II devices to bring external clocks in to the CLKDLL The following VHDL Verilog example shows a possible connection and usage of CLKDLL in your design Cascading three CLKDLLs in the Virtex Spartan II device is not allowed due to excessive jitter Synthesis tools do not infer CLKDLLs The following examples show how to instantiate CLKDLLs in your VHDL and Verilog code e VHDL example library IEEE use IEEE std_logic_1164 all entity CLOCK_TEST is port ACLK in std_logic off chip feedback connected to OUTBCLK on the board BCLK in std_logic OUT CLOCK OUTBCLK out std logic DI in std logic vector 1 downto 0 RESET in std logic QOUT out std logic vector 1 downto 0 CLKDLL lock signal BCLK LOCK out std logic end CLOCK TEST
50. e The Xilinx IBIS models are available for download at ftp ftp xilinx com pub swhelp ibis Synthesis and Verification Design Guide www xilinx com 279 1 800 255 7778 Z XILINX Chapter 6 Verifying Your Design STAMP The Xilinx development system supports Stamp Model Generation This feature supports the use of board level Static Timing Analysis tools such as Mentor Graphics Tau and Mentor Graphic s Blast With these tools users of Xilinx programmable logic products can accelerate board level design verification Using the stamp switch in the Xilinx program Trace writes out the stamp models For more information on creating the STAMP files options to use in Trace and integrating it with Tau and Blast please see the XAPP166 Application Note 280 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 XILINX Chapter 7 Equivalency Checking This chapter describes the basic Equivalency Checking flow using Xilinx software It includes the following sections e Introduction e Software and Device Support e Equivalency Checking Compatible Simulation Models e Setup for Synopsys Formality and Verplex Conformal FPGA e Conformal FPGA and Synplify Pro Flow e Formality and FPGA Compiler II Flow e Conformal FPGA and FPGA Compiler II Flow Introduction With rapid increases in FPGA design sizes new simulation a
51. end BEHAV e Verilog Example Changing Latch into a D Register D REGISTER V Ki module d_register CLK DATA Q input CLK input DATA output Q reg Q always 8 posedge CLK begin My D Reg Q lt DATA end endmodule Using Named and Positional Association Xilinx suggests that you always use named association to prevent incorrect connections for the ports of instantiated components Do not combine positional and named association in the same statement as illustrated in the following examples e VHDL Incorrect CLK 1 BUFGS port map I gt CLOCK_IN CLOCK_OUT Correct CLK 1 BUFGS port map I gt CLOCK_IN O gt CLOCK_OUT Synthesis and Verification Design Guide www xilinx com 47 1 800 255 7778 XILINX Chapter 3 General HDL Coding Styles e Verilog Incorrect BUFGS CLK 1 I CLOCK IN CLOCK OUT Correct BUFGS CLK 1 I CLOCK IN O CLOCK OUT Passing Attributes An attribute is attached to HDL objects in your design You can pass attributes to HDL objects in two ways you can predefine data that describes an object or directly attach an attribute to an HDL object Predefined attributes can be passed with a command file or constraints file in your synthesis tool or you can place attributes directly in your HDL code This section illustrates passing attributes in HDL code only For information on passing attributes via the command file please refer to yo
52. gt Q n int gt Q Nn UIO p IOBUF LVDS port map I gt iodata out T gt Tin int IO gt iodata p O iodata in Synthesis and Verification Design Guide www xilinx com 127 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan Il 3 Virtex E Il II Pro II Pro X UIO_n IOBUF_LVDS port map I gt iodata_n_out T gt Tin_int IO gt iodata_n O gt open UINV INV port map I gt iodata out O gt iodata n out UIBUFG IBUFG LVDS port map I gt CLK O gt CLK_ibufgout UBUFG BUFG port map I gt CLK ibufgout O gt CLK int My D Reg process CLK int DATA int begin if CLK int event and CLK int 1 then QO p int lt DATA int end if end process End My D Reg iodata out DATA int and iodata in OQ n int lt not Q p int end BEHAV e Verilog example module LVDSIOinst CLK DATA Tin IODATA p IODATA n Q p O n input CLK DATA Tin inout IODATA p IODATA n output Op On wire iodata in wire iodata n out wire iodata out wire DATA int reg OQ p int wire Q n int wire CLK int wire CLK ibufgout wire Tin int IBUF LVDS UI1 I DATA O DATA int IBUF LVDS UI2 I Tin O Tin int OBUF LVDS UO p I O0p int O O p OBUF LVDS UO n I Q n int O Q n IOBUF LVDS UIO p I iodata out T Tin int IO IODATA p O iodata in 128 www xi
53. gt RESET GTS gt GTSInput reset process process CLK RESET begin if RESET 1 then DOUT1 lt 0 elsif CLK event and CLK 1 then DOUT1 lt DINI end if end process gtsprocess process GTSInput begin if GTSInput 0 then DOUT3 lt 0 DOUT2 DIN2 else DOUT2 lt Z2 DOUT3 lt Z2 end if end process end RTL Synthesis and Verification Design Guide www xilinx com 113 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Verilog example This example uses both GTS and GSR pins Unused STARTUP pins are omitted from module declaration module setreset CLK DIN1 DIN2 RESET GTSInput DOUT1 DOUT2 DOUT3 input input input input input output output output reg DO STARTU always begin if RESET else end assign assign CLK DINI DIN2 R G ESET TSInput DOUT1 DOUT2 DOUT3 UT1 P VIRTEX startup inst GSR RESET GTS GTSInput Q8 posedge CLK or posedge RESET DOUT1 lt 1 b0 DOUT1 lt DINI DOUT3 GTSInput 1 b0 1 b0 1 b2 DOUT2 GTSInput 1 b0 DIN2 1 bZ endmodule 114 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778
54. ignored X lt C xor D D lt B overrides Y lt C xor D end process end SIG ARCH U UU C IBUF 7 BUF X gt XOR2 ee B IBUF OBUF Y X8542 Figure 3 1 Gate implementation of XOR_SIG Synthesis and Verification Design Guide www xilinx com 55 1 800 255 7778 XILINX Chapter 3 General HDL Coding Styles Using Variables VHDL XOR VAR VHD Library IEEE use IEEE std logic 1164 a11 use IEEE std logic unsigned all entity xor var is port A B C in STD LOGIC X m out STD LOGIC end xor var architecture VAR ARCH of xor var is begin VAR process A B C variable D STD LOGIC begin D A X lt C xor D D B Y lt C xor D end process end VAR ARCH T gt A bos 12 asus a gt bos gt OBUF Y X8543 Figure 3 2 Gate Implementation of XOR VAR Coding for Synthesis VHDL and Verilog are hardware description and simulation languages that were not originally intended as inputs to synthesis Therefore many hardware description and simulation constructs are not supported by synthesis tools In addition the various synthesis tools use different subsets of VHDL and Verilog VHDL and Verilog semantics are well defined for design simulation The synthesis tools must adhere to these semantics to ensure that designs simulate the same way before and after synthesis Follow the guidelines in th
55. infers up to four clock buffers for pure clock nets FPGA Compiler H does not infer a BUFG on a clock line that only drives one flip flop You can also instantiate clock buffers or assign them via the Express Constraints Editor Note Synthesis tools currently insert simple clock buffers BUFGs for all Virtex E II II Pro I Pro X and Spartan II 3 designs For Virtex II II Pro ll Pro X and Spartan 3 some tools provide an attribute to use BUFGMUX as an enabled clock buffer To use BUFGMUX as a real clock multiplexer in Virtex II II Pro Il Pro X and Spartan 3 it must be instantiated LeonardoSpectrum forces clock signals to global buffers when the resources are available The best way to control unnecessary BUFG insertions is to turn off global buffer insertion then use the BUFFER_SIG attribute to push BUFGs onto the desired signals By doing this you do not have to instantiate any BUFG components As long as you use chip options to optimize the IBUFs they are auto inserted for the input The following is a syntax example of the BUFFER SIG attribute set attribute port clkl name buffer sig value BUFG set attribute port clk2 name buffer sig value BUFG Synplify assigns a BUFG to any input signal that directly drives a clock The maximum number of global buffers is defined as 4 Auto insertion of the BUFG for internal clocks occurs with a fanout threshold of 16 loads To turn off automatic clock buffers inser
56. rst in std logic q out std logic vector 7 downto 0 end counter architecture behave of counter is signal count std logic vector 7 downto 0 begin process clk rst begin if rst 1 then count lt others gt 0 elsif rising edge clk then if ld 1 then count lt d elsif ce 1 then count lt count 1 end if end if end process q lt count end behave e Verilog example module counter d ld ce clk rst q input 7 0 d input ld ce clk rst output 7 0 q reg 7 0 count always posedge clk or posedge rst begin if rst count lt 0 else if 1d count lt d else if ce count lt count 1 end assign q count endmodule For applications that require faster counters LFSR can implement high performance and area efficient counters LFSR requires very minimal logic only an XOR or XNOR feedback For smaller counters it is also effective to use the Johnson encoded counters This type of counter does not use the carry chain but provides a fast performance Synthesis and Verification Design Guide www xilinx com 149 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X The following is an example of a sequence for a 3 bit johnson counter 000 001 011 111 110 100 e VHDL example library IEEE use IEEE STD LOGIC 1164 a11 entity johnson is
57. sigCLKFB_LF CLKO_LF std_logic signal sigLFCount std_logic_vector 3 downto 0 begin INST_IBUFGLF IBUFG port map I gt CLK_LF O gt sigCLK_LF INST BUFGLF BUFG port map I gt sigCLKO_LF O gt sigCLKFB LF INST CLKDLL CLKDLI generic map DUTY CYCLE CORRECTION gt FALSE CLKDV DIVIDE 4 0 port map CLKIN gt sigCLK LF CLKFB gt sigCLKFB LF RST RST LF CLKO gt sigCLKO_LF CLK90 gt CLK9O_LF CLK180 gt CLK180_LF CLK270 gt CLK270_LF CLK2X gt CLK2X_LF CLKDV gt CLKDV_LF LOCKED gt LOCKED_LF CLKO LF lt sigCLKO_LF procCLKDLLCount process CLKO LF begin if CLKO LF event and CLKO_LF 1 then sigLFCount lt sigLFCount 0001 end if LFCount lt sigLFCount end process end struct Note Some synthesis tools may not support the use of a generic statements See the Generics Support Considerations section for details Simulating the Virtex II II Pro Il Pro X Spartan 3 DCM The Virtex II Virtex II Pro Virtex II Pro X Spartan 3 DCM is a super set of the Virtex CLKDLL It provides more clock options including fine phase shifting and digital clock synthesis The DCM attributes like all UNISIM components are specified via generics for simulation purposes and most synthesis tools can read in the generics for passing to the implementation tools
58. string attribute IOSTANDARD of ul label is LVDS attribute IOSTANDARD of u2 label is LVDS attribute IOSTANDARD of u3 label is LVDS Synthesis and Verification Design Guide www xilinx com 129 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Pin location A5 on the cs144 package represents th positive LVDS pin Pin location D8 represents the positive LVDS pin Pin location C8 represents the negative LVDS pin attribute LOC of ul label is A5 attribute LOC of u2 label is D8 attribute LOC of u3 label is C8 signal d lvds q_lvds q lvds n std logic begin ul IBUF port map d d lvds u2 OBUF port map q_lvds q u3 OBUF port map q lvds n q n process clk begin if clk event and clk 1 then q lvds lt d_lvds end if end process q lvds n lt not q lvds end flip flop arch e Verilog example module flip flop d clk q qn 8K KK kk kk kc ko kc ko ke ko ke ko ke ke ke koe kk ke ke ke e ke e kx Pin location A5 on the Virtex E cs144 package represents th positive LVDS pin Pin location D8 represents the positive LVDS pin Pin location C8 represents the negative LVDS pin BRK RK IK Ck kk kk kk kk kk ke kc ke ko ke ke ke ke ke ke e e eG k input synthesis xc loc A5 input clk output q
59. this process is not covered in this document Please see the Conformal FPGA documentation for more information Implementing the Design and Running NetGen This section assumes that the user has prior experience with the Xilinx implementation tools For information on using the ISE GUI to implement a design please see the ISE Quick Start Tutorial For more information on the following command line programs see the Development System Reference Guide Following is an example script that shows how to run the implementation tools and how to run NetGen Note If CORE Generator components are used see the Using CORE Generator Components with Conformal RTL vs Post PAR Verification section for more information ngdbuild uc design ucf design sedif design ngd map design ngd o design map ncd par w design map ncd design ncd design map pcf netgen ecn conformal ngm design map ngm w design ncd design postpar ecn v fIf using Coregen run the following for each core in the design xilperl XILINX verilog bin sol core2formal pl verplex family core name NetGen is a new application It combines NGDANNO NGD2VHDL and NGD2VER into a single application Using the ecn conformal switch NetGen writes out a Verilog netlist that is compatible with the Conformal FPGA tool In addition to creating the Verilog netlist NetGen creates an assertion file that tells Conformal if any ports were optimized away or optimized from bi d
60. using the NetGen mhf switch to create multiple hierarchical files This helps in analyzing lower level modules individually Every netlist contains the design name ROCTOC package definition with X GTS5 GLOBAL SIGNAL signal When lower modules are simulated though X TOCBUF is connected to X GTS GLOBAL SIGNAL there will be no event on it Hence the X TOCBUF creates a pulse similar to X TOC and the GTS of the module is toggled The TOC pulse width of the X TOCBUF component can be controlled using the tpw switch for NetGen If all the modules including the top level design modules are compiled and analyzed together then the top level port created via the tp switch would drive the X GTS GLOBAL SIGNAL and all X TOCBUF cells In this situation the X TOCBUF component does not create a pulse but rather behaves like a buffer passing on the value of the X GT5 GLOBAL SIGNAL The TOC pulse width of the X TOCBUF component can be controlled using the tpw switch for NetGen Using VHDL STARTBUF VIRTEX STARTBUF VIRTEX or STARTBUF SPARTAN Block The STARTUP VIRTEX STARTUP VIRTEX2 and STARTUP SPARTAN2 blocks can be instantiated to identify the GTS signal for implementation if the global reset or tristate is connected to a chip pin However these cells cannot be simulated as there is no simulation model for them The VHDL STARTBUF VIRTEX STARTBUF VIRTEX2 and STARTBUF SPARTAN2 blocks can do a pre NGDBuild UNISIM simulation of the GTS signal
61. 3 offers more SelectlIO configuration than Virtex E and Spartan II as shown in Table 4 3 page 119 IOSTANDARD and synthesis tools specific attributes can be used to configure the SelectIO Additionally Virtex II II Pro II Pro X or Spartan 3 provides digitally controlled impedance DCT I Os which are useful in improving signal integrity and avoiding the use of external resistors This option is only available for most of the single ended I O standards To access this option you can instantiate the DCT suffixed I Os from the library such as HSTL IV DCI For low voltage differential signaling additional IBUFDS OBUFDS OBUFTDS and IOBUFDS components are available These components simplify the task of instantiating the differential signaling standard Differential Signaling in Virtex II II Pro Il Pro X or Spartan 3 Differential signaling in Virtex TII II Pro II Pro X or Spartan 3 can be configured using IBUFDS OBUFDS and OBUFTDS The IBUFDS is a two input one output buffer The OBUFDS is a one input two output buffer Refer to the Libraries Guide for the component diagram and description LVDS 25 LVDS 33 LVDSEXT 38 and LVPECL 38 are valid IOSTANDARD values to attach to differential signaling buffers If no IOSTANDARD is attached the default is LVDS 33 The following is the VHDL and Verilog example of instantiating differential signaling buffers Synthesis and Verification Design Guide www xilinx
62. 4 Provide detailed package parasitic information Package parasitics are provided in the form of lumped RLC data This is typically not a significant limitation as package parasitics have an almost negligible effect on signal transitions The implications of 2 and 3 above are that ground bounce power supply droop and simultaneous switching output SSO noise CANNOT be simulated with IBIS models To ensure that these effects do not harm the functionality of your design Xilinx provides device package dependent SSO guidelines based on extensive lab measurements The locations of these guidelines are as follows e Virtex II The Design Considerations section of the Virtex II Platform FPGA User Guide http support xilinx com publications products ug_index htm e Virtex II Pro The PCB Design Considerations section of the Virtex II Pro Platform FPGA User Guide http support xilinx com publications products ug index htm e Virtex M E Xilinx Application Note 133 Using the Virtex Select I O Resource XAPP133 Application Note e Spartan II IIE Xilinx Application Note 179 Using Select I O Interfaces in Spartan II FPGAs XAPP179 Application Note e IBIS models for Xilinx devices can be found at http support xilinx com support sw ibis htm e For more information about the IBIS specification please see the IBIS Home Page at http www eigroup org ibis ibis htm
63. 4 2 CLKDLL S IBUFG gt CLKO CLK90 CLK180 CLK270 CLK2X CLKDV LOCKED CLKDLL P CLKO CLK90 CLK180 CLK270 CLK2X CLKDV LOCKED X9240 Figure 4 2 DLL Generation of 4x Clock in Virtex E Devices Following are examples of coding a CLKDLL in both VHDL and Verilog e VHDL example library IEEE use IEEE std_logic_1164 all entity CLOCK_TEST is port ACLK in std logic DIN in std logic vector 1 downto 0 RESET in std logic QOUT out std logic vector 1 downto 0 CLKDLL lock signal BCLK LOCK out std logic end CLOCK TEST Synthesis and Verification Design Guide www xilinx com 89 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X architecture RTL of CLOCK_TEST is component IBUFG I in std logic port ou end compone component B port Lo i O ou end compone nio UFG nt component CLKDLL port CLKIN LKFB ST LKO LK90 LK180 LK270 LKDV LK2X LOCKED end compone C R C C C C C C nes in in in out out out out out out out Clock signals signal ACLK ibufg signal ACLK 2x B signal BCLK 4x design signal BCLK lockin begin ACLK ibufgi port map I gt A O gt A nst CLK BCLK bufg BUFG port map I gt B O gt B ACLK dll po
64. 800 255 7778 Placing and Routing Your Design lt XILINX from Lowest fastest run time to Highest best results with the default equal to Low Use the l switch at the command line to perform the same function Note n some cases poor placement with a lower placement level setting can result in longer route times Router Options You can limit router iterations to reduce routing times by setting the Number of Routing Passes option However this may prevent your design from meeting timing requirements or your design may not completely route From the command line you can control router passes with the i switch Use Timing Constraints During Place and Route You can improve run times by not specifying some or all timing constraints This is useful at the beginning of the design cycle during the initial evaluation of the placed and routed circuit To disable timing constraints in the Project Navigator uncheck the Use Timing Constraints check box To disable timing constraints at the command line use the switch with PAR 2 Click OK to exit the Process Properties dialog box 3 Double click Place amp Route in the Process Window of Project Navigator to begin placing and routing your design Improving Implementation Results You can select options that increase the run time but produce a better design These options generally produce a faster design at the cost of a longer run time These options are useful when
65. B els cmp lt 1 end archi Verilog example Unsigned 8 bit greater or module compar A B cmp input 7 0 A input 7 0 B output cmp assign cmp A gt B 1 bl endmodule Encoder and Decoders TOES qual comparator 17B Synthesis tools might infer MUXF5 and MUXF6 for encoder and decoder in Virtex E I I Pro II Pro X and Spartan II 3 devices Virtex II II Pro II Pro X or Spartan 3 devices feature additional components MUXF7 and MUXES to use with the encoder and decoder LeonardoSpectrum infers MUXCY when an if then else priority encoder is described in the code This results in a faster encoder Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 151 SZ XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X LeonardoSpectrum Priority Encoding HDL Example VHDL example library IEEE use IEEE std_logic_1164 all entity prior is generic size integer 8 port elk in std logio condl in std logic vector size downto 1 cond2 in std logic vector size downto 1 data in std logic vector size downto 1 q out std logic end prior architecture RTL of prior is signal data ff condl ff cond2 ff std logic vector size downto 1 begin process clk begin if clk event and clk 1 then data ff data condl1 ff lt condl cond2 ff
66. CLOCK event and CLOCK 1 then CS lt NS end if end process End REG_PROC ti COMB_PROC process CS A B C D begin case CS is when S1 gt MULTI lt 0 CONTIG lt 0 SINGLE lt 0 if A and not B and C then NS lt S2 elsif A and B and not C then NS lt S4 else NS S1 end if 136 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Encoding State Machines Z XILINX when S2 gt MULTI lt 1 CONTIG lt 0 SINGLE lt 0 if not D then NS lt S3 else NS lt S4 end if when S3 gt MULTI lt 0 CONTIG lt 1 SINGLE lt 0 if A or D then NS lt S4 else NS lt S3 end if when S4 gt MULTI lt 1 CONTIG lt 1 SINGLE lt 0 if A and B and not C then S lt S5 else NS lt S4 end if when S5 gt MULTI lt 1 CONTIG lt 0 SINGLE lt 0 NS lt S6 when S6 gt MULTI lt 0 CONTIG lt 1 SINGLE lt 1 if not E then NS lt S7 else NS lt S6 end if when S7 gt MULTI lt 0 CONTIG lt 1 SINGLE lt 0 if E then NS lt S1 else NS lt S7 end if end case end process End COMB PROC end BEHV Synthesis and Verification Design Guide www xilinx com 137 1 800 255 7778 138 Binary Encoded State Machine Veril
67. Chapter 6 Verifying Your Design e The second line gives information about the two signals that are the cause of the error This line states the following The type of violation setup hold recovery etc The above example is a setup violation The name of each signal involved in the violation followed by the simulation time at which that signal last changed values In the above example the failing signals would be the negative going edge of the signal WE which last changed at 29138 picoseconds and the positive going edge of the signal CLK which last changed at 29151 picoseconds The third value is the allotted amount of time for the setup For this example the signal on WE should be stable for 373 pico seconds before the clock transitions Since WE changed only 13 pico seconds before the clock this violation was reported e The third line gives the simulation time at which the error was reported and the instance in the structural design time sim in which the violation occurred Verilog System Timing Tasks Verilog system tasks and functions are used to perform simulation related operations such as monitoring and displaying simulation time and associated signal values at a specific time during simulation All system tasks and functions begin with a dollar sign for example setup See the Verilog Language Reference Manual available from IEEE for details about specific system tasks Timing check tasks may be in
68. DCM Hence you need to instantiate the DCM in your VHDL and Verilog designs then wou www xilinx com 1 800 255 7778 Synthesis and Verification Design Guide 95 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X To more easily set up the DCM use the Clocking Wizard See Architecture Wizard in Chapter 2 for details on the Clocking Wizard Please refer to the Design Considerations Chapter of the Virtex II Platform FPGA User Guide or the Virtex II Pro Platform FPGA User Guide respectively for information on the various features in the DCM These books can be found on the Xilinx website at http www xilinx com The following examples show how to instantiate DCM and apply a DCM attribute in VHDL and Verilog Note For more information on passing attributes in the HDL code to different synthesis vendors refer to Chapter 3 General HDL Coding Styles e VHDL example Using a DCM for Virtex II VHDL The following code passes the attribute for the synthesis tools Synplify FPGA Compiler II LeonardoSpectrum and XST library IEEE use IEEE std logic 1164 a11 entity clock block is port CLK PAD in std logic SPREAD SPECTRUM YES in std logic RST DLL in std logic CLK out out std logic LOCKED out std logic end clock block architecture STRUCT of clo
69. End SYNC PROC 142 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Encoding State Machines lt XILINX COMB_PROC process CS A B C D E begin case CS is when S1 gt MULTI lt 0 CONTIG lt 0 SINGLE lt 0 if A and not B and C then NS lt S2 elsif A and B and not C then NS lt S4 else NS S1 end if One hot Encoded State Machine Verilog Example VMIMMMBMB M MIEMLIIIIEEIP P PIPCPMMMEEMPMMP gae dl P P PM ll PL Pg P C P 049 M I IT ONE HOT V Version 1 0 Example of a one hot encoded state machine Xilinx HDL Synthesis Design Guide for FPGAs VMUIMMMBMIMMMEMLB MP MBMMETMIMBPM AHIIMIMEPMMP ATT TTT MEM module one hot CLOCK RESET A B C D E SINGLE MULTI CONTIG input CLOCK RESET input A B C D E output SINGLE ULTI CONTIG reg SINGLE ULTI CONTIG Declare the symbolic names for states parameter 6 0 S1 7 50000001 S2 7 b0000010 S3 7 p0000100 S4 7 p0001000 S5 7 p0010000 S6 7 b0100000 S7 7 b1000000 Declare current state and next state variables reg 2 0 CS reg 2 0 NS state_vector CS always posedge CLOCK or posedge RESET begin if RESET 1 b1 CS lt S1 else CS lt NS end Synthesis and Verification Design Guide www xilinx com 143 1 800 255 7
70. Guide 1 800 255 7778 Implementing Memory lt XILINX UO ram 16x1s generic map FFFF port map O gt o 0 WE gt we CLK gt clk D gt d 0 AO gt a 0 Al gt a 1 A2 gt a 2 A3 gt a 3 Ul ram_l6xls generic map ABCD port map O gt o 1 WE gt we CLK gt clk D gt d 1 AO gt a 0 Al gt a 1 A2 gt a 2 A3 gt a 3 U2 ram_l6xls generic map BCDE port map O gt o 2 WE gt we CLK gt clk D gt d 2 AO gt a 0 Al gt a 1 A2 gt a 2 A3 gt a 3 U3 ram 16x1s generic map CDEF port map O gt o 3 WE gt we CLK gt clk D gt d 3 A0 gt a 0 Al gt a 1 A2 gt a 2 A3 gt a 3 end xilinx Synplify This example shows how to create a 16x4s RAM using xilinx RAM16x1S component library IEEE use IEEE std_logic_1164 all library virtex use virtex components all library synplify use synplify attributes all entity ram_l6xls is generic init val string 0000 port O out std logic D in std logic A3 A2 Al AO in std logic WE CLK in std logic end ram 16x1s architecture xilinx of ram 16x1s is attribute xc props string attribute xc props of ul label is INIT amp init val begin U1 RAM16X1S port map O gt O WE gt WE WCLK gt CLK D gt D AO gt AO Al gt Al A2 gt A2 A3 gt A3
71. INFO MapLib No environment variables are currently set INFO MapLib 535 The following Virtex BUFG s is are being retargetted to Virtex2 BUFGMUX s with input tied to IO and Select pin tied to constant 0 BUFGP symbol clk bufgp output signal clk bufgp Section 4 Removed Logic Summary Section 5 Removed Logic Section 6 IOB Properties IOB Name Type Direction IO Standard Drive Slew Reg s Resistor IOB Strength Rate Delay bidir IOB BIDIR V i 12 SLOW OFF1 ENFF1 clk IOB INPUT V di IOB INPUT V en IOB INPUT V Section 7 RPMs Section 8 Guide Report Guide not run on this design Section 9 Area Group Summary No area groups were found in this design Section 10 Modular Design Summary Modular Design not used for this design 38 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Evaluating your Design for Coding Style and System Features Z XILINX Evaluating your Design for Coding Style and System Features At this point if you are not satisfied with your design performance you can re evaluate your code and make any necessary improvements Modifying your code and selecting different compiler options can dramatically improve device utilization and speed Tips for Improving Design Performance This section includes ways of improving design performance by modifying your cod
72. IOB TRUE constraint to be written on every flip flop in the design LeonardoSpectrum through ISE can push registers into IOBs Right click on the Synthesize process click Properties click the Architecture Options tab and enable the Map to IOB Registers setting In standalone LeonardoSpectrum you can select Map IOB Registers from the Technology tab in the GUI or set the following attribute in your TCL script set virtex map iob registers TRUE In Synplify attach the SYN USEIOFF attribute to the module or architecture of the top level in one of these ways e Add the attribute in SCOPE The constraint file syntax looks like this define global attribute syn useioff 1 e Add the attribute in the VHDL Verilog top level source code as follows VHDL example architecture rtl of test is attribute syn_useioff boolean attribute syn useioff of rtl architecture is true Verilog example module test d clk q synthesis syn_useioff 1 Using Dual Data Rate IOB Registers The following VHDL and Verilog examples show how to infer dual data rate registers for inputs only See the Using IOB Register and Latch section for an attribute to enable I O register inference in your synthesis tool The dual data rate register primitives the synchronous set reset with clock enable FDDRRSE and asynchronous set reset with clock enable FDDRCPE must be instantiated in order to utilize the dual data rate registers www xilinx com
73. Il II Pro II Pro X e LeonardoSpectrum This example shows how to create a 16x4s RAM using xilinx RAM16x1S component library IEEE use IEEE std_logic_1164 all entity ram_l6xls is generic init val string 0000 port O out std logic D in std logic A3 A2 Al AO in std logic WE CLK in std logic end ram 16x1s architecture xilinx of ram 16xl1s is attribute INIT string attribute INIT of ul label is init val component RAM16X1S is port O out std logic D in std logic WE in std logic WCLK in std logic A0 in std logic Al in std logic A2 in std logic A3 in std logic end component begin Ul RAM16X1S port map O gt O WE gt WE WCLK gt CLK D gt D A0 gt AO Al gt A1 A2 gt A2 A3 gt A3 end xilinx library IEEE use IEEE std_logic_1164 all use IEEE std_logic_unsigned all entity ram 16x4s is port o out std logic vector 3 downto 0 we in std logic Clk in std logic d in std logic vector 3 downto 0 a in std logic vector 3 downto 0 end ram 16x4s architecture xilinx of ram 16x4s is component ram 16x1s generic init val string 0000 port O out std logic D in std logic A3 A2 Al A0 in std logic WE CLK in std logic end component begin 168 www xilinx com Synthesis and Verification Design
74. L_ gt N1 gt EN EN 2 OUTI GATECLK IN2 CLK AN D3 X8628 Figure 3 6 Implementation of Gated Clock www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Coding for Synthesis XILINX e VHDL Example CLOCK ENABLE VHD library IEEE use IEEE std logic 1164 a1 use IEEE std logic unsigned all entity clock enable is port IN1 IN2 DATA CLOCK LOAD in STD LOGIC DOUT out STD LOGIC end clock enable architecture BEHAV of clock enable is signal ENABLE STD LOGIC begin ENABLE lt IN1 and IN2 and LOAD EN_PR process ENABLE DATA CLOCK begin if CLOCK event and CLOCK 1 then if ENABLE 1 then DOUT lt DATA end if end if end process End EN PR end BEHAV e Verilog Example Clock enabl xampl CLOCK ENABLE V May 2001 x module clock enable IN1 IN2 DATA CLK LOAD DOUT input IN1 IN2 DATA input CLK LOAD output DOUT wire ENABLE reg DOUT assign ENABLE IN1 amp IN2 amp LOAD always posedge CLK begin if ENABLE DOUT lt DATA end endmodule Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 73 XILINX Chapter 3 General HDL Coding Styles DATA L gt IN1 IN2 LOAD AND3 CLOCK gt
75. M M TITAS ENUM V Version 1 0 Example of an enumerated encoded state machine HMIMMLMBM lE PL P gl illl I P ll I P P PP P P M MEE TTT TST TTT lt XILINX module enum CLOCK RESET A B C D E SINGLE MULTI CONTIG input CLOCK RESET input A B C D E output SINGLE MULTI CONTIG reg SINGLE MULTI CONTIG Declare the symbolic names for states parameter 2 0 S1 3 b000 S2 3 b001 S3 3 b010 S4 3 b011 S5 3 b100 S6 3 b101 S7 3 b110 Declare current state and next state variables reg 2 0 CS reg 2 0 NS state vector CS always posedge CLOCK or posedge RESET begin if RESET 1 b1 CS lt S1 else CS lt NS end always CS or A or B or C or D or D or E begin case CS Si i begin MULTI 1 50 CONTIG 1 b0 SINGLE 1 b0 if A amp amp B amp amp C S S2 else if A amp amp B amp amp C S S4 else NS S1 end Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 141 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Using One Hot Encoding One hot encoding allows you to create state machine implementations that are more efficient for FPGA architectures One hot encoding is usually the preferred method
76. Map program double click Map 3 Toview the Map Report double click Map Report in the Process Window If the report does not currently exist it is generated at this time If a green check mark is in front of the report name the report is up to date and no processing is performed If the desired report is not up to date you can click the report name and then select Process ReRun to update the report before you view it The auto make process automatically runs only the necessary processes to update the report before displaying it Or you can select Process Rerun All to re run all processes even those processes that are currently up to date from the top of the design to the stage where the report would be 4 View the Logic Level Timing Report with the Report Browser This report shows the performance of your design based on logic levels and best case routing delays 5 Atthis point you may want to start the Timing Analyzer to create a more specific report of design paths 6 Usethe Logic Level Timing Report and any reports generated with the Timing Analyzer or the Map program to evaluate how close you are to your performance and utilization goals Use these reports to decide whether to proceed to the place and route phase of implementation or to go back and modify your design or implementation options to attain your performance goals You should have some slack in routing delays to allow the place and route tools to successfully
77. NGDBuild pre map gate level functional simulation is used when it is not possible to simulate the direct output of the synthesis tool This occurs when the tool cannot write UNISIM compatible VHDL or Verilog netlists In this case the NGD file produced from NGDBUILD is the input into the Xilinx simulation netlister NetGen NetGen creates a structural simulation netlist based on SIMPRIM models Like post synthesis simulation pre NGDBuild simulation allows you to verify that your design has been synthesized correctly and you can begin to identify any differences due to the lower level of abstraction Unlike the post synthesis pre NGDBuild simulation there are GSR and GTS nets that must be initialized just as for post Map and post PAR simulation Please refer to the Understanding the Global Reset and Tristate for Simulation section for details on using the GSR and GTS signals for post NGDBuild simulation Post Map Partial Timing CLB and IOB Block Delays 208 You may also perform simulation after mapping the design Post Map simulation occurs before placing and routing This simulation includes the block delays for the design but not the routing delays This is generally a good metric to test whether the design is meeting the timing requirements before additional time is spent running the design through a complete place and route As with the post NGDBuild simulation NetGen is used to create the structural simulation netlist based
78. OUT 1 D DATA_BUS 1 A3 ADDR 3 A2 ADDR 2 Al ADDR 1 AO ADDR 0 WE WE WCLK CLK exemplar attribute RAM1 INIT AAAA RAM16X1S RAMO O DATA OUT 0 D DATA BUS 0 A3 ADDR 3 A2 ADDR 2 Al ADDR 1 AO ADDR 0 WE WE WCLK CLK Synthesis and Verification Design Guide www xilinx com 171 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X exemplar attribute RAMO INIT 0101 endmodule module RAM16X1S O D A3 A2 Al AO WE WCLK output O input D input A3 input A2 input Al input A0 input WE input WCLK endmodule e Synplify M This example shows how to create a 16x4 RAM using Xilinx RAM16X1S component include virtex v module RAM INIT EX1 DATA BUS ADDR WE CLK input 3 0 ADDR inout 3 0 DATA BUS input WE CLK wire 3 0 DATA OUT Only for Simulation the defparam will not synthesize Use the defparam for RTL simulation There is no defparam needed for Post P amp R simulation synthesis translate off defparam RAMO INIT 0101 RAMI INIT AAAA RAM2 INIT FFFF RAM3 INIT 5555 synthesis translate_on assign DATA BUS WE DATA OUT 4 hz Instantiation of 4 16X1 Synchronous RAMs Use the xc props attribute to pass the INIT pro
79. On Configuration ROC Cell 0 6 eee eee ee eee 231 Using VHDL ROCBUP Cell 5 pr m tee ent od SR ede cp ee ecole angi d 234 Using VHDL STARTBUF VIRTEX STARTBUF VIRTEX2 Block or the STARTBUF SPARTAN2 Bloe c arte detect be E EE aint Meee EEE A E leat ane a a Mean ee nen ok EA 236 Emulating the Global GTS pulse in a VHDL Functional Simulation 237 Using VHDL Tristate On Configuration TOC 6 6 eee cee eee 237 Using VHDL TOCBUP iicesesere acces ced oed ed Eae kdo db RR a on n 240 Using VHDL STARTBUF VIRTEX STARTBUF VIRTEX2 or STARTBUF SPARTAN2 Block E E S EE E E 242 STARTBUF_VIRTEX Model Example o an annuun nnna nran cee eee eee 243 Simulating Special Components in VHDL n sasssa srra nee eee 244 14 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 lt XILINX Simulating CORE Generator Components in VHDL 00 000 eee eee 244 Boundary Scan and Readback sas eerie eenei eee teens 244 Generics Support Considerations 6 6 ccc cee eens 244 Differential I O LVDS LVPECL 6 0 0 cece Rh 245 Simulating a LUT ceris ei eiecr bid es teneri e eed vede Pied wee Lee 245 Simulating Virtex Block SelectRAM 2 0 0 c ccc eee eens 246 Simulating the Virtex Clock DLL 00 cece II 248 Simulating the Virtex II II Pro II Pro X Spartan 3 DCM 00000 249 Simulating SRLS trpis tesi sistas ove ee ea E eee ae ee rd ce tk 252 Simulating Ve
80. Phase In this phase the inferred output buffers are mapped to a device and the TOCBUF instantiation is carried from the RTL to the implementation tools This maintains consistent global output tristate enable behavior between the RTL and the synthesized structural descriptions during simulation www xilinx com 1 800 255 7778 241 XILINX Chapter 6 Verifying Your Design e Implemented Phase In this phase the TOCBUF is removed from the logical description and the global resources are used for this function e Back annotated Phase In this phase use the NetGen option gp to replace the port that was previously occupied by the TOCBUF in the RTL description of the design A non hierarchical netlist will have this port drive the fully wired GTS signal For hierarchical designs the GTS net is not wired across hierarchical modules The VHDL global signal X_GTS_GLOBAL_SIGNAL is used to connect the top level port created by the tp switch to the GTS signals of the hierarchical modules Each hierarchical module contains an XTROCBUF cell which is driven by X GIS GLOBAL SIGNAL The output of the X TOCBUF is connected to the GTS signal of the hierarchical module Toggling the input to the top level port affects the entire design The X GTS GLOBAL SIGNAL global signal is defined in a package within the VHDL netlist The package name is design name ROCTOC If desired each of the hierarchical modules can be written out as a separate netlist
81. RIG e ex RI E CURIE E EE 188 Design Hierarchy eee cine rere eI eek R Cerea Re eg 189 Using Synthesis Tools with Hierarchical Designs sessiles 189 Restrict Shared Resources to Same Hierarchy Level lleeeeeeeeees 189 Compile Multiple Instances Together lessen 189 Restrict Related Combinatorial Logic to Same Hierarchy Level sss 189 Separate Speed Critical Paths from Non critical Paths 189 Restrict Combinatorial Logic that Drives a Register to Same Hierarchy Level 190 Restrict Mod le SIz 1 4 ke e ri eie roe de teas eee Dee rra oed arab aaa 190 Register All O tpults aene e tr ped ee Poo ac ced ce dece s 190 Restrict One Clock to Each Module or to Entire Design lesse 190 Chapter 5 Virtex ll Pro Considerations Introduction s ccc cece e he 191 Using SmartModels to Simulate Virtex II Pro Designs 191 Simulation Components eese hh exque kae ek ER RT ERR arbre 192 Overview of Virtex II Pro Simulation Flow ueseeeess 192 SmartModels nete eC ERA CER eda s er a ee P qe doces ds 193 Supported SuntUilatDES ees rtt Eee dr e Rob do erede ci dea n et d 193 LutoNM v C 193 WV ATA OW SB ces esc PHP rP C M 193 Required Software cic d exer eek a V oe eu ao E T LAT HER OCIO REESE 194 Solaris coe cete bb obi enbicacdxernirietseeddesdeSieu Rib eere dues 194 WiInd
82. Synthesis Verification section for more information Example script for verifying RTL to post synthesis set hdlin_ignore_full_case false set hdlin_ignore_parallel_case false set hdlin_error_on_mismatch_message false set verification_set_undriven_signals 0 Read Golden RTL design The core2formal_output v file below is an optional file that is only needed if a Coregen component is used in the design There will be a file for each core in the design read verilog container r libname WORK vcs y SXILINX verilog formality unisims y SXILINX verilog formality simprims libext v core2formal output v rtl filel rtl file2 290 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Formality and FPGA Compiler IIT Flow XILINX set_top module_name_of_top_level Read Post NGDBuild design read verilog container i libname WORK vcs y SXILINX verilog formality simprims libext v output from netgen v set top module name of top level source output of makeconstraints fms Add additional Formality constraints here verify Save the script file as script name fms Running the Script in Formality Follow these steps to run the verification 1 Ensure that the Xilinx and Formality environment variables are properly set up See Setup for Synopsys Formality and Verplex Conformal FPGA for details 2 Invoke the Formality shell fm shell 3 Source
83. These design examples show you how to take a design that has been previously encoded for example binary encoded and synthesize it to the appropriate decoding logic and registers These designs use three flip flops to implement seven states E State3 State7 D 7 E State4 State6 4 Multi Contig Figure 4 4 State Machine Bubble Diagram Contig Single X6102 Synthesis and Verification Design Guide www xilinx com 135 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan Il 3 Virtex E Il II Pro II Pro X Binary Encoded State Machine VHDL Example The following is a binary encoded state machine VHDL example BINARY VHD Version 1 0 a Example of a binary encoded state machine mE Library IEEE use IEEE std logic 1164 a11 use IEEE std logic unsigned all entity binary is port CLOCK RESE in STD_LOGIC A B C D E in BOOLEAN SINGLE ULTI CONTIG out STD_LOGIC i end binary architecture BEHV of binary is type STATE TYPE is S1 S2 S3 S4 S5 S6 S7 attribute ENUM ENCODING STRING attribute ENUM ENCODING of STATE TYPE type is 001 010 O11 100 101 110 111 signal CS NS STATE TYPE begin SYNC PROC process CLOCK RESET begin if RESET 1 then GS lt Sl elsif
84. an IBUF BUFG connection This is done by instantiating BUFG after disabling global buffer insertion www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Using Global Clock Buffers lt XILINX Instantiating Buffers Driven from Internal Logic Some synthesis tools require you to instantiate a global buffer in your code to use the dedicated routing resource if a high fanout signal is sourced from internal flip flops or logic such as a clock divider or multiplexed clock or if a clock is driven from a non dedicated I O pin If using Virtex E or Spartan II devices the following VHDL and Verilog examples instantiate a BUFG for an internal multiplexed clock circuit Note Synplify infers a global buffer for a signal that has 16 or greater fanouts e VHDL example CLOCK MUX BUFG VHD Version 1 1 This is an example of an instantiation of global buffer BUFG from an internally a driven signal a multiplexed clock library IEEE use IEEE std_logic_1164 all entity clock_mux is port DATA SEL in STD LOGIC SLOW CLOCK FAST CLOCK in STD LOGIC DOUT out STD LOGIC end clock mux architecture XILINX of clock mux is signal CLOCK STD LOGIC signal CLOCK GBUF STD LOGIC component BUFG port I in STD LOGIC O out STD LOGIC end component begin Clock MUX process SEL FAST CLOCK SLOW CLOCK begin if SEL 1 the
85. cet RO ert ERE hea Eee Geese dae eee rerea 75 Instantiating Components isssesssssssssss rnr rnnr rrrrrrr rreren 76 Instantiating FPGA Primitiv S e deiis e pE E E E eens 76 Instantiating CORE Generator Modules 0 6 666 c cece eens 77 Using Boundary Scan JTAG 1149 1 78 Using Global Clock Buffers 0 0 0000s 78 Inserting Clock Buffers erenn kme aapa een nnn ees 79 Instantiating Global Clock Buffers 2 0 0 6 eens 80 Instantiating Buffers Driven froma Port lessen 80 Instantiating Buffers Driven from Internal Logic 000 cee eee ee eee 81 Using Advanced Clock Management uuu 83 Using CLKDLL Virtex Virtex E and Spartan IITM 00000 84 Using the Additional CLKDLL in Virtex E 00 00 87 Using BUPGDLL ca tcccexiv i srties erinit EERE a a RET EE PEE erts 92 CLKDLEL Attributes sie bs ie devi ae RB e ev be EEET FEN RE PSSEFYRE vetoes 93 Using DCM In Virtex I II Pro II Pro X and Spartan 37M uuuuuuuuuu 95 Attaching Multiple Attributes to CLKDLL and DCM 0004 98 Using Dedicated Global Set Reset Resource 0 000 e eee 112 Startup State eestis cient ccd REA T rex PSP EP NU phu Reo keer 112 Preset vs Clearance pale etnies RE R EL ERAR REEERE RERE Rd 116 Implementing Inputs and Outputs 0 0 118 VO Standard Seat reeset eee arta tes cet tss eon eve tad ac sie ee e ete ec e Sav
86. complete your design Use the Synthesis and Verification Design Guide www xilinx com 35 1 800 255 7778 XILINX 36 Chapter 2 Understanding High Density Design Flow verbose option in the Timing Analyzer to see block by block delay The timing report of a mapped design before place and route shows block delays as well as minimum routing delays Note A typical Virtex E II II Pro Il Pro X design should allow 40 of the delay for logic and 60 of the delay for routing If most of your time is taken by logic then most likely the design will not meet timing after place and route Using the Command Line to Map Your Design 1 Translate your design as follows ngdbuild p target device design name edf Map your design as follows map design name ngd Use a text editor to view the Device Summary section of the design name mrp Map Report This section contains the device utilization information Run a timing analysis of the logic level delays from your mapped design as follows trce options design name ncd Note For available options enter only the trce command at the command line without any arguments Use the Trace reports to evaluate how close you are to your performance goals Use the report to decide whether to proceed to the place and route phase of implementation or to go back and modify your design or implementation options to attain your performance goals You should have some slack in routing delays
87. connected to an active signal the state of that signal controls the startup state of the flip flop For example if you connect an active signal to the Preset pin the flip flop starts up in the preset state If you do not connect the Clear or Preset pin the default startup state is a clear state To change the default to preset assign an INIT 1 to the Virtex E II II Pro II Pro X or Spartan IT 3 flip flop I O flip flops and latches in Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X and Spartan TII 3 have an SR pin which can be configured as a synchronous Set a synchronous Reset an asynchronous Preset or an asynchronous Clear The SR pin can be driven by any user logic but INIT also works for these flip flops Following are examples of setting register INIT using ROCBUF In the HDL code the instantiated ROCBUF connects the set reset signal The Xilinx tools automatically remove the ROCBUF during implementation leaving the set reset signal active only during power up 116 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Using Dedicated Global Set Reset Resource Z XILINX e VHDL example library IEEE use IEEE std logic 1164 all entity d register is port CLK in std logic RESET in std logic DO in std logic D1 in std logic Q0 out std logic Ol out std logico end d register architecture XILINX of d register is signal RESET int std logic comp
88. described in this section From Project Navigator 1 Create or open an existing project for Project Navigator 2 Inthe Sources in Project window highlight the target device 3 Inthe Processes for Source window under the Design Entry Utilities toolbox right click Compile HDL Simulation Libraries and select Properties to open the Process Properties dialog box 2 xl B E watch sc E readme stmach v dia Cf xev50 6bg256 B stopwatch stopwatch sch stopwatch tb stopwatch tb tbw B cnt amp 0 cntE0 sch iy decode behavioral decode vhd iy hex2led hex2led arch hex2led vhd Eg outs3 outs3 sch iv stmach_v behavior stmach_v vhd 285 tenths tenths xco wa Snapshot View wu ID Library View E Add Existing Source E Create New Source E d Design Entry Utilities E Update All Schematic Files BE Module View OO View Compilation Log E Regenerate All Cores HDL Converter Wi Process View 214 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Compiling Xilinx Simulation Libraries COMPXLIB XILINX 4 Choose one or more of the following options from the Process Properties dialog box Simulation Library Compiler Properties Property Name Note Project Navigator will only show the options that apply to your specific design flow For example if you have created a Virtex II project it will only show yo
89. example library IEEE use IEEE std logic 1164 all entity LVDSIO is port CLK DATA Tin in STD LOGIC IODATA p IODATA n inout STD LOGIC Qp On out STD LOGIC end LVDSIO architecture BEHAV of LVDSIO is component IBUF LVDS is port I in STD LOGIC O out STD LOGIC end component 126 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Inputs and Outputs Z XILINX component OBUF_LVDS is port I in STD_LOGIC O out STD LOGIC end component component IOBUF LVDS is port I in STD LOGIC T in STD LOGIC IO inout STD LOGIC O out STD LOGIC end component component INV is port I in STD LOGIC O out STD LOGIC end component component IBUFG LVDS is port I in STD LOGIC O out STD LOGIC end component component BUFG is port I in STD LOGIC O out STD LOGIC end component signal iodata in std logic signal iodata n out std logic signal iodata out std logic signal DATA int std logic signal Q p int std logic signal Q n int std logic signal CLK int std logic signal CLK ibufgout std logic signal Tin int std logic begin UI1 IBUF LVDS port map I DATA O gt DATA int UI2 IBUF LVDS port map I gt Tin O gt Tin int UO p OBUF LVDS port map I gt Qp int O gt Q p n i Oo r UO OBUF_LVDS port map
90. for correct simulation and implementation Here is an example of the variables set 200 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Running Simulation lt XILINX setenv XILINX Xilinx_path setenv LM_LICENSE_FILE verilogxl_license dat LM_LICENSE_FILE setenv CDS_INST_DIR Cadence_path setenv LD_LIBRARY_PATH S V2PRO source sim_models Xilinx verilog smartmodel sol installed lib sun4Solaris lib LD_LIBRARY_PATH setenv LMC CDS VCONFIG CDS INST DIR tools sun4v verilog bin vconfig setenv LM LICENSE FILE license dat LM LICENSE FILE setenv PATH LMC_HOME bin S CDS INST DIR tools bin PATH setenv PATH S XILINX bin sol PATH Note The user is responsible for changing the parameters in italics to match the systems configuration The LD_LIBRARY_PATH variable must be pointing to the SmartModel installation directory Simulate An example Verilog XL compilation simulation script Illustrates which files need to be compiled and loaded for simulation This file can be modified to simulate a design by including the design and test bench files appropriately Cadence NC Verilog Solaris Running Simulation In the XILINX verilog smartmodel sol simulation ncverilog directory there are several files to help set up and run a simulation utilizing the SWIFT interface e Setup Description of variables
91. for details Simulating Virtex Block SelectRAM By default the Virtex Block SelectRAM comes up initialized to zero in all data locations starting at time zero If you want to initialize the RAM or ROM contents to anything other than zero you can do this by applying the appropriate INIT_xx generics in the VHDL code The following is an example of using generic mapping to apply an initial value to a Block SelectRAM This code was written with the assumption that the synthesis tool can understand and pass the INIT attribute using the generic notation 246 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulating VHDL Z XILINX LIBRARY ieee use IEEE std_logic_1164 all Library UNISIM use UNISIM vcomponents all entity ex_blkram is port CLK EN RST WE in std_logic ADDR in std_logic_vector 9 downto 0 DI in std_logic_vector 3 downto 0 DORAMBA S4 out std_logic_vector 3 downto 0 end architecture struct of ex blkram is component RAMBA S4 generic INIT 00 INIT O1 INIT 02 bit vector INIT 03 INIT 04 INIT 05 bit vector INIT 06 INIT 07 INIT 08 bit vector INIT 09 INIT OA INIT OB bit vector INIT OC INIT OD INIT O0 bit vector E INIT OF bit vector port DI in STD LOGIC VECTOR 3 downto 0 EN in STD ULOGIC WE in STD ULOGIC RST in STD ULOGIC CLK in
92. ieee std logic unsigned all entity ram examplel is generic data width integer 8 address width integer 8 mem depth integer 256 port data in std logic vector data width 1 downto 0 address in std logic vector address width 1 downto 0 we clk in std logic q out std logic vector data width 1 downto 0 end ram examplel architecture rtl of ram examplel is type mem array is array mem depth 1 downto 0 of std logic vector data width 1 downto 0 Signal mem mem array attribute syn ramstyle string attribute syn ramstyle of mem signal is block ram signal raddress std logic vector address width 1 downto 0 begin 10 process clk begin if clk 1 and clk event then raddress address if we 1 then mem CONV INTEGER address data end if end if end process q lt mem CONV INTEGER raddress end rtl Synthesis and Verification Design Guide www xilinx com 163 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X e VHDL example for Synplify 7 0 In Synplify 7 0 the same conditions exist as with the previous release except that there is a new coding style for Block Select RAM inference in VHDL The following is a Synplify 7 0 VHDL example library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity ram_exampl
93. in one Virtex I TI Pro II Pro X or Spartan 3 CLB up to a 128 bit shift register can be implemented effectively using SRLC16 Synthesis tools Synplify 7 1 LeonardoSpectrum 2002a and XST can infer the SRLC16 For more information please refer to the Virtex II Platform FPGA User Guide Dynamic Length Mode can be implemented using SRL16 or SRLC16 Each time a new address is applied to the 4 input address pins the new bit position value is available on the Q output after the time delay to access the LUT LeonardoSpectrum Synplify and XST can infer a shift register component A coding example for a dynamic SRL is included following the SRL16 inference example Synthesis and Verification Design Guide www xilinx com 181 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Inferring SRL16 in VHDL e FPGA Compiler II LeonardoSpectrum Synplify and XST VHDL example design of SRL16 inference for Virtex This design infer 16 SRL16 with 16 pipeline delay library ieee use ieee std logic 1164 al l use ieee std logic arith all use ieee std logic unsigned all entity pipeline delay is generic cycle integer 16 width integer 16 i port input in std logic vector width 1 downto 0 clk in std logic output out std logic vector width 1 downto 0 nd pipeline delay architecture behav of pipelin
94. it for arithmetic functions that are part of your design s time critical path Since resource sharing allows you to reduce the number of design resources the device area required for your design is also decreased The area that is used for a shared resource depends on the type and bit width of the shared operation You should create a shared resource to accommodate the largest bit width and to perform all operations Synthesis and Verification Design Guide www xilinx com 65 1 800 255 7778 XILINX Chapter 3 General HDL Coding Styles If you use resource sharing in your designs you may want to use multiplexers to transfer values from different sources to a common resource input In designs that have shared operations with the same output target the number of multiplexers is reduced as illustrated in the following VHDL and Verilog examples The HDL example is shown implemented with gates in Figure 3 4 D 7 0 Q 7 0 Z1 7 0 Z1 5 7 0 UN1 C1 7 0 UN1 D1 7 0 X9462 Figure 3 4 Implementation of Resource Sharing e VHDL Example RES SHARING VHD library IEEE use IEEE std logic 1164 a1l use IEEE std logic unsigned all use IEEE std logic arith all entity res sharing is port Al B1 C1 D1 in STD LOGIC VECTOR 7 downto 0 COND 1 in STD LOGIC Zl out STD LOGIC VECTOR 7 downto 0 end res sharing architecture BEHAV of res shari
95. lesser device utilization and decreased design performance e Design file revision control becomes more difficult e Designs become more verbose Most of the disadvantages listed above can be overcome with careful design consideration when choosing the design hierarchy Using Synthesis Tools with Hierarchical Designs By effectively partitioning your designs you can significantly reduce compile time and improve synthesis results Here are some recommendations for partitioning your designs Restrict Shared Resources to Same Hierarchy Level Resources that can be shared should be on the same level of hierarchy If these resources are not on the same level of hierarchy the synthesis tool cannot determine if these resources should be shared Compile Multiple Instances Together You may want to compile multiple occurrences of the same instance together to reduce the gate count However to increase design speed do not compile a module in a critical path with other instances Restrict Related Combinatorial Logic to Same Hierarchy Level Keep related combinatorial logic in the same hierarchical level to allow the synthesis tool to optimize an entire critical path in a single operation Boolean optimization does not operate across hierarchical boundaries Therefore if a critical path is partitioned across boundaries logic optimization is restricted In addition constraining modules is difficult if combinatorial logic is not restricted to the
96. logic vector 7 downto 0 end srltest architecture rtl of srltest is type dataAryType is array 3 downto 0 of std logic vector 7 downto 0 signal regBank dataAryType begin outData lt regBank outStage process clk inData begin if clk event and clk 1 then if en 1 then regBank lt regBank 2 downto 0 amp inData end if end if end process end rtl Inferring Dynamic SRL16 in Verilog e LeonardoSpectrum Synplify and XST module test srl clk enable dataIn result addr input clk enable input 3 0 dataIn input 3 0 addr output 3 0 result reg 3 0 regBank 15 0 integer i Synthesis and Verification Design Guide www xilinx com 183 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X always posedge clk begin if enable 1 begin for i 15 i 0 i i 1 begin regBank i lt regBank i 1 end regBank 0 lt dataIn end end assign result regBank addr endmodule Implementing LFSR The SRL Shift Register LUT implements very efficient shift registers and can be used to implement Linear Feedback Shift Registers See the XAPP210 Application Note for a description of the implementation of Linear Feedback Shift Registers LFSR using the Virtex SRL macro One half of a CLB can be configured to implement a 15 bit LFSR one CLB can implement a 52 bit LFSR and with two CLBs a
97. of a 5 to 1 multiplexer built with gates Typically the gate version of this multiplexer has binary encoded selector inputs and requires three select inputs SEL lt 2 0 gt The schematic representation of this design is shown in Figure 4 5 page 186 Some synthesis tools include commands that allow you to switch between multiplexers with gates or with tristates Check with your synthesis vendor for more information The VHDL and Verilog designs provided at the end of this section show a 5 to 1 multiplexer built with tristate buffers The tristate buffer version of this multiplexer has 184 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Multiplexers Z XILINX one hot encoded selector inputs and requires five select inputs SEL lt 4 0 gt The schematic representation of these designs is shown in Figure 4 6 page 187 Mux Implemented with Gates VHDL Example The following example shows a MUX implemented with Gates MUX GATE VHD 5 to 1 Mux Implemented in Gates library IEEE use IEEE std logic 1164 a11 use IEEE std logic arith all entity mux gate is port SEL in STD LOGIC VECTOR 2 downto 0 A B C D E in STD LOGIC SIG out STD LOGIC end mux gate architecture RTL of mux gate is begin SEL PROCESS process SEL A B C D E begin case SEL is when 000 gt SIG lt when 001 gt SIG when 010 gt SIG lt whe
98. on SIMPRIM models When you run the simulation netlister tool NetGen an SDF file is created The delays for the design are stored in the SDF file which contains all block or logic delays However it does not contain any of the routing delays for the design since the design has not yet been www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulation Points Z XILINX placed and routed As with all Netgen created netlists GSR and GTS signals must be accounted for Please refer to the Understanding the Global Reset and Tristate for Simulation section for details on using the GSR and GTS signals for post NGDBuild simulation Timing Simulation Post Place and Route Full Timing Block and Net Delays After your design has completed the place and route process in the Xilinx Implementation Tools a timing simulation netlist can be created It is not until this stage of design implementation that you start to see how your design behaves in the actual circuit The overall functionality of the design was defined in the beginning stages but it is not until the design has been placed and routed that all of the timing information of the design can be accurately calculated The previous simulations that used NetGen created a structural netlist based on SIMPRIM models However this netlist comes from the placed and routed NCD file This netlist has GSR and GTS nets that must be initialized For more information on initia
99. place and route verification in Formality Note See the Using CORE Generator Components with Formality RTL vs Post PAR Verification section for more information Example script for verifying RTL to post synthesis set hdlin_ignore_full_case false set hdlin_ignore_parallel_case false set hdlin_error_on_mismatch_message false set verification_set_undriven_signals 0 Read Golden RTL design The core2formal_output v file below is an optional file that is only needed if a Coregen component is used in the design There will be a file for each core in the design read verilog container r libname WORK vcs y SXILINX verilog formality unisims y SXILINX verilog formality simprims libext v core2formal output v rtl filel rtl fale set top module name of top level fRead Post PAR design read verilog container i libname WORK vcs y SXILINX verilog formality simprims libext v output from netgen v set top module name of top level source output of makeconstraints fms source design ecn svf output assertion file from netgen Add additional Formality constraints here verify Save the script file as script name fms Running the Script in Formality Follow these steps to run the verification 1 Ensure that the Xilinx and Formality environment variables are properly set up See Setup for Synopsys Formality and Verplex Conformal FPGA for details 2 Invoke
100. process and select Properties You can choose the following options from this window Process Properties 2050 I III I a Simulation Model Properties NUR Property Name Vale Simulation Model T arget Post Place amp RouteSimulaion Model Name j Rename Top Level Entity to eee Rename Top Level Architecture To s Structure Change Device Speed To 5 a e aa Correlate Simulation Data to Input Design M Retain Hierarchy GlobalSet ResetPotName Z Reset On Configuration Pulse Width Generate TestbenchFie lt lt E Rename Design Instance in Testbench File to Global Disable of X generation for Simulation Generate Architecture Only No Entry Declaration d Other NETGEN Command Line Options 0 Se Note Project Navigator only shows the options that apply to your specific design flow i e if you have created a Verilog project it only shows you options for creating a Verilog netlist Simulation Model Target The Simulation Model Target property allows you to select the target simulator for the simulation netlist All supported simulators are listed as well as a generic VHDL or Verilog netlist for other simulators Post Place amp Route Simulation Model Name The Post Translate Simulation Model Name property allows you to designate a name for the generated simulation netlist This only affects the fi
101. same level of hierarchy Separate Speed Critical Paths from Non critical Paths To achieve satisfactory synthesis results locate design modules with different functions at different levels of the hierarchy Design speed is the first priority of optimization Synthesis and Verification Design Guide www xilinx com 189 1 800 255 7778 190 XILINX Chapter 4 Architecture Specific Coding Styles for Spartan Il 3 Virtex E Il II Pro II Pro X algorithms To achieve a design that efficiently utilizes device area remove timing constraints from design modules Restrict Combinatorial Logic that Drives a Register to Same Hierarchy Level To reduce the number of CLBs used restrict combinatorial logic that drives a register to the same hierarchical block Restrict Module Size Restrict module size to 100 200 CLBs This range varies based on your computer configuration the time required to complete each optimization run if the design is worked on by a design team and the target FPGA routing resources Although smaller blocks give you more control you may not always obtain the most efficient design For the final compilation of your design you may want to compile fully from the top down Check with your synthesis vendor for guidelines Register All Outputs Arrange your design hierarchy so that registers drive the module output in each hierarchical block Registering outputs makes your design easier to constrain because you on
102. statement to define module bus widths e Example 1 Using parameters for OPCODE functions parameter ZERO 2 b00 parameter A AND B 2 b01 parameter A OR B 2 b10 parameter ONE 2 b11 always OPCODE or A or B begin if OPCODE ZERO OP OUT 1 b0 else if OPCODE A AND B OP OUT AS amp B else if OPCODE A OR B OP OUT A B else OP OUT 1 b 1 end e Example 2 Using a parameter for Bus Size parameter BUS_SIZE 8 output BUS_SIZE 1 0 OUT input BUS_SIZE 1 0 X Y Choosing Data Type VHDL only Use the Std_logic IEEE 1164 standards for hardware descriptions when coding your design These standards are recommended for the following reasons the states found in Applies as a wide range of state values 1t has nine different values that represent most of digital circuits 52 wwWwW xilinx com 1 800 255 7778 Synthesis and Verification Design Guide Choosing Data Type VHDL only lt XILINX e Automatically initializes to an unknown value Automatic initialization is important for HDL designs because it forces you to initialize your design to a known state which is similar to what is required in a schematic design Do not override this feature by initializing signals and variables to a known value when they are declared because the result may be a gate level circuit that cannot be initialized to a known value e Easily performs b
103. that was specified during simulation is greater than that specified in the timing constraints then this over clocking of the design could cause timing violations For example if your simulation clock has a frequency of 5 ns and you have a PERIOD constraint set at 10 ns a timing violation could occur This situation can also be complicated by the presence of DLL or DCM in the clock path Generally this problem is caused by an error either in the test bench or in the constraint specification Check to ensure that the constraints match the conditions in the test bench and correct any inconsistencies If you modify the constraints be sure to re run the design through place and route to ensure that all constraints are met Unaccounted Clock Skew Clock skew is the difference between the amount of time the clock signal takes to reach the destination register and the amount of time the clock signal takes to reach the source register The data must reach the destination register within a single clock period plus or minus the amount of clock skew Clock skew is generally not a problem when you use global buffers however clock skew can be a concern if you use the local routing network for your clock signals To find out if clock skew is your problem use TRACE to do a setup test See the TRACE chapter of the Development Systems Reference Guide for directions on how to run a setup check and read the TRACE report You can also use Timing Analyzer to d
104. the xilinx verilog smartmodel sol simulation mtiverilog directory there are several files to help set up and run a simulation utilizing the SWIFT interface e modelsim ini An example modelsim ini file used to set up ModelSim for SWIFT interface support This file contains the changes outlined above Xilinx suggests that you make the changes to the modelsim ini file located in the SMODEL TECH directory because of the library mappings included in this file e Setup A script used to set the user environment for simulation and implementation Here is an example of the variables set setenv XILINX Xilinx path setenv MODEL TECH MTI path setenv LM LICENSE FILE modelsim license dat LM LICENSE FILE setenv LMC HOME XILINX verilog smartmodel sol image setenv PATH S LMC HOME bin LMC HOME lib pont lib MODEL in sol PATH rH ECH bin XILINX b Note The user is responsible for changing the parameters in italics to match the systems configuration e Simulate An example ModelSim simulation script Illustrates which files need to be compiled and loaded for simulation This file can be modified to simulate a design by including the design and test bench files appropriately If the user s modelsim ini file is being used which contains the system mappings the vmap commands can be commented out or deleted from this file
105. the Formality shell fm shell 3 Source the script file Ssource script name fms 4 If any verification errors occur start the GUI and debug the errors start gui Using CORE Generator Components with Formality RTL vs Post PAR Verification When using CORE Generator components the contents of the cores are read in during NGDBuild the first stage of the Xilinx implementation process The cores are then Synthesis and Verification Design Guide www xilinx com 293 1 800 255 7778 XILINX Chapter 7 Equivalency Checking implemented with the rest of the design and the post PAR netlist will contain the contents of the cores The RTL design only contains black box instantiations of the cores Xilinx provides a Perl script core2 formal p1 that creates Verilog representations of the cores which can be read in as part of the reference design Usage gt xilperl XILINX verilog bin platform core2formal pl vendor family coregen_module For Formality the vendor option must be formality e The family option can be virtex virtexe virtex2 virtex2p and spartan2 spartan2e or spartan3 e The Perl script runs the following commands ngdbuild p family coregen_module edn netgen ecn formality coregen module ngd coregen module for v The output from NetGen is a Verilog representation of the core that is read in with the RTL design as part of the golden reference design You must run the core2 ormal pl s
106. the RTL code occurs during synthesis The synthesis tool optimizes the code and converts it from RTL to a post synthesis netlist Performing an equivalence check between the RTL and post synthesis netlist verifies that the functionality of the design has not been changed by the transformation or by the optimization done by the synthesis tool Note In addition to the documentation provided in this guide please see Formal Verification Flow for Xilinx Devices Using the Synplify Pro Software and the Conformal_ LEC Tool at the Symplicity website at http www synplicity com literature pdf formal verification final pdf Perform the following steps to verify that the golden RTL and the post synthesis netlist from Synplify Pro are logically equivalent 1 Turn on verification mode in Synplify Pro 2 Run the DO file fpgaR2G do created by Verplex in Conformal FPGA 3 Ifthe two netlists are not equivalent use Conformal FPGA to debug the differences The debug process is not covered in this document Please see the Conformal FPGA documentation for more information on using Conformal Turning on Verification Mode Do one of the following to turn on Verification Mode in Synplify Pro e Command line set_option verification_mode 1 e GUI Imp Options Device Mapping Option Verification Mode www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Conformal FPGA and Synplify Pro Flow lt XILINX A
107. the Xilinx Verilog libraries Depending on the makeup of the design Xilinx instantiated primitives or CORE Generator components for RTL simulation edit the hd1 var and cds 1ib files to specify the library mapping Synthesis and Verification Design Guide www xilinx com 275 1 800 255 7778 XILINX Chapter 6 Verifying Your Design cds lib DEFINE simprims_ver compiled_lib_dir simprims_ver DEFINE xilinxcorelib_ver compiled_lib_dir xilinxcorelib_ver DEFINE worklib worklib hdl var DEFINE VIEW_MAP SVIEW_MAP v gt v DEFINE LIB MAP SLIB_MAP compiled_lib_dir unisims_ver gt unisims ver DEFINE LIB MAP SLIB MAP compiled lib dir simprims ver gt simprims ver DEFINE LIB MAP S LIB MAP gt worklib After setting up the libraries now compile and simulate the design ncvlog messages update SXILINX verilog src glbl v testfixture v design v ncelab messages testfixture name glbl ncsim messages testfixture name The update option of Ncvlog enables incremental compilation For timing or post NGDBuild simulation use the SIMPRIM based libraries Specify the following at the command line ncvlog messages update S XILINX verilog src glbl v testfixture v time sim v ncelab messages autosdf testfixture name glbl ncsim messages testfixture name For more information on how to back annotate the SDF file for timing si
108. the other signals In this case A1 is the fastest signal followed by A2 and A3 A4 is the slowest signal Most synthesis tools can balance or restructure the arithmetic operator tree if timing constraints require it However Xilinx recommends that you code your design for your selected structure Comparing If Statement and Case Statement 58 The If statement generally produces priority encoded logic and the Case statement generally creates balanced logic An If statement can contain a set of different expressions while a Case statement is evaluated against a common controlling expression In general use the Case statement for complex decoding and use the If statement for speed critical paths Most current synthesis tools can determine if the if elsif conditions are mutually exclusive and will not create extra logic to build the priority tree The following are points to consider when writing if statements e Make sure that all outputs are defined in all branches of an if statement If not it can create latches or long equations on the CE signal A good way to prevent this is to have default values for all outputs before the if statements e Limiting the number of input signals into an if statement can reduce the number of logic levels If there are a large number of input signals see if some of them can be pre decoded and registered before the if statement e Avoid bringing the dataflow into a complex if statement Only control sig
109. timing simulation the clocks may not appear to be de skewed within the range specified This is due to the way the delays in the SDF file are handled by some simulators The SDF file annotates the CLOCK PORT delay on the X_FF components However some simulators may show the clock signal in the waveform viewer before taking this delay into account If it appears that the simulator is not properly de skewing the clock consult your simulator s documentation to find out if it is not displaying the input port delays in the waveform viewer at the input nodes If this is the case then when the CLOCK PORT delay on the X_FF is added to the internal clock signal it should line up within the device specifications in the waveform viewer with the input port clock The simulation is still functioning properly the waveform viewer is just not displaying the signal at the expected node To verify that the CLKDLL DCM is functioning correctly delays from the SDF file may need to be accounted for manually to calculate the actual skew between the input and internal clocks Simulating the DLL DCM Although the functionality of the Xilinx DLL and DCM components may seem easy to understand the simulation of these components can be easily misinterpreted The purpose of this section is to clarify how the DLL DCM is supposed to simulate and to identify some of the common problems designers face when simulating these components TRACE Simulation Model Differences
110. to transmit one data bit it is handled differently from any other I O standards A UCF or an NGC file with complete pin LOC information must be created to ensure that the I O banking rules are not violated If a UCF or NGC file is not used PAR issues errors The input buffer of these two I O standards may be placed in a wide number of IOB locations The exact locations are dependent on the package that is used The Virtex E package information lists the possible locations as IO_L P for the P side and IO_L N for the N side where is the pair number Only one input buffer is required to be instantiated in the design and placed on the correct IO_L P location The N side of the buffer is reserved and no other IOB is allowed on this location The output buffer may be placed in a wide number of IOB locations The exact locations are dependent on the package that is used The Virtex E package information lists the possible locations as IO_L P for the P side and IO_L N for the N side where is the pair number However both output buffers are required to be instantiated in the design and placed on the correct IO_L P and IO_L N locations In addition the output O pins must be inverted with respect to each other one HIGH and one LOW Failure to follow these rules leads to DRC errors in the software The following examples show VHDL and Verilog coding for LVDS I O standards targeting a VS0ECS144 device An AUCF example is also provided e VHDL
111. vsim L simprims ver testfixture glbl The incr option enables incremental compilation The L compiled lib dir option provides VSIM with a library to search for design units instantiated from Verilog 278 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 IBIS lt XILINX IBIS The Xilinx IBIS models provide information on I O characteristics The IBIS models can be used for the following IBIS models provide information about I O driver and receiver characteristics without disclosing proprietary knowledge of the IC design as unencrypted SPICE models do However there are some limitations on the information that IBIS models can provide Please note that these are limitations imposed by the IBIS specification itself IBIS models can be used for the following 1 Model best case and worst case conditions best case strong transistors low temperature high voltage worst case weak transistors high temperature low voltage Best case conditions are represented by the fast strong model while worst case conditions are represented by the slow weak model Typical behavior is represented by the typical model 2 Model varying drive strength and slew rate conditions for Xilinx I Os that support such variation IBIS cannot be used for any of the following 1 Provide internal timing information propagation delays and skew 2 Model power and ground structures 3 Model pin to pin coupling
112. whose inputs A3 A2 A1 A0 determine the length of the shift register The shift register may be of a fixed static length or it may be dynamically adjusted The shift register LUT contents are initialized by assigning a four digit hexadecimal number to an INIT attribute The first or the left most hexadecimal digit is the most significant bit If an INIT value is not specified it defaults to a value of four zeros 0000 so that the shift register LUT is cleared during configuration The data D is loaded into the first bit of the shift register during the Low to High clock CLK transition During subsequent Low to High clock transitions data is shifted to the next highest bit position as new data is loaded The data appears on the Q output when the shift register length determined by the address inputs is reached The Static Length Mode of SRL16 implements any shift register length from 1 to 16 bits in one LUT Shift register length is N 1 where N is the input address Synthesis tools implement longer shift registers with multiple SRL16 and additional combinatorial logic for multiplexing In Virtex IT II Pro II Pro X or Spartan 3 devices additional cascading shift register LUTs SRLC16 are available SRLC16 supports synchronous shift out output of the last 16th bit This output has a dedicated connection to the input of the next SRLC16 inside the CLB With four slices and dedicated multiplexers MUXF5 MUXF6 and so forth available
113. 0 VITAL standard for simulation acceleration This VITAL 2000 is in turn based on the IEEE STD 1076 93 VHDL language Because of this the Xilinx libraries must be compiled as 1076 93 VITAL libraries include some additional processing for timing checks and back annotation styles The UNISIM library turns these timing checks off for unit delay functional simulation The SIMPRIM back annotation library keeps these checks on by default to allow accurate timing simulations 204 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulation Points XILINX Simulation Points Xilinx supports functional and timing simulation of HDL designs at five points in the HDL design flow Figure 6 1 shows the points of the design flow All five points are described in the following section 1 Register Transfer Level RTL simulation which may include the following RTL Code Instantiated UNISIM library components XilinxCoreLib and UNISIM gate level models CORE Generator SmartModels 2 Post synthesis functional simulation which may include one of the following optional Gate level netlist containing UNISIM library components written by the synthesis tool XilinxCoreLib and UNISIM gate level models CORE Generator SmartModels 3 Post NGDBUILD Simulation optional Gate level netlist containing SIMPRIM library components SmartModels 4 Post Map with partial back annotated timing without
114. 00000000000000000000 port DI in STD_LOGIC_VECTOR 7 downto 0 EN in STD_ULOGIC WE in STD_ULOGIC RST in STD_ULOGIC C A LK in STD_ULOGIC DDR in STD_LOGIC_VECTOR 8 downto 0 DO out STD_LOGIC_VECTOR 7 downto 0 end component begin INST RAMBA S4 RAMBA S4 generic map INIT 00 gt IF1EI1D1C1B1A191817161514131211100F0E0D0C0B0A0980706050403020100 port map DI gt DI 3 downto 0 EN gt E WE gt WE RST gt RST CLK gt CLK ADDR gt ADDR 9 downto 0 DO gt DORAMB4_S4 INST RAMBA S8 RAMBA S8 generic map INIT 00 gt I1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A0980706050403020100 port map DI gt DI 7 downto 0 EN gt E WE gt WE RST gt RST CLK gt CLK ADDR gt ADDR 8 downto 0 DO gt DORAMBA S8 end struct Synplify With Synplify you can instantiate the RAMB cells by using the Xilinx family library supplied with Synplify The following code example illustrates instantiation of a RAMB cell library IEEE use IEEE std_logic_1164 all library virtex use virtex components all library synplify use synplify attributes all Synthesis and Verification Design Guide www xilinx com 157 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan
115. 1 FAST_CLOC S SEL K K always 8 posedge CLOCK GBUF DOUT lt DATA endmodule Using Advanced Clock Management Virtex E and Spartan II devices feature Clock Delay Locked Loop CLKDLL for advanced clock management The CLKDLL can eliminate skew between the clock input pad and internal clock input pins throughout the device CLKDLL also provides four quadrature phases of the source clock With CLKDLL you can eliminate clock distribution delay double the clock or divide the clock The CLKDLL also operates as a clock mirror By driving the output from a DLL off chip and then back on again the CLKDLL can be used to de skew a board level clock among multiple Virtex Virtex E and Spartan II devices For detailed information on using CLKDLLs refer to the Libraries Guide and the XAPP132 and XAPP174 Application Notes Synthesis and Verification Design Guide www xilinx com 83 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X In Virtex II II Pro II Pro X or Spartan 3 devices the Digital Clock Manager DCM is available for advanced clock management The DCM contains the following four main features For more information on the functionality of these features refer to the Libraries Guide and the Virtex II Platform FPGA User Guide e Delay Locked Loop DLL The DLL feature is very similar to CLKDLL
116. 1 downto 0 end CLOCK TEST architecture RTL of CLOCK TEST is component IBUFG port I im std logre O out std logic end component component BUFG port I Xm std logico O out std logic end component Synthesis and Verification Design Guide www xilinx com 93 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X component CLKDLL port CLKIN in std logic CLKFB in std logic RST in std logic CLKO out std logic CLK90 out std logic CLK180 out std logic CLK270 out std logic CLKDV out std logic CLK2X out std logic LOCKED out std logic end component Clock signals signal ACLK ibufg std logic signal div 2 div 2 design std logic signal ACLK0 ACLKObufg std logic signal logic O0 std logic attribute CLKDV DIVIDE attribute CLKDV DIVID string of ACLK dll label is 2 E El logic 0 lt 0 begin ACLK ibufginst IBUFG port map I gt ACLK O gt ACLK ibufg i ACLK_bufg BUFG port map I gt ACLKO O gt ACLKObufg i DIV_bufg BUFG port map I gt div_2 O gt div 2 design ACLK dll CLKDLL port map CLKIN gt ACLK ibufg CLKFB gt ACLKObufg RST gt logic O0 CLK2X OPEN CLKO gt ACLKO CLK90 gt OPEN CLK180 gt OPEN CLK270 gt OPEN CLKDV gt div_2 LOCKED gt OPE i
117. 10 ROM WORD 1100 ROM WORD 1001 ROM WORD 1001 ROM WORD 1101 ROM WORD 1011 ROM WORD 1111 begin DATA lt ROM ADDR Read from the ROM end XILINX www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Memory RTL Description of a Distributed ROM Verilog Example Note LeonardoSpectrum does not infer ROM lt XILINX Use the following coding example for FPGA Compiler II Synplify and XST ROM RTL V Behavioral El Example of 16x4 ROM module rom rtl ADDR DATA input 3 0 ADDR output 3 0 DATA reg 3 0 DATA A memory is implemented using a case statement always Q8 ADDR begin case ADDR 4 p0000 4 50001 4 50010 4 50011 4 50100 4 50101 4 50110 4 50111 1000 1001 1010 1011 1100 1101 1110 4 p1111 endcase end endmodule 4 4 4 4 4 4 4 0 5 0 0 0 0 9 DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT o oM oS oM oS ll JS G4 GR dS uS uS aS aS aus Oooo PPP Pp op op mpg 4 p0000 4 p0001 4 p0010 4 p0100 4 bl 4 bl 1100 1010 1001 1001 1010 1100 1001 1001 1101 r111 000 000 With the VHDL and Verilog examples above synthesis tools create ROMs using function generators LUTs and MUXFs or the ROM primitives Another method for implementing ROMs i
118. 118 bit LFSR is implemented Implementing Multiplexers A 4 to 1 multiplexer can be efficiently implemented in a single Virtex M E TI II Pro II Pro X and Spartan II 3 family slice The six input signals four inputs two select lines use a combination of two LUTs and MUXF5 available in every slice Up to 9 input functions can be implemented with this configuration In the Virtex E and Spartan II families larger multiplexers can be implemented using two adjacent slices in one CLB with its dedicated MUXF5s and a MUXF6 Virtex IT TI Pro II Pro X and Spartan 3 slices contain dedicated two input multiplexers one MUXF5 and one MUXFX per slice MUXFS is used to combine two LUTs MUXFX can be used as MUXF6 MUXF7 and MUXTS to combine 4 8 and 16 LUTs respectively Please refer to the Virtex II Platform FPGA User Guide for more information on designing large multiplexers in Virtex IT II Pro II Pro X or Spartan 3 This book can be found on the Xilinx website at http www xilinx com In addition you can use internal tristate buffers BUFIs to implement large multiplexers Large multiplexers built with BUFTs have the following advantages e Can vary in width with only minimal impact on area and delay e Can have as many inputs as there are tristate buffers per horizontal longline in the target device e Have one hot encoded selector inputs This last point is illustrated in the following VHDL and Verilog designs
119. 2 This is an example of an instantiation of a multiplexing global buffer BUFGMUX E from an internally driven signal library IEEE use IEEE std_logic_1164 all entity clock_mux is port DATA SEL in std logic SLOW CLOCK FAST CLOCK in std logic DOUT out std logic end clock mux architecture XILINX of clock mux is signal CLOCK GBUF std logic component BUFGMUX port IO in std logic Il t Xn std logre S in std logic O out std logic end component 82 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Using Advanced Clock Management Z XILINX begin GBUF_FOR_MUX_CLOCK BUFGMUX port map I0 gt SLOW CLOCK Il gt FAST CLOCK S gt SEL O gt CLOCK GBUF Data Path process CLOCK GBUF begin if CLOCK GBUF event and CLOCK GBUF 1 then DOUT lt DATA end if end process end XILINX e Verilog example TILER TTTTIATIAT TAT TAIT TET AEE Te CLOCK_MUX_BUFG V Version 1 2 This is an example of an instantiation of a multiplexing global buffer BUFGMUX from an internally driven signal HMUMUMLMBg MM lC LT I P MM IP Pg MU P TTT TTT module clock mux DATA SEL SLOW CLOCK FAST CLOCK DOUT input DATA SEL SLOW_CLOCK FAST_CLOCK output DOUT reg CLOCK DOUT wire CLOCK_GBUF BUFGMUX GBUF_FOR_MUX_CLOCK O CLOCK GBUF I0 SLOW CLOC 1
120. 2 n Tin p Tin n output ODATA p ODATA n output Op O n wire datain2 wire odata in wire odata out wire DATA int reg Q int wire CLK int wire CLK ibufgout wire Tin int IBUFDS UI1 I DATA p IB DATA n O DATA int i IBUFDS UI2 I Tin p IB Tin n O Tin int IBUFDS UI3 I DATAIN2 p IB DATAIN2 n O datain2 OBUFDS UO1 I Q int O QO p OB Q_n OBUFTDS UO2 I odata out T Tin int O ODATA p OB ODATA n IBUFGDS UIBUFG I CLK p IB CLK n O CLK ibufgout BUFG UBUFG I CLK ibufgout O CLK int always 8 posedge CLK int begin Q int lt DATA int end assign odata out DATA int amp amp datain2 endmodule Encoding State Machines The traditional methods used to generate state machine logic result in highly encoded states State machines with highly encoded state variables typically have a minimum number of flip flops and wide combinatorial functions These characteristics are acceptable for PAL and gate array architectures However because FPGAs have many flip flops and narrow function generators highly encoded state variables can result in inefficient implementation in terms of speed and density One hot encoding allows you to create state machine implementations that are more efficient for FPGA architectures You can create state machines with one flip flop per state and decreased width of combinatorial logic One hot encoding is
121. 364 95 It was not originally intended as an input to synthesis and many Verilog constructs are not supported by synthesis software The www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Designing FPGAs with HDLs XILINX Verilog examples in this manual were tested and synthesized with current commonly used FPGA synthesis software The coding strategies presented in the remaining chapters of this manual can help you create HDL descriptions that can be synthesized Using VHDL VHSIC Hardware Description Language VHDL is a hardware description language for designing Integrated Circuits ICs It was not originally intended as an input to synthesis and many VHDL constructs are not supported by synthesis software However the high level of abstraction of VHDL makes it easy to describe the system level components and testbenches that are not synthesized In addition the various synthesis tools use different subsets of the VHDL language The examples in this manual will work with most commonly used FPGA synthesis software The coding strategies presented in the remaining chapters of this manual can help you create HDL descriptions that can be synthesized Comparing ASICs and FPGAs Xilinx FPGAs are reprogrammable and when combined with an HDL design flow can greatly reduce the design and verification cycle seen with traditional ASICs Using Synthesis Tools Most of the commonly used FPGA synthesis tools have spec
122. 4 all use synplify attributes all entity test padtype is port a in std logic vector 3 downto 0 b in std logic vector 3 downto 0 Clk rst en in std logic bidir inout std logic vector 3 downto 0 q out std logic vector 3 downto 0 attribute xc padtype of a signal is IBUF SSTL3 I attribute xc padtype of bidir signal is IOBUF HSTL III attribute xc padtype of q signal is OBUF S 8 end entity e Verilog example module test padtype a b clk rst en bidir q input 3 0 a synthesis xc padtype IBUF AGP input 3 0 b input clk rst en inout 3 0 bidir synthesis xc padtype IOBUF CTT output 3 0 q synthesis xc padtype OBUF F 12 Note Refer to IBUF_selectlO in the Libraries Guide for a list of available IBUF_selectlO values Virtex E TI II Pro II Pro X and Spartan II 3 outputs can also be configured to any of I O standards listed in the I O standards section An OBUF that uses the LVTTL LVCMOS15 LVCMOS18 LVCMOS25 or LVCMOS33 signaling standards has selectable drive and slew rates using the DRIVE and SLOW or FAST constraints The defaults are DRIVE 12 mA and SLOW slew In addition you can control the slew rate and drive power for LVTTL outputs using OBUF slew drivepower Refer to OBUF selectIO in the Libraries Guide for a list of available OBUF selectIO values You can use the examples in the Inputs section to configure OBUF to an I O standard Using IOB Regi
123. 55 7778 Table of Contents Preface About This Guide Guide Contents uu eese e beeen e Additional Resources sese Re eeneens Conventlons v dauern erxerReunbraea how bie Palade ete be es Typographical setes cree rece eee e e Er ee Ueber eek aaa prs Online Document ereen sessen tr oet ete Re does Ca n e db Soda oe dg eet Chapter 1 Introduction Axchitecture Support iue cepe Co er ehm bd Obi aded e Ra ep tae s Overview of Hardware Description Languages 00 0005 Advantages of Using HDLs to Design FPGAs 00 0 005 Designing FPGAs with HDS igna xr eder Im eb RR CR e b a Using Verilog cce dete REPCEeH Re EC ne e eee eed de ee bbb e dei Using VEDI qaos ac ncn be bedienen rcl ei oda Comparing ASICs and FPGAS 6 66 6 ences Using Synthesis TOONS ic cce re netos een Ie n eene ptr R eee eon p Re et de Using FPGA System Features 6 66 cece ne Designing Hierarchy isco cid enering eee red sans aphid eet Specifying Speed Requirements 6 6 6 cece nee Xilinx Internet Websites vos 2 cin onsen EXE due DOC a CE GR eee ACE QURE ades Xilinx World Wide Web Site liiis Technical Support Websit serere rereensreiteseie sesi snemiene e Technical and Applications Support Hotlines nasa 0 0 cece cece eee KAO FTP SiE RETE Vendor Support S68 621 Led tes e od RR Aas ctp e ORE qe eek Chapter 2 Understanding High Density Design Flow
124. 6 00 1 2 Accumulated miscellaneous updates and bug fixes 08 28 00 13 Fine tuning of text frame and paragraph format spacings 04 11 01 2 0 Revised formats to take advantage of FrameMaker 6 0 book features 05 02 01 2 1 Master page changes 07 11 01 2 2 Accumulated miscellaneous updates and bug fixes 04 04 02 2 21 Updated trademarks page in ug000_title fm 06 24 02 3 0 Initial Xilinx release of corporate wide common template set used for User Guides Tutorials Release Notes Manuals and other lengthy multiple chapter documents created by both CMP and ITP See related documents for further information Descriptions for revisions prior to v3 0 have been abbreviated For a full summary of revision changes prior to v3 0 refer to v2 21 template set 06 06 03 4 0 Name changed from Synthesis and Simulation Design Guide to Synthesis and Verification Design guide Added new chapter for Equivalency Checking Accumulated miscellaneous updates and bug fixes www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 XILINX Preface About This Guide This manual provides a general overview of designing Field Programmable Gate Arrays FPGAs with Hardware Description Languages HDLs It includes design hints for the novice HDL user as well as for the experienced user who is designing FPGAs for the first ti
125. 778 XILINX Chapter 4 Architecture Specific Coding Styles for Spartan Il 3 Virtex E Il II Pro Il Pro X always CS or A or B or C or D or D or E begin case CS Si begin MULTI 1 50 CONTIG 1 b0 SINGLE 1 b0 if A amp amp B amp amp C S S2 else if A amp amp B amp amp C S S4 else S Sl end Accelerating FPGA Macros with One Hot Approach Most synthesis tools provide a setting for finite state machine FSM encoding This setting prompts synthesis tools to automatically extract state machines in your design and perform special optimizations to achieve better performance The default option for FSM encoding is One Hot for most synthesis tools However this setting can be changed to other encoding such as binary gray sequential etc In FPGA Compiler II FSM encoding is set to One Hot by default To change this setting select Synthesis Options Project Tab Available options are One Hot Binary and Zero One Hot In LeonardoSpectrum FSM encoding is set to Auto by default which differs depending on the Bit Width of your state machine To change this setting to a specific value select the Input tab Available options are Binary One Hot Random Gray and Auto In Synplify the Symbolic FSM Complier option can be accessed from the main GUI When set the FSM Compiler extracts the state machines as symbolic graphs and then optimizes them
126. 778 Synthesis and Verification Design Guide Using Advanced Clock Management lt XILINX attribute DLL_FREQUENCY_MODE string attribute DUTY_CYCLE_CORRECTION string attribute STARTUP_WAIT string attribute DFS FREQUENCY MODE string attribute CLKFX DIVIDE string attribute CLKFX MULTIPLY string attribute CLK FEEDBACK string attribute CLKOUT PHASE SHIFT string attribute PHASE SHIFT string attribute DLL FREQUENCY MODE of dcm0 label is LOW attribute DUTY CYCLE CORRECTION of dcmO0 label is TRUE attribute STARTUP WAIT of dcm0 label is TRUE attribute DFS FREQUENCY MODE of dcm0 label is LOW attribute CLKFX DIVIDE of dcm0 label is 1 attribute CLKFX MULTIPLY of dcmO0 label is 1 attribute CLK FEEDBACK of dcm0 label is 1X attribute CLKOUT PHASE SHIFT of dcm0 label is NONE attribute PHASE SHIFT of dcmO label is 0 attribute DLL FREQUENCY MODE of dcml label is LOW attribute DUTY CYCLE CORRECTION of dcml label is TRUE attribute STARTUP WAIT of dcml label is TRUE attribute DFS FREQUENCY MODE of dcml label is LOW attribute CLKFX DIVIDE of dcml1 label is 1 attribute CLKFX MULTIPLY of dcml label is 1 attribute CLK FEEDBACK of dcml label is 1X attribute CLKOU
127. 8 mem depth integer 256 port data in std logic vector data width 1 downto 0 address in unsigned address width 1 downto 0 we clk in std logic q out std logic vector data width 1 downto 0 end ram examplel architecture ex1 of ram examplel is type mem type is array mem depth 1 downto 0 of std logic vector data width 1 downto 0 Signal mem mem type signal raddress unsigned address width 1 downto 0 Synthesis and Verification Design Guide www xilinx com 161 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan Il 3 Virtex E Il II Pro II Pro X begin 10 process clk we address begin if clk 1 and clk event then raddress lt address if we 1 then mem to integer raddress lt data end if end if end process ll process clk address begin if clk 1 and clk event then q lt mem to integer address end if end process end ex1 e LeonardoSpectrum VHDL example dual port Block SelectRAM library ieee use ieee std logic 1164 a11 use ieee std logic unsigned all entity dualport ram is port clka in std logic clkb in std logic wea in std logic addra in std logic vector 4 downto 0 addrb in std logic vector 4 downto 0 dia in std logic vector 3 downto 0 dob out std logic vector 3 downto 0 end dualport ram architecture dualport ram arch of dualport ram i
128. 94 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Using Advanced Clock Management lt XILINX RESET process div_2_design begin if RES QOUT ET 71 then lt 00 elsif div 2 design event and div 2 design 1 QOUT end if end process END RTL lt DIN Verilog example module clock_test ACLK DIN QOUT input ACLK input RESET input 220 output 1 0 QOUT reg 1 0 QOUT IBUFG CLK ibufg A I ACLK O ACLK ibu i BUFG div_CLK_bufg I div 2 O div 2 design BUFG clk0 bufg CLKDLL ACLK div 2 CLKIN ACLK ibufg CLKFB clk bufg ST 1 b0 LK2X LKO c1k0 K90 LK180 LK270 LKDV div 2 OCKED RE DIN Fg I clk0 div by 2 aqaaaaawn E sL i exemplar attribute ACLK_div_2 C synopsys attribute CLKDV_DIVID synthesis attribute CLKDV_DIVI LKDV_DIVI WD dE always posedge div_2_design or posedge RE begin if RE QOUT else QOUT end endmodule SET lt 2 p00 lt DIN O clk bufg DE of ACLK D div 2 is SET Using DCM In Virtex II II Pro Il Pro X and Spartan 3 Use the DCM in your Virtex II Virtex II Pro Virtex II Pro X or Spartan 3 design to improve routing between clock pads and global buffers Most synthesis tools currently do not automatically infer the
129. ACLK ibufg BUFG BCLK bufg I BCLK 4x O BCLK 4x design CLKDLL ACLK dll 2x 2x clock CLKIN ACLK ibufg CLKFB ACLK 2x ST 1 b0 K2X ACLK 2x LKO LK90 LK180 1 LK270 CLKDV LOCKED R C C SC C C C then Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 91 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan Il 3 Virtex E Il II Pro II Pro X CLKDLL BCLK dll 4x 4x clock CLKIN ACLK 2x KFB BCLK 4x design BCLK 4x after bufg ST 1 b0 K2X BCLK Ax LKO LK90 LK180 LK270 LKDV LOCKED BCLK_LOCK always posedge BCLK 4x design or posedge RESET begin if RESET QOUT 1 0 lt 2 000 else if BCLK LOCK QOUT 1 0 lt DIN 1 0 Q aaaaanaWw end endmodule Using BUFGDLL BUFGDLL macro is the simplest way to ensure zero propagation delay for a high fanout on chip clock from the external input This macro uses the IBUFG CLKDLL and BUFG primitive to implement the most basic DLL application as shown in Figure 4 3 IBUFG BUFG CLKDLL CLKIN CLKO CLK90 ES CLK180 CLK270 CLK2X CLKDV RST LOCKED X9222 Figure 4 3 BUFGDLL Schematic In FPGA Compiler II use the Constraints Editor to change the global buffer insertion to BUFGDLL 92 www xilinx com Synthesis and Ve
130. ARTBUF_VIRTEX2 Block or the STARTBUF SPARTAN Block The STARTUP VIRTEX STARTUP VIRTEX2 and STARTUP_SPARTAN2 blocks can be instantiated to identify the GSR signals for implementation if the global reset or tristate is connected to a chip pin However these cells cannot be simulated as there is no simulation model for them Table 6 5 Virtex E and Spartan lI STARTBUF STARTUP Pins Virtex E Spartan II V STARTBUF Connection STARTUP STARTUP Pin Names Points Pin Names Pin Names GSRIN Global GSR GSR Set Reset Port of Design GTSIN Global GTS GTS Tristate Port of Design CLKIN Port or CLK CLK Internal Logic www xilinx com 1 800 255 7778 Synthesis and Verification Design Guide Simulating VHDL lt XILINX Table 6 5 Virtex E and Spartan lI STARTBUF STARTUP Pins Virtex E Spartan II STARTBUF Connection STARTUP STARTUP Pin Names Points Pin Names Pin Names GTSOUT AllOutput N A N A Buffers Tristate Control GSROUT All N A N A Registers Asynchron ous set reset Xilinx recommends that you use the local routing for Virtex devices as opposed to using the dedicated GSR If the design resources are available this method gives better performance and more predictable design behavior If you do not plan to bring the GSR pin out to a device pin but want to have access to it for simulation Xilinx suggests that you use the ROC or ROCBUF
131. C CLKDLL BCLK dll OUT off chip synchronization CLKIN ACLK ibufg CLKFB BCLK ibufg BCLK and OUTBCLK is connected outside the chip RST 1 b0 oi CLKO CLK90 CLK180 CLK270 CLKDV LOCKED BCLK_LOCK always posedge ACLK 2x design or posedge RE begin if RESET QOUT 1 0 lt 2 b00 else if ACLK_lock QOUT 1 0 lt DIN 1 0 end endmodule Using the Additional CLKDLL in Virtex E LK2X OUTBCLK connected to BCLK outside There are eight CLKDLLs in each Virtex E device with four located at the top and four at the bottom as shown in Figure 4 1 The basic operations of the DLLs in the Virtex ETM devices remain the same as in the Virtex and Spartan II devices but the connections may have changed for some configurations Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 87 SZ XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Bottom Right Half Edge X9239 Figure 4 1 DLLs in Virtex E Devices 88 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Using Advanced Clock Management Z XILINX Two DLLs located in the same half edge top left top right bottom right bottom left can be connected together without using a BUFG between the CLKDLLs to generate a 4x clock as shown in Figure
132. COMPXLIB help type the following on the command line compxlib help Library Support COMPXLIB supports the compilation of the following Xilinx HDL Simulation Libraries UNISIM Functional Uni9000 Timing SIMPRIM Timing XilinxCoreLib Functional SmartModel Library Functional amp Timing CoolRunner Functional Abel Functional Device Family Support COMPXLIB supports the compilation of libraries for all Xilinx Device Families Simulator Support COMPXLIB supports the compilation of Xilinx HDL Simulation Libraries for the following simulators 216 ModelSim SE all Xilinx supported platforms ModelSim PE all Xilinx supported platforms NCSIM all Xilinx supported platforms www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Compiling Xilinx Simulation Libraries COMPXLIB XILINX VCS only on Solaris and Linux based platforms VCSi only on Solaris and Linux based platforms Scirocco only on Solaris and Linux based platforms Note The VHDL SIMPRIM library in this release is VITAL2000 compliant Ensure that your simulator is also VITAL2000 compliant to successfully compile the SIMPRIM library Note f using ModelSim XE device library compilation is not necessary as the libraries are pre compiled and installed with the software For updates for the ModelSim xXE library please consult the Xilinx support website at http support xil
133. D sir BIOW cs ecuxre rin on n ao od ade CIO AGE HUE HUE CLR Ced GO a ee ie Entering your Design and Selecting Hierarchy uuuuuuusuuuuuuuse Design Entry Recommendations sss e Using KEb COde ieu err m ache epe enm od todos e E APRI tpa heed Gat ds Carefully Select Design Hierarchy eese Architecture Wizard dew IER A bens ey She Sees ov Y a pr e re Aes Clocking Wizard c cernere cer E COCHE EE Ea E eei ME CR Ed RocketlOM Wizard 23 2e teege cbe E do ERU EEG cine RAE RE HO CORE Generato Miurirrcir i urr dor ERE X RES cae eee ECHTE ER ERR Functional Simulation of your Design ouuluuuusssssssesseeeesee Synthesizing and Optimizing your Design uus Creating an Initialization File nananana nnn Creating a Compile Run Script 0 066 a ccc nee FPGA Compiler UM 14 e due depths a Vad a Aa uk BAG eR E wade denn EeonardoSpe ctrum M isses isses ee or reed te lee ch le Rb IRURE CA AUR RU e n drin dk Synplify M essien dh epe ENG eie Pelr GL be Rey REPE bees Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 XILINX Compiling Your Design sekreiesyese krti a hen Ea e Saa e 32 Modifying your Desigtt 5 eee Decio EEA chad E E ede iet set 32 Compiling Large Designs o 0ccs0cken enida tipa needa beads eda i aiiai a 32 Saving Compiled Design as EDIF lees 32 Reading CORES cocer seres tx eteti eI RUP a ea a ee pt deed 33 Setting Constraint
134. DCMO P defparam DCM1 D defparam DCM1 D defparam DCM1 S defparam DCM1 D defparam DC C defparam DCM1 C defparam DCM1 C defparam DCM1 C defparam DCM1 P synthesis tra endmodule DC Verilog code is for simulation only nslate off L FREQUENCY MODE LOW UTY CYCLE CORRECTION TRUE ARTUP WAIT TRUE FS FREQUENCY MODE LOW LKFX DIVIDE 1 KFX MULTIPLY 1 K FEEDBACK 1X LKOUT PHASE SHIFT NONE HASE SHIFT 0 L FREQUENCY MODE LOW UTY CYCLE CORRECTION TRUE ARTUP WAIT TRUE FS FREQUENCY MODE LOW LKFX DIVIDE 1 LKFX MULTIPLY 1 K FEEDBACK 1X LKOUT PHASE SHIFT FIXED HASE SHIFT 0 nslate on TOP VHDL example for LeonardoSpectrum library IEEE use IEEE std 1o entity DCM TOP port clock in clock out clock with ps out out std logic reset end DCM TOP architecture XI signal low hig signal dcm0 loc signal dcml loc signal clock signal clkO s signal clk1l s signal clock wi signal clock ou gic 1164 all is in std logic out std logic out std logic LINX of DCM TOP is h std logic ked std logic ked std logic std logic td logic td logic th ps std logic b int r Std logic wwWw xilinx com 1 800 255 7
135. DR 1 A0 ADDR O WE WE WCLK CLK synopsys attribute INIT AAAA RAM16X1S RAMO O DATA OUT 0 D DATA BUS 0 A3 ADDR 3 A2 ADDR 2 Al ADDR 1 A0 ADDR 0 WE WE WCLK CLK synopsys attribute INIT 0101 endmodule module RAM16X1S O D A3 A2 Al AO W output O input D input A3 input A2 input Al input A0 input WE input WCLK endmodule za WCLK e LeonardoSpectrum This example shows how to create a 16x4 RAM using Xilinx RAM16X1S component module RAM INIT EX1 DATA BUS ADDR WE CLK input 3 0 ADDR inout 3 0 DATA BUS input WE CLK wire 3 0 DATA OUT Only for Simulation the defparam will not synthesize Use the defparam for RTL simulation There is no defparam needed for Post P amp R simulation exemplar translate off defparam RAMO INIT 0101 RAM1 INIT AAAA RAM2 INIT FFFF RAM3 INIT 5555 exemplar translate_on assign DATA BUS WE DATA OUT 4 hz Instantiation of 4 16X1 Synchronous RAMs RAM16X1S RAM3 O DATA OUT 3 D DATA BUS 3 A3 ADDR 3 A2 ADDR 2 Al ADDR 1 AO ADDR 0 WE WE WCLK CLK exemplar attribute RAM3 INIT 5555 RAM16X1S RAM2 O DATA OUT 2 D DATA BUS 2 A3 ADDR 3 A2 ADDR 2 Al ADDR 1 AO ADDR 0 WE WE WCLK CLK exemplar attribute RAM2 INIT FFFF RAM16X1S RAMI O DATA
136. ER 272 Simulation Flows ssssssseee IR e 273 ModelSimi Vcot d ee teRRREAEPERET CLR E CIVI v qe p eid eg 273 Using Shared Precompiled Libraries 6 1 0 0 cece eee 273 Scirocco os Lv osa E et voe Rudd c Ede a aa rd RE ox rao un 273 Using Shared Precompiled Libraries 6 eee 273 NCVHDEN 7 3523 1 48b a E eu dmt dde de tami Ei ded 274 Using Shared Precompiled Libraries 1 1 0 0 ccc ce eee 274 NC Verilog M i coast eee ee ti eee 275 Using Library Source Files With Compile Time Options 0 005 275 Using Shared Precompiled Libraries 0 eens 275 pues EV eS Tr 276 Using Library Source Files With Compile Time Options 00005 276 Using Shared Precompiled Libraries 1 1 0 0 cece ce eens 277 ModelSim Vlog ie iet Let Ce eH Cede ee dae SA Ide b eee tds 278 Using Library Source Files With Compile Time Options sees 278 Using Shared Precompiled Libraries 1 1 0 0 ccc ce eens 278 IBIS 4 un eeu Li a he aed oN Ste ey ELE IE 279 STAM Beene ed She aden gcse NS ok a Seong A cg teat tts ee artes seas 280 Chapter 7 Equivalency Checking Introduction ee Pe ee OUR UP a RA Rahs a Ee Bs RR 281 Software and Device Support tutus 281 Supported Equivalency Checking Software 0 0000 281 Supported Synthesis Tools isses ea er e p rra 282 Supported Devices age i kr Re b Er 3 REI E eS EC GEE ein 282 Equivalency Checking Comp
137. Each hierarchical module contains an X ROCBUF cell which is driven by X GSR GLOBAL SIGNAL The output of the X ROCBUF is connected to the GSR signal of the hierarchical module Toggling the input to the top level port affects the entire design The X GSR GLOBAL SIGNAL global signal is defined in a package within the VHDL netlist The package name is design name ROCTOC If desired each of the hierarchical modules can be written out as a separate netlist using the NetGen mhf switch to create multiple hierarchical files This helps in analyzing lower level modules individually Every netlist contains the design name ROCTOC package definition with X GSR GLOBAL SIGNAL signal When lower modules are simulated though X ROCBUF is connected to X GSR GLOBAL SIGNAL there will be no event on it Hence the X ROCBUF creates a pulse similar to X ROC and the GSR of the module is toggled The ROC pulse width of the X ROCBUF component can be controlled using the rpw switch for NetGen If all the modules including the top level design module are compiled and analyzed together the top level port created via the gp switch would drive the X GSR GLOBAL SIGNAL and all X ROCBUF cells In this situation the X ROCBUF component does not create a pulse but rather behaves like a buffer passing on the value of the X GSR GLOBAL SIGNAL The ROC pulse width of the X ROCBUF component can be controlled using the rpw switch for NetGen Using VHDL STARTBUF VIRTEX ST
138. End FF Flip flop with asynchronous reset FF ASYNC RESET process RESET CLOCK begin if RESET 1 then B Q OUT lt 00000000 elsif CLOCK event and CLOCK 1 then B Q OUT lt D IN end if end process End FF ASYNC RESET Flip flop with asynchronous set FF ASYNC SET process SET CLOCK begin if SET 1 then C O OUT lt 13111111 elsif CLOCK event and CLOCK 1 then C Q OUT lt D IN end if end process End FF ASYNC SET 68 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Coding for Synthesis 2 XILINX Flip flop with asynchronous reset and clock enable RESET CLOCK FF CLOCK ENABLE process ENABLE begin if RESET 1 then D Q OUT 00000000 elsif CLOCK event and CLOCK 1 then if ENABLE 1 D Q OUT D IN end if end if then end process End FF CLOCK ENABLE Flip flop with asynchronous reset asynchronous set and clock enable FF ASR CLOCK ENABLE process ENABLE RESET SET CLOCK begin if RESET 1 then E Q OUT lt 00000000 elsif SET 1 then BO OUT lt 11111111 elsif CLOCK event and CLOCK 1 then if ENABLE 1 then E Q OUT lt D IN end if end if
139. HD Version 1 1 Illustrates clock buffer control Bet clock r implementation is to use enable rather than gated clock library I EEE use I use I EEE EE r td_logic_1164 all td_logic_unsigned all o o entity gate clock is port end gate INl1 IN2 DATA CLK LOAD in STD LOGIC OUT1 out STD LOGIC clock architecture BEHAVIORAL of gate clock is signal GATECLK STD LOGIC begin GATECLK lt IN1 and IN2 and CLK GATE PR process GATECLK DATA LOAD begin if GATECLK event and GATECLK 1 then if LOAD 1 then OUT1 lt DATA end if end if end process End GATE_PR end BEHAVIORAL Synthesis and Verification Design Guide www xilinx com 71 1 800 255 7778 2 XILINX 72 Chapter 3 General HDL Coding Styles Verilog Example VLIMllllll Yl P P M P ML ATTA ATT TT GATE CLOCK V Version 1 1 Gated Clock Example Better implementation to use clock enables than gating the clock HMUMUMLBMBgMMMLlMIMIIIIPBGMlHlll ll P TTT TTT TTT TT module gate clock IN1 IN2 DATA CLK LOAD OUT1 input IN1 input IN2 input DATA input CLK input LOAD output OUT reg OUT1 wire GATECLK assign GATECLK IN1 amp IN2 amp CLK always 8 posedge GATECLK begin if LOAD 1 b1 OUT1 lt DATA end endmodule DATA L_ gt LOAD
140. II 3 Virtex E Il II Pro II Pro X entity RAMB4 S8 synp is generic INIT 00 INIT 01 string 000000000000000000000000000000000000000000000000000000000000000 port WE EN RST CLK in std logic ADDR in std logic vector 8 downto 0 DI in std logic vector 7 downto 0 DO out std logic vector 7 downto 0 end RAMBA S8 synp architecture XILINX of RAMBA S8 synp is component RAMBA S8 port WE EN RST CLK in STD LOGIC ADDR in STD LOGIC VECTOR 8 downto 0 DI in STD LOGIC VECTOR 7 downto 0 DO out STD LOGIC VECTOR 7 downto 0 end component attribute xc props of ul label is INIT 00 2 amp INIT 00 amp INIT Ol1 amp INIT 01 begin Ul RAMBA S8 port map WE gt WE EN gt EN RST gt RST CLK gt CLK ADDR gt ADDR DI gt DI DO gt DO end XILINX library IEEE use IEEE std_logic_1164 all entity block_ram_ex is port CLK WE in std_logic ADDR in std_logic_vector 8 downto 0 DIN in std_logic_vector 7 downto 0 DOUT out std_logic_vector 7 downto 0 end block ram ex architecture XILINX of block ram ex is component RAMBA S8 synp generic INIT 00 INIT 01 string 000000000000000000000000000000000000000000000000000000000000000 port WE EN RST CLK in STD LOGIC ADDR in STD LOGIC VECTOR 8 downto 0 DI in STD LOGIC VECTOR 7 do
141. ILINX Another method for passing the CLKDLL attributes is through the use of a UCF file For example the following statement defines the initialization string for the code example above Note that passing attributes via the UCF file will not be reflected in behavioral simulation Care must be taken to ensure that there is not a miscorelation between behavioral simulation and implementation by ensuring that the defparam and UCF attributes are the same INST DLLO CLKDV_DIVIDE 4 INST DLLO DUTY_CYCLE_CORRECTION FALSE DCM The DCM Digital Clock Management component available in Virtex II Virtex II Pro Virtex II Pro X and Spartan 3 is an enhancement over the Virtex E CLKDLL The following example shows how to pass the attributes to the DCM component using the defparam statement in Verilog module DCM TEST clock in clock out clock with ps out reset input clock in output clock out output clock with ps out output reset wire low high dcm0 locked reset clk0 assign low 1 b0 assign high 1 bl assign reset dcm0_locked IBUFG CLOCK IN I clock in O clock DCM DCMO CLKFB clock out CLKIN clock DSSEN low PSCLK low PSEN low PSINCDEC low RST low CLKO clk0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX
142. INX 292 Chapter 7 Equivalency Checking RTL to Post Place and Route The second and final point at which most designers verify the functionality of their design is after place and route PAR This is the final transformation of the design The entire design has been mapped into primitive components and placed and routed on the FPGA By running an equivalence check between the golden RTL and the post PAR netlist you can verify that the optimizations and transformations done by the Xilinx implementation tools did not affect the functionality of the design The equivalence check includes the following steps 1 Implement the design with the Xilinx implementation tools and run NetGen to create a Verilog netlist Create a script file for running the verification in Formality Run the script file If the two netlists are not equivalent use Formality to debug the differences this process is not covered in this document Please see the Formality documentation for more information Implementing the Design and Running NetGen This section assumes that the user has prior experience with the Xilinx implementation tools For information on using the ISE GUI to implement a design please see the ISE Quick Start Tutorial For more information on the following command line programs see the Development System Reference Guide Following is a sample script that shows how to run the implementation tools and how to run NetGen N
143. Implemented 4 Back Annotated FDCE FDPE D Q D Q CK CK R GSR R GSR ROC Figure 6 3 ROC Simulation and Implementation Local Set Local Set X8348 e Behavioral Phase In this phase the behavioral or RTL description registers are inferred from the coding style and the ROC cell is instantiated This ensures that GSR behavior at the RTL level matches the behavior of the post synthesis and implementation netlists e Synthesized Phase In this phase inferred registers are mapped to a technology and the ROC instantiation is carried from the RTL to the implementation tools As a result consistent global set reset behavior is maintained between the RTL and synthesized structural descriptions during simulation e Implemented Phase During implementation the ROC is removed from the logical description and is placed and routed as a pre existing circuit on the chip All set resets for the registers are automatically assumed to be driven by the global set reset net so data is not lost e Back annotated Phase In this phase the Xilinx VHDL netlist program assumes all registers are driven by the GSR net uses the X ROC simulation model for the ROC and rewires it to the GSR nets in the back annotated netlist For a non hierarchical netlist the GSR net is a fully wired net and the X ROC cell drives it For a hierarchical netlist the GSR net is not wired across hierarchical modules The GSR net in each hierarchical modul
144. J lt 7 J J 1 begin G2 if tri state cntrl J begin data out J lt data in r J end else tri state data out begin data out J lt 1 bz end end end end always posedge clk begin data_in lt data_in_p register for input data in r data in register for output tri state cntrl 0 lt temp tri state 0 tri state cntrl 1 lt temp tri state l1 tri state cntrl 2 lt temp tri state 2 tri state cntrl 3 lt temp tri state 3 tri state cntrl 4 temp tri state 4 tri state cntrl 5 temp tri state 5 tri state cntrl 6 temp tri state 6 tri state cntrl 7 lt temp tri state 7 end endmodule Synthesis and Verification Design Guide www xilinx com 125 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Using pr Option with Map Use the pr pack registers option when running Map This option specifies to the Map program to move registers into IOBs when possible Use the following is the syntax map pr i o b input file name output file name Example map pr b design name ngd Virtex E OBs Virtex E has the same IOB structure and features as Virtex and Spartan II devices except for the available I O standards Additional I O Standards Virtex E devices have two additional I O standards LVPECL and LVDS Because LVDS and LVPECL require two signal lines
145. K if ENABLE then 17 COUNT DOWN lt COUNT DOWN end if end if end process DOWN COUNTER UP lt COUNT UP when GTS CDOWN lt COUNT_DOWN when end A CLOCK ENABLE OR COUNT_DOWN ror GTS AND COUNT UP r 0 d 0101 then 1 then 0001 else ZZZZ 0000 lt XILINX GSR COUNT_DOWN else ZZZZ2 The following figure shows the progression of the TOCBUF model and its interpretation in the four main design phases 1 Behavioral TOCBUF Global Tri State User Tri State Enable VO User Output gt Pad Output Buffer I X User Input lt Input Buffer 3 Implementation Global Tri State GTS User Tri State Enable User Output gt vO Pad Output Buffer I Xx User Input lt H Input Buffer 2 Synthesized TOCBUF Global Tri State User Tri State Enable User Output N Output Buffer 1 0 Pad m User Input IL Input Buffer 4 Back Annotation GTS PORT GTS User Tri State Enable User Output gt Output Buffer Global Tri State VO Pad S User Input lt J Input Buffer with global tri state port option X8351 Figure 6 6 TOCBUF Simulation and Implementation e Behavioral Phase In this phase the behavioral or RTL description of the output buffers is inferred from the coding style and may be inserted You can instantiate the TOCBUF cell e Synthesized
146. KDV_DIVIDE to 4 and sets the DUTY_CYCLE_CORRECTION to FALSE This code was written with the assumption that the synthesis tool can understand and pass the INIT attribute using generic notation library IEEE use IEEE STD LOGIC 1164 a11 use IEEE std logic arith all use IEEE std logic unsigned all Library UNISIM use UNISIM vcomponents all entity clkdlls is port CLK LF RST LF in std logic CLK90 LF CLK180 LF out std logic CLK270 LF CLK2X LF out std logic CLKDV LF LOCKED LF out std logic LFCount out std logic vector 3 downto 0 end architecture struct of clkdlls is component CLKDLL generic FACTORY JF bit vector X 00 STARTUP WAIT boolean false DUTY CYCLE CORRECTION boolean TRUE CLKDV DIVIDE real 2 0 port CLKIN in std logic CLKFB in std logic RST in std logic CLKO out std logic CLK90 out std logic CLK180 out std logic CLK270 out std logic CLK2X out std logic CLKDV out std logic LOCKED out std logic end component 248 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulating VHDL lt XILINX component IBUFG port I im std Logic O out std logic i end component component BUFG port I in std logic O out std logic i end component integer range 0 to 15 0 signal sigCLK_LF sigCLKO_LF
147. LK2X CLK2X180 CLKDV CLKFX CLKFX180 LOCKED dcm0_locked PSDONE STATUS i exemplar attribute DCMO DLL_FREQUENCY_MODE LOW exemplar attribute DCMO DUTY CYCLE CORRECTION TRUE exemplar attribute DCMO STARTUP WAIT TRUE exemplar attribute DCMO DFS FREQUENCY MODE LOW exemplar attribute DCMO CLKFX DIVIDE 1 exemplar attribute DCMO CLKFX MULTIPLY 1 exemplar attribute DCMO CLK FEEDBACK 1X exemplar attribute DCMO CLKOUT PHASE SHIFT NONE exemplar attribute DCMO PHASE SHIFT 0 BUFG CLK BUFO O clock out I clk0 DCM DCM1 CLKFB clock with ps out CLKIN clock DSSEN low PSCLK low PSEN low PSINCDEC low RST low LKO clk1 LK90 LK180 LK270 LK2X LK2X180 LKDV LKFX LKFX180 CKED dcm1 locked DONE TATUS Et dv det E E Ee E o n nurFaANqgqagQqQaAgaQqaQAaAaaAaAAa E 106 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Using Advanced Clock Management Z XILINX exemplar attribute DCM1 DLL_FREQUENCY_MODE LOW exemplar attribute DCM1 DUTY_CYCLE_CORRECTION TRUE exemplar attribute DCM1 STARTUP_WAIT TRUE exemplar attribute DCM1 DFS_FREQUENCY_MODE LOW exemplar attribute DCM1 CLKFX_DIVIDE 1 exemplar attribute DCM1 CLKFX_MULTIPL
148. LKIN in std logic GSROUT GTSOUT out std logic end component Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 243 XILINX begin U1 G Chapter 6 Verifying Your Design STARTBUF VIRTEX port map TSIN gt STP GSRIN gt ZERO CLKIN gt ZERO G TSOUT gt GTS_sig UP COUNTER begin if process CLOCK ENABLE RESE COUNT then UP lt 0000 elsif CLOCK event AND CLOCK 1 if ENABLE 1 then COUNT UP lt COUNT UP 0001 end if end if end process UP COUNTER DOWN COUNTER process begin if then CLOCK ENABLE RE SE T COUNT DOWN RESE 1 OR COUNT DOWN 0101 then COUNT DOWN 1111 elsif CLOCK event AND CLOCK 1 if ENABLE 1 then COUNT DOWN lt COUNT DOWN end if end if end process DOWN COUNTER CUP lt COUNT UP when GTS_sig 0 CDOWN lt COUNT DOWN when GTS sig end A then 0001 AND COUNT UP 0000 else 0 else ZZZ2 Z222 Simulating Special Components in VHDL The following section provides a description and examples of using special components such as the Block SelectRAM for Virtex M Simulating CORE Generator Components in VHDL For CORE Generator model simulation flows see the CORE Generator Guide Boundary Scan a
149. LL FREQUENCY MOD RUE DFS FREQUENCY MODE LOW CLKFX DIVIDE 1 CLKFX MULTIPLY EDBACK 1X CLKOUT PHASE SHIE NONE PHASE SHIF 0 Do not insert any carriage return between th E E CORRECTION TRUE STARTUP WAIT TRUE DFS FREQUENCY MODE LOW CLKFX DIVIDE 1 CLKFX MULTIPLY 1 CLK FEEDBACK Do no begin low lt 0 high lt 1 reset Ul dcm0 1X CLKOUT PHASE SHIFT FIXED PHASE SHIFT 0 t insert any carriage return between the lines abov lt not dem0_locked and dcml_locked clock_with_ps_out lt clock_with_ps clock_out lt clock_out_int IBUFG port map I gt clock_in O gt clock DCM port map CLKFB gt clock_out_int CLKIN gt clock DSSEN gt low PSCLK gt low PSEN gt low PSINCDEC gt low RST gt low CLKO gt clk0 LOCKED gt dcm0_locked Synthesis and Verification Design Guide wwWw xilinx com 99 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Clk buf0 BUFG port map I gt clk0 dcml1 DCM port map CLKFB clock with ps CLKIN gt clock DSSEN gt low PSCLK gt low PSEN gt low PSINCDEC gt low RST gt low CLKO gt clkl LOCKED gt doml1 locked i clk_bufl B
150. MULTIPLY integer 4 CLKFX_DIVIDE integer 1 CLKDV_DIVIDE real 2 0 DESKEW_ADJUST string SYSTEM_SYNCHRONOUS i 250 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulating VHDL 7 XILINX std_ulogic std_ulogic std_ulogic std_ulogic std_ulogic std_ulogic std_ulogic port CLKIN in CLKFB in DSSEN in PSINCDEC i PSEN in PSCLK in RST in CLKO out CLK90 out CLK180 out CLK270 out CLK2X out CLK2X180 out CLKDV out CLKFX out CLKFX180 out LOCKED out PSDONE out STATUS out end component begin GND lt 0 Ul IBUFG port map I gt clkin O gt clk ibufg U2 DCM generic map DFS EF QUENCY MODE std ulogic std ulogic std ulogic std ulogic std ulogic std ulogic std ulogic std logic std logic std ulogic std ulogic std logic vector 7 downto 0 gt LOW iL_F R R QUENCY_MODE gt LOW UTY CYCL D I E CORRECTION TRUE IVIDE BY 2 FALSE DBACK gt 1X T od H PHASE_SHIF gt VARIABLE Y_JF gt X 00 P WAIT gt FALSI DE gt NONE Ss MULTIPLY gt 4 D D ESKEW ADJUST gt HIFT gt 0 IVIDE gt 1 E A pH IVIDE gt 2 0 port map gt clk ibufg CLKFB gt clk0 bufg gt Pr
151. NGD simulation type the following at the command line For Verilog netgen sim ofmt verilog options design ngd For VHDL netgen sim ofmt vhdl options design ngd Post Map simulation To run a post Map simulation perform the following command line operations ngdbuild options design map options design ngd For Verilog netgen sim ofmt verilog options design ncd ngm design ngm For VHDL netgen sim ofmt vhdl options design ncd ngm design ngm Post PAR simulation To run a post PAR simulation perform the following command line operations ngdbuild options design map options design ngd par options design ncd w design par ncd For Verilog netgen sim ofmt verilog options design par ncd ngm design ngm For VHDL netgen sim ofmt vhdl options design par ncd ngm design ngm Disabling X Propagation During a timing simulation when a timing violation occurs the default behavior of a latch register RAM or other synchronous element is to output an X to the simulator The reason for this is that when a timing violation occurs it is not known what the actual output value should be The output of the register could retain its previous value update to the new value or perhaps go metastable in which a definite value is not settled upon until sometime after the clocking of the synchronous element Since this value cannot be determined accurate simulation results cannot be guaranteed and s
152. NIT AAAA RAM2 INIT FFFF assign DATA BUS WE DATA OUT 4 hz Instantiation of 4 16X1 Synchronous RAMs Use the xc props attribute to pass the INIT property synthesis attribute INIT of RAM2 is FFFF synthesis attribute INIT of RAM1 is AAAA synthesis attribute INIT of RAMO is 0101 RAM16X1S RAM3 O DATA OUT 3 D DATA_BUS 3 A3 ADDR 3 A2 Al ADDR 1 AO ADDR 0 WE WE WCLK CLK RAM16X1S RAM2 O DATA OUT 2 D DATA BUS 2 A3 ADDR 3 A2 A1 ADDR 1 AO ADDR 0 WE WE WCLK CLK RAM16X1S RAMI O DATA OUT 1 D DATA BUS 1 A3 ADDR 3 A2 A1 ADDR 1 AO ADDR 0 WE WE WCLK CLK RAM16X1S RAMO O DATA OUT 0 D DATA_BUS 0 A3 ADDR 3 A2 Al ADDR 1 AO ADDR 0 WE WE WCLK CLK endmodule Inferring Distributed SelectRAM in VHDL The following coding examples provide VHDL and Verilog coding styles for FPGA Compiler II LeonardoSpectrum Synplify and XST FPGA Compiler IITM FPGA Compiler II does not infer RAMs LeonardoSpectrum Synplify and XST ADDR 2 ADDR 2 ADDR 2 ADDR 2 The following is a 32x8 32 words by 8 bits per word synchronous dual port RAM example Synthesis and Verification Design Guide wwWw xilinx com 1 800 255 7778 173 SZ XILINX Chapter 4 Architecture Specific Codin
153. NIT 04 256 hnew hex value UO INIT 05 256 hnew hex value UO INIT 06 256 hnew hex value UO INIT 07 256 hnew hex value UO INIT 08 256 hnew hex value UO INIT 09 256 hnew hex value UO INIT 0A 256 hnew hex value UO INIT OB 256 hnew hex value UO INIT OC 256 hnew hex value UO INIT OD 256 hnew hex value UO INIT OE 256 hnew hex value UO INIT OF 256 hnew hex value endmodule Note Some synthesis tools may not support the use of a defparam statements See the Defparam Support Considerations section for details Synthesis and Verification Design Guide www xilinx com 257 1 800 255 7778 2 XILINX 258 Chapter 6 Verifying Your Design Another method for passing the INIT 0x attributes is through the use of a UCF file For example the following statement defines the initialization string for the code example above INST UO INIT 00 INST UO INIT 01 5555aaaa5555aaaa5555aaaa5555aaaa5555aaaa 5555aaaa5555aaaa5555aaaa5555aaaa5555aaaa The value of the INIT_Ox string is a hexadecimal number that defines the initialization string for implementation however it will not be reflected for behavioral simulation When using Distributed RAM or Block RAM in dual port mode special care must be taken to avoid memory collisions See the Collision Checking section for a general description of collision checking CLKDLL The duty cycle of the CLKO output is 50 unless the DUTY_CYCLE_CORRECTION att
154. OWS cede sche eee antes bud sves qe agqa adu anh T ES Eam 194 Installing SmartModels from Xilinx Implementation Tools 194 Method One ee EE ak REPETI RED ancl een eae 194 Wind OWS i RE pex Pie oh Ro oe ee oe ene oS 194 Solaris sut cha hdd y x ee bes ach Raa aes AER EE RR HERR EEE aA 194 Method TWO e cs54 0 oc escsedis ernier tiee Aann eu LEN based bade gae ries 195 eia c sacs haste Bs DA ERNE A eee E Bea a CGN Geb RAE ERS 195 Wind OWS cco cn ee text eben tuique ee PN qun PEU X Hic ads 195 R nning Simulation MU V M a es 196 MTIG ModelSim SE Solaris esee RII 196 SimulatorSet p 4i ds aee pee aee s Wr eR ERR ce due p dcr eta d 196 Running Simulation eei ee eee decides ek dace der ede eres 197 MTIG ModelSim SE Windows eeeeeeeee RR n 197 Simulator Setup so vy acer rete creep e race ead es ad es ees 197 Running Sinr latlOnk zum ede eC p turpe ace een a tg dn d gebe cerdos IR es 198 Cadence Verilog XL Solaris nanunua nannan eee eee 199 R nning Sin latlOD ccn decet beet ep lad ae ated oe Gilad ase ned ens hice 199 Cadence NC Verilog Solaris 0 0 0 0 201 R nrmng Sim Wath Othe cdd pe pO ere ety ute ec a tg es ease Rob dtr dte d 201 Synopsys VCS Solaris 0 eee ees 202 Running Sim latloh cot pee ee adieve teed Gedy p ia e e eer ghee eee 202 Chapter 6 Verifying Your Design Introduction ios ores een ce li
155. SR PORT Local Set TD Local Set With global reset port option X8349 Figure 6 4 ROCBUF Simulation and Implementation e Behavioral Phase In this phase the behavioral or RTL description registers are inferred from the coding style and the ROCBUF cell is instantiated Use the ROCBUF cell instead of the ROC cell when you want test bench control of GSR simulation e Synthesized Phase In this phase inferred registers are mapped to a technology and the ROCBUF instantiation is carried from the RTL to the implementation tools As a result consistent global set reset behavior is maintained between the RTL and synthesized structural descriptions during simulation e Implemented Phase During implementation the ROCBUF is removed from the logical description of the design and the global resources are used for the set reset function Synthesis and Verification Design Guide www xilinx com 235 1 800 255 7778 lt XILINX 236 Chapter 6 Verifying Your Design e Back annotated Phase In this phase use the NetGen option gp to replace the port that was previously occupied by the ROCBUF in the RTL description of the design A non hierarchical netlist will have this port drive the fully wired GSR signal For hierarchical designs the GSR net is not wired across hierarchical modules The VHDL global signal X GSR GLOBAL SIGNAL is used to connect the top level port created by the gp switch to the GSR signals of the hierarchical modules
156. STD ULOGIC ADDR in STD LOGIC VECTOR 9 downto 0 DO out STD LOGIC VECTOR 3 downto 0 i end component begin INST RAMBA S4 RAMBA S4 generic map INIT 00 gt X new hex value INIT 01 X new hex value INIT 02 X new hex value INIT 03 X new hex value INIT 04 X new hex value INIT 05 X new hex value INIT 06 X new hex value INIT 07 X new hex value INIT 08 X new hex value INIT 09 gt X new hex value INIT 0A X new hex value INIT OB X new hex value INIT 0C X new hex value INIT OD X new hex value INIT OE X new hex value INIT OF gt X new hex value Synthesis and Verification Design Guide www xilinx com 247 1 800 255 7778 2 XILINX Chapter 6 Verifying Your Design port map DI gt DI EN gt EN WE gt WE RST gt RST CLK gt CLK ADDR gt ADDR DO gt DORAMB4_S4 end struct Note Some synthesis tools may not support the use of a generic statements See the Generics Support Considerations section for details Simulating the Virtex Clock DLL When functionally simulating the Virtex Clock DLL generic maps are used to specify the CLKDV_DIVIDE and DUTY_CYCLE_CORRECTION values By default the CLKDV_DIVIDE is set to 2 and DUTY_CYCLE_CORRECTION is set to TRUE The following example sets the CL
157. Scan and Readback The Boundary Scan and Readback circuitry cannot be simulated at this time Defparam Support Considerations Some synthesis tools do not support the use of defparams to attach attributes If your synthesis tool does not support defparams use of the special meta comment to make the code visible only to the simulator Place the meta comments immediately before and after the defparam declarations and mappings as follows synthesis translate off defparam UO INIT 2 b01 synthesis translate off The attributes can then be passed to the implementation tools by defining them in the UCF file Alternatively the synthesis tool may support a mechanism to pass these attributes directly from the Verilog file without using the generics Please see your synthesis tool documentation for specific details on attribute passing for your synthesis tool Synthesis and Verification Design Guide www xilinx com 255 1 800 255 7778 XILINX Chapter 6 Verifying Your Design Differential I O LVDS LVPECL For Virtex E and Spartan ITE families the inputs of the differential pair are currently modeled with only the positive side whereas the outputs have both pairs positive and negative For details please see Answer Record 8187 on the Xilinx support website at http support xilinx com This is not an issue for the Virtex II II Pro II Pro X or Spartan 3 architecture because the differential buffers for Virtex II
158. Spartan 3 are as follows e RAMI6XID e RAM32XID e RAM64XID In addition to distributed RAM and ROM capabilities Virtex E II and Spartan II FPGAs provide edge triggered Block SelectRAM in large blocks Virtex E and Spartan II devices provide 4096 4k bits RAMB4_Sn and RAMBA Sm Sn Virtex II II Pro II Pro X and Spartan 3 devices provide larger Block SelectRAM in 16384 16k bit size RAMB16 Sn and RAMB16 Sm 5n where Sm and Sn are configurable port widths See the Libraries Guide for more information on these components The edge triggered capability simplifies system timing and provides better performance for RAM based designs This RAM can be used for status registers index registers counter storage constant coefficient multipliers distributed shift registers LIFO stacks latching or any data storage operation The dual port RAM simplifies FIFO designs Implementing Block RAM Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X Spartan II and Spartan 3 FPGAs incorporate several large Block SelectRAM memories These complement the distributed SelectRAM that provide shallow RAM structures implemented in CLBs The Block SelectRAM is a True Dual Port RAM which allows for large discrete blocks of memory Block SelectRAM memory blocks are organized in columns All Virtex and Spartan II devices contain two such columns one along each vertical edge In Virtex E t
159. Synthesis and Verification Design Guide XILINX XILINX Xilinx and the Xilinx logo shown above are registered trademarks of Xilinx Inc Any rights not expressly granted herein are reserved CoolRunner RocketChips Rocket IP Spartan StateBENCH StateCAD Virtex XACT XC2064 XC3090 XC4005 and XC5210 are registered trademarks of Xilinx Inc The shadow X shown above is a trademark of Xilinx Inc ACE Controller ACE Flash A K A Speed Alliance Series AllianceCORE Bencher ChipScope Configurable Logic Cell CORE Generator CoreLINX Dual Block EZTag Fast CLK Fast CONNECT Fast FLASH FastMap Fast Zero Power Foundation Gigabit Speeds and Beyond HardWire HDL Bencher IRL J Drive JBits LCA LogiBLOX Logic Cell LogiCORE LogicProfessor MicroBlaze MicroVia MultiLINX NanoBlaze PicoBlaze PLUSASM PowerGuide PowerMaze QPro Real PCI RocketlO SelectlO SelectRAM SelectRAM Silicon Xpresso Smartguide Smart IP SmartSearch SMARTswitch System ACE Testbench In A Minute TrueMap UIM VectorMaze VersaBlock VersaRing Virtex Il Pro Virtex Il EasyPath Wave Table WebFITTER WebPACK WebPOWERED XABEL XACT Floorplanner XACT Performance XACTstep Advanced XACTstep Foundry XAM XAPP X BLOX XC designated products XChecker XDM XEPLD Xilinx Foundation Series Xilinx XDTV Xinfo XSI XtremeDSP and ZERO are trademarks of Xilinx Inc The Programmable Logic Company is a service mark of Xilinx Inc
160. Synthesis and Verification Design Guide 1 800 255 7778 Implementing Inputs and Outputs Z XILINX in the outputs Please refer to the Instantiating Components section for information on instantiating primitives e VHDL example library ieee use ieee std_logic_1164 all entity ddr_input is port clk in std_logic d 2 in std logic rst in std logic gl z out std logic q2 out std logic end ddr input architecture behavioral of ddr input is begin qlreg process clk rst begin if rst 1 then qi 0 elsif clk event and clk 1 then ql lt d end if end process q2reg process clk rst begin if rst 1 then q2 lt 0 elsif clk event and clk 0 then q2 lt d end if end process end behavioral e Verilog example module ddr_input data_in data_out clk rst input data_in clk rst output data_out reg ql q2 always posedge clk or posedge rst begin if rst qi lt 1 b0 else ql lt data in end always negedge clk or posedge rst begin if rst q2 lt 1 b0 else q2 lt data_in end assign data_out ql amp q2 end module Synthesis and Verification Design Guide www xilinx com 123 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan Il 3 Virtex E Il II Pro II Pro X Using Output Enable IOB Register The following VHDL and Verilog examples illustrate how to infer an output enable
161. Synthesis and Verification Design Guide www xilinx com 263 1 800 255 7778 XILINX Chapter 6 Verifying Your Design The primary job of the DLL DCM is to remove the clock delay from the internal clocking circuit as shown in the following figure Clock Distribution Hatwork Veriable CLKOLT ERI Delay Line EEJ Doh Figure 6 7 Delay Locked Loop Block Diagram Do not confuse this with the function of de skewing the clock Clock skew is generally associated with delay variances in the clock tree which is a different matter By removing the clock delay the input clock to the device pin should be properly phase aligned with the clock signal as it arrives at each register it is sourcing This means that observing signals at the DLL DCM pins generally does not give the proper view point to observe the removal of the clock delay The place to see if the DCM is doing its job is to compare the input clock at the input port to the design with the clock pins of one of the sourcing registers If these are aligned or shifted to the desired amount then the DLL DCM has accomplished its job Non LVTTL Input Drivers When using non LVTTL input buffer drivers to drive the clock the DCM does not make adjustments as to the type of input buffer chosen but instead has a single delay value to provide the best amount of clock delay across all I O standards If you are using the same input standard for the data the delay values shoul
162. T PHASE SHIFT of dcml label is FIXED attribute PHASE SHIFT of dcml label is O0 component IBUFG is port I in std logic O out std logic end component component BUFG is port I in std logic O out std logic end component Synthesis and Verification Design Guide www xilinx com 103 1 800 255 7778 SZ XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X component DCM is port CLKFB in std logic CLKIN in std logic DSSEN in std logic PSEN in std logic PSINCDEC in std logic RST in std logic CLKO out std logic CLK90 out std logic CLK180 out std logic CLK270 out std logic CLK2X out std logic e C C C LKDV ou LKFX ou td_logic td_logic ct ct S S LOCKED out std logic PSDONE out std logic STATUS out std logic vector end component begin low lt 0 high lt 1 LK2X180 out std logic LKFX180 out std logic 7 downto 0 reset lt not dcm0_locked and dcml_locked clock_with_ps_out lt clock_with_ps clock_out lt clock_out_int Ul IBUFG port map I gt clock in O gt clock dcm0 DCM port map CLKFB gt clock_out_int CLKIN gt clock DSSEN gt low PSCLK gt low PSEN gt low PSINCDEC gt low RST gt low CLKO gt clk0 LOCKED gt dcm0_locked
163. This code written with the assumption that the synthesis tool can understand and pass the INIT attribute using the generic notation Synthesis and Verification Design Guide www xilinx com 245 1 800 255 7778 XILINX Chapter 6 Verifying Your Design entity lut_ex is port LUT1 IN LUT2 IN in std logic vector 1 downto 0 LUT1 OUT LUT2 OUT out std logic vector 1 downto 0 end entity lut ex architecture lut arch of lut ex is component LUT1 generic INIT std logic vector 1 downto 0 10 port O out std logic I0 in std logic end component component LUT2 generic INIT std logic vector 3 downto 0 0000 port O out std logic IO I1 in std logic end component begin LUT1 used as an inverter UO LUT1 generic map INIT 01 port map O gt LUT1 OUT 0 IO gt LUT1 IN 0 LUT1 used as a buffer Ul LUT1 generic map INIT 10 port map O gt LUT1 OUT 1 IO gt LUT1 IN 1 LUT2 used as a 2 input AND gate U2 LUT2 generic map INIT 1000 t map O gt LUT2 OUT 0 Il gt LUT2 IN 1 IO gt LUT2 IN 0 LUT2 used as 2 input NAND gate 3 LUT2 generic map INIT 0111 port map O gt LUT2 OUT 1 I1 gt LUT2 IN 1 I0 gt LUT2 IN 0 end lut arch Note Some synthesis tools may not support the use of a generic statements See the Generics Support Considerations section
164. UFG port map I gt clkl O gt clock with ps i end XILINX Verilog example for Synplify O gt clock out int This example attaches multiple attributes to DCM components using the Synplify XC PROP attribute Note Do not insert carriage returns between the values assigned to xc props A carriage return could cause Synplify to attach only part of the attributes Nerilog code begin include path to virtex2 v module DCM TOP clock in clock out clock with ps out reset input clock in output clock out output clock with ps out output reset wire low wire high wire dcmO0 locked wire dcml locked wire reset wire clk0 wire clk1 assign low 1 b0 assign high 1 b1 assign reset dcm0 locked amp doml locked IBUFG CLOCK IN I clock in O clock 100 wwWw xilinx com 1 800 255 7778 Synthesis and Verification Design Guide Using Advanced Clock Management lt XILINX DCM DCMO CLKFB clock out CLKIN clock DSSEN low PSCLK low PSEN low PSINCDEC low RST low LKO c1k0 LK90 LK180 LK270 LK2X LK2X180 LKDV LKFX LKFX180 OCKED dcm0 locked DONE STATUS synthesis xc props DLL FREQUENCY MODE LOW DUTY CYCLE CORRECTION TRUE STARTUP_WAIT TRUE DFS FREQUENCY MODE LOW CLKFX DIVIDE 1 CLKFX MULTIPLY 1 CLK FEEDBACK 1X CLKOUT PHASE SHIFT NONE PHASE SHIFT 0
165. UT PHASE SHIFT of DCMO is FIXED synthesis attribute PHASE SHIFT of DCMO is 0 110 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Using Advanced Clock Management lt XILINX DCM DCM1 CLKFB clock_with_ps_out CLKIN clock DSSEN low PSCLK low PSEN low PSINCDEC low RST low LKO c1k1 LK90 LK180 LK270 LK2X LK2X180 LKDV LKFX LKFX180 OCKED decm1 locked DONE STATUS i synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis ee Et rv Ie E E Ew pn T EO GOOO GOAO E n tribute DLL_FREQUENCY_MODE of DCM1 is LOW tribute DUTY CYCLE CORRECTION of DCM1 is TRUE tribute STARTUP WAIT of DCM1 is TRUE tribute DFS FREQUENCY MODE of DCM1 is LOW tribute CLKFX DIVIDE of DCM1 is 1 tribute CLKFX MULTIPLY of DCM1 is 1 C C P tribute IK FEEDBACK of DCM1 is 1X tribute LKOUT PHASE SHIFT of DCM1 is FIXED tribute HASE SHIFT of DCM1 is 0 y moomomyonmonmnontmvgtv Chet cr cb ct cb cb ch cr BUFG CLK_BUF1 O clock_with_ps_out JCLET 4 The following Verilog code is for simulation only synthesis translate off
166. VITAL timing checks Timing Problem Root Causes Timing violations such as setuphold occur any time data changes at a register input either data or clock enable within the setup or hold time window for that particular register There are a few typical causes for timing violations the most common are the following e The design is not constrained e A path in the design is not constrained e The design does not meet timespecs e The design simulation clock does not match what is called for in the timespecs e Clock skew is unaccounted for in a particular data path e A path in the design has asynchronous inputs crosses out of phase clock domains or has asynchronous clock boundaries Design Not Constrained Timing constraints are essential to help you meet your design goals or obtain the best implementation of your circuit Global timing constraints cover most constrainable paths in a design These global constraints cover clock definitions input and output timing requirements and combinatorial path requirements Specify global constraints like PERIOD OFFSET_IN_BEFORE and OFFSET_OUT_AFTER to match your simulation stimulus with the timespecs of the devices used in the design In general keep in mind the following two points when constraining a design e PERIOD Can be quickly applied to a design It also leads in the support of OFFSET which you can use to specify your I O timing This works well for a single clock design or multi
167. Verification Design Guide 1 800 255 7778 Using Advanced Clock Management lt XILINX synopsys attribute DLL_FREQUENCY_MODE LOW DUTY_CYCLE_CORRECTION TRUE STARTUP WAIT TRUE DFS FREQUENCY MODE LOW CLKFX DIVIDE 1 CLKFX MULTIPLY 1 CLK FEEDBACK 1X CLKOUT PHASE SHIFT FIXED PHASE SHIFT 0 BUFG CLK BUF1 O clock with ps out I clk1 The following Verilog code is for simulation only synopsys translate off defparam DCMO DLL FREQUENCY MODE LOW defparam DCMO DUTY CYCLE CORRECTION TRUE defparam DCMO STARTUP WAIT TRUE defparam DCMO DFS FREQUENCY MODE LOW defparam DCMO CLKFX DIVIDE 1 defparam DCMO CLKFX MULTIPLY 1 defparam DCMO CLK FEEDBACK 1X defparam DCMO CLKOUT PHASE SHIFT NONE defparam DCMO PHASE SHIFT 0 defparam DCMI DLL FREQUENCY MODE LOW defparam DCMI DUTY CYCLE CORRECTION TRUE defparam DCMI STARTUP WAIT TRUE defparam DCM1 DFS FREQUENCY MODE LOW defparam DCMI CLKFX DIVIDE 1 defparam DCM1 CLKFX_MULTIPLY 1 defparam DCMI CLK FEEDBACK 1X defparam DCMI CLKOUT PHASE SHIFT FIXED defparam DCMI PHASE SHIFT 0 synopsys translate on endmodule DCM TOP e Verilog example for XST module DCM TOP clock in clock out
168. Y and MULT AND primitives for Virtex Virtex E Spartan II Spartan 3 Virtex II Virtex II Pro and Virtex Pro X The following example shows this construct e VHDL example library IEEE use IEEE td logic 1164 all use IEEE std logic arith all o entity multiply is generic size integer 16 level integer 4 port Clk in std logic Ain in std logic vector size 1 downto 0 Bin in std logic vector size 1 downto 0 Qout out std logic vector 2 size 1 downto 0 end multiply architecture RTL of multiply is type levels of registers is array level 1 downto 0 of unsigned 2 size 1 downto 0 signal reg bank levels of registers signal a b unsigned size 1 downto 0 begin Qout lt std logic vector reg bank level 1 process begin wait until clk event and clk 1 a lt unsigned Ain b lt unsigned Bin reg bank 0 lt a b for i in 1 to level 1 loop reg bank i lt reg bank i 1 end loop end process end architecture RTL www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Operators and Generate Modules Z XILINX The following is a synchronous multiplier VHDL example coded for Synplify and XST library ieee use ieee std_logic_1164 all use ieee std_logic_arith all use ieee std_logic_unsigned all entity xcv2_mult18x18s is Port a in std logic vect
169. Y 1 exemplar attribute DCM1 CLK_FEEDBACK 1X exemplar attribute DCM1 CLKOUT_PHASE_SHIFT FIXED exemplar attribute DCM1 PHASE_SHIFT 0 BUFG CLK_BUF1 O clock_with_ps_out I clk1 The following Verilog code is for simulation only exemplar translate off defparam DCMO DLL FREQUENCY MODE LOW defparam DCMO DUTY CYCLE CORRECTION TRUE defparam DCMO STARTUP WAIT TRUE defparam DCMO DFS FREQUENCY MODE LOW defparam DCMO CLKFX DIVIDE 1 defparam DCMO CLKFX MULTIPLY 1 defparam DCMO CLK FEEDBACK 1X defparam DCMO CLKOUT PHASE SHIFT NONE defparam DCMO PHASE SHIFT 0 defparam DCMI DLL FREQUENCY MODE LOW defparam DCMI DUTY CYCLE CORRECTION TRUE defparam DCMI STARTUP WAIT TRUE defparam DCM1 DFS FREQUENCY MODE LOW defparam DCMI CLKFX DIVIDE 1 defparam DCMI CLKFX MULTIPLY 1 defparam DCMI CLK FEEDBACK 1X defparam DCMI CLKOUT PHASE SHIFT FIXED defparam DCMI PHASE SHIFT 0 exemplar translate on endmodule DCM TOP e Verilog example for FPGA Compiler II module DCM_TOP clock_in clock_out clock_with_ps_out reset input clock in output clock out output clock with ps out output reset wire low wire high wire dcmO0 locked wire dcml locked wire reset wire clk0 wire cl
170. You can also correctly back annotate a GTS signal by instantiating a STARTUP_VIRTEX STARTBUF VIRTEX STARTUP_SPARTAN2 or STARTBUF_SPARTAN2 symbol and correctly connect the GTSIN input signal of the component 242 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulating VHDL Z XILINX See the following table for Virtex Virtex II and Spartan II correspondence of pins between STARTBUF and STARTUP Table 6 6 Virtex II E and Spartan II STARTBUF STARTUP Pins STARTBUF Connection STARTUP Pin Pin Names Points Names GSRIN Global GSR Set Reset Port of Design GTSIN Global Tristate GTS Port of Design CLKIN Port of Internal CLK Logic GTSOUT All Output N A Buffers Tristate Control GSROUT All Registers N A Asynchronous Set Reset STARTBUF_VIRTEX Model Example The following is an example of the STARTBUF_VIRTEX model library IEEE use IEEE std_logic_1164 all use IEEE std logic unsigned all library UNISIM use UNISIM all entity EX STARTBUF is port CLOCK ENABLE RESET STP in std logic CUP CDOWN EX STARTBUF out std logic vector 3 downto 0 end architecture A of EX STARTBUF is signal GTS sig std logic signal COUNT UP COUNT DOWN std logic vector 3 downto 0 signal ZERO std ulogic 0 component STARTBUF VIRTEX port GSRIN GTSIN C
171. _logic Data Type IEEE STD 1164 93 The Xilinx software currently supports the Verilog IEEE 1364 2001 Standard VHDL IEEE Standard 1076 1993 and IEEE Standard 1076 4 2000 for Vital Vital 2000 and SDF version 3 0 Note Although the Xilinx HDL netlisters produce IEEE STD 1076 93 VHDL code or IEEE STD 1364 2001 Verilog code that does not restrict the use of newer or older standards for the creation of test benches or other simulation files If the simulator being used supports both older and newer standards then generally both standards can be used in these simulation files Be sure to indicate to the simulator during code compilation which standard was used for the creation of the file Xilinx currently tests and supports the following simulators for VHDL and Verilog simulation e VHDL MTI ModelSim Cadence NC VHDL Synopsys Scirocco e Verilog MTI ModelSim Cadence Verilog XL Cadence NC Verilog Synopsys VCSi In general you should run the most current version of the simulator available to you Xilinx develops its libraries and simulation netlists using IEEE standards so you should be able to use most modern VHDL and Verilog simulators Check with your simulator vendor before you start to confirm that the proper standards are supported by your simulator and to verify the proper settings for your simulator The Xilinx VHDL libraries are tied to the IEEE STD 1076 4 200
172. aint can be found in the Constraints Guide 260 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Design Hierarchy and Simulation XILINX Alternatively if the design was compiled using a bottom up methodology where individual implementation files EDIF or NGC were created for each level of design hierarchy the KEEP_HIERARCHY constraint may be automatically generated A KEEP HIERARCHY constraint is generated for each separate design file passed to the Xilinx software by the use of a switch during input netlist translation During the NGDBuild netlist translation stage if the insert keep hierarchy switch is enabled the hierarchy for each individual input file for the design is preserved during implementation After the design is mapped placed and routed run NetGen with the resulting NGM file from Map during delay annotation to properly back annotate the hierarchy of the design netgen sim ofmt vhdl verilog ngm design name map ngm design name ncd netlist name This is the default way NetGen is run when using ISE or XFLOW to generate the simulation files It is only necessary to know this if you plan to execute NetGen outside of ISE or XFLOW or if you have modified the default options in ISE or XFLOW When you run NetGen using the NGM file all hierarchy that was specified to KEEP HIERARCHY will be reconstructed in the resulting VHDL or Verilog netlist NetGen has the ability to write out a separate netli
173. al routing Synthesis and Verification Design Guide www xilinx com 237 1 800 255 7778 XILINX Chapter 6 Verifying Your Design The following is an example of how to use the TOC cell library IEEE use IEEE std_logic_1164 all use IEEE std_logic_unsigned all library UNISIM use UNISIM all entity EX_TOC is port CLOCK ENABLE in std_logic CUP CDOWN out std_logic_vector 3 downto 0 end EX TOC architecture A of EX TOC is signal GSR GTS std logic signal COUNT UP COUNT DOWN std logic vector 3 downto 0 component ROC port O out std logic end component component TOC port O out std logic end component begin Ul ROC port map O gt GSR U2 TOC port map O gt GTS UP COUNTER process CLOCK ENABLE GSR begin if GSR 1 then COUNT UP 0000 elsif CLOCK event AND CLOCK 1 then if ENABLE 1 then COUNT_UP lt COUNT UP 0001 end if end if end process UP_COUNTER DOWN_COUNTER process CLOCK ENABLE GSR COUNT_DOWN begin if GSR 1 OR COUNT DOWN 0101 then COUNT_DOWN lt 1111 elsif CLOCK event AND CLOCK 1 then if ENABLE 1 then COUNT DOWN lt COUNT DOWN 0001 end if end if end process DOWN COUNTER CUP lt COUNT UP when GTS 0 AND COUNT UP 0000 else ZZZZ CDOWN lt
174. amp Route Simulation Model Project Navigator now runs through the steps required to produce the back annotated simulation netlist From XFLOW To display the available options for XFLOW and for a complete list of the XFLOW option files type flow at the prompt without any arguments For complete descriptions of the options and the option files see the Development System Reference Guide 1 Opena command terminal and change directory to the project directory 2 Typethe following at the command prompt To create a functional simulation Post NGD netlist from an input design EDIF file xflow fsim option file opt design name edif To create a timing simulation post PAR netlist from an input EDIF design file xflow implement option file tsim option file design name edf To create a timing simulation Post PAR netlist from an NCD file gt xflow tsim option file opt design name ncd XFLOW runs the appropriate programs with the options specified in the option file To change the options run xflow first with the norun switch to have XFLOW copy the option file s to the project directory Then edit the appropriate option file to modify the run parameters for the flow For more information on running XFLOW see the Development System Reference Guide 226 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Running NetGen lt XILINX From Command Line or Script File Post NGD simulation To run a post
175. and then Service Packs Software documentation tutorials and design files are also available from this website Advantages of Using HDLs to Design FPGAs Using HDLs to design high density FPGAs is advantageous for the following reasons e Top Down Approach for Large Projects HDLs are used to create complex designs The top down approach to system design supported by HDLs is advantageous for large projects that require many designers working together After the overall design plan is determined designers can work independently on separate sections of the code e Functional Simulation Early in the Design Flow You can verify the functionality of your design early in the design flow by simulating the HDL description Testing your design decisions before the design is implemented at the RTL or gate level allows you to make any necessary changes early in the design process e Synthesis of HDL Code to Gates You can synthesize your hardware description to a design implemented with gates This step decreases design time by eliminating the need to define every gate Synthesis to gates also reduces the number of errors that can occur during a manual translation of a hardware description to a schematic design Additionally you can apply the automation techniques used by the synthesis tool such as machine encoding styles or automatic I O insertion during the optimization of your design to the original HDL code resulting in greater efficiency
176. ard hase teed E ee 119 Inputs visited Med bee ee aE A 120 Sup c IL PCT 121 Using IOB Register and Latch 0 66 nee eee 121 Using Dual Data Rate IOB Registers 0 6 6 cece eee eee 122 Using Output Enable IOB Register 06 ce cee eens 124 Using pr Option with Map ssec sies sen sasin daien aae eee eee eens 126 Virtex E JOBS v4 3 techie y sendy denied ceeded aA RICH PA EE Maeda Rd 126 Additional I O Standards oo cit coc e ss een eb cae da Phare show Grav DR bi ads n 126 Synthesis and Verification Design Guide www xilinx com 11 1 800 255 7778 lt XILINX Virtex II II Pro II Pro X Spartan 3 IOBs 60 eee 131 Differential Signaling in Virtex II II Pro II Pro X or Spartan 3 l naana 131 Encoding State Machines 0 00 0 cece cece eee een ees 134 Using Binary Encoding peregi cepi iepa eee nee eee 135 Binary Encoded State Machine VHDL Example 6 0 0 cee eee eee eee 136 Binary Encoded State Machine Verilog Example 000 cee e ee eee eee 138 Using Enumerated Type Encoding 2 6 c cece eee eens 140 Enumerated Type Encoded State Machine VHDL Example 0 005 140 Enumerated Type Encoded State Machine Verilog Example less 141 Using One Hot Encoding 0 6 6 eee eens 142 One hot Encoded State Machine VHDL Example 0 60 c ee eee eae 142 One hot Encoded State Machine Verilog Example 0 2 0 00 cee eee eee 143
177. artan 3 Block SelectRAM is used to infer ROM if the address line is between 10 and 14 bits no minimum data width is required LeonardoSpectrum e In LeonardoSpectrum synchronous ROMs with address widths greater than eight bits are automatically mapped to Block SelectRAM e Asynchronous ROMs and synchronous ROMs with address widths less than eight bits are automatically mapped to distributed SelectRAM Synplify Synplify can infer ROMs using Block SelectRAM instead of LUTs for Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X and Spartan 3 in the following cases e For Virtex and Virtex E the address line must be between 8 and 12 bits e For Virtex II Virtex II Pro Virtex II Pro X or Spartan 3 the address line must be between 9 and 14 bits e The address lines must be registered with a simple flip flop no resets or enables etc or the ROM output can be registered with enables or sets resets However you cannot use both sets resets and enables The flip flops sets resets can be either synchronous or asynchronous In the case where asynchronous sets resets are used Synplify creates registers with the sets resets and then either AND or OR these registers with the output of the Block RAM RTL Description of a ROM VHDL Example Using Block SelectRAM Following is some incomplete VHDL that demonstrates the above inference rules
178. as a clock it is possible that the data input will be scheduled by the simulator to occur after the clock edge Thus the data will not go through until the next clock edge although it is possible that the intent was to have the data get clocked in before the first clock edge To avoid any such unintended simulation results Xilinx recommends not switching data signals and clock signals simultaneously The UNISIM dual port Block RAM models have a built in collision checking function that monitors reads and writes to each port and reports violations if data is improperly handled for the RAM While this is reported similarly to a timing violation in reality it is warning of a potential functionality issue for the design If you receive any collision warnings from the UNISIM dual port Block RAM models during functional simulation you should investigate the warning to ensure it will not have any negative impact on the end design functionality Generally this is best handled either by trying to re code to avoid such errors or by ensuring that the data written or received from the RAM will be discarded as the actual value cannot be determined and so should not be used Timing Simulation In back annotated timing simulation the introduction of delays can cause the behavior to be different from what is expected Most problems are caused due to timing violations in the design and are reported by the simulator However there are a few other situatio
179. at it overlaps the pin of a symbol the two nets are not connected Square brackets An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild option name design name Braces A list of items from which you must choose one or more lowpwr on off Vertical bar Separates items in a list of choices lowpwr on off Vertical ellipsis Repetitive material that has been omitted IOB IOB n Name QOUT Name CLKIN N Horizontal ellipsis Repetitive material that has allow block block_name Online Document been omitted loci loc2 locn The following conventions are used in this document Convention Meaning or Use Example Cross reference link to a See the section Additional location in the current file or Resources for details Blue text io in another file in the current Refer to Using Synthesis document Tools for details Cross reference link to a See Figure 2 5 in the Virtex II Red text location in another document Platform FPGA User Guide Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest speed files Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 XILINX Preface About This Guide 8 www xilinx com Synthesis and Verification Design Guide 1 800 2
180. ata in register for output for I in 0 to 7 loop tri state cntrl I lt temp tri state I register tri state end loop end if end process end behavioral 124 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Inputs and Outputs lt XILINX e Verilog example VMMIMMMMMMMMPMBlMeQLEMlMVMllMl li ebbldDHB IM M ATTA TATA Inferring output enable register VMIMMEMMHMMMELPPL MP ALULLA AA ILLIA module tri state data_in_p clk tri_state_a tri_state_b data out input 7 0 data in p input clk input tri state a input tri state b output 7 0 data out reg 7 0 data out reg 7 0 data in reg 7 0 data in r reg 7 0 tri state cntrl wire 7 0 temp tri state create duplicate input signal assign temp tri state 0 tri state a amp tri state b assign temp tri state 1 tri state a amp tri state b assign temp tri state 2 tri state a amp tri state b assign temp tri state 3 tri state a amp tri state b assign temp tri state 4 tri state a amp tri state b assign temp tri state 5 tri state a amp tri state b assign temp tri state 6 tri state a amp tri state b assign temp tri state 7 tri state a amp tri state b exemplar attribute temp tri state preserve signal TRUE always G tri state cntrl or data in r begin begin xhdl 1 integer J for J 0
181. ated if they share common inputs When assembling slices Map gives priority to combine logic that is related Doing so results in the best timing performance Unrelated logic shares no connectivity Map will only begin packing unrelated logic into a slice once 99 of the slices are occupied through related logic packing Note that once logic distribution reaches the 99 level through related logic packing this does not mean the device is completely utilized Unrelated logic packing will then begin continuing until all usable LUTs and FFs are occupied Depending on your timing budget increased levels of unrelated logic packing may adversely affect the overall timing performance of your design Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 37 XILINX Chapter 2 Understanding High Density Design Flow Table of Contents Section 1 Errors Section 2 Warnings Section 3 Informational Section 4 Removed Logic Summary Section 5 Removed Logic Section 6 IOB Properties Section 7 RPMs Section 8 Guide Report Section 9 Area Group Summary Section 10 Modular Design Summary Section 1 Errors Section 2 Warnings Section 3 Informational INFO LIT 95 All of the external outputs in this design are using slew rate limited output drivers The delay on speed critical outputs can be dramatically reduced by designating them as fast outputs in the schematic
182. atible Simulation Models 282 Setup for Synopsys Formality and Verplex Conformal FPGA 282 Setup for Synopsys Formality lsssssssssssss eee 282 Setup for Verplex Conformal FPGA sssssssssse ee 283 Conformal FPGA and Synplify Pro Flow 0 00 2000s 283 RILevs Post Synthesis sso restore eb ee t ex YR RR RR EE baa a d a 284 Turning on Verification Mode 0 6c ce eee eee teens 284 Running the DO File in Conformal FPGA 0 0 cece eee eee 285 Using CORE Generator Components with Conformal RTL vs Post Synthesis Verification cr UEEUMNMESRMUE Wala 285 Black Boxing Entire Modules llseeseseeeee nee 285 Post Synthesis vs Post Place and Route 00 00 e eee eee 286 Implementing the Design and Running NetGen 0000 e cee eee eee ee 286 Creating a DO File to Run Conformal Post Synthesis vs Post PAR Verification 287 Running the DO File in Conformal FPGA 6 00 ccc eee 287 Using CORE Generator Components with Conformal Post Synthesis vs Post PAR Verification ikke 4 p eb RE ERES NC ROG ERR A ERN Eee Rhee Rd 287 Black Boxing Entire Modules 1 0 0 ccc cece 288 Known ISSUES i dda eu eeu ee ees ORUIR ad Sa ae eS hes bea ted 288 Formality and FPGA Compiler II Flow 00 0000 e eee ee 289 RTL vs Post Synthesis eeiam ai 6 cece cee ee e en ee nen 289 Synthesizing the Desigrti iserice
183. ation sse 265 Simulating the DCM in Digital Frequency Synthesis Mode Only 265 Debugging Timing Problems usus ee 265 Identifying Timing Violations 6 6 ee 265 Verilog System Timing Tasks cece eee nnn 266 VITAL Timing CHECKS eter Dre petiere re eb eot BR eb En 266 Timing Problem Root Causes 2 0 6 666 cece eens 267 Design Not Constrained i ies oie een heh ere ek bre eg eee Sree 267 Path Not or Improperly Constrained seen 268 Design Does Not Meet Timespec 1 0 6 268 Simulation Clock Does Not Meet Timespec 66 0 c eee cece eee 269 Unaccounted Clock Skew 6 eee eee e eee ee hr 269 Asynchronous Inputs Asynchronous Clock Domains Crossing Out OF Phase tc esrb cst oet ode i atre denied 269 Debugging Tips e ceeitce eiie eC oe CIR HE ESSERE e ee otek 270 Special Considerations for Setup and Hold Violations 0004 271 Zero Hold Time Considerations 0 00 cee ccc eee eee eens 271 Negative Hold Times edet onec pre eat etna not wae URL eol tri dor et id 271 RAM Considerations llle hr hrs 271 Synthesis and Verification Design Guide www xilinx com 15 1 800 255 7778 lt XILINX Hierarchy Considerations esee ceter s20cc rer RR Re ER RE X RR EE cede 272 SWidth Violalions sise eescrpeer ee eeu ee Secr Re dagen ECCE 272 Recovery Violations iier eer eb e tritati siete seed breed cree OP
184. ation Design Guide 1 800 255 7778 Xilinx Internet Websites Technical and Applications Support Hotlines The telephone hotlines give you direct access to Xilinx Application Engineers worldwide You can also e mail or fax your technical questions to the same locations Table 1 1 Technical Support Location North America Telephone 1 800 255 7778 or 1 408 879 5199 Electronic Mail link to http support xilinx com support clearexpress websupport htm Support Hours M T W F 7 00 5 00 PST Th 7 00 4 00 PST United Kingdom 44 870 7350 610 link to http support xilinx com support clearexpress websupport htm M F 8 00 5 30 GMT France 33 1 3463 0100 link to http support xilinx com support clearexpress websupport htm M F 8 00 5 30 GMT Germany 49 180 3 60 60 60 link to http support xilinx com support clearexpress websupport htm M F 8 00 5 30 GMT aSweden 46 8 33 14 00 link to http support xilinx com support clearexpress websupport htm M F 8 00 5 30 GMT 2Netherlands 31 0 800 0233868 link to http support xilinx com support clearexpress websupport htm M F 8 00 5 30 GMT Belgium 432 0 800 90913 link to http support xilinx com support clearexpress websupport htm M F 8 00 5 30 GMT Rest of Europe 44 870 7350 610 lin
185. ator creates an EDIF netlist that contains the functionality of the core This EDIF netlist is read in during NGDBuild the first step in the Xilinx amp Implementation process This is why the contents of the cores are not in the RTL or in the EDIF netlist output from Synplify Please see the CORE Generator Guide for more information Black Boxing Entire Modules Entire modules can be black boxed before running verification You can do this to ignore certain modules during verification or to verify each module separately by black boxing all of the other modules To do this the hierarchy must be maintained by Synplify Pro To instruct Synplify Pro to preserve the hierarchy place the following commands in the HDL code for each module on which the hierarchy should be preserved module name instance name port mapping synthesis syn hier hard xc props KEEP HIERARCHY TRUE Note The KEEP HIERARCHY constraint is not used by Synplify Pro but will instruct the Xilinx implementation tools to preserve the hierarchy as well After instructing the synthesis tool to maintain the hierarchy add the following line to the fpgaR2G do file before the read design commands for each module that is being black boxed Add notranslate model module name Synthesis and Verification Design Guide www xilinx com 285 1 800 255 7778 XILINX Chapter 7 Equivalency Checking Post Synthesis vs Post Place and Route T
186. b1 SINGLE 1 b0 if A D NS S4 else NS 3 end S4 begin MULTI 1 bl CONTIG 1 bl SINGLE 1 b0 if A amp amp B amp amp C NS S5 else NS S4 end S5 s begin MULTI 1 bl CONTIG 1 b0 SINGLE 1 b0 NS S6 end S6 begin MULTI 1 b0 CONTIG 1 bl SINGLE 1 bl if E S S7 else NS S6 end S7 begin MULTI 1 b0 CONTIG 1 bl SINGLE 1 b0 if E S S1 else S S7 end endcase end endmodule Synthesis and Verification Design Guide www xilinx com 139 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan Il 3 Virtex E Il II Pro II Pro X 140 Using Enumerated Type Encoding The recommended encoding style for state machines depends on which synthesis tool you are using Some synthesis tools encode better than others depending on the device architecture and the size of the decode logic You can explicitly declare state vectors or you can allow your synthesis tool to determine the vectors Xilinx recommends that you use enumerated type encoding to specify the states and use the Finite State Machine FSM extraction commands to extract and encode the state machine as well as to perform state minimization and optimization algorithms The enumerated type method of encoding the seven state machine is shown in the following VHDL and Verilog examples The encoding st
187. brary IEEE use IEEE std_logic_1164 all entity ram 16x4s is port o out std_logic_vector 3 downto 0 we in std logic clk in std_logic d in std_logic_vector 3 downto 0 a in std_logic_vector 3 downto 0 end ram 16x4s architecture xilinx of ram 16x4s is component RAM16x1S is generic INIT string port O out std logic D in std logic A3 A2 Al AO WE WCLK in std logic i end component begin UO RAM16x1S generic map INIT gt FFFF port map O gt 0 0 WE gt we AO gt a 0 Al gt a 1 U1 RAM16x1S generic map INIT ABCD port map O gt o 1 WE gt we A0 gt a 0 Al gt a 1 U2 RAM16x1S generic map INIT BCDE port map O gt o 2 WE gt we AO gt a 0 Al gt a 1 U3 RAM16x1S generic map INIT CDEF O gt o 3 WE gt we A0 gt a 0 Al gt a 1 port map end xilinx 0000 in std_logic WCLK gt clk D A2 gt a 2 WCLK gt clk D A2 gt a 2 WCLK gt clk D A2 gt a 2 WCLK gt clk D A2 gt a 2 D gt d 2 a 3 d 3 gt A3 gt A3 gt A3 gt A3 a 3 d 0 d 1 gt a 3 d 2 gt a 3 www xilinx com 1 800 255 7778 Synthesis and Verification Design Guide 167 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E
188. by re encoding the state representations and generating a better logic optimization starting point for the state machines This usually results in one hot encoding However you may override the default on a register by register basis with the SYN_ENCODING directive attribute Available options are One Hot Gray Sequential and Safe In XST FSM encoding is set to Auto by default Available options are Auto One Hot Compact Gray Johnson Sequential and User Note XST only recognizes enumerated encoding if the encoding option is set to User Summary of Encoding Styles In the three previous examples the state machine s possible states are defined by an enumeration type Use the following syntax to define an enumeration type type type_name is enumeration literal enumeration literal After you have defined an enumeration type declare the signal representing the states as the enumeration type as follows 144 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Operators and Generate Modules lt XILINX type STATE TYPE is S1 S2 S3 S4 S5 S6 S7 signal CS NS STATE TYPE The state machine described in the three previous examples has seven states The possible values of the signals CS Current State and NS Next State are S1 S2 56 S7 To select an encoding style for a state machine specify the state vectors Alternatively you can specify the encoding s
189. c blocks such as Block RAM This also reduces the amount of distributed logic Synthesis and Verification Design Guide www xilinx com 67 1 800 255 7778 XILINX Chapter 3 General HDL Coding Styles Using Preset Pin or Clear Pin Xilinx FPGAs consist of CLBs that contain function generators and flip flops Spartan II Spartan 3 Virtex Virtex E Virtex II Virtex II Pro and Virtex II Pro X registers can be configured to have either or both preset and clear pins Register Inference The following VHDL and Verilog designs show how to describe a register with a clock enable and either an asynchronous preset or a clear e VHDL Example FF EXAMPLE VHD Example of Implementing Registers library IEEE use IEEE std logic 1164 a11 use IEEE std logic unsigned all entity ff example is port RESET SET CLOCK ENABLE in STD LOGIC D IN in STD LOGIC VECTOR 7 downto 0 A Q OUT out STD LOGIC VECTOR 7 downto 0 B Q OUT out STD LOGIC VECTOR 7 downto 0 C Q OUT out STD LOGIC VECTOR 7 downto 0 0 0 D Q OUT out STD LOGIC VECTOR 7 downto E Q OUT out STD LOGIC VECTOR 7 downto nd ff example architecture BEHAV of ff example is begin D flip flop FF process CLOCK begin if CLOCK event and CLOCK 1 then A Q OUT lt D IN end if end process
190. c simprims SXILINX verilog src glbl v libext v Mupdat RN testfixture v time sim v The R option automatically simulates the executable after compilation Finally the Mlib compiled lib dir option provides VCS with a central place to look for the descriptor information before it compiles a module and a central place to get the object files when it links together the executable The Mupdate option enables incremental compilation Modules are recompiled for any of the following reasons 1 Targetofa hierarchical reference has changed 2 Acompile time constant such as a parameter has changed 3 Ports of a module instantiated in the module have changed 4 Module inlining For example a group of module definitions merging internally in VCS into a larger module definition which leads to faster simulation These affected modules are again recompiled This is done only once For more information on how to back annotate the SDF file for timing simulation go to Answer Record 6349 on the Xilinx support website at http support xilinx com Synthesis and Verification Design Guide www xilinx com 277 1 800 255 7778 XILINX Chapter 6 Verifying Your Design ModelSim Vlog There are two methods to run simulation with ModelSim Vlog 1 Using library source files with compile time options 2 Using shared precompiled libraries Using Library Source Files With Compile Time Options Depending on the ma
191. chniques apply the same way to all these devices Unless otherwise stated the features and examples in this chapter apply to all Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X Spartan II and Spartan 3 devices For details specific to Virtex II Pro and Virtex II Pro X see the Virtex II Pro Platform FPGA User Guide Synthesis and Verification Design Guide www xilinx com 75 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X This chapter covers the following FPGA HDL coding features e Advanced clock management e On chip RAM and ROM e IEEE 1149 1 compatible boundary scan logic support e Flexible I O with Adjustable Slew rate Control and Pull up Pull down Resistors e Various drive strength e Various I O standards e Dedicated high speed carry propagation circuit You can use these device characteristics to improve resource utilization and enhance the speed of critical paths in your HDL designs The examples in this chapter are provided to help you incorporate these system features into your HDL designs Instantiating Components Xilinx provides a set of libraries that your Synthesis tool can infer from your HDL code description However architecture specific and customized components must be explicitly instantiated as components in your design Instantiating FPGA Primitives Architecture specific compone
192. ck block is signal CLK CLK int CLK dcm std logic attribute CLKIN PERIOD string attribute CLKIN PERIOD of U2 label is 10 component IBUFG port I in std logic O out std logic end component component BUFG port I in std logie O out std logic end component 96 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Using Advanced Clock Management Z XILINX component DCM is port CLKFB in std_logic CLKIN in std_logic DSSEN in std_logic PSCLK in std_logic PSEN in std_logic PSINCDEC in std_logic RST in std_logic CLKO out std_logic CLK90 out std logic CLK180 out std logic CLK270 out std logic CLK2X out std logic CLK2X180 out std logic CLKDV out std logic CLKFX out std_logic CLKFX180 out std_logic LOCKED out std_logic PSDONE out std_logic STATUS out std_logic_vector 7 downto 0 i end component signal logic 0 std logic begin logic 0 lt 0 U1 IBUFG port map I gt CLK PAD O gt CLK int U2 DCM port map CLKFB gt CLK CLKIN gt CLK_int DSSEN gt logic O0 PSCLK gt logic O0 PSEN gt logic O0 PSINCDEC gt logic O0 RST gt RST DLL CLKO gt CLK_dcm LOCKED gt LOCKED U3 BUFG port map I gt CLK dcm O gt CLK CLK out CLK end end architecture STRUCT Synthesis and Verificatio
193. ck box for components that do not have a Verilog functional description Synthesis and Verification Design Guide www xilinx com 77 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Example of Black Box Directive and Empty Module Declaration module r256x16s addr di clk we en rst do input 7 0 addr input 15 0 di input clk input we input en input rst output 15 0 do endmodule module top addrp dip clkp wep enp rstp dop input 7 0 addrp input 15 0 dip input clkp input wep input enp input rstp output 15 0 dop r256x16s UO addr addrp di dip clk clkp we wep en enp rst rstp do dop endmodule Using Boundary Scan JTAG 1149 1 Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X Spartan II and Spartan 3 FPGAs contain boundary scan facilities that are compatible with IEEE Standard 1149 1 You can access the built in boundary scan logic between power up and the start of configuration Ina configured Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X Spartan II and Spartan 3 device basic boundary scan operations are always available BSCAN_VIRTEX BSCAN_VIRTEX2 and BSCAN_SPARTAN2 are instantiated only if you want to create internal boundary scan chains in a Virtex Virtex E Virtex II Virtex II Pro
194. clock design that is not multi cycle e FROM TO This constraint works well with more complicated timing paths Designs that are multi cycle or have paths that cross clock domains are better handled this way For I O however you must add subtract the delay of the global buffer Note that using an OFFSET before for input and an OFFSET after for output is supported without the need to specify a period so you can use the advantages of both For detailed information on constraining your design consult any or all of the following resources e Constraints Guide The Constraints Guide lists all of the Xilinx constraints along with explanations and guides to their usage The Timing Constraint Strategies chapter in the Constraints Guide gives detailed information on the best ways to constrain the timing on your design to get optimum results Synthesis and Verification Design Guide www xilinx com 267 1 800 255 7778 XILINX 268 Chapter 6 Verifying Your Design e Timing and Constraints area on the Xilinx home page The Timing and Constraints area on the Xilinx home page provides a presentation of Basic Timing Concepts and Syntax Examples This presentation gives an overview of how to constrain your design and has examples of how to code various constraints e The Timing Improvement Wizard The Timing Improvement Wizard provides suggestions for improving failing paths and can help you find answers to your specific timing q
195. clock with ps out reset input clock in output clock out output clock with ps out output reset wire low wirehigh wire dcmO0 locked wire dcml locked wire reset wire clk0 wire clk1 Synthesis and Verification Design Guide www xilinx com 109 1 800 255 7778 SZ XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X assign low 1 b0 assign high 1 b1 assign reset dcm0 locked amp doml locked IBUFG CLOCK_IN I clock in O clock DCM DCMO CLKFB clock out CLKIN clock DSSEN low PSCLK low PSEN low PSINCDEC low RST low LKO c1k0 LK90 LK180 LK270 LK2X LK2X180 LKDV LKFX LKFX180 CKED dcm0_locked DONE STATUS lv cb m z Ie dry uE Ij o tg Et OQ Y OY C 0 E n BUFG CLK BUFO O clock out I clk0 synthesis attribute DLL FREQUENCY MODE of DCMO is LOW synthesis attribute DUTY CYCLE CORRECTION of DCMO is TRUE synthesis attribute STARTUP WAIT of DCMO is TRUE synthesis attribute DFS FREQUENCY MODE of DCMO is LOW synthesis attribute CLKFX DIVIDE of DCMO is 1 synthesis attribute CLKFX MULTIPLY of DCMO is 1 synthesis attribute CLK FEEDBACK of DCMO is 1x synthesis attribute CLKO
196. code See the following example module block ram ex CLK WE ADDR DIN DOUT input CLK WE input 8 0 ADDR input 7 0 DIN output 7 0 DOUT RAMBA4 S8 UO WE WE EN 1 b1 RST 1 b0 CLK CLK ADDR ADDR DI DIN DO DOUT synthesis attribute INIT 00 of UO is lIF1EID1C1B1A191817161514131211100F0E0D0C0B0A0980706050403020100 endmodule Instantiating Block SelectRAM in Virtex II II Pro ll Pro X and Spartan 3 Virtex II TI Pro II Pro X and Spartan 3 devices provide 16384 bit data memory and 2048 bit parity memory totaling to 18Mbit memory in each Block SelectRAM These RAMBI16 Sn single port and RAMB16 Sm Sn dual port blocks are configurable to various width and depth The Virtex II Platform FPGA User Guide provides VHDL and Verilog templates for Virtex II II Pro II Pro X and Spartan 3 Block SelectRAM instantiations You can also refer to the Libraries Guide for a more detailed component and attribute 160 description www xilinx com 1 8 00 255 7778 Synthesis and Verification Design Guide Implementing Memory lt XILINX Inferring Block SelectRAM The following coding examples provide VHDL and Verilog coding styles for FPGA Compiler II LeonardoSpectrum Synplify and XST For Virtex Virtex E and Spartan II devices the RAMB4_Sn or RAMB4_Sm_Sn is inferred For Virtex II II Pro II P
197. com 131 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X e VHDL example LVDS 33 IO VHD Version 1 0 Example of a behavioral description of differential signal I O standard using LeonardoSpectrum attribute HDL Synthesis Design Guide for FPGAs library IEEE use IEEE std_logic_1164 all us xemplar exemplar 1164 all entity LVDS 33 IO is port CLK p CLK n DATA p DATA n Tin p Tin n in STD LOGIC datain2 p datain2 n in STD LOGIC ODATA p ODATA n out STD LOGIC Qp On out STD LOGIC end LVDS 33 IO architecture BEHAV of LVDS 33 IO is component IBUFDS is port I in STD LOGIC IB in STD LOGIC O out STD LOGIC end component component OBUFDS is port I in STD LOGIC O out STD LOGIC OB out STD LOGIC end component component OBUFTDS is port I in STD LOGIC T in STD LOGIC O out STD LOGIC OB out STD LOGIC end component component IBUFGDS is port I in STD LOGIC IB in STD LOGIC O out STD LOGIC end component component BUFG is port I in STD LOGIC O out STD LOGIC end component 132 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Inputs and Outputs 2 XILINX signal datain2 std_logic signal odata_out std_logic
198. corresponding properties and not just a code snippet This allows the output file to be referenced from the HDL Editor There is no UCF output file since the necessary attributes are embedded inside the HDL file Launch the Architecture Wizard from Project Navigator From the File dropdown menu select Project New Source Architecture Wizard menu item Synthesis and Verification Design Guide www xilinx com 27 1 800 255 7778 XILINX Chapter 2 Understanding High Density Design Flow Clocking Wizard The Clocking Wizard component of the Architecture Wizard provides the following functions e Specifies Setup information e Lets you view the DCM component specify attributes generate corresponding components and signals and execute DRC checks e Displays up to eight clock buffers e Sets up the Feedback Path information e Sets up the Clock Frequency Generator information and execute DRC checks e Lets you view and edit component attributes e Lets you view and edit component constraints e Automatically places one component in the XAW file e Saves component settings in a VHDL file e Saves component settings in a Verilog file RocketlO Wizard The RocketIO Wizard component of the Architecture Wizard provides the following functions e Provides the ability to specify RocketIO type e Provides the ability to define Channel Bonding options e Provides the ability to specify General Transmitter Setti
199. cript on each CORE Generator module in the design Known Issues For known issues with verifying Xilinx designs with Formality please search the Answers Database on the Xilinx support website at http support xilinx com Search using the following keyword string enter exactly as shown Synopsys AND Formality Conformal FPGA and FPGA Compiler II Flow 294 When using FPGA Compiler II and targeting a Xilinx FPGA Conformal FPGA can be used to verify that the golden RTL design and the post synthesis or post place and route netlists are logically equivalent Figure 7 3 describes the FPGA Compiler II Conformal FPGA flows for equivalency checking Post Synthesis netlist Post PAR neti Conformal FPGA Post netlist Equivalence Checker Lv FPGA Netlist Compiler II db Synopsys Design Constraints Golden netlist X10002 Figure 7 3 FPGA Compiler II Conformal FPGA Flow for Equivalency Checking www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Conformal FPGA and FPGA Compiler II Flow XILINX RTL vs Post Synthesis The first transformation of the RTL code is synthesis The synthesis tool will optimize the code and convert it from RTL to a post synthesis EDIF netlist Performing an equivalence check between the RTL and post synthesis netlist will verify that the functionality of the design has not been changed by the transformation
200. d data path delays Refer to your synthesis vendor s documentation for command syntax The timing report is based on the logic level delays from the cell libraries and estimated wire load models for your design This report is an estimate of how close you are to your timing goals however it is not the actual timing for your design An accurate report of your design s timing is only available after your design is placed and routed This timing report does not include information on any instantiated components such as CORE Generator modules EDIF files or other components that are not recognized by your synthesis tool during compilation Determining Actual Device Utilization and Pre routed Performance To determine if your design fits the specified device you must map it with the Xilinx Map program The generated report file design name mrp contains the implemented device utilization information The report file can be read by double clicking on Map Report in the Project Navigator Process Window You can run the Map program from Project Navigator or from the command line Using Project Navigator to Map Your Design Use the following steps to map your design using Project Navigator Note For more information on using the Project Navigator see Project Navigator Online Help 1 After opening Project Navigator and creating your project go to the Process Window and click the symbol in front of Implement Design 2 Torun the Xilinx
201. d examples included in this chapter are not intended to teach you every aspect of VHDL or Verilog but they should help you develop an efficient coding style Naming and Labeling Styles Because HDL designs are often created by design teams Xilinx recommends that you agree on a style for your code at the beginning of your project An established coding style allows you to read and understand code written by your fellow team members Also inefficient coding styles can adversely impact synthesis and simulation which can result in slow circuits Additionally because portions of existing HDL designs are often used in new designs you should follow coding standards that are understood by the majority of HDL designers This section of the manual provides a list of suggested coding styles that you should establish before you begin your designs Using Xilinx Naming Conventions Use the Xilinx naming conventions listed in this section for naming signals variables and instances that are translated into nets buses and symbols Note Most synthesis tools convert illegal characters to legal ones Synthesis and Verification Design Guide www xilinx com 45 1 800 255 7778 2 XILINX Chapter 3 General HDL Coding Styles e User defined names can contain A Z a z lt and gt A is also valid however it is not recommended because it is used as a hierarchy separator e Names must contain at least one non numeric character
202. d inst Note To use this example in Synplify you need to add the Xilinx primitive library and remove the component declarations as noted above The Virtex library contains primitives of Virtex and Spartan II architectures Replace virtex with the appropriate device family if you are targeting other Xilinx FPGA architectures If you are designing with a Virtex E device use the virtexe library If you are designing with a Virtex II Virtex II Pro Virtex II Pro X and Spartan 3 device use the virtex2 library Verilog example module flops dl ce clk ql rst input dl input ce input clk output ql input rst FDCE ul D dl CE ce sC elk CLR rst Q ql endmodule CORE Generator Modules The CORE Generator allows you to generate complex ready to use functions such as FIFO Filter Divider RAM and ROM CORE Generator generates an EDIF netlist to describe the functionality and a component instantiation template for HDL instantiation For more information on the use and functions created by the CORE Generator see the CORE Generator Guide In VHDL you can declare the component and port map as shown in the Instantiating FPGA Primitives section above Synthesis tools assume a black box for components that do not have a VHDL functional description In Verilog an empty module must be declared to get port directionality Synthesis tools assume a bla
203. d track and generally not cause a problem Even if you are not using the same input standard the amount of delay variance generally does not cause hold time failures because the delay variance is small compared to the amount of input delay The delay variance is calculated in both static timing analysis and simulation so you should see proper setup time values during static timing analysis as well as during simulation Viewer Considerations Depending on which simulator you use the waveform viewer might not depict the delay timing the way you expect to see it Some simulators including the current version of MTI ModelSim combine interconnect delays either interconnect or port delays with the input pins of the component delays when you view the waveform on the waveform viewer In terms of the simulation the results are correct but in terms of what you see in the waveform viewer this may not always be what you expect to see 264 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Debugging Timing Problems Z XILINX Since interconnect delays are combined when you look at a pin using the MTI ModelSim viewer you do not see the transition as it happens on the pin In terms of functionality the simulation acts properly and this is not very relevant but when attempting to calculate clock delay the interconnect delays before the clock pin must be taken into account if the simulator you are using combines thes
204. de The flow is shown in the following figure 1 VHDL Verliog with PPC and GT Instantiations 2 Install Smart Models If necessary 3 HDL Simulator with SWIFT Interface Support X9821 Figure 5 1 HDL Simulation Flow for Virtex ll Pro Devices 192 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 SmartModels SmartModels lt XILINX The Xilinx Virtex II Pro simulation flow uses SmartModels for simulating the IBM PowerPC microprocessor and RocketIO SmartModels are simulator independent models that are derived from the actual design and are therefore accurate evaluation models To simulate these models you must us a simulator that supports the SWIFT interface Synopsys Logic Modeling uses the SWIFT interface to deliver models SWIFT is a simulator and platform independent API developed by Synopsys and adopted by all major simulator vendors including Synopsys Cadence Mentor Graphics Model Technology and others as a way of linking simulation models to design tools When running a back annotated simulation the precompiled SmartModels support gate level pin to pin and back annotation timing Gate level timing distributes the delays throughout the design and all internal paths are accurately distributed Multiple timing versions can be provided for different speed parts Pin to pin timing is less accurate but is faster since only a few top leve
205. dows e IBM CoreConnect Software Details are available at http www xilinx com ipcenter processor central register coreconnect htm e HDL Simulator that can simulate both VHDL Verilog and SWIFT interface Installing SmartModels from Xilinx amp Implementation Tools The SmartModels are installed with the Xilinx implementation tools but they are not immediately ready for use There are two ways to use them In method one use the precompiled models The only additional setup necessary for this method is to set the LMC HOME environment variable Use this method if your design does not use any other vendors Smart Models In method two install the PPC405 and GT SmartModel with additional SmartModels incorporated in the design Compile all SmartModels into a common library for the simulator to use Method One Windows For Windows the SmartModels are precompiled in the following directory Xilinx smartmodel nt installed_nt To use the precompiled SmartModels set the following variable LMC_HOME C Xilinx smartmodel nt installed_nt Solaris For Solaris the SmartModels are precompiled in the following directory Xilinx smartmodel sol installed_sol To use the precompiled SmartModels set the following variables setenv LMC HOME SXILINX smartmodel sol installed sol setenv LMC CONFIG S LMC HOME data solaris lmc setenv LD LIBRARY PATH LMC HOME lib sun4Solaris lib LD LIBRARY PATH 194 www x
206. e 4 cd verification directory 5 lec dofile dofile name do Synthesis and Verification Design Guide www xilinx com 287 1 800 255 7778 XILINX Chapter 7 Equivalency Checking Using CORE Generator Components with Conformal Post Synthesis vs Post PAR Verification When using CORE Generator components the contents of the cores are read in during NGDBuild the first stage of the Xilinx implementation process The cores are then implemented with the rest of the design and the post PAR netlist will contain the contents of the cores The post synthesis netlist only contains black box instantiations of the cores Xilinx provides a Perl script core2formal pl that creates a pre implementation Verilog representation of the cores which can be read in as part of the golden reference design Usage gt xilperl SXILINX verilog bin platform core2formal pl vendor family coregen module e For Conformal FPGA the vendor option must be verplex e The family option can be virtex virtexe virtex2 virtex2p spartan2 spartan2e or spartan3 The Perl script runs the following commands ngdbuild p family coregen module edn netgen ecn conformal coregen module ngd coregen module for v The output from NetGen is a pre implementation Verilog representation of the core that is read in with the post synthesis netlist as part of the golden reference design You must run the core2formal p1 script on each CORE Generator module in the de
207. e ASYNC_REG is a constraint in the Xilinx software that helps identify asynchronous registers in the design and disable X propagation for those particular registers If the attribute ASYNC_REG is attached to a register in the front end design by either an attribute in HDL code or by a constraint in the UCF during timing simulation those registers retain the previous value and do not output an X to simulation A timing violation error should still occur so use caution as the new value may have been clocked in very well The ASYNC REG attribute is only applicable to CLB and IOB registers and latches If clocking in asynchronous data cannot be avoided Xilinx suggests that you only do so on IOB or CLB registers Clocking in asynchronous signals to RAM SRL or other synchronous elements has less deterministic results and therefore should be avoided Refer to the Constraints Guide for more information on using the ASYNC REG constraint Xilinx highly suggests to first properly synchronize any asynchronous signal in a register latch or FIFO before writing to a RAM SRL or any other synchronous element Using Global Switches Xilinx generally suggests that you use the ASYNC_REG to control X propagation However there is an option to use use global switches to disable X propagation for all components in the simulation Verilog For Verilog use the no_notifier switch from within your simulator When a timing violation occurs the s
208. e rule is no longer valid and can interfere with optimization Check with your synthesis vendor for the current recommendations for preferred module size As a last resort use the grouping commands of your synthesizer if available The size and content Synthesis and Verification Design Guide www xilinx com 21 1 800 255 7778 XILINX Chapter 1 Introduction of the modules influence synthesis results and design implementation This manual describes how to create effective design hierarchy Specifying Speed Requirements To meet timing requirements you should understand how to set timing constraints in both the synthesis and placement routing tools For more information see Setting Constraints in Chapter 2 Xilinx Internet Websites You can get product information and product support from the Xilinx internet websites Both sites are described in the following sections 22 Xilinx World Wide Web Site You can reach the Xilinx website at http www xilinx com The following features can be accessed from the Xilinx website Products You can find information about new Xilinx products that are being offered as well as previously announced Xilinx products Service and Support You can jump to the Xilinx technical support site by choosing Service and Support Xpresso Cafe You can purchase Xilinx software hardware and software tool education classes through Xilinx and Xilinx distributors
209. e following 1 Select the File Run Script menu item from the LeonardoSpectrum graphical user interface 2 Type in the Level 3 GUI command line source script file tcl 30 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Synthesizing and Optimizing your Design lt XILINX 3 Type in the UNIX DOS prompt with the EXEMPLAR environment path set up spectrum file script file tcl 4 Type spectrumat the UNIX DOS prompt This puts you in a TCL prompt Then at the TCL prompt type source script file tcl LeonardoSpectrum TCL Examples You can enter the following TCL commands in LeonardoSpectrum e To set the part type enter the following set part v50ecs144 e To read the HDL files enter the following read macrol vhd macro2 vhd top level ohd e To set assign buffers enter the following PAD IBUF LVDS data 7 0 e To optimize while preserving hierarchy enter the following optimize ta xcve hier preserve e To write out the EDIF file enter the following auto write M1 ff_example edf Synplify You can run the following TCL script from Synplify by doing one of the following 1 Use the File gt Run TCL Script menu item from the GUI 2 Type synplify batch script_file tcl at a UNIX DOS command prompt Synplify TCL Example You can enter the following TCL commands in Synplify e To start a new project enter the following project new e To set device options enter t
210. e information e LeonardoSpectrum Use the read coregen TCL command line option Please refer to Answer Record 13159 for more information e Synplify Pro EDIF is treated as just another source format but when reading in EDIF you must specify the top level VHDL Verilog in your project Support for reading in EDIF is included in Symplify Pro version 7 3 Please see the Symplify documentation for more information Setting Constraints You can define timing specifications for your design in the User Constraints File UCF You can use the Xilinx Constraints Editor which provides a graphical user interface allowing for easy constraints specification You can also enter constraints directly into the UCF file Both methods are described in the following sections Most synthesis tools support an easy to use Constraints Editor interface for entering constraints in your design Using the UCF File The UCF gives you tight control of the overall specifications by giving you access to more types of constraints the ability to define precise timing paths and the ability to prioritize signal constraints Furthermore you can group signals together to simplify timing specifications Some synthesis tools translate certain synthesis constraints to Xilinx implementation constraints The translated constraints are placed in the NCF EDIF file NGC file for XST For more information on timing specifications in the UCF file refer to the Constra
211. e information on this option refer to the Understanding the Global Reset and Tristate for Simulation section Global Set Reset Port Name The Global Set Reset Port Name property allows you to specify a port name to match the port name you used in the front end if a ROCBUF component was used Generate Testbench File VHDL Only The Generate Testbench Template File property creates a test bench file The file has a tvhd extension and displays in the Sources in Project window Generate Testfixture File Verilog Only The Generate Testfixture Template File property generates a test fixture file The file has a tv extension and it is a ready to use template test fixture that the Verilog file bases on the input design file The following options appear if the Advanced Process Settings are enabled in Project Navigator Rename Top Level Entity To VHDL Only This option allows you to change the name of the top level entity in the structural VHDL file By default the output files inherit the top entity name from the input design file Rename Top Level Module to Verilog only www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Running NetGen Z XILINX This option allows you to change the name of the top level module in the structural Verilog file By default the output files inherit the top module name from the input design file Rename Top Level Architecture To VHDL Only This option a
212. e and by incorporating FPGA system features Most of these techniques are described in more detail in this manual Modifying Your Code You can improve design performance with the following design modifications e Reduce levels of logic to improve timing e Redefine hierarchical boundaries to help the compiler optimize design logic e Pipeline e Logic replication e Use of CORE Generator modules e Resource sharing e Restructure logic Using FPGA System Features After correcting any coding style problems use any of the following FPGA system features in your design to improve resource utilization and to enhance the speed of critical paths Each device family has a unique set of system features Go to the Xilinx support website http support xilinx com and refrence the Data Sheet for the system features available for the device you are targeting e Use clock enables e In Virtex family components modify large multiplexers to use tristate buffers e Use one hot encoding for large or complex state machines e Use I O registers when applicable e In Virtex families use dedicated shift registers e In Virtex II families use dedicated multipliers Using Xilinx specific Features of Your Synthesis Tool Most synthesis tools have special options for the Xilinx specific features listed in the previous section Refer to your synthesis tool white papers application notes documentation and online help for detailed infor
213. e delay is type my type is array 0 to cycle 1 of std logic vector width 1 downto 0 signal int sig my type begin main process clk begin if clk event and clk 1 then int sig input amp int sig 0 to cycle 2 end if end process main output lt int sig cycle 1 end behav Inferring SRL16 in Verilog Use the following coding example for FPGA Compiler II LeonardoSpectrum Synplify and XST e FPGA Compiler II LeonardoSpectrum Synplify and XST Verilog Example SRL This design infer 3 SRL16 with 4 pipeline delay module srle_exampl clk enable data_in result parameter cycle 4 parameter width 3 input clk enable input O width data_in output 0 width result reg 0 width 1 shift cycle 1 0 integer i 182 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Shift Registers Virtex E II II Pro Il Pro X and Spartan II 3 XILINX always posedge clk begin if enable 1 begin for i cycle 1 i gt 0 i i 1 shift i shift i 1 shift 0 data_in end end assign result shift cycle 1 endmodule Inferring Dynamic SRL16 in VHDL e LeonardoSpectrum Synplify and XST library IEEE use IEEE std_logic_1164 all entity srltest is port inData std logic vector 7 downto 0 clk en in std logic outStage in integer range 3 downto 0 outData out std
214. e following sections to create code that simulates the same way before and after synthesis 56 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Coding for Synthesis lt XILINX Omit the Wait for XX ns Statement Omit the Do not use the Wait for XX ns statement in your code XX specifies the number of nanoseconds that must pass before a condition is executed This statement does not synthesize to a component In designs that include this statement the functionality of the simulated design does not match the functionality of the synthesized design VHDL and Verilog examples of the Wait for XX ns statement are as follows VHDL wait for XX ns Verilog XX After XX ns or Delay Statement Do not use the After XX ns statement in your VHDL code or the Delay assignment in your Verilog code Examples of these statements are as follows VHDL Q lt 0 after XX ns Verilog assign XX Q 0 XX specifies the number of nanoseconds that must pass before a condition is executed This statement is usually ignored by the synthesis tool In this case the functionality of the simulated design does not match the functionality of the synthesized design Omit Initial Values Do not assign signals and variables initial values because initial values are ignored by most synthesis tools The functionality of the simulated design may not match the functionality of the synthesized design For example do not us
215. e initialization statements like the following VHDL and Verilog statements VHDL signal sum integer 0 Verilog initial sum 1 b0 Order and Group Arithmetic Functions Synthesis and Verification Design Guide The ordering and grouping of arithmetic functions can influence design performance For example the following two VHDL statements are not necessarily equivalent ADD lt Al A2 A3 A4 ADD lt Al A2 A3 A4 For Verilog the following two statements are not necessarily equivalent ADD Al A2 A3 A4 ADD Al A2 A3 A4 The first statement cascades three adders in series The second statement creates two adders in parallel Al A2 and A3 A4 In the second statement the two additions are www xilinx com 57 1 800 255 7778 X XILINX Chapter 3 General HDL Coding Styles evaluated in parallel and the results are combined with a third adder RTL simulation results are the same for both statements however the second statement results in a faster circuit after synthesis depending on the bit width of the input signals Although the second statement generally results in a faster circuit in some cases you may want to use the first statement For example if the A4 signal reaches the adder later than the other signals the first statement produces a faster implementation because the cascaded structure creates fewer logic levels for A4 This structure allows A4 to catch up to
216. e interconnect delays with component delays Please refer to Answer Record 11067 on the Xilinx support website at http support xilinx com for the most current information on this issue Attributes for Simulation and Implementation Ensure that the same attributes are passed for simulation and implementation During implementation of the design DLL DCM attributes may be passed either by the synthesis tool via a synthesis attribute generic or defparam declaration or within the UCF file For RTL simulation of the UNISIM models the simulation attributes must be passed via a generic if you are using VHDL or a defparam if you are using Verilog If you do not use the default setting for the DLL DCM and you use a UCF file or a synthesis attribute to pass the attribute values you must ensure that the attributes for RTL simulation are the same as those used for implementation If not there may be differences between RTL simulation and the actual device implementation The best way to ensure the attributes passed to implementation are the same as those used for simulation is to use the generic mapping method VHDL or defparam passing Verilog if your synthesis tool supports these methods for passing functional attributes Simulating the DCM in Digital Frequency Synthesis Mode Only To simulate the DCM in Digital Frequency Synthesis Mode only set the CLK_FEEDBACK attribute to NONE and leave the CLKFB unconnected The CLKFX and CLKFX180 are ge
217. e is driven by an X ROC cell The ROC pulse width of the X ROC component can be controlled using the rpw switch for NetGen Synthesis and Verification Design Guide www xilinx com 233 1 800 255 7778 XILINX Chapter 6 Verifying Your Design Using VHDL ROCBUF Cell A second method of emulating GSR in the functional simulation is to use the ROCBUF This component creates a buffer for the global set reset signal and provides an input port on the buffer to drive the global set reset line This port must be declared in the entity list and driven in RTL simulation This method is applicable when system level issues make your design s initialization synchronous to an off chip event In this case you provide a pulse that initializes your design at the start of simulation time and you possibly provide further pulses as simulation time progresses perhaps to simulate cycling power to the device During the place and route process this port is removed it is not implemented on the chip ROCBUF does not by default reappear in the post routed netlist unless the gp switch is used during NetGen netlisting The nets driven by a ROCBUF must be an active High set reset The following example illustrates how to use the ROCBUF in your designs library IEEE use IEEE std_logic_1164 all use IEEE std logic unsigned all library UNISIM use UNISIM all entity EX ROCBUF is port CLOCK ENABLE SRP i
218. e is the latch code example modified to infer a D register e VHDL Example D_REGISTER VHD Changing Latch into a D Register library IEEE use IEEE std_logic_1164 all entity d_register is port CLK DATA in STD_LOGIC Q out STD_LOGIC i end d_register architecture BEHAV of d_register is begin MY_D_REG process CLK DATA begin if CLK event and CLK 1 then Q lt DATA end if end process End MY D REG end BEHAV e Verilog Example Changing Latch into a D Register D REGISTER V Xi module d_register CLK DATA Q input CLK input DATA output Q reg Q always posedge CLK begin My_D_Reg Q lt DATA end endmodule With some synthesis tools you can determine the number of latches that are implemented in your design Check the manuals that came with your software for information on determining the number of latches in your design You should convert all If statements without corresponding Else statements and without a clock edge to registers Use the recommended register coding styles in the synthesis tool documentation to complete this conversion 64 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Coding for Synthesis XILINX Resource Sharing Resource sharing is an optimization technique that uses a single functional block such as an adder or comparator to implement several op
219. ecture Specific Coding Styles for Spartan II 3 Virtex E II II Pro II Pro X includes coding techniques to help you use the latest Xilinx devices e Chapter 5 Virtex II Pro Considerations describes the special considerations encountered when simulating designs for Virtex II Pro and Virtex II Pro X FPGAs e Chapter 6 Verifying Your Design describes simulation methods for verifying the function and timing of your designs e Chapter 7 Equivalency Checking describes how to use third party tools to perform formal verification on your designs Synthesis and Verification Design Guide www xilinx com 5 1 800 255 7778 XILINX Preface About This Guide Additional Resources For additional information go to http support xilinx com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Description URL Tutorials Tutorials covering Xilinx design flows from design entry to verification and debugging http support xilinx com support techsup tutorials index htm Answer Browser Database of Xilinx solution records http support xilinx com xInx xil ans browserjsp Application Notes Descriptions of device specific design techniques and approaches http support xilinx com apps appsweb htm Data Sheets Pages from The Programmable Logic Data Book which co
220. edance state during configuration mode with the dedicated GTS global output tristate enable net All general purpose outputs are affected whether they are regular tristate or bi directional outputs during normal operation This ensures that the outputs do not erroneously drive other devices as the FPGA is being configured In simulation the GTS signal is usually not driven The circuitry for driving GTS is available in the back end simulation and can be optionally added for the front end simulation but the GTS pulse width is set to 0 by default For more information about controlling the GTS pulse or inserting the circuitry to pulse GTS in the front end simulation see the Simulating VHDL and Simulating Verilog sections www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulating VHDL Z XILINX The following figure shows how the global GTS and GSR signals are used in the FPGA l Os Used for Initialization User Programmable Latch Register Global Tri State GTS Initialization User Tri State Controller Enable loss GTS User io Programmable User Output Logic Pad Resources A Ues KH Output Buffer bl Global obal User Input eae Input Buffer General Purpose e962 Figure 6 2 Built in FPGA Initialization Circuitry Simulating VHDL Emulating the Global GSR pulse in VHDL in Functional Simulation Many HDL designs targeted for Xilinx FPGAs have a user reset that initializes a
221. egister If synchronization is not possible you can use the ASYNC_REG constraint to work around the problem See Using the ASYNC_REG Attribute in this chapter Out of Phase Data Paths Data paths can be clock controlled at the same frequency but nevertheless can have setup or hold violations because the clocks are out of phase Even if the clock frequencies are a derivative of each other improper phase alignment could cause setup violations Check the source code and the Timing Analyzer report to see if the path in question crosses another path with an out of phase clock Debugging Tips When you are faced with a timing violation the following questions may give valuable clues as to what went wrong Was the clock path analyzed by TRACE or Timing Analyzer Did TRACE or Timing Analyzer report that the data path can run at speeds being clocked in simulation Is clock skew being accounted for in this path delay Does subtracting the clock path delay from the data path delay still allow clocking speeds Will slowing down the clock speeds eliminate the setup hold time violations www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Debugging Timing Problems lt XILINX e Does this data path cross clock boundaries from one clock domain to another Are the clocks synchronous to each other Is there appreciable clock skew or phase difference between these clocks e If this path is an input path to t
222. el is generic data_width integer 8 address_width integer 8 mem_depth integer 256 port data in std logic vector data width 1 downto 0 address in std logic vector address width 1 downto 0 en we clk in std logic q out std logic vector data width 1 downto 0 end ram examplel architecture rtl of ram examplel is type mem array is array mem depth 1 downto 0 of std logic vector data width 1 downto 0 signal mem mem array attribute syn ramstyle string attribute syn ramstyle of mem signal is block ram signal raddress std logic vector address width 1 downto 0 begin 10 process clk begin if clk 1 and clk event then if we 1 then mem CONV_INTEGER address lt data q lt mem CONV_INTEGER address end if end if end process end rtl e Verilog example for Synplify 7 0 In Synplify 7 0 the same conditions exist as with the previous release except that there is a new coding style for Block Select RAM inference in Verilog The following is a Synplify 7 0 VHDL example module sp ram din addr we clk dout parameter data width 16 address width 10 mem elements 600 input data width 1 0 din input address width 1 0 addr input rst we clk output data width 1 0 dout reg data width 1 0 mem mem elements 1 0 synthesis syn ramstyle block ram reg data width 1 0 dout 164 www x
223. elining You can use pipelining to dramatically improve device performance Pipelining increases performance by restructuring long data paths with several levels of logic and breaking it up over multiple clock cycles This method allows a faster clock cycle and as a result an increased data throughput at the expense of added data latency Because the Xilinx FPGA devices are register rich this is usually an advantageous structure for FPGA designs because the pipeline is created at no cost in terms of device resources Because data is now on a multi cycle path special considerations must be used for the rest of your design to account for the added path latency You must also be careful when defining timing specifications for these paths Some synthesis tools have limited capability for constraining multi cycle paths or translating these constraints to Xilinx implementation constraints Check your synthesis tool documentation for information on multi cycle paths If your tool cannot translate the constraint but can synthesize to a multi cycle path you can add the constraint to the UCF file Before Pipelining In the following example the clock speed is limited by the clock to out time of the source flip flop the logic delay through four levels of logic the routing associated with the four function generators and the setup time of the destination register pra Slow_Clock X8339 Figure 4 7 Before Pipelining After Pipelini
224. enter timing constraints through your synthesis tool the Xilinx Constraints Editor or by editing the User Constraint File UCF For detailed information on entering timing specifications see the Development System Reference Guide For detailed information about the constraints you can use with your schematic entry software see the Constraints Guide Once you define timing specifications use TRACE Timing Report Circuit Evaluator and TSI Report or Timing Analyzer to analyze the results of your timing specifications Review the timing report carefully to ensure that all paths are constrained and that the constraints are specified properly Be sure to check for any error messages in the report If after applying timing constraints your design still does not meet timespec there are several things you can do Generally your synthesis and implementation tools have options intended to improve timing performance Check with your tool s documentation to see what options can be applied to your design If refining your tool options is not sufficient it may be necessary to go back to your source code to reconfigure parts of your design Reducing levels of logic reduces timing delays as well as arranging your floor plan so that related logic is grouped together www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Debugging Timing Problems lt XILINX Simulation Clock Does Not Meet Timespec If the frequency of the clock
225. erators in the HDL code Use resource sharing to improve design performance by reducing the gate count and the routing congestion If you do not use resource sharing each HDL operation is built with separate circuitry However you may want to disable resource sharing for speed critical paths in your design The following operators can be shared either with instances of the same operator or with an operator on the same line i a gt gt lt lt For example a operator can be shared with instances of other operators or with operators A operator can be shared only with other operators You can implement arithmetic functions magnitude comparators with gates or with your synthesis tool s module library The library functions use modules that take advantage of the carry logic in Spartan II Spartan 3 Virtex family and Virtex II Pro family CLBs slices Carry logic and its dedicated routing increase the speed of arithmetic functions that are larger than 4 bits To increase speed use the module library if your design contains arithmetic functions that are larger than 4 bits or if your design contains only one arithmetic function Resource sharing of the module library automatically occurs in most synthesis tools if the arithmetic functions are in the same process Resource sharing adds additional logic levels to multiplex the inputs to implement more than one function Therefore you may not want to use
226. erein are free from patent infringement or from any other third party right Xilinx Inc assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made Xilinx Inc will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user Xilinx products are not intended for use in life support appliances devices or systems Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited The contents of this manual are owned and copyrighted by Xilinx Copyright 1994 2003 Xilinx Inc All Rights Reserved Except as stated herein none of the material may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of any material contained in this manual may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 The following table shows the revision history for this document Version Revision 06 01 00 1 0 Initial Xilinx release 06 15 00 1 1 Accumulated miscellaneous updates and bug fixes 07 2
227. ers for the synchronous models into a single setuphold parameter in which the timing for the setup hold window can be expressed This should not change the timing simulation methodology in any way however when using Cadence NC Verilog there are no longer separate violation messages for setup and hold as they are now combined into a single setuphold violation RAM Considerations Timing Violations Xilinx devices contain two types of memories Block RAM and Distributed RAM Both Block RAM and Distributed RAM are synchronous elements when you write data to them so the same precautions must be taken as with all synchronous elements to avoid timing violations The data input address lines and enables all must be stable before the clock signal arrives to guarantee proper data storage Collision Checking Block RAMs also perform synchronous read operations This means that during a read cycle the addresses and enables must be stable before the clock signal arrives or a timing violation may occur When using Distributed RAM or Block RAM in dual port mode special care must be taken to avoid memory collisions A memory collision occurs when one port is being written to while the other port is either read or write is attempted to the same address at the same time or within a very short period of time thereafter The model warns you if a collision occurs If the RAM is being read on one port as it is being written to on the other the model
228. ertain cores only The Electronic Data Netlist EDN and NGC files contain the information required to implement the module in a Xilinx FPGA Since NGC files are in binary format ASCII NDF files may also be produced to communicate resource and timing information for NGC files to third party synthesis tools The ASY and XSF symbol information files allow you to integrate the CORE Generator module into a schematic design for Mentor or ISE tools VEO and VHO template files contain code that can be used as a model for instantiating a CORE Generator module in a Verilog or VHDL design Finally V and VHD wrapper files are provided to support functional simulation These files contain simulation model customization data that is passed to a parameterized simulation model for the core In the case of Verilog designs the V wrapper file also provides the port information required to integrate the core into a Verilog design for synthesis For details about using CORE Generator see the CORE Generator Guide Note The V and VHD wrapper files generated by CORE Generator cores are provided mainly to support simulation and are not synthesizable Functional Simulation of your Design Use functional or RTL simulation to verify the syntax and functionality of your design Use the following recommendations when simulating your design e Typically with larger hierarchical HDL designs you should perform separate simulations on each module before test
229. eset signal explicitly in the HDL code and not use the STARTUP VIRTEX STARTUP_VIRTEX2 or STARTUP_SPARTAN2 blocks There are two advantages to this method 1 This method gives you a faster speed The set reset signals are routed onto the secondary longlines in the device which are global lines with minimal skews and high speed Therefore the reset set signals on the secondary lines are much faster than the GSR nets of the STARTUP_VIRTEX block Since Virtex is rich in routings placing and routing this signal on the global lines can be easily done by our software 2 The trce program analyzes the delays of the explicitly written set reset signals You can read the TWR file report file of the trce program and find out exactly how fast your design s speed is The trce program does not analyze the delays on the GSR net of the STARTUP VIRTEX STARTUP_VIRTEX2 or STARTUP SPARTAN2 Hence using an explicit set reset signal improves your design accountability For Virtex M E TI II Pro II Pro X and Spartan II 3 devices the Global Set Reset GSR signal is by default set to active high globally resets device when logic equals 1 You can change this to active low by inverting the GSR signal before connecting it to the GSR input of the STARTUP component Note See Chapter 6 Verifying Your Design for more information on simulating the Global Set Reset Startup State The GSR pin on the STARTUP block or the GSRIN pin on the STARTBUF bl
230. esign file for your synthesis script file with either a do scr script or the appropriate default script file extension for your synthesis tool Naming Identifiers Types and Packages You can use long 256 characters maximum identifier names with underscores and embedded punctuation in your code Use meaningful names for signals and variables such as CONTROL REGISTER Use meaningful names when defining VHDL types and packages as shown in the following examples type LOCATION TYPE is package STRING IO PKG is Labeling Flow Control Constructs 46 You can use optional labels on flow control constructs to make the code structure more obvious as shown in the following VHDL and Verilog examples However you should note that these labels are not translated to gate or register names in your implemented design Flow control constructs can slow down simulations in some Verilog simulators www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Naming and Labeling Styles Z XILINX e VHDL Example D_REGISTER VHD Changing Latch into a D Register library IEEE use IEEE std_logic_1164 all entity d_register is port CLK DATA in STD_LOGIC Q out STD_LOGIC end d register architecture BEHAV of d register is begin My D Reg process CLK DATA begin if CLK event and CLK 1 then Q lt DATA end if end process End My D Reg
231. etermine clock skew See the Timing Analyzer Online Help for instructions Be aware that clock skew is modeled in the simulation but not in TRACE unless you invoke TRACE using the skew switch Simulation results may not equal TRACE results if the skew is significant as when a non BUFG clock is used To account for skew in TRACE use the following command trce skew or set the following environment variable setenv XILINX DOSKEWCHECK yes If your design has clock skew consider redesigning your path so that all registers are tied to the same global buffer If that is not possible consider using the USELOWSKEWLINES constraint to minimize skew Refer to the Constraints Guide for detailed information on the USELOWSKEWLINES constraint Note Avoid using the XILINX DOSKEWCHECK environment variable with PAR If you have clocks on local routing the PAR timing score may oscillate This is because the timing score is a function of both a clock delay and the data delay and attempts to make the data path faster may make the clock path slower or vice versa It should only be used within PAR on designs with paths that make use of global clock resources Synthesis and Verification Design Guide www xilinx com 269 1 800 255 7778 XILINX 270 Chapter 6 Verifying Your Design Asynchronous Inputs Asynchronous Clock Domains Crossing Out of Phase Timing violations can be caused by data paths that are not contro
232. etlist The post synthesis gate level netlist will consist of UNISIM components in the EDIF format Formality cannot directly process this EDIF netlist To create a Verilog netlist that is compatible with Formality run the design through NGDBuild and NetGen This post NGDBuild Verilog netlist is treated as a representation of the post synthesis netlist Following is a sample script that shows the necessary commands Note f CORE Generator components are used see the Using CORE Generator Components with Formality RTL vs Post Synthesis Verification section for more information ngdbuild design edf design ngd netgen ecn formality w design ngd design post synth ecn v If using Coregen run the following for each core in the design see the Using Coregen Components section below for more information xilperl XILINX verilog bin sol core2formal pl formality family core name Note f you are using CORE Generator make sure that the CORE Generator netlists are in the same directory design edf or use the sd switch in the NGDBuild command line to point to the directory with the CORE Generator netlists Creating a Script File to Run Formality for RTL vs Post Synthesis Verification Following is an sample script file that can be used to verify RTL vs post synthesis in Formality Note If CORE Generator components are used see the Using CORE Generator Components with Formality RTL vs Post
233. fer 174 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Memory lt XILINX architecture xilinx of ram_32x8s_infer is type mem type is array mem depth 1 downto 0 of STD LOGIC VECTOR d width 1 downto 0 signal mem mem type begin process wclk we addr begin if rising edge wclk then if we 1 then mem conv_integer addr lt d end if end if end process o lt mem conv_integer addr end xilinx Inferring Distributed SelectRAM in Verilog The following coding examples provide Verilog coding hints for FPGA Compiler II Synplify LeonardoSpectrum and XST e FPGA Compiler IITM FPGA Compiler II does not infer RAMs e LeonardoSpectrum Synplify and XST The following is a 32x8 32 words by 8 bits per word synchronous dual port RAM example module ram 32x8d infer o we d raddr waddr clk parameter d width 8 addr width 5 output d width 1 0 o input we clk input d width 1 0 d input addr width 1 0 raddr waddr reg d width 1 0 o reg d width 1 0 mem 1 addr width 1 0 always posedge clk if we mem waddr d always raddr o mem raddr endmodule The following is a 32x8 32 words by 8 bits per word synchronous single port RAM example module ram 32x8s infer o we d addr wclk parameter d width 8 addr width 5 output d width 1 0 o i
234. ffer Resources Virtex II II TM FTM IMTM ZTM Buffer Type Virtex Virtex E Pro ll Pro X Spartan ll Spartan 3 BUFG 4 4 Implemented 4 Implemented as as BUFGMUX BUFGMUX BUFGMUX N A N A 16 N A 8 Virtex E II II Pro II Pro X and Spartan II 3 devices include two tiers of global routing resources referred to as primary global and secondary local clock routing resources Note In Virtex II Il Pro Il Pro X and Spartan 3 BUFG is available for instantiation but is implemented with BUFGMUX e The primary global routing resources are dedicated global nets with dedicated input pins that are designed to distribute high fanout clock signals with minimal skew Each global clock net can drive all CLB IOB and Block SelectRAM clock pins The primary global nets may only be driven by the global buffers BUFG one for each global net There are four primary global nets in Virtex Virtex E and Spartan II There are sixteen in Virtex II and Virtex II Pro e The secondary local clock routing resources consist of backbone lines or longlines These secondary resources are more flexible than the primary resources since they are not restricted to routing clock signal only These backbone lines are accessed differently between Virtex E Spartan II and Virtex TII II Pro II Pro X Spartan 3 devices as follows In Virtex Virtex E and Spartan II devices there are 12 longlines ac
235. fferential buffers for Virtex II and later architectures have been updated to accept both the positive and negative inputs The following is an example of an instantiated differential I O in a Virtex E or Spartan ITE design entity lvds ex is port data in std logic data op out std logic data on out std logic end entity lvds ex architecture lvds arch of lvds ex is signal data n int std logic component OBUF LVDS port I in std logic O out std logic end component component IBUF LVDS port I in std logic O out std logic end component begin Input side I0 IBUF LVDS port map I data O data int Output side OPO OBUF LVDS port map I gt data int O gt data op data n int not data int ONO OBUF LVDS port map I gt data n int O gt data on end arch lvds ex Simulating a LUT The LUT look up table component is initialized for simulation by a generic mapping to the INIT attribute If the synthesis tool being used can accept generics in order to pass attributes then a generic specification is all that is needed to specify the INIT value If the synthesis tool cannot pass attributes via generics then the generic and generic map portions of the code must be omitted for synthesis by the use of translate off and translate on synthesis directives The INIT values must be passed using attribute notation The following is an example in which a LUT is initialized
236. following are some sample scripts that can be run from the command line or from the GUI FPGA Compiler II FPGA Scripting Tool FST implements a TCL based command line interface for FPGA Compiler II FST can be accessed from a command line by typing the following e For FPGA Compiler IITM fc2 shell f synth_file tcl The script executes and puts you back at the UNIX or DOS prompt FPGA Compiler II FST Example The following FST commands can be run in FPGA Compiler II e To create the project enter the following create project dir d register e To open the project enter the following open project d register e To add the files to the project enter the following add file format VHDL src d_register vhd e To analyze the design files enter the following analyze file progress e To create a chip for a device enter the following create chip progress target Virtex device 050PQ240 speed 5 name d register d register e To set the top level as the current design enter the following current chip d register e To optimize the design enter the following set opt chip format s Optimized d register optimize chip progress name opt chip e To write out the messages enter the following list message e To write out the netlist enter the following export chip progress dir e close project e quit LeonardoSpectrum You can run the following TCL script from LeonardoSpectrum by doing one of th
237. for large FPGA based state machine implementation The following examples show a one hot encoded state machine Use this method to control the state vector specification or when you want to specify the names of the state registers These examples use one flip flop for each of the seven states If you are using FPGA Compiler II use enumerated type and avoid using the when others construct in the VHDL Case statement This construct can result in a very large state machine Note Refer to the previous VHDL and Verilog Binary Encoded State Machine examples for the complete Case statement portion of the code One hot Encoded State Machine VHDL Example Library IEEE use IEEE std_logic_1164 all use IEEE std logic unsigned all entity one hot is port CLOCK RESE in STD_LOGIC A B C D E in BOOLEAN SINGLE MULTI CONTIG out STD LOGIC i end one_hot architecture BEHV of one_hot is type STATE TYPE is S1 S2 S3 S4 S5 S6 S7 attribute ENUM ENCODING STRING attribute ENUM ENCODING of STATE TYPE type is 0000001 0000010 0000100 0001000 0010000 0100000 1000000 signal CS NS STATE TYPE begin SYNC PROC process CLOCK RESET begin if RESET 1 then CS lt S1 elsif CLOCK event and CLOCK 1 then CS lt NS end if end process
238. from NetGen is a Verilog representation of the core that is read in with the RTL design as part of the golden reference design You must run the core2 ormal pl script on each CORE Generator module in the design Known Issues For known issues with verifying Xilinx designs with Conformal FPGA please search the Answers Database on the Xilinx support website at http support xilinx com Search using the following keyword string enter exactly as shown Verplex AND Conformal Synthesis and Verification Design Guide www xilinx com 299 1 800 255 7778 XILINX Chapter 7 Equivalency Checking 300 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778
239. from the same memory cell to which the other is simultaneously writing also violating the clock setup requirement the write will be successful but the data read will be invalid www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulation Flows Z XILINX Recovery tasks are also used to detect if an asynchronous set reset signal is released just before a clock event occurs If this happens the result is similar to a setup violation in that it is undetermined whether the new data should be clocked in or not Simulation Flows When simulating compile the Verilog source files in any order since Verilog is compile order independent However VHDL components must be compiled bottom up due to order dependency Xilinx recommends that you specify the test fixture file before the HDL netlist of your design as in the following examples Xilinx recommends giving the name testbench to the main module in the test fixture file This name is consistent with the name used by default in the ISE Project Navigator If this name is used no changes are necessary to the option in ISE in order to perform simulation from that environment ModelSim Vcom The following is information regarding ModelSim Vcom Using Shared Precompiled Libraries Simulation Libraries have to be compiled to compiled_lib_dir before using ModelSim Vcom See Compiling Xilinx Simulation Libraries COMPXLIB for instruction on how to comp
240. fter turning on the verification mode Synplify Pro creates the following files design vm post synthesis netlist for verification design vtc design file information design vlc link to Xilinx UNISIM and SIMPRIM design vfc vsc vmc setup information Running the DO File in Conformal FPGA Note Please refer to the Running LEC section in the Conformal User Manual The DO file fpgaR2G do created by Verplex has all of the necessary information to run the RTL to post synthesis verification Do the following to run the verification 1 Ensure that the Xilinx and Verplex environment variables are properly set up See Setup for Synopsys Formality and Verplex Conformal FPGA for details 2 Type the following at the command line and press Enter scd synthesis_project_directory 3 Type the following at the command line and press Enter cp SVERPLEX HOME fpga fpgaR2G do lec dofile design vtc Using CORE Generator V Components with Conformal RTL vs Post Synthesis Verification If CORE Generator components are used in the design the cores are considered black boxes in the RTL design The cores are also black boxes in the netlist output from Synplify Thus the cores must be black boxed in Conformal FPGA before performing verification The fpgaR2G do file generated by Verplex automatically black boxes the CORE Generator components Note CORE Gener
241. g Styles for Spartan II 3 Virtex E Il II Pro II Pro X library IEEE use IEEE std_logic_1164 all use IEEE std logic unsigned all entity ram 32x8d infer is generic d_width integer 8 addr_width integer 5 mem_depth integer 32 port O out STD LOGIC VECTOR d width 1 downto 0 we clk in STD LOGIC d in STD LOGIC VECTOR d width 1 downto 0 raddr waddr in STD LOGIC VECTOR addr width 1 downto 0 end ram 32x8d infer architecture xilinx of ram 32x8d infer is type mem type is array mem depth 1 downto 0 of STD LOGIC VECTOR d width 1 downto 0 signal mem mem type begin process clk we waddr begin if rising edge clk then if we 1 then mem conv integer waddr lt d end if end if end process process raddr begin o lt mem conv integer raddr end process end xilinx e The following is a 32x8 32 words by 8 bits per word synchronous single port RAM example library IEEE use IEEE std logic 1164 a11 use IEEE std logic unsigned all o entity ram 32x8s infer is generic d_width integer 8 addr_width integer 5 mem_depth integer 32 i port o out STD LOGIC VECTOR d width 1 downto 0 we wclk in STD LOGIC d in STD LOGIC VECTOR d width 1 downto 0 addr in STD LOGIC VECTOR addr width 1 downto 0 end ram 32x8s in
242. g value F1E1D1C1B1A191817161514131211100F0E0D0C0B0A0908006050403020100 name LeonardoSpectrum block ram ex Verilog example module block ram ex CLK WE ADDR DIN DOUT input CLK WE input 8 0 ADDR input 7 0 DIN output 7 0 DOUT RAMBA S8 UO WE WE EN LBL RST 1 b0 CLK CLK ADDR ADDR DI DIN DO DOUT exemplar attribute UO INIT 00 1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100 endmodule wwWw xilinx com 159 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Synplicity block_ram_ex Verilog example CLK WE module block_ram_ex ADDR DIN DOUT input CLK WE input 8 0 ADDR input 7 0 DIN output 7 0 DOUT synthesis translate_off defparam UO INIT 00 256 h0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF UO INIT 01 256 hFEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210 synthesis translate on RAMBA S8 UO WE WE L DI Jy RST 1 b0 LK CLK ADDR ADDR DI DIN DO DOUT synthesis Q W i XC props INIT 00 0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF INIT 01 FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210 endmodule XST With XST the INIT attribute must set in the HDL
243. ginning stages of the design Alternately you may use the HDL Bencher tool in ISE to automatically create a test bench by drawing the intended stimulus and the expected outputs in a waveform viewer Please refer to the ISE and or HDL Bencher Online Help for more information With yet another method you can use NetGen to create a test bench file The tb switch for Netgen creates a test fixture or test bench template The Verilog test fixture file has a tv extension and the VHDL test bench file has a tvhd extension Xilinx recommends giving the name testbench to the main module or entity name in the test bench file Xilinx also suggests but does not require that you specify the instance name for the instantiated top level of the design in the test bench as UUT These names are Synthesis and Verification Design Guide www xilinx com 209 1 800 255 7778 XILINX Chapter 6 Verifying Your Design consistent with the default names used by ISE for calling the test bench and annotating the SDF file when invoking the simulator Xilinx recommends that you initialize all inputs to the design within the test bench at simulation time zero in order to properly start simulation with known values Xilinx also suggests that you not begin applying stimulus data until after 100 ns in order to account for the default Global Set Reset pulse used in SIMPRIM based simulation However the clock source should begin before the GSR is released Fo
244. gn by including the design and test bench files appropriately The user should add 1oadplil swiftpli swift boot a Verilog directive to the simulate script For example verilog loadplil swiftpli swift boot Once each of these files has been properly updated you can run the simulation Synthesis and Verification Design Guide www xilinx com 199 1 800 255 7778 XILINX Chapter 5 Virtex Il Pro Considerations 2 This flow requires administrative privileges and is not recommended In the SXILINX verilog smartmodel sol simulation verilogxl directory there are several files to help set up and run a simulation using the SmartModels A description of each file follows a Readme Outlines the steps of the secondary flow to utilize the SWIFT interface Edit the setup file as shown below to set up environment for Verilog XL source setup Note The following step is not required if the models have been installed cd SXILINX verilog smartmodel sol image Enter sl admin csh Enter pliwiz Config Session Name xilinx Verilog XL Stand Alone SWIFT Interface Finish No cp p SCDS INST DIR tools pliwizard src Makefile xl sun4v edit Makefile pliwiz xl change INSTALL_DIR tools pliwizard src Makefile xl sun4v to Makefile xl sun4v edit Makefile xl sun4v Change CC cc to CC gcc make all edit the simulate file Source simulate Setup Description of variables which a user must set
245. gn hierarchy is advantageous for the following reasons e Improves simulation and synthesis results Improves debugging and modifying modular designs e Allows parallel engineering a team of engineers can work on different parts of the design at the same time Improves the placement and routing of your design by reducing routing congestion and improving timing e Allows for easier code reuse in the current design as well as in future designs Architecture Wizard The Architecture Wizard is a graphical application provided in Project Navigator that lets you configure complicated aspects of some Xilinx devices The Architecture Wizard consists of several components that you can use to configure specific device features Each component is presented as an independent wizard The following is a list of the wizards that make up the Architecture Wizard e Clocking Wizard RocketlO Wizard The Architecture Wizard produces an XAW file which is an XDM file with xaw file extension The Architecture Wizard can create a new XAW file or it can read in an existing XAW file When it reads in an existing XAW file it allows you to modify the settings When you finish with the wizard the new data is saved to the same XAW file that was read in The Architecture Wizard can also produce a VHDL Verilog or EDIF file depending on the flow type that is passed to it The generated HDL output is a module consisting of one or more primitives and the
246. h0 else COUT COUT 1 b1 end GSR is modeled as a wire within a global module So CLR does not need to be connected to GSR and the flop will still be reset with GSR FDCE UO Q Q D D C CLK CE 1 b1 CLR 1 b0 endmodule Since GSR is declared as a floating wire and is not in the port list the synthesis tool optimizes the GSR signal out of the design GSR is replaced later by the implementation software for all post implementation simulation netlists 254 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulating Verilog lt XILINX In the test fixture file set testbench uut GSR to glb1 GSR See the following example timescale 1 ns 1 ps module testbench reg CLK D wire Q wire 3 0 COUT assign testbench uut GSR glbl GSR glbl GSR asserted in glbl v my counter uut CLK CLK D D Q Q COUT COUT initial begin Stimeformat 9 1 ns 12 display Nt TCG DO o4 display Nt iLs o display Nt m KR Ul Sdisplay Nt e Ti monitor t b b Sb b Sh time CLK GSR D Q COUT end initial begin CIK 0 forever 25 CLK CLK end Apply Design Stimulus here initial begin D 1 b1 100 D 1 b0 200 D 1 b1 100 Sfinish end endmodule Simulating Special Components in Verilog The following section provides descriptions and examples of simulating special components for Virtex Boundary
247. has been properly updated run the simulation by double clicking simulate bat Cadence Verilog XL M Solaris Running Simulation A Verilog XL simulation incorporating the SWIFT interface canbe initiated in two ways 1 Inthe SXILINX verilog smartmodel sol simulation verilogxl directory there are several files to help set up and run a simulation using the SWIFT interface Setup Description of variables which a user must set for correct simulation and implementation Here is an example of the variables set setenv XILINX Xilinx path setenv LM LICENSE FILE verilogxl license dat S LM LICENSE FILE setenv CDS INST DIR Cadence path setenv LD LIBRARY PATH V2PRO source sim models Xilinx verilog smartmodel sol installed lib sun4Solaris lib S LD LIBRARY PATH setenv LMC CDS VCONFIG CDS INST DIR tools sun4v verilog bin vconfig setenv LM LICENSE FILE license dat LM LICENSE FILE setenv PATH LMC_HOME bin S CDS INST DIR tools bin PATH setenv PATH XILINX bin sol PATH Note The user is responsible for changing the parameters in italics to match the systems configuration The Lb LIBRARY PATH variable must point to the SmartModel installation directory Simulate An example Verilog XL compilation simulation script Illustrates which files need to be compiled and loaded for simulation This file can be modified to simulate a desi
248. he Block SelectRAM column is inserted every 12 CLB columns In Virtex EM Virtex E with extended memory the Block SelectRAM column is inserted every 4 CLB columns In Virtex II Virtex II Pro Virtex II Pro X or Spartan 3 there are at least four Block SelectRAM columns and a column is inserted every 12 CLB columns in larger devices Instantiating Block SelectRAM The following coding examples provide VHDL and Verilog coding styles for FPGA Compiler IITM LeonardoSpectrum Synplify and XST Instantiating Block SelectRAM VHDL Example e FPGA Compiler II LeonardoSpectrum and XST With FPGA Compiler II LeonardoSpectrum and XST you can instantiate a RAMB cell as a blackbox The INIT_ attribute can be passed as a string in the HDL www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Memory lt XILINX file as well as the script file The following VHDL code example shows how to pass INIT in the VHDL file e XST XST allows you to pass the INIT values through VHDL generics e LeonardoSpectrum With LeonardoSpectrum in addition to passing the INIT string in HDL you can pass an INIT string in a LeonardoSpectrum command script The following code sample illustrates this method set attribute instance INIT 00 type string value IF1bE1D1C1B1A191817161514131211100F0E0D0C0B0A09 80706050403020100 library IEEE
249. he design uses CORE Generator components see the Using CORE Generator Components with Conformal Post Synthesis vs Post PAR Verification section for more information ngdbuild uc design ucf design edf design ngd map design ngd o design map ncd par w design map ncd design ncd design map pcf netgen ecn conformal ngm design map ngm w design ncd design postpar ecn v fIf using Coregen run the following for each core in the design xilperl XILINX verilog bin sol core2formal pl verplex family core name NetGen is a new application It combines NGDANNO NGD2VHDL and NGD2VER into a single application Using the ecn conformal switch NetGen will write a Verilog netlist that is compatible with the Conformal FPGA tool In addition to creating the Verilog netlist NetGen creates an assertion file that tells Conformal FPGA if any ports were optimized away or if any ports were optimized from bi directional ports to just input or just output ports It also tells Conformal FPGA if any registers were optimized to constants The assertion file name will be design ecn vxc and should be read into Conformal FPGA to prevent any verification failures because of optimizations done by the Xilinx implementation tools 286 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Conformal FPGA and Synplify Pro Flow Z XILINX Creating a DO File to Run Conformal Post Synthesis vs Post PAR Verification Follow
250. he device does changing the time at which the input stimulus is applied eliminate the setup hold time violations Based on the answers to these questions you may need to make changes to your design or test bench to accommodate the simulation conditions Special Considerations for Setup and Hold Violations Zero Hold Time Considerations While Xilinx data sheets report that there are zero hold times on the internal registers and I O registers with the default delay and using a global clock buffer it is still possible to receive a hold violation from the simulator This hold violation is really a setup violation on the register However in order to get an accurate representation of the CLB delays part of the setup time must be modeled as a hold time For more information on this modeling please refer to Xilinx Answer Record 782 at the Xilinx support website Negative Hold Times In older versions of Xilinx simulation models negative hold times were truncated and specified as zero hold times While this does not cause inaccuracies for simulation it does reveal a more pessimistic model in terms of timing than is possible in the actual FPGA Therefore this made it more difficult to meet stringent timing requirements With the current release negative hold times are now specified in the timing models to provide a wider yet more accurate representation of the timing window This is accomplished by combining the setup and hold paramet
251. he following set_option technology Virtex E set_option part XCV50E set_option package CS144 set_option speed_grade 8 e To add file options enter the following add_file constraint watch sdc add file vhdl lib work macrol ohd add file vhdl lib work macro2 vhd add file vhdl lib work top_levle vhd Synthesis and Verification Design Guide www xilinx com 31 1 800 255 7778 XILINX Chapter 2 Understanding High Density Design Flow e To set compilation mapping options enter the following set_option default_enum_encoding onehot set_option symbolic_fsm_compiler true set_option resource_sharing true e To set simulation options enter the following set_option write_verilog false set_option write_vhdl false e To set automatic place and route vendor options enter the following set_option write_apr_constraint true set_option part XCV50E set_option package CS144 set_option speed_grade 8 e To set result format file options enter the following project result format edif project result file top level edf project run project save watch prj exit Compiling Your Design 32 Use the recommendations in this section to successfully compile your design Modifying your Design You may need to modify your code to successfully compile your design because certain design constructs that are effective for simulation may not be as effective for synthesis The synthesis syntax a
252. he second and final point at which you can verify the functionality of the design is after place and route PAR This is the final transformation of the design The entire design has been mapped into primitive components and placed and routed on the FPGA By running an equivalence check between the post synthesis netlist and the post PAR netlist you can verify that the optimizations and transformations done by the Xilinx implementation tools did not affect the functionality of the design The equivalence check includes the following steps 1 Implement the design with the Xilinx implementation tools and run NetGen to create a Verilog netlist 2 Create a dofile for running the verification in Conformal FPGA Run the DO file 4 Ifthe two netlists are not equivalent use Conformal FPGA to debug the differences the debugging process is not covered in this document Please see the Conformal FPGA documentation for more information on using Conformal Implementing the Design and Running NetGen This section assumes that the user has prior experience with the Xilinx Implementation tools For information on using the ISE GUI to implement a design please see the ISE Quick Start Tutorial For more information on the command line programs shown in this section please see the Development System Reference Guide The following is a sample script that shows how to run the Xilinx implementation tools and how to run NetGen Note f t
253. hin the supported range the constraint is ignored and an architecture specific default value is used instead Not all architectures support prorated timing values For simulation the VOLTAGE and TEMPERATURE constraints are processed from the UCF file into the PCF file The PCF file must then be referenced when running NetGen in order to pass the operating conditions to the delay annotator Synthesis and Verification Design Guide www xilinx com 229 1 800 255 7778 XILINX Chapter 6 Verifying Your Design To generate a simulation netlist using prorating for VHDL type the following netgen sim ofmt vhdl options pcf design pcf design ncd To generate a simulation netlist using prorating for Verilog type the following netgen sim ofmt verilog options pcf design pcf design ncd Note Combining both minimum values would override prorating and result in issuing only absolute process MIN values for the simulation SDF file Prorating may only be available for select FPGA families and it is not intended for military and industrial ranges It is applicable only within the commercial operating ranges MIN TYP MAX Field in SDF File Netsen Option Produced by NetGen sim default MAX MAX MAX s min Process MIN Process MIN Process MIN Prorated MAX Prorated MAX Prorated MAX voltage temperature in UCF PCF Understanding the Global Reset and Tristate for Simulation 230 Xilinx FPGAs have dedicated routing a
254. ial Compilation order required FPGA Families src XilinxCore src XilinxCoreL compilation see the vhdl analyze_order only pug ib order file located in required for sy rr rwx vng1 src Verilog XilinxCoreLib for the libraries required compile order Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 211 lt XILINX Table 6 4 Simulation Library Source Files Chapter 6 Verifying Your Design Location of Source Files Compile Order Bic Verilo bole Verilo VITAL g VHDL g VHDL SmartModel XILINX XILINX No special Required Virtex II Pro smartmodel smartmodel compilation Typical compilation order Virtex II Pro X Platform plat form order for Functional Simulation wrappers wrappers required for m simulator simulator Verilog unisi VOD vind libraries smartmodel_wrappers vhd unisim SMODEL vhd Typical compilation order for Timing Simulation simprim Vcomponents vhd smartmodel wrappers vhd simprim SMODEL vhd SIMPRIM SXILINX verilog XILINX vhdl Nospecial Required All Xilinx src simprims src simprims compilation typical compilation order order Technologies required for simprim Vcomponents Verilog i libraries simprim Vpackage vhd simprim VITAL vhd Using the UNISIM Library 212 The UNISIM Library is used for functional simulation only This library includes all of the Xilinx Unified Library primitives that are infer
255. ial optimization algorithms for Xilinx FPGAs Constraints and compiling options perform differently depending on the target device There are some commands and constraints in ASIC synthesis tools that do not apply to FPGAs and if used may adversely impact your results You should understand how your synthesis tool processes designs before creating FPGA designs Most FPGA synthesis vendors include information in their manuals specifically for Xilinx FPGAs Using FPGA System Features You can improve device performance and area utilization by creating HDL code that uses FPGA system features such as global reset wide I O decoders and memory FPGA system features are described in this manual Designing Hierarchy Current HDL design methods are specifically written for ASIC designs You can use some of these ASIC design methods when designing FPGAs however certain techniques may unnecessarily increase the number of gates or CLB levels This design guide will train you in techniques for optional FPGA design methodologies Design hierarchy is important in the implementation of an FPGA and also during incremental or interactive changes Some synthesizers maintain the hierarchical boundaries unless you group modules together Modules should have registered outputs so their boundaries are not an impediment to optimization Otherwise modules should be as large as possible within the limitations of your synthesis tool The 5 000 gates per modul
256. ies By default COMXPLIB will not overwrite the precompiled libraries cfg Create Configuration File Specify this option to create a configuration file with default settings By default COMPXLIB will create the compx1ib cfg file if it is not present in the current directory Use the configuration file to pass run time options to COMPXLIB while compiling the libraries For more details on the configuration file see Specifying Run Time Options info Print Precompiled Library Info Specify this option to print the precompiled information of the libraries You can specify a directory path with the info option to print the information for that directory help Print COMXPLIB help Specify this option to print the COMPXLIB help to standard output COMPXLIB Command Line Examples To print the COMPXLIB online help to your monitor screen type the following at the command line compxlib h To compile all of the Verilog libraries for a Virtex device UNISIM SIMPRIM and XilinxCoreLib on the ModelSim SE simulator and overwrite the results in SXILINX verilog mti se type the following at the command line compxlib s mti s f virtex l verilog w To compile the Verilog UNISIM Uni9000 and SIMPRIM libraries for the ModelSim PE simulator and save the results in the MYAREA directory type the following at the command line compxlib s mti pe f all u s l verilog o SMYAREA To compile the VHDL and Verilog S
257. ile the Xilinx VHDL libraries Depending on the makeup of the design Xilinx instantiated primitives or CORE Generator components for RTL simulation specify the following at the command line 1 Create working directory vlib work 2 Compile design files and workbench vcom lower level files vhd top level vhd testbench vhd testbench cfg vhd 3 Simulate design vsim testbench cfg For timing or post NGDBuild simulation use the SIMPRIM based libraries Specify the following at the command line 1 Create working directory vlib work 2 Compile design files and workbench vcom design vhd testbench vhd testbench cfg vhd 3 Simulate design vsim sdfmax instance namezdesign sdf testbench cfg Synthesis and Verification Design Guide www xilinx com 273 1 800 255 7778 XILINX Chapter 6 Verifying Your Design Scirocco Using Shared Precompiled Libraries Simulation Libraries have to be compiled to compiled_lib_dir before using Scirocco See Compiling Xilinx Simulation Libraries COMPXLIB for instruction on how to compile the Xilinx VHDL libraries Depending on the makeup of the design Xilinx instantiated components or CORE Generator components for RTL simulation specify the following at the command line 1 Create working directory mkdir work 2 Compile design files and workbench vhdlan work_macrol vhd top_level vhd testbench vhd testbench_cfg vhd scs testbench cfg 3 Simu
258. ile the other flip flops are cleared initialized to 0 Implementing Operators and Generate Modules Xilinx FPGAs feature carry logic elements that can be used for optimal implementation of operators and generate modules Synthesis tools infer the carry logic automatically when a specific coding style or operator is used Adder and Subtractor Synthesis tools infer carry logic in Virtex E II II Pro II Pro X and Spartan 1I 3 devices when an adder and Subtractor is described or operator Synthesis and Verification Design Guide www xilinx com 145 1 800 255 7778 146 Multiplier lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Synthesis tools utilize carry logic by inferring XORCY MUXCY and MULT_AND for Virtex Virtex E and Spartan II when a multiplier is described When a Virtex II II Pro part is targeted an embedded 18x18 two s complement multiplier primitive called a MULT18X18 is inferred by the synthesis tools For synchronous multiplications LeonardoSpectrum Synplify and XST infer a MULT18X18S primitive LeonardoSpectrum also features a pipeline multiplier that involves putting levels of registers in the logic to introduce parallelism and as a result improve speed A certain construct in the input RTL source code description is required to allow the pipelined multiplier feature to take effect This construct infers XORCY MUXC
259. ilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Memory lt XILINX always posedge clk begin if we mem addr lt din dout lt mem addr end endmodule Inferring Block SelectRAM Verilog Example The following coding examples provide Verilog coding styles for FPGA Compiler II LeonardoSpectrum Synplify and XST e FPGA Compiler IITM FPGA Compiler II does not infer RAMs All RAMs must be instantiated via primitives or cores e LeonardoSpectrum Refer to the VHDL example in the section above for restrictions in inferring Block SelectRAM e LeonardoSpectrum Verilog example module dualport_ram clka clkb wea addra addrb dia dob input clka clkb wea input 4 0 addra addrb input 3 0 dia output 3 0 dob synthesis syn_ramstyle block_ram reg 3 0 ram 31 0 reg 4 0 read_dpra reg 3 0 dob exemplar attribute ram block_ram TRUE always posedge clka begin if wea ram addra dia end always posedge clkb begin dob ram addrb end endmodule dualport_ram e Synplify Verilog example module sp_ram din addr we clk dout parameter data_width 16 address_width 10 mem_elements 600 input data_width 1 0 din input address_width 1 0 addr input we clk output data width 1 0 dout reg data width 1 0 mem mem elements 1 0 synthesis syn ramstyle block ram reg address width 1 0 addr reg
260. ilinx com Synthesis and Verification Design Guide 1 800 255 7778 Installing SmartModels from Xilinx Implementation Tools XILINX Method Two Solaris 1 Begin SmartModel Installation Run the s1_admin csh program from the SXILINX verilog smartmodel sol image directory using the following commands cd SXILINX verilog smartmodel sol image sl admin csh 2 Select SmartModels To Install a The sl admin GUI and the Set Library Directory dialog box appears Change the default directory from image pcnt to installed Click OK If the directory does not exist the program asks if you want to create it Click OK The sl admin GUI and the Install From dialog box appears Click Open to use the default directory The Select Models to Install dialog box appears Click Add All to select all models Click Continue The Select Platforms for Installation dialog box appears For Platforms select Sun 4 For EDAV Packages select Other Click Install When the words Install complete appear and the status line bottom line of the sl admin GUI changes to Ready installation is complete At this point the SmartModels have been installed Exit the GUI by selecting File gt Exit from the pull down menu or use the GUI to perform other operations such as accessing documentation and running checks on your newly installed library To properly use the newly compiled models set the LMC HOME variable to the image directory For exam
261. imulations This library is architecture independent SIMPRIM Library Structure The VHDL SIMPRIM Library source files are found in SXILINX vhdl src simprims The Verilog SIMPRIM Library source files are found in SXILINX verilog src simprims Using the SmartModel Library The SmartModel Libraries are used to model very complex functions of modern FPGAs such as the PowerPC PPC and the RocketIO SmartModels are encrypted source files that communicate with simulators via the SWIFT interface The SmartModel Libraries are located at SXILINX smartmodel and require additional installation steps to properly install on your system Additional setup within the simulator may also be required Please refer to Chapter 5 Virtex II Pro Considerations for more information on proper installation and setup of the SmartModel Libraries Synthesis and Verification Design Guide www xilinx com 213 1 800 255 7778 XILINX Chapter 6 Verifying Your Design Compiling Xilinx Simulation Libraries COMPXLIB Before starting the functional simulation of your design you must compile the Xilinx Simulation Libraries for the target simulator For this purpose Xilinx provides a tool called COMPXLIB COMXPLIB is a tool for compiling the Xilinx HDL based simulation libraries using the tools provided by the simulator vendor Compiling Simulation Libraries You can compile the libraries from Project Navigator or from the command line as
262. imulator puts out a message but the synchronous element retains its previous value Please consult your simulator s documentation for details on applying and using the no_notifier switch VHDL For VHDL if the simulator does not have a switch to disable X propagation NetGen can create a netlist in which this behavior is disabled By invoking NetGen with the xon FALSE switch the previous value should be retained during a timing violation If the simulation netlist is created within the ISE environment use the Global Disable of X generation for Simulation option in the advanced process properties options for Generate Post Map Simulation Model Use With Care Xilinx highly recommends that you only disable X propagation on paths that are truly asynchronous where it is impossible to meet synchronous timing requirements This capability is present for simulation in the event that timing violations cannot be avoided such as when a register must input asynchronous data Use extreme caution when disabling X propagation as simulation results may no longer properly reflect what is happening in the silicon www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Running NetGen lt XILINX MIN TYP MAX Simulation The Standard Delay Format SDF file allows you to specify three sets of delay values for simulation These are Minimum Typical and Maximum worst case typically abbreviated as MIN TYP MAX Xilinx h
263. ing is a sample DO file for running post synthesis vs post PAR verification in Conformal FPGA Note f the design uses CORE Generator components see the Using CORE Generator Components with Conformal Post Synthesis vs Post PAR Verification section for more information set log file top_postpar log replace set naming rule s register both The core2formal_output v file below is an optional file that is only needed if a Coregen component is used in the design There will be a file for each core in the design read design f SXILINX verilog verplex verilog vc core2formal output v design vm gol root top replace read design f SXILINX verilog verplex verilog vc design postpar ecn v rev root top replace set flatten model seq constant set sys mode lec add compared points all compare usage Save the script file as do ile name do Running the DO File in Conformal FPGA Follow these steps to run the verification 1 Ensure that the Xilinx and Verplex environment variables are properly set up See Setup for Synopsys Formality and Verplex Conformal FPGA for details 2 Copy the outputs from NetGen design_postpar_ecn vand design_postpar_ecn vxc into a verification directory or add the path to these files to the DO file 3 Copy the post synthesis netlist from Synplify Pro design vm into the verification directory or add the path to this file to the DO fil
264. ing your entire design This makes it easier to debug your code e Once each module functions as expected create a test bench to verify that your entire design functions as planned You can use the test bench again for the final timing simulation to confirm that your design functions as expected under worst case delay conditions Synthesizing and Optimizing your Design This section includes recommendations for compiling your designs to improve your results and decrease the run time Note Refer to your synthesis tool documentation for more information on compilation options and suggestions Creating an Initialization File Most synthesis tools provide a default initialization with default options You may modify the initialization file or use the GUI to change compiler defaults and to point to the applicable implementation libraries Refer to your synthesis tool documentation for more information Creating a Compile Run Script FPGA Compiler II LeonardoSpectrum and Synplify all support TCL scripting Using TCL scripting can make compiling your design easier and faster while achieving shorter compile times With more advanced scripting you can run a compile multiple times using different options and write to different directories You can also invoke and run other Synthesis and Verification Design Guide www xilinx com 29 1 800 255 7778 XILINX Chapter 2 Understanding High Density Design Flow command line tools The
265. initialize contents of the SRL16 256 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulating Verilog Z XILINX The following is an example of the defparam statement being used to initialize the contents of an SRL16 module srll6_ex CLK DIN QOUT input CLK DIN output QOUT Static length 16 bit SRL SRL16 UO D DIN Q QOUT CLK CLK AO 1 b1 Al 1 b1 A2 1 b1 A3 1 b1 defparam UO INIT 16 hAAAA endmodule Note Some synthesis tools may not support the use of a defparam statements See the Defparam Support Considerations section for details Block RAM For simulation the INIT 0x attributes passed by the defparam statement are used to initialize contents of the block ram MODULE bram512x4 CLK DATA BUSA ADDRA WEA DATA BUSB ADDRB WEB input 9 0 ADDRA ADDRB input CLK WEA WEB inout 3 0 DATA BUSA DATA BUSB wire 3 0 DOA DOB assign DATA BUSA WEA DOA 4 hz assign DATA BUSB WEB DOB 4 hz RAMBA S4 S4 UO DOA DOA DOB DOB ADDRA ADDRA DIA DATA BUSA ENA 1 b1 CLKA CLK WEA WEA RSTA 1 b0 ADDRB ADDRB DIB DATA BUSB ENB 1 b1 CLKB CLK WEB WEB RSTB 1 b0 defparam UO INIT 00 256 hnew hex value UO INIT 01 256 hnew hex value UO INIT 02 256 hnew hex value UO INIT 03 256 hnew hex value UO I
266. ints Table 6 3 Simulation Phase Library Information Simulation Point Compilation Order of Library Required RTL UNISIM XilinxCoreLib SmartModel Post Synthesis UNISIM XilinxCoreLib SmartModel Post NGDBuild SIMPRIM SmartModel Post Map SIMPRIM SmartModel Post Route SIMPRIM SmartModel www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 VHDL Verilog Libraries and Models Locating Library Source Files lt XILINX The following table provides information on the location of the simulation library source files as well as the order for a typical compilation Table 6 4 Simulation Library Source Files Location of Source Files Compile Order ee Verilo VITAE Verilo VITAE VHDL s VHDL UNISIM SXILINX verilog XILINX vhdl No special Required Spartan II src unisims src unisims compilation typical compilation order Spartan IIE order Ea Spartan 3 required for unisim VCOMP vhd Virtex Verilog unisim_VPKG vhd Virtex E libraries unisim_VITAL vhd Virtex II Virtex II Pro Virtex II Pro X UNISIM SXILINX verilog XILINX vhdl No special Required 9500 src uni9000 src unisims compilation typical compilation order CoolRunner order T CoolRunner II require dfor Unis im VCOMP vhd CoolRunner IISTM Verilog unisim VPKG vhd libraries unisim VITAL vhd XilinxCoreLib SXILINX verilog XILINX vhdl No spec
267. ints Guide and the Answers Database on the Xilinx Support Website Using the Xilinx Constraints Editor The Xilinx Constraints Editor is a GUI based tool that can be accessed from the Processes for Current Source window of the Project Navigator GUI Design Entry Utilities User Constraints Constraints Editor or from the command line constraints editor The Constraints Editor enables you to easily enter design constraints in a spreadsheet form and writes out the constraints in the UCF file This eliminates the need to know the UCF file syntax The other benefit is the Constraints Editor reads the design and lists all the nets and elements in the design This is very helpful in the HDL flow when the synthesis tool creates the names Some constraints are not available through the Constraints Editor The unavailable constraints must be entered directly in the UCF file using a text editor The new UCF file Synthesis and Verification Design Guide www xilinx com 33 1 800 255 7778 XILINX Chapter 2 Understanding High Density Design Flow needs to be re run through the Translate step or NGDBuild using the command line method For more information on using the Xilinx Constraints Editor please refer to the Constraints Editor Guide Using Synthesis Tools Constraints Editor The FPGA Compiler II LeonardoSpectrum and Synplify synthesis tools all have constraint editors to apply constraints to your HDL design Refer to you
268. ints so that the timing violation no longer occurs Usually most implemented designs have a small percentage of unconstrained paths after timing constraints have been applied and these are the ones where setup and hold violations generally occur Note The debugging steps for the hold violations and the setup violations are identical Width Violations The width Verilog system task monitors the width of signal pulses When the pulse width of a specific signal is less than what is required for the device being used the simulator issues a width violation Generally width violations are only specified for clock signals and asynchronous set or reset signals Consult the specific product Data Sheets for the device switching characteristics for your device Find the minimum pulse width requirements and ensure that the device stimulus conforms to these specifications Recovery Violations 272 The recovery Verilog system task specifies a time constraint between an asynchronous control signal and a clock signal for example between clearbar and the clock for a flip flop A recovery violation occurs when a change to the signal occurs within the specified time constraint The recovery Verilog system task is used to check for one of two dual port block RAM conflicts e If both ports write to the same memory cell simultaneously violating the clock to setup requirement the data stored is invalid e fone port attempts to read
269. inx com COMPXLIB Syntax The following command compiles all Xilinx Verilog libraries for the Virtex device family on the ModelSim SE simulator The compiled results are saved in the default location XILINX verilog mti_se compxlib s mti se f virtex l verilog COMPXLIB Options This section describes COMPXLIB command line options s Target Simulator Specify the simulator for which the libraries will be compiled If s option is not specified COMPXLIB will exit without compiling the libraries Valid values for s option are s mti se s mti pe s ncsim S vcs s vcsi S Scirocco 1 Language Specify the language from which the libraries will be compiled By default COMPXLIB detects the language type from the s Target Simulator option If the simulator supports both Verilog and VHDL COPMXLIB sets the 1 option to all and compiles both Verilog and VHDL libraries otherwise COMXPLIB detects the language type supported by the simulator and sets the l option value accordingly If the l option is specified COMXPLIB compiles the libraries for the language specified with l option Valid values for l option are 1 verilog l vhdl l all Synthesis and Verification Design Guide www xilinx com 217 1 800 255 7778 XILINX Chapter 6 Verifying Your Design e Device Family Specify the device family If f option is not specified COMPXLIB will exit with an error message without compi
270. ion Languages HDLs are used to describe the behavior and structure of system and circuit designs This chapter includes a general overview of designing FPGAs with HDLs HDL design examples are provided in subsequent chapters of this book and design examples can be downloaded from the Xilinx website System requirements and installation instructions for designs available from the web are also provided in this chapter This chapter also includes a brief description of why using FPGAs is more advantageous than using ASICs for your design needs To learn more about designing FPGAs with HDLs Xilinx recommends that you enroll in the appropriate training classes offered by Xilinx and by the vendors of synthesis software An understanding of FPGA architecture allows you to create HDL code that effectively uses FPGA system features For the latest information on Xilinx parts and software visit the Xilinx website at http www xilinx com On the Xilinx home page click on Products You can get Synthesis and Verification Design Guide www xilinx com 19 1 800 255 7778 lt XILINX Chapter 1 Introduction answers to your technical questions from the Xilinx support website at http www support xilinx com On the support home page click on Advanced Search to set up search criteria that match your technical questions You can also download software service packs from from this website On the support home page click on Software
271. irectional ports to just input or just output ports It also tells Conformal if any registers were optimized to constants The assertion file name will be design ecn vxc and should be read by Conformal to prevent any verification failures because of optimizations done by the Xilinx implementation tools Synthesis and Verification Design Guide www xilinx com 297 1 800 255 7778 XILINX Chapter 7 Equivalency Checking Creating a DO File to Run RTL vs Post PAR Verification Following is a sample DO file for running RTL vs post place and route verification in Conformal FPGA Note t CORE Generator components are used see the Using CORE Generator Components with Conformal RTL vs Post PAR Verification section for more information set log file top postpar log replace set naming rule s register both The core2formal output v file below is an optional file that is only needed if a Coregen component is used in the design There will be a file for each core in the design read design f SXILINX verilog verplex verilog vc core2formal output v rtl filel v rtl file2 v gol root top replace read design f SXILINX verilog verplex verilog vc design postpar ecn v rev root top replace set flatten model seq constant set flatten model mux loop to dlat set sys mode lec read map point design postpar ecn vxc add compared points all compare usage Save the DO file as dofile_name d
272. is important in verifying the operation of your circuit after the worst case placed and routed delays are calculated for your design In many cases you can use the same test bench that you used for functional simulation to perform a more accurate simulation with less effort You can compare the results from the two simulations to verify that your design is performing as initially specified The Xilinx tools create a VHDL or Verilog simulation netlist of your placed and routed design and provide libraries that work with many common HDL simulators Timing Analysis Using TRACE Timing driven PAR is based upon the Xilinx timing analysis software an integrated static timing analysis tool that is it does not depend on input stimulus to the circuit This means that placement and routing are executed according to timing constraints that you specify in the beginning of the design process The timing analysis software interacts with PAR to ensure that the timing constraints you impose on the design are met If you have timing constraints TRACE generates a report based on your constraints If there are no constraints the timing analysis tool has an option to write out a timing report containing the following e An analysis that enumerates all clocks and the required OFFSETs for each clock e An analysis of paths having only combinatorial logic ordered by delay For more information on TRACE refer to the Development System Reference Guide For mo
273. k to http support xilinx com support clearexpress websupport htm M F 8 00 5 30 GMT Japan 81 3 5321 7750 link to http support xilinx com support clearexpress websupport htm M F 9 00 12 00 1 00 5 00 JST Hong Kong 852 2 424 5200 china_support xilinx com Taiwan 886 2 2174 1388 taiwan_support xilinx com China 852 2 424 5200 china_support xilinx com Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 lt XILINX 23 2 XILINX Table 1 1 Technical Support Chapter 1 Introduction Location aRest of Asia Telephone 1 408 879 5199 Electronic Mail link to http support xilinx com support clearexpress websupport htm Support Hours Corporate Switchboard 1 408 559 7778 link to http support xilinx com support clearexpress websupport htm a English language support Note When e mailing or faxing inquiries provide your complete name company name and phone number Also provide a complete problem description including your design entry software and design stage Xilinx FTP Site ftp ftp xilinx com The FIP site provides online access to automated tutorials design examples online documents utilities and published patches Vendor Support Sites Vendor support for synthesis and verification products can be obtai
274. k1 Synthesis and Verification Design Guide www xilinx com 107 1 800 255 7778 SZ XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X assign low 1 b0 assign high 1 b1 assign reset dcm0 locked amp doml locked IBUFG CLOCK IN I clock in O clock DCM DCMO CLKFB clock out CLKIN clock DSSEN low PSCLK low PSEN low PSINCDEC low RST low LKO c1k0 LK90 LK180 LK270 LK2X LK2X180 LKDV LKFX LKFX180 CKED dcmO locked DONE STATUS synopsys attribute DLL FREQUENCY MODE LOW DUTY CYCLE CORRECTION TRUE STARTUP WAIT TRUE DFS FREQUENCY MODE LOW CLKFX DIVIDE wp CLKFX MULTIPLY 1 CLK FEEDBACK 1X CLKOUT PHASE SHIFT NONE PHASE SHIFT 0 lv cb m z le dry uE Ij o tg Et C Y OQ Y OY C 0 E n BUFG CLK BUFO O clock out I clk0 DCM DCM1 CLKFB clock with ps out CLKIN clock DSSEN low PSCLK low PSEN low PSINCDEC low RST low LKO clk1 LK90 LK180 LK270 LK2X LK2X180 LKDV LKFX LKFX180 OCKED dcm1 locked DONE STATUS E z E E E E E IE Ij g opt ocY Q0 Ck ae A E n 108 www xilinx com Synthesis and
275. keup of the design Xilinx instantiated primitives or CORE Generator components for RTL simulation specify the following at the ModelSim prompt set XILINX Senv XILINX vlog y SXILINX verilog src unisims t libextt v SXILINX verilog src glbl v incr testfixture v design v vsim testfixture glbl For timing or post NGDBuild simulation the SIMPRIM based libraries are used Specify the following at the ModelSim prompt vlog y SXILINX verilog src simprims S XILINX verilog src glbl v libextt v testfixture v time sim v incr vsim testfixture glbl libext v testfixture v The incr option enables incremental compilation Using Shared Precompiled Libraries Simulation Libraries have to be compiled to compiled lib dir before using ModelSim Vlog See Compiling Xilinx Simulation Libraries COMPXLIB for instruction on how to compile the Xilinx Verilog libraries Depending on the makeup of the design Xilinx instantiated primitives or CORE Generator components for RTL simulation specify the following at the ModelSim prompt set XILINX Senv XILINX vlog SXILINX verilog src glbl v testfixture v time sim v incr vsim L unisims ver L simprims ver L xilinxcorelib ver testfixture glbl For timing or post NGDBuild simulation the SIMPRIM based libraries are used Specify the following at the ModelSim prompt vlog SXILINX verilog src glbl v testfixture v time sim v incr
276. l delays must be processed Back annotation timing allows the model to accurately process the interconnect delays between the model and the rest of the design It can be used with either gate level or pin to pin timing or by itself You can find more details about SmartModels and the SWIFT interface in Design Flow volume of the Virtex II Pro Platform FPGA Developers Kit and on the Synopsys website at http www synopsys com products designware docs Supported Simulators A simulator with SmartModel capability is required to use the SmartModels While any HDL simulator that supports the Synopsys SWIFT interface should be able to handle the Virtex II Pro simulation flow the following HDL simulators are officially supported by Xilinx for Virtex II Pro simulation Solaris e MTI ModelSim SE 5 5 and newer e MTI ModelSim PE 5 7 and newer e Cadence NC Verilog e Cadence NC VHDL e Cadence Verilog XLTM e Synopsys amp VCS e Synopsys Scirocco Windows e MTI ModelSim SE 5 5 e MTI ModelSim PE 5 7 and newer Synthesis and Verification Design Guide www xilinx com 193 1 800 255 7778 XILINX Chapter 5 Virtex Il Pro Considerations Required Software To set up the simulation install the Xilinx implementation tools along with the simulator you are using Solaris e Xilinx Implementation Tools e HDL Simulator that can simulate both VHDL Verilog and SWIFT interface Win
277. l design creation is to keep the code behavioral Avoid instantiating specific components unless necessary This allows for more readable code faster and simpler simulation code portability the ability to migrate to different device families and code reuse the ability to use the same code in future designs However you may find it necessary to instantiate components if the component is not inferrable i e DCM GT PPC405 etc or in order to control the mapping placement or structure of a function Post Synthesis Pre NGDBuild Gate Level Simulation Most synthesis tools have the ability to write out a post synthesis HDL netlist for a design If the VHDL or Verilog netlists are written for UNISIM library components you may then use the netlists to simulate the design and evaluate the synthesis results However Xilinx does not support this method if the netlists are written in terms of the vendor s own simulation models The instantiated CORE Generator models are used for any post synthesis simulation because these modules are processed as a black box during synthesis It is important that you maintain the consistency of the initialization behavior with the behavioral model used for RTL post synthesis simulation and the structural model used after implementation In addition the initialization behavior must work with the method used for synthesized logic and cores Post NGDBuild Pre Map Gate Level Simulation The post
278. late design scsim For timing or post NGDBuild simulation use the SIMPRIM based libraries Specify the following at the command line 1 Create working directory mkdir work 2 Compile design files and workbench vhdlan work design vhd testbench vhd scs testbench 3 Simulate design scsim sdf testbench design sdf NC VHDL The following is information regarding NC VHDL Using Shared Precompiled Libraries Simulation Libraries have to be compiled to compiled_lib_dir before using NC_VHDL See Compiling Xilinx Simulation Libraries COMPXLIB for instruction on how to compile the Xilinx VHDL libraries It is assumed that the proper mapping and setup files are present before simulation If you are unsure that you have the simulator properly set up please consult the simulator vendor documentation Depending on the makeup of the design Xilinx instantiated components or CORE Generator components for RTL simulation specify the following at the command line 1 Create a working directory mkdir test 2 Compile design files and workbench ncvhdl work test testwork_macrol vhd top level vhd testbench vhd testbench cfg vhd 3 Elaborate the design at the proper scope ncelab testbench cfg A 274 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulation Flows lt XILINX 4 Invoke the simulation ncsim testbench cfg A For timing or post NGDBuild simulation use the SIMPRIM based lib
279. le Using Block SelectRAM 178 RTL Description of a ROM Verilog Example using Block SelectRAM 179 Implementing FIEO renes ke eth ehm epR e bre bb tae eek e Lae 180 Implementing CAM s ecoute ceret ve elds tees a eae esate dod iue 180 Using CORE Generator to Implement Memory ssssseeeeeeee 181 Implementing Shift Registers Virtex E II II Pro II Pro X and Spartan II 3 r qu teenie pace tala td CPP EET 181 Inferring SRL16 in VHD Leres crre te tineep ise eri iii et elm one aes gere ed 182 Inferring SRL16 in Verilog lesessesseseseeee III 182 Inferring Dynamic SRL16 in VHDL 2 eee 183 Inferring Dynamic SRL16 in Verilog 0 6 eee eee 183 Implementing LESR 2 tee ed ER ure bee Ure ee ene CERA IR e IRR 184 Implementing Multiplexers 00 0 184 Mux Implemented with Gates VHDL Example 0000 cece eee eee 185 Mux Implemented with Gates Verilog Example 00000 c cece een 185 Wide MUX Mapped to MUXFS 2 Ie 186 Mux Implemented with BUFTs VHDL Example 0 0 0 0 cece eee 186 Mux Implemented with BUFTs Verilog Example 0 06 c cece eee ee 187 Using PIpelinitig soso 61 utectrice liber end ce PROC o EORR EO OEC UR I ee 188 12 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 XILINX Before Pipelining i iiec RR eee Re Re eed ave REX eR EES 188 After Pipelining cerc ceo me e Rh ee Rp E RE
280. le name for the written netlist and does not affect the entity or module name By default this field is left blank and the simulation netlist name is top level name timesim Correlate Simulation Data to Input Design The Correlate Simulation Data to Input Design property uses an optional NGM file during the back annotation process This is a design file produced by Map that contains information about the original design hierarchy specified by the KEEP HIERARCHY constraint The default for this property is On checkbox is checked Generate Multiple Hierarchical Netlist Files The Generate Multiple Hierarchical Netlist Files property allows the netlister to generate separate gate level netlists and SDF files if applicable for each hierarchy level in the design that is designated with a KEEP_HIERARCHY attribute This allows for piece wise verification of a design Refer to the Design Hierarchy and Simulation section for more details on this option Synthesis and Verification Design Guide www xilinx com 223 1 800 255 7778 lt XILINX 224 Chapter 6 Verifying Your Design The default for this option is Off checkbox is unchecked This option must be used with Correlate Simulation Data to Input Design enabled Use Automatic DO File for ModelSim Simulation This option enables Project Navigator to create and use a batch script file for compiling and simulating your test bench and design files when the ModelSim simulato
281. le script that shows the necessary commands Note f CORE Generator components are used see the Using CORE Generator Components with Conformal RTL vs Post Synthesis Verification section for more information ngdbuild design edf design ngd netgen ecn conformal w design ngd design post synth ecn v fIf using Coregen run the following for each core in the design xilperl XILINX verilog bin sol core2formal pl verplex family core name Note f you are using CORE Generator make sure that the CORE Generator netlists are in the same directory design edf or use the sd switch in the ngdbuild command line to point to the directory with the CORE Generator netlists Creating a DO File to Run RTL vs Post Synthesis Verification Following is a sample script file that can be used to verify RTL vs post synthesis in Conformal FPGA Synthesis and Verification Design Guide www xilinx com 295 1 800 255 7778 XILINX 296 Chapter 7 Equivalency Checking Note t CORE Generator components are used see the Using CORE Generator Components with Conformal RTL vs Post Synthesis Verification section for more information set log file top postpar log replace set naming rule s register both The core2formal output v file below is an optional file that is only needed if a Coregen component is used in the design There will be a file for each core in the design read desig
282. ling the libraries Valid values for f option are f all all device families f virtex f virtexe f virtex2 f virtex2p f spartan2 f spartan3 f spartan2e f cpld f xpla3 f xbr f xc9500 f xc9500xl f xc9500xv j You can compile selected libraries by using the following f syntax f device family descriptor descriptor The descriptor identifies the Library Name You can specify the following descriptors Descriptor Library u UNISIM S SIMPRIM n Uni9000 c XilinxCoreLib m SmartModel r CoolRunner a Abel For example the following will compile only the Verilog UNISIM library for the Virtex II Pro family on the NC Sim simulator compxlib s ncsim f virtex2p u 1 verilog e o Output Directory Specify the directory path where you want to compile the libraries By default COMXPLIB will compile the libraries in SXILINX language target simulator directory 218 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Compiling Xilinx Simulation Libraries COMPXLIB XILINX p Simulator Path Specify the directory path where the simulator executables reside By default COMPXLIB will automatically search for the path from the PATH environment variable This option is required if the target simulator is not specified in the PATH environment variable w Overwrite Compiled Library Specify this option if you want to overwrite the precompiled librar
283. linx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Inputs and Outputs Z XILINX IOBUF_LVDS UIO_n I iodata n out SD Iin int IO IODATA n O INV UINV I iodata out O iodata n out IBUFG LVDS UIBUFG I CLK O CLK ibufgout BUFG UBUFG I CLK ibufgout O CLK int always posedge CLK int begin Q p int lt DATA int end assign iodata out DATA int amp amp iodata in assign Q n int Q p int endmodule e UCF example targeting V50ECS144 NE CLK LOC A6 GCLK3 NET DATA LOC A4 IO LOP YY NET Q p LOC A5 IO L1P YY NET Q n LOC B5 IO L1N YY NET iodata p LOC D8 IO L3P yy NET iodata n LOC C8 IO L3N yy NE Tin LOC F13 IO L10P The following examples use the IOSTANDARD attribute on I O buffers as a work around for LVDS buffers This example can also be used with other synthesis tools to configure I O standards with the IOSTANDARD attribute e VHDL example library IEEE use IEEE std_logic_1164 all entity flip_flop is port d in std logic Clk in std logic q out std logic qin out std logic end flip flop architecture flip flop arch of flip flop is component IBUF port I in std logic O out std logic end component component OBUF port I in std logic O out std logic end component attribute IOSTANDARD string attribute LOC
284. lizing the GSR and GRTS nets please refer to Understanding the Global Reset and Tristate for Simulation in this chapter When you run timing simulation an SDF file is created as with the post Map simulation However this SDF file contains all block and routing delays for the design Providing Stimulus Before you perform simulation you should create a test bench or test fixture to apply the stimulus to the design A test bench is HDL code written for the simulator that instantiates the design netlist s initializes the design and then applies stimuli to verify the functionality of the design You can also set up the test bench to display the desired simulation output to a file waveform or screen The test bench has many advantages over interactive simulation methods For one it allows repeatable simulation throughout the design process It also provides documentation of the test conditions There are several methods to create a test bench and simulate a design A test bench can be very simple in structure and sequentially apply stimulus to specific inputs A test bench may also be very complex including subroutine calls stimulus read in from external files conditional stimulus or other more complex structures The ISE tools create a template test bench containing the proper structure library references and design instantiation based on your design files from Project Navigator This greatly eases test bench development at the be
285. ll use IEEE std logic arith all o entity mux tbuf is port SEL in STD LOGIC VECTOR 4 downto 0 A B C D E in STD LOGIC SIG out STD LOGIC end mux tbuf 186 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Multiplexers Z XILINX architecture RTL of mux_tbuf is begin SIG lt A when SEL 0 2 0 else Z SIG lt B when SEL 1 0 else Z SIG lt C when SEL 2 2 0 else Z SIG lt D when SEL 3 2 0 else Z SIG lt E when SEL 4 0 else Z end RTL Mux Implemented with BUFTs Verilog Example The following example shows a MUX implemented with BUFIs MUX_TBUF V module mux tbuf A B C D E SEL SIG input A B C D E input 4 0 SEL output SIG assign SIG SEL 0 2 1 b0 A 1 bz assign SIG SEL 1 2 1 b0 B 1 bz assign SIG SEL 2 1 b0 C 1 bz assign SIG SEL 3 1 b0 D 1 bz assign SIG SEL 4 1 b0 E 1 bz endmodule SEL lt 0 gt A op SEL lt 1 gt B B SEL lt 2 gt SIG C gt SEL lt 3 gt D SEL lt 4 gt E X6228 Figure 4 6 5 to 1 MUX Implemented with BUFTs Synthesis and Verification Design Guide www xilinx com 187 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Using Pip
286. ll registers in the design during the functional simulation For these designs it is not necessary to emulate the GSR pulse in the functional simulation If the design contains registers that are not connected to a user reset the GSR pulse can be emulated to ensure that the functional simulation matches the timing simulation There are two methods that can be used to emulate the GSR pulse e Use the ROC cell to generate a one time GSR pulse at the beginning of the simulation as described in the Using VHDL Reset On Configuration ROC Cell section e Use the ROCBUF cell to control the emulated GSR signal in the test bench as described in the Using VHDL ROCBUF Cell section Using VHDL Reset On Configuration ROC Cell The ROC cell which is modeled in the UNISIM library can be used to emulate the GSR pulse at the beginning of a functional simulation This is the same component that is automatically inserted into the back end netlist It generates a one time pulse at the beginning of the simulation that lasts for a default value of 100ns During implementation the signal connected to the output of the ROC component will automatically be mapped to the Global GSR network and will not be routed on local routing Synthesis and Verification Design Guide www xilinx com 231 1 800 255 7778 XILINX Chapter 6 Verifying Your Design Following is an example that shows how to use the ROC cell library IEEE
287. lled by the simulation clock or are not clock controlled at all Timing violations also include data paths that cross asynchronous clock boundaries have asynchronous inputs or cross data paths out of phase Asynchronous Clocks If the design has two or more clock domains defined any path that crosses data from one domain to another could cause timing problems Although data paths that cross from one clock domain to another are not always asynchronous it is always best to be cautious with these situations If two clocks have unrelated frequencies they should certainly be treated as asynchronous Any clocking signal that is coming from off chip should also be treated as asynchronous Note that any time a register s clock is gated it should be treated as asynchronous unless extreme caution is used Check the source code and the Timing Analyzer report to see if the path in question crosses asynchronous clock boundaries If your design does not allow enough time for the path to be properly clocked into the other domain you may have to redesign your clocking scheme Consider using an asynchronous FIFO as a better way to pass data from one clock domain to another Asynchronous Inputs Data paths that are not controlled by a clocked element are asynchronous inputs Because they are not clock controlled they can easily violate setup and hold time specifications Check the source code to see if the path in question is synchronous to the input r
288. llows you to rename the architecture name generated by NetGen VHDL The default architecture name for each entity in the netlist is STRUCTURE Change Device Speed To This option allows you to change the targeted speed grade for the output simulation netlist without re running place and route This option also allows you to create a simulation netlist with absolute minimum timing numbers if they are available for the target device Retain Hierarchy This option when enabled allows the netlister to write a verification netlist in which the netlist will retain each level of design hierarchy that was specified on the KEEP HIERARCHY attribute When disabled it removes all hierarchy from the output simulation netlist and writes out a flat design The default for this option is ON Tristate on Configuration Pulse Width VHDL Only This option specifies the pulse width in nanoseconds for the TOC component You must specify a positive integer to stimulate the component properly This option is disabled if you are controlling the global tristate via a port using the Bring Out Global Tristate Net as a Port option For more information on this option refer to the Understanding the Global Reset and Tristate for Simulation section By default the TOC pulse width is set to 0 ns Reset On Configuration Pulse Width VHDL Only This option specifies the pulse width in nanoseconds for the ROC component in the simulation netlist Y
289. ly need to constrain the clock period and the ClockToSetup of the previous module If you have multiple combinatorial blocks at different levels of the hierarchy you must manually calculate the delay for each module Also registering the outputs of your design hierarchy can eliminate any possible problems with logic optimization across hierarchical boundaries Restrict One Clock to Each Module or to Entire Design By restricting one clock to each module you only need to describe the relationship between the clock at the top level of the design hierarchy and each module clock By restricting one clock to the entire design you only need to describe the clock at the top level of the design hierarchy Note See your synthesis tool documentation for more information on optimizing logic across hierarchical boundaries and compiling hierarchical designs www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 XILINX Chapter 5 Virtex II Pro Considerations This chapter includes coding techniques to help you improve synthesis results It includes the following sections e Introduction e Using SmartModels to Simulate Virtex II Pro Designs e Simulation Components e Overview of Virtex II Pro Simulation Flow e SmartModels e Supported Simulators e Required Software e Installing SmartModels from Xilinx Implementation Tools e Running Simulation Introduction
290. martModels for the Cadence NC Sim simulator and save the results in tmp directory type the following at the command line compxlib s ncsim f virtex2p m l all o tmp To compile the Verilog Virtex II XilinxCoreLib library for the Synopsys VCS simulator and save the results in the default directory SXILINX verilog vcs type the following at the command line compxlib s vcs f virtex2 c To compile the Verilog CoolRunner library for the Synopsy s VCSi simulator and save the results in the current directory type the following at the command line compxlib s vcsi f cpld r o Synthesis and Verification Design Guide www xilinx com 219 1 800 255 7778 XILINX 220 Chapter 6 Verifying Your Design To compile the Spartan IIE and Spartan 3 libraries VHDL UNISIMs SIMPRIMs and XilinxCoreLib for the Synopsys Scirocco simulator and save the results in the default directory XILINX vhdl scirocco and use the simulator executables from the path specified with the p option type the following at the command line compxlib s scirocco f spartan2e p products eproduct ver2 0 2 0 comnon sunos5 bin To print the precompiled library information for the libraries compiled in XILINX type the following at the command line compxlib info To create compxlib cfg with default options type the following at the command line compxlib cfg Specifying Run Time Options You can specify r
291. mation on using Xilinx specific features Synthesis and Verification Design Guide www xilinx com 39 1 800 255 7778 XILINX Chapter 2 Understanding High Density Design Flow Modular Design and Incremental Design ECO For information on Incremental Design ECO please refer to the following Application Notes e XAPP165 Using Xilinx and Exemplar for Incremental Designing ECO v1 0 8 9 99 e XAPP164 Using Xilinx and Synplify for Incremental Designing ECO v1 0 8 6 99 Xilinx Development Systems feature Modular Design to help you plan and manage large designs Reference the following link for more information on the Xilinx Modular Design feature Placing and Routing Your Design Note For more information on placing and routing your design refer to the Development System Reference Guide The overall goal when placing and routing your design is fast implementation and high quality results However depending on the situation and your design you may not always accomplish this goal as described in the following examples e Earlier in the design cycle run time is generally more important than the quality of results and later in the design cycle the converse is usually true e During the day you may want the tools to quickly process your design while you are waiting for the results However you may be less concerned with a quick run time and more concerned about the quality of results when you run
292. me The design examples in this manual were created with Verilog and VHSIC Hardware Description Language VHDL compiled with various synthesis tools and targeted for Spartan II Spartan IIE Spartan 3 Virtex Virtex E Virtex II Virtex II Pro and Virtex II Pro X devices Xilinx equally endorses both Verilog and VHDL VHDL may be more difficult to learn than Verilog and usually requires more explanation This manual does not address certain topics that are important when creating HDL designs such as the design environment verification techniques constraining in the synthesis tool test considerations and system verification Refer to your synthesis tool s reference manuals and design methodology notes for additional information Before using this manual you should be familiar with the operations that are common to all Xilinx software tools Guide Contents This book contains the following chapters e Chapter 1 Introduction provides a general overview of designing Field Programmable Gate Arrays FPGAs with HDLs This chapter also includes installation requirements and instructions e Chapter 2 Understanding High Density Design Flow provides synthesis and Xilinx implementation techniques to increase design performance and utilization e Chapter 3 General HDL Coding Styles includes HDL coding hints and design examples to help you develop an efficient coding style e Chapter 4 Archit
293. mpiled for any of the following reasons 1 Target of a hierarchical reference has changed 2 A compile time constant such as a parameter has changed 3 Ports of a module instantiated in the module have changed 4 Module inlining For example a group of module definitions merging internally in VCS into a larger module definition which leads to faster simulation These affected modules are again recompiled This is done only once For more information on how to back annotate the SDF file for timing simulation go to Answer Record 6349 on the Xilinx support website at http support xilinx com Using Shared Precompiled Libraries Simulation Libraries have to be compiled to compiled_lib_dir before using VCS VCSi See Compiling Xilinx Simulation Libraries COMPXLIB for instruction on how to compile the Xilinx Verilog libraries Depending on the makeup of the design Xilinx instantiated primitives or CORE Generator components for RTL simulation specify the following at the command line ves Mupdat Mlib compiled_dir unisims_ver y SXILINX verilog src unisims Mlib compiled dir simprims ver y SXILINX verilog src simprims Mlib compiled dir xilinxcorelib ver libext v SXILINX verilog src glbl v R testfixture v design v For timing or post NGDBuild simulation the SIMPRIM based libraries are used Specify the following at the command line ves tcompsdf y SXILINX verilog sr
294. mulation go to Answer Record 941 on the Xilinx support website at http support xilinx com VOS TM VOGIM VCS and VCSi are identical except that VCS is more highly optimized resulting in greater speed for RTL and mixed level designs Pure gate level designs run with comparable speed However VCS and VCSi are guaranteed to provide the exact same simulation results VCSi is invoked using the vesi command rather than the ves command There are two methods to run simulation with VCS VCSi 1 Using library source files with compile time options 2 Using shared precompiled libraries Using Library Source Files With Compile Time Options Depending on the makeup of the design Xilinx instantiated primitives or CORE Generator components for RTL simulation specify the following at the command line ves y SXILINX verilog src unisims t tlibext v SXILINX verilog src glbl v Mupdat R testfixture v design v For timing or post NGDBuild use the SIMPRIM based libraries Specify the following at the command line vcs compsdf y S XILINX verilog src simprims SXILINX verilog src glbl v t tlibext v Mupdat R testfixture v time_sim v The R option automatically simulates the executable after compilation 276 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulation Flows XILINX The Mupdate option enables incremental compilation Modules are reco
295. mulation and implementation Here is an example of the variables set setenv XILINX Xilinx path setenv VCS HOME VCS path setenv LM LICENSE FILE license dat LM LICENSE FILE setenv LMC HOME S XILINX verilog smartmodel sol image setenv LMC CONFIG LMC_HOME data solaris 1mc setenv VCS CC gcc setenv PATH LMC_HOME bin VCS_HOME bin PATH setenv PATH S XILINX bin sol PATH Note The user is responsible for changing the parameters in italics to match the systems configuration e Simulate Example Verilog XL compilation simulation script Illustrates which files need to be compiled and loaded for simulation This file can be modified to simulate a design by including the design and test bench files appropriately Once each of these files has been properly updated run the simulation 202 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 XILINX Chapter 6 Verifying Your Design Introduction This chapter describes the basic HDL simulation flow using the Xilinx and third party software It includes the following sections e Introduction e Adhering to Industry Standards e Simulation Points e VHDL Verilog Libraries and Models e Compiling Xilinx Simulation Libraries COMPXLIB e Running NetGen e Understanding the Global Reset and Tristate for Simulation e Simulating VHDL e
296. n OPTION Simulator Language Command Line Options Syntax OPTION Target Simulator Language Command Line Options www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Running NetGen Z XILINX By default COMXPLIB will pick the simulator compilation commands specified in the Command_Line_Options You can add or remove the options from Command Line Options depending on the compilation requirements Sample Configuration File EXECUTE on OCK_PRECOMPILED off LOG_CMD_TEMPLATE on RECOMPILED_INFO on PTION mti se vhdl source 93 PTION mti se verilog source 93 PTION ncsim vhdl MESSAGES v93 RELAX NOLOG ncsim verilog MESSAGES NOLOG PTION vcsi verilog Mupdate PTION vcs verilog Mupdate oO OO OO O U td H o z PTION scirocco vhdl nc Running NetGen Xilinx provides a program that can create a verification netlist file from your design files You can run the netlist writer from Project Navigator XFLOW or the command line Each method is described in the following sections Creating a Simulation Netlist You can create a timing simulation netlist from Project Navigator XFLOW or from the command line as described in this section From Project Navigator 1 Highlight the top level design in the Sources in Project window 2 Inthe Processes for Source window click on the sign nex
297. n 011 gt SIG lt when others gt SIG lt E end case end process SEL PROCESS end RTL tow gd Jawar Mux Implemented with Gates Verilog Example The following example shows a MUX implemented with Gates mux gate v 5 to 1 Mux Implemented in Gates module mux gate SEL A B C D E SIG input 2 0 SEL input A B C D E output SIG reg SIG Synthesis and Verification Design Guide www xilinx com 185 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X always SEL A B C D E begin case SEL 3 b000 SIG A 3 b001 SIG B 3 b010 SIG C 3 b011 SIG D default SIG E endcase end A B C SIG D E SEL 0 SEL lt 1 gt SEL lt 2 gt Figure 4 5 5 to 1 MUX Implemented with Gates Wide MUX Mapped to MUXFs Synthesis tools use MUXF5 and MUXF6 and for Virtex II Virtex II Pro Virtex II Pro X and Spartan 3 use MUXF7 and MUXES to implement wide multiplexers These MUXes can respectively be used to create a 5 6 7 or 8 input function or a 4 to 1 8 to 1 16 to 1 or a 32 to 1 multiplexer Mux Implemented with BUFTs VHDL Example The following example shows a MUX implemented with BUFTs MUX_TBUF VHD 5 to 1 Mux Implemented in 3 State Buffers May 2001 library IEEE use IEEE td logic 1164 a
298. n CLOCK lt FAST CLOCK else CLOCK lt SLOW CLOCK end if end process GBUF FOR MUX CLOCK BUFG port map gt CLOCK O gt CLOCK GBUF Data_Path process CLOCK_GBUF begin if CLOCK GBUF event and CLOCK_GBUF 1 then DOUT lt DATA end if end process end XILINX Synthesis and Verification Design Guide www xilinx com 81 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Verilog example VMIMMLMMHMMPMMMMMMPI MoaEL LP ITAA TAIT TTT CLOCK MUX BUFG V Version 1 1 This is an example of an instantiation of global buffer BUFG from an internally driven signal a multiplied clock MM ITAA ATA AAA TITAS module clock_mux DATA SEL SLOW_CLOCK FAST_CLOCK DOUT input DATA SEL input SLOW CLOCK FAST CLOCK output DOUT reg CLOCK wire CLOCK GBUF reg DOUT always SEL or FAST CLOCK or SLOW CLOCK begin if SEL 1 b1 CLOCK lt FAST CLOCK else CLOCK lt SLOW CLOCK end BUFG GBUF FOR MUX CLOCK O CLOCK GBUF I CLOCK always posedge CLOCK GBUF DOUT DATA endmodule If using a Virtex II II Pro II Pro X or Spartan 3 device a BUFGMUX can be used to multiplex between clocks The above examples are rewritten for Virtex II TI Pro II Pro X or Spartan 3 VHDL example CLOCK MUX BUFG VHD Version 1
299. n f SXILINX verilog verplex verilog vc core2formal output v rtl filel v rtl file2 v gol root top replace read design f SXILINX verilog verplex verilog vc design post synth ecn v rev root top replace set flatten model seq constant set flatten model mux loop to dlat set sys mode lec add compared points all compare usage Save the dofile as dofile_name do Running the DO File in Conformal FPGA Follow these steps to run the verification 1 Ensure that the Xilinx and Verplex environment variables are properly set up See Setup for Synopsys Formality and Verplex Conformal FPGA cd verification directory 9olec dofile dofile_name do Using CORE Generator V Components with Conformal RTL vs Post Synthesis Verification When using CORE Generator components the contents of the cores are read in during NGDBuild the first stage of the Xilinx implementation process Since the post synthesis netlist was run through NGDBuild the contents of the cores will be in the post NGDBuild netlist that is being used for verification The RTL design only contains black box instantiations of the cores Xilinx provides a Perl script core2formal p1 that creates Verilog representations of the cores which can be read in as part of the reference design Usage gt xilperl S SXILINX verilog bin platform core2formal pl vendor family coregen module e For Conformal FPGA the vendor option must be verplex
300. n if RESET 1 bl D Q OUT lt 00000000 else if CLOCK 1 b1 begin if ENABLE 1 b1 D Q OUT lt D IN end end End Flip flop with asynchronous reset and clock enable Flip flop with asynchronous reset begin if RESET asynchronous set and clock enable always posedge CLOCK posedge RE ET posedge SI ET 1 b1 E Q OU else if lt 00000000 ET 1 bl E Q OU else if begin C lt ULITIITITI LOCK 1 bl if E NABLE 1 bl end as end module end m Q OUT lt D IN End Flip flop with asynchronous reset ynchronous set and clock enable Using Clock Enable Pin Instead of Gated Clocks Use the CLB clock enable pin instead of gated clocks in your designs Gated clocks can introduce glitches increased clock delay clock skew and other undesirable effects The first two examples in this section VHDL and Verilog illustrate a design that uses a gated clock Figure 3 6 shows this design implemented with gates Following these examples are VHDL and Verilog designs that show how you can modify the gated clock design to use the clock enable pin of the CLB Figure 3 7 shows this design implemented with gates 70 wwWwW xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Coding for Synthesis XILINX VHDL Example P GATI CLOCK V
301. n Design Guide www xilinx com 97 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Verilog example Using a DCM for Virtex II The following code passes the attribute for the synthesis tools Synplify FPGA Compiler II LeonardoSpectrum and XST module clock_top clk_pad rst_dll Verilog clk_out locked input clk_pad spread spectrum yes rst dll output clk out locked wire clk clk int clk dcm IBUFG ul I clk pad O clk int DCM u2 CLKFB clk CLKIN clk int DSSEN spread spectrum yes PSCLK 1 b0 PSE 1 b0 PSINCDEC 1 b0 RST rst dll CLKO clk dom LOCKED locked synthesis CLKIN PERIOD 10 synopsys attribute CLKIN PERIOD 10 exemplar attribute u2 CLKIN PERIOD 10 synthesis attribute CLKIN PERIOD of u2 is 10 BUFG u3 I clk dcm O clk assign clk out clk endmodule clock top Attaching Multiple Attributes to CLKDLL and DCM CLKDLLs and DCMs can be configured to various modes by attaching attributes during instantiation In some cases multiple attributes must be attached to get the desired configuration The following HDL coding examples show how to attach multiple attributes to DCM components The same method can be used to attach attributes to CLKDLL components See the Libraries Guide for available attributes for Virte
302. n a generic specification is all that is needed to specify the INIT value to the implementation tools If the synthesis tool cannot pass attributes via generics then the generic and generic map portions of the code must be omitted for synthesis by the use of translate off and translate on synthesis directives and the INIT values must be passed using the attribute notation entity design is port list goes here end entity design architecture toplevel of designs component SRL16 generic INIT BIT VECTOR X 0000 port D in STD ULOGIC CLK in STD ULOGIC A0 in STD ULOGIC Al in STD ULOGIC A2 in STD ULOGIC A3 in STD ULOGIC Q out STD ULOGIC end component signal declarations go here begin UO SRL16 generic map INIT gt X 1100 port map CLK CLK rest of port maps end toplevel In the example above the INIT attribute is passed down to the simulation model through the generic map 252 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulating Verilog XILINX Simulating Verilog Defining Global Signals in Verilog The global set reset and global tristate signals are defined in the SXILINX verilog src glbl v module The VHDL UNISIM library contains the ROC ROCBUF TOC TOCBUF and STARTBUF cells to assist in VITAL VHDL simulation of the global set reset and tristate signals However Verilog allows a global signal t
303. n a report of device resource utilization Some synthesis tools provide area reports automatically Refer to your synthesis tool documentation for correct command syntax The device utilization and performance report lists the compiled cells in your design as well as information on how your design is mapped in the FPGA These reports are generally accurate because the synthesis tool creates the logic from your code and maps your design into the FPGA However these reports are different for the various synthesis tools Some reports specify the minimum number of CLBs required while other reports specify the unpacked number of CLBs to make an allowance for routing For an accurate comparison compare reports from the Xilinx place and route tool after implementation Also any instantiated components such as CORE Generator modules EDIF files or other components that your synthesis tool does not recognize during compilation are not 34 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Evaluating Design Size and Performance XILINX included in the report file If you include these components in your design you must include the logic area used by these components when estimating design size Also sections of your design may get trimmed during the mapping process and may result in a smaller design Using the Timing Report Command Use your synthesis tool s timing report command to obtain a report with estimate
304. n std logic CUP CDOWN out std logic vector 3 downto 0 end EX ROCBUF architecture A of EX ROCBUF is signal GSR std logic signal COUNT UP COUNT DOWN std logic vector 3 downto 0 component ROCBUF port I in std logic O out std logic end component begin Ul ROCBUF port map I gt SRP O gt GSR UP_COUNTER process CLOCK ENABLE GSR begin if GSR 1 then COUNT UP lt 0000 elsif CLOCK event AND CLOCK 1 then if ENABLE 1 then COUNT UP lt COUNT UP 0001 end if end if end process UP COUNTER 234 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulating VHDL lt XILINX DOWN_COUNTER process CLOCK ENABLE GSR COUNT_DOWN begin if GSR 1 OR COUNT DOWN 0101 then COUNT_DOWN lt 1111 elsif CLOCK event AND CLOCK 1 then if ENABLE 1 then COUNT DOWN lt COUNT DOWN 0001 end if end if end process DOWN COUNTER CUP lt COUNT UP CDOWN lt COUNT DOWN end A The following figure shows the progression of the ROCBUF model and its interpretation in the four main design phases 1 Behavioral 2 Synthesized Inferred g e FDCE D Q D Q D Q CK CK C R C S CK R ROCBUF ROCBUF gt GSR gt Local Set 3 Implemented 4 Back Annotated FDPE D Q CK GSR R GSR G
305. nals should be generated in complex if else statements The following examples use an If construct in a 4 to 1 multiplexer design www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Coding for Synthesis XILINX 4 to 1 Multiplexer Design with If Construct e VHDL Example IF EX V HD library IE EE use IEEE o use IEEE s entity if ex is port SEL A B CDs MUX_OUT end if_ex architecture BI begin td logic 1164 all td logic unsigned all in STD LOGIC VECTOR 1 downto 0 in STD LOGIC out STD LOGIC EHAV of if ex is IF PRO process SEL A B C D begin if S elsif MU elsif MU elsif MU else MU end i end process end BEHAV EL 00 then MUX OUT lt A SEL 01 then X OUT B SEL 10 then X OUT lt C SEL 11 then X OUT D X OUT lt 0 f END IF PRO Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 59 2 XILINX Chapter 3 General HDL Coding Styles Verilog Example VII P P ll lll ll lb lll All M I Pg P PPP PPP PPP M MM P MM IF EX V Example of a If statement showing a max created using priority encoded logic HDL Synthesis Design Guide for FPGAs HMHUEUMUMLBMlllllll ll l ll I P Malle l P L P gg M lll b gl ld module if ex A B C D SEL
306. nd Readback The Boundary Scan and Readback circuitry cannot be simulated at this time Generics Support Considerations Some synthesis tools do not support the use of generics to attach attributes If your synthesis tool does not support generics use the special meta comment to make the code visible only to the simulator Place the meta comments immediately before and after the generic declarations and mappings as follows synthesis translate off generic INIT std logic vector 1 downto 0 synthesis translate off 10 The attributes can then be passed to the implementation tools by defining them in the UCF file Alternatively the synthesis tool may support a mechanism to pass these attributes 244 www xilinx com 1 800 255 7778 Synthesis and Verification Design Guide Simulating VHDL lt XILINX directly from the VHDL file without using the generics Please see your synthesis tool documentation for specific details on attribute passing for your synthesis tool Differential O LVDS LVPECL When targeting a Virtex E or Spartan IIE device the inputs of the differential pair are currently modeled with only the positive side whereas the outputs have both pairs positive and negative For details please refer to Xilinx Answer Record 8187 on the Xilinx support web sit at http support xilinx com for more details This is not an issue for the Virtex I TI Pro II Pro X or Spartan 3 architecture as the di
307. nd circuitry that connects to every register in the device The dedicated global GSR Global Set Reset net is asserted and is released during configuration immediately after the device is configured All the flip flops and latches receive this reset and are either set or reset depending on how the registers are defined Although designers can access the GSR net after configuration Xilinx does not recommend using the GSR circuitry in place of a manual reset This is because the FPGAs offer high speed backbone routing for high fanout signals like a system reset This backbone route is faster than the dedicated GSR circuitry and is easier to analyze than the dedicated global routing that transports the GSR signal In back end simulations a GSR signal is automatically pulsed for the first 100 ns to simulate the reset that occurs after configuration A GSR pulse can optionally be supplied in front end functional simulations but is not necessary if the design has a local reset that resets all registers When creating a test bench it is important to remember that the GSR pulse occurs automatically in the back end simulation as this will hold all registers in reset for the first 100 ns of the simulation For more information about controlling the GSR pulse or inserting a GSR pulse in the front end simulation see the Simulating VHDL and Simulating Verilog sections In addition to the dedicated global GSR all output buffers are set to a high imp
308. nd code set may differ slightly from the simulator syntax and code set Compiling Large Designs Older versions of synthesis tools required incremental design compilations to decrease run times Some or all levels of hierarchy were compiled with separate compile commands and saved as output or database files The output netlist or compiled database file for each module was read during synthesis of the top level code This method is not necessary with new synthesis tools which can handle large designs from the top down The 5 000 gates per module rule of thumb no longer applies with the new synthesis tools Refer to your synthesis tool documentation for details Saving Compiled Design as EDIF After your design is successfully compiled save it as an EDIF file for input to the Xilinx software www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Setting Constraints XILINX Reading COREs Synplify Pro LeonardoSpectrum and XST support the reading in of CORE Generator EDIF files for timing and area analysis When these tools read in the EDIF files better timing optimizations can be done since the delay through the logic elements inside of the CORE file will be known The procedure for reading in COREs in these synthesis tools are as follows e XST Invoke XST using the read_cores switch When the switch is set to on the default XST reads in EDIF and NGC netlists Please refer to the XST User Guide for mor
309. nd logic verification methodologies must be explored to expedite the verification of design logic and functionality Because of its accuracy and speed logic equivalency checking also known as formal verification is quickly gaining acceptance by designers creating multi million gate designs Formal verification requires the presence of a golden verified reference design and checks the netlists from the design under development for logic equivalence with this golden standard Typically the golden reference design will be the RTL design and it will be verified against the post synthesis and post place and route netlists This will ensure that any transformations done by the synthesis tool or the Xilinx implementation tools have not affected the functionality of the design Software and Device Support Supported Equivalency Checking Software Xilinx supports the following equivalency checking software e Synopsys Formality e Verplex Conformal FPGA Synthesis and Verification Design Guide www xilinx com 281 1 800 255 7778 XILINX Chapter 7 Equivalency Checking Supported Synthesis Tools Xilinx supports equivalency checking with the following synthesis tools e Synopsys FPGA Compiler II for use with Formality and Conformal FPGA e Synplicity Synplify Pro 7 2 or later for use with Conformal FPGA Supported Devices Xilinx supports equivalency checking for the following technologies e Spartan II
310. ned at the following locations Table 1 2 Vendor Support Sites Vendor Name Telephone Electronic Mail Website Synopsys 1 800 245 8005 support_center synopsys com www synopsys com Cadence Concept 1 877 237 4911 support cadence com sourcelink cadence com HDL Mentor Graphics 1 800 547 4303 support_net mentor com www mentor com Synplicity 1 408 548 6000 support synplicity com www synplicity com 24 www xilinx com 1 800 255 7778 Synthesis and Verification Design Guide XILINX Chapter 2 Understanding High Density Design Flow This chapter describes the steps in a typical HDL design flow Although these steps may vary with each design the information in this chapter is a good starting point for any design This chapter includes the following sections Design Flow Entering your Design and Selecting Hierarchy Functional Simulation of your Design Synthesizing and Optimizing your Design Setting Constraints Evaluating Design Size and Performance Evaluating your Design for Coding Style and System Features Modular Design and Incremental Design ECO Placing and Routing Your Design Timing Simulation of Your Design Synthesis and Verification Design Guide www xilinx com 25 1 800 255 7778 XILINX Chapter 2 Understanding High Density Design Flow Design Flow An overview of the design flow steps is sh
311. nerated based on CLKFX_MULTIPLY and CLKFX_DIVIDE attributes These outputs do not have phase correction with respect to CLKIN Debugging Timing Problems In back annotated timing simulation the simulator takes into account timing information that resides in the standard delay format SDF file This may lead to eventual timing violations issued by the simulator if the circuit is operated too fast or has asynchronous components in the design This section explains some of the more common timing violations and gives advice on how to debug and correct them Identifying Timing Violations After you run timing simulation check the messages generated by your simulator If you have timing violations they are indicated by warning or error messages The following example is a typical setup violation message from MTI ModelSim for a Verilog design Message formats vary from simulator to simulator but all contain the same basic information See your simulator documentation for details Error path to xilinx verilog src simprims X RAMD16 v 96 Ssetup negedge WE 29138 ps posedge CLK 29151 ps 373 ps Time 29151 ps Iteration 0 Instance test_bench ul U1 X_RAMD16 e The first line points to the line in the simulation model that is in error In the example above the failing line would be line 96 of the Verilog file X_RAMD16 Synthesis and Verification Design Guide www xilinx com 265 1 800 255 7778 lt XILINX 266
312. ng This is an example of the same data path in the previous example after pipelining Because the flip flop is contained in the same CLB as the function generator the clock speed is limited by the clock to out time of the source flip flop the logic delay through one level of logic one routing delay and the setup time of the destination register In this example the system clock runs much faster than in the previous example Function Function Generator Fast Clock X8340 Figure 4 8 After Pipelining 188 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Design Hierarchy Z XILINX Design Hierarchy HDL designs can either be synthesized as a flat module or as many small modules Each methodology has its advantages and disadvantages but as higher density FPGAs are created the advantages of hierarchical designs outweigh any disadvantages Advantages to building hierarchical designs are as follows e Easier and faster verification simulation e Allows several engineers to work on one design at the same time e Speeds up design compilation e Reduces design time by allowing design module re use for this and future designs e Allows you to produce designs that are easier to understand e Allows you to efficiently manage the design flow Disadvantages to building hierarchical designs are as follows e Design mapping into the FPGA may not be as optimal across hierarchical boundaries this can cause
313. ng is begin Pl process A1 B1 C1 D1 COND 1 begin if COND 1 1 then Z1 lt Al Bl else Z1 lt C1 D1 end if end process end Pl end BEHAV 66 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Coding for Synthesis XILINX Verilog Example Resource Sharing Example RES_SHARING V ri module res sharing Al Bl Cl Dl COND 1 Z1 input COND 1 input 7 0 Al Bl Cl Dl output 7 0 Z1 reg 7 0 21 always Al or Bl or Cl or D1 or COND 1 begin if COND 1 Zl lt Al Bl else Z1 lt C1 D1 end endmodule If you disable resource sharing or if you code the design with the adders in separate processes the design is implemented using two separate modules as shown in Figure 3 5 UN4_Z1 7 0 gt oro ao z1 7 0 Z1 5 7 0 Z1 1 7 0 nr Figure 3 5 Implementation without Resource Sharing Note Refer to the appropriate reference manual for more information on resource sharing Reducing Gate Count Use the generated module components to reduce the number of gates in your designs The module generation algorithms use Xilinx carry logic to reduce function generator logic and improve routing and speed performance Further gate reduction can occur with synthesis tools that recognize the use of constants with the modules You can reduce the number of gates further by mapping your design onto dedicated logi
314. ng the Use of Ports Declared as Buffers Do not use buffers when a signal is used internally and as an output port In the following VHDL example signal C is used internally and as an output port Entity alu is port A in STD LOGIC VECTOR 3 downto 0 B in STD LOGIC VECTOR 3 downto 0 CLK in STD LOGIC C buffer STD LOGIC VECTOR 3 downto 0 end alu architecture BEHAVIORAL of alu is begin process begin if CLK event and CLK 1 then C lt UNSIGNED A UNSIGNED B UNSIGNED C end if end process end BEHAVIORAL Synthesis and Verification Design Guide www xilinx com 53 1 800 255 7778 2 XILINX Chapter 3 General HDL Coding Styles Because signal C is used both internally and as an output port every level of hierarchy in your design that connects to port C must be declared as a buffer However buffer types are not commonly used in VHDL designs because they can cause problems during synthesis To reduce the amount of buffer coding in hierarchical designs you can insert a dummy signal and declare port C as an output as shown in the following VHDL example Entity alu is port A in STD_LOGIC_VECTOR 3 downto 0 B in STD LOGIC VECTOR 3 downto 0 CLK in STD LOGIC C out STD LOGIC VECTOR 3 downto 0 end alu architecture BEHAVIORAL of alu is dummy signal Signal C INT STD LOGIC VECTOR 3 downto 0 begin C lt C INT pr
315. ngs including encoding CRC and clock e Provides the ability to specify General Receptor Settings including encoding CRC and clock e Provides the ability to specify Synchronization e Provides the ability to specify Equalization Signal integrity tip resister termination mode e Provides the ability to view and edit component attributes e Provides the ability to view and edit component constraints e Provides the ability to automatically place one component in the XAW file e Provides the ability to save component settings to a VHDL file e Provides the ability to save component settings to a Verilog file CORE Generator The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx FPGAs It provides you with a catalog of ready made functions ranging in complexity from simple arithmetic operators such as adders accumulators and multipliers to system level building blocks such as filters transforms FIFOs and memories For each core it generates the CORE Generator System produces an Electronic Data Interchange Format EDIF netlist EDN file a Verilog template VEO file with a Verilog V wrapper file and or a VHDL template VHO file with a VHDL VHD wrapper file It 28 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Functional Simulation of your Design Z XILINX may also create one or more NGC and NDF files NGC files are produced for c
316. nment variables that you must set before using Synopsys Formality to verify a Xilinx design 282 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Conformal FPGA and Synplify Pro Flow lt XILINX Table 7 1 Environment Variables Needed to Set Up Synopsys Formality and Xilinx Name of Variable Location Pointed by the Variable Synopsys Variables LM_LICENSE_FILE port license_server or license_install_directory license_file PATH formality_install_dir fm bin Spath Xilinx Variables XILINX xilinx_install_directory PATH SXILINX bin sol Spath Synopsys also uses a setup file for each project Create this setup file in the project directory by copying the template from SXILINX verilog formality template synopsys_fm setup and renaming it to synopsys_fm setup For more information on the use and customization possibilities of the synopsys_fm setup file contact Synopsys Setup for Verplex Conformal FPGA Following is a table of the environment variables that you must set before using Verplex Conformal FPGA to verify a Xilinx design Table 7 2 Environment Variables Needed to Set Up Verplex Conformal FPGA and Xilinx Name of Variable Location Pointed by the Variable Synopsys Variables VERPLEX_HOME conformal_lec_install_directory LM_LICENSE_FILE port license_server or license_install_directory lice
317. nput we wclk input d width 1 0 d input addr width 1 0 addr reg d width 1 0 mem 1 addr width 1 0 Synthesis and Verification Design Guide www xilinx com 175 1 800 255 7778 176 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X always posedge wclk if we mem addr d assign o mem addr endmodule Implementing ROMs ROMs can be implemented as follows e Use RTL descriptions of ROMs e Instantiate 16x1 and 32x1 ROM primitives Following are RTL VHDL and Verilog ROM coding examples RTL Description of a Distributed ROM VHDL Example Note LeonardoSpectrum does not infer ROM Use the following coding example for FPGA Compiler II Synplify and XST Behavioral 16x4 ROM Example rom rtl vhd library IEEE use IEEE std logic 1164 a11 entity rom rtl is port ADDR in INTEGER range 0 to 15 DATA out STD LOGIC VECTOR 3 downto 0 end rom rtl architecture XILINX of rom rtl is subtype ROM WORD is STD LOGIC VECTOR 3 downto 0 type ROM TABLE is array 0 to 15 of ROM WORD constant ROM ROM TABLE ROM TABLE ROM WORD 0000 ROM WORD 0001 ROM WORD 0010 ROM WORD 0100 ROM WORD 1000 ROM WORD 1100 ROM WORD 1010 ROM WORD 1001 ROM WORD 1001 ROM WORD 10
318. ns that can occur Glitches in your Design 262 When a glitch small pulse occurs in an FPGA circuit or any integrated circuit the glitch may be passed along by the transistors and interconnect transport in the circuit or it may be swallowed and not passed internal to the next resource in the FPGA This depends on the width of the glitch and the type of resource the glitch passes through To produce more accurate simulation of how signals are propagated within the silicon Xilinx models this behavior in the timing simulation netlist For Verilog simulation this information is passed by the PATHPULSE construct in the SDF file This construct is used to specify the size of pulses to be rejected or swallowed on components in the netlist For VHDL there are two library components called X_BUF_PP and X_TRI_PP in which proper values are annotated www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Timing Simulation lt XILINX for pulse rejection in the simulation netlist The result of these constructs in our simulation netlists is a more true to life simulation model and so a more accurate simulation CLKDLL DCM Clocks do not appear de skewed The CLKDLL and DCM components remove the clock delay from the clock entering into the chip As a result the incoming clock and the clocks feeding the registers in the device have a minimal skew within the range specified in the Databook for any given device However in
319. nse_file PATH SVERPLEX HOME bin path Xilinx amp Variables XILINX xilinx install directory PATH SXILINX bin sol path Conformal FPGA and Synplify Pro Flow When using Synplify Pro in verification mode and targeting a Xilinx FPGA you can use Conformal FPGA to verify that the golden RTL design and the post synthesis netlist are logically equivalent When verification mode is turned on Synplify Pro produces a netlist for verification and several files that you can use to run the verification in Conformal FPGA These files from Synplify Pro help automate the RTL to the post synthesis verification process Synthesis and Verification Design Guide www xilinx com 283 1 800 255 7778 lt XILINX Chapter 7 Equivalency Checking After verifying that the post synthesis netlist is logically equivalent to the golden RTL design the post synthesis netlist is considered the golden netlist and can be compared against the post place and route netlist to verify that it is also logically equivalent Figure 7 1 shows the Conformal FPGA Synplify Pro Flow for equivalency checking Synplify Pro Annotations ISE Alliance Post Synthesis netlist Post PAR netlist X10000 Figure 7 1 Conformal FPGA and Synplify Pro Logic Equivalency Checking flow Golden l Conformal FPGA Equivalence Checker RTL vs Post Synthesis 284 The first transformation of
320. nt variable Please note that if you have multiple simulator installation versions on your system or if you do not have the simulator executable path defined in your environment variable you can use this option to specify the executable path to your appropriate simulator Synthesis and Verification Design Guide www xilinx com 215 1 800 255 7778 2 XILINX Chapter 6 Verifying Your Design Overwrite Compiled Library The Overwrite Compiled Library property allows you to overwrite the previously compiled library Select the check box in the Value field to enable overwriting By default the check box is checked Compile library_name Library This is a list of libraries that allows you to select or deselect the libraries that you want to compile By default all the libraries will be selected Please note that the list of libraries depends upon the type of device family selected in the Project Properties Click OK The Compile HDL Simulation Libraries properties are now set Double click Compile HDL Simulation Libraries Project Navigator will now compile the libraries using the properties specified in the properties you have set After the process is completed double click View Compilation Log to open the COMPXLIB log file to view the compilation results From Command Line To compile libraries type the following on the command line compxlib options See COMPXLIB Syntax for options and syntax details To view
321. ntains device specific information on Xilinx device characteristics including readback boundary scan configuration length count and debugging http www support xilinx com xlnx xweb xil publications inde xjsp Problem Solvers Interactive tools that allow you to troubleshoot your design issues http support xilinx com support troubleshoot psolvers htm Tech Tips Latest news design tips and patch information for the Xilinx design environment http www support xilinx com xlnx xil tt home jsp Conventions This document uses the following conventions An example illustrates each convention Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Messages prompts and Courier font program files that the system speed grade 100 displays Courier bold Literal ends mat you ngdbuild design_name enter in a syntactical statement iced that you select File gt Open Helvetica bold OTTAEN Keyboard shortcuts Ctrl C 6 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Conventions XILINX Convention Italic font Meaning or Use Variables in a syntax statement for which you must supply values Example ngdbuild design name References to other manuals See the Development System Reference Guide for more information Emphasis in text If a wire is drawn so th
322. nted in the available CLBs Using IOBs also improves design performance by increasing the number of available routing resources The Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X Spartan II and Spartan 3 IOBs feature SelectIO inputs and outputs that support a wide variety of I O signaling standards In addition each IOB provides three storage elements The following sections discuss IOB features in more detail 118 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Inputs and Outputs lt XILINX I O Standards The following table summarizes the I O standards supported in Virtex E II II Pro 1I Pro X and Spartan II 3 devices A complete table is available in the Libraries Guide Table 4 3 VO Standard in Virtex E II and Spartan II Devices VirtexT II Il Pro Virtex E II Pro X Spartan 3 LVTTL default AGP CTT y o Virtex Standard Spartan II7 GTL GTLP HSTLClass I HSTL Class II HSILClass III HSILClass IV LVCMOS2 LVCMOS1 5 LVCMOS1 8 LVCMOS2 5 33 LVCZ_15 18 25 33 LVCZ_DV2 _15 18 25 33 LVDS LVPECL PCI33_5 PCI33 3 PCI66_3 PCIX Synthesis and Verification Design Guide www xilinx com 119 1 800 255 7778 120 Input
323. nts that are built in to the implementation software s library are available for instantiation without the need for specifying a definition These components are marked as primitive in the Libraries Guide Components marked as macro in the Libraries Guide are not built into the implementation software s library so they cannot be instantiated The macro components in the Libraries Guide define the schematic symbols When macros are used the schematic tool decomposes the macros into their primitive elements when the schematic tool writes out the netlist FPGA primitives can be instantiated in VHDL and Verilog e VHDL example declaring component and port map library IEEE use IEEE std_logic_1164 all Add the following two lines if using Synplify library virtex use virtex components all entity flops is port di in std logic ce in std logic clk in std logic qo out std logic rst in std logic end flops remove the following component declaration if using Synplify 76 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Instantiating Components Instantiating lt XILINX architecture inst of flops is component FDCE port D dn std Logic CE in std logic C in std logic CLR in std logic Q out std logic end component begin UO FDCE port map D gt di CE gt ce C gt clk CLR gt rst Q gt qo en
324. o Running the DO File in Conformal FPGA Follow these steps to run the verification 1 Ensure that the Xilinx and Verplex environment variables are properly set up Setup for Synopsys Formality and Verplex Conformal FPGA for more information cd verification directory lec dofile dofile_name do Using CORE Generator Components with Conformal RTL vs Post PAR Verification When using CORE Generator components the contents of the cores are read in during NGDBuild the first stage of the Xilinx implementation process The cores are then implemented with the rest of the design and the post PAR netlist will contain the contents of the cores The RTL design only contains black box instantiations of the cores Xilinx provides a Perl script core2 formal p1 that creates Verilog representations of the cores which can be read in as part of the reference design Usage gt xilperl SXILINX verilog bin platform core2formal pl vendor family coregen module e For Conformal the vendor option must be verplex 298 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Conformal FPGA and FPGA Compiler II Flow XILINX e The family option can be virtex virtexe virtex2 virtex2p spartan2 spartan2e or spartan3 e The Perl script runs the following commands ngdbuild p family coregen_module edn netgen ecn conformal coregen module ngd coregen module for v The output
325. o be modeled as a wire in a global module and thus does not contain these cells Using the glbl v Module The g1b1 v module connects the global signals to the design which is why it is necessary to compile this module with the other design files and load it along with the design v file and the test fixture v file for simulation Note n previous releases of the software the g151 v file only declared the global signals In the 6 1i release code has been added to the g1b1 v file that automatically pulses GSR for 100 ns at the beginning of simulation The following is the definition of the glb1 v file timescale 1 ps 1 ps module glbl parameter ROC WIDTH 100000 parameter TOC WIDTH 0 wire GSR wire GTS wire PRLD reg GSR int reg GTS int reg PRLD int assign weakl weak0 GSR GSR int assign weakl weak0 GTS GTS int assign weakl weak0 PRLD PRLD int initial begin GSR int 1 bl PRLD int 1 b1 ROC WIDTH GSR int 1 b0 PRLD int 1 b0 initial begin GTS int 1 bl TOC WIDTH GTS int 1 b0 end endmodule Synthesis and Verification Design Guide www xilinx com 253 1 800 255 7778 XILINX Chapter 6 Verifying Your Design Defining GSR GTS in a Test Bench In most cases GSR and GTS need not be defined in the test bench The g1b1 v file declares the global GSR and GTS signals and automatically pulses GSR for 100 ns This is all that is necessary fo
326. o the element outputs an X to represent an unknown value The X output remains until the next clock cycle in which the next clocked value updates the output if another violation does not occur Sometimes this situation can have a drastic affect on simulation For example an X generated by one register can be propagated to others on subsequent clock cycles causing large portions of the design under test to become unknown If this happens on a synchronous path in the design you can ensure a properly operating circuit by analyzing the path and fixing any timing problems associated with this or other paths in the design If however this path is an asynchronous path in the design and you cannot avoid timing violations you can disable the X propagation on synchronous elements during timing Synthesis and Verification Design Guide www xilinx com 227 1 800 255 7778 lt XILINX 228 Chapter 6 Verifying Your Design violations so that these elements do not output an X When X propagation is disabled the previous value is retained at the output of the register Please understand that in the actual silicon the register may have very well changed to the new value and that disabling X propagation may yield simulation results that do not match the silicon behavior Exercise caution when using this option you should only use it when you cannot otherwise avoid timing violations Using the ASYNC_REG Attribut
327. oard level simulation For example if you use an integer type for ports for one circuit and standard logic for ports for another circuit your design can be synthesized however you need to perform time consuming type conversions for a board level simulation The back annotated netlist from Xilinx implementation is in Std logic If you do not use Std logic type to drive your top level entity in the test bench you cannot reuse your functional test bench for timing simulation Some synthesis tools can create a wrapper for type conversion between the two top level entities however this is not recommended by Xilinx Declaring Ports Xilinx recommends that you use the Std_logic package for all entity port declarations This package makes it easier to integrate the synthesized netlist back into the design hierarchy without requiring conversion functions for the ports The following is a VHDL example using the Std_logic package for port declarations Entity alu is port A in STD_LOGIC_VECTOR 3 downto 0 B in STD_LOGIC_VECTOR 3 downto 0 CLK in STD_LOGIC C out STD LOGIC VECTOR 3 downto 0 end alu Since the downto convention for vectors is supported in a back annotated netlist the RTL and synthesized netlists should use the same convention if you are using the same test bench This is necessary because of the loss of directionality when your design is synthesized to an EDIF netlist Minimizi
328. ocess begin if CLK event and CLK 1 then C INT lt UNSIGNED A UNSIGNED B UNSIGNED C INT end if end process end BEHAVIORAL Comparing Signals and Variables VHDL only 54 You can use signals and variables in your designs Signals are similar to hardware and are not updated until the end of a process Variables are immediately updated and as a result can affect the functionality of your design Xilinx recommends using signals for hardware descriptions however variables allow quick simulation The following VHDL examples show a synthesized design that uses signals and variables respectively These examples are shown implemented with gates in the Gate Implementation of XOR VAR and Gate Implementation of XOR SIG figures Note f you assign several values to a signal in one process only the final value is used When you assign a value to a variable the assignment takes place immediately A variable maintains its value until you specify a new value www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Choosing Data Type VHDL only Z XILINX Using Signals VHDL XOR_SIG VH Library IEEE use IEEE std_logic_1164 all entity xor_sig is port C in STD LOGIC out STD LOGIC A X end xor sig architecture SIG ARCH of xor sig is signal D STD LOGIC begin SIG process A B C begin D lt A
329. ock drives the GSR net and connects to each flip flop s Preset and Clear pin When you connect a signal from a pad to the STARTUP block s GSR pin the GSR net is activated Because the GSR net is built into the silicon it does not appear in the pre routed netlist file When the GSR signal is asserted High the default all flip flops and latches are set to the state they were in at the end of configuration When you simulate the routed design the gate simulator translation program correctly models the GSR function See Chapter 6 Verifying Your Design for more information on STARTUP and STARTBUF Note The following VHDL and Verilog example shows a STARTUP_VIRTEX instantiation using both GSR and GTS pins for FPGA Compiler II LeonardoSpectrum and XST 112 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Using Dedicated Global Set Reset Resource lt XILINX e VHDL example This example uses both GTS and GSR pins Unconnected STARTUP pins are omitted from declaration component library IEEE use IEEE std logic 1164 a1 entity setreset is port CLK in std logic DIN1 in STD LOGIC DIN2 in STD LOGIC RESET in STD LOGIC GTSInput in STD LOGIC DOUT1 out STD LOGIC DOUT2 out STD LOGIC DOUT3 out STD LOGIC end setreset architecture RTL of setreset is component STARTUP VIRTEX port GSR GTS in std logic end component begin startup inst STARTUP VIRTEX port map GSR
330. og Example VUALA LLANASA TIA Be TTA STAT TTA TATA TTA TTT BINARY V Version 1 0 Example of a binary encoded state machine HMOIMMLMBMl MM P BP MIMIMIMMMPMPMIKMMLIMMMIB B II P gl TTT module binary CLOCK RESET A B C D E SINGLE lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan Il 3 Virtex E I II Pro II Pro X MULTI CONTIG input CLOCK RESET r input A B C D E output SINGLE ULTI CONTIG reg SINGLE ULTI CONTIG Declare the symbolic names for states parameter 2 0 S1 3 b001 S2 3 b010 S3 3 b011 S4 3 b100 S5 3 b101 S6 3 b110 S7 3 b111 Declare current state and next state variables reg 2 0 CS reg 2 0 NS state vector CS always 8 posedge CLOCK or posedge RESET begin if RESET 1 b1 CS lt S1 else CS NS end always CS or A or B or C or D or D or E begin case CS S1 begin MULTI 1 50 CONTIG 1 b0 SINGLE 1 b0 if A amp amp B amp amp C NS S2 else if A amp amp B amp amp C S S4 else NS S1 end S23 begin MULTI 1 bl CONTIG 1 b0 SINGLE 1 b0 if D NS S3 else S S4 end www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Encoding State Machines XILINX S3 begin MULTI 1 50 CONTIG 1
331. om 191 1 800 255 7778 XILINX Chapter 5 Virtex Il Pro Considerations Simulation Components The Virtex II Pro device consists of several components Each component has its own simulation model and the individual simulation models must be correctly interconnected to get the simulation to work as expected Following are the components that need to be simulated e FPGA Logic This consists of either the RTL design constructed by the designer or the back annotated structural design created by the Xilinx implementation tools IBM PowerPC microprocessor The microprocessor is simulated using SWIFT interface RocketlO This is simulated using SWIFT interface Overview of Virtex Il Pro Simulation Flow The HDL simulation flow using Synopsys SmartModels consists of three steps 1 Instantiate the PowerPC and or RocketlIO wrapper used for simulation and synthesis During synthesis the PowerPC and the transceiver are treated as black box components This requires that a wrapper be used that describes the modules port 2 Install the SmartModels if needed See Installing SmartModels from Xilinx Implementation Tools for details on installing SmartModels 3 Usethe SmartModels along with your design in an HDL simulator that supports the SWIFT interface You can find the instantiation wrapper files for the PowerPC and RocketIO in the Virtex II Pro Platform FPGA Developers Kit and the RocketIO User Gui
332. on Design Guide www xilinx com 225 1 800 255 7778 XILINX Chapter 6 Verifying Your Design writes the full path of the current work directory and the SDF file name to the sdf_annotate file The default path for the SDF file is in the same directory in which the Verilog simulation netlist resides Global Disable of X generation for Simulation VHDL Only This option is used to disable X generation by all registers in the design when a timing violation occurs If this option is set all registers in the design retain their last value when a timing violation occurs For more information on this option refer to Disabling X Propagation in this manual The default value for this option is OFF Generate Architecture Only No Entry Declaration Specifies whether to create an entity for each level of hierarchy in the design or whether to generate the architecture portion only This option is useful when generics are declared in the top level entity declaration in the original RTL design as it allows the re use of the original entity declaration for proper linking of the structural design to the test bench file By default this property is set to False checkbox is unchecked and both entity and architectures are created in the resulting netlist Other NetGen Command Line Options This allows the user to specify options for NetGen that are not available from the above options 4 Double click Generate Post Place
333. onent ROCBUF is port I in STD LOGIC O r out STD LOGIC end component begin U1 ROCBUF port map I RESET O gt RESET int process CLK RESET int begin if RESET int 1 then Q0 0 Ql lt 1 elsif rising_edge CLK then Q0 lt DO Ql lt D1 end if end process end XILINX Synthesis and Verification Design Guide www xilinx com 117 1 800 255 7778 SZ XILINX Chapter 4 Architecture Specific Coding Styles for Spartan Il 3 Virtex E Il II Pro II Pro X e Verilog example Note In Synplify set blackbox attribute for ROCBUF as follows module ROCBUF I O synthesis syn_black_box input I output O endmodule y module ROCBUF I O input I output O0 endmodule module rocbuf example reset clk d0 dl q0 ql input reset input clk input d0 input dl output q0 output ql reg q0 ql wire reset int ROCBUF ul I reset O reset int always posedge clk or posedge reset int begin if reset int begin q0 lt 1 b0 ql lt 1 b1l end else begin q0 lt d0 ql lt dl end end endmodule Implementing Inputs and Outputs FPGAs have limited logic resources in the user configurable input output blocks IOB You can move logic that is normally implemented with CLBs to IOBs By moving logic from CLBs to IOBs additional logic can be impleme
334. or 7 downto 0 b in std logic vector 7 downto 0 Clk in std logic prod out std logic vector 15 downto 0 end xcv2 mult18x18s architecture arch xcv2 multi18x18s of xcv2 multi18x18s is begin process clk is begin if clk event and clk 1 then prod lt a b end if end process end arch xcv2 mult18x18s The following is a synchronous multiplier VHDL example coded for LeonardoSpectrum library ieee use ieee std_logic_1164 all use ieee std_logic_arith all use ieee std_logic_unsigned all entity xcv2_mult18x18s is port clk in std_logic a in std_logic_vector 7 downto 0 b in std_logic_vector 7 downto 0 prod out std_logic_vector 15 downto 0 end xcv2_mult18x18s architecture arch xcv2 multi18x18s of xcv2 multi18x18 is signal reg prod std logic vector 15 downto 0 begin process clk begin if rising edge clk then reg prod lt a b prod lt reg prod end if end process end arch xcv2 mult18x18s Synthesis and Verification Design Guide www xilinx com 147 1 800 255 7778 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X e Verilog example module multiply clk ain bin q parameter size 16 parameter level 4 input clk input size 1 0 ain bin output 2 size 1 0 q reg size 1 0 a b reg 2 size 1 0 reg bank level 1 0 integer i always posedge clk begin a l
335. or Spartan II device For specific information on boundary scan for an architecture refer to the Libraries Guide and the product Data Sheets For information on configuration and readback of Virtex Virtex E and Spartan II FPGAs see the XAPP139 Application Note Using Global Clock Buffers 78 For designs with global signals use global clock buffers to take advantage of the low skew high drive capabilities of the dedicated global buffer tree of the target device Your synthesis tool automatically inserts a clock buffer whenever an input signal drives a clock signal or whenever an internal clock signal reaches a certain fanout The Xilinx implementation software automatically selects the clock buffer that is appropriate for your specified design architecture www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Using Global Clock Buffers lt XILINX Some synthesis tools also limit global buffer insertions to match the number of buffers available on the device Refer to your synthesis tool documentation for detailed information You can instantiate the clock buffers if your design requires a special architecture specific buffer or if you want to specify how the clock buffer resources should be allocated Table 4 1summarizes global buffer BUFG resources in Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X Spartan II and Spartan 3 devices Table 4 1 Global Bu
336. ote t CORE Generator components are used see the Using CORE Generator Components with Formality RTL vs Post PAR Verification section for more information ngdbuild uc design ucf design sedif design ngd map design ngd o design_map ncd par w design map ncd design ncd design map pcf netgen ecn formality ngm design map ngm w design ncd design postpar ecn v fIf using Coregen run the following for each core in the design xilperl SXILINX verilog bin sol core2formal pl formality family core name NetGen is a new application It combines NGDANNO NGD2VHDL and NGD2VER into a single application Using the ecn formality switch NetGen will write out a Verilog netlist that is compatible with the Formality tool In addition to creating the Verilog netlist NetGen creates an assertion file that tells Formality if any ports were optimized away or optimized from bi directional ports to just input or just output ports It also tells Formality if any registers were optimized to constants The assertion file name will be design ecn svf and should be read by Formality to prevent any verification failures because of optimizations done by the Xilinx implementation tools www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Formality and FPGA Compiler IIT Flow XILINX Creating a Script File to Run RTL vs Post PAR Verification Following is a sample script file for running RTL vs post
337. ou must specify a positive integer to stimulate the component properly This option is disabled if you are controlling the global reset via a port using the Bring Out Global Set Reset Net as a Port option For more information on this option see the Understanding the Global Reset and Tristate for Simulation section By default the ROC pulse width is set to 100 ns Rename Design Instance in Testbench File To This option specifies the name of the top level design instance name appearing within the output test bench template file if the Generate Testbench Testfixture File option is selected The option allows you to match the top level instance name to the name specified in your RTL test bench file The default name for the test bench instance is UUT Include uselib Directive in Verilog File Verilog Only The Include uselib Directive in Verilog File property causes ISE to write a library path pointing to the SIMPRIM library into the output Verilog v file In general Xilinx only suggests that you use this option with the Verilog XL simulator when simulations are performed on the same network as where the ISE software exists By default this field is set to Off checkbox is blank Path Used in SDF_annotate Verilog Only This option allows you to specify a path to the SDF file that you want written to the sdf_annotate function in the Verilog netlist file If a full path is not specified it Synthesis and Verificati
338. owever only writes a single value for all three fields in the SDF file for simulation By default Xilinx uses the worst case values for the speed grade of the target architecture at the maximum operating temperature the minimum voltage and various process variations to populate the MAX TYP and MIN delay sets in the SDF file This value set is used for most timing simulation runs to test circuit operation and timing Optionally NetGen can produce absolute minimum delay values for simulation by applying the s min switch The resulting SDF file produced from NetGen has the absolute process minimums populated in all three SDF fields MIN TYP and MAX Absolute process MIN values are the absolute fastest delays that a path can run in the target architecture given the best operating conditions within the specifications of the architecture lowest temperature highest voltage best possible silicon Generally these process minimum delay values are only useful for checking board level chip to chip timing for high speed data paths in best worst case conditions By default the worst case delay values are derived from the worst temperature voltage and silicon process for a particular target architecture If better temperature and voltage characteristics can be ensured during the operation of the circuit you can use prorated worst case values in the simulation to gain better performance results The default would apply worst case timing values over
339. own in the following figure Entering your Design and Selecting Hierarchy Functional Simulation of your Design Synthesizing and Optimizing your Design Adding Design Constraints Evaluating your Design s Coding Style and System Features Timing Simulation Static Timing of your Design Analysis Evaluating your Design Size and Performance Placing and Routing your Design Downloading to the Device In System Debugging Creating a PROM File for Stand Alone Operation X9203 Figure 2 1 Design Flow Overview Entering your Design and Selecting Hierarchy The first step in implementing your design is creating the HDL code based on your design criteria Design Entry Recommendations The following recommendations can help you create effective designs 26 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Entering your Design and Selecting Hierarchy XILINX Using RTL Code By using register transfer level RTL code and avoiding when possible instantiating specific components you can create designs with the following characteristics Note n some cases instantiating optimized CORE Generator or LogiCORE modules is beneficial with RTL e Readable code e Faster and simpler simulation e Portable code for migration to different device families e Reusable code for future designs Carefully Select Design Hierarchy Selecting the correct desi
340. perty RAM16X1S RAM3 O DATA OUT 3 D DATA_BUS 3 A3 ADDR 3 Al ADDR 1 AO ADDR 0 WE WE WCLK CLK synthesis xc props INIT 5555 RAM16X1S RAM2 O DATA OUT 2 D DATA BUS 2 A3 ADDR 3 Al ADDR 1 AO ADDR 0 WE WE WCLK CLK synthesis xc props INIT FFFF RAM16X1S RAMI O DATA OUT 1 D DATA BUS 1 A3 ADDR 3 Al ADDR 1 AO ADDR 0 WE WE WCLK CLK synthesis xc props INIT AAAA RAM16X1S RAMO A2 A2 A2 ADDR 2 ADDR 2 ADDR 2 O DATA OUT 0 D DATA BUS 0 A3 ADDR 3 A2 ADDR 2 Al ADDR 1 AO ADDR 0 WE WE WCLK CLK synthesis xc props INIT 0101 endmodule 172 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Memory lt XILINX XST This example shows how to create a 16x4 RAM using Xilinx RAM16X1S component module RAM INIT ADDR DAT input 3 0 inout 3 0 input WE CLK wire EX1 DATA_BUS ADDR WE CLK lA BUS 3 0 DATA OUT Only for Simulation the defparam will not synthesize Use the defparam for RTL simulation There is no defparam needed for Post P amp R simulation synthesis translate off defparam RAMO INIT 0101 RAM3 INIT 5555 synthesis translate_on RAM1 I
341. ple Setenv LMC HOME SXILINX verilog smartmodel sol installed Windows 1 Begin SmartModel Installation by running the s1_admin exe program from the verilog smartmodel nt image pcnt directory 2 Select SmartModels To Install a The sl_admin GUI and the Set Library Directory dialog box appears Change the default directory from image pcent to installed Click OK If the directory does not exist the program asks if you want to create it Click OK Click Install on the left side of the sl admin window This allows you choose the models to install When the Install From dialog box appears click Browse and select sim_models xilinx verilog smartmodel nt image directory Click OK to select that directory The Select Models to Install dialog box appears Click Add All then click OK The Choose Platform window appears For Platforms select Wintel For EDAV Packages select Other Click OK to install From the sl admin window you will see Loading gt swift and Loading ppc405 swift When the words Install complete appear installation is complete Synthesis and Verification Design Guide www xilinx com 195 1 800 255 7778 2 XILINX Chapter 5 Virtex Il Pro Considerations At this point the SmartModels have been installed Exit the GUI by selecting File Exit from the drop down menu or use the GUI to perform other operations such as bringing up documentation and running checks on your newly installed lib
342. process ena End FF ASR CLOCK ENABLE end BEHAV Verilog Example FF EXAMPLE V Example of Implementing Registers ENABLE D IN E Q OUT module ff example RESET SET CLOCK A Q OUT B_Q OUT C Q OUT D Q OUT input RESET input SET input CLOCK input ENABLE input 7 0 D IN output 7 0 A Q OUT output 7 0 B Q OUT output 7 0 C Q OUT output 7 0 D Q OUT output 7 0 E Q OUT D flip flop always posedge CLOCK begin A_Q OUT lt D_IN end End FF Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 69 2 XILINX Chapter 3 General HDL Coding Styles Flip flop with asynchronous rese always posedge CLOCK begin posedge RE if RE S i 1 bl B Q else if B Q end Flip always begin if SI EJ ET Co else if CO end Flip flop wi posedge CLOCK UT lt 00000000 CLOCK 1 b1 OUT lt D IN End Flip flop with asynchronous reset op with asynchronous set posedge SI ET 1 bl OUT lt 11111111 CLOCK 1 b1 UT D IN End Flip flop with asynchronous set O th asynchronous reset and clock enable always posedge CLOCK posedge RESET begi
343. prove design utilization and performance many times the synthesis tool or the Xilinx implementation tools flatten or modifie the design hierarchy After this flattening and restructuring of the design hierarchy in synthesis and implementation many times it becomes impossible to reconstruct this hierarchy and thus much of the advantage of using the original design hierarchy in RTL verification is lost in back end verification In an effort to improve visibility of the design for back end simulation the Xilinx design flow allows for retention of the original design hierarchy with this described methodology To allow preservation of the design hierarchy through the implementation process with little or no degradation in performance or increase in design resources stricter design rules should be followed and design hierarchy should be carefully selected so that optimization is not necessary across the design hierarchy Some good design practices to follow are e Register all outputs exiting a preserved entity or module e Do not allow critical timing paths to span multiple entities or modules e Keep related or possibly shared logic in the same entity or module e Place all logic that is to be placed merged into the I O IOB registers three state buffers instantiated I O buffers etc in the top level module or entity for the design This includes double data rate registers used in the I O e Manually duplicate high fanout registers at hie
344. r back end simulations and is generally all that is necessary for functional simulations If GSR or GTS needs to be emulated in the functional simulation then it is necessary to add GSR and GTS to the test bench and connect them to the user defined global signals This is discussed in more detail in the following section Note The terms test bench and test fixture are used synonymously throughout this manual Emulating the Global GSR in a Verilog Functional Simulation Many HDL designs that target Xilinx FPGAs have a user reset that initializes all registers in the design during the functional simulation For these designs it is not necessary to emulate the GSR pulse that occurs after the device is configured If the design contains registers that are not connected to a user reset the GSR pulse can be emulated to ensure that the functional simulation matches the timing simulation In the design code declare a GSR as a Verilog wire The GSR is not specified in the port list for the module Describe the GSR to reset or set every inferred register or latch in your design GSR need not be connected to any instantiated registers or latches as the UNISIM models for these components connect to GSR directly This is shown in the following example module my_counter CLK D Q COUT input CLK D output Q output 3 0 COUT wire GSR reg 3 0 COUT always posedge GSR or posedge CLK begin if GSR 1 b1 COUT 4
345. r commands should be described in VHDL or Verilog format For VHDL PathSeparator for Verilog PathSeparator Comment out the following statement PathSeparator by adding a at the start of the line 3 After the line List of dynamically loaded objects for Verilog PLI applications Add the following statement Veriuser MODEL TECH libswiftpli dll 4 After the line Logic Modeling s SmartModel SWIFT software Windows NT add the following statements libsm MODEL TECH libsm dll libswift LMC HOME lib pont lib libswift dll Note It is important to make these changes in the order in which the commands appear in the modelsim ini file The simulation may not work if the order recommended is not followed After editing the modelsim ini file add the following environment variable to the MTI ModelSim SE setup script set MODELSIM path to modelsim ini scriptNmodelsim ini If the MODELSIM environment variable is not set properly MTI might not use this INI file and then the initialization settings required for simulation will not be read by the simulator Set up the MTI ModelSim SE simulation environment by sourcing the MTI SE setup script from the terminal Running Simulation In the XILINX verilog smartmodel sol simulation mtiverilog directory there are several files to help you set up and run a simulation using the SWIFT interface e modelsim ini An e
346. r is invoked The default for this option is On checkbox is checked This option is only relevant if you invoke the ModelSim simulator from Project Navigator Bring Out Global Tristate Net as a Port The Bring Out Global Tristate Net as a Port option causes NetGen to bring out the global tristate signal which forces all FPGA outputs to the high impedance state as a port on the top level design module in the output netlist Specifying the port name allows you to match the port name you used in the front end if being driven by a TOCBUF This option should only be used if the global tristate net is not driven by a STARTUP STARTBUF block For more information on this option refer to the Understanding the Global Reset and Tristate for Simulation section Global Tristate Port Name The Global Tristate Port Name property allows you to specify a port name to match the port name you used in the front end if a TOCBUF component was used Bring Out Global Set Reset Net as a Port The Bring Out Global Set Reset Net as a Port property causes NetGen to bring out the Global Set Reset signal which is connected to all flip flops and latches in the physical design as a port on the top level design module in the output netlist Specifying the port name allows you to match the port name you used in the front end if a ROCBUF component was used This option should only be used if the global set reset net is not driven by a STARTUP STARTBUF block For mor
347. r more information on GSR refer to the Understanding the Global Reset and Tristate for Simulation section VHDL Verilog Libraries and Models 210 The five simulation points listed previously require the UNISIM CORE Generator XilinxCoreLib SmartModel and SIMPRIM libraries The first point RTL simulation is a behavioral description of your design at the register transfer level RTL simulation is not architecture specific unless your design contains instantiated UNISIM or CORE Generator components To support these instantiations Xilinx provides a functional UNISIM library a CORE Generator Behavioral XilinxCoreLib library and a SmartModelLibrary You can also instantiate CORE Generator components if you do not want to rely on the module generation capabilities of your synthesis tool or if your design requires larger memory structures The second simulation point is post synthesis pre NGDBuild gate level simulation If the UNISIM library and CORE Generator components are used then the UNISIM the XilinxCorLib and SmartModelLibraries must all be used The synthesis tool must write out the HDL netlist using UNISIM primitives Otherwise the synthesis vendor provides its own post synthesis simulation library The third fourth and fifth points post NGDBuild post map and post route use the SIMPRIM and the SmartModelLibraries The following table indicates what library is required for each of the five simulation po
348. r synthesis tool s documentation for information on how to use the constraints editor specific to your synthesis environment You can add the following constraints e Clock frequency or cycle and offset Input and Output timing e Signal Preservation e Module constraints e Buffering ports e Path timing e Global timing Generally the timing constraints are written to an NCF file and all other constraints are written to the output EDIF file In XST all constraints are written to the NGC file Please refer to the documentation for your synthesis tool to obtain more information on Constraint Editors Evaluating Design Size and Performance Your design should meet the following requirements e Design must function at the specified speed e Design must fit in the targeted device After your design is compiled you can determine preliminary device utilization and performance with your synthesis tool s reporting options After your design is mapped by the Xilinx tools you can determine the actual device utilization At this point in the design flow you should verify that your chosen device is large enough to incorporate any future changes or additions and that your design will perform as specified Using your Synthesis Tool to Estimate Device Utilization and Performance Use your synthesis tool s area and timing reporting options to estimate device utilization and performance After compiling use the report area command to obtai
349. rarchy boundaries if improved timing is necessary Generally it is good practice to follow the guidelines in the FPGA Reuse Field Guide You can find this manual in PDF format on the Xilinx website at http www xilinx com ipcenter designreuse index htm To maintain the entire hierarchy or specified parts of the hierarchy during synthesis the synthesis tool must first be instructed to preserve hierarchy for all levels or each selected level of hierarchy This may be done with a global switch compiler directive in the source files or a synthesis command Consult your synthesis tool documentation for details on how to retain hierarchy After taking the necessary steps to preserve hierarchy and properly synthesizing the design a hierarchical implementation file EDIF or NGC will be created by the synthesis tool that retains the hierarchy Before implementing the design with the Xilinx software place a KEEP HIERARCHY constraint on each instance in the design in which the hierarchy is to be preserved This tells the Xilinx software exactly which parts of the design should not be flattened or modified to maintain proper hierarchy boundaries This constraint may be passed in the source code as an attribute as an instance constraint in the NCF or UCF file or may be automatically generated by the synthesis tool See your synthesis vendor documentation to see how your synthesis tool handles this More information on the KEEP HIERARCHY constr
350. raries Specify the following at the command line 1 Compile the SDF annotation file ncsdfc design sdf 2 Create an SDF command file sdf cma the following data in it COMPILED SDF FILE design sdf X SCOPE uut MTM CONTROL MAXIMUM 3 Create a working directory mkdir test 4 Compile design files and workbench ncvhdl work test work design vhd testbench vhd 5 Elaborate the design at the proper scope ncelab sdf cmd file cmd testbench cfg A 6 Invoke the simulation ncsim testbench cfg A NC Verilog There are two methods to run simulation with NC Verilog 1 Using library source files with compile time options 2 Using shared precompiled libraries Using Library Source Files With Compile Time Options Depending on the makeup of the design Xilinx instantiated primitives or CORE Generator components for RTL simulation specify the following at the command line ncxlmode libext v y SXILINX verilog src unisims testfixture v design v SXILINX verilog src glbl v For timing or post NGDBuild simulation use the SIMPRIM based libraries Specify the following at the command line ncxlmode y XILINX verilog src simprims libext v testfixture v time sim v SXILINX verilog src glbl v Using Shared Precompiled Libraries Simulation Libraries have to be compiled to compiled lib dir before using NC Verilog See Compiling Xilinx amp Simulation Libraries COMPXLIB for instruction on how to compile
351. rary To properly use the newly compiled models set the LMC_HOME variable to the image directory For example Set LMC_HOME SXilinx verilog smartmodel nt installed For details specific to Virtex II Pro see the Virtex II Pro Platform FPGA User Guide Running Simulation This section describes how to set up and run simulation on the various supported simulators MTI ModelSim SE Solaris 196 Simulator Setup Although ModelSim SE supports the SWIFT interface some modifications must be made to the default ModelSim setup to enable this feature The ModelSim install directory contains an initialization file called modelsim ini In this initialization file users can edit GUI and Simulator settings to default to their preferences Parts of this modelsim ini file must be edited to work properly along with the Virtex II Pro device simulation models The following changes are needed in the modelsim ini file Make these changes to the modelsim ini file located in the MODEL TECH directory An alternative to making these edits is to change the MODELSIM environment variable setting in the MTI setup script to point to the modelsim ini file located in the each example s design directory 1 After the lines Simulator resolution Set to fs ps ns us ms or sec with optional prefix of 1 10 or 100 Edit the statement that follows from Resolution ns to Resolution ps 2 After the lines
352. rations are initially limited or when your design timing goals are close to being achieved From the Project Navigator To initiate a reentrant route from Project Navigator follow these steps See the Project Navigator Online Help for details on reentrant routing 1 Inthe Project Navigator Process Window right click Place amp Route and then select Properties The Process Properties dialog box appears Set the Place and Route Mode option to Reentrant Route 2 Click OK to exit the Process Properties dialog box 3 Double click Place amp Route in the Process Window of Project Navigator to begin placing and routing your design Using PAR and Cost Tables The PAR module places in two stages a constructive placement and an optimizing placement PAR writes the NCD file after constructive placement and modifies the NCD after optimizing placement During constructive placement PAR places components into sites based on factors such as constraints specified in the input file for example certain components must be in certain locations the length of connections and the available routing resources This placement also takes into account cost tables which assign weighted values to each of the relevant factors There are 100 possible cost tables Constructive placement continues until all components are placed PAR writes the NCD file after constructive placement For more information on PAR and Cost Tables refer to the Developmen
353. re information on Timing Analysis refer to the Timing Analyzer Online Help Synthesis and Verification Design Guide www xilinx com 43 1 800 255 7778 Z XILINX Chapter 2 Understanding High Density Design Flow 44 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 XILINX Chapter 3 General HDL Coding Styles This chapter contains HDL coding styles and design examples to help you develop an efficient coding style It includes the following sections e Naming and Labeling Styles e Specifying Constants e Choosing Data Type VHDL only e Coding for Synthesis HDLs contain many complex constructs that are difficult to understand at first Also the methods and examples included in HDL manuals do not always apply to the design of FPGAs If you currently use HDLs to design ASICs your established coding style may unnecessarily increase the number of gates or CLB levels in FPGA designs HDL synthesis tools implement logic based on the coding style of your design To learn how to efficiently code with HDLs you can attend training classes read reference and methodology notes and refer to synthesis guidelines and templates available from Xilinx and the synthesis vendors When coding your designs remember that HDLs are mainly hardware description languages You should try to find a balance between the quality of the end hardware results and the speed of simulation The coding hints an
354. red by most synthesis tools In addition the UNISIM Library includes primitives that are commonly instantiated such as DCMs BUFGs and GTs You should generally infer most design functionality using behavioral RIL code unless the desired component is not inferrable by your synthesis tool or you want to take manual control of mapping and or placement of a function UNISIM Library Structure The UNISIM library structure is different for VHDL and Verilog The VHDL UNISIM library is split into four files containing the component declarations unisim_VCOMP vhd package files unisim_VPKG vhd entity and architecture declarations unisim VITAL vhd and SmartModel declarations unisim SMODEL vhoG All primitives for all Xilinx device families are specified in these files The VHDL UNISIM Library source files are located at SXILINX vhdl src unisims For Verilog each library component is specified in a separate file The reason for this is to allow automatic library expansion using the uselib compiler directive or the y library specification switch All Verilog module names and file names are all upper case i e module BUFG would be BUFG v module IBUF would be IBUF v Since Verilog is a case www xilinx com 1 800 255 7778 Synthesis and Verification Design Guide VHDL Verilog Libraries and Models XILINX sensitive language ensure that all UNISIM primitive instantiations adhere to this upper case naming convention The librar
355. register See the above section for an attribute to turn on I O register inference in synthesis tools Note f using FPGA Compiler II to synthesize the following examples open up FPGA Compiler Il s constraints editor select the Ports tab and change the default Use I O Reg option from NONE to TRUE Doing so places an IOB TRUE constraint on every flip flop in the design There is no option to specify only the output enable registers e VHDL example library IEEE use IEEE STD_LOGIC_1164 ALL entity tri_state is Port data_in_p in std_logic_vector 7 downto 0 clk in std_logic tri_state_a in std_logic tri_state_b in std_logic data out out std_logic_vector 7 downto 0 end tri state architecture behavioral of tri state is signal data in std logic vector 7 downto 0 signal data in r std logic vector 7 downto 0 signal tri state cntrl std logic vector 7 downto 0 signal temp tri state std logic vector 7 downto 0 begin Gl for I in 0 to 7 generate temp tri state I lt tri state a AND tri state b create duplicate input signal end generate process tri state cntrl data in r begin G2 for J in 0 to 7 loop if tri state cntrl J 0 then tri state data out data out J data in r J else data out J lt Z end if end loop end process process clk begin if clk event and clk 1 then data in lt data in p register for input data in r d
356. ribute is set to FALSE in which case the duty cycle is the same as that of the CLKIN The frequency of CLKDV is determined by the value assigned to the CLKDV_DIVIDE attribute The default is 2 The STARTUP_WAIT is not implemented in the model however it can be passed via a defparam similar to CLKDV_DIVIDE and DUTY_CYCLE_CORRECTION module clkdll ex CLKIN P RST P CLKO P CLK90 P CLK180 P CLK270 P CLK2X CLKDV P LOCKED P input CLKIN P RST P output CLKO P CLK90 P CLK180 P CLK270 P CLK2X P output CLKDV P Active high indication that DLL is LOCKED to CLKIN output LOCKED P wire CLKIN CLKO0 Input buffer on the clock IBUFG UO I CLKIN P O CLKIN GLOBAL CLOCK BUFFER on the delay compensated output BUFG U2 I CLKO O CLKO P Instantiate the DLL primitive cell CLKDLL DLLO CLKIN CLKIN CLKFB CLKO P RST RST P CLKO CLK0 CLK90 CLK90 P CLK180 CLK180 P CLK270 CLK270 P CLK2X CLK2X P CLKDV CLKDV P LOCKED LOCKED P CLKO divided by 1 5 2 0 2 5 3 0 4 0 5 0 8 0 or 16 0 defparam DLLO CLKDV DIVIDE 4 0 defparam DLLO DUTY CYCLE CORRECTION FALSE endmodule Note Some synthesis tools may not support the use of a defparam statements See the Defparam Support Considerations section for details www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulating Verilog Z X
357. rification Design Guide 1 800 255 7778 Using Advanced Clock Management lt XILINX In LeonardoSpectrum set the following attribute in the command line or TCL script set attribute port CLOCK PORT name PAD value BUFGDLL LeonardoSpectrum supports implementation of BUFGDLL with the CLKDLLHF component To use this implementation set the following attribute set attribute port CLOCK PORT name PAD value BUFGDLLHF In Synplify set the following attribute in the SDC file define attribute port name xc clockbuftype BUFGDLL This attribute can be applied to the clock port in HDL code as well In XST the BUFGDLL can be used by the CLOCK_BUFFER constraint entered in either HDL or the XST constraints file For more information on using XST specific constraints see the XST User Guide CLKDLL Attributes To specify how the signal on the CLKDIV pin is frequency divided with respect to the CLKO pin you can set the CLKDV_DIVIDE property The values allowed for this property are 1 5 2 2 5 3 4 5 8 or 16 The default is 2 In HDL code the CLKDV DIVIDE property is set as an attribute to the CLKDLL instance The following are VHDL and Verilog coding examples of CLKDLL attributes e VHDL example library IEEE use IEEE std_logic_1164 all entity CLOCK_TEST is port ACLK in std logic DIN in std logic vector 1 downto 0 RESE in std logic QOUT out std logic vector
358. rilog under dor rtr OR a HO Ea d be re Coe ad keting tienen ts 253 Defining Global Signals in Verilog sesllesseeeeeeeeeee 253 Using the glbl y Module lsssssssssssee III 253 Defining GSR GTS ina Test Bench 0 254 Emulating the Global GSR in a Verilog Functional Simulation 254 Simulating Special Components in Verilog 6 0 66 eee 255 Boundary Scan and Readback 2 6 cette eens 255 Defparam Support Considerations 0 0 6 0 isse 255 Differential I O LVDS LVPECL socer eresse newn cece eee eee mr 256 InsyDL rPTS 256 SRE UG iets tie T v P u Y 256 Block RAM eR E RR GRE ROY Ga eee hae a ee 257 e prM P rTTEDET 258 joel rrr RT PI 259 Simulation CORE Generator Components s s ssas sass sr eee 260 Design Hierarchy and Simulation uuusuuuusssss esses 260 RTL Simulation Using Xilinx Libraries 00 e eee 262 Timing SAMA HON 6534 0 dede Ee E pO RERO RE CR AUCI QUO E UO Uae ee Ra 262 Glitches in your Design 06 6 en 262 CLKDLL DCM Clocks do not appear de skewed 6 cece cece eee een 263 Simulating the DLL DCM sisssssssees II 263 TRACE Simulation Model Differences llle 263 Non EVIILJInput DEVers ez I eer ee ere dcs ety on 264 Viewer Considerations nnonser asnon unne eee rrr 264 Attributes for Simulation and Implement
359. ro X or Spartan 3 devices RAMB16_Sn or RAMB16_Sm_Sn is inferred Inferring Block SelectRAM VHDL Example Block SelectRAM can be inferred by some synthesis tools Inferred RAM must be initialized in the UCF file Not all Block SelectRAM features can be inferred Those features are pointed out in this section e FPGA Compiler IITM RAM inference is not supported by FPGA Compiler II e LeonardoSpectrum LeonardoSpectrum can map your memory statements in Verilog or VHDL to the Block SelectRAM on all Virtex devices The following is a list of the details for Block SelectRAM in LeonardoSpectrum Virtex Block SelectRAM is completely synchronous both read and write operations are synchronous LeonardoSpectrum infers single port RAMs RAMs with both read and write on the same address and dual port RAMs RAMs with separate read and write addresses Virtex Block SelectRAM supports RST reset and ENA enable pins Currently LeonardoSpectrum does not infer RAMs which use the functionality of the RST and ENA pins By default RAMs are mapped to Block SelectRAM if possible You can disable mapping to Block SelectRAM by setting the attribute BLOCK RAM to false e LeonardoSpectrum VHDL example library ieee exemplar use ieee std logic 1164 all use ieee numeric std all entity ram examplel is generic data width integer 8 address width integer
360. ross the top of the chip and 12 across the bottom From these lines up to 12 unique signals per column can be distributed via the 12 longlines in the column To use this you must specify the USELOWSKEWLINES constraint in the UCF file For more information on the USELOWSKEWLINES constraint syntax refer to the Constraints Guide In Virtex II Virtex II Pro and Virtex II Pro X and Spartan 3 longlines resources are more abundant There are many ways in which the secondary clocks or high fanout signals can be routed using a pattern of resources that result in low skew The Xilinx Implementation tools automatically use these resources based on various constraints in your design Additionally the USELOWSKEWLINES constraint can be applied to access this routing resource Inserting Clock Buffers Many synthesis tools automatically insert a global buffer BUFG when an input port drives a register s clock pin or when an internal clock signal reaches a certain fanout A Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 79 80 XILINX Chapter 4 Architecture Specific Coding Styles for Spartan Il 3 Virtex E Il II Pro II Pro X BUFGP an IBUFG BUFG connection is inserted for the external clock whereas a BUFG is inserted for an internal clock Most synthesis tools also allow you to control BUFG insertions manually if you have more clock pins than the available BUFGs resources FPGA Compiler II
361. routing delays which may include the following optional Gate level netlist containing SIMPRIM library components Standard Delay Format SDF files SmartModels 5 Post Place and Route with full back annotated timing which may include the following Gate level netlist containing SIMPRIM library components Standard Delay Format SDF files SmartModels Synthesis and Verification Design Guide www xilinx com 205 1 800 255 7778 XILINX XilinxCoreLib Modules SmartModel Libraries SmartModel Libraries SIMPRIM Library Figure 6 1 206 1 800 255 7778 www xilinx com Chapter 6 Verifying Your Design HDL Design HDL RTL Simulation Synthesis Testbench Stimulus Post Synthesis Gate Level Functional Simulation Xilinx Implementation HDL Timing Simulation X10018 Primary Simulation Points for HDL Designs Synthesis and Verification Design Guide Simulation Points Z XILINX The Post NGDBuild and Post Map simulations can be used when the synthesis tool either cannot write VHDL or Verilog or if the netlist is not in terms of UNISIM components Table 6 2 Five Simulation Points in HDL Design Flow i unisim XllinxCoreLib S martModel SIMPRIM SDF Simulation Models 1 RTL X X X 2 Post Synthesis optional X X X 3 Functional Post NGDBuild X X optional 4 Functional Post Map X X X optional 5 Post Route Timing X X X
362. rs sccdon ete tie id chee E E dusk nau dee ae sendet esd 214 From Command Lire seses vials ovine e bx Pees YEG Vee E a ne Sek 216 Library SUpport cot eto ate akinesia te etree tita edu atest mem tui 216 Device Family Support ieseciod e p ethene EXE M b HORS ERES SERRA ERIS 216 niii ue 04 0 01 0 o eM EE 216 COMPXLIB Syntax civ sec iler b etei t ued eye edad ied ERR awe ege 217 COMPXEIB Options 22 2400 a0 Rees ER Setanta Saas E NS Dee EE aa 217 COMPXLIB Command Line Examples sees eee 219 Specifying Run Time Options 66 66 220 Sample Configuration Files cepe ck eee Ved god ene xe REY os eee 221 R nning tll ER rnrm 221 Creating a Simulation Netlist 0 0 066 eens 221 Fron Project Navigator fits i ete sass ere P eue ging mede peo acd 221 From XELOW pse seduce ven word ness nedeG ceed eu Ru saad keer aduana 226 From Command Line or Script File 2 2 cece ne 227 Disabling X Propagation 0 0 eee enn eens 227 Using the ASYNC_REG Attribute 2 cies ee 228 Using Global Switches 2 se 0 t40c1 00 oiteseiecwer law vataw rede e RENTE sha 228 Use With Care aiu eoa d eese rro ocinea die e dete taie ama ma tended 228 MIN TYP MAX Simulation sssse ee 229 Understanding the Global Reset and Tristate for Simulation 230 Simulating VHDL reRCkRRECC CI RE E CHR CRI da Aoi pese ses 231 Emulating the Global GSR pulse in VHDL in Functional Simulation 231 Using VHDL Reset
363. rt map LKIN LKFB ST LK2X LKO LK90 LK180 LK270 LKD LOCKED C C R C C C C C C t std logic std logic t std logic std logic std logic std logic std logic std logic std logic std logic std logic std logic std logic std logic CLK 4x std logic IBUFG CLK ibufg CLK 4x CLK gt gt gt gt gt gt gt DLL AC AC 0 AC OP OP OP OP OP OP CLK 4x design LK ibufg LK 2x ZZZZZm N X Ej E Dd Ld B D zZ std Logic std logic 90 wwWw xilinx com 1 800 255 7778 Synthesis and Verification Design Guide Using Advanced Clock Management 2 XILINX BCLK dll CLKDLL port map CLKIN gt ACLK 2x CLKFB BCLK 4x design RST gt Q CLK2X gt BCLK 4x CLKO gt OPEN CLK90 gt OPEN CLK180 gt OPEN CLK270 gt OPEN CLKDV gt OPEN LOCKED gt BCLK lockin process BCLK 4x design RESET begin if RESET 1 then QOUT 00 elsif BCLK 4x design event and BCLK 4x design 1 if BCLK lockin 1 then QOUT lt DIN end if end if end process BCLK lock lt BCLK lockin END RTL e Verilog example module clock test ACLK DIN QOUT BCLK LOCK RESET input ACLK input RESET input 1 0 DIN output 1 0 QOUT output BCLK LOCK reg 1 0 QOUT IBUFG CLK ibufg A I ACLK O
364. s XILINX Chapter 4 Architecture Specific Coding Styles for Spartan Il 3 Virtex E Il II Pro II Pro X Table 4 3 VO Standard in Virtex V E Il and Spartan II Devices VirtexT II Il Pro Virtex E II Pro X Spartan 3 I O Virtex Standard Spartan II7 SSTL2 Class I and Class II SSTL3 Class I and Class II For Virtex Virtex E and Spartan II devices Xilinx provides a set of IBUF IBUFG IOBUF and OBUF with its SelectIO variants For example IBUF GTL IBUFG PCI66 3 IOBUF HSTL IV OBUF LVCMOS2 Alternatively an IOSTANDARD attribute can be set to a specific I O standard and attached to an IBUF IBUFG IOBUF and OBUF The IOSTANDARD attribute can be set in the user constraint file UCF or in the netlist by the synthesis tool The Virtex II library includes certain SelectIO components for compatibility with other architectures However the recommended method for using SelectIO components for Virtex II is to attach an IOSTANDARD attribute to I BUF IBUFG IOBUF OBUF For example attach IOSTANDARD GTLP to an IBUF instead of using the IBUF GTLP The default for the IOSTANDARD attribute is LVTTL For all Virtex E II and Spartan II devices you must specify IBUF IBUFG IOBUF or OBUF on the IOSTANDARD attribute if LVTTL is not desired For more information on I O standards and components please refer to the Libraries Guide Virtex Vir
365. s VHDL Do not use variables for constants in your code Define constant numeric values in your code as constants and use them by name This coding convention allows you to easily determine if several occurrences of the same literal value have the same meaning In some simulators using constants allows greater optimization In the following code example the OPCODE values are declared as constants and the constant names refer to their function This method produces readable code that may be easier to modify Synthesis and Verification Design Guide www xilinx com 51 1 800 255 7778 XILINX Chapter 3 General HDL Coding Styles constant ZERO STD LOGIC VECTOR 1 downto 0 2 00 constant A AND B STD LOGIC VECTOR 1 downto 0 01 constant A OR B STD LOGIC VECTOR 1 downto 0 10 constant ONE STD LOGIC VECTOR 1 downto 0 11 process OPCODE A B begin if OPCODE A AND B then OP OUT lt A and B elsif OPCODE A OR B then OP OUT lt A or B elsif OPCODE ONE then OP OUT lt 1 else OP OUT lt 0 end if end process Using Parameters to Specify OPCODE Functions Verilog You can specify a constant value in Verilog using the parameter special data type as shown in the following examples The first example includes a definition of OPCODE constants as shown in the previous VHDL example The second example shows how to use a parameter
366. s type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal ram ram type attribute block ram boolean attribute block ram of RAM signal is TRUE En begin write process clka begin if clka event and clka 1 then if wea 1 then ram conv integer addra lt dia end if end if end process write read process clkb begin if clkb event and clkb 1 then dob lt ram conv integer addrb end if end process read end dualport_ram_arch 162 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Memory Z XILINX e Synplify You can enable the usage of Block SelectRAM by setting the attribute SYN_RAMSTYLE to block_ram Place the attribute on the output signal driven by the inferred RAM Remember to include the range of the output signal bus as part of the name For example define attribute a dout 3 0 syn ramstyle block ram The following are limitations of inferring Block SelectRAM ENA ENB pins currently are inaccessible The are always tied to 1 RSTA RSTB pins currently are inaccessible They are always inactive Automatic inference is not yet supported The syn ramstyle attribute is required for inferring Block SelectRAM Initialization of RAMs is not supported Dual port with Read Write on a port is not supported e Synplify VHDL example library ieee use ieee std logic 1164 a11 use
367. s are not equivalent use Formality to debug the differences this process is not covered in this manual Please see the Formality documentation for more information on using Formality Synthesizing the Design When synthesizing the design it is important to note that several synthesis options can cause verification failures These include register merging max fanout control register duplication and register re timing optimization options There is currently not a workaround for register re timing so these options cannot be set during synthesis The following are workarounds for register merging and max fanout control Synthesis and Verification Design Guide www xilinx com 289 1 800 255 7778 XILINX Chapter 7 Equivalency Checking e Register merging option Use the Synopsys developed makeconstraints sh script if the register merging option is turned on This shell script reads in the FPGA Compiler II generated report detailing the list of merged registers and produces a Formality set constraint command file This command file must be then read into Formality before verification By default register merging option is turned on e Max fanout control register duplication option When using Max Fanout Control Synopsys recommends enabling the verification merged duplicated registers variable in Formality prior to verification By default max fanout control is turned off Generating a Post NGDBuild N
368. s cues dee ER oe d HE HARDER RU eee REOR ERES E 33 Using the UCF File cete t tae EIS E R E RH EPA 33 Using the Xilinx Constraints Editor 06 33 Using Synthesis Tools Constraints Editor sls 34 Evaluating Design Size and Performance 000 0 e cece eee ee 34 Using your Synthesis Tool to Estimate Device Utilization and Performance 34 Using the Timing Report Command ssseeeeeeeeeeee ee eens 35 Determining Actual Device Utilization and Pre routed Performance 35 Using Project Navigator to Map Your Design sssseeeeee ee 35 Using the Command Line to Map Your Design leseeeeeeeeeeee 36 Evaluating your Design for Coding Style and System Features 39 Tips for Improving Design Performance ssssssseeeeeee 39 Modifying Your Code ios erem tevaet tee ede eee eG eee eee ee EEG 39 Using FPGA System Features 2 0 0 c ccc cece hn 39 Using XilinxG specific Features of Your Synthesis Tool eese 39 Modular Design and Incremental Design ECO LLuuutiuuuuuus 40 Placing and Routing Your Design 0 0 0 0 cece cece eee ee 40 Decreasing Implementation Time sssssssseee eee eens 40 Improving Implementation Results 0 c cece eee 41 Map Timing Op thom 2 eene Yat eto retener eto e ears e ines aiU ains 41 Extra Effort Modein PAR i secco ce ede ce petet educi quede eds 41
369. s to instantiate the 16x1 or 32x1 ROM primitives To define the ROM value use the Set Attribute or equivalent command to set the INIT property on the ROM component Note Refer to your synthesis tool documentation for the correct syntax This type of command writes the ROM contents to the netlist file so the Xilinx tools can initialize the ROM The INIT value should be specified in hexadecimal values See the VHDL and Verilog RAM examples in the following section for examples of this property using a RAM primitive Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 177 178 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Implementing ROMs Using Block SelectRAM FPGA Compiler II LeonardoSpectrum and Synplify can infer ROM using Block SelectRAM FPGA Compiler II FPGA Compiler II can infer ROMs using Block SelectRAM instead of LUTs for Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X and Spartan 3 in the following cases e The inference is synchronous e For Virtex and Virtex E Block SelectRAM are used to infer ROM when the address line is at least ten bits and the data line is three bits or greater Also Block SelectRAM is used when the address line is 11 or 12 bits no minimum data width is required e For Virtex II Virtex II Pro Virtex II Pro X and Sp
370. se IEEE std logic 1164 all use IEEE std logic unsigned all entity ram 16x4s is port o out std_logic_vector 3 downto 0 we in std logic Clk in std logic d in std logic vector 3 downto 0 a in std logic vector 3 downto 0 end ram 16x4s architecture xilinx of ram 1l6x4s is component RAM16x1S is port O out std logic D in std logic A3 A2 Al AO in std logic WE WCLK in std logic end component attribute INIT string attribute INIT of U0 label is FFFF attribute INIT of U1 label is ABCD attribute INIT of U2 label is BCDE attribute INIT of U3 label is CDEF begin UO RAM16x1S port map O gt o 0 WE gt we WCLK gt clk D gt d 0 AO gt a 0 Al gt a 1 A2 gt a 2 A3 gt a 3 Ul RAM16x1S port map O gt o 1 WE gt we WCLK gt clk D gt d 1 A0 gt a 0 Al gt a 1 A2 gt a 2 A3 gt a 3 I I I I 166 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Memory 2 XILINX RAM16x1S port map O gt o 2 WE AO gt a 0 Al gt a 1 RAM16x1S port map O gt o 3 WE AO gt a 0 Al gt a 1 end xilinx U2 gt we U3 gt we A2 gt a 2 A2 gt a 2 WCLK gt clk A3 gt WCLK gt clk A3 gt e XST This example shows how to create a 16x4s RAM using xilinx RAM16x1S component li
371. sign Black Boxing Entire Modules As in the RTL vs post synthesis flow entire modules can be black boxed when verifying post synthesis vs post place and route You can use this to ignore certain modules during verification or to verify each module separately by black boxing all of the other modules To do this the hierarchy must be maintained by Synplify Pro and by the Xilinx implementation tools To instruct Synplify Pro and the Xilinx implementation tools to preserve the hierarchy place the following commands in the HDL code for each module in which the hierarchy should be preserved module name instance name port mapping synthesis syn hier hard xc props KEEP HIERARCHY TRUE The only other requirement for preserving the hierarchy is to supply the NGM file to NetGen The NGM file is an optional input file for NetGen It contains all of the hierarchical information and must be supplied to NetGen for the output netlist to contain the desired hierarchy For each module that is to be black boxed add the following to the DO file before the read design commands Add notranslate model module name Known Issues For known issues with verifying Xilinx designs with Conformal FPGA please search the Answers Database on the Xilinx support website at http support xilinx com Search using the following keyword string enter exactly as shown Verplex AND Conformal 288 www xilinx com Syn
372. signal DATA_int std_logic signal Q int std logic signal CLK int std logic signal CLK ibufgout std logic signal Tin int std logic begin UIl IBUFDS port map I gt DATA p IB gt DATA n O gt DATA int UI2 IBUFDS port map I gt datain2 p IB gt datain2 n O gt datain2 UI3 IBUFDS port map I gt Tin p IB gt Tin n O gt Tin int UO1l OBUFDS port map I gt Q_int O gt Q_p OB gt On UO2 OBUFTDS port map I gt odata out T gt Tin int O gt odata p OB gt odata n UIBUFG IBUFGDS port map I gt CLK p IB gt CLK n O gt CLK ibufgout UBUFG BUFG port map I gt CLK ibufgout O gt CLK int My D Reg process CLK int DATA int begin if CLK int event and CLK int 1 then Q int DATA int end if end process End My D Reg odata out lt DATA int and datain2 end BEHAV www xilinx com 1 800 255 7778 Synthesis and Verification Design Guide 133 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X e Verilog example LVDS 33 IO v Version 1 0 Example of a behavioral description of differential signal I O standard HDL Synthesis Design Guide for FPGAs module LVDS 33 IO CLK_p CLK_n DATA p DATA n DATAIN2 p DATAIN2 n Tin p Tin n ODATA p ODATAn Op O n input CLK p CLK n DATA p DATA n DATAIN2 p DATAIN
373. ssions such as an If statement without an Else clause This can be problematic for FPGA designs because not all FPGA devices have latches available in the CLBs In addition you may think that a register is created and the synthesis tool actually created a latch The Spartan II Spartan 3 and Virtex Virtex E Virtex II Virtex II Pro and Virtex II Pro X FPGAs do have registers that can be configured to act as latches For these devices synthesizers infer a dedicated latch from incomplete conditional expressions D Latch Inference e VHDL Example D LATCH VHD library IEEE use IEEE std logic 1164 a11 entity d latch is port GATE DATA in STD LOGIC Q out STD LOGIC end d latch architecture BEHAV of d latch is begin LATCH process GATE DATA begin if GATE 1 then Q lt DATA end if end process end LATCH end BEHAV e Verilog Example Transparent High Latch D LATCH V A module d latch GATE DATA Q input GATE input DATA output O reg Q always GATE or DATA begin if GATE 1 bl Q lt DATA end End Latch endmodule Synthesis and Verification Design Guide www xilinx com 63 1 800 255 7778 XILINX Chapter 3 General HDL Coding Styles Converting D Latch to D Register If your intention is to not infer a latch but rather to infer a D register then the following cod
374. st file and SDF file for each level of preserved hierarchy This capability allows for full timing simulation of individual portions of the design thus allowing for greater test bench re use team based verification methods and potentially cutting down overall verification times To have NetGen produce individual files for each KEEP HIERARCHY instance in the design use the mhf switch You can use this switch in conjunction with the dir switch to have all associated files placed in a separate directory netgen sim ofmt vhdl verilog mhf ngm design name map ngm dir directory name design name ncd When NetGen is invoked with the mhf switch it will also produce a text file called design mhf info txt This file will list all produced module entity names their associated instance names SDF files and sub modules This file can be useful for determining proper simulation compile order SDF annotation options and other information when using one or more of these files for simulation The following is an example of an mhf_info txt file for a Verilog produced netlist Xilinx design hierarchy information file produced by netgen build G 19 0 The information in this file is useful for ae Design hierarchy relationship between modules Bottom up compilation order VHDL simulation fi SDF file annotation VHDL simulation Design Name design_top Module The name of the hierarchical design module
375. steeenstiereelerge ied ped EAE a 289 Generating a Post NGDBuild Netlist 0 2 0 0 ec eee 290 16 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 lt XILINX Creating a Script File to Run Formality for RTL vs Post Synthesis Verification 290 Running the Script in Formality 2 0 0 cece eens 291 Using CORE Generator Components with Formality RTL vs Post Synthesis Verification 0 6 ccc cece hh 291 RTL to Post Place and Route 00 cece ene 292 Implementing the Design and Running NetGen sees 292 Creating a Script File to Run RTL vs Post PAR Verification 000 293 Running the Script in Formality siipeen i eiie ie ia EE EE eee 293 Using CORE Generator Components with Formality RTL vs Post PAR Verification C O eae a 293 Known ISsues 4 24 m beatae ened PENA REN UU Eu ee eee kneel 294 Conformal FPGA and FPGA Compiler II Flow 5 294 RTL vs Post Synthesis sssseeeessesele e 295 Synthesizing the Design c esekenkbpe ecg og DR eR Rh A a neon 295 Generating a Post NGDBuild Netlist 0 0 0 eee eee 295 Creating a DO File to Run RTL vs Post Synthesis Verification 295 Running the DO File in Conformal FPGA 06 eee ee 296 Using CORE Generator Components with Conformal RTL vs Post Synthesis Verification
376. ster and Latch Virtex Virtex E and Spartan II IOBs contain three storage elements The three IOB storage elements function either as edge triggered D type flip flops or as level sensitive latches Each IOB has a clock CLK signal shared by the three flip flops and independent clock enable CE signals for each flip flop In addition to the CLK and CE control signals the three flip flops share a Set Reset SR However each flip flop can be independently configured as a synchronous set a synchronous reset an asynchronous preset or an asynchronous clear FDCP asynchronous reset and set and FDRS synchronous reset and set register configurations are not available in IOBs Virtex IT TI Pro II Pro X or Spartan 3 IOBs also contain three storage elements with an option to configure them as FDCP FDRS and Dual Data Rate DDR registers Each register has an independent CE signal The OTCLK1 and OTCLK2 clock pins are shared between the output and tristate enable register A separate clock ICLK1 and ICLK2 drives the input register The set and reset signals SR and REV are shared by the three registers Synthesis and Verification Design Guide www xilinx com 121 1 800 255 7778 122 lt XILINX Chapter 4 Architecture Specific Coding Styles for Spartan II 3 Virtex E Il II Pro II Pro X Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X Spartan II and Spartan 3 devices no longer ha
377. t ain b lt bin end always posedge clk reg bank 0 lt a bj always posedge clk for i 1 i lt level i i 1 reg_bank i lt reg_bank i 1 assign q reg bank level 1 endmodule multiply The following is a synchronous multiplier Verilog example coded for Synplify and XST module mult_sync a b clk prod input 7 0 a input 7 0 b input clk output 15 0 prod reg 15 0 prod always posedge clk prod lt a b endmodule The following is a synchronous multiplier Verilog example coded for LeonardoSpectrum module xcv2_mult18x18s a b clk prod input 7 0 a input 7 0 b input clk output 15 0 prod reg 15 0 reg_prod prod always posedge clk begin reg prod lt a b prod lt reg prod endmodule Counters When describing a counter in HDL the arithmetic operator infers the carry chain The synthesis tools then infers the MUXCY element for the counter count lt count 1 This infers MUXCY This implementation provides a very effective solution especially for all purpose counters 148 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Operators and Generate Modules Z XILINX Following is an example of a loadable binary counter e VHDL example library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity counter is port d in std logic vector 7 downto 0 ld ce clk
378. t System Reference Guide 42 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Timing Simulation of Your Design XILINX From the Command Line To initiate a reentrant route from the command line you can run PAR with the k and p options as well as any other options you want to use for the routing process You must either specify a unique name for the post reentrant routed design ncd file or use the w switch to overwrite the previous design file as shown in the following examples par k p other options design name ned new name ncd par k p w other options design name ncd design ned Guide Option This option is generally not recommended for synthesis based designs except for modular design flows Re synthesizing modules can cause the signal and instance names in the resulting netlist to be significantly different from those in earlier synthesis runs This can occur even if the source level code Verilog or VHDL contains only a small change Because the guide process is dependent on the names of signals and comps synthesis designs often result in a low match rate during the guiding process Generally this option does not improve implementation results For information on guide in modular design flows refer to the Xilinx Modular Design web page Timing Simulation of Your Design Note Refer to Chapter 6 Verifying Your Design for more information on design simulation Timing simulation
379. t to the Implement Design process and then click on the sign next to the Place amp Route process Synthesis and Verification Design Guide www xilinx com 221 1 800 255 7778 2 XILINX 222 Chapter 6 Verifying Your Design BE Module View Wd Process View six Sources in Project F watch sc E readme E stmach v dia g3 xcv50 6bg256 B stopwatch stopwatch sch stopwatch_tb stopwatch tb tbw B cnt60 ent60 sch xi wa Snapshot View i Processes for Source stopwatch Implement Design Translate Z 3 Map E Map Report Generate Post Map Static Timing Manually Place amp Route FPGA Editor Generate Post Map Simulation Model SQ Place amp Route E Place amp Route Report B Asynchronous Delay Report E Pad Report E Guide Results Report A s A Fi ORO ce X Generate Post Place amp Route Static Timing View Edit Placed Design Floorplanner View Edit Routed Design FPGA Editor Analyze Power XPower Generate Power Data TUA A Que omiula mog E54 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Running NetGen XILINX 3 If any default options need to be changed right click on the Generate Post Place amp Route Simulation Model
380. te age dae Rend een ep eee een ete ein elas 203 Adhering to Industry Standards 0 0 c cece eee 204 Synthesis and Verification Design Guide www xilinx com 1 800 255 7778 13 lt XILINX Simulation POMS 4a v cordata pier iode Peete de ede pde er donde d o b bac tac e 205 Register Transfer Level RTL ssssssssssss I 207 Post Synthesis Pre NGDBuild Gate Level Simulation sess 208 Post NGDBuild Pre Map Gate Level Simulation 0000000 208 Post Map Partial Timing CLB and IOB Block Delays sssssesse 208 Timing Simulation Post Place and Route Full Timing Block and Net Delays 209 Providing Stimulus emp emer eR HERE ERE UR FRE ER S ER 209 VHDI Verilog Libraries and Models 0 0 0 00 cece eee 210 Locating Library Source Files 2 6 0c nee eee 211 Using the UNISIM Library 0 eee 212 UNISIM Library Structure sieri i a da ee d acide doe t deos 212 Using the CORE Generator XilinxCoreLib Library 6 660 e eee eee 213 CORE Generator Library Structure 0 6 en 213 Using the SIMPRIM Library 0 aeei ee iee apa e 213 SIMPRIM Library Structure s ezacevaceeesde e ue d e ace ad c d de el 213 Using the SmartModel Library sssssssssseeeeeeee 213 Compiling Xilinx Simulation Libraries COMPXLIB 214 Compiling Simulation Libraries 0 214 From Project Navigato
381. tex E Virtex II Virtex II Pro Virtex II Pro X Spartan II and Spartan 3 inputs can be configured to the I O standards listed above In FPGA Compiler II these special IOB components exist in the synthesis library and can be instantiated in your HDL code or selected from the FPGA Compiler II constraints GUI A complete list of components understood by FPGA Compiler II can be found in the Lib Nvirtex directory under the FPGA Compiler II tree amp XTLINX synth for ISE users FPGA Compiler II understands these components and does not attempt to place any I O logic on these ports Users are alerted by this warning Warning Existing pad cell verl Optimized U1 is connected to the port clk no pads cells inserted at this port FPGA PADMAP 1 In LeonardoSpectrum insert appropriate buffers on selected ports in the constraints editor Alternatively you can set the following attribute in TCL script after the read but before the optimize options PAD lOstandard portname The following is an example of setting an I O standard in LeonardoSpectrum PAD IBUF AGP data 7 0 In Synplify users can set XC_PADTYPE attribute in SCOPE Synplify s constraint editor or in HDL code as shown in the following example www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Inputs and Outputs Z XILINX Outputs e VHDL example library ieee synplify use ieee std logic 116
382. that a user must set for correct simulation and implementation Here is an example of the variables set setenv XILINX Xilinx path setenv CDS INST DIR Cadence path setenv LM LICENSE FILE license dat LM LICENSE FILE setenv LMC HOME SXILINX verilog smartmodel sol image setenv LMC CONFIG LMC HOME data solaris lmc setenv LD_LIBRARY_PATH CDS INST DIR tools sun4v lib LD LIBRARY PATH setenv LMC CDS VCONFIG CDS INST DIR tools sun4v verilog bin vconfig setenv PATH LMC HOME bin S CDS INST DIR tools bin PATH setenv PATH XILINX bin sol PATH Note The user is responsible for changing the parameters in italics to match the systems configuration e Simulate An example NC Verilog compilation simulation script Illustrates which files need to be compiled and loaded for simulation This file can be modified to simulate a design by including the design and test bench files appropriately Once each of these files has been properly updated run the simulation Synthesis and Verification Design Guide www xilinx com 201 1 800 255 7778 XILINX Chapter 5 Virtex Il Pro Considerations Synopsys VCS Solaris Running Simulation In the XILINX verilog smartmodel sol simulation vcs directory there are several files to help set up and run a simulation utilizing the SWIFT interface e Setup Description of variables which a user must set for correct si
383. the script file Ssource script name fms 4 Ifany verification errors occur start the GUI and debug the errors start gui Using CORE Generator Components with Formality RTL vs Post Synthesis Verification When using CORE Generator components the contents of the cores are read in during NGDBuild the first stage of the Xilinx implementation process Since the post synthesis netlist was run through NGDBuild the contents of the cores will be in the post NGDBuild netlist that is being used for verification The RTL design only contains black box instantiations of the cores Xilinx provides a Perl script core2formal p1 that creates Verilog representations of the cores which can be read in as part of the reference design Usage gt xilperl SXILINX verilog bin platform core2formal pl vendor family coregen module For Formality the vendor option must be formality e The family option can be virtex virtexe virtex2 virtex2p spartan2 spartan2e or spartan3 e The Perl script runs the following commands ngdbuild p family coregen module edn netgen ecn formality coregen module ngd coregen module for v The output from NetGen is a Verilog representation of the core that is read in with the RTL design as part of the golden reference design You must run the core2formal pl script on each CORE Generator module in the design Synthesis and Verification Design Guide www xilinx com 291 1 800 255 7778 lt XIL
384. the specified TEMPERATURE and VOLTAGE within the operating conditions recommended for the device Prorating is a linear scaling operation It applies to existing speed file delays and is applied globally to all delays The prorating constraints VOLTAGE and TEMPERATURE provide a method for determining timing delay characteristics based on known environmental parameters The VOLTAGE constraint provides a means of prorating delay characteristics based on the specified voltage applied to the device The UCF syntax is as follows VOLTAGE value V Where value is an integer or real number specifying the voltage and units is an optional parameter specifying the unit of measure The TEMPERATURE constraint provides a means of prorating device delay characteristics based on the specified junction temperature The UCF syntax is as follows TEMPERATURE value C F K Where value is an integer or a real number specifying the temperature C K and F are the temperature units F is degrees Fahrenheit K is degrees Kelvin and C is degrees Celsius the default The resulting values in the SDF fields when using prorated TEMPERATURE and or VOLTAGE values are prorated worst case values for the MIN TYP and MAX fields Refer to the specific product Data Sheets to determine the specific range of valid operating temperatures and voltages for the target architecture If the temperature or voltage specified in the constraint does not fall wit
385. thesis and Verification Design Guide 1 800 255 7778 Formality and FPGA Compiler IIT Flow XILINX Formality and FPGA Compiler II V Flow When using FPGA Compiler II and targeting a Xilinx FPGA You can use Formality to verify that the golden RTL design and the post synthesis or post place and route netlists are logically equivalent Figure 7 2 describes the FPGA Compiler II Formality flow for equivalency checking FPGA Netlist Compiler II db Synopsys Design Constraints ISE Alliance Golden netlist Post Synthesis netlist Formality X10001 Figure 7 2 FPGA Compiler IIT Formality flow for equivalency checking RTL vs Post Synthesis The first transformation of the RTL code is synthesis The synthesis tool will optimize the code and convert it from RTL to a post synthesis EDIF netlist Performing an equivalence check between the RTL and post synthesis netlist will verify that the functionality of the design has not been changed by the transformation to EDIF or by the optimization done by the synthesis tool The following steps that must be done to verify that the golden RTL and the post synthesis netlist are logically equivalent 1 Synthesize the design with FPGA Compiler II Run the output EDIF file through NGDBuild and NetGen Create a script file to run the verification in Formality Run the script file in Formality TF YN If the two netlist
386. tion use the syn noclockbuf attribute This attribute can be applied to the entire module architecture or a specific signal To change the maximum number of global buffer insertion set an attribute in the SDC file as follows define global attribute xc global buffers 8 XST assigns a BUFG to any input signal that directly drives a clock The default number of global buffers for the Virtex Virtex E and Spartan II device is 4 The default number of global buffers for the Virtex II Virtex II Pro Virtex II Pro X and Spartan 3 device is 8 The number of BUFGs used for a design can be modified by the XST option bufg You can use the bufg option by inserting it in the HDL code including it in the XST constraints file or invoking it with a command line switch Refer to your synthesis tool documentation for detailed syntax information Instantiating Global Clock Buffers You can instantiate global buffers in your code as described in this section Instantiating Buffers Driven from a Port You can instantiate global buffers and connect them to high fanout ports in your code rather than inferring them from a synthesis tool script If you do instantiate global buffers verify that the Pad parameter is not specified for the buffer In Virtex E II and Spartan II designs synthesis tools insert BUFGP for clock signals which access a dedicated clock pin To have a regular input pin to a clock buffer connection you must use
387. to EDIF or by the optimization done by the synthesis tool Perform the following steps to verify that the golden RTL and the post synthesis netlist are logically equivalent 1 Synthesize the design with FPGA Compiler IITM Run the output EDIF file through NGDBuild and NetGen Create a DO file to run the verification in Conformal FPGA Run the DO file in Conformal FPGA If the two netlists are not equivalent use Conformal FPGA to debug the differences this process is not covered in this document Please see the Conformal FPGA documentation for more information TF YN Synthesizing the Design When synthesizing the design it is important to note that several synthesis options can cause verification failures These include register merging max fanout control register duplication and register re timing optimization options There is currently not a workaround for register re timing so this option cannot be set during synthesis Contact Verplex if issues are encountered with the other options Generating a Post NGDBuild Netlist The post synthesis gate level netlist will consist of UNISIM components in the EDIF format At this time Conformal FPGA cannot directly process this EDIF netlist To create a Verilog netlist that is compatible with Conformal FPGA run the design through NGDBuild and NetGen This post NGDBuild Verilog netlist is treated as a representation of the post synthesis netlist Following is a samp
388. to allow the place and route tools to successfully complete your design The following is the Design Summary section of a Map Report containing device information www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Evaluating Design Size and Performance XILINX Release 6 1i Map G 14 Xilinx Mapping Report File for Design tri state test Design Information Command Line build bcoxfndry G 14 rtf bin sol map quiet p xc2v40 cs144 6 cm area pr b k 4 c 100 tx off o tri state test map ncd tri state test ngd tri state test pcf Target Device x2v40 Target Package cs144 Target Speed 6 apper Version virtex2 Revision 1 8 apped Date Fri Feb 28 12 48 37 2003 Design Summary Number of errors 0 Number of warnings 0 Logic Utilization Number of 4 input LUTs 1 out of 512 1 Logic Distribution Number of occupied Slices 1 out of 256 1 Number of Slices containing only related logic 1 out of 1 100 Number of Slices containing unrelated logic 0 out of al 0 See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs 1 out of 512 1 Number of bonded IOBs 4 out of 88 4 IOB Flip Flops 2 Number of GCLKs 1 out of 16 6 Total equivalent gate count for design 28 Additional JTAG gate count for IOBs 192 Peak Memory Usage 45 MB NOTES Related logic is defined as being logic that shares connectivity e g two LUTs are rel
389. tyle when the state machine is compiled Xilinx recommends that you specify an encoding style If you do not specify a style your compiler selects a style that minimizes the gate count For the state machine shown in the three previous examples the compiler selected the binary encoded style S1 000 S2 001 53 010 54 011 S5 100 S6 101 and S7 110 You can use the FSM extraction tool to change the encoding style of a state machine For example use this tool to convert a binary encoded state machine to a one hot encoded state machine Note Refer to your synthesis tool documentation for instructions on how to extract the state machine and change the encoding style Initializing the State Machine When creating a state machine especially when you use one hot encoding add the following lines of code to your design to ensure that the FPGA is initialized to a Set state e VHDL example SYNC_PROC process CLOCK RESET begin if RESET 1 then CS lt sl e Verilog example always posedge CLOCK or posedge RESET begin if RESET 1 b 1 CS S1 Alternatively you can assign an INIT S attribute to the initial state register to specify the initial state Refer to your synthesis tool documentation for information on assigning this attribute In the Binary Encode State Machine example the RESET signal forces the 51 flip flop to be preset initialized to 1 wh
390. u the list of libraries that are required for simulating a Virtex II project Target Simulator The Target Simulator property allows you to select the target simulator for which the libraries are to be compiled Click anywhere in the Value field to display the list of supported simulators Note You must choose a Target Simulator before starting the process Language By default the Language property is selected according to the Project Properties Output Directory The Output Directory property allows you to specify the directory where the compiled libraries will be saved To change the directory path type a new path in the Value field or click anywhere in the Value field and double click the small button that appears to the right of the current value Use the Browse for File dialog box that appears to choose an output directory The default directory path is XILINX language simulator where language is the selected language to compile and simulator is the name of the selected simulator Simulator Path The Simulator Path property allows you to specify the simulator installation bin path where the simulator executables reside To change the simulator path click anywhere in the Value field and double click the small button that appears to the right of the current value Use the Browse for File dialog box that appears to choose a directory By default the path to the simulator will be searched for via the path environme
391. uestions You can find the Timing Improvement Wizard at http support xilinx com support troubleshoot psolvers htm Path Not or Improperly Constrained Unconstrained or improperly constrained data and clock paths are the most common sources of setup and hold violations Because data and clock paths can cross domain boundaries global constraints are not always adequate to ensure that all paths are constrained For example a global constraint such as PERIOD does not constrain paths that originate at an input pin and data delays along these paths could cause setup violations Use Timing Analyzer to determine the length of an individual data or clock path For input paths to the design if the length of a data path minus the length of the corresponding clock path plus any data delay is greater than the clock period you get a setup violation clock period lt data path clock path data delay value setup value for register For detailed information on constraining paths driven by input pins see the Timing Constraint Strategies chapter of the Constraints Guide Also see Design Not Constrained above for other constraints resources Design Does Not Meet Timespec Xilinx software enables you to specify precise timing requirements for your Xilinx FPGA designs Specify the timing requirements for any nets or paths in your design The primary method of specifying timing requirements is by assigning timing constraints You can
392. ulti Pass Place amp Route in the Process Window of Project Navigator or specify this option at the command Synthesis and Verification Design Guide www xilinx com 41 1 800 255 7778 XILINX Chapter 2 Understanding High Density Design Flow line with the n switch See the Development System Reference Guide for a description of Multi Pass Place and Route and how to set the appropriate options Turns Engine Option UNIX only This option is a Unix only feature that works with the Multi Pass Place and Route option to allow parallel processing of placement and routing on several Unix machines The only limitation to how many cost tables are concurrently tested is the number of workstations you have available To use this option in Project Navigator see the Project Navigator Online Help for a description of the options that can be set under Multi Pass Place and Route To use this feature at the command line use the m switch to specify a node list and the n switch to specify the number of place and route iterations Note For more information on the turns engine option refer to the Development System Reference Guide Reentrant Routing Option Use the reentrant routing option to further route an already routed design The router reroutes some connections to improve the timing or to finish routing unrouted nets You must specify a placed and routed design ncd file for the implementation tools This option is best used when router ite
393. un time options for COMPXLIB through the compxlib cfg file By default COMPXLIB creates this file in the current directory You can also automatically create this file with its default settings by using the cfg option The following are run time options that can be specified in the configuration file EXECUTE ON orOFF By default the value is ON which means that the COMPXLIB compiles the libraries If the value is OFF COMPXLIB generates only the list of compilation commands in the compxlib 1log file without executing them LOCK PRECOMPILED ON or OFF By default the value is OFF which means that the COMPXLIB will compile the dependent libraries automatically if not precompiled If the value is ON COMPXLIB will not compile the precompiled libraries For example if you want to compile the SmartModel Library COMPXLIB will look for this variable value to see if the dependent libraries UNISIM and SIMPRIM are to be compiled or not LOG CMD TEMPLATE ON or OFF By default the value is OFF which means that the COMPXLIB will not emit the compilation command line in compxlib 1log file If the value is ON COMXPLIB will print the compilation commands in the compxlib 1log file PRECOMPILED INFO ON or OFF By default the value is ON which means that the COMPXLIB will print the precompiled library information including the date the library was compiled If the value is OFF COMXPLIB will not print the precompiled library informatio
394. ur synthesis tool manual Most vendors adopt identical syntax for passing attributes in VHDL but not in Verilog The following examples illustrate the VHDL syntax VHDL Attribute Examples The following are examples of VHDL attributes e Attribute declaration attribute attribute_name attribute_type e Attribute use on a port or signal attribute attribute_name of object_name signal is attribute_value Example library IEEE use IEEE std_logic_1164 all entity d_register is port CLK DATA in STD LOGIC Q out STD LOGIC attribute FAST string attribute FAST of Q signal is true end d register e Attribute use on an instance attribute attribute name of object name label is attribute value Example architecture struct of spblkrams is attribute INIT 00 string attribute INIT 00 of INST RAMBA S4 label is IF1E1D1C1B1A191817161514131211100F0E0D0C0B0908706050403020100 begin INST RAMBA S4 RAMBA S4 port map DI gt DI 3 downto 0 EN WE gt WE RST gt RST CLK gt CLK ADDR gt ADDR 9 downto 0 DO gt DORAMB4 S4 48 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Naming and Labeling Styles lt XILINX e Attribute use on a component attribute attribute_name of object_name component is attribute_value Example architecture xilinx of tenths_ex is attribute black_box boolean
395. usually the preferred method for large FPGA based state machine implementation For small state machines fewer than 8 states binary encoding may be more efficient To improve design 134 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Encoding State Machines Z XILINX performance you can divide large greater than 32 states state machines into several small state machines and use the appropriate encoding style for each Three design examples are provided in this section to illustrate the three coding methods binary enumerated type and one hot you can use to create state machines All three examples contain the same Case statement To conserve space the complete Case statement is only included in the binary encoded state machine example refer to this example when reviewing the enumerated type and one hot examples Some synthesis tools allow you to add an attribute such as TYPE_ENCODING_STYLE to your VHDL code to set the encoding style This is a synthesis vendor attribute not a Xilinx attribute Refer to your synthesis tool documentation for information on attribute driven state machine synthesis Using Binary Encoding The state machine bubble diagram in the following figure shows the operation of a seven state machine that reacts to inputs A through E as well as previous state conditions The binary encoded method of coding this state machine is shown in the VHDL and Verilog examples that follow
396. ute process this port is removed it is not implemented on the chip TOCBUF does not by default reappear in the post routed netlist unless the tp switch is used in NetGen The following example illustrates how to use the TOCBUF in your design library IEEE use IEEE std_logic_1164 all use IEEE std_logic_unsigned all library UNISIM use UNISIM all entity EX_TOCBUF is port CLOCK ENABLE SRP STP in std logic CUP CDOWN out std_logic_vector 3 downto 0 end EX TOCBUF architecture A of EX TOCBUF is signal GSR GTS std logic signal COUNT UP COUNT DOWN std logic vector 3 downto 0 component ROCBUF port I in std logic O out std logic end component component TOCBUF port I in std logic O out std logic end component begin Ul ROCBUF port map I gt SRP O gt GSR U2 TOCBUF port map I gt STP O gt GTS UP_COUNTER process CLOCK ENABLE GSR begin if GSR 1 then COUNT_UP lt 0000 elsif CLOCK event AND CLOCK 1 then if ENABLE 1 then COUNT UP lt COUNT UP 0001 end if end if end process UP COUNTER 240 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Simulating VHDL Synthesis and Verification Design Guide DOWN_COUNTER begin if process GSR 1 COUNT_DOWN lt 1111 elsif CLOCK event AND CLOC
397. utsignal Driver and output of tristate preserved Hierarchy notation Other names are machine generated Synplify Naming Styles Register instance output signal Output of register output signal Clock buffer instance ibuf portname_ibuf Output of clock buffer clkname_c Output inout tristate instance outputsignal_obuft or outputsignal_iobuf Internal tristate instance unn_signalname_tb when n is any number or signalname tb www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Specifying Constants XILINX Output of tristate driving an output inout name of port Output of internal tristate signalname_tb_number RAM instance and its output Dual Port RAM ram instance memoryname n I n ram output DPO memoryname n rout bus SPO memory name n wout bus Single Port RAM ram instance memoryname n ram output memoryname Single Port Block SelectRAM ram instance memoryname I n ram output memoryname Dual Port Block SelectRAM ram instance memory_name I_n ram output memoryname the output that is used Hierarchy delimiter is usually a however when syn hier hard the hierarchy delimiter in the edif is Other names are machine generated Specifying Constants Use constants in your design to substitute numbers to more meaningful names The use of constants helps make a design more readable and portable Using Constants to Specify OPCODE Function
398. ve primitives that correspond to the synchronous elements in the IOBs There are a few ways to infer usage of these flip flops if the rules for pulling them into the IOB are followed The following rules apply e All flip flops that are to be pulled into the IOB must have a fanout of 1 This applies to output and tristate enable registers For example if there is a 32 bit bidirectional bus then the tristate enable signal must be replicated in the original design so that it has a fanout of 1 e In Virtex E and Spartan II devices all flip flops must share the same clock and reset signal They can have independent clock enables e In Virtex II II Pro II Pro X or Spartan 3 devices output and tristate enable registers must share the same clock All flip flops must share the same set and reset signals One way you can pull flip flops into the IOB is to use the IOB TRUE setting Another way is to pull flip flops into the IOB using the map pr command which is discussed in a later section Some synthesis tools apply the IOB TRUE attribute and allow you to merge a flip flop to an IOB by setting an attribute Refer to your synthesis tool documentation for the correct attribute and settings In FPGA Compiler II you can set the attribute through the FPGA Compiler IITM constraints editor for each port into which a flip flop should be merged For tristate enable flip flops set the default value for Use I O Reg to TRUE This causes the
399. voked in specific blocks to verify the timing performance of a design by making sure critical events occur within given time limits Timing checks perform the following steps e Determine the elapsed time between two events e Compare the elapsed time to a specified limit e Ifthe elapsed time does not fall within the specified time window report timing violation The following system tasks may be used for performing timing checks hold setup nochange setuphold period skew recovery width VITAL Timing Checks VITAL VHDL Initiative Towards ASIC Libraries is an addition to the VHDL specification that deals with adding timing information to VHDL models One of the key aspects of VITAL is the specification of the package vital_timing This package in addition to other things provides standard procedures for performing timing checks The package vital_timing defines the following timing check procedures e VitalSetupHoldCheck e VitalRecoveryRemovalCheck e VitallnPhaseSkewCheck www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Debugging Timing Problems Z XILINX e VitalOutPhaseSkewCheck e VitalPeriodPulseCheck VitalSetupHoldCheck is overloaded for use with test signals of type Std_Ulogic or Std_Logic_Vector Each defines a CheckEnabled parameter that supports the modeling of conditional timing checks See the VITAL Language Reference Manual available from IEEE for details about specific
400. wnto 0 DO out STD LOGIC VECTOR 7 downto 0 end component begin U1 RAMBA S8 synp generic map INIT 00 gt 0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF023456789ABCDEF INIT 01 gt FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FDCBA9876543210 port map WE gt WE EN gt 1 RST gt O CLK gt CLK ADDR gt ADDR DI gt DIN DO gt DOUT end XILINX 158 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Memory lt XILINX Instantiating Block SelectRAM Verilog Example The following Verilog examples show Block SelectRAM instantiation FPGA Compiler IITM With FPGA Compiler II the INIT attribute has to be set in the HDL code See the following example module block_ram_ex CLK WE ADDR DIN DOUT input CLK W input 8 0 input 7 0 output 7 0 RAMB4_S8 UO E ADDR DIN DOUT Synthesis and Verification Design Guide WE WE 1 b1 STA BOY LK CLK ADDR ADDR DI DIN DO DOUT synopsys attribute INIT 00 1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A0980706050403020100 endmodule QD m LeonardoSpectrum With LeonardoSpectrum the INIT attribute can be set in the HDL code or in the command line See the following example set attribute instance inst ramb4 s4 INIT 00 type strin
401. x Virtex E CLKDLL See the Virtex II Platform FPGA User Guide for the available attributes for Virtex II II Pro II Pro X and Spartan 3 DCM 98 VHDL example for Synplify This example attaches multiple attributes to DCM components using the Synplify XC_PROP attribute Note Do not insert carriage returns between the values assigned to xc_props A carriage return could cause Synplify to attach only part of the attributes VHDL code begin library IEEE library virtex2 use IEEE std_logic_1164 all use virtex2 components all www xilinx com 1 800 255 7778 Synthesis and Verification Design Guide Using Advanced Clock Management lt XILINX entity DCM_TOP is port clock_in clock_out in std_logic out std_logic clock_with_ps_out out std_logic reset end DCM TOP out std logic architecture XILINX of DCM TOP is signal low high std logic signal docm0 locked std logic signal doml locked std logic signal clock std logic signal clk0 std logic signal clkl std logic signal clock with ps std logic signal clock out int std logic attribute xoc props string attribute xc props of dcm0 label is DLL FREQUENCY MODE LOW DUTY_CYCL E CORRECTION TRUE STARTUP_WAIT 1 CLK_F T lin s abov attribu LOW DUTY_CYCL te xc_props of dcml label is D
402. xample modelsim ini file used to set up ModelSim for SWIFT interface support This file contains the changes outlined above We suggest www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Running Simulation lt XILINX that you make the changes to the modelsim ini file located in the MODEL_TECH directory because of the library mappings included in this file e Setup Description of variables which a user must set for correct simulation and implementation Here is an example of the variables set set XILINX Xilinx path set LMC HOME XILINX verilog smartmodel sol image set MODEL TECH MTI path set LM LICENSE FILE license dat LM LICENSE FILE set path LMC_HOME bin 3LMC_HOME lib pcnt lib MODEL TECH Moin XILINX Mbin Mnt path Note The user is responsible for changing the parameters in italics to match the systems configuration e simulate bat An example ModelSim simulation script Illustrates which files must be compiled and loaded for simulation This file can be modified to simulate a design by including the design and test bench files appropriately If the user s modelsim ini file is being used which contains the system mappings the vmap commands can be commented out or deleted from this file e run do A script file used by the simulate script to run the complete simulation Once each of these files
403. xilinx Instantiating Distributed SelectRAM in Verilog The following coding provides Verilog coding hints for FPGA Compiler II LeonardoSpectrum Synplify and XST FPGA Compiler IITM This example shows how to create a 16x4 RAM using Xilinx RAM16X1S component module RAM INIT EX1 DATA BUS ADDR WE CLK input 3 0 ADDR inout 3 0 DATA BUS input WE CLK wire 3 0 DATA OUT Only for Simulation the defparam will not synthesize Use the defparam for RTL simulation There is no defparam needed for Post P amp R simulation synopsys translate off defparam RAMO INIT 0101 RAM2 INIT 2 FFFF RAM1 INIT AAAA RAM3 INIT 5555 synopsys translate_on assign DATA_BUS IWE DATA OUT 4 hz Instantiation of 4 16X1 Synchronous RAMs Use the xc props attribute to pass the INIT property RAM16X1S RAM3 O DATA OUT 3 Al ADDR 1 A0 synopsys attribute INIT 5555 D DATA BUS 3 23 ADDR 0 WE WE WCLK xy ADDR 3 A2 CLK ADDR 2 170 wwWw xilinx com 1 800 255 7778 Synthesis and Verification Design Guide Implementing Memory lt XILINX RAM16X1S RAM2 O DATA OUT 2 D DATA BUS 2 A3 ADDR 3 A2 ADDR 2 Al ADDR 1 A0 ADDR 0 WE WE WCLK CLK synopsys attribute INIT FFFF RAM16X1S RAMI O DATA_OUT 1 D DATA_BUS 1 A3 ADDR 3 A2 ADDR 2 Al AD
404. y its own contents Xilinx provides several Application Notes describing CAM designs in Virtex FPGAs Please refer to the following Xilinx Application Notes for more information XAPP201 An Overview of Multiple CAM Designs in Virtex Family Devices v 1 1 9 99 XAPP202 Content Addressable Memory CAM in ATM Applications v 1 1 9 99 XAPP203 Designing Flexible Fast CAMs with Virtex Family FPGAs v 1 1 9 99 XAPP204 Using Block SelectRAM for High Performance Read Write CAMs v1 1 10 99 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Implementing Shift Registers Virtex E II II Pro Il Pro X and Spartan II 3 XILINX Using CORE Generator to Implement Memory If you must instantiate memory use the CORE Generator to create a memory module larger than 32X1 16X1 for Dual Port Implementing memory with the CORE Generator is similar to implementing any module with CORE Generator except for defining the memory initialization file Please reference the memory module data sheets that come with every CORE Generator module for specific information on the initialization file Implementing Shift Registers Virtex E II II Pro Il Pro X and Spartan II 3 The SRL16 is a very efficient way to create shift registers without using up flip flop resources You can create shift registers that vary in length from one to sixteen bits The SRL16 is a shift register look up table LUT
405. y sources are split into two directories in which the FPGA device families Spartan II Spartan IIE Spartan 3 Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X are located at SXILINX verilog src unisims and the CPLD device families XC9500XL XC9500XV CoolRunner XPLA3 CoolRunner II CoolRunner IIS are located at XILINX verilog src uni9000 Using the CORE Generator XilinxCoreLib Library The Xilinx CORE Generator is a graphical intellectual property design tool for creating high level modules like FIR Filters FIFOs and CAMs as well as other advanced IP You can customize and pre optimize modules to take advantage of the inherent architectural features of Xilinx FPGA devices such as block multipliers SRLs fast carry logic and on chip single port or dual port RAM You can also select the appropriate HDL model type as output to integrate into your HDL design The CORE Generator HDL library models are used for RTL simulation The models do not use library components for global signals CORE Generator Library Structure The VHDL CORE Generator library source files are found in SXILINX vhdl src XilinxCoreLib The Verilog CORE Generator library source files are found in SXILINX verilog src XilinxCoreLib Using the SIMPRIM Library The SIMPRIM library is used for post Ngdbuild gate level functional post Map partial timing and post place and route full timing s
406. y to the simulator to annotate the SDF file Consult your simulation documentation to find the proper method to annotate SDF files For VHDL you must specify the location of the SDF file and which instance to annotate during the timing simulation The method for doing this is different depending on the simulator being used Typically a command line or GUI switch is used to read the SDF file Consult your simulation documentation to find the proper method to annotate SDF files Register Transfer Level RTL The RTL level behavioral simulationenables you to verify or simulate a description at the system or chip level This first pass simulation is typically performed to verify code syntax and to confirm that the code is functioning as intended At this step no timing information is provided and simulation should be performed in unit delay mode to avoid the possibility of a race condition RTL simulation is not architecture specific unless the design contains instantiated UNISIM or CORE Generator components To support these instantiations Xilinx provides the UNISIM and XilinxCoreLib libraries You can instantiate CORE Generator components Synthesis and Verification Design Guide www xilinx com 207 1 800 255 7778 XILINX Chapter 6 Verifying Your Design if you do not want to rely on the module generation capabilities of the synthesis tool or if the design requires larger memory structures A general suggestion for the initia
407. yle is not defined in the code but can be specified later with the FSM extraction commands Alternatively you can allow your compiler to select the encoding style that results in the lowest gate count when the design is synthesized Some synthesis tools automatically find finite state machines and compile without the need for specification Note Refer to the previous VHDL and Verilog Binary Encoded State Machine examples for the complete Case statement portion of the code Enumerated Type Encoded State Machine VHDL Example Library IEEE use IEEE std_logic_1164 all entity enum is port CLOCK RESE in STD LOGIC A B C D E in BOOLEAN SINGLE MULTI CONTIG out STD LOGIC end enum architecture BEHV of enum is type STATE TYPE is S1 S2 S3 S4 S5 S6 S7 signal CS NS STATE TYPE begin SYNC PROC process CLOCK RESET begin if RESET 1 then CS lt 1 elsif CLOCK event and CLOCK 1 then CS lt NS end if end process End SYNC PROC COMB PROC process CS A B C D E begin case CS is when Sl gt MULTI lt 0 CONTIG lt 0 SINGLE lt 0 www xilinx com Synthesis and Verification Design Guide 1 800 255 7778 Encoding State Machines Enumerated Type Encoded State Machine Verilog Example VMIIMIMMBlMIEMIMMLLMBMPPMPMMIMIEEHITLTCBPBGMP
408. you run your designs for an extended period of time overnight or over the weekend You can use the following options to improve implementation results Detailed information for these options can be found in the Development System Reference Guide Map Timing Option Use the Xilinx Map program Timing option to improve timing during the mapping phase This switch directs the mapper to give priority to timing critical paths during packing To use this feature at the command line use the timing switch See the Development System Reference Guide for more information Extra Effort Mode in PAR Use the Xilinx PAR program Extra Effort mode to invoke advanced algorithmic techniques to provide higher quality results To use this feature at the command line use the xe level switch The level can be a value from 0 to 5 the default is 1 Using level 0 turns off all extra effort off and can significantly increase runtime See the Development System Reference Guide for more information Multi Pass Place and Route Use this feature to place and route your design with several different cost tables seeds to find the best possible placement for your design This optimal placement results in shorter routing delays and faster designs This works well when the router passes are limited with the i option After an optimal cost table is selected use the reentrant routing feature to finish the routing of your design To use this feature double click on M
409. your designs for an extended period of time during the night or weekend e If the targeted device is highly utilized the routing may become congested and your design may be difficult to route In this case the placer and router may take longer to meet your timing requirements e If design constraints are rigorous it may take longer to correctly place and route your design and meet the specified timing Decreasing Implementation Time The options you select for the placement and routing of your design directly influence the run time Generally these options decrease the run time at the expense of the best placement and routing for a given device Select your options based on your required design performance Note f you are using the command line the appropriate command line option is provided in the following procedure Use the following steps to decrease implementation time in the Project Navigator For details on implementing your design in Project Navigator see Project Navigator Online Help 1 Inthe Project Navigator Process Window right click Place amp Route and then select Properties The Process Properties dialog box appears Set options in this dialog box as follows Place amp Route Effort Level Generally you can reduce placement times by selecting a less CPU intensive algorithm for placement You can set the placement level at one of five settings 40 www xilinx com Synthesis and Verification Design Guide 1

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