Analog Devices AD5258BRMZ1 datasheet
Contents
1. 80 CODE MIDSCALE Viogic Ve 0V II l PSRR 5V DC 10 60 b 40 PSRR Q V ogic DC 10 AC N 20 0 100 1k 10k 100k 1M FREQUENCY Hz Figure 27 PSRR vs Frequency 400ns DIV Figure 28 Digital Feedthrough 05029 053 us DIV Figure 29 Midscale Glitch Code Ox7F to 0x80 05029 055 05029 056 105258 2V DIV 5V DIV 200ns DIV Figure 30 Large Signal Settling Time 05029 054 Rev 0 Page 12 of 24 105258 TEST CIRCUITS Figure 31 through Figure 36 illustrate the test circuits that define the test conditions used in the product specification tables V V 10 1LSB V 2N Vus PSRR dB 20 LoG avon Vus 8 Figure 31 Test Circuit for Potentiometer Divider Nonlinearity Error INL DNL Figure 34 Test Circuit for Power Supply Sensitivity PSS PSSR NO CONNECT Q Figure 32 Test Circuit for Resistor Position Nonlinearity Error Figure 35 Test Circuit for Gain vs Frequency Rheostat Operation R INL R DNL Rew DUT sw CODE 0x00 05029 032 GND TO Vpp 05029 035 Figure 33 Test Circuit for Wiper Resistance Figure 36 Test Circuit for Common Mode Leakage Current Rev 0 Page 13 of2. 40 20 0 20 40 60 80 Figure 21 Total Resistance vs Temperature 0 20H 6 10 12 08H 18 04 24 H 01 30 36 42 48 54 8 60 8 10 100 1 10 100 FREQUENCY Hz Figure 22 Gain vs Frequency vs Code Ras 1 n 7 d 1k 10k Figure 23 Gain vs Frequency vs Code Ras 10 100k 1M FREQUENCY Hz 05029 023 10 GAIN dB GAIN dB ILoaic HA 0 20 6 H 10 12 08 18 2 04 24 024 30 01 36 42 48 54 60 1k 10k 100k 1M FREQUENCY Hz Figure 24 Gain vs Frequency vs Code Ras 50 0 20H 6 10 12 H 08 18 04 24 H 024 30 O14 36 42 48 54 60 1k 10k 100k 1M FREQUENCY Hz Figure 25 Gain vs Frequency vs Code Ras 100 10k Voo Vioaic 5V 1k Voo Vioaic 100 t 4 10 1 0 1 2 3 4 5 V Figure 26 Logic Supply Current vs Input Voltage 05029 024 05029 025 05029 052 Rev 0 Page 11 of 24 PSRR dB 500mV DIV 5V DIV 200mV DIV AD5258
3. 0 0 1 0 2 0 3 0 4 0 5 0 8 16 24 65 40 48 56 64 CODE Decimal Figure 6 R INL vs Code vs Supply Voltage CODE Decimal Figure 7 R DNL vs Code vs Supply Voltages 85 C 40 C 25 8 16 24 65 40 48 56 64 CODE Decimal Figure 8 INL vs Code vs Temperature 05029 015 05029 017 05029 010 Rev 0 Page 8 of 24 POTENTIOMETER MODE DNL LSB 0 8 16 24 65 40 48 56 64 CODE Decimal Figure 9 DNL vs Code vs Temperature 0 10 0 08 0 06 0 04 2 7V 0 02 0 02 5 5V 0 04 0 06 1 5 0 08 0 10 0 8 16 24 65 40 48 56 64 CODE Decimal Figure 10 INL vs Supply Voltages POTENTIOMETER MODE DNL LSB CODE Decimal Figure 11 DNL vs Code vs Supply Voltages 05029 012 05029 011 05029 013 105258 0 50 0 45 ZSE Vpp 2 7V 0 40 ZSE Vpp 5 5V ZSE LSB N oa RHEOSTAT MODE INL LSB 05029 014 05029 048 CODE Decimal TEMPERATURE C Figure 12 R INL vs Code vs Temperature Figure 15 Zero Scale Error vs Temperature RHEOSTAT MODE DNL
4. 2 10 nA DIGITAL INPUTS AND OUTPUTS Input Logic High 0 7 0 5 V Input Logic Low Vit 0 5 0 3 V Leakage Current SDA ADO AD1 Vin OVor5V 0 01 1 SCL Logic High Vin OV 2 5 1 4 1 SCL Logic Low Vin 5V 0 01 1 Input Capacitance C 5 pF Rev 0 Page 3 of 24 105258 Parameter Symbol Conditions Min Unit POWER SUPPLIES Power Supply Range Voo 27 5 5 Positive Supply Current 0 5 2 Logic Supply 2 7 5 5 V Logic Supply Current lLocic Vn 5VorVi OV 3 5 6 Programming Mode Current EEPROM Vn 5VorVi O0V 35 mA Power Dissipation Poiss 5 V or 0 Voo 5 V 20 40 uW Power Supply Rejection Ratio PSRR Voo 5 V 10 Code 0x20 0 01 0 06 DYNAMIC CHARACTERISTICS Bandwidth 3 dB BW Code 0x20 1 18000 kHz Ras 10 KQ 1000 kHz Ras 50 kQ 190 kHz Ras 100 kQ 100 kHz Total Harmonic Distortion THDw Ras 10 Va 1 V rms Vs 0 0 1 f 1 kHz Vw Settling Time ts Ras 10 5 V 500 ns 1 LSB error band Resistor Noise Voltage Density Rws 5 f 1 kHz 9 nV 4Hz Typical values represent average readings at 25 C and 5 V Rev 0 Page 4 of 24 TIMING CHARACTERISTICS Vpp Vioaic 5 V 10 or 3 10 Va Von Vs 0 V 40 lt Ta lt 85 C unless otherwise noted AD5258 Table 2 Parameter Symbol C
5. 2 Writing In the write mode the last bit R W of the slave address byte is logic low The second byte is the instruction byte The first three bits of the instruction byte are the command bits see Table 6 The user must choose whether to write to the RDAC register EEPROM register or activate the software write protect see Table 7 to Table 10 The final five bits are all zeros see Table 13 to Table 14 The slave again responds by pulling the SDA line low during the ninth clock pulse The final byte is the data byte MSB first Don t cares can be left either high or low In the case of the write protect mode data is not stored rather a logic high in the LSB enables write protect Likewise a logic low will disable write protect The slave again responds by pulling the SDA line low during the ninth clock pulse 3 Storing Restoring In this mode only the address and instruction bytes are necessary The last bit R W of the address byte is logic low The first three bits of the instruction byte are the command bits see Table 6 The two choices are transfer data from RDAC to EEPROM Rev 0 Page 15 of 24 AD5258 store or from EEPROM to RDAC restore The final five bits are all zeros see Table 13 to Table 14 Reading Assuming the register of interest was not just written to it is necessary to write a dummy address and instruction byte The instruction byte will vary depending on whether the data that is wanted is th
6. Vs 0 V 40 lt Ta lt 85 C unless otherwise noted AD5258 Table 1 Parameter Symbol Conditions Min Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity R DNL Rvs Va no connect LSB 1 5 0 3 1 5 10 50 100 0 25 0 1 0 25 Resistor Integral Nonlinearity R INL Rwe Va no connect LSB 5 0 5 5 10 kQ 100 0 5 0 1 0 5 50 0 25 0 1 0 25 Nominal Resistor Tolerance Ta 25 C 5 5 V Ras 0 9 1 5 kQ 10 50 100 ARas 30 30 Resistance Temperature Coefficient ARas x 109 Ras AT Code 0x00 0x20 200 15 ppm C Total Wiper Resistance Rwe Code 0x00 75 350 DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Differential Nonlinearity DNL LSB 1 0 3 1 10 50 100 0 25 0 1 0 25 Integral Nonlinearity INL LSB 1 0 3 1 10 50 100 0 25 0 1 0 25 Full Scale Error Vwese Code 0x3F LSB 6 3 0 10 kQ 1 0 3 0 50 100 1 0 1 0 Zero Scale Error Vwzse Code 0x00 LSB 1kQ 0 3 5 10 0 0 3 1 50 100 0 0 1 0 5 Voltage Divider Temperature AVw x 10 Vw x AT Code 0x00 0x20 120 15 ppm C Coefficient RESISTOR TERMINALS Voltage Range Va 8 w GND V Capacitance A B CA 8 f 1 MHz measured to GND 45 pF code 0x20 Capacitance W Cw f 1 MHz measured to GND 60 pF code 0x20 Common Mode Leakage Icm Va Vs
7. 24 105258 THEORY OF OPERATION The AD5258 is a 64 position digitally controlled variable resistor VR device The wiper s default value prior to programming the EEPROM is midscale PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance Ras of the RDAC between Terminal A and Terminal is available in 1 10 50 and 100 The nominal resistance of the VR has 64 contact points accessed by the wiper terminal The 6 bit data in the RDAC latch is decoded to select one of 64 possible settings Figure 37 Rheostat Mode Configuration 05029 036 The general equation determining the digitally programmed output resistance between Wiper W and Terminal B is D Ryp D x Rag 2 Ry 1 where Dis the decimal equivalent of the binary code loaded in the 6 bit RDAC register is the end to end resistance Rwis the wiper resistance contributed by the on resistance of each internal switch RDAC LATCH AND DECODER 05029 037 Figure 38 AD5258 Equivalent RDAC Circuit Note that in the zero scale condition there is a relatively low value finite wiper resistance Care should be taken to limit the current flow between Wiper W and Terminal B in this state to a maximum pulse current of no more than 20 mA Otherwise degradation or destruction of the internal switch contact can occur Similar to the mechanical potentiometer the resistance of the RDAC between Wiper
8. W and Terminal A produces a digitally controlled complementary resistance Rwa The resistance value setting for Rwa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value The general equation for this operation is Ry D A x Ray 2 Ry 2 Typical device to device matching is process lot dependent and may vary by up to 30 For this reason resistance tolerance is stored in the EEPROM such that the user will know the actual Ras within 0 1 PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates a voltage divider at Wiper W to Terminal B and Wiper W to Terminal A propor tional to the input voltage at Terminal A to Terminal B Unlike the polarity of Vp to GND which must be positive voltage across Terminal A to Terminal B Wiper W to Terminal A and Wiper W to Terminal B can be at either polarity 8 2 S Figure 39 Potentiometer Mode Configuration If ignoring the effect of the wiper resistance for approximation connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at Wiper W to Terminal B starting at 0 V up to 1 LSB less than 5 V The general equation defining the output voltage at Vw with respect to ground for any valid input voltage applied to Terminal A and Terminal B is 64 D 3 D Wi Mm 64 A more accurate calculation which includes the effect of w
9. storage in the 11111 if read consecutively nonvolatile memory The tolerance is stored in the memory during factory production and can be read by users at any time In the first memory location the MSB is designated for the sign The knowledge of stored tolerance allows users to accurately 0 and 1 and the seven LSBs are designated for the integer portion of the tolerance In the second memory location all eight data bits are designated for the decimal portion of tolerance Note that the decimal portion has a limited accuracy of only 0 196 For example if the rated Ras 10 and the data readback from Address 11110 shows 0001 1100 and Address 11111 shows 0000 1111 then the tolerance can be calculated as calculate Ras This feature is valuable for precision rheostat mode and open loop applications where knowledge of absolute resistance is critical The stored tolerance resides in the read only memory and is expressed as a percentage The tolerance is stored in two memory location bytes in sign magnitude binary form see Figure 40 The two EEPROM address bytes are 11110 sign integer and MSB 0 11111 decimal number The two bytes can be individually Next 7 MSB 001 1100 28 accessed with two separate commands see Table 15 Alternatively 8 LSB 0000 1111 15 x 2 0 06 readback of the first byte followed by the second byte can be Tolerance 28 06 done in one command see Table 16 In the latter case
10. to use More detailed information is available in the user manual that comes with the board 5258 Revo Analog Devices AD5258 Enter Data Write Restore Store Data Read Data Zero Write to n Read trom RDAC ite to Mid p sil s Restore Content to RDAC Store RDAC 5 poh m Read Tolerance 8 Etuis 8 8 8 Figure 44 AD5258 Evaluation Board Software Rev 0 Page 19 of 24 105258 DISPLAY APPLICATIONS CIRCUITRY A special feature of the AD5258 is its unique separation of the Vioarc and Vpp supply pins The reason for doing this is to provide greater flexibility in applications that do not always provide needed supply voltages In particular LCD panels often require a Vcow voltage in the range of 3 V to 5 V The circuit in Figure 45 is the rare exception in which a 5 V supply is available to power the digital potentiometer 3 5 lt Vcom lt 4 5V 05029 006 Figure 45 Adjustment Application In the more common case shown in Figure 46 only analog 14 4 V and digital logic 3 3 V supplies are available By placing discrete resistors above and below the digital pot Vpp can now be tapped off the resistor string itself Based on the chosen resistor values the voltage at Vpn in this case equals 4 8 V allowing the wiper to be safely operated all the way up to 4 8 V The current draw of will not affect that nod
11. 6 of 24 105258 WRITE MODES Table 8 Writing to RDAC Register 7 Bit Device Address pe Table 5 D5 D4 03 02 D1 Table 9 Writing to EEPROM Register 7 Bit Device Address BENE Table 5 D5 D4 D3 D2 D1 The wiper s default value prior to programming the EEPROM is midscale Table 10 Activating Deactivating Software Write Protect 7 Bit Device Address EL UT Table 5 s WP Ex In O O O to activate the write protection the WP bit in Table 10 must be logic TR In order to deactivate the write protection the command must be sent again except with the WP in logic zero state READ MODES written to For example if the EEPROM was just written to then the user can skip the two dummy bytes and proceed directly to the slave address byte followed by the EEPROM readback data Read modes are referred to as traditional because the first two bytes for all three cases are dummy bytes which function to place the pointer towards the correct register This is the reason for the repeat start In theory this step can be avoided if the user is interested in reading a register that was previously Table 11 Traditional Readback of RDAC Register Value 7 Bit Device Address 7 Bit Device Address See Table 5 See Table 5 Slave Address Byte Address Slave Address Byte InstructionByte Slave Address Byte Back Data p Repeat start Table 12 Traditional Readback of Stored EEPRO
12. ANALOG Nonvolatile I C Compatible AD5258 FEATURES FUNCTIONAL BLOCK DIAGRAMS Nonvolatile memory maintains wiper settings 64 position QA Compact MSOP 10 3 mm x 4 9 mm package QW PC compatible interface pin provides increased interface flexibility E End to end resistance 1 kO 10 kO 50 kO 100 kO SUA 6 CONTROL INTERFACE Resistance tolerance stored in EEPROM 0 196 accuracy Power on EEPROM refresh time lt 1 ms DECODE LOGIC Software write protect command DECODE LOGIC Three state Address Decode Pins ADO and AD1 allow 9 packages per bus 100 year typical data retention at 55 C Wide operating temperature 40 C to 85 C AD5258 05029 001 3 V to 5 V single supply i us APPLICATIONS LCD panel Vcom adjustment n REGISTER LCD panel brightness and contrast control uL SHIFTER Mechanical potentiometer replacement in new designs p Programmable power supplies ADGRESS RF amplifier biasing Automotive electronics adjustment 20006 05029 003 Gain control and offset adjustment Fiber to the home systems Electronics level settings Figure 2 Block Diagram Showing Level Shifters GENERAL DESCRIPTION CONNECTION DIAGRAM The AD5258 provides a compact nonvolatile 3 mm x 4 9 mm packaged solution for 64 position adjustment applications These devices perform the same electronic adjustment function as mechanical potentiometer
13. LSB Ibp SUPPLY CURRENT 05029 016 05029 045 0 8 16 24 65 40 48 56 64 CODE Decimal TEMPERATURE C Figure 13 R DNL vs Code vs Temperature Figure 16 Supply Current vs Temperature FSE Vpp 2 7V lLogic LOGIC SUPPLY CURRENT uA 05029 046 05029 049 0 50 0 40 20 0 20 40 60 80 40 20 0 20 40 60 80 TEMPERATURE Figure 14 Full Scale Error vs Temperature Figure 17 Logic Supply Current vs Temperature vs Rev 0 Page 9 of 24 105258 MODE TEMPCO 250 200 150 100 50 CODE Decimal 05029 019 1k Va 50k 10k 1 zA ura E gt 100 8 16 24 65 40 48 56 64 Figure 18 Rheostat Mode Tempco ARas 109 Ras x AT vs Code POTENTIOMETER MODE TEMPCO 120 100 80 60 40 20 20 1k 50k 10k 100k 16 24 65 40 CODE Decimal 05029 018 48 56 64 Figure 19 Potentiometer Mode Tempco AVw x 105 Vw x AT vs Code Rwg 0x00 Figure 20 Rws vs Temperature TEMPERATURE 05029 047 Rev 0 Page 10 of 24 GAIN dB TOTAL RESISTANCE GAIN dB 100k Rt Vpp 5 5V 05029 050
14. M Value 7 Bit Device Address See Table 5 Ap Slave Address Byte e Slave Address Byte Address Slave Address Byte Read Back Data Repeat start STORE RESTORE MODES Table 13 Storing RDAC Value to EEPROM 7 Bit Device Address See Table 5 1 1 Slave Address instruction Byre 7 Bit Device Address See Table 5 Slave Address Byte 0 17 24 105258 TOLERANCE READBACK MODES Table 15 Traditional Readback of Tolerance Individually 7 Bit Device Address See Table 5 Slave Address Byte 5 7 Bit Device Address See Table 5 Slave Address Byte 5 Repeat start Decimal Byte instruction p Table 16 Traditional Readback of Tolerance Consecutively 7 Bit Device Address 7 Bit Device Address See Table 5 See Table 5 Slave Address Byte Slave Address Byte S m ae Byte Decimal Repeat start Calculating Ras Tolerance Stored in Read Only Memory 07 06 05 D4 03 02 DI 00 A 7 D 05 03 02 Di Do SIGN 26 25 24 23 92 p 2 21 22 23 24 25 26 27 23 J 8 SIGN 7 BITS FOR INTEGER NUMBER 8 BITS FOR DECIMAL NUMBER E Figure 40 Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions Unit is Percent Only Data Bytes are Shown the second EEPROM location increments from 11110 to The AD5258 features a patented Ras tolerance
15. P 10 RM 10 D4K AD5258BRMZ1 R7 1k 40 to 85 C MSOP 10 RM 10 D4K AD5258BRMZ10 10k 40 C to 85 MSOP 10 RM 10 D4L AD5258BRMZ10 R7 10k 40 85 C MSOP 10 RM 10 D4L AD5258BRMZ50 50k 40 to 85 C MSOP 10 RM 10 D4M AD5258BRMZ50 R7 50k 40 C to 85 MSOP 10 RM 10 D4M AD5258BRMZ100 100 k 40 to 85 C MSOP 10 RM 10 DAN AD5258BRMZ100 R7 100 k 40 to 85 C MSOP 10 RM 10 DAN AD5258EVAL Evaluation Board 17 Pb free part The evaluation board is shipped with the 10 Ras resistor option however the board is compatible with all available resistor value options Rev 0 Page 21 of 24 105258 NOTES Rev 0 Page 22 of 24 005258 NOTES Rev 0 Page 23 of 24 105258 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips Patent Rights to use these components an system provided that the system conforms to the I C Standard Specification as defined by Philips 2005 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D05029 0 3 05 0 ANALOG DEVICES Rev 0 Page 24 of 24 www analog com
16. Std 22 Method A117 Retention lifetime based on an activation energy of 0 6eV derates with junction temperature SCL SDA Figure 4 PC Interface Timing Diagram Rev 0 Page 5 of 24 05029 004 105258 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 3 Parameter Value Voo to GND 0 3Vto 47V Va Ve Vw to GND GND 0 3 V Voo 0 3 V Pulsed 20 mA Continuous 5 mA Digital Inputs and Output Voltage OV to 7 V Operating Temperature Range 40 to 85 C Maximum Junction Temperature Tmax 150 C Storage Temperature 65 to 150 C Lead Temperature Soldering 10 sec 300 C Thermal Resistance MSOP 10 200 C W 1 Maximum terminal current is bounded by the maximum current handling of the switches maximum power dissipation of the package and maximum applied voltage across any two of the A B and W terminals at a given resistance 2 Package power dissipation Tmax ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operat
17. TENTS SPECI CALI ONS onset AREE AE ETO 3 Electrical Characteristics seen Timing Characteristics essent 5 Absolute Maximum Ratings eerte 6 ESD Caution cette orte En eet ree 6 Pin Configuration and Function 5 7 Typical Performance Characteristics sees 8 Test CITCUIU adeo eit ederet teet tent 13 Theory of Operation iuit Rite i teal 14 Programming the Variable Resistor sss 14 Programming the Potentiometer Divider 14 PG Interface ec esent on eie 15 FC Byte Formats as ense teta 16 Generic eee 16 REVISION HISTORY 3 05 Revision 0 Initial Version e ee 17 Read 17 Store Restore Modes E EU 17 Tolerance Readback Modes sss 18 ESD Protection of Digital Pins and Resistor Terminals 19 Power Up Sequence seen 19 Layout and Power Supply Bypassing sss 19 Multiple Devices on One Bus serene 19 Evaluation Boatd e isset 19 Display Applications cette pne ette 20 Pisis 20 Outline Dimensions i eee ote e S 21 Ordering Guide snittar i 21 Rev 0 Page 2 of 24 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Vpp Vioarc 5 V 10 or 3 10 Va
18. e RDAC register EEPROM register or tolerance register see Table 11 to Table 16 After the dummy address and instruction bytes are sent a repeat start is necessary After the repeat start another address byte is needed except this time the R W bit is logic high Following this address byte is the readback byte containing the information requested in the instruction byte Read bits appear on the negative edges of the clock Dont cares may either be in a high or low state The tolerance register can be read back individually see Table 15 or consecutively see Table 16 Refer to the Read Modes section for detailed information on the interpreta tion of the tolerance bytes After all data bits have been read or written a STOP condition is established by the master A STOP condition is defined as a low to high transition on the SDA line while SCL is high In write mode the master pulls the SDA line high during the tenth clock pulse to establish a STOP condition see Figure 45 In read mode the master issues a no acknowledge for the ninth clock pulse that is the SDA line remains high The master then brings the SDA line low before the tenth clock pulse and then raises SDA high to establish a STOP condition see Figure 46 A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once For example after the RDAC has acknowledged its slave addre
19. es bias because it is only on the order of microamps is tied to the MCUS 3 3 V digital supply because Vioac will draw the 35 mA which is needed when writing to the EEPROM It would be impractical to try and source 35 mA through the 70 resistor therefore Vioaic is not connected to the same node as Vp For this reason Viocic and Vp are provided as two separate supply pins that can either be tied together or treated inde pendently supplying the logic EEPROM with power and Vp biasing up the B and W terminals for added flexibility VCC 3 3V SUPPLIES 144 9 TO BOTH THE 9 MICRO AND THE LOGIC SUPPLY OF THE DIGITAL POT R1 U1 AD8565 3 5V lt Vcom lt 4 5V 05029 007 Figure 46 Circuitry When a Separate Supply is Not Available for For a more detailed look at this application refer to the article Simple VCOM Adjustment uses any Logic Supply Voltage in the September 30 2004 issue of EDN magazine Rev 0 Page 20 of 24 OUTLINE DIMENSIONS AD5258 0 95 0 85 1 10 MAX Hemme 015 f ar dle SEATING 023 4 gt e 0 60 0 00 0 17 PLANE 0 08 0 40 COPLANARITY 0 10 COMPLIANT TO JEDEC STANDARDS MO 187BA Figure 47 10 Lead Mini Small Outline Package MSOP RM 10 Dimensions shown in millimeters ORDERING GUIDE Model Ras Q Temperature Package Description Package Option Branding AD5258BRMZ1 1k 40 to 85 C MSO
20. ional section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability WARNING lt proprietary ESD protection circuitry permanent damage occur on devices subjected to high energy Spr electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Rev 0 Page 6 of 24 105258 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4 Pin Function Descriptions 05029 008 Figure 5 Pin Configuration Pin No Mnemonic Description 1 W Terminal GND lt Vw lt Vpp 2 ADO Programmable Three State Address Bit 0 for Multiple Package Decoding State is registered on power up 3 AD1 Programmable Three State Address Bit 1 for Multiple Package Decoding State is registered on power up 4 SDA Serial Data Input Output 5 SCL Serial Clock Input Positive edge triggered 6 Logic Power Supply 7 GND Digital Ground 8 Voo Positive Power Supply 9 B B Terminal GND x Vs lt 10 A A Terminal GND lt Va lt Rev 0 Page 7 of 24 105258 TYPICAL PERFORMANCE CHARACTERISTICS Vioaic 5 5 V Ras 10 Ta 25 C unless otherwise noted RHEOSTAT MODE INL LSB STAT MODE DNL LSB POTENTIOMETER MODE INL LSB 0 08 0 10 0 0 5 0 4 0 3 0 2 0 1
21. iper resistance Vw is Ryp D v D Bus D AB Rp D V RwalP dy ae 4 AB Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature Unlike the rheostat mode the output voltage is dependent mainly on the ratio of the Internal Resistors Rwa and Rws and not the absolute values Rev 0 Page 14 of 24 INTERFACE Note that the wiper s default value prior to programming the EEPROM is midscale 1 master initiates data transfer by establishing a START condition when a high to low transition on the SDA line occurs while SCL is high see Figure 4 The next byte is the slave address byte which consists of the slave address first 7 bits followed by an R W bit see Table 6 When the R W bit is high the master reads from the slave device When the R W bit is low the master writes to the slave device The slave address of the part is determined by two three state configurable Address Pins ADO and AD1 The state of these two pins is registered upon power up and decoded into a corresponding 7 bit address see Table 5 The slave address corresponding to the transmitted address bits responds by pulling the SDA line low during the ninth clock pulse this is termed the slave acknowledge bit At this stage all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register 5
22. onditions Min Typ Max Unit INTERFACE TIMING CHARACTERISTICS SCL Clock Frequency 0 400 kHz teur Bus Free Time between STOP and START ti 1 3 Us Hold Time Repeated START t After this period the first clock pulse is 0 6 us generated trow Low Period of SCL Clock ts 1 3 us High Period of SCL Clock t4 0 6 us tsusta Setup Time for Repeated START ts 0 6 us Condition tup pat Data Hold Time te 0 0 9 us tsu par Data Setup Time t 100 ns tr Fall Time of Both SDA and SCL Signals ts 300 ns tr Rise Time of Both SDA and SCL Signals to 300 ns tsusro Setup Time for STOP Condition tio 0 6 Us EEPROM Data Storing Time STORE 26 ms EEPROM Data Restoring Time at Power teemem_restore1 rise time dependant Measure 300 us without decoupling capacitors at Voo and GND EEPROM Data Restoring Time upon Restore teemem_restore2 5 V 300 us Command EEPROM Data Rewritable Time TEEMEM REWRITE 540 us FLASH EE MEMORY RELIABILITY Endurance 100 700 kCycles Data Retention 100 Years 1 During power up the output is momentarily preset to midscale before restoring EEPROM content Delay time after power on PRESET prior to writing new EEPROM data 3 Endurance is qualified to 100 000 cycles per Std 22 method A117 and is measured at 40 25 C and 85 C typical endurance at 25 C is 700 000 cycles 4 Retention lifetime equivalent at junction temperature 55 C per
23. rc LAYOUT AND POWER SUPPLY BYPASSING It is good practice to employ compact minimum lead length layout design The leads to the inputs should be as direct as possible with minimum conductor length Ground paths should have low resistance and low inductance AD5258 Similarly it is also good practice to bypass the power supplies with quality capacitors for optimum stability Supply leads to the device should be bypassed with disc or chip ceramic capacitors of 0 01 uF to 0 1 uF Low ESR 1 uF to 10 pF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple see Figure 43 The digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce 05029 041 Figure 43 Power Supply Bypassing MULTIPLE DEVICES ON ONE BUS The AD5258 has two three state configurable Address Pins ADO and ADI The state of these two pins is registered upon power up and decoded into a corresponding I C 7 bit address see Table 5 This allows up to nine devices on the bus to be written to or read from independently In the case that the pin is assigned to be floated the static voltage will be Viocic 2 EVALUATION BOARD An evaluation board along with all necessary software is available to program the AD5258 from any PC running Windows 98 2000 XP The graphical user interface as shown in Figure 44 is straightforward and easy
24. s or variable resistors but with enhanced resolution and solid state reliability 05029 002 Figure 3 Pinout The wiper settings are controllable through an I C compatible digital interface that is also used to read back the wiper register and EEPROM content Resistor tolerance is also stored within EEPROM providing an end to end tolerance accuracy of 0 1 There is also a software write protection function that ensures data cannot be written to the EEPROM register 2 PEE The terms digital potentiometer VR variable resistor and RDAC are used A separate delivers increased interface flexibility For interchangeably users who need multiple parts on one bus Address Bit ADO and Address Bit ADI allow up to nine devices on the same bus Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A or otherwise under any patent or patent rights of Analog Devices Trademarks and Tel 781 329 4700 www analog com registered trademarks are the property of their respective owners Fax 781 326 8703 2005 Analog Devices Inc All rights reserved 105258 TABLE OF CON
25. ss and instruction bytes in the write mode the RDAC output is updated on each successive byte until a STOP condition is received If different instructions are needed the write read mode has to start again with a new slave address instruction and data byte Similarly a repeated read function of the RDAC is also allowed 5258 BYTE FORMATS The following generic write read and store restore control Table 5 Device Address Lookup registers for the AD5258 all refer to the device addresses listed ADI and ADO are three state address pins in E 5 and the modes condition reference key S P SA MA Device Address and X listed below Start Condition 0011001 0 0011010 1 0 Stop Condition 0101001 0 NC 0101010 NC NC SA Slave Acknowledge i Master Acknowledge 1001100 0 1 1001101 NC 1 Acknowledge 1001110 1 1 W Write R Read X Dont Care GENERIC INTERFACE Table 6 Generic Interface Format Slave Address Byte Address Slave Address Byte Instruction Byte Data Byte Table 7 RDAC to EEPROM Interface Command Descriptions C2 C1 co Command Description 0 0 0 Operation between 2 and RDAC 0 0 1 Operation between and EEPROM 0 1 0 Operation between I C and Write Protection Register See Table 10 1 0 0 NOP 1 0 1 Restore EEPROM to RDAC 1 1 0 Store RDAC to EEPROM Rev 0 Page 1
26. the Rounded islerance 4281 amd therefore memory pointer will automatically increment from the first to Ras acruaL 12 810 kQ Rev 0 Page 18 of 24 ESD PROTECTION OF DIGITAL PINS AND RESISTOR TERMINALS The AD5258 Vp Viocic and GND power supplies define the boundary conditions for proper 3 terminal and digital input operation Supply signals present on Terminal A Terminal B and Terminal W that exceed GND are clamped by the internal forward biased ESD protection diodes see Figure 41 Digital Input SCL and Digital Input SDA are clamped by ESD protection diodes with respect to Vioaic and GND as shown in Figure 42 Vpp GND 05029 039 Figure 41 Maximum Terminal Voltages Set by Vpp and GND SCL SDA 05029 040 GND Figure 42 Maximum Terminal Voltages Set by and GND POWER UP SEQUENCE Because the ESD protection diodes limit the voltage compliance at Terminal A Terminal B and Terminal W see Figure 41 it is important to power GND Vopp Viocic before applying any voltage to Terminal A Terminal B and Terminal W otherwise the diode is forward biased such that and Viocic are powered unintentionally and may affect the user s circuit The ideal power up sequence is in the following order GND Vioarc digital inputs and then Va Vs Vw The relative order of powering Va Vw and the digital inputs is not important as long as they are powered after GND Vopp Vioa
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