XEM3005 User`s Manual
Contents
1. _ o5 42 00 9 39 00 Si 4 37 00 O 5 SPA 2 ua 294 22 8 5 8 o9 TO lt an Ooo EE ig l a kH F L 13 70 1 BSS oa 2 T 7 5 00 3 00 TON 1 52 moo O Q re t 1 OOOO 28 5 ca 8 34 33 LL f 99 a F E SAR HL 862. 12 SDRAM 12 Clock Configuration 13 Expansion 14 EEA ea a See RA ere 14 asco eos ere Ses atic 14 setting Bank 3 I O Voltage 15 SPI Configuration PROM wath dea 15 Booting from PROM dsc 15 Programming the 15 XEM3005 Mechanical Drawing 16 BRK3005 Mechanical Drawing 17 XEM3005 User s Manual 4 www opalkelly com XEM3005 User s Manual Introducing the XEM3005 The XEM3005 is a compact 64mm x 42mm 2 52 x 1 65 FPGA board featuring the Xilinx Spartan 3E FPGA and a high speed USB 2 0 interface Designed as a full featured integration system the XEM3005 provides access to 103 I O pins on its 256 pin Spartan 3E device and has 32 MByte SDRAM available to the FPGA The XEM3005 is designed to work with small to medium sized FPGA designs with a wide variety of external interface requirements PCB Footprint A mechanical drawing of the XEM3005 is shown at the end of this manual The PCB is 64mm x 42mm with four mounting holes spaced as shown in the figure These mounting holes are electrically isolated from all signals on the XEM3005 The USB connector overhangs the PCB by approximately 2mm in order to accommodate mounting wit
3. s Opal Kelly XEM3005 User s Manual A compact 64mm x 42mm integration board featuring the Xilinx Spartan 3E FPGA and on board SDRAM The XEM3005 is a compact USB based FPGA integration board featuring the Xilinx Spartan 3E FPGA optional 32 MB 16 bit wide SDRAM SPI configuration PROM and two high density 0 8 mm expansion connectors The USB 2 0 interface provides fast configuration downloads and communication as well as easy access with our popular FrontPanel software and developer s API An on board clock generation device has six flexible outputs available to the FPGA SDRAM and expansion connectors Software documentation samples and related materials are Copyright 2006 2014 Opal Kelly Incorporated Opal Kelly Incorporated Portland Oregon http www opalkelly com All rights reserved Unauthorized duplication in whole or part of this document by any means except for brief excerpts in published reviews is prohibited without the express written permission of Opal Kelly Incorporated Opal Kelly the Opal Kelly Logo and FrontPanel are trademarks of Opal Kelly Incorporated Linux is a registered trademark of Linus Torvalds Microsoft and Windows are both registered trademarks of Microsoft Corporation All other trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed Revision History 20060915 Initial release 20070404 Added trace length
4. After configura tion these pins are used to allow FrontPanel communication with the FPGA If the FrontPanel okHostInterface module is instantiated in your design you must map the in terface pins to specific pin locations using Xilinx LOC constraints This may be done using the Xilinx constraints editor or specifying the constraints manually in a text file An example is shown below Xilinx constraints for okHostInterface pin mappings www opalkelly com 9 XEM3005 User s Manual 10 hi in lt gt hi lt 1 gt hi in lt 2 gt hi in lt 3 gt hi in lt 4 gt hi in lt 5 gt hi in lt 6 gt hi in lt 7 gt hi_out lt gt hi_out lt 1 gt hi inout lt gt hi inout lt 1 gt hi inout lt 2 gt hi inout lt 3 gt hi inout lt 4 gt hi inout lt 5 gt hi inout lt 6 gt hi inout lt 7 gt hi inout lt 8 gt hi inout lt 9 gt hi inout lt 10 gt hi inout lt 11 gt hi inout lt 12 gt hi inout lt 13 gt hi inout lt 14 gt hi inout lt 15 gt F9 N5 ETO p13 N12 56 N10 M8 N8 ERS Poe N9 9 RI R6 58 ERAR M6 N6 P6 Each of the samples installed with FrontPanel includes a copy of a template constraints file that lists all the XEM30
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6. board and connects to the FPGA JTAG pins These pins are also mirrored to the expansion connector JP4 The JP1 pins are connected as shown below ut Pin Signal ws 5 SDRAM Connections The SDRAM is connected to the 3 3v I O on Banks 0 and 1 of the FPGA None of these pins are shared with the expansion connectors The tables below list these connections 12 www opalkelly com SDRAM Pin FPGA Pin XEM3005 User s Manual SDRAM Pin FPGA Pin e Clock Configuration The XEM3005 has been designed to support SDRAM clocking in both system synchronous and source synchronous modes Both configurations are often referenced in Xilinx applica tion notes describing SDRAM controllers and interfaces including XAPP462 Using DCMs in Spartan 3 The block diagram below shows how the clock signals are routed on the XEM3005 PCB in the default factory configuration R29 SYS_CLK1 A8 GCLK8 9 GCLK7 Rag FPGA VW not inserted System Synchronous from the PLL Default Configuration Remove R28 Insert R29 PLL drives SYS_CLK1 This is the default configuration Expansion JP3 In this mode the clock signal is sourced at the system level by the PLL on the XEM3005 The same clock is fanned out to both the FPGA pin A8 GCLK8 and the SDRAM CLK The FPGA therefore considers this sig
7. 05 pins and maps them to the appropriate FPGA pins using LOC location constraints You can use this template to quickly get the pin locations correct on a new design MUXSEL MUXSEL is a signal on the XEM3005 which selects the signal path to the FPGA programming signals DO and CCLK When low deasserted the FPGA and USB microcontroller are connect ed When high asserted the FPGA and PROM are connected In normal USB programmed operation switch JP2 is at USB Config pulling MUXSEL low and connecting the FPGA and USB microcontroller at all times This allows USB based program ming of the FPGA and subsequent USB communication with the FPGA design after configura tion In order to allow the PROM to configure the FPGA JP2 must be at PROM Config However if the USB is to communicate with the FPGA post configuration MUXSEL must be deasserted Therefore the FPGA outputs MUXSEL so that post configuration the FPGA can deassert MUX SEL and communicate over USB even after the PROM has configured it The end result is that your FPGA design should tie HI_MUXSEL to 0 This is the case regardless of how the design was configured via PROM or USB For example in Verilog assign hi_muxsel 1750 Connections The FPGA is attached to lines from the USB microcontroller In order to avoid contention with the bus these lines should be set to high impedance within your design If this is not done FrontPanel may
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9. a momentary switch that will simply drop the signal to ground a direct connection to PROG_B can be made In this case no special consider ations are necessary However if the signal will be driven by a 3 3v CMOS logic signal R11 should be replaced by a 68 0 resistor and a shunt resistor of 2500 should be added at R2 These considerations are necessary because you will be driving 3 3v into an input PROG_B that expects 2 5v R11 is an 0603 resistor on the top side of the board near JP3 By default it is populated with a 0 resistor to connect PROG_B and JP3 4 R2 is an unpopulated 0603 resistor and is located on the bottom side of the board near the JTAG header JP1 It is connected between the 2 5v regulator output and DGND www opalkelly com 11 XEM3005 User s Manual PLL Connections The PLL contains six output clocks The first three are labelled SYS_CLK1 through SYS_CLK3 and are connected to the FPGA The remaining three clocks are labelled SYS_CLK4 through SYS_CLK6 and are connected to expansion connector JP3 The pin mapping table below details the PLL connections PLL Pin Clock Name LCLK1 SYS_CLK1 FPGA A8 LCLK2 SYS 2 FPGA E9 SDRAM Clock The SDRAM clock pin U9 F2 is connected to SYS_CLK1 which is LCLK1 the Cypress CY22150 PLL U5 7 See the section on SDRAM Connections below for more details on SDRAM clock configurations JTAG 1 JTAG Connector JP1 is the 2mm 6 pin JTAG connector on
10. e XEM3005 on Bank by allowing the user to connect an independent power supply to the VCCO3 pins By default a ferrite bead FB2 has been installed which attaches to the 3 3VDD sup ply If you intend to supply power to VCCO3 you MUST remove this ferrite bead Power can then be supplied through the expansion connector on pins JP4 41 and JP4 42 SPI Configuration PROM SPI _ Booting from PROM In order to boot the XEM3005 from PROM switch JP2 must be at PROM Config This allows the PROM to configure the FPGA from power on If your FPGA design has MUXSEL 0 the design will still be able to communicate with FrontPanel if it is connected to a PC Programming the PROM Opal Kelly s FlashLoader sample can be used to program the PROM for untethered booting i e configuring the FPGA on power up without the USB attached This is a simple command line utility to load your bitfile into the PROM The source code is included with this sample to allow you to include PROM programming from your own application The HDL source code is not included but the bitfile may be used along with your application www opalkelly com 15 XEM3005 User s Manual XEM3005 Mechanical Drawing
11. f the XEM3005 This PROM allows the XEM3005 to operate without its USB tether by automatically configuring the on board FPGA during power up This PROM may be programmed using the Opal Kelly FrontPanel Application or through API calls from your own software NOTE This feature is not yet available in FrontPanel Word Wide Synchronous DRAM The XEM optionally includes an SDRAM with a full 16 bit word wide interface to the FPGA Micron MT48LC16M16A2BG 75 D or equivalent This SDRAM is attached exclusively to the FPGA and does not share any pins with the expansion connector The maximum clock rate of the SDRAM is 133 MHz Opal Kelly can provides different variants of the XEM3005 with different SDRAM sizes installed or none installed Please contact us for more information www opalkelly com 7 XEM3005 User s Manual LEDs Four LEDs are available for general use as debug outputs Expansion Connectors Two high density 80 pin expansion connectors are available on the top side of the XEM3005 PCB These expansion connectors provide user access to several power rails on the XEM3005 three clock generator outputs two FPGA clock inputs the USB microcontroller I2C lines the JTAG chain and 101 dedicated I O pins on the FPGA The connectors on the XEM3005 are Samtec BSE 040 01 F D A The table below lists the ap propriate Samtec mating connectors along with the total mated height Samtec Part Number Mated Height BTE 040 01 F D A 5 00
12. help equalize lengths for certain applications like LVDS pair matching the XEM3005 is not an impedance controlled PCB and was not designed specifi cally for LVDS use is 80 pin high density connector Samtec BSE 040 F D A providing access to FPGA Banks 0 1 and 2 the 3 3v and 1 2v supply rails and the 5v from the USB Pins 77 and 75 are the SCL and SDA pins respectively and connect to the pins the Cypress USB microcontroller as well as the FPGA Pullups are provided on the XEM3005 for these signals Pins 71 69 and 67 connect directly to the CY22150 PLL Using FrontPanel s PLL Configuration Dialog you can configure the clock signal present on these pins JP4 is an 80 pin high density connector BSE 040 F D A providing access to FPGA Banks 0 2 and 3 Pins 72 74 76 and 78 connect directly to the FPGA JTAG pins TDI TMS and re spectively www opalkelly com XEM3005 User s Manual Pins 41 and 42 connect directly to VCCO3 on the FPGA and provide the option of providing an external I O voltage to this bank See the section below on setting the I O voltage Pins 75 and 77 are connected to FPGA GCLK11 and GCLK10 respectively These can provide external clock input to the FPGA Setting Bank 3 I O Voltage The Spartan 3E FPGA allows users to set I O bank voltages in order to support several different I O signalling standards This functionality is supported by th
13. hin an enclosure The XEM3005 has two high density 80 pin connectors on the top side which provide access to many FPGA pins power JTAG and the microcontroller s 12 interface BRK3005 Breakout Board A simple breakout board the BRK3005 is provided as an optional accessory to the XEM3005 This breakout board provides easy access to the high density connectors on the XEM3005 by routing them to lower density 0 1 spaced thru holes The breakout board also provides power to the XEM3005 Typically the user design must provide power so the BRK3005 functions as a convenient bootstrapping board A mechanical drawing of the BRK3005 is also shown at the end of this document www opalkelly com 5 XEM3005 User s Manual Functional Block Diagram SPI SDRAM PROM MT48LC16M16 Host Interface Spartan 3E FPGA Bus XC3S1200E 4FTG2 PLL E E gt C3S 00 56 22150 lt gt 4 LEDs Power Supply The XEM3005 is designed to be flexible low cost integration module In order to reduce cost and better adapt to the end user design the XEM3005 is design without power supply capabil ity and must be externally powered Power must be provided as well regulated 3 3v and 1 2v DC supplies and can be delivered via the expansion connectors or using the 0 1 spaced power header The FPGA VCCAUX supply is provided by a 2 5v regulator from 3 3v supply on the 3005 Expansion Bus Power The USB s 5v supply i
14. m ber of on board peripherals These peripherals are listed below Serial EEPROM A small serial EEPROM is attached to the USB microcontroller the XEM3005 but not directly available to the FPGA The EEPROM is used to store boot code for the microcontroller as well as PLL configuration data a unique non mutable serial number and a device identifier string The PLL configuration data is loaded from EEPROM and used to reconfigure the PLL each time a new configuration file is loaded to the FPGA Therefore stable and active clocks will be pres ent on the FPGA pins as soon as it comes out of configuration The stored PLL configuration may be changed at any time using FrontPanel s PLL Configuration Dialog The EEPROM also stores a device identifier string which may be changed at any time using FrontPanel The string serves only a cosmetic purpose and is used when multiple XEM devices are attached to the same computer so you may select the proper active device Cypress CY22150 PLL A multi output single PLL clock generator provides six clocks three to the FPGA and another three to the expansion connector JP3 The PLL is driven by a 48 MHz signal output from the USB microcontroller The PLL can output clocks up to 150 MHz and is configured through the FrontPanel software interface or the FrontPanel API SPI Serial Configuration PROM A 4 Mbit SPI Serial Configuration PROM ST Microelectronics M25P40 VMNE6TP is included on all variants o
15. mm 0 197 BTE 040 02 F D A 8 00mm 0 315 BTE 040 03 F D A 11 00mm 0 433 BTE 040 04 F D A 16 10mm 0 634 BTE 040 05 F D A 19 10mm 0 752 FrontPanel Support The XEM3005 is fully supported by Opal Kelly s FrontPanel software FrontPanel augments the limited peripheral support with a host of PC based virtual instruments such as LEDs hex displays pushbuttons toggle buttons and so on Essentially this makes your PC a reconfigu rable I O board and adds enormous value to the XEM3005 as an experimentation or prototyping system Programmer s Interface In addition to complete support within FrontPanel the XEM3005 is also fully supported by the FrontPanel programmer s interface a powerful C class library available to Windows Linux programmers allowing you to easily interface your own software to the XEM In addition to the C library wrappers have been written for Java and Python making the API available under those languages as well Java and Python extensions are available under Win dows and Linux Sample wrappers are also provided for Matlab and LabVIEW Complete documentation and several sample programs are installed with FrontPanel 8 www opalkelly com XEM3005 User s Manual Applying the XEM3005 Host Interface There are 24 pins that connect the on board USB microcontroller to the FPGA These pins com prise the host interface on the FPGA and are used for configuration downloads
16. nal an input and synchronizes its logic fabric to it typically us ing a DCM www opalkelly com 13 XEM3005 User s Manual System Synchronous from JP3 Insert R28 Remove R29 JP3 drives DRAM_CLK In this mode the clock signal is sourced at the system level by the user design on JP3 The same clock is fanned out to both the FPGA pin A9 GCLK7 and the SDRAM CLK The FPGA therefore considers this signal an input and synchronizes its logic fabric to it typically us ing DCM Source Synchronous Insert R28 Remove R29 FPGA drives DRAM_CLK In this mode the clock signal is sourced by the FPGA along with address and data signals to the SDRAM The FPGA pin A9 GCLK7 is configured as an output and provides the clock signal to the SDRAM Using the DDR buffer capabilities of the Spartan 3E IOBs the outgoing clock edges can be perfectly synchronized with the address and data signals Expansion Connectors 14 JP3 JP4 Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules It provides additional information on pin capabilities pin character istics and PCB routing Additionally Pins provides a tool for generating constraint files for place and route tools Pins can be found at the URL below http www opalkelly com pins Also included in the Pins reference are the lengths of the PCB traces on the XEM3005 Note that while these lengths may be used to
17. s 20070913 20070923 20081004 20090577 2009106 20140220 20070511 Fixed resistor notes 0603 0608 Fixed SDRAM clocking information Contents Introducing the XEM3005 5 nise 5 BRK3005 Breakout Board 5 Functional Block 6 Power SUPPI 6 Expansion Bus 6 USB 2 0 6 6 On board 7 Seral EEPROM 7 Cypress CY22150 SPI Serial Configuration PROM 7 Word Wide Synchronous DRAM 7 WEDS 8 Expansion 8 FrontPanel Support 8 Interface 8 Applying the XEM3005 9 OSH INGH ACE 9 sacs 10 FG COMneChonsS 10 LEDS 11 Reconfiguration Using 11 5 12 SDRAM ClOCK sesati 12 12 JP1 JTAG Connector
18. s provided to the expansion header and power header so that end users can design bus powered applications The USB 2 0 specification allows for up to 2 5 W 500mA at 5v to be provided to external peripherals over the USB cable While power consumption of an unconfigured XEM3005 is quite low due to the flexibility allowed in FPGA design the Spartan 3E and SDRAM could easily consume over 2 5 W during operation with a user design thus violating the USB specification Before relying on USB power you should be aware of the limitations and the fact that using USB power may render the XEM3005 a USB noncompliant device USB 2 0 Interface The XEM3005 uses a Cypress CY7C68013A FX2LP USB microcontroller to make the XEM a USB 2 0 peripheral As a USB peripheral the XEM is instantly recognized as a plug and play peripheral on millions of PCs More importantly FRGA downloads to the XEM happen blazingly fast virtual instruments under FrontPanel update quickly and data transfers are much faster than the parallel port interfaces common on many FPGA experimentation boards Capabilities Depending on the FPGA device inserted on the XEM3005 the I O pin counts will vary The table below indicates the number of I O counts for each device 6 www opalkelly com XEM3005 User s Manual 003 s o Porat 1010 On board Peripherals The XEM3005 is designed to compactly support a large number of applications with a small nu
19. timeout or hang when trying to communicate with the XEM3005 particu larly when programming the on board PLL www opalkelly com LEDs XEM3005 User s Manual The following lines in your UCF contraints file will attach pull ups to the lines i2c_scl LO NET i2c_sda LO 616 PULLUP 615 PULLUP In addition you will need to these signals to high impedance in your HDL Here is exam ple of how to do this in Verilog assign i2c_sd a 1 bz assign i2c_scl 1 bz There are four LEDs on the XEM3005 Each is wired directly to the FPGA according to the map ping in the table below The LED anodes are connected to a pull up resistor to 3 3VDD and the cathodes wired directly to the FPGA To turn ON an LED the FPGA pin should be brought low To turn OFF an LED the FPGA pin should be brought high Reconfiguration Using PROG_B Please reference Xilinx Application Note XAPP453 for more information regarding the use of PROG to force PROM based reconfiguration Asserting the PROG signal driving it low to the FPGA forces the FPGA to restart its configu ration process The XEM3005 controls this signal for USB based configuration but the signal is also available for user control with respect to PROM based configuration PROG resides on the VCCAUX 2 5v power on the Spartan 3E If you plan to control PROG externally with an open drain circuit or
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