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TMS320LF/LC240xA DSP Controllers System and Peripherals RG

1. 1 Note Re enabling interrupts Interrupts must not be re enabled until the PIVR has been read otherwise it s contents can get overwritten by a subsequent interrupt LLLLLLL System Configuration and Interrupts 2 21 2 22 This page is intentionally left blank Interrupt Operation Sequence oje vudIA3 4e1si6e1 e 09udued Hd YSI 9uioeds YSIS HSI jeueb HSID ajgeus jdnuejuj Jl paoui aq jim sidnuejur enini 40 ms Aq paea eq or seu yq siu Beyydnueju 4l 910N Ha WLNI 4289 49jsiBaj eeudued u Ug 41 189 0 dnuejui eyeudued ay eorues 0 epoo Jasn YSIS MO 4 YSIS YSIS 01 uoueJq Ald uo peseg J0 29A ujojueud JO BOIS 1dnueju 40199 uojueud Ald ONJEA Ald 40 HAld speai 1xejuoo So es opoo Jes HSI9 0l MOJA HSIO iis peJ amp e o 8q 0 WLNI speme 21B0 jdnueju u9000 0000 SSOJppe 10 99A XINI 01 sduinf 9d JOS S JN LNI po4eoj SIUG HII oBpajmouyoe jdnuaju senssi pue XINI au soziuBooa1 NdI M0l4 Nd Ndo 0 penssi Ja H41 94 jo 129 9 SJEMIJOS JO jes eq 0 Xq HNI speme 9160 uomeJeue 1dnueiu jes S 4q Hl anijoedsay X NI Buipued 1xeN YAld OU enjeA Ald peo 9160 Sid X NI Buipued sajqeue osje 9160 Jld uDHld Ald ul jsonbau jdnuejul Sje9 o oDpajmouyoe MOl4 Ald 1dnuejut ido MWS 4q 18s 3l JejsiBeJ eeudu
2. EIER 2 9 CPU Interrupt Registers lt rS E 2 10 Peripheral Interrupt Registers lt lt lt lt lt lt c lt lt 44s PANI RSA augauonauudnonochgonnunonannnanacocacnonandgooonananocur 2 12 legal Address Detect coo uen 2 13 External Interrupt Control Registers uuse 2 1 Architecture Summary 2 1 Architecture Summary The 240xA devices are implemented as ASIC customizable digital signal processors cDSPs In the CPU program ROM FLASH is implemented as ASIC hard macros as shown in the shaded blocks in Figure 2 1 The CPU uses the LP256 hard macro which consists of the TMS320C2xx DSP CPU core 544 x 16 words of dual access RAM DARAM the analysis JTAG logic the internal memory interface and the logic interface The logic interface however is not used in the 240xA The peripherals interface to the internal memory interface of the CPU through the PBUS interface All on chip peripherals are accessed through the peripheral bus PBUS At lower frequencies all peripheral accesses reads and writes are zero wait state single cycle accesses All peripherals excluding the watchdog timer counter are clocked by the CPU clock A third ASIC module is the 10 bit A D converter These devices have up to 41 bit selectable digital I O ports Most or all of these I O ports are multiplexed with other functions such as event manager signals serial communication port signals or
3. 0000 Event Manager B EVB Interrupts 044 Conditions for Interrupt Generation 00 Tables Addresses of ADC Registers cece eee n Comparison of Single and Cascaded Operating Modes ennan ADC Clock Prescale Factors for CLK 30 MHz ADC Clock Prescale Factors for CLK 2 40 MHz Reference Voltage Bit Selection 0 00 000s Bit Selections for MAX CONV1 for Various Number of Conversions Status Bit Values for SEQ CNTR n CONV nn Bit Values and the ADC Input Channels Selected ADC Conversion Phases vs CLKOUT cycles ACQ Values When ACQ PS 1 2 and 3 Overview of SCI Registers 2 2 4 n Programming the Data Format Using SCICCR 0 00 c cece ee eee eens Asynchronous Baud Register Values for Common SCI Bit Rates SCI CHAR2 0 Bit Values and Character Lengths SW RESET Affected Flags eee e eens Addresses of SPI Registers 0 00 c cece cee ete eee eens SPI Clocking Scheme Selection Guide Character Length Control Bit Values 4 Mailbox Configuration Details 0 000 c eee Event Manager Module and Signal Names for EVA and EVB Register Addresses lt lt lt Mailbox Addresses 000 ee eee CAN Bit Timing Examples for CLKOUT 40 MHz
4. Compare matches Symmetric Waveform Generation A symmetric waveform Figure 6 11 is generated when the GP timer is in continuous up down counting modes When the GP timer is in this mode the state of the output of the waveform generator is determined by the following zero before the counting operation starts LJ Remains unchanged until first compare match General Purpose GP Timers Toggles on the first compare match Remains unchanged until the second compare match Toggles on the second compare match Remains unchanged until the end of the period U LD U O O Resets to zero at the end of the period if there is no second compare match and the new compare value for the following period is not zero The output is set to one at the beginning of a period and remains one until the second compare match if the compare value is zero at the beginning of a period After the first transition the output remains one until the end of the period if the compare value is zero for the second half of the period When this happens the output does not reset to zero if the new compare value for the following period is still zero This is done again to assure the generation of PWM pulses of 0 to 100 duty cycle without any glitches The first transition does not happen if the compare value is greater than or equal to that of the period register for the first half of the period However the output still toggles when a compare match happens
5. DARAM B0 256 words CNF 1 FEFF 32K on chip Flash memory FFOO Note External if MP MC 1 DARAM B0 CNF 1 FFFF Note When boot ROM is enabled on chip locations 0000 00FFh in program memory is mapped to the bootloader Boot ROM and Flash Memory share the same starting address and hence are not visible active at the same time If the BOOT EN XF pin 0 during reset the BOOT EN bit in SCSR2 register bit 3 will be set and enable the Boot ROM at 0000 in program space While Boot ROM is enabled the entire Flash memory will be disabled The SCSR2 3 bit should be dis abled 0 to have Flash array enabled instead of Boot ROM See Appendix D for bootloader details 240xA 24x Family Compatibility 13 5 System Features 13 4 System Features This section presents some of the system features that are new to the 240xA devices Understanding these key features will help with system initialization and 24x to 240xA migration 13 4 1 Oscillator and PLL Unlike the 24x device the 240xA devices have a 5 pin PLL with a 3 bit ratio control to provide eight different CPU clock options Table 13 4 describes the pins that are used for the PLL Oscillator module and Table 13 5 lists the oscillator PLL frequency input specification PLL is preceded by an on chip oscillator which can accept a resonator or a crystal The PLL accepts the on chip oscillator or external clock as its input clock Refer to TMS320LF2407A TMS320LF2406A T
6. Peripheral 00 Off On On On On interrupts XINT1 2 Reset PDPINTA B Wakeup interrupts 01 Off Off On On On XINT1 2 Reset PDPINTA B 1X Off Off Off Off Off Reset PDPINTA B 4 4 2 Wake Up From Low Power Modes 4 4 2 1 Reset A wake up from a low power mode can occur for several reasons The sections that follow describe how the device exits low power modes A reset from any source causes the device to exit any of the IDLE modes If the device is halted the reset initially starts the oscillator however initiation of the CPU reset sequence may be delayed while the oscillator powers up before clocks are generated 4 4 2 2 External interrupts The external interrupts XINTx can cause the device to exit any of the low power modes except HALT If the device is in IDLE2 mode the synchronous logic connected to the external interrupt pins is bypassed with combinatorial logic that recognizes the interrupt on the pin starts the clocks and then allows the clocked logic to generate an interrupt request to the PIE controller 4 4 2 8 Wake Up Interrupts Some peripherals have the capability to start the device clocks and then generate an interrupt in response to certain external events such as activity on a communication line As an example the CAN wake up interrupt can assert the CAN error interrupt request even when there are no clocks running Clocks and Low Power Modes 4 9 Low Power Modes 4 42 4 Exiting Low Power Modes
7. SEQ SEQ SEQ SEQ Seve CNTR 3 CNTR 2 CNTR 1 CNTR 0 R x R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 State2 State1 Stated State3 State2 State1 Stated R x R 0 R 0 R 0 R 0 R 0 R 0 R 0 Note R Read access x undefined 0 value after reset Bits 15 12 Reserved Bits 11 8 SEQ CNTR 3 SEQ CNTR 0 Sequencing counter status bits The SEQ CNTR n 4 bit status field is used by SEQ1 SEQ2 and the cascaded sequencer Analog to Digital Converter ADC 7 33 Register Bit Descriptions SEQ2 is irrelevant in cascaded mode At the start of an autosequenced session SEQ CNTR n is loaded with the value from MAX CONVn The SEQ CNTR n bits can be read at any time during the countdown process to check status of the sequencer This value together with the SEQ1 and SEQ2 Busy bits uniquely identifies the progress or state of the active sequencer at any point in time Table 7 7 Status Bit Values for SEQ CNTH n Bit 7 Bits 6 4 Bits 3 0 SEQ CNTR Number of conversions remaining read only 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 Reserved SEQ2 State2 SEQ2 State0 Reflects the state of SEQ2 sequencer at any point of time If necessary you can poll these bits to read interim results before an EOS SEQ2 is irrelevant in cascaded mode SEQ1 State3 SEG1 State0 Reflects the state of SEQ1 sequencer at any point of time If need be user can pol
8. i Index 9 Index generating executable files figure generating wait states with the 2407A wait state generator global data memory glossary GP timer control register A GPTCONA GP timer control register B GPTCONB GP timer reset GPIO general purpose input output differences in GPIO implementation in the 240xA GSR global status register 10 32 hardware table of hardware features of the 240xA devices 1 7 highlights 240xA O mux control registers I O mux control register B MCRB 5 5 VO space address map for 2407A I O spaces overview IDE CAN data frame identifier CAN data frame message filtering message priority identifiers message message control field MSGCTRLn message identifier for high word mailboxes 0 5 MSGIDnH message identifier for low word mailboxes 0 5 MSGIDnL idle line mode steps SCI serial communications interface idle line multiprocessor communication format SCI serial communications interface idle line multiprocessor mode SCI serial communications interface IFR 2 26 tp 2 42 illegal address detect IMR 2 28 tp 2 42 Index 10 initialization SPI serial peripheral interface initialization upon reset using the SPI SW RESET bit input output I O differences in GPIO implementation in the 240xA digital I O ports register implementation on 240xA devices shared pin configuration table of I O port control registers implementati
9. r IO IN ORIGIN OFFFOh SECTIONS vectors SEERE bss data ODE P TRES RA vvv V PROGRAM MEMORY LENGTH 08000H LENGTH 0800H LENGTH 07600H LENGTH 0100h 32K On chip flash memory 2K SARAM in program space External RAM On chip DARAM if CNF 1 FFOO to FFFF DATA MEMORY LENGTH 60h LENGTH 20h LENGTH 100h LENGTH 100h LENGTH 0800H LENGTH 1000h LENGTH 8000h Block BO On chip DARAM if CNF 0 2K SARAM in data space Peripheral register spac External data RAM LENGTH 0FFFOh LENGTH 0Fh External I O mapped peripherals On chip I O mapped peripherals xf aA T x Memory mapped regs amp reservd address s x s s Program Examples PRR RR RR KR KR KR KKK k k k KKK KK KK KK KK KK KK KK KK KK KK KK ck ck ck kck ck ck kck ck ck kck ck ck k k ck k ck ck ck ck ck ck k k ko File name 240x h n Description 240x register definitions Bit codes for BIT instruction g EKK k k k k k k k k k k k k k k k k k k k k k k k k k ck ck kck kck kck kck ck ck kck kck kck ck ck kck ck ck kck ck ck kck ck ck ck ck k k ck ck ck ck ck ck ko 240x CPU core registers IMR Set IFR set 0006h 0004h r Interrupt Mask Register Interrupt Flag Register System configuration and interrupt registers SCSR1 set SCSR2 set DINR set PIVR set PIRORO set PIROR1 set PIROR2 set PIACKRO set PIACKR1
10. BO Bus Off Status 0 Normal operation 1 There is an abnormal rate of error occurrences on the CAN bus This condition occurs when the transmit error counter TEC has reached the limit of 256 While in bus off status no messages can be received or transmitted This state is only exited by clearing the CCR bit in the Master Control Register MCR or if the Auto Bus On bit in the Master Control Register is set After leaving the bus off state the error counters are cleared EP Error Passive Status 0 The CAN module is not in error passive mode 1 The CAN module is in error passive mode EW Warning Status 0 The values of both error counters are less than 96 1 At least one of the error counters reached the warning level of 96 CAN Controller Module 10 31 Status Registers 10 5 2 Global Status Register GSR Figure 10 19 Global Status Register GSR Address 7107h 15 8 Reserved 7 6 5 4 3 2 1 0 R 0 R 1 R 0 R 0 R 0 Note R Read access value following dash value after reset Bits 15 6 Reserved Bit 5 SMA Suspend Mode Acknowledge 0 The CAN peripheral is not in suspend mode 1 The CAN peripheral has entered suspend mode This bit is set after a latency of 1 clock cycle up to the length of one frame after the SUSPEND signal is activated Bit 4 CCE Change Configuration Enable 0 Write access to the configuration registers is denied 1 The CPU has write access to the configuration registers BCR while the CCR bit
11. CAN Message ID for Mailbox 3 upper 16 bits MBOX 3 RTR and DLC CAN 2 of 8 bytes of Mailbox 3 CAN 2 of 8 bytes of Mailbox 3 CAN 2 of 8 bytes of Mailbox 3 CAN 2 of 8 bytes of Mailbox 3 CAN Message ID for Mailbox 4 lower 16 bits CAN Message ID for Mailbox 4 upper 16 bits MBOX 4 RTR and DLC CAN 2 of 8 bytes of Mailbox 4 CAN 2 of 8 bytes of Mailbox 4 CAN 2 of 8 bytes of Mailbox 4 CAN 2 of 8 bytes of Mailbox 4 CAN Message ID for Mailbox 5 lower 16 bits CAN Message ID for Mailbox 5 upper 16 bits MBOX 5 RTR and DLC CAN 2 of 8 bytes of Mailbox 5 CAN 2 of 8 bytes of Mailbox 5 CAN 2 of 8 bytes of Mailbox 5 CAN 2 of 8 bytes of Mailbox 5 Event Manager A EVA GP Timer Control Register A Timer 1 Counter Register Timer 1 Compare Register Timer 1 Period Register Data Page E4h 228 E4h 228 E4h 228 E4h 228 Page 10 11 10 10 10 11 10 11 10 10 10 11 10 11 10 10 10 11 Summary of Programmable Registers on the 240xA Table B 1 Summary of Programmable Registers on the 240xA Continued Data Memory Address 7404h 7405h 7406h 7407h 7408h 7411h 7413h 7415h 7417h 7418h 7419h 7420h 7422h 7423h 7424h 7425h 7427h 7428h 7429h 742Ch 742Dh 742Eh 742Fh 7430h 7431h 7500h 7501h 7502h 7503h Register Mnemonic T1CON T2CNT T2CMPR T2PR T2CON COMCONA ACTRA DBTCONA CMPR1 CMPR2 CMPR3 CAPCONA CAPFIFOA CAP1FIFO CAP2FIFO CAP3FIFO CAP1FBOT CAP2FBO
12. CAN Notation 21r hed Zden ned ec nre Lr danse ea Mailbox RAM Layout cee cece eee Typical WDKEY Register Power Up Sequence WD Module Control Registers eee eee ee WD Overflow Timeout Selections 24x Compatible Features Peripherals in 240xA DSPs New or Modified Features Peripherals in 240xA DSPs Features of 24x and 240xA DSPs 00s 240xA PLL Pin Names 000 e ee ences Oscillator PLL Frequency Input Specification Peripheral Clock Enable Bits LF2407A Shared Pin Configuration Luuu Contents xxiii Tables B 1 Summary of Programmable Registers on the 240xA B 2 Code Security Module CSM Registers C 1 Common Files For All Example Programs C 2 Program Examples os kv dod n eere esee ce remate doe a n Rer awa dn D E E 1 Clock Speeds at Which Baud Rate Locks 00 ccc eee eens 1 Security Mode Table 2 Code Security Module CSM Registers Xxiv Examples Conversion in Dual Sequencer Mode Using SEQ1 Sequencer Start Stop Operation 0 eee eene MAXCONV Register Bit Programming 0 0c cece eens Calculating the Conversion Time for a Multiple Conversion Sequence With CPS 0 and ACQ SQ iussi one pensions diaper e doi a wld ee ade eee tae Calculating the Conversion Time for a Single Conversion Sequence With GPS tand ACOS TE yerepe inen
13. Index peripheral interrupt request register 2 PIRQR2 peripheral interrupt vector register PIVR port A data and direction control register PADATDIR 5 8 I O pin designation table port B data and direction control register PBDATDIR 5 9 VO pin designation table port C data and direction control register PCDATDIR I O pin designation table port D data and direction control register PDDATDIR I O pin designation table port E data and direction control register PEDATDIR I O pin designation table port F data and direction control register PFDATDIR pin designation table programmable register address summary receive control register RCR 10 22 receiver data buffer register SCIRXBUF receiver data buffer registers SCIRXEMU SCIRXBUF receiver status register SCIRXST bit associations SCI communication control register SCICCR SCI CHAR2 0 bit values and character lengths SCI control register 1 SCICTL1 SW RESET affected flags SCI control register 2 SCICTL2 SCI module registers overview SPI baud rate register SPIBRR SPI configuration control register SPICCR SPI emulation buffer register SPIRXEMU SPI module addresses SPI operation control register SPICTL m a SPI serial data register SPIDAT SPI serial receive buffer register SPIRXBUF SPI serial transmit buffer register SPITXBUF Index 17 Index SPI status register SPISTS C240 SCI vs LF LC240xA SCI summary
14. Register Setup for Compare Unit Operation 6 4 1 The register setup sequence for compare unit operation requires For EVA For EVB Setting up T1PR Setting up T3PR Setting up ACTRA Setting up ACTRB Initializing CMPRx Initializing CMPRx Setting up COMCONA Setting up COMCONB Setting up T1CON Setting up T3CON Compare Units Registers The addresses of registers associated with compare units and associated PWM circuits are shown in Table 6 5 Addresses of EVA Compare Control Registers on page 6 11 and in Table 6 6 Addresses of EVB Compare Control Registers on page 6 12 These registers are discussed in the subsections that follow Compare Control Registers COMCONA and COMCONB The operation of the compare units is controlled by the compare control registers COMCONA and COMCONB The bit definition of COMCONA is summarized in Figure 6 16 and that of COMCONB is summarized in Figure 6 17 COMCONA and COMCONB are readable and writeable Event Manager EV 6 41 Compare Units Figure 6 16 Compare Control Register A COMCONA Address 7411h CENABLE CLD1 CLDO SVENABLE ACTRLD1 ACTRLDO FCOMPOE n RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 PDPINTA PIN 7 0 R 0 Note R Read access W Write access 0 value after reset Bit 15 CENABLE Compare enable 0 Disables compare operation All shadowed registers CMPRx ACTRA become transparent 1 Enables compare operation Bits14 13 CLD1 CLDO Compare register CMPRx reload condition
15. Reserved 0000h Interrupt vectors 003Fh ar Code security passwords 0044h User code in flash memory 7FFFh 8000h External FDFFh FEO0h Reserved ENF 1 Software interrupts External if CNF 0 FEFF FF00 On chi DARAM B0 CNF 1 FFFF External if CNF 0 32K on chip flash MP MC 0 External MP MC 1 3 5 4 Program Memory Configuration Two factors determine the configuration of program memory Software interrupts 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 003Fh CNF bit The CNF bit bit 12 of status register ST1 determines whether DARAM BO is in on chip program space B CNF 0 The 256 words are mapped as external memory B CNF 1 The 256 words of DARAM BO are configured for program use At reset BO is mapped to data space CNF 0 Program Memory O MP MC pin The level on the MP MC pin determines whether program instructions are read from on chip flash ROM or external memory M MP MC 0 The device is configured in microcontroller mode The on chip ROM flash EEPROM is accessible The device fetches the reset vector from on chip memory Accesses to program memory addresses 0000h 7FFFh will be made to on chip memory in the case of 2407A Refer to the respective memory maps for other devices B MP NC 1 The device is configured in microprocessor mode T
16. 0h CAPSFIFO 78h CAPSFIFO 79h 78h i 3F00h CAP5FAIL NEO 79h 3F00h CAP5PASS EQ 6h 6201h 62h END_INT Program Examples Check FIFO values Report CAP3 error CAP4 SISR Peripheral page clear Capture flag Check FIFO values Report CAP4 error CAP5 SISR Peripheral page clear Capture flag Check FIFO values Report CAP5 error Program Examples C 39 Program Examples CAP5PASS LDP 6h SPLK 6200h 62h CLRC INTM RET SISR38 CAP6 SISR LDP GPTCONB gt gt 7h Peripheral page SPLK 0004h EVBIFRC Clear Capture flag LDP 0h BLDD CAP6FIFO 7Ah BLDD CAP6FIFO 7Bh LACL 7Ah Check FIFO values XOR 0h BCND CAP6FAIL NEQ LACL 7Bh XOR 3F00h BCND CAP6PASS EQ CAP6FAIL Report CAP6 error LDP 6h SPLK 6301h 63h B END INT CAP6PASS LDP 6h SPLK 6300h 63h CLERC INTM RET Delay routine CAPDLY MAR ARO Routine to generate delay between modes LAR ARO 0FFFFh CAPDLP2 RPT HOFFh NOP BANZ CAPDLP2 RET PHANTOM RET GISR1 RET GISR2 RET GISR3 RET GISR5 RET GISR6 RET end C 40 Appendix D TMS320F240x 240xA Boot ROM Loader Protocols and Interfacing This appendix describes the boot load sequence and discusses SPI synchronous and SCI asynchronous transfer protocol and data formats Topic Page D19vintrodu ctiongs eee eere ERES D 2 Protocol Definitions o eee nee e eer rere EEA E E EA D 1 Introduction D 1 D 1 1 Introduction
17. 4 Interrupt Name PDPINTA PDPINTB ADCINT XINT1 XINT2 SPIINT RXINT TXINT CANMBINT CANERINT Interrupt Priority and Vectors A centralized interrupt expansion scheme is implemented in order to accommodate the large number of peripheral interrupts with the six maskable interrupts supported by the CPU Table 2 2 provides the interrupt source priority and vectors for the 240xA devices The details of the 240xA interrupt expansion scheme are explained in Chapter 2 Table 2 2 240xA Interrupt Source Priority and Vectors CPU Interrupt Vector RSN 0000h 0026h NMI 0024h CPU Interrupt Vector INT1 0002h INT1 0002h INT1 0002h INT1 0002h INT1 0002h INT1 0002h INT1 0002h INT1 0002h INT1 0002h INT1 0002h Peripheral Interrupt Vector N A N A N A Peripheral Interrupt Vector 0020h 0019h 0004h 0001h 0011h 0005h 0006h 0007h 0040h 0041h Maskable N N N Maskable Y Y Source Peripheral RS Pin Watchdog CPU Nonmaskable interrupt Source Peripheral EVA EVB ADC External interrupt logic External interrupt logic SPI SCI SCI CAN CAN Description Reset from pin watch dog time out Emulator trap Nonmaskable interrupt Description Power drive protection interrupt pin Power drive protection interrupt pin ADC interrupt in high priority mode External interrupt pin in high priority mode External interrupt pin
18. 8 7 7 Transmit Data Buffer Register SCITXBUF Data bits to be transmitted are written to SCITXBUF These bits must be right justified because the leftmost bits are ignored for characters less than eight bits long The transfer of data from this register to the TXSHF transmitter shift register sets the TXRDY flag SCICTL2 7 indicating that SCITXBUF is ready to receive another set of data If bit TX INT ENA SCICTL2 0 is set this data transfer also causes an interrupt Figure 8 19 Transmit Data Buffer Register SCITXBUF Address 7059h 7 6 5 4 3 2 1 0 TXDT7 TXDT6 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDTO RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Serial Communications Interface SCI 8 31 SCI Module Registers 8 7 8 Priority Control Register SCIPRI SCIPRI contains the receiver and transmitter interrupt priority select bits and controls the SCI operation on the XDS emulator during a program suspend event such as hitting a breakpoint Figure 8 20 SCI Priority Control Register SCIPRI Address 705Fh 7 6 5 4 3 2 0 SCITX SCIRX R 0 RW 0 RW 0 RW 0 RW 0 R 0 Note R Read access W Write access 0 value after reset Bit 7 Reserved Reads return zero writes have no effect Bit 6 SCITX PRIORITY SCI transmitter interrupt priority select This bit specifies the priority level of the SCI transmitter interrupts 0 Interrupts are high priority requests 1 Interrupts
19. Frequently Asked Questions Should I incorporate routines to unsecure the device in my application code There is no need to incorporate routines to unsecure the device in your application code Recall that the device comes up as unsecure when you power it up in microcontroller mode without JTAG connector connected with the on chip ROM bootloader disabled Unsecuring is necessary only when you need visibility to ROM Flash on a currently secured device Is CSM applicable to any other memory space No it is applicable only to on chip Flash ROM memory Should the device be unsecure to run application code Yes The device must be unsecure in order to be able to execute code out of on chip Flash ROM memory I don t need code security Can I store code in PWL also This is not advisable Keeping tab of the password may be difficult especially if code changes are possible It is a good practice to define a password section in the project to isolate the PWL from the rest of the code This forces the user code to begin at 44h and precludes the possibility of code starting from 40h This practice is especially advantageous when migrating code from LF240x where code starts at 40h How does the presence of CSM affect flash programming of LF240xA devices Or I successfully programmed the flash once but I am unable to do it again What could be wrong The device must be first unsecured before Clear Erase Program CEP can
20. TRRn Transmission Request Reset for mailbox n TRR bits can only be set by the CPU user and reset by internal logic In case the CPU tries to set a bit while the CAN module tries to clear it the bit is set The TRR bits are set by the user writing a 1 Writing a O has no effect If TRRn is set write access to the corresponding mailboxn is denied A write access will initiate a WDIF interrupt if enabled If TRRn is set and the transmission which was initiated by TRSn is not currently processed the corresponding transmission request will be cancelled If the corresponding message is currently processed this bit is reset in the event of 1 Asuccessful transmission 2 An abort due to a lost arbitration 3 An error condition detected on the CAN bus line If the transmission is successful the status bit TAn is set If the transmission is aborted the corresponding status bit AAn is set In case of an error condition an error status bit is set in the ESR The status of the TRR bits can be read from the TRS bits For example if TRS is set and a transmission is ongoing TRR can only be reset by the actions CAN Controller Module 10 21 CAN Control Registers described above If the TRS bit is reset and the TRR bit is set no effect occurs because the TRR bit will be immediately reset 10 4 3 Receive Control Register RCR The receive control register RCR contains the bits which control the reception of messages and remote fram
21. Yes 40 Shared with other functions PDPINTA PDPINTB XINT1 XINT2 Yes 144 LQFP LF2406A Yes Yes 544 words 2K words 3 3 V Core 3 3 V I O 32K x 16 4K 12K 12K 4K Yes Yes Yes Yes Yes Yes 16 Yes 39 Shared with other functions PDPINTA PDPINTB XINT1 XINT2 No 100 LQFP 2 F243 and LF2407A are not pin compatible 3 240xA ADC is not compatible with 24x ADC 13 4 LF2402A Yes Yes 544 words 512 words 3 3 V Core 3 3 V I O 8K x 16 2x 4K Yes Yes Yes 8 Yes 16 Shared with other functions 1 Dedicated to O 2 Dedicated to l O 5 Dedicated to I O PDPINTA XINT2 No 64 TQFP 24x F243 Yes No 544 words 5 V Core 5 V I O 8K x 16 None EV2 Yes Yes Yes 8 Yes 26 Shared with other functions PDPINT XINT1 XINT2 NMI Yes 144 LQFP 1 See the TMS320LF2407A TMS320LF2406A TMS320LF2403A TMS320LF2402A TMS320LC2406A TMS320LC2404A TMS320LC2402A DSP Controllers Data Sheet vice details SPRS145 for LF Flash and LC ROM de Memory Map 13 3 Memory Map 13 3 1 Program Space Figure 13 1 LF2407A Memory Map for Program Space 0000 Interrupt Vectors Flash Block Details 003F 0000 0040 4K Sector see 0043 0044 1900 OOFF 0100 12K Sector 3FFF 4000 12K Sector 7FFF 8000 6FFF SARAM 7000 2K words 4K Sector Program Data 7FFF 87FF 8800 External off chip FDFF FE00
22. 1 IDE 1 The RECEIVED message had an extended identifier IDE 0 The RECEIVED message had a standard identifier When LAMI 0 IDE 1 The TO BE RECEIVED message must have an ex tended identifier IDE 0 The TO BE RECEIVED message must have a stan dard identifier CAN Controller Module 10 17 Message Objects Bits 14 13 Reserved Bits 12 0 LAMn 28 16 Upper 13 bits of the local acceptance mask 0 Received identifier bit value must match the identifier bit of the re ceive mailbox For example if bit 27 of LAM is zero then bit 27 of the transmitted MSGID and bit 27 of the receive mailbox MSGID must be the same 1 Accept a 0 or a 1 don t care for the corresponding bit of the re ceive identifier Figure 10 10 Local Acceptance Mask Register n 0 1 Low Word LAMn L Addresses 710Ch 710Eh 15 0 RW 0 Note R Read access W Write access value following dash value after reset Bits 15 0 LAMn 15 0 Lower part of the local acceptance mask These bits enable the masking of any identifier bit of an incoming message 0 Received identifier bit value must match the identifier bit of the receive mailbox 1 Accept a 0 or a 1 don t care for the corresponding bit of the receive identifier 10 18 CAN Control Registers 10 4 CAN Control Registers The control register bits allow mailbox functions to be manipulated Each register performs a specific function such as enabling or disabling the m
23. Data bus ADDR bus Reset INT1 2 3 4 Clock 16 16 16 EV control registers and control logic 16 GP timer 3 GP timer 3 SVPWM Full compare 3 units state 16 GP timer 4 Output 7 compare logic Output logic Prescaler T3CON 4 5 T3CON 8 9 10 4 GP timer 4 4 4 T4CON 4 5 Gb T4CON 8 9 10 16 ADC start of conversion T3CMP T3PWM TDIRB TCLKINB CLKOUT PWM7 PWM12 T4CMP T4PWM TCLKINB CLKOUT TDIRB CAPCONB 14 13 2 CAP4 QEP3 CAP5 QEP4 CAP6 Event Manager EV Functional Blocks 6 1 1 Differences Between C240 EV and 240xA EV Ll The single up count and single up down count modes have been re moved from the remaining GP timers Software change The four timer modes are now decoded with TMODE1 0 This decoding is different from the C240 EV TMODE2 is now a reserved bit There is no 32 bit timer mode The GP Timers do not stay at the period register value FFFFh or 0000h when operating in directional up down count mode including QEP mode They now reverse direction when one of these end points is reached A capture 3 event is now able to start the ADC The capture units of a particular EV can now use any timer associated with that EV as a time base The capture interrupt flag gets set when a capture event occurs only if there are one or more capture events stored in the FIFO already The Capture
24. For SPIBRR 3 to 127 CLKOUT SPI Baud Rate SPIBRR 1 9 12 SPI Interrupts For SPIBRR Q 1 or 2 SPI Baud Rate HM where CLKOUT CPU clock frequency of the device SPIBRR Contents of the SPIBRR in the master SPI device To determine what value to load into SPIBRR you must know the device system clock CLKOUT frequency which is device specific and the baud rate at which you will be operating Example 9 2 shows how to determine the maximum baud rate at which a 240xA can communicate Assume that CLKOUT 40 MHz Example 9 2 Maximum Baud Rate Calculation Maximum SPI Baud Rate ELKOUT 40 x109 4 10 x10 bps 9 4 4 SPI Clocking Schemes The CLOCK POLARITY bit SPICCR 6 and the CLOCK PHASE bit SPICTL 3 control four different clocking schemes on the SPICLK pin The CLOCK POLARITY bit selects the active edge either rising or falling of the clock The CLOCK PHASE bit selects a half cycle delay of the clock The four different clocking schemes are as follows Falling Edge Without Delay The SPI transmits data on the falling edge of the SPICLK and receives data on the rising edge of the SPICLK Falling Edge With Delay The SPI transmits data one half cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal Rising Edge Without Delay The SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge o
25. Phantom Interrupt Vector The phantom interrupt vector is an interrupt system integrity feature If the CPU s interrupt acknowledge is asserted but there is no associated peripheral interrupt request asserted the phantom vector is used so that this fault is handled in a controlled manner The phantom interrupt vector is required when for example the CPU executes a software interrupt instruction with an argument corresponding to a peripheral interrupt usually INT1 INT6 Another example is when a peripheral makes an interrupt request but its INTn flag was cleared by software before the CPU acknowledged the request In this case there may be no peripheral interrupt request asserted to the interrupt controller and therefore the controller does not know which peripheral interrupt vector to load into the PIVR In these two situations the phantom interrupt vector is loaded into the PIVR in lieu of a peripheral interrupt vector Interrupt Vectors 2 5 2 Software Hierarchy There are two levels of interrupt service routine hierarchy the general interrupt service routine GISR and the specific interrupt service routine SISR There is one GISR for each maskable prioritized request INT1 INT6 to the CPU which performs all necessary context saves before it fetches the peripheral interrupt vector from the PIVR This vector is used to generate a branch to the SISR There is one SISR for every interrupt request IRQn from a peripheral to the int
26. Some Examples NOTES As outlined in Table 4 1 peripheral interrupts are used to wake up the device from different low power modes The wake up action and the subsequent behavior of the device is dependent upon the following m m m Whether the peripheral interrupt in question has been enabled at the pe ripheral level Whether the IMR n bit corresponding to the peripheral interrupt in question has been enabled The status of the INTM bit in the STO register Following are two examples of low power mode wake up 1 Using XINT1 to wake up from LPMO When XINT1 is used to wake up the device from LPMO two things can happen based on how the XINT1 interrupt is configured If the XINT1 inter rupt is enabled by setting the appropriate bit in the XINT1CR register and setting bit 0 in IMR to 1 and the INTM bit is zero a valid XINT1 signal will first take the device out of LPMO and will also force the device to the ap propriate interrupt vector However if INTM 1 upon an XINT1 interrupt the DSP will wake up and continue executing the instruction following the IDLE instruction Using PDPINTA to wake up from LPM2 HALT Case 1 PDPINTA is enabled at peripheral level the corresponding IMR bit is 1 en abled INTM 0 Upon wake up from HALT code branches to INT1 vec tor Case 2 PDPINTA is enabled at peripheral level the corresponding IMR bit is 1 en abled INTM 1 Upon wake up from HALT co
27. and its logic level is latched into bit 3 of the SCSR2 register If the bit is set to 1 Boot ROM is active At the completion of the reset phase rising edge of RS this pin will be XF output external flag function and the Boot EN function is no longer available through this pin However the Boot EN bit in SCSR2 can be used to control the visibility of the Boot ROM or the Flash array Figure 13 3 Functional Block Diagram for Boot EN XF Feature Boot EN Boot EN XF pin C XF from core RS Program Memory Boot EN Pin Operating Mode Active for the CPU SCSR2 Bit 3 Comment Can be changed later by Functional Boot ROM 0x0000 0x00FF 0 software hit in SCSR2 Functional Flash Array 0x0000 0x7FFF 1 Ganbe Changed Iatenby 13 8 software bit in SCSR2 System Features 13 4 3 2 Fast RD Strobe Operation LF2407 is the only device that supports external memory interface XMIF to expand the internal memory space with the addition of external memory devices The interface offers decode signals for Program Data and I O space LF2407 external memory interface signals have critical timings while interfacing zero wait state memory at higher CPU clock speeds CPU memory reads are single cycle and read enable RD timing is critical to meet the output enable timing for memories that can be interfaced to this device To alleviate the memory read interface timing an additional signal W R is provided to be used as output enable signa
28. ooo tate eu aie ee rn Ende RR ApeCallbratlon a bere Decr Ue meee 7 5 Register Bit Descriptions a a 7 20 7 6 ADC Conversion Clock Cycles eeueeeeeeeee 7 38 7 1 Features 7T 1 Features 7 2 10 bit ADC core with built in Sample and Hold S H Fast conversion time S H Conversion 500 ns Sixteen 16 multiplexed analog inputs ADCINO ADCIN15 Eight in 2402A Autosequencing capability up to 16 autoconversions in a single ses sion Each conversion session can be programmed to select any one of the 16 input channels Two independent 8 state sequencers SEQ1 and SEQ that can be oper ated individually in dual sequencer mode or cascaded into one large 16 state sequencer SEQ in cascaded mode Four Sequencing Control Registers CHSELSEQn that determine the se quence of analog channels that are taken up for conversion in a given se quencing mode Sixteen individually addressable result registers to store the converted values RESULTO RESULT15 Multiple trigger sources for start of conversion SOC sequence m Software Software immediate start using SOC SEQn bit m EVA Event manager A multiple event sources within EVA m EVB Event manager B multiple event sources within EVB m External ADCSOC pin Flexible interrupt control allows interrupt request on every end of se quence EOS or every other EOS Sequencer can operate in start stop mode allowing multiple
29. set PIACKR2 set 70181 70191 TOLC 701Eh 7010h 7011h 7012h 7014h 7015h 7016h ppp System Control amp Status register 1 System Control amp Status register 2 Device Identification Number register Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral External interrupt configuration registers XINTICR XINT2CR set set Digital I O registers 70701 70711 5 5 MCRA set 7090h MCRB set 7092h MCRC set 7094h PADATDIR set 7098h PBDATDIR set 709Ah PCDATDIR set 709Ch PDDATDIR set 709Eh PEDATDIR set 7095h PFDATDIR set 7096h Watchdog WD registers WDCNTR set 7023h WDKEY set 7025h WDCR set 7029h ADC registers ADCTRL1 set 70A0h ADCTRL2 set 70A1h MAXCONV set 70A2h CHSELSEQ1 Set 70A3h CHSELSEQ2 set 70A4h CHSELSEQ3 Set 70A5h n r r 1 r r r 2 r r r 1 r r Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt External interrupt 1 External interrupt 2 Vector register Reguest register 0 Reguest register 1 Reguest register 2 Acknowledge register 0 Acknowledge register 1 Acknowledge register 2 control register control register I O I O Mux Control Mux Control Register A Register B I O Mux Control Register C I O port A Data amp Direction register I O port B Data amp Direction register I O port C Data amp Direction registe
30. 0 reserved 0 Use GPTimer 2 for CAP3 1 Use GPTimer 1 for CAP1 2 0 No ADC start on CAP3 interrupt 01 CAP1 is rising edge detect 10 CAP2 is falling edge detect 11 CAP3 on both edges 00 reserved SPLK 0000000000000111b EVAIMRC 0000 0000 0000 0 111 enable CAP3 CAP2 CAP1 interrupts LDP 6h Write the failure code to begin with SPLK 5101h 51h This will be overwritten if the test passes SPLK 5201h 52h SPLK 5301h 53h LDP 0 SPLK 0000000000001000b IMR Enable INT4 CLRC INTM Enable interrupts globally CALL CAPDLY EVB Capture tes This portion of the code tests the EVB Capture unit It is assumed that the test is failed unless an interrupt is called error code 4 GISR4 verifies the values in CAPFIFO and reports the results PERIPHERAL CODE 6 TEST CODE 1 After successful completion of this test case the value 6100 6200 6300 must be present in 361h 362 363 DM respectively Error code 6101 CAP1 value is incorrect 6201 CAP2 value is incorrect 6301 CAP3 value is incorrect Load EVB TIMERS registers SETC INTM LDP GPTCONB gt gt 7h Peripheral page SPLK 0000000001001001b GPTCONB 0000 0000 O0 1 Enable Compare o ps 00 reserved Program Examples C 35 Program Examples Load Capture registers C 36 SPI SPI SPI LK LK LK SPLK SPI SPLK SPI SPLK SPI SPLK SPLK LDP SPI SPI SPLK CL
31. 0 Disables Capture Unit 3 FIFO stack of Capture Unit 3 retains its contents 1 Enable Capture Unit 3 Reserved Reads return zero writes have no effect CAP3TSEL GP timer selection for Capture Unit 3 0 Selects GP timer 2 1 Selects GP timer 1 CAP12TSEL GP timer selection for Capture Units 1 and 2 0 Selects GP timer 2 1 Selects GP timer 1 CAP3TOADC Capture Unit 3 event starts ADC 0 No action 1 Starts ADC when the CAP3INT flag is set CAP1EDGE Edge detection control for Capture Unit 1 00 No detection 01 Detects rising edge 10 Detects falling edge 11 Detects both edges CAP2EDGE Edge detection control for Capture Unit 2 00 No detection 01 Detects rising edge 10 Detects falling edge 11 Detects both edges Event Manager EV 6 73 Capture Units Bits 3 2 CAP3EDGE Edge detection control for Capture Unit 3 00 No detection 01 Detects rising edge 10 Detects falling edge 11 Detects both edges Bits 1 0 Reserved Reads return zero writes have no effect Capture Control Register B CAPCONB Figure 6 33 Capture Control Register B CAPCONB Address 7520h 15 14 13 11 W 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 R 0 Note R Read access W Write access 0 value after reset Bit 15 CAPRES Capture reset Always reads zero Writing O clears the capture registers 0 Clears all registers of capture units to 0 1 No action Bits 14 13 CAP45EN Capture Units 4 and 5 control 00 Disables Capture Un
32. 05555h WDKEY SPLK HOAAAAh WDKEY LDP Koh endm MAIN CODE starts here text START LDP 0 SPLK 0 60h OUT 60h WSGR Set XMIF to run w no wait states SETC INTM Disable interrupts LDP 00E0h SPLK 0040h SCSR1 Enables clock to the SCI module SPLK 006Fh WDCR Disable WD KICK DOG SCI TRANSMISSION TEST SCI LDP 0E1h SPLK 0003h MCRA LAR AR1 SCIRXBUF Load AR1 with SCI RX BUF address LAR ARO SCITXBUF Load ARO with SCI TX BUF address LARP ARO LDP HKOEOh SPLK 0007h SCICCR 1 stop bit No parity 8 char bits async mode idle line protocol SPLK 0003h SCICTL1 Enable TX RX internal SCICLK Disable RX ERR SLEEP TXWAKE SPLK 0000h SCICTL2 Disable RX amp TX INTs Baud rate prescaler values for 240x devices running 40 MHz C 16 SPLK SPLK SPLK RCV RDY BIT BCND READ CHR LACL XMIT CHAR SAC B en Li d 0000h SCIHBAUD 0081h SCILBAUD 0023h SCICTL1 SCIRXST BIT6 RCV RDY NTC SCIRXBUF ARO RCV RDY Program Examples Baud Rate 38400 81h Relinquish SCI from Reset Test RXRDY bit If RXRDY 0 then repeat loop Write xmit char to TX buffer else wait for nexr character Connect the SCI to the PC s serial port Use any terminal emulation software Choose 1 stop bit No parity Default baud rate is 38400 Set emulation to ANSI Disable flow control Since this code does not use interrupts it can b
33. 1 Clock to module is enabled and running normally 2 4 Configuration Registers V7 1 Note In order to modify read the register contents of any peripheral the clock to that peripheral must be enabled by writing a 1 to the appropriate bit k Bit 1 Reserved Bit 0 ILLADR Illegal Address detect bit If an illegal address has occurred this bit will be set It is up to software to clear this bit following an illegal address detect This bit is cleared by writing a 1 to it and should be cleared as part of the initialization sequence Note An illegal address access will cause an NMI Figure 2 3 System Control and Status Register 2 SCSR2 Adaress 07019h 15 8 RW 0 RW 0 RC 1 RW 0 RW W BOOT RW RW 1 EN pin MP MC pin Note R Read access W Write access C Clear 0 value after reset Bits 15 7 Reserved Writes have no effect reads are undefined Bit 6 Input Qualifier Clocks An input qualifier circuitry qualifies the input signal to the CAP1 6 XINT1 2 ADCSOC and PDPINTA B pins in the 240xA devices The I O functions of these pins do not use the input qualifier circuitry The state of the internal input signal will change only after the pin is held high low for 6 or 12 clock edges This ensures that a glitch smaller than or equal to 5 or 11 CLKOUT cycles wide will not change the internal pin input state The user must hold the pin high low for 6 or 12 cycles to ensure that the device will see the level change
34. 10 12 message control field MSGCTRLn 10 11 11 message identifier for high word ps 0 5 MSGIDnH 10 10 message identifier for low word mailboxes 0 5 MSGIDnL message identifiers message objects CAN data frame structure figure overview of the CAN network overwrite protection control for mailbox n OPCn receive control register RCR receive message lost for mailbox n RMLn receive message pending for mailbox n RMPn register addresses table remote frame handling remote frame pending register for mailbox n RFPn remote frame requests figure 10 16 remote requests receiving sending status registers Index 5 Index suspend mode 10 41 transmission acknowledge for mailbox n TAn 10 20 transmission control register TCR 10 20 transmission request reset for mailbox n TRRn 10 21 transmission request set for mailbox n TRSn CONV conversion time CONVnn bit values and ADC input channels counting operation GP timer compare output in continuous up down counting mode table compare ET in continuous up counting mode table continuous up down counting mode figure continuous up counting mode figure directional up down counting mode figure stop hold mode CPU definition CRC CAN data frame D0 D15 external data bus definition data CAN data frame data frame CAN protocol figure data frame structure CAN protocol figure data frames CAN protocol
35. 12 3 Analog to Digital Converter When compared to the 240 ADC the 240xA ADC has been significantly enhanced As a result code written for the 240 ADC cannot be ported to the 240xA 12 4 Serial Communications Interface Some code changes are required This is code that switches the SCI pins between their SCI functions and their digital I O functions and accesses them in digital I O mode When porting code from a 240 to a 240xA device it must access the relevant bits in the digital I O peripheral instead of the SCIPC2 register The SCI has free and soft emulation modes 12 5 Serial Peripheral Interface This SPI is no longer limited to a maximum transmission rate of CLKOUT 8 in slave mode The maximum transmission rate in both slave mode and master mode is now CLKOUT 4 Some code changes are required This is code that switches the SPI pins between their SPI functions and their digital I O functions and accesses them in digital O mode When code is ported from 240 to 240xA devices it must access the relevant bits in the digital I O peripheral instead of the SCIPC1 and SCIPC2 register When code is ported from a 240 to a 240xA device writes of transmit data to the serial data register SPIDAT must be left justified within a 16 bit register not within an 8 bit register The SPI has free and soft emulation modes 12 6 Watchdog Timer 12 4 When porting code from 240 to 240xA devices all code that uses the RTI peripher
36. 7528h 7529h Register CAPCONB CAPFIFOB CAP4FIFO CAP5FIFO CAP6FIFO CAP4FBOT CAP5FBOT CAP6FBOT Name Capture control register Capture FIFO status register Two level deep capture FIFO stack 4 Two level deep capture FIFO stack 5 Two level deep capture FIFO stack 6 Bottom registers of FIFO stacks allows most recent CAPTURE value to be read Event Manager EV Register Addresses Table 6 9 Addresses of EVA Interrupt Registers Address 742Ch 742Dh 742Eh 742Fh 7430h 7431h Register EVAIMRA EVAIMRB EVAIMRC EVAIFRA EVAIFRB EVAIFRC Name Interrupt mask register A Interrupt mask register B Interrupt mask register C Interrupt flag register A Interrupt flag register B Interrupt flag register C Table 6 10 Addresses of EVB Interrupt Registers Address 752Ch 752Dh 752Eh 752Fh 7530h 7531h Register EVBIMRA EVBIMRB EVBIMRC EVBIFRA EVBIFRB EVBIFRC Name Interrupt mask register A Interrupt mask register B Interrupt mask register C Interrupt flag register A Interrupt flag register B Interrupt flag register C Event Manager EV 6 13 General Purpose GP Timers 6 3 Figure 6 13General Purpose GP Timers There are two general purpose GP timers in each module These timers can be used as independent time bases in applications such as The generation of a sampling period in a control system Lj Providing a time base for the operation of the quadrature encoder pulse QEP circuit GP timer 2
37. 8 16 Register SCIRXST Bit Associations Address 7055h anaana eee eee 8 17 Emulation Data Buffer Register SCIRXEMU Address 7056h I LL I N 5 0 Ao pod dox d jJ oOBNOU LAULA PONTO DE ODNONAVGV I Z JI GZ ODNO9NAOV OAAAAARAARADG I E ado eC d m o A T T e Co LL D Contents xix Figures ooo rub ud i plo C d W l POON ED m CD bo hch hh hae up TOME E ALIM 1er tor eh 9 21 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 10 10 10 11 10 12 10 13 XX Receiver Data Buffer SCIRXBUF Address 7057h 00 cece eed Transmit Data Buffer Register SCITXBUF Address 7059h SCI Priority Control Register SCIPRI Address 705Fh 0c eee ee SPI Module Block Diagram sssssssessssssseellls eee ees SPI Master Slave Connection lt etn e eee n ees SPIGLK Signal Options 2 2s uic eda eee rack UE aed oh OE Pee l SPI SPICLK CLKOUT Characteristic when BRR 1 is Odd BRR gt 3 and CLOCK POLARITY S 1 iiu dais mds boc ed re Foie doa dne koe a don atten Pd n we Hoe dodge 4 Five Bits per Character lt n SPI Module Registers ssssuuesssssessse ented SPI Configuration Control Register SPICCR Address 7040h SPI Operation Control Register SPICTL Address 7041h nn SPI Status Register SPISTS Address 70421 SPI Baud Rate Register
38. ACQ values when ACQ PS 1 2 and 3 calculating the conversion time for a multiple conversion sequence with CPS 0 and ACQ 0 calculating the conversion time for a single conversion sequence with CPS 1 and ACQ 1 conversion phases vs CLKOUT cycles clock domains clock prescaler ADC analog to digital convert er ADC conversion time in 240xA ADC clocks clocks and low power modes flash powering down the flash low power modes clock domains exiting low power modes examples low power modes summary table wake up from low power modes external interrupts reset wake up interrupts phase locked loop Eu ha operation external oscillator loop filter components power and ground connections figure power connections reference resonator crystal resonator crystal oscillator terms applicable to the PLL module pins watchdog timer clock watchdog suspend code migrating code from 24x to 240xA de vices code security Flash ROM code security code security module CSM registers table DOs and DON Ts to protect security logic DON Ts DOs environments that require security unlocking password match flow flowchart Index 4 features functional description LF LC240xA DSP devices programming considerations devices with code security devices without code security security mode table technical definitions codec definition COMCONA and COMCONB compare control regis ters communication format SCI serial communicatio
39. DTPH2 DTPH3 and DTPH3_ from the dead band unit and compare match signals The control bits of ACTRx PDPINTx and RESET The outputs of the Output Logic for the compare units are 1 PWMx x 1 6 for EVA A PWMy y 7 12 for EVB Event Manager EV 6 55 PWM Circuits Associated With Compare Units Figure 6 24 Output Logic Block Diagram x 1 2 or 3 y 1 2 3 4 5 or 6 ACTR 0 1 2 3 or 10 11 DTPHx DTPHx MUX 5o gt 01 gt PWMy djs mt 0 00 COMCON 9 Output logic for PWM mode PWM Waveform Generation With Compare Units and PWM Circuits 6 6 PWM Waveform Generation With Compare Units and PWM Circuits A pulse width modulated PWM signal is a sequence of pulses with changing pulse widths The pulses are spread over a number of fixed length periods so that there is one pulse in each period The fixed period is called the PWM carrier period and its inverse is called the PWM carrier frequency The widths of the PWM pulses are determined or modulated from pulse to pulse according to another sequence of desired values the modulating signal In a motor control system PWM signals are used to control the on and off time of switching power devices that deliver the desired current and energy to the motor windings see Figure 6 27 on page 6 62 The shape and frequency of the phase currents and the amount of energy delivered to the motor windings control the re
40. EVBIFRA EVB interrupt flag register B EVBIFRB EVB interrupt flag register C EVBIFRC EVB interrupt mask register A EVBIMRA EVB interrupt mask register B EVBIMRB EVB interrupt mask register C EVBIMRO 6 100 EVB interrupts table interrupt flag register and corresponding interrupt mask register table interrupt generation interrupt vector exiting low power modes examples GP timer IMR register interrupt mask register masking interrupt mask register IMR pending interrupt flag register IFR power drive protection SPI serial peripheral interface baud rate and clocking schemes Index baud rate determination example of maximum baud rate calculation example of SPI baud rate calculations for SPIBRR 0 1 or 2 example of SPI baud rate calculations for SPIBRR 3 to 127 clocking schemes selection guide SPICLK signal options SPICLK CLKOUT characteristics data format example transmission of bit from SPIRX BUF data transfer example five bits per character initialization upon reset proper SPI initialization using the SPI SW RESET bit SPI interrupt control bits OVERRUN INT ENA bit SPICTL 4 RECEIVER OVERRUN FLAG bit SPISTS 7 SPI INT ENA bit SPICTL 0 SPI INT FLAG bit SPISTS 6 SPI PRIORITY bit SPIPRI 6 wake up from low power modes external interrupts wake up interrupts introduction TMS320 family overview 1 2 TMS320Lx240xA series of devices 1 1 IR instruction register definit
41. Figure 10 15 and Figure 10 16 illustrate BCR2 and BCR1 respectively CAN Controller Module 10 25 CAN Control Registers F7 1 Note To avoid unpredictable behavior BCR1 and BCR2 should never be pro grammed with values not allowed by the CAN protocol specification I The length of a bit on the CAN bus is determined by the parameters time segment 1 TSEG1 and 2 TSEG2 and by the baud rate prescaler value BRP All controllers on the CAN bus must have the same baud rate and bit length At different clock frequencies of the individual controllers the baud rate has to be adjusted by the given parameters In the bit timing logic the conversion of the parameters to the required bit timing is realized Figure 10 15 Bit Configuration Register 2 BCR2 Address 7104h 15 8 Reserved 7 0 RW 0 Note R Read access W Write access value following dash value after reset Bits 15 8 Reserved Bits 7 0 BRP Baud Rate Prescaler Bits 7 to 0 of this field specify the duration of a time quantum TQ in CAN module system clock units The length of one TQ is defined by Ta BRP 1 ns a CLKOUT If BRP BCR2 0 then 1 TQ 1 CPU clock cycle 10 26 CAN Control Registers Figure 10 16 Bit Configuration Register 1 BCH1 Address 7105h 15 11 10 9 8 RW 0 RW 0 7 6 3 2 0 RW 0 RW 0 RW 0 Note R Read access W Write access value following dash value after reset Bits 15 11 Reserved Bit 10
42. IRQ 2 2 CMP5INT Compare 5 interrupt INT2 IRQ 2 3 CMP6INT Compare 6 interrupt INT2 IRQ 2 4 T3PINT Timer 3 period interrupt INT2 IRQ 2 5 T3CINT Timer 3 compare interrupt INT2 IRO 2 6 T3UFINT Timer 3 underflow interrupt INT2 IRQ 2 7 T3OFINT Timer 3 overflow interrupt INT2 IRO 2 8 TAPINT Timer 4 period interrupt INT3 IRQ 2 9 T4CINT Timer 4 compare interrupt INT3 IRQ 2 10 T4UFINT Timer 4 underflow interrupt INT3 IRQ 2 11 T4OFINT Timer 4 overflow interrupt INT3 IRO 2 12 CAPAINT Capture 4 interrupt INT4 IRQ 2 13 CAP5INT Capture 5 interrupt INT4 IRQ 2 14 CAP6INT Capture 6 interrupt INT4 2 10 3 Peripheral Interrupt Acknowledge Registers PIACKRO 1 2 The peripheral interrupt acknowledge registers PIACKRx are memory mapped to enable an easy test of the peripheral interrupt acknowledges There are three of these 16 bit registers and therefore the PIE controller can support up to 48 peripheral interrupts These registers are generally used for test purposes only and are not for user applications PIACKRO is shown in Figure 2 14 PIACKR1 is shown in Figure 2 15 and PIACKR2 is shown in Figure 2 16 Figure 2 14 Peripheral Interrupt Acknowledge Register 0 PIACKRO Address 7014h 15 14 13 12 11 10 9 8 IAKO 15 IAKO 14 IAKO 13 IAKO 12 IAKO 11 IAKO 10 IAKO 9 IAKO 8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7A 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset 2 34 P
43. Six maskable interrupt flags one for each capture unit 6 8 2 Operation of Capture Units After a capture unit is enabled a specified transition on the associated input pin causes the counter value of the selected GP timer to be loaded into the corresponding FIFO stack At the same time if there are already one or more valid capture values stored in the FIFO stack CAPxFIFO bits not equal to zero the corresponding interrupt flag is set If the flag is unmasked a peripheral interrupt request is generated The corresponding status bits in CAPFIFOx are adjusted to reflect the new status of the FIFO stack each time a new counter value is captured in a FIFO stack The latency from the time a transition happens in a capture input to the time the counter value of the selected GP timer is locked is two clock cycles In 240xA devices additional latency due to the input qualifier circuitry must be taken into account All capture unit registers are cleared to zero by a RESET condition Capture Unit Time Base Selection For EVA Capture Unit 3 has a separate time base selection bit from Capture Units 1 and 2 This allows the two GP timers to be used at the same time one for Capture Units 1 and 2 and the other for Capture Unit 3 For EVB Capture Unit 6 has a separate time base selection bit Capture operation does not affect the operation of any GP timer or the compare PWM operations associated with any GP timer Event Manager EV 6 71 Captu
44. Summary of Programmable Registers on the 240xA Continued Data Memory Address 7504h 7505h 7506h 7507h 7508h 7511h 7513h 7515h 7517h 7518h 7519h 7520h 7522h 7523h 7524h 7525h 7527h 7528h 7529h 752Ch 752Dh 752bh 752Fh 7530h 7531h IO FFOFh IO FFFFh Register Mnemonic T3CON T4CNT T4CMPR T4PR T4CON COMCONB ACTRB DBTCONB CMPR4 CMPR5 CMPR6 CAPCONB CAPFIFOB CAP4FIFO CAP5FIFO CAP6FIFO CAP4FBOT CAP5FBOT CAP6FBOT EVBIMRA EVBIMRB EVBIMRC EVBIFRA EVBIFRB EVBIFRC FCMR WSGR Register Name Timer 3 Control Register Timer 4 Counter Register Timer 4 Compare Register Timer 4 Period Register Timer 4 Control Register Compare Control Register B Compare Action Control Register B Dead Band Timer Control Register B Compare Register 4 Compare Register 5 Compare Register 6 Capture Control Register B Capture FIFO Status Register B Two Level Deep Capture FIFO stack 4 Two Level Deep Capture FIFO stack 5 Two Level Deep Capture FIFO stack 6 Bottom Register of Capture FIFO stack 4 Bottom Register of Capture FIFO stack 5 Bottom Register of Capture FIFO stack 6 EVB Interrupt Mask Register A EVB Interrupt Mask Register B EVB Interrupt Mask Register C EVB Interrupt Flag Register A EVB Interrupt Flag Register B EVB Interrupt Flag Register C Flash Control Mode Register Wait State Generator Register Data Page EAh 234 m 2 N 99 A m 2 ze N K 234 234 2
45. TMS320C2x TMS320C2xx and TMS320C5x assembly language tools and the C compiler for the C1x C2x C2xx and C5x de vices The installations for MS DOS OS 2 SunOS and Solaris systems are covered TMS320C 1x C2x C2xx C5x Assembly Language Tools User s Guide lit erature number SPRUO18 describes the assembly language tools as sembler linker and other tools used to develop assembly language code assembler directives macros common object file format and symbolic debugging directives for the C1x C2x C2xx and C5x genera tions of devices TMS320C2x C2xx C5x Optimizing C Compiler User s Guide literature number describes the C2x C2xx C5x C compiler This C compiler accepts ANSI standard C source code and produces TMS320 assembly language source code for the C2x C2xx and C5x generations of devices XDS51x Emulator Installation Guide literature number describes the installation of the XDS510 XDS510PP and XDS510WS emulator controllers The installation of the XDS511 emulator is also described JTAG MPSD Emulation Technical Reference literature number SPDUO79 provides the design requirements of the XDS510 emulator controller discusses JTAG designs based on the IEEE 1149 1 standard and modular port scan device MPSD designs Code Composer Studio User s Guide literature number SPRUS328 ex plains how to use the Code Composer Studio development environ ment to build and debug embedded real t
46. The LF240xA LF240x Digital Signal Processors DSPs include on chip read only memory ROM containing bootloader code This code loads code from an external serial boot device at reset and transfers control to the code loaded from the external device This chapter describes working with this feature of the device The LF240xA LF240x device Boot ROM offers the user two options it can load code through either asynchronous or synchronous serial transfer The synchronous transfer is done through the serial peripheral interface SPI and the asynchronous transfer is done through the serial communications interface SCI The code is loaded to a user specified location which is completely flexible it can be anywhere in program memory where RAM is available The serial transfer packet must contain the address as specified in the applicable Serial Transfer Format which is described in section D 2 Protocol Definitions on page D 6 Boot Load Sequence There are a few things that must be set up correctly for the control to transfer to the Boot ROM and a valid boot load to occur 1 Microcontroller mode In the case of LF2407A LF2407 the device must be placed in microcontroller mode by pulling the MP MC pin LOW 2 Boot ROM loader invocation The bootloader is invoked by pulling the BOOT EN XF pin low through a resistor prior to device reset This trans fers control to the boot load program located in the on chip ROM At reset time internal lo
47. This bit determines the width of the glitches in number of internal clock cycles that will be blocked Note that the internal clock is not the same as CLKOUT although its frequency is the same as CLKOUT O The input qualifier circuitry blocks glitches up to 5 clock cycles long 1 Theinput qualifier circuitry blocks glitches up to 11 clock cycles long System Configuration and Interrupts 2 5 Configuration Registers 2 6 Bit 5 Bit4 Bit 3 Note This bit is applicable only for the 240xA devices not for the 240x devices since they lack an input qualifier circuitry I Watchdog Override WD protect bit After RESET this bit gives you the ability to protect the WD function from being disabled through software by setting the WDDIS bit 1 in the WDCR This bit is a clear only bit and defaults to a 1 after reset Note this bit is cleared by writing a 1 to it 0 Protects the WD from being disabled by software This bit cannot be set to 1 by software It is a clear only bit cleared by writing a 1 Clearing this bit would enable the WD if it were currently disabled 1 Thisis the default reset value and allows the user to disable the WD through the WDDIS bit in the WDCR Once cleared however this bit can no longer be set to 1 by software thereby protecting the integrity of the WD timer XMIF Hi Z Control This bit controls the state of the exte
48. This reset returns the system to a known starting point Software then clears the WDCNTR register by writing a correct data pattern to the WD key logic A separate internal clocking signal WDCLK is generated by the on chip clock module and is active in all operational modes except the HALT mode WDCLK enables the WD timer to function regardless of the state of any register bit s on the chip except during the HALT low power mode which disables the WDCLK signal The current state of WDCNTR can be read at any time during its operation 11 2 4 1 WD Prescale Select The 8 bit WDCNTR can be clocked directly by the WDCLK signal or through one of six taps from the free running counter The 6 bit free running counter continuously increments at a rate provided by WDCLK The WD functions are enabled as long as WDCLK is provided to the module Any one of the six taps or the direct input from WDCLK can be selected by the WD prescale select bits WDPS2 0 as the input to the time base for the WDCNTR This prescale provides selectable watchdog overflow rates of from 3 28 ms to 209 7 ms for a WDCLK rate of 78125 Hz While the chip is in normal operating mode the free running counter cannot be stopped or reset except by a system reset Clearing WDCNTR does not clear the free running counter 11 2 4 2 Servicing the WD Timer The WDONTR is reset when the proper sequence is written to the WDKEY before the WDCNTR overflows The WDCNTR is reset enabled whe
49. VZ0vc4 1 IdS wnuuuru up uorsssauo9 O sleuueuj O OQV 18 01 Jaw 6opuoreM 49 s1681 XNOOWOO ul pejoejei uid XINIdAd Jo SNIS suid 9OSOQV PU Z LLNIX udvO X LNId ad uo fuunouro sayiyenb jnduj d3O dv9 aandeg INMd dWO exeduio SJeul d9 esodung jejeuec O gA3 pue vA3 g pue y siabeueyy uang goo d eoepelu Kiowa EuJ91X3 p1om 10 91 WOH 1008 WOH USEIJ diy9 u0 10 Aunoes epo paom 10 91 WOH diyo uo Ote Mek AZE Mp s101068 y paom 119 91 usej4 diuo uo Wvavs Wvava p1om 1 91 NYH ZHIN Ot SdIW 9jo uomonuisu 9103 dS XXZ enjeaJ S9DIAAG vxorz JO seinjee4 OJEMPIEH 1 1 ejqe JQEL ui UMOUS aJe saJnjee JI8UJ pue suoneunDijuoo 9149P e qejreAv siuBiuu6iH vxorz SI 1 7 Introduction 240x Highlights AA uid ze AGE 4 L SO VlLOveo1 Dyd Dd uld p9 AGE Ic SBA Vc0veo1 Zd uid 00L NEE g by SO Vv0reo1 Zd uid 00 L AGE S by SOA SOA V90tc21 V LOp2X 1 01 ejqeoidde eq jou Aew suid euiog SODIA9P XOPZ 0 pereduioo MeujueJeylp e1e JEU senje9J sejouep Buipeus JA Od Dvd Zd 39d uld ze uid p9 ud p9 uid 00L Uld pp L Buibexoed NE E NEE NEE NEE NEE eDeyoA Aj ddns Z G G sidnueiju jeuje x3 el IZ IZ lv lv pareys sutd O I 861g SOA SO SO NVO SOA SoA SoA SoA S9A IDS VlOtz41 VeOrcd1 V Orcd1 V90rcd1 VLOPZAI e1njea J ponunuo9 sa2ineg vxorz Jo seinjeo4 asempseH 1 1 ejqe Introduction 1 8 240x High
50. be performed Update the key asm program with the correct passwords Assemble and link the program using key bat Then run unlock batto unsecure the device You should now be able to clear erase program After invoked Code Composer couldn t see my code programmed in flash in the disassembly window see some garbage code instead What could be wrong The device is still in secure mode In order to be able to view your code in the disassembly window the device must first be unsecured Flash ROM Code Security For LF LC240xA DSP Devices E 15 CSM Frequently Asked Questions Can you provide me a simple code to unsecure the device The following code can be executed from BO or SARAM text LDP 00EOh E0 224 E0 80 7000 SPLK 006Fh 7029h Disable Watchdog LDP ton Dummy read of the PWL BLPD 0040h 60h update high word BLPD 0041h 60h third word BLPD 0042h 60h Second word BLPD 0043h 60h low word LDP 0EFh Writing the password SPLK 00123h 77F0h to the KEY registers SPLK 04567h 77F1h Replace the words shown SPLK 089ABh 77F2h with the appropriate SPLK HOCDEFh 77F3h passwords LOOP B LOOP I forgot the password I programmed in PWL Will I be able to reprogram the flash No Not unless you know which COFF file you used to program the flash It is for this reason you should always store a known value in the PWL during the code development phase Are there any restrictions on deb
51. data memory configuration data address data visibility functional timing global data memory local data memory 3 8 pages data page 0 address map table data page 0 address map table RAM block B2 scratch pad RAM data transfer SPI serial peripheral interface example five bits per character Index 6 DBTCONn dead band timer control registers dead band unit block diagram dead band generation dead band generation examples features inputs and outputs dead band timer control register A DBTCO NA dead band timer control register B DBTCONB digital input output I O differences in GPIO implementation in the 240xA digital I O ports register implementation on 240xA devices shared pin configuration table of I O port control registers implementation digital input output I O ports module digital I O ports register implementation on 240xA devices DINR device identification number register 2 8 DLC CAN data frame DMC systems 1 3 dual access RAM DARAM F 4 emulation suspend GP timer in EOC end of conversion cycle EOF CAN data frame EOS end of sequence flag setting cycle ESR error status register EVAIFRA EVA interrupt flag register A EVAIFRB EVA interrupt flag register B EVAIFRC EVA interrupt flag register C EVAIMRA EVA interrupt mask register A EVAIMRB EVA interrupt mask register B EVAIMRC EVA interrupt mask register C EVBIFRA EVB interrupt flag register A EVBIFRB EVB i
52. error detection flags physical description half or full duplex operation WO pins VO pins 52 master and slave mode operations non return to zero fori rao memory mapped status and control programmable bit rates registers programmable data word length SPI serial data register SPIDAT P rogrammable number of Stop bits SPI serial receive buffer register receive and transmit functions SPIRXBUF separate ig INS TOF TA Ana AA SPI serial transmit buffer register interrupts SPITXBUF separate error interrupts for multiple error SPICLK phase and polarity control ponies static and control logic serial clock internally generated SPI module registers transmitter and receiver operation overview wake up multiprocessor modes register addresses serial peripheral interface SPI 9 1 SPI baud rate register SPIBRR 240xA to 240 family compatibility 12 4 SPI configuration control register block diagram SPICCR C240 SPI vs LF LC240xA SPI character length control bit values interrupts SPI emulation buffer register baud rate and clocking schemes SPIRXEMU baud rate determination SPI example waveforms example of baud rate calculations for CLOCK POLARITY 0 CLOCK SPIBRR 0 1 or2 PHASE 0 example of baud rate calculations for CLOCK POLARITY 0 CLOCK SPIBRR 3 to 127 PHASE 1 example of maximum baud rate CLOCK POLARITY 1 CLOCK calculation PHASE 0 clocking schemes CLOCK POLARITY 1 CLOCK selection guide PHASE 1 SPICLK signal options SPISTE beh
53. figure continuous up down counting mode figure directional up down counting mode figure stop hold mode GP timer reset operation of capture units capture unit setup capture unit time base selection output logic block diagram for PWM mode pins power drive protection interrupt 6 8 programmable dead band unit dead band generation dead band generation examples dead band timer control registers DBTCONn dead band unit block diagram features of dead band units inputs and outputs of dead band unit PWM asymmetric waveform generation with compare units and PWM circuits figure PWM circuits associated with compare units PWM generation capability of EV PWM symmetric waveform generation with compare units and PWM circuits figure PWM symmetric waveforms figure PWM waveform generation with compare units and PWM circuits dead band PWM signal generation Index 8 quadrature encoder pulse QEP circuit decoding decoding example QEP circuit QEP circuit block diagram for EVA QEP circuit block diagram for EVB QEP circuit time base QEP counting operation with GP timer interrupt and associated compare outputs QEP pins register setup for the QEP circuit register addresses register setup for PWM generation registers space vector PWM 3 phase power inverter basic ZI and switching pat terns 6 64 schematic diagram table of switching patterns approximating motor voltage with basic space vectors power inverter sw
54. i e Top address in EEPROM PRR RRR sce ke kc e cec ke AK he he ke e he e K K he e e Se ke ke he he e e he he ke he he ke e che ke che he ke e he he che he ke e che kkk he ke e he k kkk kkk kkk he ke e k ke e i Do two word transfers and have the two words for H DEST ination and LENGTH of code boot loaded PRR RRR kc ke kc K K kk k k kc e k ke k K he K e k k K K he ke e K he e K he e k k he k k he ke e he k k e he ke e k he k k k ke e k k ke k he k e che he e ke k k e k k k k CALL GET WORD SACL DEST SACL GPR1 GPR1 used as dest ptr in TBLW CALL CHECK DEST Decide if BO is to be switched to program space CALL GET WORD SACL LENGTH p RRR RRR k k k k k k k k k RK k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ck ck ck ck ck ck ck KK This segment does all the work to transfer the code to program memory i PRR RRR RRR K KK KERR K k k k K he e k K he k K he ke e K ke K k he ke e KK k k k ke e k KR k k k ke e k k k k k ke e k k ke k he k e he k e ke k k k k k k k MAR ARO LAR ARO LENGTH Load ARO and set ARP ARO SBRK 1 AR length 1 since the loop is executed N times for AR N 1 XFER TO PROG LDP 00EOh DP now points to WDOG SPI SCI CALL reset WD Watchdog reset routine reset WD needs the DP to be OxEO CALL GET WORD get WORD does not care for DP D 14 Protocol Definitions SACL GPRO Store word in GPRO temp storage LACC GPR1 Get current dest ptr in
55. needs two clock cycles because the CAN controller performs a read modify write cycle and therefore inserts one wait state for the CPU Table 10 3 shows the mailbox locations in the RAM Mailbox Addresses Mailboxes MBOXO MBOX1 MBOX2 MBOX3 MBOX4 MBOX5 7200 7208 7210 7218 7220 7228 7201 7209 7211 7219 7221 7229 7202 720A 7212 721A 7222 722A Reserved 7204 720C 7214 721C 7224 722C 7205 720D 7215 721D 7225 722D 7206 720E 7216 Viz 7226 722E 7207 720F 7217 721F 7227 722F Message Objects 10 3 Message Objects CAN allows messages to be sent received and stored by using data frames Figure 10 4 illustrates the structure of the data frames with extended and standard identifiers Figure 10 4 CAN Data Frame Structure Standard Identifier Extended Identifier R rir nic Data Data Data Data E a 11 bit 18 bit 110 Byte 0 Byte 1 wi i Byte 6 Byte 7 R E R C K Standard Identifier R R r DLC Data Data Data Data RlIclo F 11 bit RIE 0 Byte 0 Byte 1 oi ie Byte 6 Byte 7 cik Data frame contains nom SOF Start of Frame signifies the start of frame Identifier m Message priority determines the priority of the message when two or more nodes are contending for the bus m Message filtering determines if a transmitted message will be re ceived by CAN modules RTR Remote Transmission Request bit differentiates a data frame from a remote frame _ SRR Substitute Remote Request bit this bit occu
56. that can be selected One data bit is shifted per SPICLK cycle SPICLK is the baud rate clock output on the SPICLK pin If the SPI is a network slave the module receives a clock on the SPICLK pin from the network master therefore these bits have no effect on the SPICLK signal The frequency of the incoming SPICLK from the master should not exceed CLKOUT 4 In master mode the SPI clock is generated by the SPI and is output on the SPICLK pin The SPI baud rates are determined by the following formula SPI Baud Rate Calculations For SPIBRR 3 to 127 CLKOUT SPI Baud Rate SPIBRR 1 1j J For SPIBRR 0 1 or 2 SPI Baud Rate s where CLKOUT CPU clock frequency of the device SPIBRR Contents of the SPIBRR in the master SPI device 9 24 SPI Module Registers 9 5 5 SPI Emulation Buffer Register SPIRXEMU SPIRXEMU contains the received data Reading SPIRXEMU does not clear the SPI INT FLAG bit SPISTS 6 This is not a real register but a dummy address from which the contents of SPIRXBUF can be read by the emulator without clearing the SPI INT FLAG Figure 9 11 SPI Emulation Buffer Register SPIRXEMU Address 7046h 15 14 13 12 11 10 9 8 ERXB15 ERXB14 ERXB13 ERXB12 ERXB11 ERXB10 ERXB9 ERXB8 R 0 R 0 R 0 R 0 R 0 R 0 0 0 R R 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Note R Read access 0 value after reset Bits 15 0 ERXB15 ERXBO Emulation Buffer Received Data SPIRXEMU functions
57. the message object is marked to be sent TRS bit is set See Figure 10 8 A In case of a matching identifier with the message object configured as a transmit mailbox and the AAM bit not set the message is not received See Figure 10 8 B After finding a matching identifier in a send mailbox no further compare is done In case of a matching identifier with the message object configured as a receive mailbox the message is handled like a data frame and the RMP bit in the receive control register RCR is set The CPU then has to decide how to handle the situation See Figure 10 8 E If the CPU wants to change the data in a message object that is configured as a remote frame mailbox AAM bit set it has to set the mailbox number MBNR Message Objects in the master control register and the CDR in the master control register first The CPU may then perform the access and clear the CDR to tell the CAN module that the access is finished Until the CDR is cleared the transmission of this mailbox is not performed Since the TRS bit is not affected by the CDR a pending transmission is stacked after the CDR is cleared Thus the newest data will be sent In order to change the identifier in the mailbox the message object must be disabled first ME bit in the MDER 0 Sending a Remote Request If the CPU wants to request data from another node it may configure the message object as a receive mailbox only mailboxes 2 and 3 and se
58. value after reset Bits 15 12 Reserved Reads return zero writes have no effect Bits 11 8 DBT3 MSB DBTO LSB Dead band timer period These bits define the pe riod value of the three 4 bit dead band timers Bit 7 EDBT3 Dead band timer 3 enable for pins PWM5 and PWM6 of Compare Unit 3 0 Disable 1 Enable Bit 6 EDBT2 Dead band timer 2 enable for pins PWM3 and PWM4 of Compare Unit 2 0 Disable 1 Enable PWM Circuits Associated With Compare Units Bit 5 EDBT1 Dead band timer 1 enable for pins PWM1 and PWM2 of Compare Unit 1 0 Disable 1 Enable Bits 4 2 DBTPS2 to DBTPSO Dead band timer prescaler 000 x 001 x2 010 x 4 011 x 8 100 x16 101 x 32 110 x32 111 x32 x Device CPU clock frequency Bits 1 0 Reserved Reads return zero writes have no effect Figure 6 22 Dead Band Timer Control Register B DBTCONB Address xx15h 15 12 11 10 9 8 R 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R 0 Note R Read access W Write access 0 value after reset Bits 15 12 Reserved Reads return zero writes have no effect Bits 11 8 DBT3 MSB DBTO LSB Dead band timer period These bits define the pe riod value of the three 4 bit dead band timers Bit 7 EDBT3 Dead band timer 3 enable for pins PWM11 and PWM12 of Compare Unit 6 0 Disable 1 Enable Bit 6 EDBT2 Dead band timer 2 enable for pins PWM9 and PWM10 of Compare Unit 5 0 Disable 1 Enable Event Manager EV
59. 0 A D converter 11 AcLk 7 4 Calibration Calibration In the calibration mode the sequencers are not operational and the ADCINn pins are not connected to the A D converter The signal that gets connected to the A D converter input is determined by BRG ENA Bridge Enable and HI LO VREFHIVREFLO selection bits These two signals connect either VREFLO OF VREFHI or their midpoint to the A D converter input and a single conversion is then done The calibration mode can calculate the zero midpoint or full scale offset errors of the ADC The 2 s complement of the offset error should then be loaded in the CALIBRATION register The 2 s complement operation is applicable for negative errors only From that point on the ADC hardware automatically adds the offset error to the converted value Figure 7 8 CALIBRATION Register Address 70B8h 15 14 13 12 11 10 9 8 mw ow o o o o9 109 7 6 5 4 3 2 1 0 To summarize the CALIBRATION register stores the end result of calibration in the calibration mode In the normal mode of the ADC the value in the CALIBRATION register is automatically added to the output of the ADC before the result is stored in the RESULTn register Analog to Digital Converter ADC 7 19 Register Bit Descriptions 7 5 Register Bit Descriptions 7 5 1 ADC Control Register 1 ADCTRL1 Figure 7 9 ADC Control Register 1 ADCTRL1 Address 70A0h 15 14 13 12 11 10 9 8 RS 0
60. 1 DBO 0 DBO 1 DBO 0 PX Vee toe DBO 0 DBO 1 DBO 0 MSG ID5H Reserved Databyte 0 Databyte 1 DBO 1 Databyte 3 Databyte 2 DBO 0 Databyte 4 Databyte 5 DBO 1 Databyte 7 Databyte 6 DBO 0 Address 7201h 7203h 7205h B 7207h D 7209h 720Dh 720Fh 7229h 722Dh 722Fh Register Databyte MSG IDOL MSG CTRLO Databyte 1 Databyte 0 Databyte 2 Databyte 3 Databyte 5 Databyte 4 Databyte 6 Databyte 7 MSG ID1L MSG CTRL1 Databyte 2 Databyte 3 Databyte 1 Databyte 0 Databyte 6 Databyte 7 Databyte 5 Databyte 4 DBO 1 DBO 0 DBO 1 DBO 0 DX DBO 1 DBO 0 a ee S amp S MSG ID5L MSG CTRL5 Databyte 2 Databyte 3 Databyte 3 Databyte 2 Databyte 6 Databyte 7 Databyte 5 Databyte 4 DBO 1 DBO 0 DBO 1 DBO 0 i pii Address 7200h 7202h 7204h A 7206h C 7208h 720Ah 720Ch 720Eh 7228h 722Ah 722Ch 722Eh The DBO data byte order bit is located in the MCR register and is used to define the order in which the data bytes are stored in the mailbox when received and the order in which the data bytes are transmitted Byte 0 is the first byte in the message and Byte 7 is the last one shown in the CAN message 10 44 Chapter 11 Watchdog WD Timer The watchdog WD timer peripheral monitors software and hardware operations and implements system reset functions upon CPU disrup
61. 1 following reset 0 Disable 1 Enable EVB Interrupt Mask Register B EVBIMRB Figure 6 49 EVB Interrupt Mask Register B EVBIMRB Address 752Dh 15 4 3 2 1 0 gt p T4OFINT T4UFINT T4CINT T4PINT ESEVE ENABLE ENABLE ENABLE ENABLE R 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bits 15 4 Reserved Reads return zero writes have no effect Bit 3 T4OFINT ENABLE 0 Disable 1 Enable Bit 2 TAUFINT ENABLE 0 Disable 1 Enable Bit 1 T4CINT ENABLE 0 Disable 1 Enable Bit 0 T4PINT ENABLE 0 Disable 1 Enable Event Manager EV 6 99 Event Manager EV Interrupts EVB Interrupt Mask Register C EVBIMRC Figure 6 50 EVB Interrupt Mask Register C EVBIMRC Address 752Eh 15 3 2 1 0 A R CAP6INT CAP5INT CAP4INT eserve ENABLE ENABLE ENABLE R 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bits 15 3 Reserved Reads return zero writes have no effect Bit 2 CAP6INT ENABLE 0 Disable 1 Enable Bit 1 CAP5INT ENABLE 0 Disable 1 Enable Bit 0 CAP4INT ENABLE 0 Disable 1 Enable 6 100 Chapter 7 Analog to Digital Converter ADC This chapter describes the analog to digital converter ADC includes a list of features explains the clock prescaler and provides register descriptions Topic Page VS o EE L E erEE TE SIE eh 7 2 T CADG OVerVieW a cereo rd crate r E nies m tele Te eke eee e eh ean 7 4 7 3 ADC Clock Prescaler
62. 1 lower 16 CANMSGID1H set 7209h CAN Message ID for mailbox 1 upper 16 CANMSGCTRL1 Set 720Ah CAN RTR and DLC CANMBX1A set 720Ch CAN 2 of 8 bytes of Mailbox 1 CANMBX1B set 720Dh CAN 2 of 8 bytes of Mailbox 1 CANMBX1C set 720Eh CAN 2 of 8 bytes of Mailbox 1 CANMBX1D set 720Fh CAN 2 of 8 bytes of Mailbox 1 CANMSGID2L set 7210h CAN Message ID for mailbox 2 lower 16 CANMSGID2H set 7211h CAN Message ID for mailbox 2 upper 16 CANMSGCTRL2 Set 7212h CAN RTR and DLC CANMBX2A set 7214h CAN 2 of 8 bytes of Mailbox 2 CANMBX2B set 7215h CAN 2 of 8 bytes of Mailbox 2 CANMBX2C set 7216h CAN 2 of 8 bytes of Mailbox 2 CANMBX2D set 7217h CAN 2 of 8 bytes of Mailbox 2 C 8 bits bits bits bits bits bits CANMSGID3L CANMSGID3H CANM CANM CANM CANM CANM CANM SGCTRL3 BX3A BX3B BX3C BX3D SGID4L CANMSGID4H CANMSGCTRL4 CANMBX4 CANMBX4 CANMBX4 CANMBX4 CANM CANM CANM CANM CANM CANM CANM A B C D SGID5L SGID5H SGCTRL5 BX5A BX5B BX5C BX5D set set set set set set set set set set set set set set set set set set set set set Code security module KEY3 KEY2 KEY1 KEYO set set set set 77F0h 77Fih 77F2h 77F3h Code security module PWL3 PWL2 PWL1 PWLO set set set set 0040h 0041h 0042h 0043h 7
63. 1 on page 8 10 leaves a quiet space be fore the address byte This mode does not have an extra address data bit and is more efficient than the address bit mode for handling blocks that contain more than ten bytes of data The idle line mode should be used for typical non multiprocessor SCI communication The address bit mode section 8 3 2 on page 8 13 adds an extra bit that is an address bit into every byte to distinguish addresses from data This mode is more efficient in handling many small blocks of data because un like the idle mode it does not have to wait between blocks of data Howev Serial Communications Interface SCI 8 9 SCI Multiprocessor Communication er at a high transmit speed the program is not fast enough to avoid a 10 bit idle in the transmission stream Controlling the SCI TX and RX Features Receipt Sequence The multiprocessor mode is software selectable via the ADDR IDLE MODE bit SCICCR 3 Both modes use the TXWAKE flag bit SCICTL1 3 RXWAKE flag bit SCIRXST 1 and the SLEEP flag bit SCICTL1 2 to control the SCI transmitter and receiver features of these modes In both multiprocessor modes the receive sequence is 1 Atthe receipt of an address block the SCI port wakes up and requests an interrupt bit RX BK INT ENA SCICTL2 1 must be enabled to request an interrupt It reads the first frame of the block which contains the destina tion address 2 A software routine is entered through
64. 11 Program Examples File Name SPI Description This program out the SPI If a Di obo xk ok ok ox o PROGRAM as puts gital to analog TO OUTPUT SERIAL DATA THROUGH THE SPI PORT a set of incrementing words DAC that roll over converter is connected to the SPI the DAC outputs a sawtooth waveform The program sends data to the serial DAC by means of the SPI For this example the TLC5618 serial DAC from TI was used through include include 240xA h vector h r Variable Declarations for on chip RAM Blocks bss bss GPR0 1 GPR3 1 General purpose registers MACRO Defi nitions r KICK DOG macro Watchdog reset macro LDP 00E0Oh SPLK 05555h WDKEY SPLK HOAAAAh WDKEY LDP 0h endm MAIN CODE starts here text START LDP 0 SETC INTM Disable interrupts during initialization SPLK 0h GPR3 OUT GPR3 WSGR Set XMIF to run with no wait states LRC SXM Clear Sign Extension Mode LRC OVM Reset Overflow Mode CLRC CNF Config Block BO to Data mem LDP WDCR gt gt 7 SPLK 006Fh WDCR Disable WD KICK DOG LDP HSCSR1 gt gt 7 Set PLL for x4 mode SPLK 40020h SCSR1 Enable clock to SPI module Program Examples f SPI Initialization j SPI INIT LDP SPLK SPLK SPLK LDP SPLK LDP SPLK SPICCR gt gt 7 000Fh SPICCR 0006h SPICTL 0002h SPIBRR MCRB gt gt
65. 12 for ACTRB on a compare event if the compare operation is enabled by COMCONx 15 ACTRA and ACTRB are double buffered The condition on which ACTRA and ACTRB is reloaded is defined by bits in COMCONx ACTRA and ACTRB also contain the SVRDIR D2 D1 and DO bits needed for space vector PWM operation The bit configuration of ACTRA is described in Figure 6 18 and that of ACTRB is described in Figure 6 19 Figure 6 18 Compare Action Control Register A ACTRA Address 7413h 14 13 12 11 15 10 9 8 SVRDIR D ot bo CMP6ACT1 CMP6ACTO CMP5ACT1 CMP5ACTO RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CMP4ACT1 CMP4ACTO CMP3ACT1 CMP3ACTO CMP2ACT1 CMP2ACTO CMP1ACT1 CMP1ACTO RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset 6 44 Compare Units Bit 15 SVRDIR Space vector PWM rotation direction Used only in space vector PWM output generation 0 Positive CCW 1 Negative CW Bits 14 12 D2 DO Basic space vector bits Used only in space vector PWM output gener ation Bits 11 10 CMP6ACT1 0 Action on compare output pin 6 CMP6 00 Forced low 01 Active low 10 Active high 11 Forced high Bits 9 8 CMP5ACT1 0 Action on compare output pin 5 CMP5 00 Forced low 01 Active low 10 Active high 11 Forced high Bits 7 6 CMP4ACT1 0 Action on compare output pin 4 CMP4 00 Forced low 01 Active low 10 Active high 11 Forced high
66. 4 Nominal bit time gt SYNCSEG gt Z SJW SJW PS TSEG1 1 PA TSEG2 1 1TQ A 4 Transmit point Sample point Baud rate is calculated as follows in bits per second CLKOUT 1 Baud Rate Gap 4 1 x Bt Time TQ Bit Time where Bit Time number of TQ per bit Bit Time TSEG1 1 TSEG2 1 1 BRP Baud rate prescaler Note TSEG1 and TSEG2 are the values written by the user in BCR1 register Table 10 4 CAN Bit Timing Examples for CLKOUT 40 MHz Sampling TSEG1 TSEG2 BitTime BRP Point Baud Rate 4 3 10 3 60 1 Mbit s 10 7 20 3 60 500 Kbit s 9 4 16 9 68 8 250 Kbit s 14 8 25 15 64 100 Kbit s 11 6 20 39 65 50 Kbit s CAN Controller Module 10 29 Status Registers 10 5 Status Registers The two status registers are the error status register ESR and the global status register GSR As indicated by their names ESR provides information about any type of error encountered and GSR provides information about all functions of the CAN peripheral Figure 10 18 and Figure 10 19 illustrate the ESR and the GSR respectively 10 5 1 Error Status Register ESR The error status register see Figure 10 18 is used to display errors that occurred during operation Only the first error is stored Subsequent errors do not change the status of the register These registers are cleared by writing a 1 to them except for the SA1 flag which is cleared by any recessive bit on the bu
67. 4 only and the capture units Providing a time base for the operation of the compare units and associated PWM circuits to generate PWM outputs Timer Functional Blocks 6 14 Figure 6 3 shows a block diagram of a GP timer Each GP timer includes Onereadable and writeable RW 16 bit up and up down counter register TxONT x 1 2 3 4 see Figure 6 4 This register stores the current value of the counter and keeps incrementing or decrementing depending on the direction of counting Lj One RW 16 bit timer compare register shadowed TxCMPR x 1 2 3 4 see Figure 6 5 1 One RW 16 bit timer period register shadowed TxPR x 1 2 3 4 see Figure 6 6 j RW 16 bit individual timer control register TXCON x 1 2 3 4 see Figure 6 13 _j Programmable prescaler applicable to both internal and external clock inputs J Control and interrupt logic One GP timer compare output pin TxCMP x 1 2 3 4 Output conditioning logic Another overall control register GPTCONA B specifies the action to be taken by the timers on different timer events and indicates the counting directions of the GP timers GPTCONA B is readable and writeable although writing to the status bits has no effect Note Timer 2 can select the period register of timer 1 as its period register In Figure 6 3 the mux is applicable only when the figure represents timer 2 Timer 4 can select the period register of
68. 5 3 2 O Mux Output Control Register B auaa cece eee eee 5 3 3 I O Mux Output Control Register C eee 5 4 Data and Direction Control Registers lt cece eee eee Event Manager EV cece e eee eee eee Describes the event manager EV module Includes descriptions of the general purpose timer compare units pulse width modulation waveform circuits capture units and quadrature en coder pulse circuits 6 1 Event Manager EV Functional Blocks 0 0 cece eee ees 6 1 1 Differences Between C240 EV and 240xA EV 00000 c eee eee eee 6 12 ENV I mI 6 1 3 Power Drive Protection Interrupt PDPINTx x A o0rB 6 1 4 EV Registers eeren nn EETAS RE ELA partes ode cme dating aie 6 1 5 EVWM lnterrupls sinere re odo a do eed Rede RU den ede 6 2 Event Manager EV Register Addresses cece ee eee e eee 6 3 Figure 6 13General Purpose GP Timers lt 6 3 1 GP Timer Counting Operation 00 eaea eeaeee 6 3 2 GP Timer Compare Operation 2 6 3 8 Timer Control Registers TxCON and GPTCONA B ssss 6 3 4 Generation of PWM Outputs Using the GP Timers 6 3 h GP Timer Reset cssisesus ex RR RR Rer nr a ni a TRE RR cane 6 4 Compare Units ssssssslssssssssss e m rh 6 4 1 Compare Units Registers 4 6 4 2 Compare Unit Interrupts niake a a a A Ea 6 4 3 Compare Unit Reset 2 6 5 PWM Circuits
69. 7 003CH MCRB SPICCR gt gt 7 008Fh SPICCR 16 char bits Enable master mode normal clock and enable talk Set up the SPI to max speed Set up the GPIO pins to function jas SPI pins Relinquish SPI from Reset This section generates the sawtooth by ramping a counter down to zero reloading it every time it under flows j LP XMIT VALUE XMIT RDY PHANTOM GISR1 GISR2 GISR3 GISR4 GISR5 GISR6 LAR LDP SAR LACC ADD XOR LDP SACL LDP BIT BCND LDP LACC BANZ RET RET RET RET RET RET RET ARO 07FEh 0 ARO GPRO GPRO 8000H 07FFH SPITXBUF gt gt 7 SPITXBUF SPISTS gt gt 7 SPISTS BIT6 XMIT RDY NTC SPIRXBUF gt gt 7 SPIRXBUF ARO XMIT VALUE LP II zllllllcllllclll lcl c l l l Load ARO with a count MSB should be one DAC requirement To change the direction of counting to upward Write xmit value to SPI Trasmit Buffer Test SPI INT bit If SPI INT 0 then repeat loop i e wait for the completion of transmission else read SPIRXBUF dummy read to clear SPI INT flag xmit next value if counter is non zero if counter reaches zero repeat loop re loading the counter Program Examples C 13 Program Examples SCI sm File Name Description PROGRAM TO PERFORM A LOOPBACK IN THE SCI MODULE This program is capable of doing
70. 8 6 determine the number of wait states 0 7 that are applied to reads from and writes to off chip I O space At reset the three ISWS bits become 111 setting seven wait states for reads from and writes to off chip I O space Bits 5 3 DSWS Data space wait state bits Bits 5 3 determine the number of wait states 0 7 that are applied to reads from and writes to off chip data space At reset the three DSWS bits become 111 setting seven wait states for reads from and writes to off chip data space Bits 2 0 PSWS Program space wait state bits Bits 2 0 determine the number of wait states 0 7 that are applied to reads from and writes to off chip program space At reset the three PSWS bits become 111 setting seven wait states for reads from and writes to off chip program space Table 3 3 shows how to set the number of wait states you want for each type of off chip memory 3 18 Wait State Generation Table 3 3 Setting the Number of Wait States With the 2407A WSGR Bits o o o olo ISWS Bits 7 0 0 6 DSWS PSWS Vo WS 5 4 3 Data WS 2 1 0 Prog WS 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 2 0 1 0 2 0 1 0 2 3 0 1 1 3 0 1 1 3 4 1 0 0 4 1 0 0 4 5 1 0 1 5 1 0 1 5 6 1 1 0 6 1 1 0 6 7 1 1 1 7 1 1 1 7 In summary while the READY signal remains high the wait state generator inserts from zero to seven wait states to a given memory space depending on the values of PSWS DSWS and ISWS The READY signal may then be driven low to
71. ACC TBLW GPRO GPRO is transferred to PGM MEM pointed to by acc ADD 1 Acc now points to the next location SACL GPR1 Store incremented pointer BANZ XFER TO PROG Repeat for length 1 time y EEK K k k k k k k k k k k k k k k k k k k k k k k k k k k kck kck ck ck ck ck kck ck ck k k ck ck kck ck ck kck k k k k ck ck kck k k k k ck ck ck ck ck ck k k ck ck k k k i Finally the program is loaded in the memory Branch to it and get there i As a last step the Chip Select is de activated PRR RRR RRR ke ce ke K he ke A K he ke e he ke ke K he ke K he e ke he he e e he ke A che he K he ke e che he ke e he ke ke che he ke ce he he ce he ke e he ke ke che he ke he he ke e e ke e CS NOT ACTIVE SETC XF Drive CS XF High POINT B1 LACC DEST Branch to Boot Loader Code BACC i p RRR RRR KR k k k k k RK RK KK RK KK k k k k k k RK k k k k k k k k RK RK k k k k k k RK k k k k k k k k k ck ck k k kc k ck ck ck ck k k ck ck KEK GET WORD i This routine gets a word from the EEPROM and packs it It is returned in the accumulator Exit Conditions F 1 DP is set to B1 on Exit 2 ACC GPRO are destroyed 3 Result returned in ACC i 4 Does not care about DP on enter PRR RRR RRR ke ec ke ke e he ke ke he he ke e he ke ke he he ke e he e ke che he K he ke e che he K he ke A K he ke A he ke AK K he ke e he ke K K he e e he ke e che he ke he he ke e e e e GET WORD LACC 480000H Zero Character CALL XMIT VALUE Transmit ch
72. Associated With Compare Units 2 6 5 1 PWM Generation Capability of Event Manager enaa 6 5 2 Programmable Dead Band Dead Time Unit 022 2 0005 6 5 3 OUIDUTIEOGIC z 3 55 grass ra aE Dent Rs Usar napne en Rire ias 6 6 PWM Waveform Generation With Compare Units and PWM Circuits 6 6 1 Generation of PWM Outputs With Event Manager sss 6 6 2 Register Setup for PWM Generation 2 2 6 6 3 Asymmetric PWM Waveform Generation 00 cece cece eee 6 6 4 Symmetric PWM Waveform Generation 6 6 5 Double Update PWM Mode 00 e eect eee 6 7 Space Vector PWM sss cided dee hav dex Sands lobia Means Der dae edd 6 7 1 3 Phase Power Inverter 0 cece eee k 6 7 2 Space Vector PWM Waveform Generation with Event Manager 6 7 8 Space Vector PWM Boundary Conditions eee eee eee 6 8 Capture UNIS ostai 2i ces uh Mean dae de Maden dg haw Dee be 6 8 41 Capture Unit Features 00 Contents xi Contents Xii 6 8 2 Operation of Capture Units cee eee 6 8 8 Capture Unit Registers 400 DES 6 8 4 Capture Unit FIFO Stacks 0 eee ee 6 85 Capture Interrupt 00 e aii ER i iai 6 9 Quadrature Encoder Pulse QEP Circuit 69 4 QEP PINS sete REP Te RED RR RU RE RO see hen 6 9 2 QEP Circuit Time Base roisse akaa iaaa ia aon s 69 3 Decoding snai sarien anin O a Rents 6 9 4
73. BLDD XOR BCND LACL XOR BCND LDP SPLK LDP SPLK CLRC RET LDP SPLK LDP BLDD BLDD 0038h SISR38 eq HGPTCONA gt gt 7h 0001h EVAIFRC Koh CAP1FIFO 70h CAP1FIFO 71h 70h Koh CAP1FAIL NEO 71h Koh CAP1PASS EQ 6h 5101h 51h END_INT 6h 5100h 51h INTM GPTCONA gt gt 7h 0002h EVAIFRC Koh CAP2FIFO 72h CAP2FIFO 73h 72h 3F00h CAP2FAIL NEQ 73h 3F00h CAP2PASS EQ 6h 5201h 52h END_INT 6h 5200h 52h INTM GPTCONA gt gt 7h 0004h EVAIFRC 0h CAP3FIFO 74h CAP3FIFO 75h CAP6 interrupt CAP1 SISR Peripheral page clear Capture flag Check FIFO values Report CAP1 error CAP2 SISR Peripheral page clear Capture flag Check FIFO values Report CAP2 error CAP3 SISR Peripheral page clear Capture flag CAP3FAIL CAP3PASS SISR36 CAPAFAIL CAPAPASS SISR37 CAP5FAIL LACL XOR BCND LACL XOR BCND LDP SPLK LDP SPLK CLRC RET LDP LDP XOR XOR BCND LACL SPLK BLDD BLDD LACL BCND LDP SPLK LDP SPLK CLRC RET 74h i 0h CAP3FAIL NEO 75h 3F00h CAP3PASS EQ 1 6h 5301h 53h END INT 6h 5300h 53h INTM GPTCONB gt gt 7h 0001h EVBIFRC H 0h CAP4FIFO 76h CAP4FIFO 77h 76h i 0h CAPAFAIL NEO 77h 0h CAP4PASS EQ 6h 6101h 61h END_INT 6h 6100h 61h INTM GPTCONB gt gt 7h 0002h EVBIFRC i
74. Been Selected as l O i e Secondary Function mari aea a iia eee eed PFDATDIR VO Pin Designation Assuming Pins Have Been Selected as I O i e Secondary Function 00 ccc eed Event Manager A PINS 2 iisssscssal n on po ee eee eae em hr eR Rd Event Manager BPG sese tne eq Rer XE akce RU ae ek nave db adus Addresses of EVA Timer Registers sess ee Addresses of EVB Timer Registers lt Addresses of EVA Compare Control Registers cece cece ee eee eee Addresses of EVB Compare Control Registers cece e eens Addresses of EVA Capture Registers 444444 lt lt lt Addresses of EVB Capture Registers 4444444 Addresses of EVA Interrupt Registers lt Pole bod 45d o Qo Iw UI e OO lo ceo XO o0 0 UT d GN c Bid n ce Poem CD a OBONT TODOS SCC Tre 11 1 11 2 11 3 13 1 13 2 13 3 13 4 13 5 13 6 13 7 13 8 o l o Addresses of EVB Interrupt Registers GP Timer Compare Output in Continuous Up Counting Modes GP Timer Compare Output in Continuous Up Down Counting Modes Dead Band Generation Examples ssuu Switching Patterns of a 3 Phase Power Inverter Interrupt Flag Register and Corresponding Interrupt Mask Register Event Manager A EVA Interrupts
75. Bit 3 T2OFINT FLAG GP timer 2 overflow interrupt Read 0 Flag is reset 1 Flag is set Write O No effect 1 Resets flag Bit 2 T2UFINT FLAG GP timer 2 underflow interrupt Read 0 Flag is reset 1 Flagis set Write O No effect 1 Resets flag Bit 1 T2CINT FLAG GP timer 2 compare interrupt Read 0 Flag is reset 1 Flag is set Write O No effect 1 Resets flag Event Manager EV 6 89 Event Manager EV Interrupts Bit 0 T2PINT FLAG GP timer 2 period interrupt Read 0 Flag is reset 1 Flagis set Write 0 No effect 1 Resets flag EVA Interrupt Flag Register C EVAIFRC Figure 6 41 EVA Interrupt Flag Register C EVAIFRC Address 7431h 15 3 2 1 0 CAP3INT CAP2INT CAP1INT ESENE FLAG FLAG FLAG R 0 RW1C 0 RW1C 0 RW1C 0 Note R Read access W1C Write 1 to clear 0 value after reset Bits 15 3 Reserved Reads return zero writes have no effect Bit 2 CAP3INT FLAG Capture 3 interrupt Read 0 Flag is reset 1 Flagis set Write 0 No effect 1 Resets flag Bit 1 CAP2INT FLAG Capture 2 interrupt Read O Flag is reset 1 Flagis set Write 0 No effect 1 Resets flag Bit 0 CAP1INT FLAG Capture 1 interrupt Read O Flagis reset 1 Flagis set Write O No effect 1 Resets flag 6 90 Event Manager EV Interrupts EVA Interrupt Mask Register A EVAIMRA Figure 6 42 EVA Interrupt Mask Register A EVAIMRA Address 742Ch 15 11 10 9 8 ENABLE ENABLE ENABLE R 0 RW 0 RW 0 RW 0 7 6 4 3 2 1 0 ENABLE ENABLE ENAB
76. Bits 15 0 IDL 15 0 The lower part of the extended identifier is stored in these bits 3 Message Control Field Each one of the six mailboxes has its own Message Control Field Figure 10 7 illustrates the layout and default mode of the message control field Figure 10 7 Message Control Field MSGCTRLn 15 5 4 3 0 RW RW Note R Read access W Write access Bits 15 5 Reserved Bit 4 RTR Remote Transmission Request bit 0 Data frame 1 Remote frame CAN Controller Module 10 11 Message Objects Bits 3 0 DLC Data Length Code This value determines how many data bytes are used for transmission This field will be updated by the received data frame i e the DLC value of the data frame received will be copied in this field 0001 1 byte 0010 2bytes 0011 3 bytes 0100 4 bytes 0101 5 bytes 0110 6 bytes 0111 7 bytes 1000 8 bytes 10 3 2 Message Buffers Message storage is implemented by RAM The contents of the storage elements are used to perform the functions of acceptance filtering transmission and interrupt handling The mailbox module provides six mailboxes each consisting of 8 bytes of data 29 identifier bits and several control bits Mailboxes 0 and 1 are for reception mailboxes 2 and 3 are configurable as receive or transmit and mailboxes 4 and 5 are transmit mailboxes Mailboxes 0 and 1 share one acceptance mask while mailboxes 2 and 3 share a different mask Note Unused Message Mail
77. Bits 5 4 CMP3ACT1 0 Action on compare output pin 3 CMP3 00 Forced low 01 Active low 10 Active high 11 Forced high Bits 3 2 CMP2ACT1 0 Action on compare output pin 2 CMP2 00 Forced low 01 Active low 10 Active high 11 Forced high Event Manager EV 6 45 Compare Units Bits 1 0 CMP1ACT1 0 Action on compare output pin 1 CMP1 00 Forced low 01 Active low 10 Active high 11 Forced high Figure 6 19 Compare Action Control Register B ACTRB Address 7513h 15 14 13 12 11 10 9 8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bit 15 SVRDIR Space vector PWM rotation direction Used only in space vector PWM output generation 0 Positive CCW 1 Negative CW Bits 14 12 D2 DO Basic space vector bits Used only in space vector PWM output generation Bits 11 10 CMP12ACT1 0 Action on compare output pin 12 CMP12 00 Forced low 01 Active low 10 Active high 11 Forced high Bits 9 8 CMP11ACT1 0 Action on compare output pin 11 CMP11 00 Forced low 01 Active low 10 Active high 11 Forced high Bits 7 6 CMP10ACT1 0 Action on compare output pin 10 CMP10 00 Forced low 01 Active low 10 Active high 11 Forced high Compare Units Bits 5 4 CMP9ACT1 0 Action on compare output pin 9 CMP9 00 Forced low 01 Active low 10 Active high 11 Forced high Bits 3 2 CMP8ACT1 0 Action on compare output pin 8 CMP8
78. CAI RC r r 10 T2 CMP active hi 01 T1 CMP active lo 0000000000000000b T3CNT zero timer 3 count 0000000000000000b T4CNT zero timer 4 count 0001011101000010b T3CON 000 10 Cont Up z LTI x 128 r r 0 reserved for T3 Tenable select 1 Tenable for Timer 3 00 Internal clk 00 ener 0 1 enable compare 0 use own period register 0001011111000011b T4CON r 1 r TSWT3 1 Use Timer 3 tenable bit SELT3PR 1 Use Timer 3 period register 1111111111111111b T3PR 0011111100000000b T3CMPR 0011111100000000b T4CMPR 0000000000000000b EVBIMRA 0000000000000000b EVBIMRB 7 disable group A B interrupts 0011001001101100b CAPCONB 0 clear capture registers Ol enable Capture 4 5 disable QEP 1 enable Capture 6 0 reserved 0 Use GPTimer 4 for CAP6 1 Use GPTimer 3 for CAP4 5 0 No ADC start on CAP6 interrupt 01 CAP4 is rising edge detect 10 CAP5 is falling edge detect 11 CAP6 on both edges 00 reserved 0000000000000111b EVBIMRC 6h 6101h 61h 6201h 62h 6301h 63h INTM CAPDLY 0000 0000 0000 0 111 enable CAP6 CAP5 CAP4 interrupts Write the failure code to begin with This will be overwritten if the test passes Enable interrupts globally Program Examples Exit routine 0h LDP SPLK 0h IMR Mask all interrupts LACC IFR Read Interrupt flags SACL IFR Clear all interrupt flag
79. Control Registers Mailbox enable bits are defined as follows 0 Disable mailbox 1 Enable mailbox 10 4 2 Transmit Control Register TCR The transmit control register TCR contains bits that control the transmission of messages see Figure 10 12 The control bits to set or reset a transmission request TRS and TRR respectively can be written independently In this way a write access to these registers does not set bits that were reset because of a completed transmission After power up all bits are cleared Figure 10 12 Transmission Control Register TCR Address 7101h 11 15 14 13 12 10 9 8 RC 0 RC 0 RC 0 RC 0 RC 0 RC 0 RC 0 RC 0 7 6 5 4 3 2 1 0 RS 0 RS 0 RS 0 RS 0 RS 0 RS 0 RS 0 RS 0 Note R Read access C Clear S Set only value following dash value after reset Bits 15 12 TAn Transmission Acknowledge for mailbox n If the message in mailbox n was sent successfully bit TAn is set Bits TAn are reset by writing a 1 from the CPU This also clears the interrupt if an interrupt was generated Writing a 0 has no effect If the CPU tries to reset the bit while the CAN tries to set it the bit is set These bits set a mailbox interrupt flag MIFx in the IF register The MIFx bits initiate a mailbox interrupt if enabled that is if the corresponding interrupt mask bit in the IM register is set Bits 11 8 AAn Abort Acknowledge for mailbox n If transmission of the message in mailbox n is aborte
80. ERXB3 ERXB2 ERXB1 ERXBO RXB 7047h SPIRXBUF RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXBO TXB 7048h SPITXBUF TXB7 TXB6 TXB5 TXB4 TXB3 TXB2 TXB1 TXBO SDAT 7049h SPIDAT 15 8 SDAT7 SDAT6 SDAT5 SDAT4 SDAT3 SDAT2 SDAT1 SDATO 704Ah 704Bh 704Ch 704Dh 704Eh SPI SPI SPI 704Fh SPIPRI SUSP SUSP PRIORITY SOFT FREE illegal 9 18 SPI Module Registers 9 5 1 SPI Configuration Control Register SPICCR SPICCR controls the setup of the SPI for operation Figure 9 7 SPI Configuration Control Register SPICCR Address 7040h 7 6 SPI SW CLOCK RESET POLARITY SPI CHARS SPI CHAR2 SPI CHAR1 SPI CHARO RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bit 7 SPI SW RESET SPI Software Reset When changing configuration you should clear this bit before the changes and set this bit before resuming opera tion See Section 9 4 5 1 on page 9 16 0 Initializes the SPI operating flags to the reset condition Specifically the RECEIVER OVERRUN Flag bit SPISTS 7 the SPI INT FLAG bit SPISTS 6 and the TXBUF FULL Flag bit SPISTS 5 are cleared The SPI configuration remains un changed If the module is operating as a master the SPICLK sig nal output returns to its inactive level 1 SPI is ready to transmit or receive the next character When the SPI SW RESET bit is a 0 a character written to the transmitter will not be shifted out when this bit is set
81. EY E RRURE RARE Pa Rn I O Space Address Map for 2407A lsuuusssssssssss n Program Address Data Visibility Functional Timing lt Data Address Data Visibility Functional Timing lt 2407A Wait State Generator Control Register WSGR l O Space Address FFFFh 2407A ccc eect eee eee e eens Reference Resonator Crystal 000s cece nett eee eae Power and Ground Connections essas cece eee teen nn Shared Pin Configuration 2 eens O Mux Control Register A MCRA Address 7090h 00 cece eee O Mux Control Register B MCRB Address 7092h 0 0 c eee eee O Mux Control Register C MCRC Address 7094h 00 cece ees Port A Data and Direction Control Register PADATDIR 000e eee eee Port B Data and Direction Control Register PBDATDIR Port C Data and Direction Control Register PCDATDIR 2 Contents xvii Figures l oo ODO G G I I Qc oo ae Gk Rr a I OONOG A DI Oo x h n nD OD loh ORO I dog Oo2oO I o0ouo PPFPPFP NNNNNN HAA gt 6 26 ooooooooooo CQ CQ Q0 C2 Q CO C2 IO ID IO pU Do xviii Port D Data and Direction Control Register PDDATDIR Port E Data and Direction Control Register PEDATDIR Port F Data and Direction Control Register PFDATDIR Event Manager A EVA Block Diagram III Event Manager B EVB Bl
82. FIFO status bits are now RW Bits 5 0 of CAPFIFO are now unnecessary and are reserved Both locations in the capture FIFO can be read individually not just the top location The QEP logic can only clock GP timer 2 for EVA and GP timer 4 for EVB The three simple compare units have been removed The compare mode of the full compare units has been removed They now only operate in PWM mode The dead band counters have been reduced from 8 bits to 4 bits The dead band prescaler has been increased from 3 bits to 5 bits adding two more prescale values x 16 and x 32 Software change There are now three DBTPSx bits DBTPSO moves to bit 2 of DBTCON DBTPS1 moves to bit 3 and bit 4 becomes DBTPS2 Any register bits associated with the removed functions are now reserved not implemented Most interrupt control logic has been removed from each peripheral Each peripheral now simply has one interrupt request signal and associated en able for each interrupt flag The peripheral interrupt vector table contain ing the peripheral interrupt vectors is now located in the peripheral inter rupt expansion PIE controller Event Manager EV 6 5 Event Manager EV Functional Blocks 6 1 2 EV Pins Software writing a 1 to the interrupt flag which has been identified by the interrupt vector ID is required to clear the flag Reading the interrupt vec tor ID no longer automatically clears the associated flag J PDPINTA B is now enable
83. Figure 10 10 illustrates the LAMn L low word Figure 10 9 Local Acceptance Mask Register n 0 1 High Word LAMn H Addresses 710Bh 710Dh 15 14 13 12 0 LAMI LAMn 28 16 RW 0 RW 0 Note R Read access W Write access value following dash value after reset Bit 15 LAMI Local acceptance mask identifier extension bit 0 The identifier extension bit stored in the mailbox determines which messages are received standard or extended Standard and extended frames can be received In case of an ex tended frame all 29 bits of the identifier are stored in the mailbox and all 29 bits of the global acceptance mask register are used for the filter In case of a standard frame only the first eleven bits bits 12 2 of LAMn H of the identifier and the local acceptance mask are used The AME bit of the MBX must be 1 to receive both stan dard and extended identifiers When LAMI 1 1 The IDE bit of the receive mailbox is a don t care The IDE bit of the receive mailbox is overwritten by the IDE bit of the trans mitted message 2 The filtering criterion must be satisfied in order to receive a mes sage 3 The number of bits to be compared is a function of the value of the IDE bit of the transmitted message When LAMI 0 The IDE bit of the receive mailbox determines the number of bits to be compared NOTE The definition for the IDE bit changes depending on the value of the LAMI bit When LAMI
84. GP Timer 2 compare register C 6 T2PR T2CON COMCONA ACTRA DBTCONA CMPR1 CMPR2 CMPR3 CAPCONA CAPFIFOA CAP1FIFO CAP2FIFO CAP3FIFO CAP1FBOT CAP2FBOT CAP3FBOT EVAIMRA EVAIMRB EVAIMRC EVAIFRA EVAIFRB EVAIFRC Event Manager B GPTCONB T3CNT T3CMPR T3PR T3CON T4CNT T4CMPR T4PR T4CON COMCONB ACTRB DBTCONB CMPR4 CMPR5 CMPR6 CAPCONB CAPFIFOB CAP4FIFO CAP5FIFO set set set set set set set set set set set Set Set Set set set set set set set set set EVB set set set set set set set set set set Set set set set set set set set set 7407h 7408h i 7411h i 7413h H 7415h i 7417h i 7418h H 7419h i 7420h 7422h i 7423h i 7424h 7 7425h i 7427h H 7428h H 7429h i 742Ch i 742Dh H 742Eh i 742Fh i 7430h i 7431h registers 7500h 7501h i 7502h H 7503h i 7504h i 7505h i 7506h H 7507h i 7508h i 7511h J 7513h 7515h i 7517h i 7518h 7519h i 7520h i 7522h i 7523h H 7524h i Program Examples GP Timer 2 period register GP Timer 2 control register Compare control register A Full compare Action control register A Dead band timer control register A Full compare unit compare registerl Full compare unit compare register2 Full compare unit compare register3 Capt
85. GSR CEC CAN IFR CAN IMR LAMO H LAMO L LAM1_H LAM1_L Reserved Overview of the CAN Network Description Mailbox Direction Enable Register bits 7 to 0 Transmission Control Register bits 15 to 0 Receive Control Register bits 15 to 0 Master Control Register bits 13 to 6 1 0 Bit Configuration Register 2 bits 7 to 0 Bit Configuration Register 1 bits 10 to 0 Error Status Register bits 8 to 0 Global Status Register bits 5 to 3 1 0 CAN Error Counter Register bits 15 to 0 Interrupt Flag Register bits 13 to 8 6 to 0 Interrupt Mask Register bits 15 13 to 0 Local Acceptance Mask for MBOXO and 1 bits 31 28 to 16 Local Acceptance Mask for MBOXO and 1 bits 15 to 0 Local Acceptance Mask for MBOX2 and 3 bits 31 28 to 16 Local Acceptance Mask for MBOX2 and 3 bits 15 to 0 Accesses assert the CAADDRx signal from the CAN peripheral which will assert an Illegal Address error All unimplemented register bits are read as zero writes have no effect All register bits are initialized to zero unless other wise stated in the definition CAN Controller Module 10 7 Overview of the CAN Network Table 10 3 Registers MSG IDnL MSG IDnH MSG CTRLn MBXnA MBXnB MBXnC MBXnD The mailboxes are located in one 48 x 16 RAM with 16 bit access and can be written to or read by the CPU user or CAN The CAN write or read access as well as the CPU read access needs one clock cycle The CPU write access
86. IOPB7 Note Due to the absence of XINT1 IOPA2 and TDIRA IOPB6 pins bits 2 and 14 of MCRA must be treated as reserved for 2402A devices 5 3 2 1 O Mux Output Control Register B Figure 5 3 I O Mux Control Register B MCRB Address 7092h 11 10 15 14 13 12 9 8 MCRB 15 MCRB 14 MCRB 13 MCRB 12 MCRB 11 MCRB 10 MCRB 9 MCRB 8 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 0 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 1 RW 1 Note R Read access W Write access 0 value after reset Digital Input Output I O 5 5 VO Mux Control Registers Table 5 3 I O Mux Control Register B MCRB Configuration 5 6 Notes Pin Function Selected Bit Name bit MCBn 1 MCB n 0 Primary Secondary 0 MCRB 0 WR IOPCO 1 MCRB 1 BIO IOPC1 2 MCRB 2 SPISIMO IOPC2 3 MCRB 3 SPISOMI IOPC3 4 MCRB 4 SPICLK IOPC4 5 MCRB 5 SPISTE IOPC5 6 MCRB 6 CANTX IOPC6 7 MCRB 7 CANRX IOPC7 8 MCRB 8 XINT2 ADCSOC IOPDO 9 MCRB 9 EMUO Reserved 10 MCRB 10 EMU1 Reserved 11 MCRB 11 TCK Reserved 12 MCRB 12 TDI Reserved 13 MCRB 13 TDO Reserved 14 MCRB 14 TMS Reserved 15 MCRB 15 TMS2 Reserved 1 Due to the absence of the W R IOPCO BIO IOPC1 and SPISTE IOPCS pins bits 0 1 and 5 of MCRB must be treated as reserved in the 2402A 2 Due to the absence of SPI and CAN modules in 2402A bits 2 3 4 6 and 7 of MCRB should always be written with 0 The corresponding pins work as GPIO pins only Due to the absence of the CAN module and
87. Idle i e waiting for trigger 1 Conversion sequence is in progress Analog to Digital Converter ADC 7 27 Register Bit Descriptions Checking for End of Sequence After a start of sequence SOC is initiated four NOPs need to be executed before polling the SEQ1 or SEQ2 BSY bit Example code ADC LOOPI1 LDP SPLK SPLK NOP NOP NOP NOP CHK EOS1 BIT BCND KADCTRL1 gt gt 7 0100000000000000b ADCTRL2 Reset for SEQ1 0010000000000000b ADCTRL2 SOC for SEQ1 Wait for Busy bit to set ADCTRL2 3 Wait for SEQ1 Busy bit to clear CHK EOS1 TC If TC 1 keep looping A better approach would be to check the INT FLAG SEQn bit for end of sequence This does not require NOPs as the bit should already be cleared prior to starting a sequenced conversion To reiterate the NOPs are required only when polling the SEQn BUSY bit interrupt driven conversions do not have this requirement Bits 11 10 INT ENA SEO1 Interrupt mode enable control for SEQ1 Bit 11 Bit 10 0 0 0 1 1 1 Operation Description Interrupt is Disabled Interrupt Mode 1 Interrupt requested immediately when INT FLAG SEQ1 flag is set Interrupt Mode 2 Interrupt requested only if INT FLAG SEQ flag is already set If cleart INT FLAG SEQ flag is set and INT request is suppressed This mode allows Interrupt requests to be generated for every other EOS Reserved t This means that the last completed sequence is the first
88. Interrupt Mask Register EVBIFRA set 752Fh Group A Interrupt Flag Register EVBIFRB set 7530h Group B Interrupt Flag Register EVBIFRC set 7531h Group C Interrupt Flag Register CAN registers CANMDER set 7100h CAN Mailbox Direction Enable register CANTCR set 7101h CAN Transmission Control register CANRCR set 7102h CAN Recieve Control register CANMCR set 7103h CAN Master Control register CANBCR2 set 7104h CAN Bit Config register 2 CANBCR1 set 7105h CAN Bit Config register 1 CANESR set 7106h CAN Error Status register CANGSR set 7107h CAN Global Status register CANCEC set 7108h CAN Trans and Rcv Err counters CANIFR set 7109h CAN Interrupt Flag Register CANIMR set 710ah CAN Interrupt Mask Register CANLAMOH set 710bh CAN Local Acceptance Mask MBX0 1 CANLAMOL set 710ch CAN Local Acceptance Mask MBX0 1 CANLAM1H set 710dh CAN Local Acceptance Mask MBX2 3 CANLAM1L Set 710eh CAN Local Acceptance Mask MBX2 3 CANMSGIDOL Set 7200h CAN Message ID for mailbox 0 lower 16 CANMSGIDOH set 7201h CAN Message ID for mailbox 0 upper 16 CANMSGCTRLO set 7202h CAN RTR and DLC CANMBXOA set 7204h CAN 2 of 8 bytes of Mailbox 0 CANMBXOB set 7205h CAN 2 of 8 bytes of Mailbox O0 CANMBXOC set 7206h CAN 2 of 8 bytes of Mailbox 0 CANMBXOD set 7207h CAN 2 of 8 bytes of Mailbox O0 CANMSGID1L Set 7208h CAN Message ID for mailbox
89. KICK DOG SPLK 0h GPRO Set wait state generator for OUT GPRO WSGR external address space LDP HOOElh SPLK 00000h MCRA Select IOPAn amp IOPBn as GPIO pins SPLK HOFFOOh MCRB Select IOPCn as GPIO pins SPLK 00000h MCRC Select IOPEn amp IOPFn as GPIO pins SPLK 0h PADATDIR All GPIO pins are programmed SPLK 0h PBDATDIR as inputs SPLK 0h PCDATDIR SPLK 0h PEDATDIR SPLK 0h PFDATDIR MAIN LDP 0 This loop reads the level on LAR ARO 60h the GPIO pins The bit patterns MAR ARO read from the 5 GPIO ports LDP 00E1h is copied in the data memory LACL PADATDIR SACL C 22 Program Examples LACL PBDATDIR SACL Fi LACL PCDATDIR SACL LACL PEDATDIR SACL LACL PFDATDIR SACL B MAIN PHANTOM B PHANTOM Program Examples C 23 Program Examples Program to auto answer a remote frame request in CAN To be used along with REM REQ asm P File name REM ANS asm PROGRAM TO AUTO ANSWER TO A REMOTE FRAME REOUEST IN 24x 240xA CAN To be used along with REM REO asm Reception and transmission by MBX2 Low priority interrupt used Transmit acknowledge for MBX2 is set after running this program and the message is transmitted title REM ANS Title include 240x h Variable and register declaration include vector h Vector table takes care of dummy password global START Cons
90. MCRx n Value at Reset o O O O Oo n o Oo o o o o IOP Data and Direction Register PADATDIR PADATDIR PADATDIR PADATDIR PADATDIR PADATDIR PADATDIR PADATDIR PBDATDIR PBDATDIR PBDATDIR PBDATDIR PBDATDIR PBDATDIR PBDATDIR PBDATDIR PCDATDIR PCDATDIR PCDATDIR PCDATDIR PCDATDIR PCDATDIR PCDATDIR PCDATDIR IOP Data Bit N Oo A IOP Direction Bit 8 9 10 12 13 14 15 10 12 13 14 15 10 12 13 14 15 Digital I O GPIO Pins Table 13 7 LF2407A Shared Pin Configuration Continued Shared Pin Functions IOP Data Mux Mux MCRx n IOP n po Aa a a E ita ton Function 1 Register XINT2 ADCSOC IOPDO MCRB 8 0 PDDATDIR 0 8 EMUO IOPD1 Reserved 9 1 PDDATDIR EMU1 IOPD2 Reserved 10 1 PDDATDIR TCK IOPD3 Reserved 11 1 PDDATDIR TDI IOPD4 Reserved 12 1 PDDATDIR TDO IOPD5 Reserved 13 1 PDDATDIR TMS IOPD6 Reserved 14 1 PDDATDIR TMS2 IOPD7 Reserved 15 1 PDDATDIR CLKOUT IOPEO MCRC 0 1 PEDATDIR 0 8 PWM7 IOPE1 MCRC 1 0 PEDATDIR 1 9 PWM8 IOPE2 MCRC 2 0 PEDATDIR 2 10 PWM9 IOPE3 MCRC 3 0 PEDATDIR 3 11 PWM10 IOPE4 MCRC 4 0 PEDATDIR 4 12 PWM11 IOPE5 MCRC 5 0 PEDATDIR 5 13 PWM12 IOPE6 MCRC 6 0 PEDATDIR 6 14 CAP4 QEP3 IOPE7 MCRC 7 0 PEDATDIR 7 15 CAP5 QEP4 IOPFO MCRC 8 0 PFDATDIR 0 8 CAP6 IOPF1 MCRC 9 0 PFDATDIR 1 9 T3PWM CMP IOPF2 MCRC 10 0 PFDATDIR 2 10 T4PWM CMP IOPF3 MCRC 11 0 PFDATDIR 3 11 TDIRB IOPF4 MCRC 12 0 PFDATDIR 4 12 T
91. ODOh to SPIDAT and waits for the master to shift out the data Master sets the slave SPISTE signal low active Master writes 058h to SPIDAT which starts the transmission procedure First byte is finished and sets the interrupt flags Slave reads OBh from its SPIRXBUF right justified Slave writes 04Ch to SPIDAT and waits for the master to shift out the data Master writes 06Ch to SPIDAT which starts the transmission procedure Master reads 01Ah from the SPIRXBUF right justified Second byte is finished and sets the interrupt flags Master reads 89h and the slave reads 8Dh from their respective SPIRXBUF After the user s software masks off the unused bits the master receives 09h and the slave receives ODh Master clears the slave SPISTE signal high inactive Serial Peripheral Interface SPI 9 17 SPI Module Registers 9 5 SPI Module Registers The SPI is controlled and accessed through registers in the control register file Figure 9 6 lists the SPI control registers and bit numbers Figure 9 6 SPI Module Registers idar Register Bit number Name 15 8 7 6 5 4 3 2 1 0 SPI SW CLOCK SPI SPI SPI SPI 0M SPICCR RESET POLARITY CHAR3 CHAR2 CHAR1 CHARO CLOCK MASTER SPI INT RECEIVER 7042h SPISTS OVERRUN c FLAG SPIBIT SPIBIT SPIBIT SPIBIT SPIBIT SPIBIT SPIBIT Ze SGPIBRIEE BE RATE6 RATES RATE4 RATE3 RATE2 RATE1 RATEO 7046h SPIRXEMU piss ERXB7 ERXB6 ERXB5 ERXB4
92. PIE Level 1 IRQ GEN Level 2 IRQ GEN Level 3 IRQ GEN Level 4 IRQ GEN Level 5 IRQ GEN Level 6 IRQ GEN PIRQR PIACKR PIVR Data Addr bus bus Peripheral Interrupt Expansion PIE Controller 2 4 4 Interrupt Hierarchy The number of interrupt slots available is expanded by having two levels of hierarchy in the interrupt request system Both the interrupt request acknowledge hardware and the interrupt service routine software have two levels of hierarchy 2 4 2 Interrupt Request Structure At the lower level of the hierarchy the peripheral interrupt requests PIRQ from several peripherals to the interrupt controller are ORed together to generate an interrupt request INTn to the CPU This is the core level interrupt request There is an interrupt flag bit and an interrupt enable bit located in the peripheral configuration registers for each event that can cause a PIRQ There is also one PIRQ for each event If an interrupt causing event occurs in a peripheral and the corresponding interrupt enable bit is set the interrupt request from the peripheral to the interrupt controller will be asserted This interrupt request simply reflects the status of the peripheral s interrupt flag gated with the interrupt enable bit When the interrupt flag is cleared the interrupt request is cleared Some peripherals may have the capability to make either a high priority or a low priority in
93. Qualifier Signal Description The 240xA can address the following memory sizes in each of the external memory spaces Ext Memory Space Program space Data space I O space Size in words Qualifier signal strobe 64K PS 64K DS 64K IS The signals that define the XMIF are given in Table 3 2 Table 3 2 XMIF Signal Descriptions Signal s name A 0 15 D 0 15 PS DS is STRB ENA 144 Signal description External 16 bit unidirectional address bus External 16 bit bidirectional data bus Program space strobe Data space strobe I O space strobe External memory access strobe Write strobe Read strobe Read Write qualifier Microprocessor microcontroller selection pin Is active low whenever the external data bus is driving as an output during visibility mode Can be used by external decode logic to prevent data bus contention while running in visibility mode If pulled low the 2407A device behaves like a 2402A 2404A 2406A that is has no external memory and generates an Illegal address if any of the 3 exter nal spaces are accessed This pin has an internal pull down resistor so when left disconnected device behaves appropriately Note These signals allow external memory such as SRAM to be interfaced to the 240xA in the conventional way Figure 3 5 and Figure 3 6 show Visibility mode timing diagrams Memory 3 13 XMIF Qualifier Signal Description Figure 3 5 Program Address Data Visibil
94. ROM code security features lists the code security module CSM regis ters and discusses programming considerations for the TMS320LF LC240xA devices with and without code security E 1 Flash ROM Security Feature 00 ccc cece nn E 1 1 Functional Description 0 0 cece ees E 1 2 CSM Impact on Other On Chip Resources E 1 3 Incorporating Code Security in User Applications 00 205 E2 Technical Definitions iode bad DRE ka de do Aa Weer Rd dona RP PPRU SERE E 3 Environments that Require Security Unlocking sssaaa assan aaa annann E 3 4 Password Match Flow e E 4 Unsecuring Considerations for Devices With Without Code Security E 4 1 Case 1 Device With Code Security 0c eee eee E 4 2 Case 2 Device Without Code Security 0 cece eee ees E5 DOs and DON Ts to Protect Security Logic 2 E 54 DOS iuste dees nd teed eee wet ee the et Ee hie Shee Redi E52 DONIS did daelich abies ie UR do A bd dot ass E6 CSM Features Summary 0 00 eee teens E 7 CSM Frequently Asked Questions 2 F Glossaty eT F 1 Explains terms abbreviations and acronyms used throughout this book Xvi 0 X O Orge e qol ol I D LLL PON Soe qr Tode dodo acp T N D I D I 2 15 D I N l ru adir ab wb d d NOOR OD gt yt En es se NO oP WON HD o DO hh OND Figures 240xA Device Overview k 240xA Device Architec
95. RRR KEK RK KKK KKK KK KK KKK KKK KK KK KKK k k k k k k k k k k k k k k k k k k k k k k kc kc k k k k k k k k k ck ck ck ck ck k k ck k k Table of SCI_LBAUD Contents p EKK k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k H SCI LBAUD 938 4 Kbps SYSCLK 5 CLKIN BAUD TBL word 130 40MHz 10 MHz word 117 36MHz 9 0 MHz word 104 32MHz 8 0 MHz word 97 30MHz 7 5 MHz word 91 28MHz 7 0 MHz word 78 24MHz 6 0 MHz word 65 20MHz 5 0 MHz word 52 16MHz 4 0 MHz end D 20 Appendix E Flash ROM Code Security For LF LC240xA DSP Devices This chapter describes the Flash ROM code security features lists the code security module CSM registers and discusses programming considerations for TMS320LF LC240xA devices with and without code security Topic E 1 Flash ROM Security Feature 0eeeeee eee eee ees E 2 Technical Definitions 7 51 resessie naseem aE sE E 3 Environments that Require Security Unlocking E 4 Unsecuring Considerations for Devices With Without Code Security essers ene nens eer Ee E e MT EE E DOs and DON Ts to Protect Security Logic E 6 CSM Features Summary E 7 CSM Frequently Asked Questions ssss E 1 Flash ROM Security Feature E 1 Flash ROM Security Feature E 1 1 TMS320LF24
96. RW 0 RC 0 RW 0 Note R Read access W Write access S Set only C Clear 0 value after reset Bit 15 EVB SOC SEQ EVB SOC enable for cascaded sequencer Note This bit is active only in cascaded mode 0 No action 1 Setting this bit allows the cascaded sequencer to be started by an Event Manager B signal The Event Manager can be programmed to start a conversion on various events See chapter 6 Event Man ager EV for details Bit 14 RST SEQ1 STRT CAL Reset Sequencer1 Start Calibration Case Calibration Disabled Bit 3 of ADCTRL1 0 Writing a 1 to this bit will reset the sequencer immediately to an initial pretriggered state i e waiting for a trigger at CONVOO A currently active conversion sequence will be aborted 0 No action 1 Immediately reset sequencer to state CONVOO Case Calibration Enabled Bit 3 of ADCTRL1 1 Writing a 1 to this bit will begin the converter calibration process 0 No action 1 Immediately start calibration process Bit 13 Bit 12 Register Bit Descriptions SOC SEQ1 Start of conversion SOC trigger for Sequencer 1 SEQ This bit can be set by the following triggers L SW Software writing a 1 to this bit L EVA Event Manager A EVB Event Manager B only in cascaded mode EXT External pin i e the ADCSOC pin When a trigger occurs there are three possibilities Case 1 SEQ idle and SOC bit clear SEQ1 starts immediately under arbiter control This bit is
97. RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW The reset value of these bits depends upon the state of the respective pins Note R Read access W Write access 0 value after reset Bits 15 8 BnDIR 0 Configure corresponding pin as an input 1 Configure corresponding pin as an output Bits 7 0 IOPBn If BnDIR 0 then 0 Corresponding I O pin is read as a low 1 Corresponding I O pin is read as a high If BnDIR 1 then 0 Set corresponding I O pin low 1 Set corresponding I O pin high Digital Input Output I O 5 9 Data and Direction Control Registers Table 5 6 PBDATDIR I O Pin Designation Assuming Pins Have Been Selected as I O i e Secondary Function I O Port Data Bit Pin Name IOPBO CMP3 IOPBO IOPB1 CMP4 IOPB1 IOPB2 CMP5 IOPB2 IOPB3 CMP6 IOPB3 IOPB4 T1CMP IOPB4 IOPB5 T2CMP IOPB5 IOPB6 TDIR IOPB6t IOPB7 TCLKIN IOPB7 T There is no IOPB6 pin in 2402A devices Figure 5 7 Port C Data and Direction Control Register PCDATDIR 11 1 15 14 18 12 0 9 8 C7DIR C6DIR C5DIR C4DIR C3DIR C2DIR C1DIR CODIR RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW x The reset value of these bits depends upon the state of the respective pins Note R Read access W Write access 0 value after resett x undefined Bits 15 8 CnDIR 0 Configure corresponding pin as an input 1 Configure corresponding pin as
98. RX features idle line mode steps idle line multiprocessor communication format idle line multiprocessor mode receipt sequence receiver operation recognizing the address byte 5 sleep bit wake up temporary WUT double buffered WUT and TXSHF wake up temporary WUT flag physical description port interrupts programmable data format data frame formats typical programming using SCICCR SCI block diagram SCI module registers address table baud select L Sbyte register SCILBAUD Index 19 Index baud select MSbyte register data format SCIHBAUD example transmission of bit from SPIRX emulation data buffer register BUF SCIRXEMU data transfer example overview five bits per character receiver data buffer register initialization upon reset SCIRXBUF proper SPI initialization using the SPI SW RE receiver data buffer registers SCIRXEMU SET bit SCIRXBUF SPI interrupt control bits OVERRUN INT ENA bit SPICTL 4 tea a RECEIVER OVERRUN FLAG bit ee SPISTS 7 9 11 SCI communication control register SPI INT ENA bit SPICTL 0 SCICCR SCI control register 1 SCICTL1 SCI control register d SCICTL2 SPI INT FLAG bit SPISTS 6 SPI PRIORITY bit SPIPRI 6 operation SCI priority control register SCIPRI introduction transmit data buffer register master mode 9 8 SCITXBUF 5 31 master slave connection figure SCI physical description slave mode
99. Register 2 ADCTRL2 Address 70A1h 00 cee eee ees Maximum Conversion Channels Register MAXCONV Address 70A2h Autosequence Status Register AUTO SEQ SR Address 70A7h ADC Input Channel Select Sequencing Control Registers CHSELSEQn ADC Conversion Result Buffer Registers RESULTn cee ee eee SCI Block Diagram i iue atre nte e rca de Y LR A dora d hae dedos wees Typical SCI Data Frame Formats 0000 cece eee eee eens Idle Line Multiprocessor Communication Format ccc eee eee elles Double Buffered WUT and TXSHF 0 00 cece cece nett nee ened Address Bit Multiprocessor Communication Format 2 SCI Asynchronous Communications Format 2 SCI RX Signals in Communication Modes 0000c cece eee eee eee eee SCI TX Signals in Communications Mode 0 000 cece eee eee eens SCL REGISIGMS a ga kua ker z HA brick sd ened as kod d kde OA ERE See eee Ga a SCI Communication Control Register SCICCR Address 7050h SCI Control Register 1 SCICTL1 Address 7051h 0 0 cece eee Baud Select MSbyte Register SCIHBAUD Address 7052h 005 Baud Select LSbyte Register SCILBAUD Address 7053h luisse 8 14 SCI Control Register 2 SCICTL2 Address 7054h 2 cece elles 8 15 Receiver Status Register SCIRXST Address 7055h anaana annn nn
100. SBG Synchronization on both edges Bits 9 8 Bit 7 Bits 6 3 0 The CAN module resynchronizes on the falling edge only 1 Reserved SJW Synchronization jump width SJW indicates by how many units of TQ a bit is allowed to be lengthened or shortened when resynchronizing with the receive data stream on the CAN bus The synchronization is performed with the falling edge SBG 0 SJW is programmable from 1 to 4 TQ p B Note Since the SJW 1 0 value is enhanced by one by the CAN module the value that is written in bits 1 0 is actually SJW 1 where SJW is the timing segment referred to in Figure 10 17 CAN Bit Timing I SAM Sample point setting This parameter sets the number of samples used by the CAN module to determine the actual level of the CAN bus When the SAM bit is set the level determined by the CAN bus corresponds to the result from the majority decision of the last three values The sample points are at the sample point and twice before with a distance of 1 2 TQ 0 The CAN module samples only once 1 The CAN module samples three times and makes a majority decision TSEG1 3 0 Time segment 1 This parameter specifies the length of the TSEG1 segment in TQ units CAN Controller Module 10 27 CAN Control Registers TSEG1 combines PROP SEG and PHASE SEG1 segments CAN protocol TSEG1 PROP SEG PHASE SEG The value of TSEG1 is programmable from 3 to 16 TQ and must be greater than or equal to
101. SETC INTM LDP EVAIMRA gt gt 7 Peripheral page SPLK 0h EVAIMRA Mask all EVA interrupts SPLK 0h EVAIMRB SPLK 0h EVAIMRC SPLK OFFFFh EVAIFRA clear all EVA interrupt SPLK HOFFFFh EVAIFRB SPLK HOFFFFh EVAIFRC LDP EVBIMRA gt gt 7 Peripheral page SPLK 0h EVBIMRA Mask all EVB interrupts SPLK 0h EVBIMRB SPLK 0h EVBIMRC SPLK OFFFFh EVBIFRA clear all EVB interrupt SPLK OFFFFh EVBIFRB SPLK OFFFFh EVBIFRC LDP SCSR1 gt gt 7 SPLK 0000h SCSR1 disable EVA amp EVB clocks LDP GPTCONA gt gt 7 SPLK 0000000000000000b T1CON SPLK 0000000000000000b T2CON LDP GPTCONB gt gt 7 SPLK 0000000000000000b T3CON SPLK 0000000000000000b T4CON DONE B DONE End of test module ISR GISR4 Int4 GISR NOP LDP PIVR gt gt 7h Peripheral page LACL PIVR PIVR value XOR 0033h CAP1 interrupt BCND SISR33 eq LACL PIVR PIVR value XOR 0034h CAP2 interrupt BCND SISR34 eq LACL PIVR PIVR value XOR 0035h CAP3 interrupt BCND SISR35 eq LACL PIVR PIVR value XOR 0036h CAP4 interrupt BCND SISR36 eq LACL PIVR PIVR value XOR 0037h CAP5 interrupt BCND SISR37 eq LACL PIVR PIVR value S flags flags Program Examples C 37 Program Examples SISR33 CAPIFAIL CAP1PASS END_INT SISR34 CAP2FAIL CAP2PASS SISR35 C 38 XOR BCND RET LDP SPLK LDP BLDD BLDD LACL XOR BCND LACL XOR BCND LDP SPLK LDP SPLK CLRC RET LDP SPLK LDP BLDD
102. Sel state 0 pointer Ch Sel state 1 Ch Sel state 2 Ch Sel state 3 Autosequencer state machine Ch Sel state 15 Note Possible values are Channel select 0 to 15 MAXCONV 0 to 15 Software EVA EVB External pin ADCSOC Start of sequence trigger Analog to Digital Converter ADC 7 5 ADC Overview Figure 7 2 Block Diagram of Autosequenced ADC With Dual Sequencers Result MUX RESULTO RESULT1 10 Analog MUX e ADCINO 10 ADCIN1 Result RESULT7 ADCIN2 select 10 bit 10 e S H A D converter Result MUX ADCIN15 MUX RESULT8 select RESULT9 4 e Sequencer e Result RESULT15 4 select MAX CONV1 MAX CONV2 State State Ch Sel state 0 pointer Ch Sel state 8 pointer Ch Sel state 1 4 Ch Sel state 9 4 Ch Sel state 2 Ch Sel state 10 Ch Sel state 3 Ch Sel state 11 Note Possible values Channel select 0 to 15 SEQ2 MAX CONV1 0 to 7 Ch Sel state 7 Ch Sel state 15 MAX CONV2 8 to 15 Start of sequence Start of sequence Software trigger trigger Software eva gt gt EVB External pin ADCSOC Note There is only one A D converter in the DSP This converter is shared by the two sequencers in Dual Sequencer mode 7 6 ADC Overview The sequencer operation for both 8 state and 16 state modes is almost identical the few
103. TSEG2 ee UUULIOOS xv xwoOUGOUUUWGW BILIGanGwOGGWwLUUUUUAGATCTCCCCCCCCGSREEEEAE Note Since the TSEG1 3 0 value is enhanced by one by the CAN module the value that is written in bits 3 0 is actually TSEG1 1 where TSEG1 is the timing segment referred to in Figure 10 17 CAN Bit Timing LLLLLL Bits 2 0 TSEG2 2 0 Time segment 2 TSEG2 defines the length of PHASE SEG2 in TQ units The value of TSEG2 is programmable from 2 to 8 TQ in compliance with the formula SJW 1 lt TSEG2 lt 8 p 71 Note Since the TSEG2 2 0 value is enhanced by one by the CAN module the val ue that is written in bits 2 0 is actually TSEG2 1 where TSEG2 is the timing segment referred to in Figure 10 17 CAN Bit Timing LLLLLLSS O C AA 3 M MM 4 Note The user defined values for the SJW TSEG1 and TSEG2 parameters are enhanced by one by the internal logic when the CAN module accesses these parameters LLLLLLLSS O M 10 28 CAN Control Registers CAN Bit Timing Figure 10 17 CAN Bit Timing
104. The occurrence of a break causes a receiver interrupt to be generated if the RX BK INT ENA bit is a 1 but it does not cause the receiver buffer to be loaded A BRKDT interrupt can occur even if the receiver SLEEP bit is set to 1 BRKDT is cleared by an active SW RESET or by a system reset It is not cleared by receipt of a character after the break is detected In order to receive more characters the SCI must be reset by toggling the SW RESET bit or by a system reset 0 No break condition 1 Break condition occurred FE SCI framing error flag The SCI sets this bit when an expected stop bit is not found Only the first stop bit is checked The missing stop bit indicates that synchronization with the start bit has been lost and that the character is incorrectly framed The FE bit is reset by a clearing of the SW RESET bit or by a system reset 0 No framing error detected 1 Framing error detected OE SCI overrun error flag The SCI sets this bit when a character is transferred into registers SCIRXEMU and SCIRXBUF before the previous character is fully read by the CPU The previous character is overwritten and lost The OE flag bit is reset by an active SW RESET or by a system reset 0 No overrun error detected 1 Overrun error detected PE SCI parity error flag This flag bit is set when a character is received with a mismatch between the number of 1s and its parity bit The address bit is included in the calculation If parity generat
105. VBR counter ADD 1h SACL VBR_CNTR SUB VBR_MAX Is VBR counter gt max value POINT PF1 BCND UI01 NEO No fetch another char SND ECHO LACC OAAh Yes SACL SCITXBUF Indicate Host Baud rate lock B BAUD DETECTED BAUD RETRY POINT B1 SPLK 40h VBR CNTR LACC CHAR RETRY CNTR Inc CRC counter ADD lh SACL CHAR RETRY CNTR SUB HCRC MAX Is CRC gt max value BCND INC TBL PTR GEO Yes try next baud rate POINT PF1 TMS320F240x 240xA Boot ROM Loader Protocols and Interfacing D 17 Protocol Definitions B UI01 No fetch another char INC TBL PTR LACC BAUD TBL PTR Inc CRC counter ADD 1h AND 0007H BAUD TBL PTR is MOD 8 SACL BAUD TBL PTR SPLK 0h CHAR RETRY CNTR B UIOO BAUD DETECTED p RR RR k k k k k k KKK KKK KKK KKK KKK KK k k k k k k KKK KKK KK k ke k k k k k k k k k k k k k kc kc k k k k k k k k k k k k ck ck ck ck k k k iMAIN PROGRAM PRR RRR RRR KERR KK RRR KKK KERR KKK KKK KKK KR KERR KEK KK KKK RRR KERR kkk kkk kk kkk kkk kkk kkk kkk k kkk MAIN Load amp Execute incoming algorithm MOO CALL FETCH HEADER CALL CHECK DEST M01 CALL XFER SCI 2 PROG LACC DEST BACC Branch to the address where code is loaded p RR KR k k k k k k k k k k k ke k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k kc kc kc kc k k k k k k k k k k k k ck k k k k Routine Name FETCH HEADER Routine Type SR p Kk kkk k k k k k k k k ke e k ke k k he e k k he k k k ke e k k e k k k k k he k K
106. W 0 Note R read access W write access 0 value after reset Bit 15 Reserved Bits 14 0 IACK2 14 IACK2 O Bit behavior is the same as that of PIACKRO Peripheral Interrupt Registers Table 2 8 Peripheral Interrupt Acknowledge Descriptions PIACKR2 Bit position Interrupt Interrupt Description Interrupt Level IAK 2 0 PDPINTB Power drive protection interrupt pin INT1 IAK 2 1 CMPAINT Compare 4 interrupt INT2 IAK 2 2 CMP5INT Compare 5 interrupt INT2 IAK 2 3 CMP6INT Compare 6 interrupt INT2 IAK 2 4 T3PINT Timer 3 period interrupt INT2 IAK 2 5 T3CINT Timer 3 compare interrupt INT2 IAK 2 6 T3UFINT Timer 3 underflow interrupt INT2 IAK 2 7 T3OFINT Timer 3 overflow interrupt INT2 IAK 2 8 T4PINT Timer 4 period interrupt INT3 IAK 2 9 T4CINT Timer 4 compare interrupt INT3 IAK 2 10 T4UFINT Timer 4 underflow interrupt INT3 IAK 2 11 T4OF INT Timer 4 overflow interrupt INT3 IAK 2 12 CAP4INT Capture 4 interrupt INT4 IAK 2 13 CAP5INT Capture 5 interrupt INT4 IAK 2 14 CAP6INT Capture 6 interrupt INT4 System Configuration and Interrupts 2 37 Reset Illegal Address Detect 2 11 Reset The 240xA devices have two sources of reset An external reset pin _j A watchdog timer timeout The reset pin is an I O pin If there is an internal reset event watchdog timer the reset pin is put into output mode and driven low to indicate to external circuits that the 240xA device is resetting itself The external reset pin and watchdog ti
107. W R function in 2404A bits 0 6 and 7 of MCRB should always be written with 0 The corresponding pins work as GPIO pins only Due to the absence of the W R function in 2406A bit 0 of MCRB should always be written with 0 The corresponding pin works as a GPIO pin only SE 5 3 3 I O Mux Output Control Register C Figure 5 4 I O Mux Control Register C MCRC Address 7094h 15 14 13 12 11 I O Mux Control Registers 10 8 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 1 Note R Read access W Write access 0 value after reset Table 5 4 I O Mux Control Register C MCRC Configuration Bit O oln O Ga R CO PD EMIL o u ak RB wo m o 15 Name bit MCRC 0 MCRC 1 MCRC 2 MCRC 3 MCRC 4 MCRC 5 MCRC 6 MCRC 7 MCRC 8 MCRC 9 MCRC 10 MCRC 11 MCRC 12 MCRC 13 MCRC 14 MCRC 15 Pin Function Selected MCC n 1 Primary CLKOUT PWM7 PWM8 PWM9 PWM10 PWM11 PWM12 CAP4 QEP3 CAP5 QEP4 CAP6 T3PWM T3CMP T4PWM T4CMP TDIRB TCLKINB Reserved Reserved MCC n 0 Secondary IOPEO IOPE1 IOPE2 IOPE3 IOPE4 IOPE5 IOPE6 IOPE7 IOPFO IOPF1 IOPF2 IOPF3 IOPF4 IOPF5 Reserved Reserved Notes 1 Due to the absence of the EVB bits 1 through 13 must be treated as reserved in the 2402A 2 IOPF6 is not multiplexed with any other function Independent of the value of MCRC 14 this pin always works as a GPIO pin Digital Input Output
108. a different register SCSR1 and in different bit positions on the 240xA Software reset is not available However a software reset can be achieved by writing an incorrect key to the watchdog timer after setting a flag in memory to indicate that this was a software reset and not a true watchdog time out Illegal address detection does not have 100 coverage on the 240 however it does on 240xA devices Furthermore an illegal address generates a reset on the 240 and an NMI on the 240xA The NMI service routine must poll the ILLADDR bit in SCSR1 to determine whether the NMI was caused by an illegal address External interrupts XINT2 and XINT3 on the 240 are similar to external interrupts XINT1 and XINT2 on the 240xA The addresses of the registers are different however and the general purpose I O multiplexing control bits are located in the digital I O registers not in the external interrupt control registers The external interrupt flags are cleared by writing a 1 to the flag bit This is in order to be consistent with the other peripherals The CLOCKOUT control bits are in a different register SCSR1 and bit position A code security module CSM has been added to the 240xA devices 12 2 Event Manager Event Manager In order to port code from 240 to 240xA m m The GP timer 3 must not be used The single up count and single up down count modes of the GP timers must not be used The decoding of the timer modes fro
109. access to on chip flash the device must be first unsecured In all the four modes the device is unsecured by executing the Password Match Flow PMF E 1 2 CSM Impact on Other On Chip Resources The CSM has no impact whatsoever on the following on chip resources RAM blocks such as DARAM and SARAM These memory blocks can be freely accessed and code run from them whether the device is in se cure or unsecure mode Boot ROM contents Visibility to the boot ROM contents is not impacted by the CSM however invoking the boot ROM code would immediately se cure the device On chip peripheral registers The peripheral registers can be initialized by code running off on chip program memory whether the device is in se cure or unsecure To summarize it is possible to load code onto on chip program RAM via the JTAG connector without any impact from the CSM The code can be debugged and the peripheral registers initialized independent of whether the device is in secure or unsecure mode Flash ROM Code Security For LF LC240xA DSP Devices E 3 Flash ROM Security Feature E 1 3 Incorporating Code Security in User Applications Code security is typically not required in the development phase of a project however security is needed once a robust code is developed Before such a code is programmed in the flash memory or committed to ROM a password should be chosen to secure the device Once a password is in place the dev
110. an output Bits 7 0 IOPCn If CnDIR 0 then 0 Corresponding I O pin is read as a low 1 Corresponding I O pin is read as a high If CnDIR 1 then 0 Set corresponding I O pin low 1 Set corresponding I O pin high Data and Direction Control Registers Table 5 7 PCDATDIR VO Pin Designation Assuming Pins Have Been Selected as I O i e Secondary Function VO Port Data Bit Pin Name IOPCO W R IOPCOf IOPC1 BIO OPC1 IOPC2 SPISIMO IOPC2 IOPC3 SPISOMI IOPC3 IOPC4 SPICLK IOPC4 IOPC5 SPISTE OPOSt IOPC6 CANTX IOPC6 IOPC7 CANRX IOPC7 T These pins are not available on 2402A devices Figure 5 8 Port D Data and Direction Control Register PDDATDIR 15 9 RW 0 7 1 0 Reserved IOPDO RW The reset value of this bit depends upon the state of the respective pins Note R Read access W Write access 0 value after reset Bits 15 9 Reserved Bit 8 DODIR 0 Configure corresponding pin as an input 1 Configure corresponding pin as an output Bits 7 1 Reserved Bit 0 IOPDO If DODIR 0 then 0 Corresponding I O pin is read as a low 1 Corresponding I O pin is read as a high Digital Input Output I O 5 11 Data and Direction Control Registers If DODIR 1 then 0 Set corresponding I O pin low 1 Set corresponding I O pin high Table 5 8 PDDATDIR VO Pin Designation Assuming Pins Have Been Selected as I O i e Secondary Function I O Port Data Bit Pin Name IOPDO XINT2 ADCSOC IOPDO IOPD1 Reserved IOPD2 Res
111. and direction inputs to the timer A wide range of prescale factors are provided for the clock input to each GP timer QEP Based Clock Input The quadrature encoder pulse QEP circuit when selected can generate the input clock and counting direction for GP timer 2 4 in the directional up down counting mode This input clock cannot be scaled by GP timer prescaler circuits that is the prescaler of the selected GP timer is always one if the QEP circuit is selected as the clock source Furthermore the frequency of the clock generated by the QEP circuits is four times that of the frequency of each QEP input channel because both the rising and falling edges of both QEP input channels are counted by the selected timer The frequency of the QEP input must be less than or equal to one fourth of that of the device clock GP Timer Synchronization 6 20 GP timer 2 can be synchronized with GP timer 1 for EVA and GP timer 4 can be synchronized with GP timer 3 for EVB by proper configuration of T2CON and T4CON respectively in the following ways EVA Set the T2SWT1 bit in T2CON to start GP timer 2 counting with the TEN ABLE bit in T1CON thus both timer counters start simultaneously EVA Initialize the timer counters in GP timers 1 and 2 with different values be fore starting synchronized operation EVA Specify that GP timer 2 uses the period register of GP timer 1 as its period register ignoring its own period register
112. are low priority requests Bit 5 SCIRX PRIORITY SCI receiver interrupt priority select This bit specifies the priority level of the SCI receiver interrupts 0 Interrupts are high priority requests 1 Interrupts are low priority requests Bits 4 3 SCI SOFT and FREE bits These bits determine what occurs when an emula tion suspend event occurs for example when the debugger hits a breakpoint The peripheral can continue whatever it is doing free run mode or if in stop mode it can either stop immediately or stop when the current operation the current receive transmit sequence is complete Bit4 Bit3 SOFT FREE 0 0 Immediate stop on suspend 1 0 Complete current receive transmit sequence before stopping X 1 Free run Continues SCI operation regardless of suspend Bits 2 0 Reserved Reads return zero writes have no effect Chapter 9 Serial Peripheral Interface SPI The serial peripheral interface SPI is a high speed synchronous serial input output I O port that allows a serial bit stream of programmed length one to sixteen bits to be shifted into and out of the device at a programmed bit transfer rate The SPI is normally used for communications between the DSP controller and external peripherals or another controller Typical applications include external I O or peripheral expansion via devices such as shift registers display drivers and analog to digital converters ADCs Most SPI registers are eight bits in width except
113. based clock input rO r1 CAN data frame RAM dual access on chip RAM DARAM 3 2 on chip RAM Index 15 Index single access on chip RAM SARAM 3 2 RCR receive control register 10 22 receive mailboxes 10 13 receiver operation SCI serial communications interface receiver signals in communication modes SCI serial communications interface reducing development time 1 4 register address summary code security module CSM registers table B 9 programmable table registers 2407A wait state generator control register WSGR ADC control register 1 ADCTRL1 ADC control register 2 ADCTRL2 ADC conversion result buffer registers RESULT ADC input channel select sequencing control register 1 CHSELSEQ1 ADC input channel select sequencing control register 2 CHSELSEQ2 ADC input channel select sequencing control register 3 CHSELSEQ3 ADC input channel select sequencing control register 4 CHSELSEQ4 ADC register addresses ADC register bit descriptions autosequence status register AUTO SEQ SR baud select LSbyte register SCILBAUD baud select MSbyte register SCIHBAUD bit configuration register 1 BCR1 bit configuration register 2 BCR2 CALIBRATION CAN error counter register CEC CAN interrupt mask register CAN IMR CAN module register addresses table capture control register A CAPCONA capture control register B CAPCONB capture FIFO status register A CAP
114. be shut off by the device low power mode the CAN peripheral s own low power mode must be requested before a device low power mode is entered by executing the IDLE instruction Before the CPU enters its IDLE mode prior to the device low power mode that potentially shuts off a device clocks it must first request a CAN peripheral power down by writing a 1 to the PDR bit in MCR If the module is transmitting a message when PDR is set the transmission is continued until a successful transmission a lost arbitration or an error condition on the CAN bus line occurs Then the PDA is asserted Thus the module causes no error condition on the CAN bus line When the module is ready to enter the power down mode the status bit PDA is set The CPU must then poll the PDA bit in GSR and only enter IDLE after PDA is set On exiting the power down mode the PDR flag in the MCR must be cleared by software or automatically if the WUBA bit in MCR is set and there is bus activity on the CAN bus line When detecting a dominant signal on the CAN bus the wake up interrupt flag WUIF is asserted The power down mode is exited as soon as the clock is switched on There is no internal filtering for the CAN bus line The automatic wake up on bus activity can be enabled or disabled by setting the configuration bit WUBA If there is any activity on the CAN bus line the module begins its power up sequence The module waits until detecting 11 consecutive recessive bi
115. bit 0 12 upper 13 bits of extended identifier bit 13 Auto answer mode bit bit 14 Acceptance mask enable bit bit 15 Identifier extension bit SPLK 1111111111111111b CANMSGID3L IIIT H FEDCBA9876543210 bit 0 15 lower part of extended identifier SPLK 0000000000011000b CANMSGCTRL3 HITTITE EET H FEDCBA9876543210 bit 0 3 Data length code 1000 8 bytes bit 4 1 Remote frame y EK k k k KERR KERR KERR KERR RRR RR RRR KERR RRR RRR RRR KERR KR ERR RRR RRR RRR RRR ERR RE k k k k k k k k g KKK ck ck ke ke dee de Enable Mailbox KOK KK ke ke ke ke OI oko kk kk kc ko RRR II IO IO IO IO IO IO IO IO IO IO ke ko ke kc ko kc ko kc ko kc ko kc ko kc ko kc ko kk ko ek koe kk LDP HDP CAN SPLK 0000000010001000b CANMDER LLLEEEELELL LT T I A FEDCBA9876543210 bit 0 5 enable mailbox 3 bit 7 1 mailbox 3 receive p RRR cec ke e ee ke e e he e e e he e e e he e e e he e e e he e He e he e e he he e ke e he e e He he e e che e e ce He e ke ce He e ke He He e ke ke che ke ke ke he e ke ke ke e ke pO ke dee dee Bit timing Registers configuration Kckckckckckckckckckokoke ke ke ke ke ke ke ke ke ee OI ko kk RI RO ROR RII I IO IO IO IO ke koe IO IO IO IO IO IO IO ko ko ko kc ko kc ko kc ko ke ko IR ek koe Ik ke ke e SPLK 0001000000000000b CANMCR ULL LTL P FEDCBA9876543210 bit 12 Change configuration request for write access to BCR CCR 1 W CCE BIT CANGSR 0Bh Wait for Change config Enable BCND W CCE NTC bit t
116. by setting SELT1PR in T2CON EVB Set the T4SWT3 bit in TACON to start GP timer 4 counting with the TEN ABLE bit in T3CON thus both timer counters start simultaneously EVB Initialize the timer counters in GP timers 3 and 4 with different values be fore starting synchronized operation EVB Specify that GP timer 4 uses the period register of GP timer 3 as its period register ignoring its own period register by setting SELT3PR in TACON General Purpose GP Timers This allows the desired synchronization between GP timer events Since each GP timer starts the counting operation from its current value in the counter register one GP timer can be programmed to start with a known delay after the other GP timer Starting the A D Converter with a Timer Event The bits in GPTCONA B can specify that an ADC start signal be generated on a GP timer event such as underflow compare match or period match This feature provides synchronization between the GP timer event and the ADC start without any CPU intervention GP Timer in Emulation Suspend The GP timer control register bits also define the operation of the GP timers during emulation suspend These bits can be set to allow the operation of GP timers to continue when an emulation interrupt occurs making in circuit emulation possible They can also be set to specify that the operation of GP timers stops immediately or after completion of the current counting period when emulati
117. ck ck ck k k ck ck KEK i The SCI module is held in reset until the parameter is loaded for the Baud Rate register from the Baud Rate table in SCILBAUD i so the next lines stay commented out po k k k k K k K ke e he he K he ke e he he K he e A K he e e he ke A ce he ke K he ke A che he KA he ke ke che he ke e he ke che he ke e he ke e che he ke he he ke e e e e k SPLK 0023h SCICTL1 Relinquish SCI from Reset H SPLK 65 SCILBAUD p RRR RRR k k k k k k k k k RK KK RK RK k k k k k k KK RK KK RR KKK k k k k k k kck kck kck kck k k k k kck ck ck ckck ck ck k k ck ck ck ck ck k k k k Baudrate lock protocol with Host pok RRR KEK ke kc ke ke e he k ke e he ke ke he he K he e ke K he e e he ke A ce he ke K he ke e che he ke e he ke che he ke ce he ke che he e e kkk kk kkk kkk kkk CLR VBR CNTR POINT B1 SACL CHAR RETRY CNTR Clear retry counter SACL VBR CNTR Clear valid baud rate counter SACL BAUD TBL PTR BAUD TBL PTR is really only the offset from BAUD TBL UIOO0 SET BAUD LACC BAUD TBL PTR ADD HBAUD TBL POINT PF1 SPLK 0013h SCICTL1 Enable TX RX internal SCICLK TBLR SCILBAUD SPLK 0023h SCICTL1 Relinquish SCI from Reset UIO1 CALL reset WD BIT SCIRXST BIT6 Test RXRDY bit BCND UI01 NTC If RXRDY 0 then repeat loop LACC SCIRXBUF First byte is Lo byte Check if Char is as expected CHECK CHAR AND KOFFh Clear upper byte SUB 00Dh Compare with CR BCND BAUD RETRY NEQ INC VBRC POINT B1 LACC VBR CNTR inc
118. com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2006 Texas Instruments Incorporated About This Manual Preface Read This First This reference guide describes the architecture system hardware peripher als and general operation of the TMS320Lx2407A x2406A x2404A x2403A x2402A x24014 digital signal processor DSP controllers This book is also applicable to TMS320Lx2407 2406 2402 and future derivatives of the 240x family For a description of the CPU assembly language instructions and XDS510 emulator refer to TMS320F C24x DSP Controllers Reference Guide CPU and Instruction Set literature number SPRU160 This reference guide should SPRU160 be used in conjunction with Notational Conventions This document uses the following conventions Program listings program examples and interactive displays are shown inaspecial typeface similar to a typewriter s Examples use a bold version of the special typeface for emphasis interactive displays
119. completed sending or receiving the last bit and is ready to be serviced The received character is placed in the re ceiver buffer at the same time this bit is set This flag causes an interrupt to be requested if the SPI INT ENA bit SPICTL 0 is set This bit is cleared in one of three ways Reading SPIRXBUF 4 Writing a 0 to SPI SW RESET SPICCR 7 _j Resetting the system TX BUF FULL FLAG SPI Transmit Buffer Full Flag This read only bit gets set to 1 when a character is written to the SPI Transmit buffer SPITXBUF It is cleared when the character is automatically loaded into SPIDAT when the shifting out of a previous character is complete It is cleared at reset Reserved Reads return zero writes have no effect Serial Peripheral Interface SPI 9 23 SPI Module Registers 9 5 4 SPI Baud Rate Register SPIBRR SPIBRR contains the bits used for baud rate selection Figure 9 10 SPI Baud Rate Register SPIBRR Address 7044h g SPLBIT SPI BIT SPI BIT SPI BIT SPI BIT SPI BIT SPI BIT SSSIVe RATE 6 RATE 5 RATE 4 RATE 3 RATE 2 RATE 1 RATE 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bit 7 Reserved Reads return zero writes have no effect Bits 6 0 SPI BIT RATE 6 SPI BIT RATE O SPI Bit Rate Baud Control These bits de termine the bit transfer rate if the SPI is the network master There are 125 data transfer rates each a function of the CPU clock CLKOUT
120. completes transfer of the packet a branch is made into the incoming code Watchdog The watchdog timer on the device is active during the entire sequence and is being reset at key points in the code When a branch is made into the user code it is the responsibility of the user code to handle watchdog overflow as appropriate Restrictions on the incoming code B The combination of the destination address and transfer length must point to valid locations There is absolutely no error handling whatso ever TMS320F240x 240xA Boot ROM Loader Protocols and Interfacing D 3 Introduction B The combination also must point to a memory block that is contiguous m The address check is performed only on the first location of the incom ing destination It is expected that this allows enough space for the rest of the incoming words This means that if you have external program memory at range FDFEh to FDFFh two words and you attempt to load code into the range FDFEh to FEFFh attempting to use the inter nal memory FEOOh to FEFFh this combination is invalid since the destination check will not switch BO into the program space upon en countering the destination FDFEh Lastly the incoming address and length are expected to be 16 bits as defined in the SPI and SCI trans fer protocols Figure D 1 Example Hardware Configuration for LF240xA Boot ROM Operation SCI boot SPI boot load jo O O LF240xA u
121. control register GPTCONA B specifies the action to be taken by the timers on different timer events and indicates their counting directions Event Manager EV 6 17 General Purpose GP Timers GP Timer Compare Registers The compare register associated with a GP timer stores the value to be constantly compared with the counter of the GP timer When a match happens the following events occur A transition occurs on the associated compare output according to the bit pattern in GPTCONA B The corresponding interrupt flag is set _j A peripheral interrupt request is generated if the interrupt is unmasked The compare operation of a GP timer can be enabled or disabled by the appropriate bit in TxCON The compare operation and outputs can be enabled in any of the timer modes including QEP mode GP Timer Period Register The value in the period register of a GP timer determines the period of the timer A GP timer resets to 0 or starts counting downward when a match occurs between the period register and the timer counter depending on which counting mode the timer is in Double Buffering of GP Timer Compare and Period Registers The compare and period registers TXCMPR and TxPR of a GP timer are shadowed A new value can be written to any of these registers at any time during a period However the new value is written to the associated shadow register For the compare register the content in the shadow register is loaded
122. counting mode When the GP timer is in this mode the output of the waveform generator changes according to the following sequence zero before the counting operation starts Lj remains unchanged until the compare match happens Event Manager EV 6 27 General Purpose GP Timers toggles on compare match J remains unchanged until the end of the period resets to zero at the end of a period on period match if the new compare value for the following period is not zero The output is one for the whole period if the compare value is zero at the beginning of a period The output does not reset to zero if the new compare value for the following period is zero This is important because it allows the generation of PWM pulses of 0 to 100 duty cycle without glitches The output is zero for the whole period if the compare value is greater than the value in the period register The output is one for one cycle of the scaled clock input if the compare value is the same as that of the period register One characteristic of asymmetric PWM waveforms is that a change in the value of the compare register only affects one side of the PWM pulse Figure 6 10 GP Timer Compare PWM Output in Up Counting Mode Timer value TxPWM TxCMP active low TxPWM TxCMP active high Timer Timer PWM PWM period 1 period 2 Compare match New comp value greater than period Active Inactive
123. device is unsecure when the device comes up in the intended application mode in which code is executed from on chip flash ROM without JTAG connector connected i e the device is brought up in microcontroller mode upon reset with the on chip ROM bootloader disabled Note that this is the typical usage of the DSP in an end product Under what conditions is the device secure 1 When the on chip ROM bootloader is invoked 2 When the JTAG connector is connected 3 When the DSP is powered up in MP mode 4 When the KEY register values and the PWL values are different Can you explain the terms PWL and KEY registers PWL stands for Password locations These are memory locations at addresses 40h to 43h in on chip flash ROM which store the passwords PWL is mapped in program memory space The KEY registers are memory locations at addresses 77F0h to 77F3h in on chip data memory space Writing the password to the KEY register is part of the procedure to unlock the device Flash ROM Code Security For LF LC240xA DSP Devices E 13 CSM Frequently Asked Questions How do I secure a device You secure a device by ensuring the presence of passwords other than FFFFFFFFFFFFFFFFh or 0000000000000000h in the PWL ROM Place password into ROM code at location 40h 43h This password will be fabricated into the ROM with the ROM code Flash Program addresses 40h 43h with a password other than all zeros or all ones How do l unse
124. differences are highlighted in Table 7 2 Table 7 2 Comparison of Single and Cascaded Operating Modes Feature Start of conversion triggers Maximum number of autoconversions i e sequence length Autostop at end of sequence EOS Arbitration priority ADC conversion result register locations CHSELSEOn bit field assignment Single 8 state Single 8 state Cascaded 16 state sequencer 1 SEQ1 sequencer 2 SEQ2 sequencer SEQ EVA software EVB software EVA EVB software external pin external pin 8 8 16 Yes Yes Yes High Low Not applicable 0 t0 7 8 to 15 0 to 15 CONVOO to CONVO7 CONVO68 to CONV15 CONVOO to CONV15 For convenience the sequencer states will be subsequently referred to as For SEQ1 CONVOO to CONVO7 1 For SEQ2 CONV08 to CONV15 Lj For Cascaded SEQ CONVOO to CONV15 The analog input channel selected for each sequenced conversion is defined by CONVnn bit fields in the ADC input channel select sequencing control registers CHSELSEQn See section 7 5 5 ADC Input Channel Select Sequencing Control Registers on page 7 35 CONVnn is a 4 bit field that specifies any one of the 16 channels for conversion Since a maximum of 16 conversions in a sequence is possible when using the sequencers in cascaded mode 16 such 4 bit fields CONV00 CONV15 are available and are spread across four 16 bit registers CHSELSEQ1 CHSELSEQA The CONVnn bits can have any value from 0 to 15 The analog channe
125. even odd parity bit optional One or two stop bits Coc D An extra bit to distinguish addresses from data address bit mode only The basic unit of data is called a character and is one to eight bits in length Each character of data is formatted with a start bit one or two stop bits and optional parity and address bits A character of data with its formatting information is called a frame and is shown in Figure 8 2 Figure 8 2 Typical SCI Data Frame Formats ele Te Dem rol Idle line mode Normal nonmultiprocessor communications Address bit Addr A 7 MSB seje oje re Address bit mode Start Stop To program the data format use the SCICCR register The bits used to program the data format are shown in Table 8 2 Table 8 2 Programming the Data Format Using SCICCH Bit Name Designation Functions SCI CHAR2 0 SCICCR 2 0 Select the character data length one to eight bits Bit values are shown in Table 8 4 page 8 22 PARITY ENABLE SCICCR 5 Enables the parity function if set to 1 or disables the parity function if cleared to 0 EVEN ODD PARITY SCICCR 6 If parity is enabled selects odd parity if cleared to 0 or even parity if set to 1 STOP BITS SCICCR 7 Determines the number of stop bits trans mitted one stop bit if cleared to 0 or two stop bits if set to 1 SCI Multiprocessor Communication 8 3 SCI Multiprocessor Communication Address Byte Sleep Bit The multiproces
126. flag also stops the write denied interrupt WDI from being asserted CAN read write and CPU read accesses to the mailbox RAM take one clock cycle CPU writes to the mailbox RAM take two clock cycles 10 3 4 Transmit Mailbox Mailboxes 4 and 5 are transmit mailboxes only whereas mailboxes 2 and 3 can be configured for reception or transmission The CPU stores the data to be transmitted in a mailbox that is configured as a transmit mailbox After writing the data and the identifier into RAM and provided the corresponding TRS bit has been set the message is sent If more than one mailbox is configured as a transmit mailbox and more than one corresponding TRS bit is set the messages are sent one after another in falling order beginning with the highest enabled mailbox If a transmission fails due to a law of arbitration or an error the message transmission will be re attempted 10 3 5 Receive Mailbox Mailboxes 0 and 1 are receive only mailboxes Mailboxes 2 and 3 can be configured for reception or transmission The identifier of each incoming message is compared to the identifiers held in the receive mailboxes by using the appropriate identifier mask When equality is detected the received identifier the control bits and the data bytes are written into the matching RAM location At the same time the corresponding receive message pending RMPn bit is set and a mailbox interrupt MIFx is generated if enabled If the current iden
127. flash memory in program memory space is enabled This mode is selected with the MP MC pin microprocessor mode A mode in which the on chip ROM or flash memory is disabled and external program memory is enabled This mode is se lected with the MP MC pin microstack MSTACK 4A register used for temporary storage of the program counter PC value when an instruction needs to use the PC to address a second operand MIPS Million instructions per second MP MC pin A pin that indicates whether the processor is operating in micro processor mode or microcontroller mode MP MC high selects micropro cessor mode MP NC low selects microcontroller mode This pin is used to execute the on chip bootloader user code at reset When MP MC is held low during reset program control transfers to on chip non volatile memory at location 0000h When MP MC is held high control transfers to 0000h in external program memory MSB Most significant bit The highest order bit in a word When used in plural form MSBs refers to a specified number of high order bits begin ning with the highest order bit and counting to the right For example the eight MSBs of a 16 bit value are bits 15 through 8 See also LSB MSTACK See microstack multiplier A part of the CPU that performs 16 bit x 16 bit multiplication and generates a 32 bit product The multiplier operates using either signed or unsigned 2s complement arithmetic next AR See next auxiliary regi
128. frame bits DODDO UL CAN Controller Module 10 3 Overview of the CAN Network Figure 10 1 CAN Data Frame Bit length 1 12 0r32 6 0 8 bytes 7 Start bit Control bits Data field CRC bits End Arbitration field which contains Acknowledge 4 11 bit identifier RTR bit for standard frame format 4 29 bit identifier SRR bit IDE bit RTR bit for extended frame format Where RTR Remote Transmission Request SRR Substitute Remote Request IDE Identifier Extension Note Unless otherwise noted numbers are amount of bits in field 10 2 2 CAN Controller Architecture Figure 10 2 shows the basic architecture of the CAN controller Figure 10 2 TMS320x240xA CAN Module Block Diagram 240xA CAN module inter CANTX Control bus tatus registers rupt logic CPU interface J Memory management CAN transceiver chip Temporary receive buffer Data ID t Acceptance RAM 48x16 Mar Matched ID CANRX CAN bus mailbox 5 10 4 Overview of the CAN Network The CAN module is a 16 bit peripheral that accesses the following Control status registers Lj Mailbox RAM Control Status Registers The CPU performs 16 bit accesses to the control status registers The CAN peripheral always presents full 16 bit data to the CPU bus during read cycles Mailbox RAM Wr
129. imple mented in software All WD registers are identical TMS320F243 F241 C242 DSP Controllers Reference Guide literature number SPRU276 EVA Event Manager EVA is exactly identical to TMS320F243 F241 C242 DSP Controllers EV2 in 24x family Reference Guide literature number SPRU276 TMS320F243 F241 C242 DSP Controllers Reference Guide literature number SPRU276 TMS320F243 F241 C242 DSP Controllers Reference Guide literature number SPRU276 CAN Controller Area Network SCI Serial Communications Interface SPI Serial Peripheral Interf TMS320F243 F241 C242 DSP Controllers Serial PeripheralIntertace Reference Guide literature number BPRU276 Introduction 13 1 1 Migrating Code from 24x to 240x 240xA Devices All 240x 240xA peripherals with the exception of ADC are functionally identical to those in 24x devices Hence code written for the 24x can be easily ported to 240x 240xA devices However due to feature enhancements in the 240x 240xA devices the following points should be kept in mind 1 240x 240xA devices operate at higher clock speeds This warrants a change in the values written to the event manager registers that control parameters such as PWM frequency and other registers that affect the communication speed in serial devices such as the SPI SCI and CAN 2 After reset in the 240x 240xA devices the clock to all of the peripherals is disabled The peripheral clock must be enabled as part of the perip
130. in the second half of the period This error in output transition often as a result of calculation error in the application routine is corrected at the end of the period because the output resets to zero unless the new compare value for the following period is zero In this case the output remains one which again puts the output of the waveform generator in the correct state p Sse Note The output logic determines what the active state is for all output pins LLLLLLLLLLLLL v Event Manager EV 6 29 General Purpose GP Timers Figure 6 11 GP Timer Compare PWM Output in Up Down Counting Modes Timer value Compare match Timer Timer k PWM PWM period 1 period 2 Reloaded comp value greater than period xPWM TxCMP pene active low nactive xPWM TxCMP active high Compare matches Output Logic The output logic further conditions the output of the waveform generator to form the ultimate PWM output that controls different kinds of power devices The PWM output can be specified active high active low forced low and forced high by proper configuration of the appropriate GPTCONA B bits The polarity of the PWM output is the same as that of the output of the associated asymmetric symmetric waveform generator when the PWM output is specified active high The polarity
131. is acknowledged if the corresponding IFR bit is one and the INTM bit is zero The IMR is shown in Figure 2 9 and descriptions of the bits follow the figure Figure 2 9 Interrupt Mask Register IMR Address 0004h 15 6 5 4 3 2 1 0 INT6 mask INT5 mask INT4 mask INT3 mask INT2 mask INT1 mask 0 RW RW RW RW RW RW Note 0 Always read as zeros R Read access W Write access bit values are not affected by a device reset Bits 15 6 Reserved These bits are always read as zeros Bit 5 INT6 Interrupt 6 mask This bit masks or unmasks interrupt level INT6 O Level INT6 is masked 1 Level INT6 is unmasked Bit 4 INT5 Interrupt 5 mask This bit masks or unmasks interrupt level INT5 O Level INT5 is masked 1 Level INT5 is unmasked Bit 3 INT4 Interrupt 4 mask This bit masks or unmasks interrupt level INT4 O Level INT4 is masked 1 Level INT4 is unmasked Bit 2 INT3 Interrupt 3 mask This bit masks or unmasks interrupt level INT3 O Level INT3 is masked 1 Level INT3 is unmasked Bit 1 Bit 0 CPU Interrupt Registers INT2 Interrupt 2 mask This bit masks or unmasks interrupt level INT2 O Level INT2 is masked 1 Level INT2 is unmasked INT1 Interrupt 1 mask This bit masks or unmasks interrupt level INT1 O Level INT1 is masked 1 Level INT1 is unmasked M Note The IMR bits are not affected by a device reset I System Configuration and Interrupts 2 29 Peripheral Interrupt Registers 2 10 Peri
132. k k k k k A k he k k k k k k k k e k k k k k k k k k ke e k k e k k k k FETCH_HEADER CALL FETCH_SCI_WORD LACC data_buf SACL DEST CALL FETCH_SCI_WORD LACC data_buf SACL LENGTH RET p EK Kk k k k k k k kk k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k Routine Name X F ER S QT 2 PROG Routine Type SR p RRR RRR k k k k k RK k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ck ck ck ck k k k XFER_SCI_2_PROG MAR ARO LAR ARO LENGTH LACC DEST ACC dest address XSPO CALL FETCH SCI WORD TBLW data buf data buff ACC ADD 01h ACC BANZ XSPO loop length times RET D 18 Protocol Definitions PRR RR k k k k k k k k k k k kk KK k k KK k k k k k k KK KK k k k k k k k k k k k k k k k k k k k ck ck kck ck k ck ck ck ck k k ck k ck ck ck ck ck ck k k ck k k Routine Name Description FETCH SCI WORD Routine Type SR Version that expects Lo byte Hi byte sequence from Host amp also echoes byte p EKK K k k k k k k k k k k k k k k k k k k k k k k k k k k ck ck kck ck ck kck kck ck ck kck kck kck kck ck ck kck ck ck kck ck ck kck ck ck ck ck k k ck ck k k ck k k k k FETCH_SCI_WORD POINT B1 SACL stko LDP SCIRXST gt gt 7 FSWO CALL RESET WD BIT SCIRXST BIT6 Test RXRDY bit BCND FSWO NTC If RXRDY 0 then repeat loop LACC SCIRXBUF First byte is
133. k ke k k k k k k k k k k k k k k k k k k k k k p RRR sek ek kkk k Enable Mailbox kk kk ck ke KKK OO I IO IO IO IO III III III e e He koe koe ko ke ko IO IO IO IO IO IO IO IO IO IOI OR I IK Ik ke SPLK 0000000000000100b CANMDER Ree E FEDCBA9876543210 bit 0 5 Enable MBX2 bit 6 MBX2 configured as Transmit MBX g ER d k k k k k k k k ke k k KERR ke k k ke k RRR ERK RE RK KER KR ERK KER KK ERK k k RK k k k k k k k k k k k k k k k k k p KRKK sek dee ke Bit timing Registers configuration FORK RRR RR ke ke kk eek OO IO IO IO IO III III III III IUGR IO IO IO IO IO IO ko kk IO IOI III II II IR Ik Ik SPLK 0001000000000000b CANMCR HTTP EEE H FEDCBA9876543210 bit 12 Change configuration request for write access to BCR CCR 1 W CCE BIT CANGSR 0Bh Wait for Change config Enable BCND W CCE NTC bit to be set in GSR SPLK 0000000000000000b CANBCR2 For 1 Mbps 20 MHz CLKOUT SPLK 0000000000000001b CANBCR2 For 1 Mbps 40 MHz CLKOUT LELELEELEELLE LT I f FEDCBA9876543210 Program Examples Program Examples C 25 Program Examples bit 0 7 Baud rate prescaler bit 8 15 Reserved SPLK 0000000011111010b CANBCR1 For 1 Mbps 85 samp pt 7 FEDCBA9876543210 bit 0 2 TSEG2 bit 3 6 TSEG1 Tobit 7 Sample point setting 1 3 times 0 once bit 8 9 Synchronization jump width bit A F Reserved SPLK 0000000000000000b CANMCR FEDCBA9876543210 bit 12 Change conf register W NCCE BIT CANGSR KOBh Wait f
134. memory device Note MP MC pin is available only in LF2407A and LF2407 SARAM Program Data Space Select DON PON SARAM status 0 0 SARAM not mapped disabled address space allocated to external memory SARAM mapped internally to Program space SARAM mapped internally to Data space SARAM block mapped internally to both Data and Pro gram spaces This is the default or reset value Note See memory map for location of SARAM addresses System Configuration and Interrupts 2 7 Configuration Registers 2 2 2 Device Identification Number Register DINR Figure 2 4 Device Identification Number Register DINR Address 701Ch 15 14 13 12 11 10 9 8 DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 R x R x R x R x R x R x R x R x 7 6 5 4 3 2 1 0 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DINO R x R x R x R x R x R x R x R x Note R Read access x hardwired device specific DIN value Bits 15 4 DIN15 DIN4 These bits contain the hard wired device specific device identi fication number DIN Bits 3 0 DINS3 DINO These bits contain the hard wired device revision specific value Device Rev DIN LF2407 rev 1 0 1 5 0510h LF2407 1 6 0511h LF240xA 1 0 0520h LF240xA 1 1 0521h LC2406A LC2404A All revs 0700h LC2402A All revs 0610h LF2401A All revs 0810h LC2401A All revs 0910h 2 3 Interrupt Priority and Vectors Overall Priority 1 Interrupt Name Reset Reserved NMI a INT1 level 1 Overall Priority
135. must be cleared by software 4 IMR and IFR registers pertain to core level interrupts All peripherals have their own interrupt mask and flag bits in their respective control configuration registers Note that several peripheral interrupts are grouped under one core level interrupt I CPU Interrupt Registers Figure 2 8 Interrupt Flag Register IFR Address 0006h 15 6 5 4 3 2 1 0 INT6 flag INT5flag INT4flag INT3flag INT2flag INT1 flag 0 RW1C 0 RWIC 0 RWIC 0 RWIC 0 RWIC 0 RWIC 0 Note 0 Always read as zeros R Read access W1C Write 1 to this bit to clear it 0 value after reset Bits 15 6 Reserved These bits are always read as zeros Bit 5 INT6 Interrupt 6 flag This bit is the flag for interrupts connected to interrupt level INT6 0 No INT6 interrupt is pending 1 At least one INT6 interrupt is pending Write a 1 to this bit to clear it to 0 and clear the interrupt request Bit 4 INT5 Interrupt 5 flag This bit is the flag for interrupts connected to interrupt level INT5 0 NoINT5 interrupt is pending 1 At least one INT5 interrupt is pending Write a 1 to this bit to clear it to O and clear the interrupt request Bit 3 INT4 Interrupt 4 flag This bit is the flag for interrupts connected to interrupt level INT4 0 NoINTA interrupt is pending 1 At least one INT4 interrupt is pending Write a 1 to this bit to clear it to O and clear the interrupt request Bit 2 INT3 Interrupt 3 flag This bit i
136. of the SPICLK is one CLKOUT longer than the low pulse as shown in Figure 9 4 Figure 9 4 SPI SPICLK CLKOUT Characteristic when BRR 1 is Odd BRR gt 3 and CLOCK POLARITY 1 CLKOUT 2 cycles 3 cycles 2 cycles speck LS 9 4 5 Initialization Upon Reset A system reset forces the SPI peripheral module into the following default configuration O O O CD CD D D Unit is configured as a slave module MASTER SLAVE 0 Transmit capability is disabled TALK 0 Data is latched at the input on the falling edge of the SPICLK signal Character length is assumed to be one bit SPI interrupts are disabled Data in SPIDAT is reset to 0000h SPI module pin functions are selected as general purpose inputs this is done in I O Mux control register B MCRB To change this SPI configuration 1 Clear the SPI SW RESET bit SPICCR 7 to 0 to force the SPI to the reset state Initialize the SPI configuration format baud rate and pin functions as de sired Set the SPI SW RESET bit to 1 to release the SPI from the reset state Write to SPIDAT or SPITXBUF this initiates the communication process in the master Read SPIRXBUF after the data transmission has completed SPISTS 6 1 to determine what data was received Serial Peripheral Interface SPI 9 15 SPI Interrupts 9 45 1 Proper SPI Initialization Using the SPI SW RESET Bit To prevent unwanted and unforeseen events from occurring during o
137. of the 64 bit password Environments that Require Security Unlocking E 3 Environments that Require Security Unlocking Following are the typical situations under which unsecuring may be required Code development using debuggers such as Code Composer This is the most common environment during the design phase of a product Flash programming using Tl s flash utilities Flash programming is common during code development and testing Once the user supplies the necessary password the flash utilities disable the security logic before attempting to program the flash The flash utilities can disable the code security logic in new devices without any authorization since new devices come with an erased flash However reprogramming devices that already contain custom passwords require passwords to be supplied to the flash utilities in order to enable programming Custom environment defined by the application In addition to the above access to flash ROM memory contents may be required in situations such as m Using the on chip bootloader to program the flash m Executing code from external memory LF2407A device only and requiring access to flash for code libraries etc The unsecuring sequence is identical in all the above situations This sequence is referred to as the password match flow PMF for simplicity The following flowcharts explain the sequence of operation that is required every time the user attempts to unsecu
138. output pin TxPWM The value of a GP timer counter is constantly compared to that of its associated compare register A compare match occurs when the value of the timer counter is the same as that of the compare register Compare operation is enabled by setting TXCON 1 to one If it is enabled the following happens on a compare match J The compare interrupt flag of the timer is set one clock cycle after the match _j Atransition occurs on the associated PWM output according to the bit con figuration in GPTCONA B one device clock cycle after the match K the compare interrupt flag has been selected by the appropriate GPTCONA B bits to start ADC an ADC start signal is generated at the same time the compare interrupt flag is set A peripheral interrupt request is generated by the compare interrupt flag if it is unmasked PWM Transition The transition on the PWM output is controlled by an asymmetric and symmetric waveform generator and the associated output logic and depends on the following L Bit definition in GPTCONA B Counting mode the timer is in Counting direction when the counting mode is continuous up down mode Asymmetric Symmetric Waveform Generator The asymmetric symmetric waveform generator generates an asymmetric or symmetric PWM waveform based on the counting mode the GP timer is in Asymmetric Waveform Generation An asymmetric waveform Figure 6 10 is generated when the GP timer is in continuous up
139. output pulse width is zero when the value of TxCMPR is greater than that of TxPR for up counting modes For the up down counting mode the first transition is lost when TXCMPR up is greater than or equal to TxPR Similarly the second transition is lost when TxCMPR gp is greater than or equal to TxPR The GP timer compare output is inactive for the entire period if both TXCMPR yp and TxCMPR gn are greater than or equal to TxPR for the up down counting mode Figure 6 10 GP Timer Compare PWM Output in Up Counting Mode page 6 28 shows the compare operation of a GP timer in the up counting mode Figure 6 11 GP Timer Compare PWM Output in Up Down Counting Modes page 6 30 shows the compare operation of a GP timer in the up down counting mode 6 3 8 Timer Control Registers TXCON and GPTCONA B The addresses of the GP timer registers are given in Table 6 3 and Table 6 4 on page 6 11 The bit definition of the individual GP timer control registers TxCON is shown in Figure 6 12 The bit definition of the overall GP timer control registers GPTCONA and GPTCONB are shown in Figure 6 13 on page 6 35 and Figure 6 14 on page 6 36 respectively Individual GP Timer Control Register TxCON x 1 2 3 or 4 6 32 F7 Note Each Timer Control Register TXCON is independently configurable General Purpose GP Timers Figure 6 12 Timer x Control Register TXCON x 1 2 3 or 4 Addresses 7404h T1 CON 7408h
140. program to echo received characters back to the source program to initialize the ADC module of 240xA program to output serial data through the SPI port program to perform a loopback in the SCI module program memory 3 6 configuration program address data functional timing 56 program memory map for LF2407A programmable register address summary B 9 code security module CSM registers table protocols and interfacing boot ROM loader introduction boot load sequence example hardware configuration for LF240xA boot ROM operation memory maps for the LF2407A devices in microcontroller mode ports register z es on 240xA protocol definitions SCI asynchronous transfer protocol and data formats baud rate protocol clock speeds at which baud rate locks data transfer flowchart for FETCH SCI WORD flowchart for the serial loader baud rate match algorithm flowcharts for serial asynchronous loader and the fetch header routine SCI data transfer completion D 8 SPI synchronous transfer protocol and data formats SPI data packet definition TMS320F240x 240xA PWM circuits associated with compare units block diagram PWM generation capability of event manager PWM operation PWM outputs generation using the GP timers 638 PWM operation PWM waveform generation asymmetric PWM waveform generation with compare unit and PWM circuits figure capture interrupts capture unit FIFO stacks first capture second capture thi
141. set and cleared allowing for any pending trigger requests Case 2 SEQ1 busy and SOC bit clear Bit is set signifying a trigger request is pending When SEG finally starts after completing current conversion this bit will be cleared Case 3 SEQ1 busy and SOC bit set Any trigger occurring in this case will be ignored lost 0 Clears a pending SOC trigger Note If the sequencer has already started this bit will automatical ly be cleared and hence writing a zero will have no effect i e an already started sequencer cannot be stopped by clearing this bit 1 Software trigger Start SEQ1 from currently stopped position i e Idle mode 4 Note The RST SEQ1 ADCTRL2 14 and the SOC SEQ1 ADCTRL2 13 bits should not be set in the same instruction This will reset the sequencer but will not start the sequence The correct sequence of operation is to set the RST SEQ bit first and the SOC SEQ bit in the following instruction This ensures that the sequencer is reset and a new sequence started This se quence applies to the RST SEQ2 ADCTRL2 6 and SOC SEQ2 ADCTRL2 5 bits also LLLLLLLLL SEQ1 BSY SEQ1 Busy This bit is set to a 1 while the ADC autoconversion sequence is in progress It is cleared when the conversion sequence is complete 0 Sequencer is
142. set and enabled is loaded into the PIVR when an interrupt request is acknowledged this is all done in the peripheral interrupt controller external to the event manager peripheral V7 1 Note Failure to Clear the Interrupt Flag Bit The interrupt flag bit in the peripheral register must be cleared by software writing a 1 to the bit in the ISR Failure to clear this bit will prevent future inter rupt requests by that source LLLLLLLLLLL MM A 6 10 2 EV Interrupt Flag Registers Addresses of the EVA and EVB interrupt registers are shown in Table 6 9 and Table 6 10 respectively on page 6 13 The registers are all treated as 16 bit memory mapped registers The unused bits all return zero when read by software Writing to unused bits has no effect Since EVxIFRx are readable registers occurrence of an interrupt event can be monitored by software polling the appropriate bit in EVxIFRx when the interrupt is masked EVA Interrupt Flag Register A EVAIFRA Figure 6 39 EVA Interrupt Flag Register A EVAIFRA Address 742Fh 15 11 10 9 8 B d T1OFINT T1UFINT T1CINT oso FLAG FLAG FLAG R 0 RW1C 0 RW1C 0 RW1C 0 7 6 4 3 2 1 0 T1PINT 3 2 CMP3INT CMP2INT CMP1INT PDPINTA FLAG kodiak FLAG FLAG FLAG FLAG RW1C 0 R 0 RW1C 0 RWi1C 0 JRW1C 0 RWIC 0 Note R Read access W1C Write 1 to clear 0 value after reset Bits 15 11 Reserved Reads return zero writes have no
143. the CDR is set This is checked by the state machine before and after it reads the data from the mailbox to store it in the transmit buffer ABO Auto Bus On 0 The bus off state may only be left after 128 x 11 consecutive recessive bits on the bus and after having reset the CCR bit After the bus off state the module goes back to the bus on state after 128 x 11 consecutive recessive bits STM Self Test Mode 0 1 The module is in normal mode The module is in Self Test mode In this mode the CAN module generates its own ACK signal Thus it enables operation without a bus connected to the module The message is not sent but read back and stored in the appropriate mailbox The remote frame handling with Auto Answer mode set is not implemented in STM The received message ID will not be stored in the receive mailbox in this mode Reserved MBNR Mailbox Number for CDR bit assertion The CPU requests a write access to the data field for the mailbox having this number and configured for Remote Frame Handling These are mailboxes 2 10 or 3 11 but not 0 1 4 or 5 10 4 5 Bit Configuration Registers BCRn The bit configuration registers BCR1 and BCR2 are used to configure the CAN node with the appropriate network timing parameters These registers must be programmed before using the CAN module and are writeable only in configuration mode The CCR bit MCR 12 must be set to put the CAN module in configuration mode
144. the CPU When the CPU goes into IDLE mode the CPU clock domain is stopped while the system clock domain continues to run This mode is also known as IDLE1 mode The 240xA CPU contains support for a second IDLE mode IDLE2 implemented in external logic By asserting the IDLE2 input to the 240xA CPU both the CPU clock domain and the system clock domain are stopped allowing further power savings A third low power mode HALT mode which is the deepest mode is possible if the oscillator and WDCLK are also shut down In HALT mode the input clock to the PLL is shut off The low power modes do not change the state of the GPIO pins The pins maintain the same state which they were in prior to entering the low power mode Also the GPIO pins are not put into the high impedance state and the internal pullup pulldown is not turned off while in low power modes There are two control bits LPM 1 0 that specify which of the three possible low power modes is entered when the IDLE instruction is executed This is described in Table 4 1 These bits are located in system control and status register 1 SCSR1 described in section 2 2 1 on page 2 3 Low Power Modes Table 4 1 Low Power Modes Summary Low Power Mode CPU running normally IDLE1 LPMO IDLE2 LPM1 HALT LPM2 PLL OSC power down CPU System LPMx Bits Clock Clock WDCLK PLL OSC SCSR 12 13 Domain Domain Status Status Status Exit Condition XX On On On On On
145. the IOPC2 pin on the device The code takes a snapshot of this pin after being invoked and determines which loader SPI or SCI to invoke based on the status of this pin B f IOPC2 is pulled low an SCI transfer is commenced B If IOPC2 is pulled high an SPI transfer is commenced m Note that the SPI selection is invalid on devices without the SPI It is suggested that this pin should be driven via a resistor as well because SPISIMO will be an output if the SPI is used at any time dur ing the operation of the system Destination check The incoming destination is now compared to the range FEOOh to FFFFh If the destination matches this range the CNF bit Bit 12 in status register ST1 is set configuring the DARAM memory block BO to Program Memory Space No other checks are performed and it is entirely up to the host external boot device to supply a valid combination of the memory destination address and the length for the incoming code This means that the target code must fit into the internal memory or external memory must be available Data transfer Once the incoming destination and length are fetched this protocol is defined in separate sections for the SCI and SPI the actual data transfer commences The fetch is basically destination length and data with no error checking On the SCI the incoming data is echoed back allowing the host to implement error checking if desired Execution of incoming code Once the Boot ROM loader
146. the interrupt controller When the CPU asserts its interrupt acknowledge it simultaneously puts a value on the program address bus which corresponds to the CPU interrupt being acknowledged It does this to fetch the interrupt vector from program memory each INTn has a vector stored in a dedicated program memory address This value is shown in Table 2 2 240xA Interrupt Source Priority and Vectors on page 2 9 The PIE controller decodes this value to determine which of the CPU interrupt requests is being acknowledged It then generates a peripheral interrupt acknowledge in response to the highest priority currently asserted PIRQ associated with that CPU interrupt Interrupt Vectors 2 5 Interrupt Vectors When the CPU receives an interrupt request it does not know which peripheral event caused the request To enable the CPU to distinguish between all of these events a unique peripheral interrupt vector is generated in response to an active peripheral interrupt request This vector is loaded into the peripheral interrupt vector register PIVR in the PIE controller It can then be read by the CPU and used to generate a vector to branch to the interrupt service routine ISR which corresponds to the event being acknowledged In effect there are two vector tables The CPU s vector table which is used to get to the first general interrupt service routine GISR in response to a CPU interrupt request and the peripheral vector table which is use
147. the interrupt and checks the incom ing address This address byte is checked against its device address byte stored in memory 3 If the check shows that the block is addressed to the device CPU the CPU clears the SLEEP bit and reads the rest of the block if not the software routine exits with the SLEEP bit still set and does not receive interrupts un til the next block start 8 3 1 Idle Line Multiprocessor Mode 8 10 In the idle line multiprocessor protocol ADDR IDLE MODE bit 0 blocks are separated by having a longer idle time between the blocks than between frames in the blocks An idle time of ten or more high level bits after a frame indicates the start of a new block The time of a single bit is calculated directly from the baud value bits per second The idle line multiprocessor communication format is shown in Figure 8 3 ADDR IDLE MODE bit is SCICCR 3 SCI Multiprocessor Communication Figure 8 3 Idle Line Multiprocessor Communication Format poo Several VISIONE nan Data format i N NI Pins SCIRXD SCITXD SS t SS E d Idle periods of 10 bits or more pd separate the blocks One block of frames z t E Data format expanded Address a Data Last Data First frame within block Frame within Idle period Idle period Is address it follows idle block less than of 10 bits period of 10 bits or more 10 bits or more Idle Line Mode Steps The steps followed by the idle line mode
148. the timer in this mode Either the external or internal device clock can be selected as the input clock to the timer TDIRA B input is ignored by the GP timer in this counting mode The continuous up counting mode of the GP timer is particularly useful for the generation of edge triggered or asynchronous PWM waveforms and sampling periods in many motor and motion control systems Figure 6 7 shows the continuous up counting mode of the GP timer Event Manager EV 6 23 General Purpose GP Timers Figure 6 7 GP Timer Continuous Up Counting Mode TxPH 3 or 2 TxPR 4 1 3 TXPR 3 1 2 Timer value TxCON 6 Timer clock FF LT LE LELELELELELELELE As shown in Figure 6 7 GP Timer Continuous Up Counting Mode TxPR 3 or 2 no clock cycle is missed from the time the counter reaches the period register value to the time it starts another counting cycle Directional Up Down Counting Mode The GP timer in directional up down counting mode counts up or down according to the scaled clock and TDIRA B inputs The GP timer starts counting up until its value reaches that of the period register or FFFFh if the initial count is greater than the period when the TDIRA B pin is held high When the timer value equals that of its period register or FFFFh the timer resets to zero and continues counting up to the period again When TDIRA B is held low the GP timer counts down until its value becomes zero When the value of the timer has co
149. timer 1 compare output 00 Forced low 01 Active low 10 Active high 11 Forced high Overall GP Timer Control Register B GPTCONB Figure 6 14 GP Timer Control Register B GPTCONB Address 7500h 15 12 11 10 9 8 7 14 13 T4STAT T3STAT T4TOADC T3TOADC R 1 R 1 RW 0 RW 0 RW 0 RW 0 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access n value after reset Bit 15 Reserved Reads return zero writes have no effect Bit 14 TASTAT GP timer 4 Status Read only 0 Counting downward 1 Counting upward Bit 13 T3STAT GP timer 3 Status Read only 0 Counting downward 1 Counting upward Bits 12 11 Reserved Reads return zero writes have no effect Bits 10 9 Bits 8 7 Bit 6 Bits 5 4 Bits 3 2 Bits 1 0 General Purpose GP Timers T4TOADC Start ADC with timer 4 event 00 No event starts ADC 01 Setting of underflow interrupt flag starts ADC 10 Setting of period interrupt flag starts ADC 11 Setting of compare interrupt flag starts ADC TSTOADC Start ADC with timer 3 event 00 No event starts ADC 01 Setting of underflow interrupt flag starts ADC 10 Setting of period interrupt flag starts ADC 11 Setting of compare interrupt flag starts ADC TCOMPOE Compare output enable If PDPINTx is active this bit is set to zero 0 Disable all GP timer compare outputs all compare outputs are put in the high impedance state 1 Enable all GP timer compare outputs Reserved Reads return zero writes
150. timer 3 as its period register In Figure 6 3 the mux is applicable only when the figure represents timer 4 I General Purpose GP Timers Bit s Name Description 15 0 T1CNT Holds the instantaneous value of Timer 1 counter Figure 6 3 General Purpose Timer Block Diagram x 2 or 4 When x 2 y 1andn 2 whenx 4 y 3andn 4 TxPR period register shadowed TyPR period register shadowed GPTCONA B GP timer control N mx A TnCON O0 register Symm asym waveform generator TxCMPR compare Compare register logic shadowed Output logic TxPWM Interrupt flags TxCNT GP timer counter ADC start of conversion Internal Control clock TDIRA B TxCON GPTx control register Event Manager EV 6 15 General Purpose GP Timers Figure 6 4 Timer x Counter Register TxCNT where x 1 2 3 or 4 15 0 T1CNT R W x Legend R Read access W Write access 0 value after reset Figure 6 5 Timer x Compare Register TxCMPR where x 1 2 3 or 4 15 R W x Legend R Read access W Write access 0 value after reset Bit s Name Description 15 0 T1CMPR Holds the compare value of Timer 1 counter Figure 6 6 Timer x Period Register TxPR where x 1 2 3 or 4 15 0 TIPR R W x Legend R Read access W Write access 0 value after reset GP Timer Inputs The inputs to the GP timers are The internal device CPU clock Lj An external clock TCLKI
151. will be transferred to the SPIDAT register when all bits of the character to be transmitted have been shifted out of SPIDAT If no character is currently being transmitted when SPITXBUF is written to the data will be transferred immediately to SPIDAT To receive data the SPI waits for the network master to send the SPICLK signal and then shifts the data on the SPISIMO pin into SPIDAT If data is to be transmitted by the slave simultaneously and SPITXBUF has not been previously loaded the data must be written to SPITXBUF or SPIDAT before the beginning of the SPICLK signal When the TALK bit SPICTL 1 is cleared data transmission is disabled and the output line SPISOMI is put into the high impedance state If this occurs while a transmission is active the current character is completely transmitted even though SPISOMI is forced into the high impedance state This ensures that the SPI is still able to receive incomming data correctly This TALK bit allows many slave devices to be tied together on the network but only one slave at a time is allowed to drive the SPISOMI line The SPISTE pin operates as the slave select pin An active low signal on the SPISTE pin allows the slave SPI to transfer data to the serial data line an inactive high signal causes the slave SPI s serial shift register to stop and its serial output pin to be put into the high impedance state This allows many slave devices to be tied together on the network although onl
152. your code can read from and write to DARAM in the same clock cycle DARAM configuration bit CNF See CNF bit data address generation logic Logic circuitry that generates the address es for data memory reads and writes This circuitry which includes the auxiliary registers and the ARAU can generate one address per machine cycle See also program address generation logic data page One block of 128 words in data memory Data memory contains 512 data pages Data page 0 is the first page of data memory addresses 0000h 007Fh data page 511 is the last page addresses FF80h FFFFh See also data page pointer DP direct addressing data page 0 Addresses 0000h 007Fh in data memory contains the memory mapped registers a reserved test emulation area for special information transfers and the scratch pad RAM block B2 data page pointer DP A 9 bit field in status register STO that specifies which of the 512 data pages is currently selected for direct address generation When an instruction uses direct addressing to access a data memory value the DP provides the nine MSBs of the data memory address and the instruction provides the seven LSBs data read address bus DRAB A 16 bit internal bus that carries the address for each read from data memory Glossary data read bus DRDB A 16 bit internal bus that carries data from data memory to the CALU and the ARAU data write address bus DWAB A 16 bit internal bus that carri
153. 0 must be set 4 The program writes a second character to SCITXBUF after TXRDY goes high item 3 TXRDY goes low again after the second character is written to SCITXBUF 5 Transmission of the first character is complete Transfer of the second character to shift register TXSHF begins 6 Bit TXENA goes low to disable the transmitter the SCI finishes transmitting the current character 7 Transmission of the second character is complete transmitter is empty and ready for new character Serial Communications Interface SCI 8 17 SCI Port Interrupts 8 5 SCI Port Interrupts 8 18 The SCI s receiver and transmitter can be interrupt controlled The SCICTL2 register has one flag bit TXRDY that indicates active interrupt conditions and the SCIRXST register has two interrupt flag bits RXRDY and BRKDT plus the RX ERROR interrupt flag which is a logical OR of the FE OE and PE conditions The transmitter and receiver have separate interrupt enable bits When not enabled the interrupts are not asserted however the condition flags remain active reflecting transmission and receipt status The SCI has independent peripheral interrupt vectors for the receiver and transmitter Peripheral interrupt requests can be either high priority or low priority This is indicated by the priority bits which are output from the peripheral to the PIE controller SCI interrupts can be programmed to assert the high or low priority levels by the SCIRX
154. 00 Forced low 01 Active low 10 Active high 11 Forced high Bits 1 0 CMP7ACT1 0 Action on compare output pin 7 CMP7 00 Forced low 01 Active low 10 Active high 11 Forced high 6 4 2 Compare Unit Interrupts There is a maskable interrupt flag in EVAIFRA and EVBIFRA for each compare unit The interrupt flag of a compare unit is set one clock cycle after a compare match if a compare operation is enabled A peripheral interrupt request is generated by the flag if it is unmasked 6 4 3 Compare Unit Reset When any reset event occurs all register bits associated with the compare units are reset to zero and all compare output pins are put in the high impedance state Event Manager EV 6 47 PWM Circuits Associated With Compare Units 6 5 PWM Circuits Associated With Compare Units The PWM circuits associated with compare units make it possible to generate six PWM output channels per EV with programmable dead band and output polarity The EVA PWM circuits functional block diagram is shown in Figure 6 20 It includes the following functional units Asymmetric Symmetric Waveform Generators j Programmable Dead Band Unit DBU Output Logic Space Vector SV PWM State Machine The EVB PWM circuits functional block diagram is identical to that of the EVA s with the corresponding change of configuration registers The asymmetric symmetric waveform generators are the same as those of the GP timers The dead band units an
155. 00 When T1CNT 0 that is on underflow 01 When T1OCNT 0 or T1CNT T1PR that is on underflow or period match 10 Immediately 11 Reserved result is unpredictable Bit 12 SVENABLE Space vector PWM mode enable 0 Disables space vector PWM mode 1 Enables space vector PWM mode Bits 11 10 ACTRLD1 ACTRLDO Action control register reload condition 00 When T1CNT 0 on underflow 01 When T1CNT 0 or T1CNT T1PR on underflow or period match 10 Immediately 11 Reserved Compare Units Bit 9 FCOMPOE Compare output enable Active PDPINTA clears this bit to zero 0 PWM output pins are in high impedance state that is they are disabled 1 PWM output pins are not in high impedance state that is they are enabled Bit 8 PDPINTA STATUS This bit reflects the current status of the PDPINTA pin An application could poll this bit to determine whether the fault that activated this pin has disappeared This bit is applicable to 240xA devices only it is re served on 240x devices and returns a zero when read Bits 7 0 Reserved Read returns zero writes have no effect Figure 6 17 Compare Control Register B COMCONB Address 7511h CENABLE CLD1 CLDO SVENABLE ACTRLD1 ACTRLDO FCOMPOE mum RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 PDPINTE PIN 7 0 R 0 Note R Read access W Write access 0 value after reset Bit 15 CENABLE Compare enable 0 Disable compare operation All shadowed registers CMPRx ACTRB become transp
156. 07A LF2406A LF2403A LF2402A LF240xA flash devices and LC2406A LC2404A and LC2402A LC240xA ROM devices are designed with on chip Flash and ROM memories in program space These memories range from 32K words to 6K words depending on the device derivative in this family All of these devices have a code security logic that can protect access to their respective Flash or ROM program memory spaces Functional Description In many applications there is an increasing need to have code security once the application code is fully developed and released to production Security is defined with respect to the read access to on chip program memory and prevents unauthorized copying of proprietary code The security module is intended to block the CPU s read access to on chip program memory This in effect blocks read access to Flash ROM through the JTAG port or external peripherals The Security Mode Table Table E 1 explains the conditions under which the 240xA devices are considered secure or unsecure Table E 1 Security Mode Table Mode 1 240xA memory access Mode select conditions Device status Remarks Runtime using on chip MP MC 0 upon reset Unsecure Code is free run from program memory Microcontroller mode on chip flash ROM without JTAG On chip bootloader Typical usage of the DSP connector connected disabled in an end product Runtime using external MP MC 1 upon reset Secure Code is run from external program memory Micropr
157. 1 SCI wakes up after receipt of the block start signal 2 The processor recognizes the next SCI interrupt 3 Theinterrupt service routine compares the received address sent by a re mote transmitter to its own 4 Ifthe CPU is being addressed the service routine clears the SLEEP bit and receives the rest of the data block 5 If the CPU is not being addressed the SLEEP bit remains set This lets the CPU continue to execute its main program without being interrupted by the SCI port until the next detection of a block start Block Start Signal There are two ways to send a block start signal Method 1 Deliberately leave an idle time of ten bits or more by delaying the time between the transmission of the last frame of data in the previous block and the transmission of the address frame of the new block Serial Communications Interface SCI 8 11 SCI Multiprocessor Communication Method 2 The SCI port first sets the TXWAKE bit SCICTL 1 3 to 1 before writing to the SCITXBUF register This sends an idle time of exactly 11 bits In this method the serial communications line is not idle any longer than necessary A don t care byte has to be written to SCITXBUF after setting TXWAKE and before sending the address so as to transmit the idle time Wake UP Temporary WUT Flag Associated with the TXWAKE bit is the wake up temporary WUT flag WUT is an internal flag double buffered with TXWAKE When TXSHF is loaded from S
158. 1 Values l4 lo I3 V4 Vo and V3 are read from ADC result registers 2 The sequencer is reset Step 2 is repeated Note that the interrupt flag is set every time SEQ CNTR n reaches zero This would happen after the ADC has finished converting I4 lo and Ig and also after converting V4 Vo and V3 But only the EOS generated after the conversion of V4 Vo and Vs triggers the interrupt ADC Overview Case3 Number of samples in the first and second sequences are equal with dummy read Mode 2 Interrupt operation i e Interrupt request occurs at every other EOS 1 Sequencer is initialized with MAX CONVn 2 for l4 lo x sampling 2 At ISR b and d the following events take place 1 Values l4 lo X V4 Vo and V3 are read from ADC result registers 2 The sequencer is reset 3 Step 2 is repeated Note that the third I sample x is a dummy sample and is not really required However to minimize ISR overhead and CPU inter vention advantage is taken of the every other Interrupt request feature of Mode 2 Analog to Digital Converter ADC 7 15 ADC Overview Figure 7 5 Interrupt Operation During Sequenced Conversions 25us Et 50us 9 EV1 Timer 1 counter PWM V4 Vo V3 j V4 V2 V3 te Sampling request Case 1 SEQ interrupt l4 l2 13 V4 Vo V3 4 slo V4 Vo V3 Sampling request Case 2 SEQ in
159. 1 0 Low Power mode selected 00 IDLE1 LPMO 01 IDLE2 LPM1 1x HALT LPM2 System Configuration and Interrupts 2 3 Configuration Registers Bits 11 9 PLL Clock prescale select These bits select the PLL multiplication factor for the input clock CLK CLK CLK System Clock Frequency PS2 PS1 PSO 0 0 0 4X Fin 0 0 1 2 X Fin 0 1 0 1 33 x Fin 0 1 1 1X Fin 1 0 0 0 8 X Fin 1 0 1 0 66 x Fin 1 1 0 0 57 x Fin 1 1 1 0 5 x Fin Note Finis the input clock frequency Bit 8 Reserved Bit 7 ADC CLKEN ADC module clock enable control bit O Clock to module is disabled i e shut down to conserve power 1 Clock to module is enabled and running normally Bit 6 SCI CLKEN SCI module clock enable control bit 0 Clock to module is disabled i e shut down to conserve power 1 Clock to module is enabled and running normally Bit 5 SPI CLKEN SPI module clock enable control bit 0 Clock to module is disabled i e shut down to conserve power 1 Clock to module is enabled and running normally Bit 4 CAN CLKEN CAN module clock enable control bit O Clock to module is disabled i e shut down to conserve power 1 Clock to module is enabled and running normally Bit 3 EVB CLKEN EVB module clock enable control bit 0 Clock to module is disabled i e shut down to conserve power 1 Clock to module is enabled and running normally Bit 2 EVA CLKEN EVA module clock enable control bit 0 Clock to module is disabled i e shut down to conserve power
160. 1 Conversion result buffer register 11 70B4h RESULT12 Conversion result buffer register 12 70B5h RESULT13 Conversion result buffer register 13 70B6h RESULT14 Conversion result buffer register 14 70B7h RESULT15 Conversion result buffer register 15 70B8h CALIBRATIONT Calibration result used to correct subsequent conversions t The calibration feature available in 240x devices has some restrictions in usage See the following device errata for details TMS320LF2402 DSP Controller Silicon Errata literature numbe SPRZ157 TMS320LF2406 DSP Controller Silicon Errata lit erature number SPRZ159 and TMS320LF2407 DSP Controller Silicon Errata literature a Note that the cal ibration and self test features are not supported on the 240xA devices Hence bits 0 1 2 and 3 of the ADCTRL1 register must be treated as reserved in 240xA devices and must be written with zeroes Furthermore the functionality of bit 14 of ADCTRL2 is restricted to RST SEQ only Analog to Digital Converter ADC 7 8 ADC Overview 7 2 ADC Overview 7 2 1 Autoconversion Sequencer Principle of Operation The ADC sequencer consists of two independent 8 state sequencers SEQ1 and SEQ2 that can also be cascaded together to form one 16 state sequencer SEQ The word state represents the number of autoconversions that can be performed with the sequencer Block diagrams of the single 16 state cascaded and dual two 8 state separated sequencer modes are shown in Fig
161. 1h 15 14 3 2 1 0 XINT2 flag XINT2 polarity XINT2 priority XINT2 enable Note 2 40 RC 0 R 0 RW 0 RW 0 RW 0 R Read access W Write access C Clear by writing a 1 0 value after reset Bit 15 Bits 14 3 Bit 2 Bit 1 XINT2 Flag This bit indicates whether the selected transition has been detected on the XINT2 pin and is set whether or not the interrupt is enabled This bit is cleared by the appropriate interrupt acknowledge by software writing a 1 writing a 0 has no effect or by a device reset 0 No transition detected 1 Transition detected Reserved Reads return zero writes have no effect XINT2 Polarity This read write bit determines whether interrupts are generated on the rising edge or the falling edge of a signal on the pin 0 Interrupt generated on a falling edge high to low transition 1 Interrupt generated on a rising edge low to high transition XINT2 Priority This read write bit determines which interrupt priority is requested The CPU interrupt priority levels corresponding to low and high priority are coded into the peripheral interrupt expansion controller These priority levels are shown in Table 2 2 240xA Interrupt Source Priority and Vectors in Chapter 2 on page 2 9 0 High priority 1 Low priority External Interrupt Control Registers Bit 0 XINT2 Enable This read write bit enables or disables the external interrupt XINT2 0 Disable interrupt 1 Enable interrupt
162. 20F240x 240xA Boot ROM Loader Protocols and Interfacing D 11 Protocol Definitions File Name BOOT asm Originator Digital Systems Control group Texas Instruments i PRR RRR RRR KKK KK ke he ke e he KR KR he ke KKK ke he he e e he KR ke he he ke e che ke che he ke e he he ke che he ke e che he echec he ke kkk ke che he ke e che ke ke he he ke e e kkk Constant definitions PRR RRR kc ke kc ee ke AK ke he ke e he e K Se he ke KKK ke She he e e he ke ke e he ke e che he che he ke e he ke KERR ke e che kkk he ke e che ke ke ce he ke ce che kkk he ke e ke e e READ COMMAND set 0300H Serial EEPROM Read Command in HByte VBR MAX set 09h times valid char needs to be received CRC MAX set 03h retries at each speed before giving up p RRR kk k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k Debug directives r def GPRO General purpose registers def GPR1 def GPR2 def GPR3 def DEST def LENGTH def data buf def VBR CNTR def DELAY def CHAR RETRY CNTR def BAUD TBL PTR PRR RRR kc ke kc A K ke K K he ke e K ke K K he ke e he he ke he he e e he he kiki e che he che he ke e he he ce he ke e che kkk he ke e he ke che he kkk ke ke ke he kkk ke e Include header file for peripheral address references i PRR RRR KERR kkk KK k k k e k k k k k e e k he k k he k e k k k k he ke e K k k k
163. 218h 7219h 721Ah 721Ch 721Dh 721Eh 721Fh 7220h 7221h 7222h 7224h 7225h 7226h 7227h 7228h 7229h 722Ah 722Ch 722Dh 722Eh 722Fh CAN CAN CAN CAN CAN CAN CAN CAN CAN CAN CAN CAN CAN CAN CAN CAN CAN CAN CAN CAN CAN CSM registers High word of the 64 bit KEY register Message ID for mailbox 3 Message ID for mailbox 3 RTR and DLC 2 2 2 2 Message I of of of of 8 bytes 8 bytes 8 bytes 8 bytes RTR and DLC 2 2 2 2 Message I of of of of 8 bytes 8 bytes 8 bytes 8 bytes RTR and DLC 2 2 2 2 of 8 bytes of 8 bytes of 8 bytes of 8 bytes Data memory of Mailbox of Mailbox of Mailbox of Mailbox D for mailbox 4 Message ID for mailbox 4 of Mailbox of Mailbox of Mailbox of Mailbox D for mailbox 5 Message ID for mailbox 5 of Mailbox of Mailbox of Mailbox of Mailbox Bog am gd WWW UJ U1 Ul Ul wu Third word of the 64 bit KEY register Second word of the 64 bit KEY register Low word of the 64 bit KEY register CSM registers Program memory High word of the 64 bit password Third word of the 64 bit password Second word of the 64 bit password Low word of the 64 bit password I O space mapped registers WSGR FCMR Set OFFFFh Set OFFOFh Program Examples lower upper lower upper lower upper 16 16 16 16 16 16 Wait State Generator Control register Fla
164. 3 low power modes SCSR2 system control and status register 2 2 5 sequencer autoconversion basic operation conversion in dual sequencer mode using SEQ1 block diagram of autosequenced ADC in cascaded mode block diagram of autosequenced ADC with dual sequencers comparison of single and cascaded operating modes input trigger description interrupt operation during sequenced conversion figure Sequencer start stop operation with multiple time sequenced triggers example of event manager triggers to start the sequencer example of sequencer start stop operation sequencer start stop operation with multiple time sequenced triggers with multiple time sequenced triggers uninterrupted autosequenced mode Index serial communication interface SCI 240xA to 240 family compatibility serial communications interface SCI 8 1 architecture asynchronous communication format baud rate calculations asynchronous baud register values for common SCI bit rates C240 SCI vs LF LC240xA SCI communication format receiver signals in communication mode RX signals in communication mode figure transmitter signals in communication mode TX signals in communication mode figure multiprocessor and asynchronous communication modes multiprocessor communication 8 9 address byte address bit multiprocessor mode communication format sending an address block start signal sending a block start signal controlling the SCI TX and
165. 3 compare register Timer 3 Timer 3 period register Timer 3 control register Timer 4 counter register Timer 4 compare register Timer 4 Timer 4 period register Timer 4 control register Table 6 5 Addresses of EVA Compare Control Registers Address Register 7411h COMCONA 7413h ACTRA 7415h DBTCONA 7417h CMPR1 7418h CMPR2 7419h CMPR3 Name Compare control register Compare action control register Dead band timer control register Compare register 1 Compare register 2 Compare register 3 Event Manager EV 6 11 Event Manager EV Register Addresses Table 6 6 Addresses of EVB Compare Control Registers Address 7511h 7513h 7515h 7517h 7518h 7519h Register COMCONB ACTRB DBTCONB CMPR4 CMPR5 CMPR6 Name Compare control register Compare action control register Dead band timer control register Compare register 4 Compare register 5 Compare register 6 Table 6 7 Addresses of EVA Capture Registers Address 7420h 7422h 7423h 7424h 7425h 7427h 7428h 7429h Register CAPCONA CAPFIFOA CAP1FIFO CAP2FIFO CAP3FIFO CAP1FBOT CAP2FBOT CAP3FBOT Name Capture control register Capture FIFO status register Two level deep capture FIFO stack 1 Two level deep capture FIFO stack 2 Two level deep capture FIFO stack 3 Bottom registers of FIFO stacks allows most recent CAPTURE value to be read Table 6 8 Addresses of EVB Capture Registers Address 7520h 7522h 7523h 7524h 7525h 7527h
166. 34 234 234 234 234 EAh 234 234 234 234 234 234 234 234 234 EAh 234 EAh 234 Page 6 33 6 33 6 43 6 46 6 51 6 74 6 77 Table B 2 Code Security Module CSM Registers Data Memory Address 77F0h 77F1h 77F2h 77F3h Program Memory Address 0040h 0041h 0042h 0043h Register Name Reset Values KEY3 KEY2 KEY 1 KEYO PWL3 PWL2 PWL1 PWLO FFFFh FFFFh FFFFh FFFFh 0000 FFFFh or user defined 0000 FFFFh or user defined 0000 FFFFh or user defined 0000 FFFFh or user defined Summary of Programmable Registers on the 240xA Register Description KEY registers Accessible by the user High word of the 64 bit KEY register Third word of the 64 bit KEY register Second word of the 64 bit KEY register Low word of the 64 bit KEY register PWL in program memory Reserved for passwords only High word of the 64 bit password Third word of the 64 bit password Second word of the 64 bit password Low word of the 64 bit password Programmable Register Address Summary B 9 Summary of Programmable Registers on the 240xA B 10 Appendix C Program Examples This appendix provides A brief introduction to the tools used for generating executable COFF files that run on the 240xA devices Sample programs to test some of the peripherals available in the 240xA devices This appendix is not intended to teach you how to use the softwa
167. 40xA devices compared to 240x devices 40 MHz operation as compared to 30 MHz for the 240x family Code security for on chip Flash ROM 1 Input qualifier circuitry for PDPINTx CAPn XINTn and ADCSOC pins Status of the PDPINTx pin is reflected in the COMCONXx register 240x Highlights Su 00S SO SO SOK 89A VA SBA SO M8 ZLS vvS SdlIN 07 su GZ SO VLOUVCOl VcOPcO1 VvOUVCOl V90PZO1 VLOPZ41 VcOUvCd SU Gzy 8 SO SO SOX SO g g 8 9 e VA SOK M9 vvS SdlIN 07 su GZ SO SOA SOA Su GLE su GZE 9L 9L SO SO SO SO SO So SO SO v 9 v 9 9L ZL 9L ZL v v g a 8 3 WAS VA3 SO S9A 9L AZE MI Mc vvS vvS SdlA 07 SdlIN 07 SU GZ su Gc SO SO Su 00S S SO SO SO 89A WA SOK SO M8 ZLS vvS SdlIN 07 SU GZ SOK su g g 8 SO SO SOX SO g g 8 9 VA SO SOX M8 ZLS vvS SdlIN 07 su GZ SOA SOA su SJE 8 SO SO SOK SO g g 8 9 e vag SO SOX 9L ZLS vvS SdlIN 07 su GZ SO veores SO su GE 9L SOA SO SOK SO v 9 9b el v 8 3 A3 SO SOA AZE c vvS SdlIN 07 su GZ SO V90t24 1 V LOPZX 1 01 ejqeordde eq jou Aew suid eulos l S9DIADP XOPZ 01 peeduioo Meu ueJaJip eJe JEU sanea sejouep Bulpeus SO su GZ 9L SO SO SOX SO v 9 9L el v 8 3 VAS SOA SBA S9A AZE c vvS SdlIN 07 su GZ SO
168. 6 is set to zero by software L PDPINTx is pulled low and is not masked L Anyreset event occurs TxCON 1 is set to zero by software Active Inactive Time Calculation For the continuous up counting mode the value in the compare register represents the elapsed time between the beginning of a period and the occurrence of the first compare match length of the inactive phase This elapsed time is equal to the period of the scaled input clock multiplied by the value of TxCMPR Therefore the length of the active phase the output pulse width is given by TxPR TXCMPR 1 cycle of the scaled input clock For the continuous up down counting mode the compare register can have a different value while counting down from the value while counting up The length of the active phase output pulse width for up down counting modes is given by TxPR TXCMPR yp TXPR TxCMPR gn cycles of the scaled input clock where TxCMPR yp is the compare value on the way up and TXCMPR gn is the compare value on the way down Event Manager EV 6 31 General Purpose GP Timers When the value in TXCMPR is zero the GP timer compare output is active for the whole period if the timer is in the up counting mode For the up down counting mode the compare output is active at the beginning of the period if TXCMPH yp is zero The output remains active until the end of the period if TxCMPR gn is also zero The length of the active phase the
169. 6 51 PWM Circuits Associated With Compare Units Bit 5 Bits 4 2 Bits 1 0 EDBT1 Dead band timer 1 enable for pins PWM7 and PWMB8 of Compare Unit 4 0 Disable 1 Enable DBTPS2 to DBTPSO Dead band timer prescaler 000 Xx 001 x2 010 x 4 011 x 8 100 x 16 101 x 32 110 x32 111 x 32 x Device CPU clock frequency Reserved Reads return zero writes have no effect Inputs and Outputs of Dead Band Unit The inputs to the dead band unit are PH1 PH2 and PH3 from the asymmetric symmetric waveform generators of compare units 1 2 and 3 respectively The outputs of the dead band unit are DTPH1 DTPH1 DTPH2 DTPH2 DTPH3 and DTPH3_ corresponding to PH1 PH2 and PH3 respectively Dead Band Generation 6 52 For each input signal PHx two output signals DTPHx and DTPHx are generated When dead band is not enabled for the compare unit and its associated outputs the two signals are exactly the same When the dead band unit is enabled for the compare unit the transition edges of the two signals are separated by a time interval called dead band This time interval is determined by the DBTCONx bits If you assume that the value in DBTCONx 11 8 is m and that the value in DBTCONx 4 2 corresponds to prescaler x p then the dead band value is p m device clock cycles Table 6 13 on page 6 53 shows the dead band generated by typical bit combinations in DBTCONx The values are based on a 25 ns device cloc
170. 7 SPI Operation Figure 9 2 SPI Master Slave Connection SPI master master slave 1 SPI slave master slave 0 Serial i SPI Shift SPIRXBUF 15 0 SPISIMO master out SPISIMO CsBIRXBUE 15 0 Slave in nput buffer Serial input buffer RXBUF SPIRXBUF SPISTE SPISTE SPIDAT 15 0 SPIDAT 15 0 i Slave out i i register re SPISOMI SPISOMI use ift register MSB SPIDAT master in SPIDAT 88 Serial y spicik SPITXBUF 15 0 SPITXBUF 15 0 Serial transmit buffer Serial transmit buffer SPI TXBUF SPITXBUF Processor 1 Processor 2 9 3 2 SPI Module Slave and Master Operation Modes Master Mode The SPI can operate in master or slave mode The MASTER SLAVE bit SPICTL 2 selects the operating mode and the source of the SPICLK signal In the master mode MASTER SLAVE 1 the SPI provides the serial clock on the SPICLK pin for the entire serial communications network Data is output on the SPISIMO pin and latched from the SPISOMI pin The SPIBRR register determines both the transmit and receive bit transfer rate for the network SPIBRR can select 126 different data transfer rates Data written to SPIDAT or SPITXBUF initiates data transmission on the SPISIMO pin MSB most significant bit first Simultaneously received data is shifted through the SPISOMI pin into the LSB least significant bit of SPIDAT When the selected number of bits has been transmitted the received data is tran
171. 704Eh Reserved 704Fh SPIPRI SPI priority control register SPI Operation 9 3 SPI Operation This section describes the operation of the SPI Included are explanations of the operation modes interrupts data format clock sources and initialization Typical timing diagrams for data transfers are given 9 3 1 Introduction to Operation Figure 9 2 shows typical connections of the SPI for communications between two controllers a master and a slave The master initiates data transfer by sending the SPICLK signal For both the slave and the master data is shifted out of the shift registers on one edge of the SPICLK and latched into the shift register on the opposite SPICLK clock edge If the CLOCK PHASE bit SPICTL 3 is high data is transmitted and received a half cycle before the SPICLK transition see section 9 3 2 SPI Module Slave and Master Operation Modes on page 9 8 As a result both controllers send and receive data simultaneously The application software determines whether the data is meaningful or dummy data There are three possible methods for data transmission L Master sends data slave sends dummy data Master sends data slave sends data Lj Master sends dummy data slave sends data The master can initiate data transfer at any time because it controls the SPICLK signal The software however determines how the master detects when the slave is ready to broadcast data Serial Peripheral Interface SPI 9
172. A new char acter must be written to the serial data register Bit 6 CLOCK POLARITY Shift Clock Polarity This bit controls the polarity of the SPICLK signal CLOCK POLARITY and CLOCK PHASE SPICTL 3 control four clocking schemes on the SPICLK pin See Section 9 4 4 SPI Clocking Schemes on page 9 13 0 Data is output on rising edge and input on falling edge When no SPI data is sent SPICLK is at low level The data input and output edges depend on the value of the CLOCK PHASE bit SPICTL 3 as follows CLOCK PHASE 0 Data is output on the rising edge of the SPICLK signal input data is latched on the falling edge of the SPICLK signal CLOCK PHASE 1 Data is output one half cycle before the first rising edge of the SPICLK signal and on subsequent falling edges of the SPICLK signal input data is latched on the rising edge of the SPICLK signal Serial Peripheral Interface SPI 9 19 SPI Module Registers 1 Data is output on falling edge and input on rising edge When no SPI data is sent SPICLK is at high level The data input and output edges depend on the value of the CLOCK PHASE bit SPICTL 3 as follows CLOCK PHASE 0 Data is output on the falling edge of the SPICLK signal input data is latched on the rising edge of the SPICLK signal CLOCK PHASE 1 Data is output one half cycle before the first falling edge of the SPICLK signal and on subsequent rising edges of the SPICLK signal input data is latc
173. AP5INT CAP4INT SS9ive FLAG FLAG FLAG R 0 RW1C 0 RW1C 0 RWIC 0 Note R Read access W1C Write 1 to clear 0 value after reset Bits 15 3 Reserved Reads return zero writes have no effect Bit 2 CAP6INT FLAG Capture 6 interrupt Read 0 Flag is reset 1 Flagis set Write O No effect 1 Resets flag Bit 1 CAPS5INT FLAG Capture 5 interrupt Read 0 Flag is reset 1 Flagis set Write O No effect 1 Resets flag Bit 0 CAPAINT FLAG Capture 4 interrupt Read 0 Flag is reset 1 Flagis set Write O No effect 1 Resets flag Event Manager EV 6 97 Event Manager EV Interrupts EVB Interrupt Mask Register A EVBIMRA Figure 6 48 EVB Interrupt Mask Register A EVBIMRA Address 752Ch 15 11 1 0 9 8 F p T3OFINT T3UFINT T3CINT eserve ENABLE ENABLE ENABLE R 0 RW 0 RW 0 RW 0 7 6 4 3 2 1 0 ENABLE ENABLE ENABLE ENABLE ENABLE RW 0 R 0 RW 0 RW 0 RW 0 RW 1 Note R Read access W Write access n value after reset Bits 15 11 Reserved Reads return zero writes have no effect Bit 10 T3OFINT ENABLE 0 Disable 1 Enable Bit 9 T3UFINT ENABLE 0 Disable 1 Enable Bit 8 T3CINT ENABLE 0 Disable 1 Enable Bit 7 T3PINT ENABLE 0 Disable 1 Enable Bits 6 4 Reserved Reads return zero writes have no effect Bit 3 CMP6INT ENABLE 0 Disable 1 Enable Bit 2 CMP5INT ENABLE 0 Disable 1 Enable Event Manager EV Interrupts Bit 1 CMP4INT ENABLE 0 Disable 1 Enable Bit 0 PDPINTB ENABLE This is enabled set to
174. C240 SCI vs LF LC240xA SCI 8 1 1 8 2 Multiplexing the SCI pins with general purpose l O is controlled by bits in the digital I O peripheral As a consequence the register SCIPC2 705Eh has been removed The CLKENA bit in SCICTL1 7051h has been removed since it served no purpose in 2 pin SCI implementations The function of the SCIENA bit in SCICCR 7050h has changed and is now a LOOP BACK ENA test mode bit The enable function is no longer required for correct operation of the SCI There is no difference with respect to the 241 242 243 SCI functionality however the clock for the SCI must be enabled during peripheral initialization by writing a 1 to bit 6 of the SCSRI register SCI Physical Description The SCI module shown in Figure 8 1 on page 8 4 has the following key features Lj Two l O pins B SCIRXD SCI receive data input B SCITXD SCI transmit data output Programmable bit rates to over 65 000 different speeds through a 16 bit baud select register B Range with 40 MHz CLKOUT 76 bps to 2500 kbps B Number of bit rates 64K Programmable data word length from one to eight bits Programmable number of stop bits one or two Internally generated serial clock LE E E Four error detection flags m Parity error m Overrun error m Framing error u Break detect error C240 SCI vs LF LC240xA SCI Two wake up multiprocessor modes m dile line wake up B Address bit wake up Half o
175. CHSELSEQn 7 5 6 ADC Conversion Result Buffer Registers RESULTn ADC Conversion Clock Cycles nh Describes the architecture functions and programming of the of the Serial Communications Interface SCI module 8 1 C240 SCI vs LF LC240XA SOli sis ccc eee een n eect ee i 8 1 14 SCI Physical Description 0 8 12 Architecture siran irinna dad ad Ba deda Shad E Seperate Sede aaa eee 8 1 3 SCI Module Register Addresses 2 8 1 4 Multiprocessor and Asynchronous Communication Modes Contents 8 2 SCI Programmable Data Format 0 0000 cece eee teens 8 3 SCI Multiprocessor Communication 2 n aana 8 3 1 Idle Line Multiprocessor Mode 0 ccc eee cece eee eee eed 8 3 2 Address Bit Multiprocessor Mode eee e eee eee eee 8 4 SCI Communication Format 0c cece eee ees 8 4 1 Receiver Signals in Communication Modes cece neces 8 4 2 Transmitter Signals in Communication Modes eee ee 85 SCl Port Interrupts 0 0 e n hh 8 6 SCI Baud Rate Calculations ccc teens 8 7 SCl Module Registers omissa ay aaite aniue kakae eee eens 8 7 31 SCI Communication Control Register SCICCR eeuna e nn 8 7 2 SCI Control Register 1 SCICTL1 0 eee 8 7 3 Baud Select Registers SCIHBAUD SCILBAUD nenna 8 7 4 SCI Control Register 2 SCICTL2 0 eee eee 8 7 5 Receiver Status R
176. CITXBUF WUT is loaded from TXWAKE and the TXWAKE bit is cleared to 0 This arrangement is shown in Figure 8 4 Figure 8 1 SCI Block Diagram on page 8 4 shows this in additional detail Figure 8 4 Double Buffered WUT and TXSHF TXWAKE Transmit buffer SCITXBUF 1 TXSHE Note WUT wake up temporary Sending a Block Start Signal To send out a block start signal of exactly one frame time during a sequence of block transmissions 1 Write a 1 to the TXWAKE bit 2 Write a data word content not important a don t care to the SCITXBUF register transmit data buffer to send a block start signal The first data word written is suppressed while the block start signal is sent out and ig nored after that When the TXSHF transmit shift register is free again SCITXBUF s contents are shifted to TXSHF the TXWAKE value is shifted to WUT and then TXWAKE is cleared Because TXWAKE was set to a 1 the start data and parity bits are re placed by an idle period of 11 bits transmitted following the last stop bit of the previous frame 3 Write a new address value to SCITXBUF A don t care data word must first be written to register SCITXBUF so that the TXWAKE bit value can be shifted to WUT After the don t care data word is 8 12 SCI Multiprocessor Communication shifted to the TXSHF register the SCITXBUF and TXWAKE if necessary can be written to again because TXSHF and WUT are both double buffered Receiver Operation
177. CLKINB IOPF5 MCRC 13 0 PFDATDIR 5 13 IOPF6 IOPF6 X X X PFDATDIR 6 14 240xA 24x Family Compatibility 13 13 Event Manager Module EVB 13 6 Event Manager Module EVB Table 13 8 Event Manager Module and Signal Names for EVA and EVB EV Modules GP Timers Compare Units Capture Units QEP External Inputs 13 6 1 Input Qualification Circuitry 13 14 The event manager module available on 240xA devices is identical to the event manager in the 24x family EVA and EVB are exactly identical modules except that their registers start at 7400h and 7500h respectively in the peripheral space The functional description of the event manager available in the TMS320F243 F241 C242 DSP Controllers Reference Guide literature number SPRU27ec is applicable to EVB as well EVA and EVB modules and signals are uniquely identified and in Table 13 8 for comparison EVA Modules Timer 1 Timer 2 Compare 1 Compare 2 Compare 3 Capture 1 Capture 2 Capture 3 QEP 1 QEP 2 Direction External Clock EVA Pins T1PWM T1CMP T2PWM T2CMP PWM1 2 PWM3 4 PWM5 6 CAP1 CAP2 CAPS OEP1 OEP2 TDIRA TCLKINA EVB Modules Timer 3 Timer 4 Compare 4 Compare 5 Compare 6 Capture 4 Capture 5 Capture 6 QEP 3 QEP 4 Direction External Clock EVB Pins T3PWM T3CMP T4PWM T4CMP PWM7 8 PWM9 10 PWM11 12 CAP4 CAP5 CAP6 QEP3 QEP4 TDIRB TCLKINB Some pins in the EV have an input qualification circuitry See the TMS320
178. CONA 2 7 ADC start CAPCONA 15 Cap FIFO status Clear CAPFIFOA 13 15 Event Manager EV 6 69 Capture Units Figure 6 31 Capture Units Block Diagram EVB T4CNT T3CNT GP timer 4 GP timer 3 counter counter CAPCONBI9 10 CAPCONB 12 14 EN Edge detect Capture unit 6 RS cap event CAP4 5 6 Edge 6 CAPCONBJ8 select stacks CAPCONB 2 7 ADC start CAPCONBI15 Cap FIFO status clear GAPFIFOB 13 15 6 8 1 Capture Unit Features Capture units have the following features One 16 bit capture control register CAPCONA for EVA CAPCONB for EVB RW One 16 bit capture FIFO status register CAPFIFOA for EVA CAPFIFOB for EVB Selection of GP timer 1 or 2 for EVA and GP timer 3 or 4 for EVB as the time base 6 70 Capture Units Three 16 bit 2 level deep FIFO stacks one for each capture unit Six Schmitt triggered capture input pins CAP1 through CAP6 one input pin for each capture unit All inputs are synchronized with the device CPU clock in order for a transition to be captured the input must hold at its current level to meet the two rising edges of the device clock In 240xA devices the input must be held for a duration mandated by the input qualifier circuitry Input pins CAP1 and CAP2 CAP4 and CAP5 in EVB can also be used as QEP inputs to QEP circuit _j User specified transition detection rising edge falling edge or both edges
179. CONV1 should be set to 6 and the CHSELSEQn registers should be set to the values shown in the table below Bits 15 12 Bits 11 8 Bits 7 4 Bits 3 0 CHSELSEQ1 CHSELSEQ2 CHSELSEQ3 CHSELSEQ4 Values are in decimal and x don t care Conversion begins once the start of conversion SOC trigger is received by the sequencer The SOC trigger also loads the SEQ CNTR n bits Those channels that are specified in the CHSELSEQ n registers are taken up for conversion in the predetermined sequence The SEQ CNTR n bits are decremented by one automatically after every conversion Once SEQ CNTR n reaches zero two things can happen depending on the status of the continuous run bit CONT RUN in the ADCTRL1 register ADC Overview If CONT RUN is set the conversion sequence starts all over again auto matically i e SEQ CNTR n gets reloaded with the original value in MAX CONV1 and SEQ state is set to CONVOO In this case you must ensure that the result registers are read before the next conversion sequence be gins The arbitration logic designed into the ADC ensures that the result registers are not corrupted should a contention arise ADC module trying to write into the result registers while you try to read from them at the same time Figure 7 3 Flow Chart for Uninterrupted Autosequenced Mode Initialize the ADC registers SCC trigger arrives MAXCONV value gets loaded into AUTO SEO SR register Conversion begins AUTO SEQ S
180. Channel 5 0110 Channel 6 0111 Channel 7 1000 Channel 8 1001 Channel 9 1010 Channel 10 1011 Channel 11 1100 Channel 12 1101 Channel 13 1110 Channel 14 1111 Channel 15 Register Bit Descriptions 7 5 6 ADC Conversion Result Buffer Registers RESULTn Note In the cascaded sequencer mode registers RESULT8 through RESULT15 will hold the results of the ninth through sixteenth conversions Figure 7 14 ADC Conversion Result Buffer Registers RESULTn 15 14 13 12 11 10 9 8 ww ow ow ow ox mT 9 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 NES R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Notes 1 Buffer addresses 70A8h to 70B7h i e 16 registers 2 The 10 bit conversion result D9 D0 is left justified 3 The AUTO SEQ SR register and the RESULTn registers of the 240xA ADC module are Read only Any attempt to write to these registers causes an NMI Analog to Digital Converter ADC 7 37 ADC Conversion Clock Cycles 7 6 ADC Conversion Clock Cycles The conversion time is a function of the number of conversions performed in a given sequence The conversion cycle can be divided into five phases Start of sequence sync up SOS synch The SOS synch applies only to the first conversion in a sequence Acquisition time ACQ Conversion time CONV End of Conversion cycle EOC The ACQ CONV and EOC apply to all conversions in a sequence End of Sequence flag setting cycle EOS The EOS appli
181. DFLAG After a reset the program reads this flag to determine the source of the reset After reset WDFLAG should be cleared by the software to allow the source of subsequent resets to be determined WD resets are not prevented when the flag is set When the WDCNTR overflows the WD timer asserts a system reset Reset occurs one WDCNTR clock cycle either WDCLK or WDCLK divided by a prescale value later The reset cannot be disabled in normal operation as long as WDCLK is present The WD timer is however disabled in the oscillator power down mode when WDCLK is not active For software development or flash programming purposes the WD timer can be disabled by setting the WDDIS bit in the WD control register WDCR 6 Note that there is no WDDIS pin in the 240xA devices The watchdog override bit in the SCSR2 register provides the functionality of the WDDIS pin Watchdog Timer Operations 11 2 4 4 WD Check Bit Logic 11 2 4 5 WD Setup The WD check bits WDCR 5 3 described in detail in section 11 3 3 on page 11 9 are continuously compared to a constant value 1012 If writes to the WD check bits do not match this value a system reset is generated This functions as a logic check in case the software improperly writes to the WDCR or if an external stimulus such as voltage spikes EMI or other disruptive sources corrupt the contents of the WDCR Writing to bits WDCR 5 3 with anything but the correct pattern 1015 generates a system r
182. EEPROM SPISIMO IOPC2 DIN SPISOMI DOUT SPICLK CLK BOOT EN XF CS BOOT EN Boot Flash ROM band O Q mn transceiver SCITXD IOPAO i d SCIRXD PLL multiplier PLL x2 onak PLL multiplier is set to x2 O O 0 O Vpp issetto x4 Note For LF240x devices the bootloader sets the PLL to x4 mode For LF240xA devices the multiplier depends on the state of the IOPAO pin For a list of valid CLKIN frequencies refer to Table D 1 Clock Speeds At Which Baud Rate Locks on page D 8 Introduction Figure D 2 Memory Maps for the LF240xA LF240x Devices in Microcontroller Mode 0000 0000 Bootloader OOFF Reserved 7FFF 8000 SARAM 2K words Program Data 7FFF 87FF 8800 Bootloader enabled BOOT EN XF 0 External off chip FDFF FE00 Reservedt CNF 1 I sek on chip Flasi memory External CNF 0 External if MP MC 1 p Note Flash size varies depending on the On Chip DARAM BO t CNF 1 device LF2407A is depicted as an External CNF 0 example FFFF T When CNF 1 addresses FEO0h FEFFh and FFOOh FFFFh are mapped to the same physical block BO in program memory space For example a write to FEOOh has the same effect as a write to FFOOh For simplicity addresses FEO0h FEFFh are referred to as reserved when CNF 1 Note When boot ROM is enabled on chip locations 0000 00FFh in program memory is mapped to the bootloader Boot ROM and Flash Memory share the same starting address and hence ar
183. EMU SPI receive emulation buffer register Contains the received data This register is used for emulation purposes only The SPIRXBUF should be used for normal operation SPIRXBUF SPI receive buffer the serial receive buffer register Con tains the received data SPITXBUF SPI transmit buffer the serial transmit buffer register Con tains the next character to be transmitted Serial Peripheral Interface SPI 9 5 Overview of SPI Module Registers SPIDAT SPI data register Contains data to be transmitted by the SPI acting as the transmit receive shift register Data written to SPIDAT is shifted out on subsequent SPICLK cycles For every bit shifted out of the SPI a bit from the receive bit stream is shifted into the other end of the shift register SPIPRI SPI priority register Contains bits that specify interrupt priority and determine SPI operation on the XDS emulator during program sus pensions Table 9 1 Addresses of SPI Registers Address Register Name 7040h SPICCR SPI configuration control register 7041h SPICTL SPI operation control register 7042h SPISTS SPI status register 7043h Reserved 7044h SPIBRR SPI baud rate register 7045h Reserved 7046h SPIRXEMU SPI receive emulation buffer register 7047h SPIRXBUF SPI serial receive buffer register 7048h SPITXBUF SPI serial transmit buffer register 7049h SPIDAT SPI serial data register 704Ah Reserved 704Bh Reserved 704Ch Reserved 704Dh Reserved
184. EQ triggers are active Cascaded mode can be viewed as SEQ with 16 states instead of eight 7 2 5 Interrupt Operation During Sequenced Conversions The sequencer can generate interrupts under two operating modes These modes are determined by the Interrupt Mode Enable Control bits in ADCTRL2 A variation of Example 7 2 can be used to show how interrupt mode 1 and mode 2 are useful under different operating conditions Analog to Digital Converter ADC 7 13 ADC Overview 7 14 Case 1 Number of samples in the first and second sequences are not equal E 4 Mode 1 Interrupt operation i e Interrupt request occurs at every EOS Sequencer is initialized with MAX CONVn 1 for converting l4 and lo At ISR a MAX CONVn is changed to 2 by software for converting V4 Vo and V3 At ISR b the following events take place 1 MAX CONVn is changed to 1 again for converting l4 and lo 2 Values l4 lo Vy Vo and V3 are read from ADC result registers 3 The sequencer is reset Steps 2 and 3 are repeated Note that the interrupt flag is set every time SEQ CNTR n reaches zero and both interrupts are recognized Case2 Number of samples in the first and second sequences are equal m Mode 2 Interrupt operation i e Interrupt request occurs at every other EOS Sequencer is initialized with MAX CONVn 2 for converting l4 lo and I4 or V1 Vo and V3 At ISR b and d the following events take place
185. ET end 0E1h OFFO8h PBDATDIR DELAY GPTCONA gt gt 7h 0080h EVAIFRA INTM AR0 01h 01h D_LOOP Peripheral page Set IOPB3 Peripheral page clear period int flag in EVAIFRA Enable all interrupts Gen purpose delay Delay parameters may need to be modified for easy observation Program Examples File name CAP asm Description PROGRAM TO CHECK THE CAPTURE UNITS OF 240X This program checks the Capture units of EVA amp EVB On each EV module the capture units are setup to detect different transitions On EVA CAP1 detects a rising edge CAP2 detects a falling edge and CAP3 detects both edges All capture interrupts are enabled Timers 1 amp 2 provide input signals through external connections and also serve as a time base for these capture units Upon detection the capture interrupt reads the proper CAPFIFO value to ensure that the capture units detected the correct transition The same scheme is implemented on EVB to check CAP4 5 and 6 using Timers 3 and 4 Both Timers count in CONTINUOUS UP mode CAP1 is rising edge detect T1 CMP Active low CAP2 is falling edge detect T1 CMP Active low CAP3 on both edges T2 CMP Active high This program tests the following in EVA CAP1 amp CAP2 using Timer 1 CAP3 using Timer 2 This program tests the following in EVB CAP4 amp CAP5 using Timer 3 CAP6 using Timer 4 COMME
186. FIFOA capture FIFO status register B CAPFIFOB Index 16 capture FIFO status registers capture FIFO status register A CAPFIFOA capture FIFO status register B CAPFIFOB code security module CSM compare action control registers ACTRn compare action control register A ACTRA compare action control register B ACTRB compare control registers COMCONn compare control register A COMCONA compare control register B COMCONB dead band timer control registers DBTCONn dead band timer control register A DBTCONA dead band timer control register B DBTCONB device identification number register DINR 2 8 emulation data buffer register SCIRXEMU error status register ESR EVA capture register addresses EVA compare control register addresses EVA interrupt flag register A EVAIFRA EVA interrupt flag register B EVAIFRB EVA interrupt flag register C EVAIFRC EVA interrupt mask register A EVAIMRA EVA interrupt mask register B EVAIMRB EVA interrupt mask register C EVAIMRC EVA Interrupt register addresses EVA timer register addresses EVB capture register addresses EVB compare control register addresses EVB interrupt flag register A EVBIFRA EVB interrupt flag register B EVBIFRB EVB interrupt flag register C EVBIFRC EVB interrupt mask register A EVBIMRA EVB interrupt mask register B EVBIMRB EVB interrupt mask register C EVBIMRC EVB interrupt register addresses EVB timer register addresses event m
187. Fh LDP 0 LAR ARO 300h LAR AR1 7 MAR ARO LACC AR2 LDP 00E1h SACL PADATDIR SACL PBDATDIR SACL PCDATDIR SACL PEDATDIR SACL PFDATDIR CALL DELAY MAR ARI BANZ LOOP B MAIN LAR AR2 0FFF RPT 0FFh NOP BANZ D_LOOP RET KICK DOG B PHANTOM PBDATDIR PCDATDIR PEDATDIR PFDATDIR Fh Program Examples and forced high ARO points to bit pattern in data memory AR1 is the counter Load bit pattern in accumulator Output the same bit pattern to all the GPIO ports Delay provided in between each pattern Check if all 8 patterns have been output If not continue Resets WD counter Program Examples C 21 Program Examples GPI sm File name O IN a Description PROGRAM TO CHECK GPIO PINS OF 240xA as inputs All GPIO bits are programmed as inputs and the values read from the GPIO pins are written in 60h 61h 62h 63h 64h of Data memory title 240xA GPIO bss GPRO 1 Gen purp reg include 240xA h MACRO Definitions KICK DOG macro Watchdog reset macro LDP 00E0Oh DP gt 7000h 707Fh SPLK 05555h WDKEY SPLK HOAAAAh WDKEY LDP Koh DP gt 0000h 007Fh endm text START LDP Koh Set DP 0 SETC INTM Disable interrupts SETC CNF SPLK 0000h IMR Mask all core interrupts LACC IFR Read Interrupt flags SACL IFR Clear all interrupt flags LDP 00E0Oh E0 224 E0 80 7000 SPLK 006Fh WDCR Disable WD SPLK 0 SCSR1 Put PLL in x4 mode
188. GPIO outputs the pin status can be monitored by reading the I O data register Figure 5 1 Shared Pin Configuration IOP Data Bit Read Write Primary Function Output Section Primary Function Input Section IOP DIR Bit 0 Input 1 Output MUX Control Bit 0 I O Function 1 Primary Function Pulldown Internal Primary Function or I O Pin Digital I O Ports Register Implementation on 240xA Devices Table 5 1 240xA Digital V O Port Control Registers Implementation Address Register Mnemonic Description 7090h MCRA O MUX Control Register A 7092h MCRB O MUX Control Register B 7094h MCRC O MUX Control Register C 7098h PADATDIR I O Port A Data and Direction Register 709Ah PBDATDIR I O Port B Data and Direction Register 709Ch PCDATDIR I O Port C Data and Direction Register 709Eh PDDATDIR I O Port D Data and Direction Register 7095h PEDATDIR I O Port E Data and Direction Register 7096h PFDATDIR I O Port F Data and Direction Register Digital Input Output I O 5 3 Differences in GPIO Implementation in the 240xA I O Mux Control Registers 5 2 Differences in GPIO Implementation in the 240xA There are several differences in the 240xA GPIO implementation when compared with the 241 242 243 In the 240xA devices when the bit value in an MCRx register OCRx regis ter in 24x is one the primary function is always chosen Likewise when the bit value is zero
189. I O 5 7 Data and Direction Control Registers 5 4 Data and Direction Control Registers There are six data and direction control registers Refer to Table 5 1 240xA Digital O Port Control Registers Implementation on page 5 3 for the address locations of each register Figure 5 5 Port A Data and Direction Control Register PADATDIR 11 1 15 14 18 12 0 9 8 A7DIR A6DIR ASDIR A4DIR ASDIR A2DIR A1DIR AODIR RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW The reset value of these bits depends upon the state of the respective pins Note R Read access W Write access 0 value after reset Bits 15 8 AnDIR 0 Configure corresponding pin as an input 1 Configure corresponding pin as an output Bits 7 0 IOPAn If AnDIR 0 then 0 Corresponding I O pin is read as a low 1 Corresponding I O pin is read as a high If AnDIR 1 then 0 Set corresponding I O pin low 1 Set corresponding I O pin high Data and Direction Control Registers Table 5 5 PADATDIR VO Pin Designation Assuming Pins Have Been Selected as I O i e Secondary Function VO Port Data Bit Pin Name IOPAO SCITXD IOPAO IOPA1 SCIRXD IOPA1 IOPA2 XINT1 IOPA2T IOPA3 CAP1 QEP1 IOPA3 IOPA4 CAP2 QEP2 IOPA4 IOPA5 CAP3 IOPA5 IOPA6 CMP1 IOPA6 IOPA7 CMP2 IOPA7 T There is no IOPA2 pin on 2402A devices Figure 5 6 Port B Data and Direction Control Register PBDATDIR 15 14 13 12 11 10 9 8 RW 0
190. I synchronous transfer protocol and data formats SPI data packet definition TMS320F240x 240xA protocols and interfacing calibration ADC analog to digital converter CALIBRATION register ADC analog to digital con verter CALU central arithmetic logic unit definition CAN controller area network abort acknowledge for mailbox n AAn acceptance filter architecture bit configuration register 1 BCR1 bit configuration register 2 BCR2 bit configuration registers BCRn block diagram CAN bit timing examples CAN error counter register CEC 10 34 CAN initialization diagram 10 39 CAN interrupt flag register CAN IFR 10 36 CAN interrupt mask register CAN IMR 10 38 CAN notation table CAN protocol overview data remote error and overload frames configuration mode control registers error status register ESR global status register GSR 10 32 interrupt logic 10 35 introduction local acceptance mask LAM local acceptance mask register n 0 1 high word LAMn H local acceptance mask register n 0 1 low word LAMn L mailbox addresses mailbox configuration details table mailbox configurations mailbox direction enable register MDER mailbox layout mailbox RAM mailbox RAM layout mailboxes receive 10 13 transmit master control register MCR memory map message buffers message control field MSGCTRLn 10 11 message identifier for high word mailbo
191. IOPC 0 7 Port D 0 IOPD 0 Port E 0 7 IOPE 0 7 Port F 0 6 IOPF 0 6 TRST TDO TDI TMS TCK EMUO EMU1 PDPINTB CAP4 QEP3 IOPE7 CAP5 QEP4 IOPFO CAP6 IOPF1 PWM7 IOPE1 PWMB8 IOPE2 PWM9 IOPE3 PWM10 IOPE4 PWM11 IOPES PWM12 IOPE6 T3PWM T3CMP IOPF2 T4PWM T4CMP IOPF3 TDIRB IOPF4 TCLKINB IOPF5 Indicates optional modules The memory size and peripheral selection of these modules change for different 240xA devices See Table 1 1 for device specific details For a device overview figure of the 2401A device see TMS320LF2401A TMS320LC2401A DSP Controllers Data Sheet literature number SPRS161 1 9 This page intentionally left blank Chapter 2 System Configuration and Interrupts This chapter describes the system configuration registers and interrupts associated with the 240xA devices It also explains how the peripheral interrupt expansion PIE is used to increase interrupt request capacity Topic Page 2 1 Architecture Summary 7 15 rere Emme ux I sss 22 Configuration Registers eer EIER 2 3 Interrupt Priority and Vectors eese 2 4 Peripheral Interrupt Expansion PIE Controller 2 5 MEVA E CE ECOEEECECEEPECC DE CETT 2 6 Interrupt Operation Sequence uuuuue 2 7 Interrupt Eatency 7 50 09 veo esie EEE EEE eee ana E E 28 Sample ISR Gode
192. Illegal Stores data bits to be transmitted by the SCI Illegal Illegal Illegal Illegal Illegal Contains the receiver and transmit ter interrupt priority select bits and the emulator suspend enable bits Described In Section Page 8 7 1 8 21 8 7 2 8 23 8 7 3 8 26 8 7 3 8 26 8 7 4 8 27 8 7 5 8 28 8 7 6 1 8 30 8 7 6 2 8 31 8 7 7 8 31 8 7 8 8 32 C240 SCI vs LF LC240xA SCI 8 1 4 Multiprocessor and Asynchronous Communication Modes The SCI has two multiprocessor protocols the id e line multiprocessor mode see section 8 3 1 on page 8 10 and the address bit multiprocessor mode see section 8 3 2 on page 8 13 These protocols allow efficient data transfer between multiple processors The SCI offers the universal asynchronous receiver transmitter UART communications mode for interfacing with many popular peripherals The asynchronous mode see section 8 4 on page 8 15 requires two lines to interface with many standard devices such as terminals and printers that use RS 232 C formats Data transmission characteristics include One start bit One to eight data bits An even odd parity bit or no parity bit One or two stop bits D LC D Serial Communications Interface SCI 8 7 SCI Programmable Data Format 8 2 SCI Programmable Data Format SCI data both receive and transmit is in NRZ non return to zero format The NRZ data format shown in Figure 8 2 consists of g One start bit One to eight data bits An
193. KKK KKK KK KK KK KKK ke ke ke KK KKK KKK KK k k k k k k k k k k k kc kc k k k k k k k k k k k k k k k k k k k k k k k k ck k k p EK K k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k i The rest of the implementation is the asynchronous serial port loader PRR RRR KERR kc e ke KK he he ke e he KR KERR KKK ke he he e e he KR e he he ke e che KKK he ke e he he KER he ke e KKK RRR e che ke che he kkk kkk kk e e kkk Initialization PRR RRR kc K ke ce k ke e k ke ke k k e e k he k k k ke e k k ke K he ke e k he k K k ke e k he AK K he k k k he k K k ke e k k k k he k e k he e k k ke e k k k k SCI LOADER UART INIT p RRR RRR KEK KKK KKK KK KKK KKK KK KK KK KK k k k k k k k k k k k k k k k k k k k k k kc kc k k k k k k k k k k k k k ck k k ck ck k k ck KK SCI Initialization PRR RRR K K kkk kk k he ke e k ke k k k e e k k k K k ke e k k K k he k k K he K k k ke k k he k k he k k k k k k k k e k k k k k k k k k k k k k e k k KK SCI INIT LDP MCRA gt gt 7 LACC MCRA Set up pins as SCI pins OR 0003H SACL MCRA LDP SCICCR gt gt 7 1 stop bit no parity 8bits ch SPLK 0007h SCICCR async mode idle line protocol LACK 0 SACL SCICTL2 Disable RX Int TX Int SACL SCIHBAUD SACL SCIPRI D 16 Protocol Definitions PRR RRR RK k k k KR k k k RK KK k k KK k k KK KK k k k k KK k k k k KK k k k ck ck kck ck ck kck ck k ck ck ck ck k k k ck ck ck ck k ck
194. LDP LAC SACI CLR RET LDP SPL LDP LAC SAC CLR RET LDP SPL CALI LDP LAC SACI CLR CALI CALI K Li C Li C K Li C Li C K Li C Li 0000011110000000b 1 0 0000000000000010b INTM wait PIVR gt gt 7h PIVR 002ah i SISR2a eq PIVR 0029h i SISR29 eq PIVR 0028h i SISR28 eq PIVR 0027h i SISR27 eq O0OE1h OFFO1h PBDATDIR DELAY GPTCONA gt gt 7h i 0400h i EVAIFRA i INTM i OE1h i OFFO2h PBDATDIR DELAY GPTCONA gt gt 7h 0200h i EVAIFRA INTM n OE1h i OFFO4h PBDATDIR DELAY GPTCONA gt gt 7h i 0100h H EVAIFRA A INTM H Program Examples EVAIFRA clear interrupts IMR Enable INT2 main loop Int2 GISR Peripheral page PIVR value T1 overflow T1 underflow T1 Compare T1 Period Peripheral page Set IOPBO Peripheral page clear overflow int flag in EVAIFRA Enable all interrupts Peripheral page Set IOPB1 Peripheral page clear underflow int flag in EVAIFRA Enable all interrupts Peripheral page Set IOPB2 Peripheral page clear compare int flag in EVAIFRA Enable all interrupts Program Examples C 31 Program Examples SISR27 DELAY D LOOP GISRI1 GISR3 GISR4 GISR5 GISR6 PHANTOM C 32 RET LDP SPLK CALL LDP LACC SACL CLRC RET LAR RPT NOP BANZ RET RET RET RET RET RET R
195. LE ENABLE ENABLE RW 0 R 0 RW 0 RW 0 RW 0 RW 1 Note R Read access W write access value following dash value after reset Bits 15 11 Reserved Reads return zero writes have no effect Bit 10 T1OFINT ENABLE 0 Disable 1 Enable Bit 9 T1UFINT ENABLE 0 Disable 1 Enable Bit 8 T1CINT ENABLE 0 Disable 1 Enable Bit 7 T1PINT ENABLE 0 Disable 1 Enable Bits 6 4 Reserved Reads return zero writes have no effect Bit 3 CMP3INT ENABLE 0 Disable 1 Enable Bit 2 CMP2INT ENABLE 0 Disable 1 Enable Event Manager EV 6 91 Event Manager EV Interrupts Bit 1 CMP1INT ENABLE 0 Disable 1 Enable Bit 0 PDPINTA ENABLE This is enabled set to 1 following reset 0 Disable 1 Enable EVA Interrupt Mask Register B EVAIMRB Figure 6 43 EVA Interrupt Mask Register B EVAIMRB Address 742Dh 15 4 3 2 1 0 i T2OFINT T2UFINT T2CINT T2PINT ESENE ENABLE ENABLE ENABLE ENABLE R 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bits 15 4 Reserved Reads return zero writes have no effect Bit 3 T2OFINT ENABLE 0 Disable 1 Enable Bit 2 T2UFINT ENABLE 0 Disable 1 Enable Bit 1 T2CINT ENABLE 0 Disable 1 Enable Bit 0 T2PINT ENABLE 0 Disable 1 Enable 6 92 Event Manager EV Interrupts EVA Interrupt Mask Register C EVAIMRC Figure 6 44 EVA Interrupt Mask Register C EVAIMRC Address 742Eh 15 3 2 1 2 E d CAP3INT CAP2INT CAP1INT eserve ENABLE ENABLE ENABLE
196. LF2407A TMS320LF2406A TMS320LF2403A TMS320LF2402A TMS320LC2406A TMS320LC2404A TMS320LC2402A DSP Controllers Data Sheet literature number SPRS145 for more details 240xA 24x Family Compatibility 13 15 Appendix A Revision History This document was revised to SPRU357C from SPRU357B The scope of the revisions was limited to adding technical changes as described on the next page A 1 Changes Made in This Revision A 1 Changes Made in This Revision Page lt A o e my m oV m m n e amp el e e 5 Sy Z ol INT INT IN o 3l o P A a ol P IN o eI A A Ny IN 00 o jd gt T M The following changes were made in this revision Additions Modifications Deletions Updated Related Documentation section Added Trademarks Modified the bullets in Section 1 3 Added LF2401A and LC2401A to Table 1 1 Added note to Figure 1 1 Modified last sentence in the second paragraph of Section 2 1 Changed the description of Bit 0 of SCSR1 Register Changed the description of Bit 5 of SCSR2 Register Changed the description of Bits 3 0 in DINR Register Added new data to Section 2 5 3 Nonmaskable Interrupt NMI Modified first paragraph in Section 3 11 2 Modified Table 4 1 in the Exit Condiiton column Replaced Figure 5 1 Shared Pin Configuration Changed secondary pin function of Bit 14 IOPF6 in the MCRC Register to reserved Add
197. LIF in the CAN IFR register is also set This may initiate an interrupt if the RMLIM bit in the CAN MR register is set 10 22 CAN Control Registers Bits 7 4 RMPn Received Message Pending for mailbox n If a received message is stored in mailbox n the RMPn bit is set The RMP bits can only be reset by the CPU and are set by the CAN internal logic The RMPn and RML n bits are cleared by writing a 1 to the RMPn bit at the corresponding bit location If the CPU tries to reset a bit and the CAN tries to set the bit at the same time the bit is set A new incoming message will overwrite the stored one if the OPCn bit is cleared If not the next mailboxes are checked for a matching identifier When the old message is overwritten the corresponding status bit RMLn is set The RMP bits in the RCR register set the mailbox interrupt flag MIFx bit in the CAN IFR register if the corresponding interrupt mask bit in the CAN IMR register is set The MIFx flag initiates a mailbox interrupt if enabled Bits 3 0 OPCn Overwrite Protection Control for mailbox n If there is an overflow condition for mailbox n the new message is stored ignored depending on the OPCn value If the corresponding OPCn bit is set to 1 the old message is protected against being overwritten by the new message Thus the next mailboxes are checked for a matching identifier If no other mailbox is found the message is lost without further notification If OPCn bit is not
198. LKIN combinations listed in Table D 1 Clock Speeds at Which Baud Rate Locks on page D 8 A flowchart of the baud rate match protocol is shown in Figure D 4 Flowchart for the Serial Loader Baud Rate Match Algorithm on page D 9 TMS320F240x 240xA Boot ROM Loader Protocols and Interfacing D 7 Protocol Definitions Table D 1 Clock Speeds at Which Baud Rate Locks D 2 2 2 Data Transfer CLKIN MHz CLKIN MHz CLKOUT MHz PLL x4 PLL x2 40t 10t 20t 36t gt 18t 32t gt 16t 30 7 5 15t 28 7 14t 24 6 12t 20 5 10t 16 4 st Note that these clocking options are valid only on the LF240xA i e not available on the LF240x Once the communications are synchronized the actual data transfer is commenced The first two bytes fetched are interpreted as the destination The next two bytes fetched are the length Once the destination is known a check is performed to see if the destination lies within BO If it does then the bootloader will switch the block BO into program memory and transfer code into Bo After this the user code is transferred to the destination and then a branch is executed to the first address of the code So as is the case with the SPI the entry point of the code must be at the first location for the SCI D 2 2 3 SCI Data Transfer Completion A noteworthy point is the completion of transmission of the SCI data echo There can be a character still in transmission when the control is transferred to the user code So i
199. Lo byte SACL SCITXBUF Echo byte back AND 0FFh Clear upper byte FSW1 CALL RESET WD BIT SCIRXST BIT6 Test RXRDY bit BCND FSW1 NTC If RXRDY 0 then repeat loop NOP ADD SCIRXBUF 8 Concatenate Hi byte to Lo SFL used because 7 is max in SACH SACH SCITXBUF 7 Echo byte back after SFL 8 POINT B1 SFR restore ACC as before SACL data buf Save received word LACC stko RET p EEK K k k k k k k k k k k k k k k k k k k k k k k k k k k KKK KK k k k KR k k k k k k kck k k k k k k k k k k kck ck ck ckck ck ck k k ck k k k k k k k k Check the destination address and switch BO into program space if needed p EKK k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ckck k k k k k CHECK DEST BCND SETC CHK DST EXIT LACC HOFEOOH OFEOOh OFFFFH CHK DST EXIT NEO CNF RET DEST Anywhere in BO means flip BO use both pri amp sec BO ranges mask bits in Acc High PRR RRR RK RRR KR k k k k k k k RK k k k k k k k k k kck kck kck kck kck kck ck ck kck kck kck ck ck k ck kck kc k ck ck kc kckck ck ck ck ck ck ck k k k k KEK Reset WD RET SPLK SPLK 05555h WDKEY HOAAAAh WDKEY p RRR RRR KR KKK k k k k k k k k k k k k k k k k k k k k KK KK k k k k k k k k k k ck k k ck ck k k ck ck kck ck ck k k ck ck k k ck k ck ck ck ck ck ck k k ck k k TMS320F240x 240xA Boot ROM Loader Protocols and Interfacing D 19 Protocol Definitions p RRR
200. MCR 12 is set Access is granted after reset or when the CAN module reaches the idle state This bit is set after a latency of 1 clock cycle up to the length of one frame Bit 3 PDA Power Down Mode Acknowledge Before the CPU enters its IDLE mode to potentially shut off ALL device clocks it must request a CAN power down by writing to the PDR bit in MCR The CPU must then poll the PDA bit and enter IDLE only after PDA is set 0 Normal operation 1 The CAN peripheral has entered the power down mode This bit is set after a latency of 1 clock cycle up to the length of one frame Bit 2 Reserved Bit 1 RM The CAN module is in the Receive Mode This bit reflects what the CBM is actually doing regardless of mailbox configuration 0 The CAN core module is not receiving a message 1 The CAN core module is receiving a message 10 32 Status Registers Bit 0 TM The CAN module is in the Transmit Mode This bit reflects what the CBM is actually doing regardless of mailbox configuration 0 The CAN core module is not transmitting a message 1 The CAN core module is transmitting a message CAN Controller Module 10 33 Status Registers 10 5 3 CAN Error Counter Register CEC The CAN module contains two error counters the receive error counter REC and the transmit error counter TEC The values of both counters can be read from the CEC register via the CPU interface Figure 10 20 illustrates the CEC Figure 10 20 CAN Error C
201. MS320LF2403A TMS320LF2402A TMS320LC2406A TMS320LC2404A TMS320LC2402A DSP Controllers Data Sheet literature number SPRS145 for clock circuits and recommended values for the external filter components Table 13 4 240xA PLL Pin Names Pin Names Description Oscillator input crystal and ceramic resonator input or XTAL1 CLKIN external clock input XTAL2 Used only by crystal or ceramic resonators as an output PLLF PLL loop filter terminal 1 PLLVcCA PLL supply 3 3 V PLLF2 PLL loop filter terminal 2 Table 13 5 Oscillator PLL Frequency Input Specification Value Input crystal frequency range 4 20 MHz Input ceramic resonator frequency range 4 13 MHz Input oscillator CLOCKIN frequency range 4 20 MHz 13 6 System Features 13 4 2 Watchdog Clock Watchdog clock generation logic is different in 240xA devices with respect to 24x devices Unlike the fixed PLL x4 in 24x the 240xA devices have a variable clock from the PLL This changes the input clock options for the watchdog module The clock flow diagram below explains the watchdog clock generation logic 240xA devices have a watchdog override bit in the SCSR2 register which is similar to the WDDIS pin available on the 24x devices Refer to the description of SCSR2 register bit 5 section 2 2 1 on page 2 3 for details on this bit function Figure 13 2 240xA Watchdog Clock Generation Logic Oscillator clock External clock 3 bit ratio selector 13 4 2 1 Other Lo
202. NA B that has a maximum frequency of one fourth that of the device clock 6 16 LI LJ General Purpose GP Timers Direction input TDIRA B for use by the GP timers in directional up down counting mode Reset signal RESET When a timer is used with the QEP circuit the QEP circuit generates both the timer s clock and the counting direction GP Timer Outputs The outputs of the timers are m E E LJ GP timer compare outputs TXCMP x 2 1 2 3 4 ADC start of conversion signal to ADC module Underflow overflow compare match and period match signals to its own compare logic and to the compare units Counting direction indication bits Individual GP Timer Control Register TxCON The operational mode of a timer is controlled by its individual control register TxCON Bits in the TxCON register determine m m D ovo O Which of the four counting modes the timer is in Whether an internal or external clock is to be used by the GP timer Which of the eight input clock prescale factors ranging from 1 to 1 128 is used On which condition the timer compare register is reloaded Whether the timer is enabled or disabled Whether the timer compare operation is enabled or disabled Which period register is used by timer 2 its own or timer 1 s period register EVA Which period register is used by timer 4 its own or timer 3 s period register EVB Overall GP Timer Control Register GPTCONA B The
203. NABLE bit 1 Use TENABLE bit of T1CON in case of EVA or T3CON in case of EVB to enable and disable operation ignoring own TENABLE bit TENABLE Timer enable 0 Disable timer operation the timer is put in hold and the prescaler counter is reset 1 Enable timer operations TCLKS1 TCLKSO Clock Source Select 5 4 Source 0 0 Internal 0 1 External 1 0 Reserved i 4 QEP Circuitt in case of Timer 2 Timer 4 Reserved in case of Timer 1 Timer 3 t This option is valid only if SELT1PR 0 TCLD1 TCLDO Timer Compare Register Reload Condition 00 When counter is 0 01 When counter value is 0 or equals period register value 10 Immediately 11 Reserved TECMPR Timer compare enable 0 Disable timer compare operation 1 Enable timer compare operation SELT1PR In the case of EVA this bit is SELT1PR Period register select When set to1 in T2CON the period register of Timer 1 is chosen for Timer 2 also ignoring the period register of Timer 2 This bit is a reserved bit in T1 CON SELT3PR In the case of EVB this bit is SELT3PR Period register select When set to1 in T4CON the period register of Timer 3 is chosen for Timer 4 also ignoring the period register of Timer 4 This bit is a reserved bit in T3CON 0 Use own period register 1 Use T1PR in case of EVA or T3PR in case of EVB as period register ignoring own period register General Purpose GP Timers Overall GP Timer Control RegisterA GPTCONA Figure 6 13 GP Timer Co
204. NTS Connect T1CMP to CAP1 2 T2CMP to CAP3 inputs Connect T3CMP to CAP4 5 T4CMP to CAP6 inputs PERIPHERAL CODE 5 EVA and 6 EVB TEST CODE CAP 1 2 3 4 5 6 1 2 3 1 2 3 respectively title EV capture test Title include 240xA h Variable and register declaration include vector h Vector label declaration del set Offfh define delay text START LDP Koh set DP 0 SETC INTM Disable interrupts SPLK 0000h IMR Mask all core interrupts LACC IFR Read Interrupt flags SACL IFR Clear all interrupt flags LDP WDKEY gt gt 7h Peripheral page SPLK 006Fh WDCR Disable WD if VCCP 5V LDP SCSR1 gt gt 7 SPLK 000Ch SCSR1 EVA amp EVB modules clock enable LDP EVAIMRA gt gt 7 Peripheral page SPLK HOFFFFh EVAIFRA Clear all EVA interrupt flags SPLK HOFFFFh EVAIFRB SPLK OFFFFh EVAIFRC Program Examples C 33 Program Examples C 34 LDP EVBIMRA gt gt 7 Peripheral page SPLK OFFFFh EVBIFRA Clear all EVB interrupt flags SPLK OFFFFh EVBIFRB SPLK OFFFFh EVBIFRC LAR AR7 del Load AR7 with delay value MAR ART Set ARP to ar7 LDP 0E1h Peripheral page SPLK 1111111111111111b MCRA enable all EV signals SPLK 1111111111111111b MCRC enable all EV signals I Za a a ee eS EVA Capture test This portion of the code tests the EVA Capture unit It is assumed that the test is failed unless an interrupt is called error code 4 GISR4 veri
205. NVO 2 l3 are performed SEQ1 then waits at current state for another trigger Twenty five microseconds later when the second trigger arrives another three conversions occur with channel select values of CONVOS V4 CONV04 Va and CONVOS V3 The value of MAX CONV 1 is automatically loaded into SEQ CNTR n for both trigger cases If a different number of conversions are required at the second trigger point you must at some appropriate time before the second trigger change the value of MAX CONV1 through software otherwise the current originally loaded value will be reused This can be done by an ISR that changes the value of MAX CONV1 at the appropriate time The interrupt operation modes are described in section 7 2 5 Interrupt Operation During Sequenced Conversions on page 7 13 Analog to Digital Converter ADC 7 11 ADC Overview At the end of the second autoconversion session the ADC result registers will have the following values Buffer Register ADC conversion result buffer RESULTO l4 RESULT1 lo RESULT2 l3 RESULT3 V4 RESULT4 Vo RESULT5 V3 RESULT6 X RESULT7 x RESULT8 X RESULT9 X RESULT10 X RESULT11 x RESULT12 X RESULT13 X RESULT14 x RESULT15 X At this point SEQ1 keeps waiting at the current state for another trigger Now the user can reset SEQ1 by software to state CONVOO and repeat the same trigger1 2 sessions ADC Overview 7 2 4 Input Trigger Description Each sequencer has a set of trigger
206. O pins AND 0001H Mask out all bits except IOPAO BCND PLL MULT 4 NEQ If the pin is high multiply by 4 backward compatible else continue with PLL MULT 2 PLL MULT 2 LDP SCSR1 gt gt 7 SPLK 0260h SCSR1 B SELECT LOADER PLL MULT 4 LDP SCSR1 gt gt 7 SPLK 0060h SCSR1 H SELECT LOADER LDP PCDATDIR gt gt 7 SPLK 0000H PCDATDIR Config all as i ps SPI pins MUST be I Os by default at reset controlled by MCRB LACC PCDATDIR AND 0004H Mask for check on SPISIMO BCND SCI LOADER EQ if SPISIMO is low branch to SCI load else SPI loader and set SPISTE high SETC XF Drive CS XF High p RRR RRR k k k RK k k k k k KR KR KK KKK KK RK KK RK KK RK KK RK KK k k k k k k k k k k k k k k k kck kc kc kck kc k k k ck ck ck ck ck ck KEK SPI Initialization PRR RRR k k k ke ck ke ke K he ke k K ke ke e he ke k e he ke e he ke k k he ke e he ke e k he ke e he ke k KK ke k he k k k he k k he he che he ke e he k k k he ke e he k e ke ke k k SPI INIT LACC MCRB Set up the SPI pins to primary functions OR 001CH SACL MCRB LDP HSPICCR gt gt 7 SPLK 0007h SPICCR 8 char bits SPLK 000Eh SPICTL Enable master mode and enable talk TMS320F240x 240xA Boot ROM Loader Protocols and Interfacing D 13 Protocol Definitions SPLK 007 h SPIBRR SPI Speed ASAP as slow as possible SPLK 0087h SPICCR Relinquish SPI from Reset p RR RR KKK RK KKK KKK KK KKK KKK KKK KKK KK KKK k k k k k k k k k k k k k k k
207. OAAAAh WDKEY LDP 0h endm MAIN CODE starts here text START KICK DOG Reset Watchdog counter SPLK 0 60h OUT 60h WSGR Set waitstates for external memory if used SETC INTM Disable interrupts SPLK 0000h IMR Mask all core interrupts LDP 0EOh SPLK 006Fh WDCR Disable WD SPLK 0010h SCSR1 Enable clock to CAN module For 240xA only LDP 225 SPLK 00COH MCRB Configure CAN pins LDP DP_CAN SPLK 1011111111111111b CANIMR Enable all CAN interrupts y EK k k k k ke de ke ke de k ke ke ke ke ke ke ke ke ke ke ke ke ke de ke de ke e ke ke e ke ke e k ke ke k ke ke ke ke ke ke ke ke ke ke k k ke k k ke k k k k k k k k k k k k k k k k k k je Re DISABLE MBX BEFORE WRITING TO MSGID MSGCTRL OF MBX3 s y EK k k k k ke de k ke ke k ke ke ke ke ke ke ke ke ke de ke ke ke ke ke ke ke ke ke ke ke ke ke de k ke ke k ke ke k ke ke ke ke ke ke ke k k ke k k ke k k k k k k k k k k k k k k k k k k SPLK 0000000000000000b CANMDER IVETE FEDCBA9876543210 y EK k k k ke ke de ke ke de k ke de k ke ke ke ke de e de ke ke de ke e de ke de ke ke de ke ke ke ke ke de ke ke ke ke ke ke ke ke ke ke ke ke k ke ke k ke k k k k k k k k k k k k k k k k k k zkk k k k k Write CAN Mailboxes KR KKK KK ke ke OI I I RRR RRR RRR I IO IO IO IO IO IO IO IO IO IO IO I IO IO IO IOI IIR IR IR Ik ke Program Examples C 27 Program Examples LDP DP_CAN2 SPLK 1001111111111111b CANMSGID3H HITTITE EEE i FEDCBA9876543210
208. PDA is set 0 The power down mode is not requested normal operation 1 The power down mode is requested Bit 10 DBO Data Byte Order 0 The data is received or transmitted in the following order Data byte 3 2 1 0 7 6 5 4 1 The data is received or transmitted in the following order Data byte 0 1 2 3 4 5 6 7 z Qo 0 9 9 as Mn S Sa 4a Note The DBO bit is used to define the order in which the data bytes are stored in the mailbox when received and in which the data bytes are transmitted Byte 0 is the first byte in the message and Byte 7 is the last one as shown in the figure of the CAN message Figure 10 4 nd Bit 9 WUBA Wake Up on Bus Activity 0 The module leaves the power down mode only after the user writes a 0 to clear PDR 1 The module leaves the power down mode upon detecting any dominant value on the CAN bus 10 24 Bit 8 Bit 7 Bit 6 Bits 5 2 Bits 1 0 CAN Control Registers CDR Change Data Field Request The CDR bit is applicable for mailboxes 2 and 3 only and in the following situation 1 either or both of these mailboxes are configured for transmission and 2 the corresponding AAM bit MSGIDxH 13 is set 0 1 The CPU requests normal operation The CPU requests write access to the data field of the mailbox in MBNR also located in MCR The CDR bit must be cleared by the CPU after accessing the mailbox The CAN module does not transmit the mailbox if
209. PIDAT and SPITXBUF L Data read back from SPIRXBUF is right justified _ SPIRXBUF contains the most recently received character right justified plus any bits that remain from previous transmission s that have been shifted to the left shown in Example 9 1 Serial Peripheral Interface SPI 9 11 SPI Interrupts Example 9 1 Transmission of Bit from SPIRXBUF Conditions 1 Transmission character length 1 bit specified in bits SPICCR 3 0 2 The current value of SPIDAT 737Bh SPIDAT before transmission SPIDAT after transmission lt RXed esce ED ERES E EA EH E E EE SPIRXBUF after transmission Note x 1if SPISOMI data is high x 0 if SPISOMI data is low master mode is assumed 9 4 3 Baud Rate and Clocking Schemes The SPI module supports 125 different baud rates and four different clock schemes Depending on whether the SPI clock is in slave or master mode the SPICLK pin can receive an external SPI clock signal or provide the SPI clock signal respectively Lj Inthe slave mode the SPI clock is received on the SPICLK pin from the external source and can be no greater than the CLKOUT frequency divided by 4 In the master mode the SPI clock is generated by the SPI and is output on the SPICLK pin and can be no greater than the CLKOUT frequency divided by 4 Baud Rate Determination Equation 9 1 shows how to determine the SPI baud rates Equation 9 1 SPI Baud Rate Calculations
210. PRIORITY SCIPRI 5 and SCITX PRIORITY SCIPRI 6 control bits When both RX and TX interrupt requests are made at the same priority level the receiver always has higher priority than the transmitter reducing the possibility of receiver overrun The operation of peripheral interrupts is described in the Peripheral Interrupt Expansion controller chapter of the device specification of which this SCI chapter is a part If the RX BK INT ENA bit SCICTL2 1 is set the receiver peripheral inter rupt request is asserted when one of the following events occurs m The SCI receives a complete frame and transfers the data in the RXSHF register to the SCIRXBUF register This action sets the RXRDY flag SCIRXST 6 and initiates an interrupt m A break detect condition occurs the SCIRXD is low for ten bit periods following a missing stop bit This action sets the BRKDT flag bit SCIRXST 5 and initiates an interrupt Ifthe TX INT ENA bit SCICTL2 0 is set the transmitter peripheral inter rupt request is asserted whenever the data in the SCITXBUF register is transferred to the TXSHF register indicating that the CPU can write to SCITXBUF this action sets the TXRDY flag bit SCICTL2 7 and initiates an interrupt Note Interrupt generation due to the RXRDY and BRKDT bits is controlled by the RX BK INT ENA bit SCICTL2 1 Interrupt generation due to the RX ERROR bit is controlled by the RX ERR INT ENA bit SCICTL1 6 I SCI Baud Ra
211. Q 1 3 T2OFINT Timer 2 overflow interrupt INT3 IRQ 1 4 CAP1INT Capture 1 interrupt INT4 IRQ 1 5 CAP2INT Capture 2 interrupt INT4 IRQ 1 6 CAPSINT Capture 3 interrupt INT4 IRQ 1 7 SPIINT SPI interrupt Low priority INT5 IRQ 1 8 RXINT SCI receiver interrupt Low priority INT5 IRQ 1 9 TXINT SCI transmitter interrupt Low priority INT5 IRQ 1 10 CANMBINT CAN mailbox interrupt Low priority INT5 IRQ 1 11 CANERINT CAN error interrupt Low priority INT5 IRQ 1 12 ADCINT ADC interrupt Low priority INT6 IRQ 1 13 XINT1 External interrupt pin 1 Low priority INT6 IRQ 1 14 XINT2 External interrupt pin 2 Low priority INT6 Figure 2 13 Peripheral Interrupt Request Register 2 PIRQR2 Address 7012h 1 IRQ2 14 IRQ2 13 IRO2 12 IRO2 11 IRQ2 10 IRQ2 9 IRQ2 8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 IRQ2 7 IRQ2 6 IRQ2 5 IRQ2 4 IRQ2 3 IRQ2 2 IRQ2 1 IRQ2 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access 0 value after reset Bit 15 Reserved Bits 14 0 IRQ2 14 IRQ2 0 0 Corresponding peripheral interrupt is not pending 1 Peripheral Interrupt is pending Note Writing a 1 sends IRQ to core writing a 0 has no effect System Configuration and Interrupts 2 33 Peripheral Interrupt Registers Table 2 5 Peripheral Interrupt Request Descriptions PIRQR2 Bit position Interrupt Interrupt Description Interrupt Level IRQ 2 0 PDPINTB Power drive protection interrupt pin INT1 IRQ 2 1 CMPAINT Compare 4 interrupt INT2
212. QEP Circuit Modified second bullet item conversion time rates in Section 7 1 Features Modified Figure 7 1 Modified Figure 7 2 Added a note to description of bits 3 0 of AUTO SEQ SR Register Added a note to Figure 7 14 Added data sheet nomenclature column to Table 7 9 Modified description of Bit 6 of RX ERR INT ENA in Figure 8 11 Modified first paragraph of Section 8 7 5 Receiver Status Register SCIRXST Changed bits from illegal to reserved in Table 9 1 Modified last paragraph in Master Mode Modified description of bits 6 0 in Figure 9 10 Modified title of Figure 9 21 Modified description of bit 15 in Figure 10 9 Modified description of bit 9 WUBA in Figure 10 14 Modified descriptions for Bits 10 0 in BCR1 Register Figure 10 16 Revision History A 3 Changes Made in This Revision U rol g co o 2 A A AK A 4 sa Q N A B S Additions Modifications Deletions Modified Figure 10 17 Replaced Table 10 4 Changed description of Bit 6 in the WDCR Register Figure 11 4 and changed reset information on bits 5 3 Added new first paragraph and new last paragraph to Section 12 1 Added a new bullet item to port code instructions in Section 12 2 Added a row to Table 13 3 for the CSM Modified Section 13 4 3 2 Fast RD Strobe Operation Added Section 13 6 1 Input Qualification Circuitry Replaced code for REM ANS asm and REM REQ asm Replaced code for BOOT asm Appendix B Pr
213. QEP Counting sseueeeeeeeeemee teen EE 6 9 5 Register Setup for the QEP Circuit 6 10 Event Manager EV Interrupts 0 00 cee ete eee 6 10 1 EV Interrupt Request and Service 6 10 2 EV Interrupt Flag Registers lt eee eee Analog to Digital Converter ADC lt lt lt eee 7 1 Describes the analog to digital converter ADC Includes a list of features explains the clock prescaler and provides register descriptions 7 1 7 2 7 8 7 4 7 5 7 6 Serial Communications Interface SCI n FeALUIES D ETIIIMUITTM ADC Overview sssssssss ss 7 2 1 Autoconversion Sequencer Principle of Operation 7 2 2 Uninterrupted Autosequenced Mode 7 2 3 Sequencer Start Stop Mode Sequencer Start Stop Operation With Multiple Time Sequenced Triggers 2c cece eee eee eens 7 2 4 Input Trigger Description lt RII 7 2 5 Interrupt Operation During Sequenced Conversions suus ADC Clock Prescaler 0 00 cect nent hn Calibra pP c MTM Register Bit Descriptions 44 444 lt 444 lt 4 e ne 7 5 4 ADC Control Register 1 ADCTRL1 00 cece eee eee 7 5 2 ADC Control Register 2 ADCTRL2 ssssssssssese eee 7 5 8 Maximum Conversion Channels Register MAXCONV ssuee 7 5 4 Autoseguence Status Register AUTO SEQ SR 7 5 5 ADC Input Channel Select Sequencing Control Registers
214. R register is decremented by one for every conversion Current conversion complete Digital result is written into corresponding RESULTn register All conversions complete AUTO SEQ SR 0 Yes Set INT FLAG SEQn Note Flow chart corresponds to CONT RUN bit 0 Analog to Digital Converter ADC 7 9 ADC Overview If CONT RUN is not set the sequencer stays in the last state CONVO6 in this example and SEQ CNTR n continues to hold a value of zero Since the interrupt flag is set every time SEQ CNTR n reaches zero you can if needed manually reset the sequencer using the RST SEQn bit in the ADCTRL2 register in the interrupt service routine ISR so that SEQ CNTR n gets reloaded with the original value in MAX CONV1 at the next SOC and SEG state is set to CONVOO This feature is useful in the Start Stop operation of the sequencer Example 7 1 also applies to SEQ2 and the cascaded 16 state sequencer SEQ with differences outlined in Table 7 2 7 2 8 Sequencer Start Stop Mode Sequencer Start Stop Operation With Multiple Time Sequenced Triggers In addition to the uninterrupted autosequenced mode any sequencer SEQ1 SEQ2 or SEQ can be operated in a stop start mode which is synchronized to multiple start of conversion SOC triggers separated in time This mode is identical to Example 7 1 but the sequencer is allowed to be retriggered without being reset to the initial state CON
215. R 0 D2 D1 D0 001 Full compare match 2 Timer value Full compare match 1 DTPH1 MM 0 2 R DTPH2 DTPH3 U300 U240 Lo jJ U240 U300 101 100 000 000 100 101 SVRDIR 1 D2 D1 D0 101 Event Manager EV 6 67 Capture Units 6 8 Capture Units Capture units enable logging of transitions on capture input pins There are six capture units three is each EV module Capture Units 1 2 and 3 are associated with EVA and Capture Units 4 5 and 6 are associated with EVB Each capture unit is associated with a capture input pin Each EVA capture unit can choose GP timer 2 or 1 as its time base however CAP1 and CAP2 cannot choose a different timer between themselves as their timebase Each EVB capture unit can choose GP timer 4 or 3 as its time base however CAP4 and CAP5 cannot choose a different timer between themselves as their timebase The value of the GP timer is captured and stored in the corresponding 2 level deep FIFO stack when a specified transition is detected on a capture input pin CAPx Figure 6 30 shows a block diagram of an EVA capture unit and Figure 6 31 shows a block diagram of an EVB capture unit Capture Units Figure 6 30 Capture Units Block Diagram EVA T2CNT TICNT GP timer 2 GP timer 1 counter counter GAPCONA 9 10 CAPCONA 12 14 EN Edge detect Capture unit 3 RS cap event CAP1 2 3 Edge CAPCONAJ8 select CAP
216. R 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bits 15 3 Reserved Reads return zero writes have no effect Bit 2 CAP3INT ENABLE 0 Disable 1 Enable Bit 1 CAP2INT ENABLE 0 Disable 1 Enable Bit 0 CAP1INT ENABLE 0 Disable 1 Enable Event Manager EV 6 93 Event Manager EV Interrupts EVB Interrupt Flag Register A EVBIFRA Figure 6 45 EVB Interrupt Flag Register A EVBIFRA Address 752Fh 15 11 10 9 8 r F T3OFINT T3UFINT T3CINT eee FLAG FLAG FLAG R 0 RW1C 0 RW1C 0 RW1C 0 7 6 4 3 2 1 0 FLAG FLAG FLAG FLAG FLAG RW1C 0 R 0 RW1C 0 RW1C 0 RW1C 0 RW1C 0 Note R Read access W1C Write 1 to clear 0 value after reset Bits 15 11 Reserved Reads return zero writes have no effect Bit 10 T3OFINT FLAG GP timer 3 overflow interrupt Read 0 Flagis reset 1 Flagis set Write O No effect 1 Resets flag Bit 9 T3UFINT FLAG GP timer 3 underflow interrupt Read 0 Flagis reset 1 Flagis set Write O No effect 1 Resets flag Bit 8 T3CINT FLAG GP timer 3 compare interrupt Read 0 Flag is reset 1 Flagis set Write 0 No effect 1 Resets flag Bit 7 Bits 6 4 Bit 3 Bit 2 Bit 1 Bit 0 Event Manager EV Interrupts T3PINT FLAG GP timer 3 period interrupt Read 0 Flag is reset Flag is set Write No effect Oo a Resets flag Reserved Reads return zero writes have no effect CMP6INT FLAG Compare 6 interrupt Read 0 Flag is reset 1 Flag is set Wr
217. RQRO 0 ccc eee ee ee eee Peripheral Interrupt Request Descriptions PIRQR1 00 cece eee eee Peripheral Interrupt Request Descriptions PIRQR2 00 cee Peripheral Interrupt Acknowledge Descriptions PIACKRO Peripheral Interrupt Acknowledge Descriptions PIACKR1 eee Peripheral Interrupt Acknowledge Descriptions PIACKR2 ees Data Page 0 Address Map eet nents XMIF Signal Descriptions lt cece nee Setting the Number of Wait States With the 2407A WSGR Bits Low Power Modes Summary 0 00 cece cece eee n 240xA Digital I O Port Control Registers Implementation eee O Mux Control Register A MCRA Configuration lt O Mux Control Register B MCRB Configuration lt O Mux Control Register C MCRC Configuration lt PADATDIR VO Pin Designation Assuming Pins Have Been Selected as I O i e Secondary Function enai ia E eee eee E 5 9 PBDATDIR VO Pin Designation Assuming Pins Have Been Selected as I O Le Sesondaty FUNGON p es asce acta x CRX RARI i Ge Y xod vicio qq d Vide PCDATDIR I O Pin Designation Assuming Pins Have Been Selected as I O i e Secondary Function 20 0 0 ccc cee nent nn 5 11 PDDATDIR I O Pin Designation Assuming Pins Have Been Selected as I O i e Secondary Function 2056 x ectetur t eroe stir dobre einer sa ada O PEDATDIR I O Pin Designation Assuming Pins Have
218. RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access S Set only 0 value after reset Bit 15 Reserved Bit 14 RESET ADC module software reset This bit causes a master reset on the entire ADC module All register bits and sequencer state machines are reset to the initial state as occurs when the device reset pin is pulled low or after a power on reset 0 No effect 1 Resets entire ADC module bit is then set back to 0 by ADC logic 71 Note Using the RESET Bit in the ADCTRL1 Register The ADC module is reset during a system reset If an ADC module reset is desired at any other time you can do so by writing a 1 to this bit After a NOP you can then write the appropriate values to the ADCTRL 1 register bits SPLK 401xxxxxxxxxxxxxxb ADCTRL1 Resets the ADC RESET 1 NOP Provides the required delay between writes to ADCTRL1 SPLK 00xxxxxxxxxxxxxxb ADCTRL1 Takes the ADC out of Reset RESET 0 Note that the second SPLK is not required if the default configuration is sufficient Register Bit Descriptions Bits 13 12 SOFT and FREE Soft and Free bits Bits 11 8 These bits determine what occurs when an emulation suspend occurs due to the debugger hitting a breakpoint for example In free run mode the peripheral can continue with whatever it is doing In stop mode the peripheral can either stop immediately or stop when the current opera
219. SPIBRR Address 7044h 0 0 0 ccc eee eee ee SPI Emulation Buffer Register SPIRXEMU Address 7046h L SPI Serial Receive Buffer Register SPIRXBUF Address 7047h SPI Serial Transmit Buffer Register SPITXBUF Address 7048h SPI Serial Data Register SPIDAT Address 7049h 0 0 0 0 cece eee eee es SPI Priority Control Register SPIPRI Address 704Fh cece eens CLOCK POLARITY 0 CLOCK PHASE 0 All data transitions are during the rising edge non delayed clock Inactive level islow lt ee eee eee CLOCK POLARITY 0 CLOCK PHASE 1 All data transitions are during the rising edge but delayed by half clock cycle Inactive level is low CLOCK POLARITY 1 CLOCK PHASE 0 All data transitions are during the falling edge Inactive level is high lt 0 00 e cece eee eee CLOCK POLARITY 1 CLOCK PHASE 1 All data transitions are during the falling edge but delayed by half clock cycle Inactive level is high SPISTE Behavior in Master Mode Master lowers SPISTE during the entire 16 bits of transmission uma eats 408 eim acta oae hluk Dd e ope E E qd HO Ld SPISTE Behavior in Slave Mode Slave s SPISTE is driven low during the entire 16 bits of transmission ssssssssesee IRI CAN Data Frame eee hn TMS320x240xA CAN Module Block Diagram eese TMS320x240xA CAN Module Mem
220. SPITXBUF SPIFFRX 15 r I l I I I I I I I I I I I I RX Interrupt Logic gt SPIFFOVF FLAG TX Interrupt Logic gt TX FIFO intdrrup TXFIFO 1 TXFIFO 0 L SPI INT FLAG SPISTS 6 SPITX SPITXINT sPicTLO SPIDAT 15 0 o o Talk SPICTL1 SPI Char SPICCR 3 0 Master Slave sleli fo SPI Bit Rate LSPCL Clock Polarity Clock Phase SPIBRR 6 0 ists 4 sf2 1 Jo t SPISTE of a slave device is driven low by the master spicor 6 sPIcTL 3 Overview of SPI Module Registers 9 2 Overview of SPI Module Registers Nine registers inside the SPI module listed in Table 9 1 control the SPI operations Ll SPICCR SPI configuration control register Contains control bits used for SPI configuration B SPI module software reset B SPICLK polarity selection m Four SPI character length control bits SPICTL SPI operation control register Contains control bits for data transmission B Two SPI interrupt enable bits B SPICLK phase selection m Operational mode master slave B Data transmission enable SPISTS SPI status register Contains two receive buffer status bits and one transmit buffer status bit m RECEIVER OVERRUN B SPIINT FLAG m TX BUF FULL FLAG SPIBRR SPI baud rate register Contains seven bits that determine the bit transfer rate SPIRX
221. System Configuration and Interrupts 2 41 2 42 Chapter 3 Memory This chapter describes the RAM ROM and Flash availability on the 240xA In addition to single access RAM SARAM and dual access RAM DARAM BO B1 B2 which is part of the CPU core the 240xA devices include flash EPROM or ROM for additional on chip program memory Devices with an LF prefix are flash devices and those with an LC prefix are ROM devices The 2407A device has a 16 bit address bus that can access the following three individually selectable spaces 192K words total L 64K word program space L 64K word data space g 64K word I O space This chapter shows memory maps for program data and I O spaces It also describes available 240xA memory configuration options Topic Page SA COD ChIpHAMES eee olea sedy NUN SU EE 13 2 3 2 Factory Masked On Chip ROM eeeeeeeeeeee SA lash ee uec E M Ee EUM 3 3 3 4 Overview of Memory and I O Spaces Luueueeeeee 3 5 ES MOC Memory a oH DEA EON aaooooooaonnooononnoonoonaondaonoannaonononnonoca d 74910 Space a tese MM RA een dr E 3 12 3 8 XMIF Qualifier Signal Description 0eceeeeeeeeeees 3 13 3 9 Program and Data Spaces emere eer rnnt a Re XE R 3 16 330 L 0 Space c co eee te uL e eee ee eee ERE 3 16 3 11 Walt State Generation cereus exeo ex EE UE YS 3 1 On Chip RAM 3 1 On Chip RAM The 240xA on chip RAM includes on c
222. System Control and Status Register 2 EOh 224 2 5 701Ch DINR Device Identification Number Register EOh 224 2 8 701Eh PIVR Peripheral Interrupt Vector Register EOh 224 2 30 Watchdog 7023h WDCNTR Watchdog Counter Register EOh 224 11 8 7025h WDKEY Watchdog Reset Key Register EOh 224 11 9 7029h WDCR Watchdog Timer Control Register EOh 224 11 9 Serial Peripheral Interface SPI 7040h SPICCR SPI Configuration Control Register EOh 224 9 19 7041h SPICTL SPI Operation Control Register EOh 224 9 21 7042h SPISTS SPI Status Register EOh 224 9 22 7044h SPIBRR SPI Baud Rate Register EOh 224 9 24 7046h SPIRXEMU SPI Emulation Buffer Register EOh 224 9 25 7047h SPIRXBUF SPI Serial Receive Buffer Register EOh 224 9 26 7048h SPITXBUF SPI Serial Transmit Buffer Register EOh 224 9 27 7049h SPIDAT SPI Serial Data Register EOh 224 9 28 704Fh SPIPRI SPI Priority Control Register EOh 224 9 29 Serial Communications Interface SCI 7050h SCICCR SCI Communication Control Register EOh 224 8 21 7051h SCICTL1 SCI Control Register 1 EOh 224 8 23 7052h SCIHBAUD SCI Baud Select Register high bits EOh 224 8 26 7053h SCILBAUD SCI Baud Select Register low bits EOh 224 8 26 Summary of Programmable Registers on the 240xA Table B 1 Summary of Programmable Registers on the 240xA Continued Data Memory Register Address Mnemonic Register Name Data Page Page 7054h SCICTL2 SCI Control Register 2 EOh 224 8 27 7055h SCIRXST SCI Receiver Status R
223. T CAP3FBOT EVAIMRA EVAIMRB EVAIMRC EVAIFRA EVAIFRB EVAIFRC GPTCONB T3CNT T3CMPR T3PR Register Name Timer 1 Control Register Timer 2 Counter Register Timer 2 Compare Register Timer 2 Period Register Timer 2 Control Register Compare Control Register A Compare Action Control Register A Dead Band Timer Control Register A Compare Register 1 Compare Register 2 Compare Register 3 Capture Control Register A Capture FIFO Status Register A Two Level Deep Capture FIFO stack 1 Two Level Deep Capture FIFO stack 2 Two Level Deep Capture FIFO stack 3 Bottom Register of Capture FIFO stack 1 Bottom Register of Capture FIFO stack 2 Bottom Register of Capture FIFO stack 3 EVA Interrupt Mask Register A EVA Interrupt Mask Register B EVA Interrupt Mask Register C EVA Interrupt Flag Register A EVA Interrupt Flag Register B EVA Interrupt Flag Register C Event Manager B EVB GP Timer Control Register B Timer 3 Counter Register Timer 3 Compare Register Timer 3 Period Register Programmable Register Address Summary Data Page E8h 232 m m rmm m 5 585 5 m m m nm Ow A CO m m m m ITI co N Co N m 2 m m CO m Im m gt N ev n E8h 232 E8h 232 Page 6 33 6 33 6 42 6 44 6 50 6 72 6 76 6 91 6 92 6 93 6 87 6 89 6 90 6 36 B 7 Summary of Programmable Registers on the 240xA Table B 1
224. T2CON 7504h T3CON and 7508h T4CON 11 10 15 14 18 12 9 1 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 T2SWT1 SELT1PR TaswTat TENABLE TCLKS1 TCLKSO TCLD1 TCLDO TECMPR SELT3PRT RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset t Reserved in T1CON andT3CON Bits 15 14 Free Soft Emulation control bits 00 Stop immediately on emulation suspend 01 Stop after current timer period is complete on emulation suspend 10 Operation is not affected by emulation suspend 11 Operation is not affected by emulation suspend Bit 13 Reserved Reads return zero writes have no effect Bits 12 11 TMODE1 TMODEO Count Mode Selection 00 Stop Hold 01 Continuous Up Down Count Mode 10 Continuous Up Count Mode 11 Directional Up Down Count Mode Bits 10 8 TPS2 TPSO Input Clock Prescaler 000 Xx 100 x6 001 x2 101 x 32 010 x 4 110 x 64 011 x 8 111 x 128 x device CPU clock frequency Event Manager EV 6 33 General Purpose GP Timers 6 34 Bit 7 Bit 6 Bits 5 4 Bits 3 2 Bit 1 Bit 0 T2SWT1 In the case of EVA this bit is T2SWT1 GP timer 2 start with GP tim er 1 Start GP timer 2 with GP timer 1 s timer enable bit This bit is reserved in T1CON T4SWTS In the case of EVB this bit is T4SWT3 GP timer 4 start with GP timer 3 Start GP timer 4 with GP timer 3 s timer enable bit This bit is reserved in T3CON 0 Use own TE
225. TMS320LF LC240xA DSP Controllers Reference Guide System and Peripherals Literature Number SPRU357C Revised May 2006 35 TEXAS INSTRUMENTS IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI paten
226. The receiver operates regardless of the SLEEP bit However the receiver neither sets RXRDY nor the error status bits nor does it request a receive interrupt until an address frame is detected 8 3 2 Address Bit Multiprocessor Mode In the address bit protocol ADDR IDLE MODE bit 1 frames have an extra bit called an address bit that immediately follows the last data bit The address bit is set to 1 in the first frame of the block and to 0 in all other frames The idle period timing is irrelevant see Figure 8 5 ADDR IDLE MODE bit in SCICCR 3 Sending an Address The TXWAKE bit value is placed in the address bit During transmission when the SCITXBUF register and TXWAKE are loaded into the TXSHF register and WUT respectively TXWAKE is reset to 0 and WUT becomes the value of the address bit of the current frame Thus to send an address 1 Setthe TXWAKE bit to 1 and write the appropriate address value to the SCITXBUF register When this address value is transferred to the TXSHF register and shifted out its address bit is sent as a 1 This flags the other proces sors on the serial link to read the address 2 Write to SCITXBUF and TXWAKE after TXSHF and WUT are loaded Can be written to immediately since both TXSHF and WUT are both double buffered 3 Leave the TXWAKE bit set to 0 to transmit non address frames in the block po M M M M Note T
227. The space vector PWM waveforms generated are symmetric with respect to the middle of each PWM period and for this reason it is called the symmetric space vector PWM generation method Figure 6 29 shows examples of the symmetric space vector PWM waveforms The Unused Compare Register Only two compare registers are used in space vector PWM output generation The third compare register however is still constantly compared with GP timer 1 When a compare match happens the corresponding compare interrupt flag remains set and a peripheral interrupt request is generated if the flag is unmasked Therefore the compare register that is not used in space vector PWM output generation can still be used to time events happening in a specific application Also because of the extra delay introduced by the state machine the compare output transitions are delayed by one clock cycle in space vector PWM mode 6 7 3 Space Vector PWM Boundary Conditions All three compare outputs become inactive when both compare registers CMPR1 and CMPR2 are loaded with a zero value in space vector PWM mode It is the user s responsibility to assure that CMPR1 lt CMPR2 lt T1PR in the space vector PWM mode otherwise unpredictable behavior may result Space Vector PWM Figure 6 29 Symmetric Space Vector PWM Waveforms Full compare mateng Timer value Full compare match 1 UO U60 U60 UO 001 011 111 111 011 001 SVRDI
228. VOO once it has finished its first sequence i e the sequencer is not reset in the interrupt service routine Therefore when one conversion sequence ends the sequencer stays in the current conversion state The continuous run bit CONT RUN in the ADCTRL1 register must be set to zero i e disabled for this mode Example 7 2 Sequencer Start Stop Operation 7 10 Requirement To start three autoconversions e g 4 l2 l3 off trigger 1 underflow and three autoconversions e g V4 Vo V3 off trigger 2 period Triggers 1 and 2 are separated in time by say 25 us and are provided by Event Manager A EVA See Figure 7 4 Only SEQ1 is used in this case Note Triggers 1 and 2 may be an SOC signal from EVA external pin or software The same trigger source may occur twice to satisfy the dual trigger requirement of this example ADC Overview Figure 7 4 Example of Event Manager Triggers to Start the Sequencer 50us l K 25us EV1 Timer 1 counter EV1 PWM A A A A gt 4 lo la V4 Vo V3 lo V4 Vo V3 Here MAX CONV is set to 2 and the ADC Input Channel Select Sequencing Control Registers CHSELSEQn are set to Bits 15 12 Bits 11 8 Bits 7 4 Bits 3 0 CHSELSEQ1 CHSELSEQ2 CHSELSEQ3 CHSELSEQ4 Once reset and initialized SEQ1 waits for a trigger With the first trigger three conversions with channel select values of CONVOO I4 CONVO1 lo and CO
229. Veca pin to the low pass T filter with short leads This 10 MHz cutoff filter is not essential but may improve jitter significantly and reduce EMI Keep the traces short to ensure that Cpypass 0 01 to 0 1 uF ceramic is closely coupled to the VccA and Vss pins Minimize the loop area formed by these traces the chip and the bypass capacitor Large loop areas increase EMI Avoid nearby noisy traces which may couple noise back into the clock module pins 4 2 3 PLL Bypass Mode 4 2 3 1 4 6 The 240x 240xA devices feature a mode in which the on chip PLL can be bypassed This mode is entered by pulling the TRST TMS and TMS2 pins low upon reset In this mode not only is the PLL bypassed but so is the PLL clock prescaler Therefore changing SCSR1 register bits 11 10 and 9 in bypass mode will have no effect The only way to change the speed in bypass mode is to change the input frequency For example if a CPU clock speed of 30 MHz is desired then a 30 MHz CLKIN must be supplied To summarize the device operates at the same speed as the input clock frequency The external loop filter components are not needed in the bypass mode Input Clock Specification in PLL Bypass Mode m If the on chip oscillator is used i e a quartz crystal ceramic resonator is used as the clock source then the min and max CLKIN frequencies are 4 MHz and 20 MHz respectively If the on chip oscillator is not used i e an external oscillator is used as th
230. W 0 RW 0 RW 0 RW 0 RW 0 RW 0 IAK1 7 IAK1 6 IAK1 5 IAK1 4 IAK1 3 IAK1 2 IAK1 1 IAK1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset System Configuration and Interrupts 2 35 Peripheral Interrupt Registers Bit 15 Reserved Reads return zero writes have no effect Bits 14 0 IACK1 14 IACK1 0 Bit behavior is the same as that of PIACKRO Table 2 7 Peripheral Interrupt Acknowledge Descriptions PIACKR1 Bit position Interrupt Interrupt Description Interrupt Level IAK 1 0 T2PINT Timer 2 period interrupt INT3 IAK 1 1 T2CINT Timer 2 compare interrupt INT3 IAK 1 2 T2UFINT Timer 2 underflow interrupt INT3 IAK 1 3 T2OFINT Timer 2 overflow interrupt INT3 IAK 1 4 CAPINT1 Capture 1 interrupt INT4 IAK 1 5 CAPINT2 Capture 2 interrupt INT4 IAK 1 6 CAPINT3 Capture 3 interrupt INT4 IAK 1 7 SPIINT SPI interrupt Low priority INT5 IAK 1 8 RXINT SCI receiver interrupt Low priority INT5 IAK 1 9 TXINT SCI transmitter interrupt Low priority INT5 IAK 1 10 CANMBINT CAN mailbox interrupt Low priority INT5 IAK 1 11 CANERINT CAN error interrupt Low priority INT5 IAK 1 12 ADCINT ADC interrupt Low priority INT6 IAK 1 13 XINT1 External interrupt pin 1 Low priority INT6 IAK 1 14 XINT2 External interrupt pin 2 Low priority INT6 opis 2 16 Peripheral id Se d d 2 pe Address 7016h 14 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R
231. WM waveform generation one during the upward counting before period match and another during downward counting after period match A new compare value becomes effective after the period match reload on period because itmakes it possible to advance or delay the second edge of a PWM pulse An application of this feature is when a PWM waveform modification compensates for current errors caused by the dead band in AC motor control Because the compare registers are shadowed a new value can be written to them at any time during a period For the same reason new values can be written to the action and period registers at any time during a period to change the PWM period or to force changes in the PWM output definition 6 6 5 Double Update PWM Mode The 240xA Event Manager supports Double Update PWM Mode This mode refers to a PWM operation mode in which the position of the leading edge and the position of the trailing edge of a PWM pulse are independently modifiable in each PWM period To support this mode the compare register that determines the position of the edges of a PWM pulse must allow buffered compare value update once at the beginning of a PWM period and another time in the middle of a PWM period The compare registers in 240xA Event Managers are all buffered and support three compare value reload update value in buffer becoming active modes These modes have earlier been documented as compare value reload conditions The relo
232. aarature Encoder Pulse QEP Circuit To start the operation of the QEP circuit in EVB 1 Load GP timer 4s counter period and compare registers with desired val ues if necessary 2 Configure TACON to set GP timer 4 in directional up down mode with the QEP circuits as clock source and enable the selected timer Event Manager EV 6 83 Event Manager EV Interrupts 6 10 Event Manager EV Interrupts Table 6 15 EV interrupt events are organized into three groups A B and C Each group is associated with a different interrupt flag and interrupt enable register There are several event manager peripheral interrupt requests in each EV interrupt group Table 6 16 shows all EVA interrupts their priority and grouping and Table 6 17 shows all EVB interrupts their priority and grouping There is an interrupt flag register and a corresponding interrupt mask register for each EV interrupt group as shown in Table 6 15 A flag in EVAIFRx x A B or C is masked will not generate a peripheral interrupt request if the corresponding bit in EVAIMRx is zero Interrupt Flag Register and Corresponding Interrupt Mask Register Flag Register Mask Register EV Module EVAIFRA EVAIMRA EVAIFRB EVAIMRB EVA EVAIFRC EVAIMRC EVBIFRA EVBIMRA EVBIFRB EVBIMRB EVB EVBIFRC EVBIMRC 6 10 1 EV Interrupt Request and Service When a peripheral interrupt request is acknowledged the appropriate peripheral interrupt vector is loaded into the peripher
233. abled Clearing the WD OVERRIDE bit in the SCSR2 register after disab ling the WD would re enable the WD WDCHK2 Watchdog Check Bit 2 This bit must be written as a 1 when you write to the WDCR register otherwise a system reset is asserted This bit is always read as 0 0 System reset is asserted 1 Normal operation continues if all check bits are written correctly WDCHK1 Watchdog Check Bit 1 This bit must be written as a 0 when you write to the WDCR register othewise a system reset is asserted This bit is always read as 0 0 Normal operation continues if all check bits are written correctly 1 System reset is asserted WDCHKO Watchdog Check Bit 0 This bit must be written as a 1 when you write to the WDCR register otherwise a system reset is asserted This bit is always read as 0 0 System reset is asserted 1 Normal operation continues if all check bits are written correctly Bits 2 0 Watchdog Control Registers WDPS2 WDPSO Watchdog Prescale Select Bits These bits select the counter overflow tap that is used to clock the WD counter Each selection sets up the maximum time that can elapse before the WD key logic is serviced Table 11 3 shows the overflow times for each prescaler setting when the WDCLK is running at 78125 Hz Because the WD timer counts 257 clocks be fore overflowing the times given are the minimum for overflow reset The maximum timeout can be up to 1 256 longer than the times listed in Ta
234. ace SPI 9 29 SPI Example Waveforms 9 6 SPI Example Waveforms Figure 9 16 CLOCK POLARITY 0 CLOCK PHASE 0 All data transitions are during the rising edge non delayed clock Inactive level is low 4 Ch1 Period 200 ns SPICLK SPISIMO 9 30 SPI Example Waveforms Figure 9 17 CLOCK POLARITY 0 CLOCK PHASE 1 All data transitions are during the rising edge but delayed by half clock cycle Inactive level is low Ch1 Period 200 ns SPICLK E eene metta SPISIMO WI 3 00v th 2 00V M 500ns Chi 7 1 52V Serial Peripheral Interface SPI 9 31 SPI Example Waveforms Figure 9 18 CLOCK POLARITY 1 CLOCK PHASE 0 All data transitions are during the falling edge Inactive level is high Ch1 Period 199 ns SPISIMO 9 32 SPI Example Waveforms Figure 9 19 CLOCK POLARITY 1 CLOCK PHASE 1 All data transitions are during the falling edge but delayed by half clock cycle Inactive level is high Ch1 Period 200 ns SPICLK SPISIMO Serial Peripheral Interface SPI 9 33 SPI Example Waveforms Figure 9 20 SPISTE Behavior in Master Mode Master lowers SPISTE during the entire 16 bits of transmission Ch1 Period 200 ns PI INPUNE SA AAA AM eee SPICLK X00v ths 200v Mi o0us Chi 7 1 52V 9 34 SPI Example Waveforms Figure 9 21 SPISTE Behavior in Slave Mode Slave s SPISTE is driven low during the entire 16 bits of trans
235. acters to SCIRXEMU and SCIRXBUF Clearing RXENA stops received characters from being transferred to the two receiver buffers and also stops the generation of receiver interrupts However the receiver shift register can continue to assemble characters Thus if RXENA is set during the reception of a character the complete character will be transferred into the receiver buffer registers SCIRXEMU and SCIRXBUF Serial Communications Interface SCI 8 25 SCI Module Registers 8 7 8 Baud Select Registers SCIHBAUD SCILBAUD The values in SCIHBAUD and SCILBAUD specify the baud rate for the SCI Figure 8 12 Baud Select MSbyte Register SCIHBAUD Address 7052h 15 14 13 12 11 10 9 8 BAUD15 MSB BAUD14 BAUD13 BAUD12 BAUD11 BAUD10 BAUD9 BAUD8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access S Set only 0 value after reset Figure 8 13 Baud Select LSbyte Register SCILBAUD Adaress 7053h 7 6 5 4 3 2 1 0 BAUDO BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 LSB RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access S Set only 0 value after reset Bits 15 0 BAUD15 BAUDO SCI 16 bit baud selection Registers SCIHBAUD MSbyte and SCILBAUD LSbyte are concatenated to form a 16 bit baud value BRR The internally generated serial clock is determined by the CLKOUT signal and the two baud select registers The SCI uses the 16 bit value of these registers to select one
236. ad access 0 value after reset Bits 15 0 V15 VO Interrupt vector This register contains the peripheral interrupt vector of the most recently acknowledged peripheral interrupt Peripheral Interrupt Registers 2 10 2 Peripheral Interrupt Request Registers PIRQRO 1 2 The peripheral interrupt request registers PIRQRx enable The state of the peripheral interrupt requests to be read _ A simulated assertion of a particular peripheral interrupt request PIRQRO is shown in Figure 2 11 PIRQR1 is shown in Figure 2 12 and PIRQR2 is shown in Figure 2 13 Figure 2 11 Peripheral Interrupt Request Register 0 PIRHQRO Address 7010h 15 14 13 12 11 10 9 8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 f 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bits 15 0 IRQ0 15 IRQO O 0 Corresponding peripheral interrupt is not pending 1 Peripheral Interrupt is pending Note Writing a 1 sends IRQ to core writing a O has no effect Table 2 3 Peripheral Interrupt Request Descriptions PIRQRO Bit position Interrupt Interrupt Description Interrupt Level IRQ 0 0 PDPINTA Power device protection interrupt pin INT1 IRQ 0 1 ADCINT ADC interrupt High priority INT1 IRQ 0 2 XINT1 External interrupt pin 1 High priority INT1 IRQ 0 3 XINT2 External interrupt pin 2 High priority INT1 IRQ 0 4 SPIINT SPI interrupt High priority INT1 IRQ 0 5 RXINT SCI receiver in
237. ad condition that supports double update PWM mode is reloaded on underflow beginning of PWM period OR period middle of PWM period Double update PWM mode can be achieved by using this condition for compare value reload Event Manager EV 6 61 Space Vector PWM 6 7 Space Vector PWM Space vector PWM refers to a special switching scheme of the six power transistors of a 3 phase power converter It generates minimum harmonic distortion to the currents in the windings of a 3 phase AC motor It also provides more efficient use of supply voltage in comparison with the sinusoidal modulation method 6 7 1 3 Phase Power Inverter The structure of a typical 3 phase power inverter is shown in Figure 6 27 where Va Vp and V are the voltages applied to the motor windings The six power transistors are controlled by DTPHy and DTPH x a b and c When an upper transistor is switched on DTPH 1 the lower transistor is switched off DTPH 0 Thus the on and off states of the upper transistors Q1 Q3 and Q5 or equivalently the state of DTPHx x a b and c are sufficient to evaluate the applied motor voltage Ug Figure 6 27 3 Phase Power Inverter Schematic Diagram Ude e e e e e DTPHa K Q A orPH Qs A orit O5 A Va Vp Vc e e e DTPHa K ao A orm T Q4 A DTP He p O6 A GND o o o o Power Inverter Switching Patterns and the Basic Space Vectors When an upper transistor of a le
238. aeaaaee 19 5 Digital O GPIO PINS zs 204224 b seh 400004 dee ER obden be REY ERE n 13 5 1 Digital I O and Shared Pin Functions for the 240xA ss 13 6 Event Manager Module EVB nh 18 6 1 Input Qualification Circuitry sessin 0 eee A Revision History 44 eee eee eee III m m m Provides a summary or changes made in this revision A 1 Changes Made in This Revision 22 0 A 2 B Programmable Register Address Summary eseseeeeees esee Provides a summary of all programmable registers on TMS320X240xA devices C Program Examples s s cbse Re I we Rer mr EAE ER UN EE E xax eee id C 1 Presents program examples for the 240xA C 1 About These Program Examples ssssssssses nh C 2 C 2 Program Examples 2 cusa oss seme tad adde d avs d Ae d odo ed eoa wid C 4 D TMS320F240x 240xA Boot ROM Loader Protocols and Interfacing Decribes the boot load sequence and discusses SPI synchronous and SCI asynchronous transfer protocol and data formats D 1 nieje VT0j110 MERCED RETE ETE EO O O A D 2 Contents XV Contents D 1 1 Boot Load Sequence sens D 2 Protocol Definitions sssssssssssssssesese I ra D 2 1 SPI Synchronous Transfer Protocol and Data Formats D 2 2 SCI Asynchronous Transfer Protocol and Data Formats E Flash ROM Code Security For LF LC240xA DSP Devices sees E 1 Describes the Flash
239. ailbox controlling the transmit receive mail function and handling interrupts 10 4 1 Mailbox Direction Enable Register MDER The Mailbox Direction Enable register MDER consists of the Mailbox Enable ME and the Mailbox Direction MD bits In addition to enabling disabling the mailboxes MDER is used to select the direction transmit receive for mailboxes 2 and 3 Mailboxes that are disabled may be used as additional memory for the DSP Figure 10 11 illustrates this register Figure 10 11 Mailbox Direction Enable Register MDER Address 7100h 15 8 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access value following dash value after reset Bits 15 8 Reserved Bits 7 6 MDn Mailbox direction for mailbox n Mailboxes 2 and 3 can be configured as a transmit or receive mailbox Mailbox direction bits are defined as follows 0 Transmit mailbox 1 Receive mailbox After power up all bits are cleared Bits 5 0 MEn Mailbox enable for mailbox n Each mailbox can be enabled or disabled If the bit MEn is 0 the corresponding mailbox n is disabled The mailbox must be disabled before writing to any identifier field If the corresponding bit in ME is set the write access to the identifier of a message object is denied and the mailbox is enabled for the CAN module Mailboxes that are disabled may be used as additional memory for the DSP CAN Controller Module 10 19 CAN
240. al most identically to SPIRXBUF except that reading SPIRXEMU does not clear the SPI INT FLAG bit SPISTS 6 Once the SPIDAT has received the com plete character the character is transferred to SPIRXEMU and SPIRXBUF where it can be read At the same time SPI INT FLAG is set This mirror register was created to support emulation Reading SPIRXBUF clears the SPI INT FLAG bit SPISTS 6 In the normal operation of the emulator the control registers are read to continually update the contents of these registers on the display screen SPIRXEMU was created so that the emulator can read this register and properly update the contents on the display screen Reading SPIRXEMU does not clear the SPI INT FLAG bit but reading SPIRXBUF clears this flag In other words SPIRXEMU enables the emulator to emulate the true operation of the SPI more accurately It is recommended that you view SPIRXEMU in the normal emulator run mode Serial Peripheral Interface SPI 9 25 SPI Module Registers 9 5 6 SPI Serial Receive Buffer Register SPIRXBUF SPIRXBUF contains the received data Reading SPIRXBUF clears the SPI INT FLAG bit SPISTS 6 Figure 9 12 SPI Serial Receive Buffer Register SPIRXBUF Address 7047h 15 14 13 12 11 10 9 8 RXB15 RXB14 RXB13 RXB12 RXB11 RXB10 RXB9 RXB8 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Note R Read access 0 value after reset Bits 15 0 RXB15 RXBO Received Data On
241. al if any must be removed Chapter 13 240xA 24x Family Compatibility This chapter discusses the compatibility issues between the 24x 241 242 243 devices and the 240x 240xA devices It outlines the points to be considered while migrating from the 24x family to the 240x 240xA family Topic del Noe ECCE TRECE 13 2 24x 240xA DSP Overview ceecee eneo eeren nennen j3 39 Memory Map a e E 13 4 System Features lt 2c cosine e vests EEEN RII IT 13 57 Digital lO GPIO PINS 302 522 oe SULCIS 13 6 Event Manager Module EVB 13 1 Introduction 13 1 Introduction This chapter highlights the major differences in terms of features peripherals between the 240xA and the 24x TMS320F243 F241 C242 family of DSP devices The 240xA devices share most of the 24x features however 240xA devices have some enhancements The common features differences and enhancements are described in Table 13 1 and Table 13 2 Table 13 1 24x Compatible Features Peripherals in 240xA DSPs 13 2 24x Compatible Features Peripherals in 240xA Reference Document TMS320F C24x DSP Controllers Reference C2xx CPU Instruction Set Interrupt Behavior and Guide CPU and Instruction Set literature num BO B1 B2 DARAM berlSPRU160 TMS320F243 TMS320F241 DSP Controllers AMI External Memory nterrace Data Sheet literature number SPRS064 Watchdog With the minor exception of the ab sence of the WDDIS pin this feature is now
242. al interrupt vector register PIVR by the PIE controller The vector loaded into the PIVR is the vector for the highest priority pending enabled event The vector register can be read by the interrupt service routine ISR Event Manager EV Interrupts Table 6 16 Event Manager A EVA Interrupts Group Interrupt PDPINTA CMP1INT CMP2INT CMP3INT T1PINT T1CINT T1UFINT T1OFINT T2PINT T2CINT T2UFINT T2OFINT CAP1INT CAP2INT CAPSINT Priority within group 1 highest 2 3 4 5 6 7 8 lowest 1 highest 2 3 4 1 highest 2 3 Vector ID 0020h 0021h 0022h 0023h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 0033h 0034h 0035h Description Source INT Power Drive Protection Interrupt A 1 Compare Unit 1 compare interrupt Compare Unit 2 compare interrupt Compare Unit 3 compare interrupt GP timer 1 period interrupt 2 GP timer 1 compare interrupt GP timer 1 underflow interrupt GP timer 1 overflow interrupt GP timer 2 period interrupt GP timer 2 compare interrupt GP timer 2 underflow interrupt GP timer 2 overflow interrupt Capture Unit 1 interrupt Capture Unit 2 interrupt 4 Capture Unit 3 interrupt Event Manager EV 6 85 Event Manager EV Interrupts Table 6 17 Event Manager B EVB Interrupts Priority Vector Group Interrupt within group ID Description Source INT PDPINTB 1 highest 0019h Power Drive Protection Interrupt B 1 A CMP4INT 2 0024h Compare Unit 4 comp
243. anager EV external interrupt 1 control register XINT1CR external interrupt 2 control register XINT2CR global status register GSR GP timer control registers overall GPTCONn GP timer control register A GPTCONA GP timer control register B GPTCONB I O mux control registers MCRn I O mux control register A MCRA WO mux control register B MCRB I O mux control register C MCRC individual GP M control register TxCON interrupt flag E IFR 2 26 to 2 42 interrupt mask register IMR 2 28 to 2 42 local aceeptenze n mask register n 0 1 high word LAMn H local separe mask register n 0 1 low word LAMn L mailbox ea T register MDER 10 19 19 mapped to data page 0 ee master control register M maximum conversion ee register MAXCONV bit selections for MAX CONV for various number of conversions 7 33 MAX CONV value gt 7 for dual sequencer mode register bit programming output control register A MCRA overall GP timer control register A GPTCONA overall GP timer control register B GPTCONB peripheral interrupt peripheral interrupt acknowledge registers PIACKRn peripheral interrupt acknowledge register 0 PIACKRO peripheral interrupt acknowledge register 1 PIACKR1 peripheral interrupt acknowledge register 2 PIACKR2 peripheral interrupt request registers PIRQRn peripheral interrupt request register 0 PIRQRO peripheral interrupt request register 1 PIRQR1
244. and a half cycle after WE goes high This prevents data contention on the external busses Wait State Generation 3 11 Wait State Generation Wait states are necessary when you want to interface the 2407A with slower external logic and memory By adding wait states you lengthen the time the CPU waits for external memory or an external I O port to respond when the CPU reads from or writes to that memory or port Specifically the CPU waits one extra cycle one CLKOUT cycle for every wait state The wait states operate on CLKOUT cycle boundaries To avoid bus conflicts writes from the 2407A always take at least two CLKOUT cycles The 2407A offers two options for generating wait states The READY signal With the READY signal you can externally generate any number of wait states The on chip wait state generator With this generator you can generate zero to seven wait states 3 11 1 Generating Wait States With the READY Signal When READY is low the 2407A waits one CLKOUT cycle and checks READY again The 2407A will not continue executing until READY is driven high therefore if the READY signal is not used it should be pulled high during external accesses The READY pin can be used to generate any number of wait states However when the 2407A operates at full speed it cannot respond fast enough to provide a READY based wait state for the first cycle For extended wait states using external READY logic the on chip wait s
245. and synchronized with the internal clock The qualification and synchronization cause a delay of two clock cycles The setting of the flag does not depend on whether or not the PDPINTx interrupt is masked it happens when a qualified transition occurs on the PDPINTx pin This interrupt is enabled following reset If the PDPINTx interrupt is disabled the action of driving the PWM outputs to the high impedance state upon a valid PDPINTx interrupt is also disabled Event Manager EV Functional Blocks 6 1 3 1 240xA Specific Features for PDPINTx Function In 240xA devices the status of the PDPINTx pin is reflected in bit 8 of the COMCONXx register The PDPINTx pin must be held low for 6 or 12 CLKOUT cycles before it is recognized by the core 6 1 4 EV Registers The Event Manager registers occupy two 64 word 16 bit frames of address space The Event Manager module decodes the lower six bits of the address while the upper 10 bits of the address are decoded by the peripheral address decode logic which provides a module select to the Event Manager when the peripheral address bus carries an address within the range designated for the EV on that device On 240xA devices as with the C240 device EVA registers are located in the range 7400h to 7431h EVB registers are located in the range of 7500h to 7531h The undefined registers and undefined bits of the EV registers all return zero when read by user software Writes have no e
246. anging from 15 MHz to 40 MHz For information on configuring the flash programming utilities to program the flash at any particular frequency refer to the documentation included with the flash programmaing utilities Flash Overview of Memory and I O Spaces In the case of serial port flash programming utilities the available number of frequencies is limited further by the serial port synchronization protocol implemented within the Boot ROM See Appendix C TMS320F240x Boot ROM Loader Protocols and Interfacing 3 4 Overview of Memory and I O Spaces The 240xA design is based on an enhanced Harvard architecture These devices have multiple memory spaces accessible on three parallel buses a program address bus PAB a data read address bus DRAB and a data write address bus DWAB Each of the three buses access different memory spaces for different phases of the device s operation Because the bus operations are independent it is possible to access both the program and data spaces simultaneously Within a given machine cycle the CALU can execute as many as three concurrent memory operations The 240xA address map is organized into three individually selectable spaces Program memory 64K words contains the instructions to be executed as well as immediate data used during program execution _j Data memory 64K words holds data used by the instructions Input output I O space 64K words interfaces to external periphera
247. apter describes the architecture functions and programming of the serial communications interface SCI module All registers in this peripheral are eight bits wide The programmable SCI supports asynchronous serial UART digital communications between the CPU and other asynchronous peripherals that use the standard NRZ non return to zero format The SCI s receiver and transmitter are double buffered and each has its own separate enable and interrupt bits Both may be operated independently or simultaneously in the full duplex mode To ensure data integrity the SCI checks received data for break detection parity overrun and framing errors The bit rate baud is programmable to over 65 000 different speeds through a 16 bit baud select register For convenience references to a bit in a register are abbreviated using the register name followed by a period and the number of the bit For example the notation for bit 6 of the SCI priority control register SCIPRI is SCIPRI 6 Topic Page 8 1 C240 SCI vs LF LC240xA SCI eee nnn 8 2 SCI Programmable Data Format 8 8 8 3 SCI Multiprocessor Communication sseeeeee 8 9 8 4 SCI Communication Format s sass sasssa eee 85 ESC POrtIntennUlptSweretert slots lata lete gt 8 6 SCI Baud Rate Calculations eeee ee 8 19 8 7 SScl Module Registers rt ERE ERR 8 1 C240 SCI vs LF LC240xA SCI 8 1
248. ar amp get response POINT B1 AND OFFH MSByte of start address is in the acc Get rid of any higher bits SACL GPRO A LACC 0000H Zero Character CALL XMIT VALUE Transmit char amp get response POINT B1 LSByte of start address is in ACC AND OOFFH Mask any upper byte ADD GPRO 8 Bring in the MS Byte RET TMS320F240x 240xA Boot ROM Loader Protocols and Interfacing D 15 Protocol Definitions p RRR RRR k k k KKK KKK KK KK KK KKK KKK KK KKK KKK KK k k k KKK KK k k k k k kc kc k k k k k k k k k k k k k k k k k k k k k k ck KK Transmit a char on the SPI Bus and return received data in accumulator Exit Conditions 1 DP is set to B1 on Exit i 2 ACC is destroyed n 3 Does not care about DP on enter p RR RR k k k k k k k k KKK KKK KKK KK KK KKK KKK KK KKK KKK k k k ke k k k k k k k k k k k kc kc k k k k k k k k k k k k k ck ck ck k k k k k XMIT_VALUE LDP SPITXBUF gt gt 7 SACL SPITXBUF Write xmit value to SPI TX Buffer XMIT NCOMPL BIT SPISTS BIT6 Test SPI INT bit BCND XMIT NCOMPL NT If bit TC 0 then wait for TX Compl i e wait for transmit to finish LACC SPIRXBUF Read also clears SPI INT flag RET p RRR RRR KEK RK KK RK KK KKK KKK KK KK k k KKK KKK k k k ke k ke k ke k k k k k k k k k k k k k kc kc k k k k k k k k k k k ck ck ck ck ck ck KK Transmit a char on the SPI Bus and return received data in accumulator Exit Conditions 1 DP is set to B1 on Exit 2 ACC is destroyed p RRR RRR KEK
249. are interrupt CMPS5INT 3 0025h Compare Unit 5 compare interrupt CMP6INT 4 0026h Compare Unit 6 compare interrupt T3PINT 5 002Fh GP timer 3 period interrupt 2 T3CINT 6 0030h GP timer 3 compare interrupt T3UFINT 7 0031h GP timer 3 underflow interrupt T3OFINT 8 lowest 0032h GP timer 3 overflow interrupt B T4PINT 1 highest 0039h GP timer 4 period interrupt T4CINT 2 003Ah GP timer 4 compare interrupt T4UFINT 3 003Bh GP timer 4 underflow interrupt T4OFINT 4 003Ch GP timer 4 overflow interrupt C CAPAINT 1 highest 0036h Capture Unit 4 interrupt CAP5INT 2 0037h Capture Unit 5 interrupt 4 CAP6INT 3 0038h Capture Unit 6 interrupt Table 6 18 Conditions for Interrupt Generation Interrupt Condition For Generation Underflow When the counter reaches 0000h Overflow When the counter reaches FFFFh Compare When the counter register contents match that of the compare register Period When the counter register contents match that of the period register Interrupt Generation When an interrupt event occurs in the EV module the corresponding interrupt flag in one of the EV interrupt flag registers is set to one A peripheral interrupt request is generated to the Peripheral Interrupt Expansion controller if the flag is locally unmasked the corresponding bit in EVAIMRx is set to one Event Manager EV Interrupts Interrupt Vector The peripheral interrupt vector corresponding to the interrupt flag that has the highest priority among the flags that are
250. arent 1 Enable compare operation Bits14 13 CLD1 CLDO Compare register CMPRx reload condition 00 When T3CNT 0 that is on underflow 01 When T3CNT 0 or T3CNT T3PR that is on underflow or period match 10 Immediately 11 Reserved result is unpredictable Bit 12 SVENABLE Space vector PWM mode enable 0 Disables space vector PWM mode 1 Enables space vector PWM mode Event Manager EV 6 43 Compare Units Bits 11 10 Bit 9 Bit 8 Bits 7 0 ACTRLD1 ACTRLDO Action control register reload condition 00 When T3CNT 0 on underflow 01 When T3CNT 0 or T3CNT T3PR on underflow or period match 10 Immediately 11 Reserved FCOMPOE Compare output enable Active PDPINTB clears this bit to zero 0 PWM output pins are in high impedance state that is they are dis abled 1 PWM output pins are not in high impedance state that is they are enabled PDPINTB STATUS This bit reflects the current status of the PDPINTB pin An application could poll this bit to determine whether the fault that activated this pin has disappeared This bit is applicable to 240xA devices only it is re served on 240x devices and returns a zero when read Reserved Read returns zero writes have no effect Compare Action Control Registers ACTRA and ACTRB The compare action control registers ACTRA and ACTRB control the action that takes place on each of the six compare output pins PWMx where x 1 6 for ACTRA and x 7
251. ate low priority requests Bit 14 Reserved Bits 13 8 See section 10 6 1 CAN Interrupt Flag Register CAN IFR on page 10 36 Bit 7 EIL Error Interrupt Priority Level For the error interrupts RMLIF AAIF WDIF WUIF BOIF EPIF and WLIF 0 The named interrupts generate high priority requests 1 The named interrupts generate low priority requests Bits 6 0 See section 10 6 1 CAN Interrupt Flag Register CAN IFR on page 10 36 10 38 Configuration Mode 10 7 Configuration Mode The CAN module must be initialized before activation This is only possible when the module is in the configuration mode which is set by programming CCR with 1 The initialization can be performed only if the status bit CCE confirms the request by getting 1 Afterwards the bit configuration registers can be written The module is activated again by programming the control bit CCR with zero After a hardware reset the configuration mode is active Figure 10 23 CAN Initialization Normal mode CCR 0 CCE 0 Configuration mode requested CCR 1 CCE 0 Wait for configuration mode CCR 1 CCE 0 Configuration mode active CCR 1 CCE 1 Changing of bit timing parameters enabled Normal mode requested CCR 0 CCE 1 Wait for normal mode CCR 0 CCE 1 CCE 1 CAN Controller Module 10 39 Power Down Mode PDM 10 8 Power Down Mode PDM 10 40 If the peripheral clocks are to
252. avior in master mode SPICLK CLKOUT characteristics SPISTE behavior in slave mode Index 20 SPI operation control register SPICTL SPI priority control register SPIPRI SPI serial data register SPIDAT SPI serial receive buffer register SPIRXBUF SPI serial transmit buffer register SPITXBUF SPI status register SPISTS SOF CAN data frame SOS synch start of sequence sync up SPI serial peripheral interface 9 1 block diagram C240 SPI vs LF LC240xA SPI interrupts baud rate and clocking schemes baud rate determination example of baud rate calculations for SPIBRR 0 1 or2 example of baud rate calculations for SPIBRR 3 to 127 example of maximum baud rate calculation clocking schemes selection guide SPICLK signal options SPICLK CLKOUT characteristics data format example transmission of bit from SPIRXBUF data transfer example five bits per character initialization upon reset proper SPI initialization using the SPI SW RESET bit SPI interrupt control bits OVERRUN INT ENA bit SPICTL 4 RECEIVER OVERRUN FLAG bit SPISTS 7 SPI INT ENA bit SPICTL 0 SPI INT FLAG bit SPISTS 6 SPI PRIORITY bit SPIPRI 6 operation introduction master mode 9 8 master slave connection figure slave mode physical description I O pins master and slave mode operations memory mapped control and status registers Index SPI serial data register SPIDAT SPI serial receive buffer register SPIRXBUF SPI serial transm
253. ble 11 3 because of the added uncertainty resulting from not clearing the prescaler Table 11 3 WD Overflow Timeout Selections WD Prescale Select Bits 78125 Hz WDCLKT WDPS2 WDPS1 WDPSO eae hs dole Osis Hz ms 0 0 X 1 305 2 3 28 0 1 0 2 152 6 6 6 0 1 1 4 76 3 13 1 1 0 0 8 38 1 26 2 1 0 1 16 19 1 52 4 1 1 0 32 9 5 104 9 1 1 1 64 4 8 209 7 X Don t care T Generated by a 40 MHz clock Watchdog WD Timer 11 11 11 12 Chapter 12 240xA 240 Family Compatibility This chapter describes the compatibility issues between the 240xA and 240 family of processors The software changes required between 240 code and 240xA code have been kept to a minimum A majority of the register addresses bit positions and functions are identical between the 240 and 240xA devices Topic Page 12 1 General aeae a a so cane See sta ala spala soe tere eterne EE 12 2 12 20Eventi Managen cec 12 3 Analog to Digital Converter 4 4 44 12 4 Serial Communications Interface 12 5 Serial Peripheral Interface eee ee eee eens 12 6 Watchdog Timer 2 09 99 xe esse Erster 12 1 General 12 1 General 12 2 The 240 is a 5 V part whereas the 240xA devices operate on 3 3 V Low power mode 2 HALT is the lowest power mode on the 240xA It is similar to the LPMG oscillator power down on the 240 There is no equivalent to LPM2 PLL power down on the 240 The low power mode bits are in
254. boxes Unused mailbox RAM may be used as normal memory Because of this you must ensure that no CAN function uses the RAM area This is usually done by disabling the corresponding mailbox or by disabling the CAN function 10 3 3 Write Access to Mailbox RAM 10 12 There are two different types of write accesses to the Mailbox RAM 1 write access to the identifier of a mailbox 2 write access to the data or control field Note Write accesses to the identifier can only be accomplished when the mailbox is disabled MEn 0 in MDER register Message Objects During accesses to the data field or control field it is critical that the data does not change while the CAN module is reading it Therefore a write access to the data field or control field is disabled for a receive mailbox For transmit mailboxes the access is usually denied if the transmit request set TRS bit or the transmit request reset TRR bit is set In these cases a write denied interrupt flag WDIF is asserted A way to access mailboxes 2 and 3 is to set the change data field request CDR bit before accessing the mailbox data After the CPU access is finished the CPU must clear the CDR flag by writing a 0 to it The CAN module checks for that flag before and after reading the mailbox If the CDR flag is set during the mailbox checks the CAN module does not transmit the message but continues to look for other transmit requests The setting of the CDR
255. bytes m Two receive mailboxes MBOX0 1 two transmit mailboxes MBOX4 5 m Two configurable transmit receive mailboxes MBOX2 3 Local acceptance mask registers LAMn for mailboxes 0 and 1 and mail boxes 2 and 3 Programmable bit rate Programmable interrupt scheme Programmable wake up on bus activity Automatic reply to a remote request Automatic re transmission in case of error or loss of arbitration Bus failure diagnostic Bus on off Error passive active Bus error warning Bus stuck dominant Frame error report Readable error counter Self Test Mode B The CAN peripheral operates in a loopback mode m Receives its own transmitted message and generates its own ac knowledge signal Two Pin Communication B The CAN module uses two pins for communication CANTX and CANRX B These two pins are connected to a CAN transceiver chip which in turn is connected to a CAN bus Overview of the CAN Network 10 2 Overview of the CAN Network The controller area network CAN uses a serial multimaster communication protocol that efficiently supports distributed real time control with a very high level of data integrity and communication speeds of up to 1 Mbps The CAN bus is ideal for applications operating in noisy and harsh environments such as in the automotive and other industrial fields that require reliable communication Prioritized messages of up to eight bytes in data length can be sent on a multimaster serial bus usi
256. cal Description The SPI module as shown in Figure 9 1 consists of Four I O pins B SPISIMO SPI slave in master out B SPISOMI SPI slave out master in B SPICLK SPI clock m SPISTE SPI slave transmit enable Master and slave mode operations SPI serial receive buffer register SPIRXBUF This buffer register contains the data that is received from the network and that is ready for the CPU to read Lj SPI serial transmit buffer register SPITXBUF This buffer register contains the next character to be transmitted when the current transmit has completed O SPI serial data register SPIDAT This data shift register serves as the transmit receive shift register SPICLK phase and polarity control C240 SPI vs LF LC240xA SPI State control logic Memory mapped control and status registers The basic function of the strobe SPISTE pin is to act as a transmit enable input for the SPI module in slave mode It stops the shift register so it cannot receive data and puts the SPISOMI pin in the high impedance state Serial Peripheral Interface SPI 9 3 C240 SPI vs LF LC240xA SPI Figure 9 1 SPI Module Block Diagram SPIFFENA SPIFFTX 14 RX FIFO registers Receiver Overrun Flag SPISTS 7 SPIRXBUF RX FIFO 0 RX FIFO 1 RX FIFO Interrupt Overrun INT ENA ay SPICTL 4 SPINT SPIRXINT 18 Zal SPIRXBUF Buffer Register r
257. cause of a capture event the write data takes precedence Event Manager EV 6 75 Capture Units The write operation to the CAPFIFOx registers can be used as a programming advantage For example if a 01 is written into the CAPnFIFO bits the EV module is led to believe that there is already an entry in the FIFO Subsequently every time the FIFO gets a new value a capture interrupt will be generated Figure 6 34 Capture FIFO Status Register A CAPFIFOA Adaress 7422h 15 14 13 12 11 10 9 8 R 0 RW 0 RW 0 RW 0 7 0 R 0 Note R Read access W Write access 0 value after reset Bits 15 14 Reserved Reads return zero writes have no effect Bits 13 12 CAPS3FIFO CAP3FIFO Status 00 Empty 01 Has one entry 10 Has two entries 11 Had two entries and captured another one first entry has been lost Bits 11 10 CAP2FIFO CAP2FIFO Status 00 Empty 01 Has one entry 10 Has two entries 11 Had two entries and captured another one first entry has been lost Bits 9 8 CAP1FIFO CAP1FIFO Status 00 Empty 01 Has one entry 10 Has two entries 11 Had two entries and captured another one first entry has been lost Bits 7 0 Reserved Reads return zero writes have no effect Capture Units Capture FIFO Status Register B CAPFIFOB CAPFIFOB contains the status bits for each of the three FIFO stacks of the capture units The bit description of CAPFIFOB is given in Figure 6 35 If a write occurs to the CAPnFIFOB status bits at t
258. ccess C Clear by writing a 1 0 value after reset Bit 15 XINT1 Flag This bit indicates whether the selected transition has been detected on the XINT1 pin and is set whether or not the interrupt is enabled This bit is cleared by the appropriate interrupt acknowledge by software writing a 1 writing a 0 has no effect or by a device reset 0 No transition detected 1 Transition detected Bits 14 3 Reserved Reads return zero writes have no effect Bit 2 XINT1 Polarity This read write bit determines whether interrupts are generated on the rising edge or the falling edge of a signal on the pin 0 Interrupt generated on a falling edge high to low transition 1 Interrupt generated on a rising edge low to high transition Bit 1 XINT1 Priority This read write bit determines which interrupt priority is requested The CPU interrupt priority levels corresponding to low and high priority are coded into the peripheral interrupt expansion controller These priority levels are shown in Table 2 2 240xA Interrupt Source Priority and Vectors in Chapter 2 on page 2 9 0 High priority 1 Low priority System Configuration and Interrupts 2 39 External Interrupt Control Registers Bit 0 XINT1 Enable This read write bit enables or disables external interrupt XINT1 0 Disable interrupt 1 Enable interrupt 2 13 2 External Interrupt 2 Control Register XINT2CR Figure 2 18 External Interrupt 2 Control Register XINT2CR Address 707
259. ce enters a subroutine such as an interrupt service routine and restoring the system status when exiting the subroutine On the 24x only the pro gram counter value is saved and restored automatically other context saving and restoring must be performed by the subroutine CPU Central processing unit The 24x CPU is the portion of the processor involved in arithmetic shifting and Boolean logic operations as well as the generation of data and program memory addresses The CPU includes the central arithmetic logic unit CALU the multiplier and the auxiliary register arithmetic unit ARAU Glossary F 3 Glossary F 4 CPU cycle The time required for the CPU to go through one logic phase during which internal values are changed and one latch phase during which the values are held constant current AR See current auxiliary register current auxiliary register The auxiliary register pointed to by the auxiliary register pointer ARP The auxiliary registers are ARO ARP 0 through AR7 ARP 7 See also auxiliary register next auxiliary register current data page The data page indicated by the content of the data page pointer DP See also data page DP DO D15 Collectively the external data bus the 16 pins are used in parallel to transfer data between the 24x and external data memory program memory or I O space DARAM Dual access RAM RAM that can be accessed twice in a single CPU clock cycle For example
260. ce SPIDAT has received the complete character the character is transferred to SPIRXBUF where it can be read At the same time the SPI INT FLAG bit SPISTS 6 is set Since data is shifted into the SPI s most significant bit first it is stored right justified in this register SPI Module Registers 9 5 7 SPI Serial Transmit Buffer Register SPITXBUF SPITXBUF stores the next character to be transmitted Writing to this register sets the TX BUF FULL Flag bit SPISTS 5 When transmission of the current character is complete the contents of this register are automatically loaded in SPIDAT and the TX BUF FULL Flag is cleared If no transmission is currently active data written to this register falls through into the SPIDAT register and the TX BUF FULL Flag is not set In master mode if no transmission is currently active writing to this register initiates a transmission in the same manner that writing to SPIDAT does Figure 9 13 SPI Serial Transmit Buffer Register SPITXBUF Address 7048h 15 14 13 12 11 10 9 8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bits 15 0 TXB15 TXBO Transmit Data Buffer This is where the next character to be transmitted is stored When the transmission of the current character has com pleted if the TX BUF FULL Flag bit is set the contents of this register is auto matically transferr
261. ced before the original lower priority interrupt as suming both are enabled ISR Latency is the time it takes to get to the specific interrupt service routine ISR code for the event that caused the acknowledged interrupt ISR latency can vary depending on how much context saving is required 2 8 Sample ISR Code Sample ISR Code This sample ISR code illustrates how to branch to an SISR corresponding to a peripheral interrupt No context save is done Timer 1 period interrupt is assumed main code GISR2 This instruction resides at 0004h of PM SISR27s 5 EXIT ISR CLRC RET PIVR gt gt 7h PIVR 0027h SISR27 eq 0E8h 0080h EVIFRA INTM Load the data page containing PIVR Load PIVR value in the accumulator Timer 1 period interrupt Branch to T1PINT if Accumulator 0 Else reload PIVR in the accumulator and continue checking for other peripheral interrupts Execute the ISR specific to T1PINT After executing the SISR clear the flag bit that asserted the interrupt so that future interrupts may be recognized Before exiting the SISR clear the interrupt mode bit System Configuration and Interrupts 2 25 CPU Interrupt Registers 2 9 CPU Interrupt Registers The CPU interrupt registers in the upper level of heirarchy include the following Interrupt flag register IFR _j Interrupt mask register IMR 2 9 1 Interrupt Flag Register IFR The interrupt flag regi
262. ceived successfully This event as serts the Mailbox interrupt LJ Abort Acknowledge Interrupt m A send transmission operation was aborted This event asserts the Error interrupt I Write Denied Interrupt B The CPU tried to write to a mailbox but was not allowed to This event asserts the Error interrupt Wake up Interrupt m After wake up this interrupt is generated This event asserts the Error interrupt even when clocks are not running Receive Message Lost Interrupt B Anold message was overwritten by a new one This event asserts the Error interrupt Bus Off Interrupt B The CAN module enters the bus off state This event asserts the Error interrupt Error Passive Interrupt B The CAN module enters the error passive mode This event asserts the Error interrupt LJ Warning Level Interrupt B One or both of the error counters is greater than or equal to 96 This event asserts the Error interrupt Note While servicing a CAN interrupt the user should check all the bits in the CAN IFR register to ascertain if more than one bit has been set The corresponding interrupt service routines ISRs should be executed for all the set bits This must be done since the core interrupt will be asserted only once even if multiple bits are set in the CAN IFR register CAN Controller Module 10 35 Interrupt Logic 10 6 1 CAN Interrupt Flag Register CAN IFR The interrupt flag bits are set if the correspondi
263. code out of the flash is to program the flash with the code and powering up the DSP in microcomputer mode Since the flash is unsecured after reset provided none of the security conditions are violated the code will function correctly Connecting a JTAG emulator at any time will immediately put the flash into secure mode In addition running the ROM bootloader at reset or having the MP MC pin high at reset also puts the flash into secure mode This functionality keeps hackers from accessing the flash by using the emula tor by trying to bootload code into the device that copies the flash contents to the outside world or by booting up directly into external memory and running code that tries to copy the flash contents to the outside world CSM Frequently Asked Questions E 7 CSM Frequently Asked Questions What is CSM CSM is a security feature incorporated in TMS320Lx240xA DSP controllers It prevents access visibility to on chip Flash ROM memory in program space to unauthorized persons i e it prevents duplication reverse engineering of proprietary code What do the terms secure and unsecure mean Secure means access to on chip flash ROM memory is protected Unsecure means access to on chip flash ROM memory is not protected i e the contents of the flash ROM could be read by any means through a debugging tool such as Code Composer for example Under what conditions is the device unsecure A
264. counter Figure 11 4 WD Timer Control Register WDCR Address 7029h WDFLAG WDDIS WDCHK2 WDCHK1 WDCHKO WDPS2 WDPS1 WDPSO RC x RWc 0 RW 0 RW 0 RW 0 Note R Read access C Clear by writing 1 W Write access Wc Write access conditional on WD OVERRIDE bit being equal to 1 0 value after reset x value after reset determined by action inaction of WD timer Bit 7 WDFLAG Watchdog Flag Bit This bit indicates if a system reset was asserted by the WD timer The bit is set to 1 by a WD generated reset 0 Indicates that the WD timer has not asserted a reset since the bit was last cleared 1 Indicates that the WD timer has asserted a reset since the bit was last cleared Watchdog WD Timer 11 9 Watchdog Control Registers 11 10 Bit 6 Bit 5 Bit4 Bit 3 F7 Note Power on reset POR and WDFLAG The power on reset POR state of the WDFLAG bit is undefined This could cause confusion if the user code attempts to differentiate a watchdog initi ated reset from a power on reset If an application implements a mechanism to differentiate a POR from other types of reset the WDFLAG bit must be cleared after a POR Once this is done the WDFLAG bit can be set only by a watchdog reset LLLLLL AAM WDDIS Watchdog Disable This bit can be written only when the WD OVER RIDE bit in the SCSR2 register is 1 0 Watchdog is enabled 1 Watchdog is dis
265. ctions in the memory F7 Note The procedure here applies to the PC development environment and is giv en only as an example LLLLLLLL MD Figure C 1 Procedure for Generating Executable Files Step 1 Using any ASCII editor create source program test asm and command file 240xA cmd Step 2 Assemble source program dspa test asm v2xx S Output files lest lst error listings test obj assembled file Step 3 Output files l Run linker test out executable file dsplink test obj 240xA cmd o test out m test map map file test map About These Program Examples Table C 1 Common Files For All Example Programs Program 240xA PM cmd 240xA h vector h Functional Description Linker command file that defines the program data and I O memory maps of the target hardware It also locates the various sections in the user code into predetermined segments of memory This cmd file locates user code vectors and text sections in program memory beginning at 0000h Header file that designates labels for the addresses of the various registers File that contains the vectors for various interrupts Table C 2 Program Examples Program SPl asm SCl asm PC_ECHO asm ADC asm GPIO_OUT asm GPIO_IN asm REM_ANS asm REM_REQ asm EV_T1INT asm CAP asm Functional Description Program to output seria
266. cure a device You unsecure a device by executing the following steps 1 Doa dummy read of PWL The word dummy implies that the destina tion address of this read is insignificant Only the read of the PWL is impor tant 2 Write the passwords to the KEY The value of these passwords should al ready be known by the user and should match the value stored in the PWL Should I program all 64 bits of the password For maximum protection it is advisable to program all 64 bits I don t want to use the CSM Can I bypass it There is no way to bypass the CSM in TMS320Lx240xA DSP controllers If code security is not a concern you can program the dummy passwords FFFFFFFFFFFFFFFFh or 0000000000000000h in the PWL I have programmed the PWL with dummy passwords Do I still need to perform dummy reads of the PWL when I am doing JTAG emulation debug A dummy read of the PWL is still essential to gain visibility to on chip flash ROM A write to the KEY is not required In situations where a debugger is used a read of the PWL by the debugger in the disassembly window is sufficient For example right click in the disassembly window select Start Address and enter 0x0040 in the box This will unsecure the on chip ROM FLASH Are there any precautions I should observe while developing code During the code development phase it is a good idea to use the dummy passwords or stick to a single password E 14 CSM
267. d 0005 Illegal Interrupt flag register 0006 Reserved Emulation registers and reserved Illegal 0007 005F 7000 700F On chip DARAM BO System configuration and control registers 7010 701F On chip DARAM B1 Watchdog timer registers 7020 702F Illegal 7030 703F Reserved SPI 7040 704F Illegal SARAM 2K SCI 7050 705F Illegal 7060 706F External interrupt registers 7070 707F Illegal Illegal 7080 708F Digital I O control registers 7090 709F Peripheral frame 1 PF1 ADC control registers 70A0 70BF Peripheral frame 2 PF2 Illegal 70C0 70FF Illegal CAN control registers 7100 710E Illegal 710F 71FF Peripheral frame 3 PF3 CAN mailbox 7200 722F Illegal Code security passwords Illegal Event manager EVA 7230 73FF General purpose timer registers 7400 7408 Reserved Compare PWM and deadband registers 7411 7419 Illegal Capture and QEP registers 7420 7429 Externalt Illegal indicates that access to these addresses causes a nonmaskable interrupt NMI Reserved indicates addresses that are reserved for test Available in LF2407A only Interrupt mask vector and flag registers 742C 7431 Illegal Event manager EVB 7432 743F General purpose timer reg
268. d bit AAn is set and the AAIF bit in the IF register is set The AAIF bit generates an error interrupt if enabled Bits AAn are reset by writing a 1 from the CPU Writing a 0 has no effect If the CPU tries to reset a bit and the CAN tries to set the bit at the same time the bit is set 10 20 Bits 7 4 Bits 3 0 CAN Control Registers TRSn Transmission Request Set for mailbox n In order to initiate a transfer the TRSn bit has to be set in the TCR register After this the entire transmission procedure and possible error handling is done without any CPU involvement If TRSn is set write access to the corresponding mailbox is denied and the message in mailbox n will be transmitted Several TRS bits can be set simultaneously TRS bits can be set by the CPU user or the CAN module and reset by internal logic If the CPU tries to set a bit while the CAN tries to clear it the bit is set TRS bits are set by the user writing a 1 Writing a 0 has no effect In the event of a remote frame request the TRS bits are set by the CAN module for mailboxes 2 and 3 The TRSn bits are reset after a successful or an aborted transmission if an abort is requested A write to a mailbox with TRS set will have no effect and will generate the WDIF interrupt if enabled A successful transmission initiates a mailbox interrupt if enabled TRS bits are used for mailboxes 4 and 5 and also for 2 and 3 if they are configured for transmission
269. d by the QEP circuit Therefore the frequency of the clock generated by the QEP logic to GP timer 2 or 4 is four times that of each input sequence This quadrature clock is connected to the clock input of GP timer 2 or 4 Event Manager EV 6 81 Quaarature Encoder Pulse QEP Circuit Quadrature Encoded Pulse Decoding Example Figure 6 38 shows an example of quadrature encoded pulses and the derived clock and counting direction Figure 6 38 Quadrature Encoded Pulses and Decoded Timer Clock and Direction Quadrature CLK U U DIR MN 6 9 4 QEP Counting GP timer 2 or 4 always starts counting from its current value A desired value can be loaded to the GP timer s counter prior to enabling the QEP mode When the QEP circuit is selected as the clock source the timer ignores the TDIRA B and TCLKINA B input pins GP Timer Interrupt and Associated Compare Outputs in QEP Operation Period underflow overflow and compare interrupt flags for a GP timer with a QEP circuit clock are generated on respective matches A peripheral interrupt request can be generated by an interrupt flag if the interrupt is unmasked 6 9 5 Register Setup for the QEP Circuit To start the operation of the QEP circuit in EVA 1 Load GP timer 2 s counter period and compare registers with desired values 2 Configure T2CON to set GP timer 2 in directional up down mode with the QEP circuits as clock source and enable the selected timer 6 82 Qu
270. d disabled by a system reset 0 Disables transmission Slave mode operation If not previously configured as a general purpose I O pin the SPISOMI pin will be put in the high impedance state Master mode operation If not previously configured as a general purpose I O pin the SPISIMO pin will be put in the high impedance state 1 Enables transmission For the 4 pin option ensure to enable the receiver s SPISTE input pin Bit 0 SPI INT ENA SPI Interrupt Enable This bit controls the SPI s ability to gener ate a transmit receive interrupt The SPI INT FLAG bit SPISTS 6 is unaf fected by this bit 0 Disables interrupt 1 Enables interrupt 9 5 3 SPI Status Register SPISTS SPISTS contains the receive buffer status bits Figure 9 9 SPI Status Register SPISTS Address 7042h 7 6 5 4 0 RECEIVER OVERRUN SPI INT FLAGT TX BUF FULL FLAGt Reserved FLAGT RC 0 RC 0 RC 0 R 0 Note R Read access C Clear 0 value after reset t The RECEIVER OVERRUN FLAG bit and the SPI INT FLAG bit share the same interrupt vector t Writing a 0 to bits 5 6 and 7 has no effect Bit 7 RECEIVER OVERRUN FLAG SPI Receiver Overrun Flag This bit is a read clear only flag The SPI hardware sets this bit when a receive or transmit op eration completes before the previous character has been read from the buff er The bit indicates that the last received character has been overwritten and therefore lost whe
271. d O14 The same transformation can be applied to the demanded voltage vector Ugut to be applied to a motor Figure 6 28 shows the projected vectors and the projected desired motor voltage vector Ug The d axis and q axis of a d q plane correspond here to the horizontal and vertical geometrical axes of the stator of an AC machine The objective of the space vector PWM method is to approximate the motor voltage vector Ugur by a combination of these eight switching patterns of the Six power transistors Event Manager EV 6 63 Space Vector PWM Figure 6 28 Basic Space Vectors and Switching Patterns CCW direction U120 010 Ugo 011 W SVRDIR 0 Tod Uout U380 110 T Up 001 T 38 U 101 a OW direction 140 100 300 101 SVRDIR 1 The binary representations of two adjacent basic vectors are different in only one bit that is only one of the upper transistors switches when the switching pattern switches from Uy to Ux go or from Ux 60 to Ux Also the zero vectors Opoo and O44 apply no voltage to the motor Approximation of Motor Voltage with Basic Space Vectors The projected motor voltage vector Ug at any given time falls into one of the six sectors Thus for any PWM period it can be approximated by the vector sum of two vector components lying on the two adjacent basic vectors Uout T1 Ux T2 Ux 60 To Oooo Or O411 where Tg is given by T5 T4 T2 and Tp is the PWM carrier period The third term on the rig
272. d With Compare Units Other Important Features of Dead Band Units The dead band unit is designed to prevent an overlap under any operating situation between the turn on period of the upper and lower devices controlled by the two PWM outputs associated with each compare unit This includes those situations where you have loaded a dead band value greater than that of the duty cycle and when the duty cycle is 100 or 0 As a result the PWM outputs associated with a compare unit do not reset to an inactive state at the end of a period when dead band is enabled for the compare unit 6 5 3 Output Logic The output logic circuit determines the polarity and or the action that must be taken on a compare match for outputs PWMx for x 1 12 The outputs associated with each compare unit can be specified active low active high forced low or forced high The polarity and or the action of the PWM outputs can be programmed by proper configuration of bits in the ACTR register The PWM output pins can all be put in the high impedance state by any of the following L Software clearing the COMCONX 9 bit L Hardware pulling PDPINTx low when PDPINTx is unmasked _j The occurrence of any reset event Active PDPINTx when enabled and system reset override the bits in COMCONXx and ACTRx Figure 6 24 on page 6 56 shows a block diagram of the output logic circuit OLC The inputs of Output Logic for the compare units are J DTPH1 DTPH1 DTPH2
273. d following reset Only one write is required to initialize COMCONA B not two as on the C240 Each EV module has eight device pins available for compare PWM outputs Two GP timer compare PWM output pins EVA EVB T1CMP T1PWM T3CMP T3PWM T2CMP T2PWM T4CMP T4PWM Six full compare PWM output pins EVA EVB PWM1 PWM7 PWM2 PWM8 PWMS PWM9 PWM4 PWM10 PWM5 PWM11 PWM6 PWM12 The EVA module uses three device pins CAP1 QEP1 CAP2 QEP2 and CAP3 as capture or quadrature encoder pulse inputs The EVB module uses three device pins CAP4 QEP3 CAP5 QEP4 and CAP6 as capture or quadrature encoder pulse inputs The timers in the EV module can be programmed to operate based on an external clock or the internal device clock The device pin TCLKINA B supplies the external clock input The device pin TDIRA B is used to specify the counting direction when a GP timer is in directional up down counting mode The device pins are summarized in Table 6 1 Event Manager A Pins and Table 6 2 Event Manager B Pins Table 6 1 Event Manager A Pins Pin Name CAP1 QEP1 CAP2 QEP2 CAP3 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 T1CMP T1PWM T2CMP T2PWM TCLKINA TDIRA Event Manager EV Functional Blocks Description Capture Unit 1 input QEP circuit input 1 Capture Unit 2 input QEP circuit input 2 Capture Unit 3 input Compare Unit 1 output 1 Compare Unit 1 output 2 Compare Unit 2 output 1 Compare Unit 2 output 2 Compar
274. d output logic are discussed in sections 6 5 2 and 6 5 3 respectively The space vector PWM state machine and the space vector PWM technique are described later in this chapter Figure 6 20 PWM Circuits Block Diagram Compare matches GPT1 flags 6 48 Sym asym waveform generator SVPWM state machine TXCON 12 11 COMCONA 9 Output logic DBTCONA ACTRA dead band full compare COMCONA 12 timer control action control register register PWM1 PWM6 ACTRA 12 15 PWM Circuits Associated With Compare Units The PWM circuits are designed to minimize CPU overhead and user intervention when generating pulse width modulated waveforms used in motor control and motion control applications PWM generation with compare units and associated PWM circuits are controlled by the following control registers T1CON COMCONA ACTRA and DBTCONA in case of EVA and T3CON COMCONB ACTRB and DBTCONB in case of EVB 6 5 1 PWM Generation Capability of Event Manager The PWM waveform generation capability of each event manager module A and B is summarized as follows d Five independent PWM outputs three of which are generated by the compare units the other two are generated by the GP timer compares plus three additional PWM outputs dependent on the three compare unit PWM outputs Programmable dead band for the PWM output pairs associated with the compare units Minimum dead band dura
275. d to get to the event specific interrupt service routine SISR corresponding to the event which caused the PIRQ The code in the GISR should read the PIVR and after saving any necessary context use this value to generate a vector to the SISR Figure 2 6 shows an example of how XINT1 external interrupt in high priority mode generates an interrupt For XINT1 in high priority mode a value of 0001h is loaded into the PIVR register The CPU ascertains the value that was loaded in the PIVR register and uses this value to determine which peripheral caused the interrupt and then branches to the appropriate SISR Such a branch to the SISR could be a conditional branch BCND which is executed on the condition that the PIVR register holds a particular value An alternative scheme would be to left shift the PIVR register by one bit while loading it in the accumulator and adding a fixed offset value Program control could then branch to the address value stored in the accumulator using the BACC instruction This address would point to the SISR System Configuration and Interrupts 2 17 Interrupt Vectors Figure 2 6 Interrupt Requests 1 5 14 13 12 gt Interrupt acknowledge Interrupt controller pores s 14 13 12 Priority 2 5 1 2 18 Flag Bi ft XINT1CR register Priority LEAL EL dede
276. dU S RR 3 8 XMIF Qualifier Signal Description 2 44 4444 3 9 Program and Data Spaces 0 cece ene eens 3 10 l O SpaCes 4 zdra des iar ERE UNS ered ned IEEE nERS UEDSSeObURS qug Pie ded 3 11 Wait State Generation 2 eens 3 11 1 Generating Wait States With the READY Signal 3 11 2 Generating Wait States With the 2407A Wait State Generator 4 Clocks and Low Power Modes 2 lt lt lt lt lt n nnn nnn Describes the PLL CPU and watchdog WD timer clocks C ME UC 42 Phase Locked Loop PLL 00 cece eee eens 42 1 QVGIVIGW 22 002 s00ee ee bb bd dad Oden de uk deaa ED RE Re RE d bau dd us 4 2 2 Operation cuoc Rt RR deda eS god raed xb Rabe qs 42 3 PLL Bypass Mode 348880 ober tnb d added deba 4 3 Watchdog Timer Clock sssssssessssssssse sh 4 38 4 Watchdog Suspend 000 cece e 44 Low Power Modes 2 000 cece n 444 Clock DOMAINS 2e asi ok eS Ia RR pet ada pod K deba E ia 4 4 2 Wake Up From Low Power Modes 0 0 c eee eee eee eee 4 4 3 Powering Down the Flash 0 cece eee 5 Digital Input Output I O lt eee Describes the digital I O ports module 5 1 Digital I O Ports Register Implementation on 240xA Devices 5 2 Contents 5 2 Differences in GPIO Implementation in the 240xA 5 3 O Mux Control Registers n 5 3 1 NO Mux Control Register A lt eee
277. de starts executing the next instruction after the IDLE instruction Case 3 PDPINTA is enabled at peripheral level the corresponding IMR bit is 0 disabled INTM 1 Device does not come out of LPM2 1 Clock to EVA must be enabled in order for PDPINTA to pull the device out of reset 2 When the PDPINTA pin is used to wake up the device from LPM2 it must be held low for 4096 CLKIN cycles 6 or 12 CLKOUT cycles For a device with a 10 MHz CLKIN and 40 MHz 4 10 Low Power Modes CLKOUT this translates into about 410 us The 4096 cycles are required to initiate a clock output to the CPU The remaining 12 cycles trigger a valid PDPINTA interrupt 3 PDPINTA has both a synchronous path and an asynchronous path The asynchronous path is used to wake up from HALT i e the clocks are turned on asynchronously by PDPINTA Once clocks start it generates an interrupt However PDPINTA must be held low long enough for the first clock s edge to catch it 4 4 3 Powering Down the Flash The Flash module can be powered down before entering the LPM2 mode This operation is done while executing code from on chip RAM such as SARAM or BO This mode achieves the lowest possible current consumption Following is the sequence of instructions that powers down the Flash module kkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkxk Flash module power down routine LDP Koh Set DP 0 SPLK 0008h 60h 0008 puts t
278. e CPU following a device reset 4 2 Phase Locked Loop PLL 4 2 1 Overview The PLL used in the 240xA device is different than the one used in the 24x device The 240xA PLL supports multiplication factors ranging from 0 5 to 4 times the input clock frequency This module contains a phased locked loop PLL crystal oscillator clock monitor circuit clock enable circuit and prescaler The purpose of using a PLL is to multiply the external frequency reference to a higher frequency for use internally This avoids having high frequency signals sent to externally packaged pins which could cause excessive EMI PLLs also avoid the use of crystals above 20 25 MHz Such crystals usually operate in overtone mode and require extra tank circuit components The advantages of using a PLL based clock module are 1 Lower EMI due to lower external oscillator frequencies 2 Lower cost crystals and resonators can be used 3 Avoids overtone crystals that require tank circuits The PLL s main disadvantage over a simple oscillator is that they can be sensitive to noise if proper board decoupling layout practices are not adhered to and thus require more system level design effort to insure low jitter robust operation Phase Locked Loop PLL Main features Oscillator operates with both resonators and crystals Covers external CLKIN frequencies from 4 MHz to 20 MHz External low pass loop filter allows maximum flexability and trade of
279. e ID for mailbox 1 lower 16 bits CAN Message ID for mailbox 1 upper 16 bits MBOX 1 RTR and DLC CAN 2 of 8 bytes of Mailbox 1 CAN 2 of 8 bytes of Mailbox 1 CAN 2 of 8 bytes of Mailbox 1 CAN 2 of 8 bytes of Mailbox 1 CAN Message ID for mailbox 2 lower 16 bits CAN Message ID for mailbox 2 upper 16 bits MBOX 2 RTR and DLC CAN 2 of 8 bytes of Mailbox 2 CAN 2 of 8 bytes of Mailbox 2 Programmable Register Address Summary Data Page E2h 226 E2h 226 E2h 226 E2h 226 E2h 226 E2h 226 E4h 228 E4h 228 E4h 228 E4h 228 E4h 228 E4h 228 Page 10 36 10 38 10 17 10 18 10 17 10 18 10 11 10 10 10 11 10 11 10 10 10 11 10 11 10 10 10 11 B 5 Summary of Programmable Registers on the 240xA Table B 1 Summary of Programmable Registers on the 240xA Continued Data Memory Address 7216h 7217h 7218h 7219h 721Ah 721Ch 721Dh 721Eh 721Fh 7220h 7221h 7222h 7224h 7225h 7226h 7227h 7228h 7229h 722Ah 722Ch 722Dh 722Eh 722Fh 7400h 7401h 7402h 7403h Register Mnemonic MBOX2C MBOX2D MSGID3L MSGID3H MSGCTRL3 MBOX3A MBOX3B MBOX3C MBOX3D MSGID4L MSGID4H MSGCTRL4 MBOX4A MBOX4B MBOX4C MBOX4D MSGID5L MSGID5H MSGCTRL5 MBOX5A MBOX5B MBOX5C MBOX5D GPTCONA T1CNT T1CMPR T1PR Register Name CAN 2 of 8 bytes of Mailbox 2 CAN 2 of 8 bytes of Mailbox 2 CAN Message ID for Mailbox 3 lower 16 bits
280. e Unit 3 output 1 Compare Unit 3 output 2 Timer 1 compare PWM output Timer 2 compare PWM output External clock input for timers in EVA External timer direction input in EVA Event Manager EV 6 7 Event Manager EV Functional Blocks Table 6 2 Event Manager B Pins Pin Name Description CAP4 QEP3 Capture Unit 4 input QEP circuit input 3 CAP5 QEP4 Capture Unit 5 input QEP circuit input 4 CAP6 Capture Unit 6 input PWM7 Compare Unit 4 output 1 PWM8 Compare Unit 4 output 2 PWM9 Compare Unit 5 output 1 PWM10 Compare Unit 5 output 2 PWM11 Compare Unit 6 output 1 PWM12 Compare Unit 6 output 2 T3CMP T3PWM Timer 3 compare PWM output T4CMP T4PWM Timer 4 compare PWM output TCLKINB External clock input for timers in EVB TDIRB External timer direction input in EVB 6 1 3 Power Drive Protection Interrupt PDPINTx x A or B The PDPINTx is a safety feature that is provided for the safe operation of systems such as power converters and motor drives PDPINTx can be used to inform the monitoring program of motor drive abnormalities such as over voltage over current and excessive temperature rise If the PDPINTx interrupt is unmasked all PWM output pins will be put in the high impedance state immediately after the PDPINTx pin is driven low An interrupt will also be generated The interrupt flag associated with PDPINTx is also set when such an event occurs however it must wait until the transition on PDPINTx has been qualified
281. e cece eee eee 2 10 2 Peripheral Interrupt Request Registers PIRQRO 1 2 2 10 3 Peripheral Interrupt Acknowledge Registers PIACKRO 1 2 Contents 2 11 2 12 2 13 RESET RP TITEL LETT Illegal Address Detect anessin A AA S External Interrupt Control Registers 2 2 13 1 External Interrupt 1 Control Register XINT1CR 2 13 2 External Interrupt 2 Control Register XINT2CR 3 Memory eee he ee eee ete nas t ooo EO EE mw Eure o ERE e mid Describes the RAM ROM and Flash availability on the 240xA devices 39 1 On Chip RAM lt a ov esc edem adbuc dele ea Ra Aenean ed aont wood woe don d a 3 1 1 Dual Access On Chip RAM sssssssssse n 3 1 2 Single Access On Chip Program Data RAM 3 2 Factory Masked On Chip ROM ssssssesssssssss ee eee eens 9 9 C R O O O V O eL dos 3 89 1 Flash Program Memory ellen 3 3 2 Flash Control Mode Register FCMR k 3 3 8 Flash Control Register Access 0 esses 3 9 4 Flash Programming at Variable Frequencies suele 3 4 Overview of Memory and I O Spaces lt esee 3 5 Program Memory a ssceteme t adasha ses E PIRE REB NER seda METER 3 5 1 Program Memory Configuration asasan eraann 3 6 Dala Memory zssussstecxtunesReiee wesenmireSqeDeREBUPRREUVENEE hee ke Rd 3 6 1 Global Data Memory 20 00 c cece tenet eens Bf MO SP CB z zz e ERR eR ton a ERIS TRE o sadue sean EM
282. e clock source then the min and max CLKIN frequencies are 4 MHz and 40 MHz 30 MHz for 240x devices respectively Watchdog Timer Clock 4 3 Watchdog Timer Clock 4 3 1 A low frequency clock WDCLK is used to clock the watchdog timer WDCLK has a nominal frequency of 78125 Hz when CPUCLK 40 MHz WDCLK is derived from the CLKOUT of the CPU This ensures that the watchdog timer continues to count when the CPU is in IDLE1 or IDLE 2 mode see section 4 4 Low Power Modes on page 4 8 The WDCLK is generated in the watchdog timer peripheral CLKOUT WDCLK 512 Watchdog Suspend WDCLK is stopped when the CPU s suspend signal goes active This is achieved by stopping the clock input to the clock divider which generates WDCLK from CLKIN Clocks and Low Power Modes 4 7 Low Power Modes 4 4 Low Power Modes The 240xA has an IDLE instruction When executed the IDLE instruction stops the clocks to all circuits in the CPU however the clock output from the CPU continues to run With this instruction the CPU clocks can be shut down to save power The CPU exits the IDLE state if it resets or if it receives an interrupt request 4 4 1 Clock Domains 4 8 All 240xA based devices have the following two clock domains j The CPU clock domain consists of the clock for most of the CPU logic The system clock domain consists of the peripheral clock which is derived from CLKOUT of the CPU and the clock for the interrupt logic in
283. e handling Figure 10 13 Receive Control Register RCR Address 7102h 11 RFP3 RFP2 RFP1 RFPO RML3 RML2 RML1 RMLO RC 0 RC 0 RC 0 RC 0 7 6 5 4 3 2 1 0 RC 0 RC 0 RC 0 RC 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access C Clear value following dash value after reset Bits 15 12 RFPn Remote Frame Pending Register for mailbox n Whenever a remote frame request is received by the CAN Peripheral the corresponding bit RFPn is set It may be cleared by the CPU if the TRSn is not set otherwise it is reset automatically If the CPU tries to reset a bit and the CAN Peripheral tries to set the bit at the same time the bit is cleared If the AAM bit in the MSGIDn register is not set and thus no answer is sent automatically the CPU must clear bit RFPn after handling the event If the message is sent successfully RFPn is cleared by the CAN Peripheral The CPU cannot interrupt an ongoing transfer Bits 11 8 RMLn Receive Message Lost for mailbox n If an old message is overwritten by a new one in mailbox n bit RMLn is set RMLn is not set in mailboxes that have the OPCn bit set Thus a message may be lost without notification These bits can only be reset by the CPU and can be set by the internal logic They can be cleared by writing a 1 to RMPn If the CPU tries to reset a bit and the CAN tries to set the bit at the same time the bit is set If one or more RML bits in the RCR register are set the RM
284. e machines and operating flags registers SCICTL2 and SCIRXST to the reset condition The SW RESET bit does not affect any of the configuration bits All affected logic is held in the specified reset state until a 1 is written to SW RESET the bit values following a reset are shown beneath each register diagram in this section Thus after a system reset re enable the SCI by writing a 1 to this bit Clear this bit after a receiver break detect BRKDT flag bit SCIRXST 5 SW RESET affects the operating flags of the SCI but it neither affects the configuration bits nor restores the reset values Once SW RESET is asserted the flags are frozen until the bit is de asserted Table 8 5 lists the affected flags Serial Communications Interface SCI 8 23 SCI Module Registers Table 8 5 SW RESET Affected Flags SCI Flag Register Bit Value After SW RESET TXRDY SCICTL2 7 1 TX EMPTY SCICTL2 6 1 RXWAKE SCIRXST 1 0 IE SCIRXST 2 0 OE SCIRXST 3 0 HE SCIRXST 4 0 BRKDT SCIRXST 5 0 RXRDY SCIRXST 6 0 RX ERROR SCIRXST 7 0 Bit 4 Reserved Reads return zero writes have no effect Bit 3 TXWAKE SCI transmitter wakeup method select The TXWAKE bit controls selection of the data transmit feature depending on which transmit mode idle line or address bit is specified at the ADDR IDLE MODE bit SCICCR 3 0 Transmit feature is not selected 1 Transmit feature selected is dependent on the mode idle line or address bit In idle line mode
285. e ne db C UR E d a TRE OA System Configuration and Interrupts 0 cece eee eee eee Describes the system configuration interrupts and how the peripheral interrupt expansion PIE is used to increase interrupt requests capacity 2 4 Architecture Summary eriin wnei niaaa hn 2 2 Configuration Registers 2 4440 k 2 2 1 System Control and Status Registers 1 and 2 SCSR1 SCSR2 2 2 2 Device Identification Number Register DINR 2 2 3 Interrupt Priority and Vectors III 2 4 Peripheral Interrupt Expansion PIE Controller lt 2 4 4 Interrupt Hierarchy ee n 2 4 2 Interrupt Request Structure 00 0 eee eee 2 4 8 Interrupt Acknowledge cece eee eee eh 2 5 Jlnterr pt VECIOIS used yee eek ee heed Deke u le dir ad DR RB ake decked nes 2 5 41 Phantom Interrupt Vector 00 2 e eee eee eee 2 5 2 Software Hierarchy 0 06 0 cece duta iddaa a aE Sia 2 5 8 Nonmaskable Interrupt NMI 0000 e eee eee ee eee 2 6 Interrupt Operation Sequence 00 ccs 2 lnterrupt Latenoy ss seccideeeit heeiddnenad xor aded Paha Diet eh veo Duker d des 2 8 Sample ISR Code ern 2 9 CPU Interrupt Registers rari seii panii 0c cece een 2 9 1 Interrupt Flag Register IFR eiii redironais 2 9 2 Interrupt Mask Register IMR 0 c cee eee IIR 2 10 Peripheral Interrupt Registers 0 eens 2 10 1 Peripheral Interrupt Vector Register PIVR 000e
286. e not visible active at the same time If the BOOT EN XF pin 0 during reset the BOOT EN bit in SCSR2 register bit 3 will be set and will enable the Boot ROM at 0000 in program space While Boot ROM is enabled the entire Flash memory will be disabled The SCSR2 3 bit should be dis abled 0 to have Flash array enabled instead of Boot ROM See Appendix D for bootloader details TMS320F240x 240xA Boot ROM Loader Protocols and Interfacing D 5 Protocol Definitions D 2 Protocol Definitions The transfer of data is done according to a defined protocol for the SPI and SCI The protocol for the synchronous transfer over the SPI is discussed in section D 2 1 and the protocol for the SCI transfer is discussed in section D 2 2 D 2 1 SPI Synchronous Transfer Protocol and Data Formats D 6 The ROM loader expects an 8 bit wide SPI compatible EEPROM device to be present on the SPI pins as indicated in Figure D 1 Example Hardware Configuration for LF240xA Boot ROM Operation on page D 4 If the download is to be performed from an SPI port on another device then that device must be set up to operate in the slave mode and mimic a serial EEPROM Immediately after entering the SPI loader the pin functions for the SPI pins are set to primary and the SPI is initialized The initialization is done at the slowest speed possible The data transfer is done in burst mode for the EEPROM The transfer is carried out entirely in byte mode SPI at 8 bit
287. e run from BO memory also Program Examples C 17 Program Examples Tr M 9 d File name ADC asm Description PROGRAM TO INITIALIZE THE ADC MODULE OF 240xA This program initializes the ADC module of the 240xA and does a conversion of all the analog input channels The results of the conversion are available in the RESULTSn register which can be accessed by the user application The ADC operates as one 16 state sequencer amp the conversions are stopped once the sequencer reaches EOS End of sequence T ss n m N title ADC bss GPR0 1 General purpose register include 240xA h copy vector h MACRO Definitions KICK DOG macro Watchdog reset macro LDP 00E0h DP gt 7000h 707Fh SPLK 05555h WDKEY SPLK HOAAAAh WDKEY LDP 0h DP gt 0000h 007Fh endm text START LDP 0h Set DP 0 SETC INTM Disable interrupts CLRC SXM SPLK 0000h IMR Mask all core interrupts LACC IFR Read Interrupt flags SACL IFR Clear all interrupt flags LDP 00E0h E0 224 E0 80 7000 SPLK 006Fh WDCR Disable WD SPLK 0080h SCSR1 Enable clock to ADC module KICK DOG SPLK 0h GPRO Set wait state generator for OUT GPRO WSGR Program Space 0 7 wait states Initiali
288. e snippet will work 87FB XXXXX 87FC XXXXX 87FD RET 87FE XXXXX 87FF XXXXX However if the RET instruction is pushed down to 87FE or 87FF an NMI will be asserted System Configuration and Interrupts 2 19 Interrupt Vectors The following code snippet illustrates the behavior of unconditional branch 87FB NOP 87FC B address 87FE XXXXX 87FF XXXXX This will work fine However if the B occupies 87FD or above then NMI will be asserted TBLR and TBLW instructions can operate on data at locations 87FE or 87FF without any issue Interrupt Operation Sequence 2 6 Interrupt Operation Sequence An interrupt generating event occurs in a peripheral Refer to Figure 2 7 for the interrupt responses and flow in each module of the 240xA The interrupt flag IF bit corresponding to that event is set in a register in the peripheral If the corresponding interrupt enable IE bit is set the peripheral generates an interrupt request to the PIE controller by asserting its PIRQ If the interrupt is not enabled the IF remains set until cleared by software If the interrupt is enabled at a later time and the interrupt flag is still set the PIRQ will immediately be asserted If no unacknowledged CPU interrupt request of the same priority level INTn has previously been sent the PIRQ causes the PIE controller to generate a CPU interrupt request INTn This pulse is active low for two CPU clock cycles The interrupt request to the CPU set
289. e two devices A dead time dead band is often inserted between the turning off of one transistor and the turning on of the other transistor This delay allows complete turning off of one transistor before the turning on of the other transistor The required time delay is specified by the turning on and turning off characteristics of the power transistors and the load characteristics in a specific application Event Manager EV 6 57 PWM Waveform Generation With Compare Units and PWM Circuits 6 6 1 Generation of PWM Outputs With Event Manager Each of the three compare units together with GP timer 1 in the case of EVA or GP timer 3 in the case of EVB the dead band unit and the output logic in the event manager module can be used to generate a pair of PWM outputs with programmable dead band and output polarity on two dedicated device pins There are six such dedicated PWM output pins associated with the three compare units in each EV module These six dedicated output pins can be used to conveniently control 3 phase AC induction or brushless DC motors The flexibility of output behavior control by the compare action control register ACTRx also makes it easy to control switched reluctance and synchronous reluctance motors in a wide range of applications The PWM circuits can also be used to conveniently control other types of motors such as DC brush and stepper motors in single or multi axis control applications Each GP timer compare u
290. ed The entire 64K of data memory consists of 512 data pages labeled 0 through 511 The current data page is determined by the value in the 9 bit data page pointer DP in status register STO Each of the 128 words on the current page is referenced by a 7 bit offset taken from the instruction that is using direct addressing Therefore when an instruction uses direct addressing you must specify both the data page with a preceding instruction and the offset in the instruction that accesses data memory An access to the following address spaces in the data memory is illegal and generates an NMI In addition to these addresses an access to any of the reserved addresses within the peripheral register maps is also illegal 0080h 00FFh 0500h 07FFh 710Fh 71FFh inside CAN 7230h 73FFh partly inside CAN 1000h 700Fh 7030h 703Fh 7060h 706Fh 7080h 708Fh 70COh 70FFh 7440h 74FFh 7540h 75FFh 7600h 77EFh 77F4 7FFFh 8000h FFFFh on 2406A 2404A and 2402A only Figure 3 2 2407A Peripheral Memory Map Hex 0000 005F 0060 007F 0080 00FF 0100 01FF 0200 02FF 0300 03FF 0400 04FF 0500 07FF 0800 OFFF 1000 6FFF 7000 73FF 7400 743F 7440 74FF 7500 753F 7540 77EF 77F0 77F3 77F4 77FF 7800 7FFF 8000 FFFF Reserved Memory mapped registers and reserved Reserved Data Memory Hex 0000 0003 Interrupt mask register 0004 On chip DARAM B2 Reserve
291. ed u 188 Jig 41 eui JO 189 9 BIEMYOS JO 19s eq 0 3 Seme uone4euoB 1dnueiu MO 4 J amp Jouduad X NI S8A19981 Add pereJeue si XLNI eAnoedsai y pue jes eq oi sej Ald s1e66u1 Ould Ald 01 pereJeueB OHId Hd Ul L 3l ejqeuo jdnuaju Hd 1e1s1De1 eyeudued ur jas 41 Bey jdnusju SJno90 1dnueiur j eueudue g M0J4 pue esuodsag 1dnuaiu vyxOrz Z z eunbl4 2 23 System Configuration and Interrupts Interrupt Latency 2 7 Interrupt Latency There are three components to interrupt latency 1 Synchronization is the time it takes for the request generated in response to the occurrence of an interrupt generating event to be recognized by the PIE controller and converted into a request to the CPU Core Latency is the time it takes for the CPU to recognize the enabled in terrupt request clear it s pipeline and begin fetching the first instruction from the CPU s interrupt vector table There is a minimum core latency of four CPU cycles If a higher priority maskable interrupt is requested during this minimum latency period it is masked until the ISR for the interrupt be ing serviced re enables the interrupt The latency can be longer than the minimum if the interrupt request occurs during an uninterruptible opera tion for example a repeat loop a multicycle instruction or during a wait stated access If a higher priority interrupt occurs during this additional la tency period itgets servi
292. ed a note to Table 5 4 Changed the first paragraph of Section 6 4 Compare Units Modified Figure 6 12 Compare Unit Block Diagram Modified first paragraph on page 6 40 changing GP timer 2 to GP timer 3 Changed description of Bit 8 of the COMCONA Register Changed description of Bit 8 of the COMCONB Register Corrected register names in Section 6 4 2 Compare Unit Interrupts Modified Figure 6 17 Modified Figure 6 20 Added Section 6 6 56 6 5 Double Update PWM Mode Modified Figure 6 31 Capture Units Block Diagram EVB e 2 N o P 4 e Jj N P 2 N 9 u AR P o o P o 1 00 part ba Moos of o sl AK s J Br e e e X eo m Dv n2 ik N P m A hv x Changes Made in This Revision Additions Modifications Deletions Added a sentence to the fifth second on page 6 71 bullet in Section 6 8 1 Capture Unit Features Added to first paragraph in Section 6 8 2 Operation of Capture Units Changed first paragraph in Section 6 8 3 Capture Unit Registers Changed the CAPQEPN field 14 13 to CAP12EN bit in Figure 6 32 Deleted and QEP circuit from description of Bit 15 in CAPCONA Register Figure 6 32 Changed name and description of Bits 14 13 of CAPCONB Register Figure 6 30 Modified Section 6 9 first paragraph Modified Section 6 9 1 QEP Pins Replaced Figure 6 36 Replaced Figure 6 34 Modified lists in Section 6 9 5 Register Setup for the
293. ed by dividing the desired PWM period by two times the period of the GP timer input clock The GP timer can be initialized the same way as in the previous example During run time the GP timer compare register is constantly updated with newly determined compare values corresponding to the newly determined duty cycles 6 3 5 GP Timer Reset When any RESET event occurs the following happens Lj All GP timer register bits except for the counting direction indication bits in GPTCONAPB are reset to 0 thus the operation of all GP timers is dis abled The counting direction indication bits are all set to 1 Lj All timer interrupt flags are reset to 0 All timer interrupt mask bits are reset to 0 except for PDPINTx thus all GP timer interrupts are masked except for PDPINTx All GP timer compare outputs are put in the high impedance state Compare Units 6 4 Compare Units There are three full compare units compare units 1 2 and 3 in the EVA module and three full compare units compare units 4 5 and 6 in the EVB module Each compare unit has two associated PWM outputs The time base for the compare units is provided by GP timer 1 for EVA and by GP timer 3 for EVB The compare units in each EV module include Three 16 bit compare registers CMPR1 CMPR2 and CMPR3 for EVA and CMPR4 CMPR5 and CMPR6 for EVB all with an associated shad ow register RW One 16 bit compare control register COMCONA fo
294. ed loader operation is more involved than the SPI based loader operation The SCl based loader incorporates a mechanism for baud rate matching Once the baud rate from the host is matched the SCI loader commences the transfer Section D 2 2 1 describes the baud rate protocol D 2 2 1 Baud Rate Protocol The baud rate over the communication link is always 38400 bps The baud rate protocol is necessary because the LF240xA device may be operated at different speeds The underlying assumption for the baud rate matching is that the device is clocked at a clock frequency from a given predetermined set The host is required to send probe characters with the hexadecimal value ODh same as the carriage return character The target listens in on the serial port at the set speeds in succession Every time a character is detected it is compared to ODh If more than three characters do not match the target tries a new baud rate If the baud rate is correct and the character matches ODh then the target expects to receive nine successive ODh characters If any other character is received the baud match fails Once the nine characters are received correctly the target sends an acknowledge character Once the acknowledge character is sent each and every character hereafter is bounced back to the host to ensure data transfer integrity All the communications are with 8 bit characters 1 stop bit and no parity Baud rate locks are possible at clock speeds C
295. ed to SPIDAT and the TX BUF FULL Flag is cleared z O O wss DEEXMMOOA USE Note Writes to SPITXBUF must be left justified Serial Peripheral Interface SPI 9 27 SPI Module Registers 9 5 8 SPISerial Data Register SPIDAT SPIDAT is the transmit receive shift register Data written to SPIDAT is shifted out MSB on subsequent SPICLK cycles For every bit MSB shifted out of the SPI a bit is shifted into the LSB end of the shift register Figure 9 14 SPI Serial Data Register SPIDAT Address 7049h 11 15 14 18 12 10 9 8 SDAT15 SDAT14 SDAT13 SDAT12 SDAT11 SDAT10 SDAT9 SDAT8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bits 15 0 SDAT15 SDATO Serial Data Writing to the SPIDAT performs two functions L It provides data to be output on the serial output pin if the TALK bit SPICTL 1 is set j When the SPI is operating as a master a data transfer is initiated When initiating a transfer see the CLOCK POLARITY bit SPICCR 6 described in section 9 5 1 SPI Configuration Control Register on page 9 19 and the CLOCK PHASE bit SPICTL 3 described in section 9 5 2 SP Operation Control Register on page 9 21 for the requirements In master mode writing dummy data to SPIDAT initiates a receiver sequence Since the data is not hardware justified for characters shorter than sixteen bits
296. effect Bit 10 T1OFINT FLAG GP timer 1 overflow interrupt Read 0 Flag is reset 1 Flagis set Event Manager EV 6 87 Event Manager EV Interrupts Bit 9 Bit 8 Bit 7 Bits 6 4 Bit 3 Bit 2 6 88 Write O No effect 1 Resets flag T1UFINT FLAG GP timer 1 underflow interrupt Read 0 Flag is reset 1 Flagis set Write 0 No effect 1 Resets flag T1CINT FLAG GP timer 1 compare interrupt Read O Flagis reset 1 Flagis set Write O No effect 1 Resets flag T1PINT FLAG GP timer 1 period interrupt Read 0 Flagis reset 1 Flagis set Write O No effect 1 Resets flag Reserved Reads return zero writes have no effect CMP3INT FLAG Compare 3 interrupt Read 0 Flag is reset 1 Flagis set Write 0 No effect 1 Resets flag CMP2INT FLAG Compare 2 interrupt Read 0 Flag is reset 1 Flagis set Write 0 No effect 1 Resets flag Bit 1 Bit 0 Event Manager EV Interrupts CMP1INT FLAG Compare 1 interrupt Read 0 Flag is reset 1 Flagis set Write O No effect 1 Resets flag PDPINTA FLAG Power drive protection interrupt Read 0 Flag is reset 1 Flagis set 0 No effect 1 Resets flag Write EVA Interrupt Flag Register B EVAIFRB Figure 6 40 EVA Interrupt Flag Register B EVAIFRB Address 7430h 15 4 3 2 1 0 FLAG FLAG FLAG FLAG R 0 RW1C 0 RW1C 0 RW1C 0 RW1C 0 Note R Read access W1C Write 1 to clear 0 value after reset Bits 15 4 Reserved Reads return zero writes have no effect
297. egister IFR A 16 bit memory mapped register that indi cates pending interrupts Read the IFR to identify pending interrupts and write to the IFR to clear selected interrupts Writing a 1 to any IFR flag bit clears that bit to O interrupt latency The delay between the time an interrupt request is made and the time it is serviced interrupt mask register IMR A 16 bit memory mapped register used to mask external and internal interrupts Writing a 1 to any IMR bit position enables the corresponding interrupt when INTM 0 interrupt mode bit INTM Bit 9 in status register STO either enables all maskable interrupts that are not masked by the IMR or disables all mask able interrupts interrupt service routine ISR A module of code that is executed in response to a hardware or software interrupt interrupt trap See interrupt service routine ISR Glossary F 7 Glossary interrupt vector A branch instruction that leads the CPU to an interrupt service routine ISR interrupt vector location An address in program memory where an inter rupt vector resides When an interrupt is acknowledged the CPU branches to the interrupt vector location and fetches the interrupt vector INTM bit See interrupt mode bit INTM l O mapped register One of the on chip registers mapped to addresses in I O input output space These registers which include the registers for the on chip peripherals must be accessed with the IN and OUT
298. egister SCIRXST 0 0000 c cece eee eee 8 7 6 Receiver Data Buffer Registers SCIRXEMU SCIRXBUF 8 7 7 Transmit Data Buffer Register SCITXBUF 000222 eee eee 8 7 8 Priority Control Register SCIPRI 0 002 e cece eee eee eee Serial Peripheral Interface SPI 002 c cece eee eee eee ees Describes the architecture functions and programming of the serial peripheral interface SPI module 9 1 C240 SPI vs LF LC240xA SPI 2 ccc arraren 9 1 1 SPI Physical Description 0 ccc eee 9 2 Overview of SPI Module Registers cece eee eee eee 9 3 SPlOperation iius es scu pe ud ARR V anne XOU RUE Rees RU E lec eda 9 3 1 Introduction to Operation 0 ccc ss 9 3 2 SPI Module Slave and Master Operation Modes 9 4 SPI Intermpls 5 s a DR be cee B Aa E ee z jooo tbe ee AAR a Rec du eda 9 414 SPIInterrupt Control Bits ieis aiaei aana a ni iuan iaa aaa aa A Ea 942 DaaFomai zadu Er ARRE EARE LRN ALEE SR Ue eR 9 4 3 Baud Rate and Clocking Schemes lt 9 44 SPI Clocking Schemes cc cece eee ented 9 45 Initialization Upon Reset 02 0 c cece eee eee eee 9 4 Data Transfer Example lt el 9 5 SPI Module Registers niaii aE DEAE hn 9 5 1 SPI Configuration Control Register SPICCR 0222 eee 9 5 2 SPI Operation Control Register SPICTL 0c cece 9 5 3 SPI Status Register SPISTS 0 cee ceed 9 5 4 SPI Ba
299. egister EOh 224 8 28 7056h SCIRXEMU SCI Emulation Data Buffer Register EOh 224 8 31 7057h SCIRXBUF SCI Receiver Data Buffer Register EOh 224 8 31 7059h SCITXBUF SCI Transmit Data Buffer Register EOh 224 8 31 705Fh SCIPRI SCI Priority Control Register EOh 224 8 32 External Interrupt 7070h XINT1CR External Interrupt 1 Control Register EOh 224 2 39 7071h XINT2CR External Interrupt 2 Control Register EOh 224 2 40 Digital I O 7090h MCRA I O Mux Control Register A Eth 225 5 4 7092h MCRB I O Mux Control Register B E1h 225 5 5 7094h MCRC I O Mux Control Register C E1h 225 5 7 7098h PADATDIR Port A Data and Direction Control E1h 225 5 8 Register 709Ah PBDATDIR Port B Data and Direction Control E1h 225 5 9 Register 709Ch PCDATDIR Port C Data and Direction Control E1h 225 5 10 Register 709Eh PDDATDIR Port D Data and Direction Control Eth 225 5 11 Register 7095h PEDATDIR Port E Data and Direction Control E1h 225 5 12 Register 7096h PFDATDIR Port F Data and Direction Control Eth 225 5 13 Register Analog to Digital Converter ADC 10 Bit 70A0h ADCTRL1 ADC Control Register 1 E1h 225 7 20 70A1h ADCTRL2 ADC Control Register 2 E1h 225 7 26 70A2h MAX CONV Maximum Conversion Channels E1h 225 7 31 Register 70A3h CHSELSEQ1 Channel Select Sequencing Control Eth 225 7 35 Register 1 70A4h CHSELSEQ2 Channel Select Sequencing Control Eth 225 7 35 Register 2 Programmable Register Address Summary B 3 Sum
300. either an internal loopback or an external loopback depending on the value written in SCICCR SCITXD SCIRXD pins should be connected together if external loopback is desired This is not required for an internal loopback The SCI receives the bit stream and stores the received data in memory 60h and above for verification An 8 bit value is transmitted through the SCITXD pin at a baud rate of 9600 bits sec A counter is used to determine how many times data is transmitted and received This code is useful to determine the health of the SCI hardware quickly without the aid of any other equipment include 240x KICK DOG macro Watchdog reset macro LDP 00EOh SPLK 05555h WDKEY SPLK HOAAAAh WDKEY LDP Koh endm MAIN CODE starts here text START LDP 0 SETC INTM Disable interrupts LDP 00E0Oh SPLK 0040h SCSR1 Enable clock for SCI module SPLK 006Fh WDCR Disable WD KICK DOG SPLK 0h 60h Set wait state generator for OUT 60h WSGR Program Space 0 7 wait states SCI TRANSMISSION TEST starts here SCI LDP KOElh SPLK 0003h MCRA LAR ARO SCITXBUF Load ARO with SCI_TX_BUF address LAR AR1 SCIRXBUF Load AR1 with SCI RX BUF address LAR AR2 1Fh AR2 is the counter LAR AR3 60h AR3 is the pointer LDP SCICCR gt gt 7 SPLK 17h SCICCR 17 for internal loopback 07 External 1 stop bit odd parity 8 char bits async mode idle line protocol SPLK 0003
301. eived a message successfully Each of the six mailboxes may initiate an interrupt These interrupts can bea receive or a transmit interrupt depending on the mailbox configuration If one of the configurable mailboxes is configured as Remote Request Mailbox AAM set and a remote frame is received a transmit interrupt is set after sending the corresponding data frame If a remote frame is sent a receive interrupt is set after the reception of the desired data frame 10 36 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Interrupt Logic There is one interrupt mask bit for each mailbox If a message is received the corresponding RMPn bit in the RCR is set If a message is sent the corresponding TAn bit in the TCR register is set The setting of the RMPn bit or the TAn bit also sets the appropriate MIFx flag in the CAN IFR register if the corresponding interrupt mask bit is set The MIFx flag generates an interrupt The MIMx mask bits in the CAN IMR register determine if an interrupt can be generated by a mailbox Reserved RMLIF Receive Message Lost Interrupt Flag 0 No message was lost 1 An overflow condition has occurred in at least one of the receive mailboxes AAIF Abort Acknowledge Interrupt Flag 0 No transmission was aborted 1 A send transmission operation was aborted WDIF Write Denied Interrupt Flag 0 The write access to the mailbox was successful 1 The CPU tried to write to a mailbox but wa
302. er A EVAIFRA Address 742Fh EVA Interrupt Flag Register B EVAIFRB Address 7430h EVA Interrupt Flag Register C EVAIFRC Address 7431h sss EVA Interrupt Mask Register A EVAIMRA Address 742Ch EVA Interrupt Mask Register B EVAIMRB Address 742Dh EVA Interrupt Mask Register C EVAIMRC Address 742Eh EVB Interrupt Flag Register A EVBIFRA Address 752Fh s sss EVB Interrupt Flag Register B EVBIFRB Address 7530h EVB Interrupt Flag Register C EVBIFRC Address 7531h lusus EVB Interrupt Mask Register A EVBIMRA Address 752Ch EVB Interrupt Mask Register B EVBIMRB Address 752Dh EVB Interrupt Mask Register C EVBIMRC Address 752bEh Luuuuue Block Diagram of Autosequenced ADC in Cascaded Mode Luuuuuuu Block Diagram of Autosequenced ADC With Dual Sequencers nnana Flow Chart for Uninterrupted Autosequenced Mode Example of Event Manager Triggers to Start the Sequencer 000004 Interrupt Operation During Sequenced Conversions 0cc cece cece eee ADC Conversion Time sssssssseeseses es Clock Prescalers in 240xA ADC nee teen eens Calibration Register Address 70B8h wo tenet eens ADC Control Register 1 ADCTRL1 Address 70A0h 0 0 0 0 eee eee ADC Control
303. er Status Register SCIRXST Address 7055h 7 6 5 4 3 2 1 0 ERROR R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Note R Read access W Write access 0 value after reset Bit 7 RX ERROR SCI receiver error flag The RX ERROR flag indicates that one of the error flags in the receiver status register is set RX ERROR is a logical OR of the break detect framing error overrun and parity error enable flags bits 5 2 BRKDT FE OE and PE 0 No error flags set 1 Error flag s set A 1 on this bit will cause an interrupt if the RX ERR INT ENA bit SCICTL1 6 is set This bit can be used for fast error condition checking during the interrupt service routine This error flag cannot be cleared directly it is cleared by an active SW RESET or by a system reset Bit 6 RXRDY SCI receiver ready flag When a new character is ready to be read from the SCIRXBUF register the receiver sets this bit and a receiver interrupt is generated if the RX BK INT ENA bit SCICTL2 1 is a 1 RXRDY is cleared by a reading of the SCIRXBUF register by an active SW RESET or by a system reset 0 No new character in SCIRXBUF 1 Character ready to be read from SCIRXBUF Bit 5 BRKDT SCI break detect flag The SCI sets this bit when a break condition occurs A break condition occurs when the SCI receiver data line SCIRXD remains continuously low for at 8 28 Bit 4 Bit 3 Bit 2 SCI Module Registers least ten bits beginning after a missing first stop bit
304. er register SCITXBUF and shift register TXSHF An active SW RESET SCICTL1 2 or a system reset sets this bit This bit does not cause an interrupt request 0 Transmitter buffer or shift register or both are loaded with data 1 Transmitter buffer and shift registers are both empty Bits 5 2 Reserved Reads return zero writes have no effect Bit 1 RX BK INT ENA Receiver buffer break interrupt enable This bit controls the interrupt request caused by eitherthe RXRDY flag orthe BRKDT flag bits SCIRXST 6 and 5 being set However RX BK INT ENA does not prevent the setting of these flags 0 Disable RXRDY BRKDT interrupt 1 Enable RXRDY BRKDT interrupt Bit 0 TX INT ENA SCITXBUF register interrupt enable This bit controls the interrupt request caused by setting the TXRDY flag bit SCICTL2 7 However it does not prevent the TXRDY flag from being set being set indicates that register SCITXBUF is ready to receive another character Serial Communications Interface SCI 8 27 SCI Module Registers 0 Disable TXRDY interrupt 1 Enable TXRDY interrupt 8 7 5 Receiver Status Register SCIRXST SCIRXST contains seven bits that are receiver status flags two of which can generate interrupt requests Each time a complete character is transferred to the receiver buffers SCIRXEMU and SCIRXBUF the status flags are updated Figure 8 16 on page 8 30 shows the relationships between several of the register s bits Figure 8 15 Receiv
305. erations for devices with and without code security E 4 1 Case 1 Device With Code Security A device with code security should have a predetermined password stored in the PWL locations 0040h through 0043h in program memory The following are steps to unsecure this device 1 Perform a dummy read of the PWL 2 Write the password into the KEY registers locations 77FOh through 77F3h in data memory 3 If the password is correct the device becomes unsecure otherwise it stays secure E 4 2 Case 2 Device Without Code Security A device without code security should have 0000 0000 0000 0000h or FFFF FFFF FFFF FFFFh stored in the PWL The following are steps to use this device 1 Perform a dummy read of the PWL 2 The device can be used soon after this operation is completed Note A dummy read operation must be performed prior to using the device even though the device is not protected with a password Flash ROM Code Security For LF LC240xA DSP Devices E 9 DOs and DON Ts to Protect Security Logic E 5 DOs and DON Ts to Protect Security Logic E 5 1 DOs E 5 2 DON Ts E 10 To keep the debug and code development phase simple use the device in the unsecure mode i e use 0000 0000 0000 0000h or FFFF FFFF FFFF FFFFh as PWL words or use a password that is easy to remember Use passwords after the development phase when the code is frozen Recheck the passwords in PWL before programming the COFF file using
306. eripheral Interrupt Registers Bits 15 0 IACKO0 15 IACKO O Peripheral interrupt acknowledge bits Writing a one causes the corresponding peripheral interrupt acknowledge to be asserted which clears the corresponding peripheral interrupt request Note that assert ing the interrupt acknowledge by writing to this register does not update the PIVR Reading the register always returns zeros Table 2 6 Peripheral Interrupt Acknowledge Descriptions PIACKRO Bit position Interrupt Interrupt Description Interrupt Level IAK 0 0 PDPINT Power device protection interrupt pin INT1 IAK 0 1 ADCINT ADC interrupt High priority INT1 IAK 0 2 XINT1 External interrupt pin 1 High priority INT1 IAK 0 3 XINT2 External interrupt pin 2 High priority INT1 IAK 0 4 SPIINT SPI interrupt High priority INT1 IAK 0 5 RXINT SCI receiver interrupt High priority INT1 IAK 0 6 TXINT SCI transmitter interrupt High priority INT1 IAK 0 7 CANMBINT CAN mailbox interrupt High priority INT1 IAK 0 8 CANERINT CAN error interrupt High priority INT1 IAK 0 9 CMP1INT Compare 1 interrupt INT2 IAK 0 10 CMP2INT Compare 2 interrupt INT2 IAK 0 11 CMP3INT Compare 3 interrupt INT2 IAK 0 12 T1PINT Timer 1 period interrupt INT2 IAK 0 13 T1CINT Timer 1 compare interrupt INT2 IAK 0 14 T1UFINT Timer 1 underflow interrupt INT2 IAK 0 15 T1OFINT Timer 1 overflow interrupt INT2 ME 2 15 b dui A 1 oua 1 Adaress 7015h IAK1 14 1AK1 43 1AK1 12 JAK1 11 IAK1 10 IAK1 9 IAK1 8 RW 0 R
307. errupt acknowledge register 1 PIACKR1 peripheral interrupt acknowledge register 2 PIACKR2 peripheral interrupt expansion PIE controller block diagram interrupt acknowledge hierarchy request structure peripheral interrupt registers peripheral interrupt request descriptions PIRQRO PIROR1 PIRQR2 peripheral interrupt request register 0 PIRQRO peripheral interrupt request register 1 PIRQR1 peripheral interrupt request register 2 PIRQR2 peripheral interrupt vector register PIVR peripheral memory map 2407A PFDATDIR port F data and direction control register pin designation table PFDATDIR port F data and direction control register phantom interrupt vector phase locked loop PLL 4 2 operation external oscillator loop filter components power and ground connections figure power connections reference resonator crystal figure resonator crystal oscillator terms applicable to the PLL module PIACKRO peripheral interrupt acknowledge register 0 Index 13 Index PIACKR1 peripheral interrupt acknowledge register 1 PIACKR2 peripheral interrupt acknowledge register 2 PIE peripheral interrupt expansion controller block diagram interrupt acknowledge hierarchy request structure pin configuration shared pin configuration digital I O ports register implementation pins event manager EV event manager A EVA pins 6 7 event manager B EVB pins 6 8 PIRQRO peripheral i
308. errupt controller and this SISR performs the required actions in response to the peripheral interrupt request The GISR must read the peripheral interrupt vector from the PIVR before interrupts are re enabled All interrupts are automatically disabled when an interrupt is taken If the PIVR is not read before interrupts are re enabled and another interrupt is asserted a new peripheral interrupt vector will be loaded into the PIVR causing permanent loss of the original peripheral interrupt vector Nonmaskable interrupts such as reset and NMI are not part of PIE The PIE controller does not support expansion of nonmaskable interrupts 2 5 3 Nonmaskable Interrupt NMI The 240xA devices do not have an NMI pin like the 240 or 241 242 243 devices NMI will be asserted when access to any illegal address is made When NMI is asserted the code will branch to 0024h in program memory which is the NMI vector There is no control register corresponding to the NMI feature The following caution should be observed while using the SARAM on 240xA devices that lack an external memory interface XMIF The last 2 words in SARAM cannot be used to store a RET or Branch instruction This is because when a RET or Branch instruction reaches the execute phase of the pipeline the next two instruction words have already been fetched Since addresses 8800h and above are illegal in 240xA devices that lack XMIF this asserts an NMI As an example the following cod
309. errupts See Table 2 2 240xA Interrupt Source Priority and Vectors on page 2 9 for priority and vector values CPU response On receipt of an INT1 2 3 or 4 interrupt request the re spective bit in the CPU interrupt flag register IFR will be set If the corres ponding interrupt mask register IMR bit is set and INTM bit is cleared then the CPU recognizes the interrupt and issues an acknowledgement to the PIE Following this the CPU finishes executing the current instruc tion and branches to the interrupt vector corresponding to INT1 2 3 or 4 At this time the respective IFR bit will be cleared and the INTM bit will be set disabling further interrupt recognition The interrupt vector contains a branch instruction for the interrupt service routine From here the inter rupt response is controlled by the software PIE response The PIE logic uses the acknowledge signal from the core to clear the PIRQ bit that issued the CPU interrupt Along with this the PIE updates its PIVR register with the interrupt vector unique to the peripheral interrupt that was just acknowledged After this the PIE hardware works in parallel to the current interrupt software to generate a CPU interrupt and other pending interrupts if any nterrupt software The interrupt software has two levels of response m Level 1 GISR In the first level the software should do any context save and read the PIVR register from PIE module to decide which in terr
310. erved IOPD3 Reserved IOPD4 Reserved IOPD5 Reserved IOPD6 Reserved IOPD7 Reserved Figure 5 9 Port E Data and Direction Control Register PEDATDIR 15 14 13 12 11 10 9 8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW x T The reset value of these bits depends upon the state of the respective pins Note R Read access W Write access 0 value after reset x undefined Bits 15 8 EnDIR 0 Configure corresponding pin as an input 1 Configure corresponding pin as an output Bits 7 0 IOPEn If EnDIR 0 then 0 Corresponding I O pin is read as a low 1 Corresponding I O pin is read as a high Data and Direction Control Registers If EnDIR 1 then 0 Set corresponding I O pin low 1 Set corresponding I O pin high Table 5 9 PEDATDIR VO Pin Designation Assuming Pins Have Been Selected as I O i e Secondary Function VO Port Data Bit Pin Name IOPEO CLKOUT IOPEO IOPE1 PWM7 IOPE1t IOPE2 PWM8 IOPE2 IOPE3 PWM9 IOPE3 IOPE4 PWMt10 IOPE4T IOPE5 PWM11 IOPE5t IOPE6 PWM12 IOPE6t IOPE7 CAPA QEP3 IOPE7T T These pins are not available on 2402A devices Figure 5 10 Port F Data and Direction Control Register PFDATDIR 15 14 13 12 11 10 9 8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 T 6 5 4 3 2 1 0 RW RW RW RW RW RW RW The reset value of these bits depends upon the state of the respective pins Note R Read access W Write access 0 value afte
311. es not send or receive any messages The module is not active on the CAN bus line Acknowledge flags and error flags are not sent The error counters and all other internal registers are frozen Suspend is only asserted when a system is being debugged with an in circuit emulator In case the module is in bus off mode when suspend mode is requested it enters suspend mode immediately It does however still count the 128 x 11 recessive bits needed to return to the bus on mode All error counters are undefined in that state The bus off flag and the error passive flag are set The module leaves the suspend mode when the SUSPEND signal is deactivated It waits for the next 11 recessive bits on the bus and goes back to normal operation This is called the idle mode different from the CPU s IDLE mode The module waits for the next message or tries to send one itself When the module is in bus off mode it continues to wait for the bus on condition This occurs when 128 x 11 recessive bits are received It also counts those that occurred during the suspend mode Note The clock is not switched off internally for suspend or low power mode For easy reference Table 10 5 provides a listing of the CAN notation definition and register and bit number CAN Controller Module 10 41 Suspend Mode Table 10 5 CAN Notation Notation Signification Register Bit No AA Abort Acknowledge TCR 11 8 AAIF Abort Acknowledge Interrupt Flag CAN_IFR 5 AAIM Ab
312. es only to the last conversion in a sequence Each category is listed in Table 7 9 with the number of CLKOUT cycles it takes to complete Table 7 9 ADC Conversion Phases vs CLKOUT cycles Datasheet No Conversion CLKOUT cycles CLKOUT cycles menclature phase CPS 0 CPS 1 ta soc sH SOS synch 2 2 or 3t tw SH ACQ 2t 4t tw C CONV 10 20 EOC 1 2 d EOC EOS 1 1 TWhen CPS 1 a start of sequence can take an extra CLKOUT cycle to sync up with the ADC clock ADCCLK depending on which cycle the SOC bit is set in software t The ACQ value is dependent on the ACQ PSn bits Values shown in Table 7 9 are applicable when ACQ PS 0 As an example values for ACQ when ACQ PS 1 2 and 3 are shown in Table 7 10 This table can be extrapolated for all ACQ PS values Table 7 10 ACQ Values When ACQ PS 1 2 and 3 ACQ PS CPS 0 CPS 1 1 ACQ 4 ACQ 8 2 ACO 6 ACO 12 3 ACO 8 ACO 16 ADC Conversion Clock Cycles Example 7 4 Calculating the Conversion Time for a Multiple Conversion Sequence With CPS 0 and ACQ 0 1st conversion 15 CLKOUT cycles 2nd conversion 13 CLKOUT cycles 3rd conversion 13 CLKOUT cycles Last conversion 14 CLKOUT cycles Example 7 5 Calculating the Conversion Time for a Single Conversion Sequence With CPS 1 and ACQ 1 1st and only conversion 33 or 34 CLKOUT cycles Analog to Digital Converter ADC 7 39 7 40 Chapter 8 Serial Communications Interface SCI This ch
313. es the address for each write to data memory data write bus DWEB A 16 bit internal bus that carries data to both program memory and data memory decode phase The phase of the pipeline in which the instruction is decoded See also pipeline instruction fetch phase operand fetch phase instruction execute phase direct addressing One of the methods used by an instruction to address data memory In direct addressing the data page pointer DP holds the nine MSBs of the address the current data page and the instruction word provides the seven LSBs of the address the offset See also indirect addressing DP See data page pointer DP DRAB See data read address bus DRAB DRDB See data read bus DRDB DS Data memory select pin The 24x asserts DS to indicate an access to external data memory local or global DSWS Data space wait state bit s A value in the wait state generator control register WSGR that determines the number of wait states applied to reads from and writes to off chip data space dual access RAM See DARAM dummy cycle A CPU cycle in which the CPU intentionally reloads the program counter with the same address DWAB See data write address bus DWAB DWEB See data write bus DWEB execute phase The fourth phase of the pipeline the phase in which the instruction is executed See also pipeline instruction fetch phase instruction decode phase operand fetch phase external interrupt A
314. eset The check bits are always read as zeros 0002 regardless of what value has been written to them The WD timer operates independently of the CPU and is always enabled It does not need any CPU initialization to function When a system reset occurs the WD timer defaults to the fastest WD timer rate available 3 28 ms for a 78125 Hz WDCLK signal As soon as reset is released internally the CPU starts executing code and the WD timer begins incrementing This means that to avoid a premature reset WD setup should occur early in the power up sequence Watchdog WD Timer 11 7 Watchdog Control Registers 11 3 Watchdog Control Registers The WD module control registers are shown in Table 11 2 and discussed in detail in the sections that follow the table Table 11 2 WD Module Control Registers Bit Number Register Address mnemonic 7 6 5 4 3 2 1 0 7020h Reserved 7021h Reserved 7022h Reserved 7023h WDCNTR 7024h Reserved 7025h WDKEY 7026h Reserved 7027h ne Reserved 7028h Reserved 7029h 11 3 1 WD Counter Register The 8 bit WD counter register WDCNTR contains the current value of the WD counter This register continuously increments at a rate selected through the WD control register When WDCNTR overflows an additional single cycle delay either WDCLK or WDCLK divided by a prescale value is incurred before system reset is asserted Writing the proper sequence to
315. est Receive Error Counter Remote Frame Pending Receive Mode Receive Message Lost Receive Message Lost Interrupt Flag Receive Message Lost Interrupt Mask Receive Message Pending Remote Transmission Request Stuck at Dominant Error Sample Point Setting Synchronization on Both Edge Stuff Error Synchronization Jump Width Suspend Mode Acknowledge Self Test Mode Action on Emulator Suspend Transmission Acknowledge Transmit Error Counter Transmit Mode Transmission Request Set Transmission Request Reset Time Segment 1 Time Segment 2 Write Denied Interrupt Flag Write Denied Interrupt Mask Warning Level Interrupt Flag Warning Level Interrupt Mask Wake Up on Bus Activity Wake Up Interrupt Flag Wake Up Interrupt Mask CAN Controller Module Suspend Mode Register CAN_IMR RCR GSR MCR CEC RCR GSR RCR CAN_IFR CAN_IMR RCR MSGCTRLn ESR BCR1 BCR1 ESR BCR1 GSR MCR MCR TCR CEC GSR TCR TCR BCR1 BCR1 CAN IFR CAN IMR CAN IFR CAN IMR MCR CAN IFR CAN IMR Bit No 13 8 3 0 3 11 7 0 15 12 1 11 8 6 6 74 4 6 7 10 9 8 13 15 12 15 8 74 3 0 6 3 2 0 w w O O O A 10 43 Suspend Mode Table 10 6 Mailbox RAM Layout Register Databyte MSG IDOH Reserved Databyte 3 Databyte 2 Databyte 2 Databyte 1 Databyte 7 Databyte 6 Databyte 4 Databyte 5 MSG ID1H Reserved Databyte 0 Databyte 1 Databyte 3 Databyte 2 Databyte 4 Databyte 5 Databyte 7 Databyte 6 DBO
316. ext program address register definition on chip RAM dual access on chip RAM DARAM 3 2 single access on chip program data RAM SARAM 3 2 on chip memory advantages OPCn overwrite protection control for mailbox n 10 23 oscillator and PLL 240xA devices frequency input specification pin names output logic compare match for outputs PWMx compare operation GP timer overview 240xA device graphical overview peripherals 1 5 TMS320 family PADATDIR port A data and direction control register I O pin designation table PADATDIR port A data and direction control register 5 8 PAR program address register definition password match flow PMF code security PBDATDIR port B data and direction control register I O pin designation table PBDATDIR port B data and direction control register 53 PCDATDIR port C data and direction control register I O pin designation table PCDATDIR port C data and direction control register PDDATDIR port D data and direction control register I O pin designation table PDDATDIR port D data and direction control register PEDATDIR port E data and direction control register I O pin designation table Index PEDATDIR port E data and direction control register peripheral clock enable bits 240xA devices peripheral interrupt acknowledge descriptions PIACKRO PIACKR1 2 36 P 37 PIACKR2 peripheral interrupt acknowledge register 0 PIACKRO peripheral int
317. f between acquisition time and noise immunity Phase frequency detector assures lock to the fundamental reference frequency Terms applicable to the PLL module LI L Charge Pump CP a circuit used to convert the pulse width modulated correction signals into an analog control voltage Electro Magnetic Interference EMI the radio freguency noise radiated by a circuit which could disturb the proper operation of other eguipment the radio freguency noise radiated by other eguipment which could disturb the proper operation of the subject circuit Jitter The maximum positive or negative deviation of a clock edge with respect to it s normal position within a single clock period expressed in nanoseconds or in percent of one clock period Lock The condition in which the PLL s output is synchronized to the phase and frequency of it s reference input Phase Frequency Detector PFD a circuit which compares two signals in both phase and frequency It is not fooled by one signal being a harmonic or sub harmonic of the other signal Phase Locked Loop PLL an oscillator circuit whose output frequency is typically an integer multiple of it s reference input frequency Voltage Controlled Oscillator VCO an oscillator whose output frequency is proportional to a control voltage input Clocks and Low Power Modes 4 3 Phase Locked Loop PLL 4 2 2 Operation The sections that follow describe the operation and operating mode
318. f SCI Registers Address 7050h 7051h 7052h 7053h 7054h 7055h 7056h 7057h 7058h 7059h 705Ah 705Bh 705Ch 705Dh 705Eh 705Fh 8 6 Symbol SCICCR SCICTL1 SCIHBAUD SCILBAUD SCICTL2 SCIRXST SCIRXEMU SCIRXBUF SCITXBUF SCIPRI Name SCI communication control register SCI control register 1 SCI baud select register high bits SCI baud select register low bits SCI control register 2 SCI receiver status register SCI emulation data buffer register SCI receiver data buffer register Illegal SCI transmiter data buffer register Illegal Illegal Illegal Illegal Illegal SCI priority control register Description Defines the character format pro tocol and communications mode used by the SCI Controls the RX TX and receiver error interrupt enable TXWAKE and SLEEP functions and the SCI software reset Stores the data MSbyte required to generate the bit rate Stores the data LSbyte required to generate the bit rate Contains the transmitter interrupt enable the receiver buffer break interrupt enable the transmitter ready flag and the transmitter empty flag Contains seven receiver status flags Contains data received for screen updates principally used by the emulator Not a real register just an alternate address for reading SCIRXBUF without clearing RXRDY Contains the current data from the receiver shift register
319. f the SPICLK sig nal Rising Edge With Delay The SPI transmits data one half cycle ahead of the rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal Serial Peripheral Interface SPI 9 13 SPI Interrupts The selection procedure for the SPI clocking scheme is shown in Table 9 2 Examples of these four clocking schemes relative to transmitted and received data are shown in Figure 9 3 Table 9 2 SPI Clocking Scheme Selection Guide CLOCK POLARITY CLOCK PHASE SPICLK Scheme SPICCR 6 SPICTL 3 Rising edge without delay 0 0 Rising edge with delay 0 1 Falling edge without delay 1 0 Falling edge with delay 1 1 Figure 9 3 SPICLK Signal Options SPICLK cycle 1 2 3 4 5 6 7 8 number SPICLK Vo r AA SNA WINANS NS NL without delay SPICLK with delay SPICLK uus NF NLS NS NS NT NS NS E T without delay SPICLK ao ou Nel OY A U RA DU Ni Ned with delay SPISIMO PISMO em MSB C X X X X X XE SPISTE Into slave N Receive latch points Note Previous data bit 9 14 SPI Interrupts For the SPI SPICLK symmetry is retained only when the result of SPIBRR 1 is an even value When SPIBRR 1 is an odd value and SPIBRR is greater than 3 SPICLK becomes asymmetrical The low pulse of SPICLK is one CLKOUT longer than the high pulse when the CLOCK POLARITY bit is clear 0 When the CLOCK POLARITY bit is set to 1 the high pulse
320. f the WD timer once system reset is released A WD prescale with six selections from the 6 bit free running counter Figure 11 1 shows a block diagram of the WD module Watchdog Timer Features Figure 11 1 Block Diagram of the WD Module 6 bit free 64 running counter 324 WDCLK 16 8t _ At 2t Register Name WDCNTR Watchdog Counter Register WD prescale dienen bits WDKEY Watchdog Reset Key Register WDCR Watchdog Control Register WDCR 2 0 WDPS2 0 6 WDCR 6 WD FLAG WDONTR 7 0 8 bit watchdog counter CLR WDDIS Prescale WDKEY 7 0 selection Bad key Watchdog 2 reset key Good register PS 257 System reset request WDCHK2 0 WDCR 5 3t Bad WDCR key 3 System reset T 3 Constant value T Writing to bits WDCR 5 3 with anything but the correct pattern 101 generates a system reset These prescale values are with respect to the WDCLK signal Watchdog WD Timer 11 3 Watchdog Timer Operations 11 2 Watchdog Timer Operations 11 2 1 Overview of WD Timer Operations Three registers control the WD operations g WD Counter Register WDCNTR This register contains the value of the WD counter _ WD Key Register WDKEY This register clears the WDCNTR when a 55h value followed by an AAh value is written to WDKEY WD Control Register WDCR This register contains the followin
321. f the user code does anything which disturbs the transmission of the SCI then that last character may be lost An example is changing the bit definition of the SCI transmit pin If this is allowed the host must take this fact into account A second possible option is to incorporate a small delay in the user code or perform an SCI check to confirm that the character transmission is complete Protocol Definitions Figure D 4 Flowchart for the Serial Loader Baud Rate Match Algorithm Initialize Baud Rate Parameters Clear VBR COUNTER Listen for a character Is the RX flag set Y Fetch character Is Char 0x0D Y Increment VBR Is VBR max Y Send 0xAA to host TMS320F240x 240xA Boot ROM Loader Protocols and Interfacing D 9 Protocol Definitions Figure D 5 Flowcharts for Serial Asynchronous Loader and the Fetch Header Routine FETCH HEADER Get user code from the host XFER SCI 2 PROG Branch to user code D 10 Protocol Definitions Figure D 6 Flowchart for FETCH SCI WORD Has a character been received Echo Byte to Host Y Store Lower Byte Has a character been received Store High Byte Echo Byte to Host Form the word LE PRR RR RRR KK ce ke ke e he ke ke he he ke e he ke ke e he K he e ke K he e e he ke A ce he ke K he he A K he K e he RRR he ke e he ke che he ke e he kc ke ce he ke e he ke e e e e TMS3
322. ffect See Section 6 2 Event Manager EV Register Addresses on page 6 11 6 1 5 EV Interrupts The Event Manager interrupts are arranged into three groups Each group is assigned one CPU interrupt INT2 3 or 4 Since each group has multiple interrupt sources the CPU interrupt reguests are processed by the peripheral interrupt expansion PIE module The 240xA interrupt reguests have the following stages of response Interrupt source If peripheral interrupt conditions occur the respective flag bits in registers EVxIFRA EVxIFRB or EVxIFRC x A or B are set Once set these flags remain set until explicity cleared by the software It is mandatory to clear these flags in the software or future interrupts will not be recognized D Interrupt enable The Event Manager interrupts can be individually en abled or disabled by interrupt mask registers EVxIMRA EVxIMRB and EVxIMRC x A or B Each bit is set to 1 to enable unmask the interrupt or cleared to 0 to disable mask the interrupt Event Manager EV 6 9 Event Manager EV Functional Blocks PIE request If both interrupt flag bits and interrupt mask bits are set then the peripheral issues a peripheral interrupt request to the PIE module The PIE module can receive more than one interrupt from the peripheral The PIE logic records all the interrupt requests and generates the respective CPU interrupt INT1 2 3 or 4 based on the preassigned priority of the received int
323. fies the values in CAPFIFO and reports the results PERIPHERAL CODE 5 TEST CODE 1 2 3 After successful completion of this test case the value 5100 5200 5300 must be present in 351h 352 353 DM respectively Error code 5101 CAP1 value is incorrect 5102 CAP2 value is incorrect 5103 CAP3 value is incorrect Lr T Load EVA TIMERS registers LDP GPTCONA gt gt 7h Peripheral page SPLK 0000000001001001b GPTCONA 0000 0000 0 1 Enable Compare o ps 00 reserved 10 T2 CMP active hi 01 T1 CMP active lo SPLK 0000000000000000b TICNT zero timer 1 count SPLK 0000000000000000b T2CNT zero timer 2 count SPLK 0001011101000010b T1CON 000 10 Cont Up gt LLL x 128 0 reserved for T1 Tenable select 1 Tenable for Timer 1 00 Internal clk 00 cntr 0 1 enable compare 0 use own period register SPLK 0001011111000011b T2CON TSWT1 1 Use Timer 1 tenable bit SELTIPR 1 Use Timer 1 period register SPLK 1111111111111111b T1PR SPLK 0011111100000000b T1CMPR SPLK 0011111100000000b T2CMPR SPLK 0000000000000000b EVAIMRA SPLK 0000000000000000b EVAIMRB disable group A B interrupts ook ok ok o o Program Examples Load Capture registers SPLK 0011001001101100b CAPCONA 0 clear capture registers Ol enable Capture 1 2 disable QEP 1 enable Capture 3
324. flash module has four registers that control operations on the flash array At any given time you can access the memory array in the flash module array access mode or you can access the control registers register access mode but you cannot access both simultaneously The flash module has a flash access control register that selects between the two access modes This register is the flash control mode register FCMR and is mapped at FFOFh in I O space This is a special type of I O register that cannot be read The register functions as follows An OUT instruction using the register address as an O port places the flash module in register access mode The data operand used is insignifi cant For example OUT dummy OFFOFh Selects register access mode An IN instruction using the register address as an O port places the flash module in array access mode The data operand used is insignificant For example IN dummy OFFOFh Selects array access mode The flash array is not directly accessible as memory in register access mode and the control registers are not directly accessible in array access mode When operating as a program memory to store code the flash module operates in array access mode In user applications the FCMR is used to power down the flash prior to entering the LPM2 mode 3 3 4 Flash Programming at Variable Frequencies The embedded flash EEPROM on LF240x LF240xA devices can be programmed at frequencies r
325. flash utilities O While migrating code from 240x or 24x devices to the 240xA devices recheck the PWL contents before committing the code to flash memory Note that program memory locations 0040h through 0043h in 240x 24x devices are not reserved for passwords and these locations can contain user code If 0040h 0043h contain code it would inadvertently secure the 240xA device Referto Table E 1 Security Mode Table on page E 2 and its conditions before designing the reset circuit for the LC LF240xA devices There are some situations when the code security feature could be compromised However awareness of these situations during the design phase could eliminate any possibility of code security being violated Some design configurations to be avoided are An application code should not transfer control to any code that could be loaded through a peripheral such as SCI or CAN For example suppose that a customer develops their own version of the bootloader to be able to bootload from CAN Typically this program would initialize the CAN module transfer a piece of code through the CAN bus onto on chip RAM and then transfer control to the loaded code A hacker could potentially transfer a piece of code that could read the flash ROM contents and then output the same through any on chip peripheral or the external memory interface if present This is not a concern with the boot ROM embedded in the LF240xA device since the device is secu
326. for the data registers a carryover from the 8 bit version of the SPI on the TMS320C240 device The upper 8 bits return zeros when read Topic 9 1 C240 SPIivs EE EC240xA SPI i meet eere erronea 9 2 Overview of SPI Module Registers OSS SBliOperationi Ie 9 4 SPlinterr pts e ru ETE rS 9 5 SPI Module Registers IHRER ERE REM 9 6 SPl Example Waveforms rrer e c Irt 9 1 C240 SPI vs LF LC240xA SPI 9 1 C240 SPI vs LF LC240xA SPI 9 1 1 9 2 This SPI has 16 bit transmit and receive capability with double buffered transmit and double buffered receive All data registers are 16 bits wide The SPI is no longer limited to a maximum transmission rate of CLKOUT 8 in slave mode The maximum transmission rate in both slave mode and master mode is now CLKOUT 4 Note that there is a software change required since writes of transmit data to the serial data register SPIDAT and the new transmit buffer SPITXBUF must be left justified On the C240 these writes had to be left justified within an 8 bit register Now they must be left justified within a 16 bit register The control and data bits for general purpose bit I O multiplexing have been removed from this peripheral along with the associated registers SPIPC1 704Dh and SPIPC2 704Eh These bits are now in the General Purpose I O registers The polarity of the SPI SW RESET bit in 240xA is the opposite of the 240 SPI SPI Physi
327. g con trol bits used for watchdog configuration B WD disable bit B WD flag bit B WD check bits three E WD prescale select bits three 11 2 2 Watchdog Timer Clock The watchdog timer clock WDCLK is a low frequency clock used to clock the watchdog timer WDCLK has a nominal frequency of 78125 Hz when CPUCLK 40 MHz WDCLK is derived from the CLKOUT of the CPU This ensures that the watchdog continues to count when the CPU is in IDLE1 or IDLE 2 mode see section 4 4 Low Power Modes on page 4 8 WDCLK is generated in the watchdog peripheral The frequency of WDCLK can be calculated from WDCLK CLKOUT 512 WDCLK is seen at the CLKOUT pin only when the watchdog is enabled If the watchdog is enabled the watchdog counter should be reset before it overflows otherwise the DSP will be reset 11 2 3 Watchdog Suspend WDCLK is stopped when the CPU s suspend signal goes active This is achieved by stopping the clock input to the clock divider which generates WDCLK from CLKOUT Note that the watchdog timer clock does not run when the real time monitor is running This is different from the F C240 Watchdog Timer Operations 11 2 4 Operations of the WD Timer The WD timer is an 8 bit resetable incrementing counter that is clocked by the output of the prescaler The timer protects against system software failures and CPU disruption by providing a system reset when the WDKEY register is not serviced before a watchdog overflow
328. g is on the voltage Vy x a b or c applied by the leg to the corresponding motor winding is equal to the voltage supply Ugc When it is off the voltage applied is zero The on and off switching of the upper transistors DTPHy x a b or c have eight possible combinations The eight combinations and the derived motor line to line and phase voltage in terms of DC supply voltage Ugc are shown in Table 6 14 on page 6 63 where a b and c represent the values of DTPHa DTPHp and DTPH respectively 6 62 Space Vector PWM Table 6 14 Switching Patterns of a S Phase Power Inverter a b C Vao Ugc Vpo Uac Vco Uac Vap Udc Vpc Uac Vca Uac 0 0 0 0 0 0 0 0 0 0 0 1 1 3 1 3 2 3 0 1 1 0 1 0 1 3 2 3 1 3 1 1 0 0 1 1 2 3 1 3 1 3 1 0 1 1 0 0 2 3 1 3 1 3 1 0 1 1 0 1 1 3 2 3 1 3 1 1 0 1 1 0 1 3 1 3 2 3 0 1 1 1 1 1 0 0 0 0 0 0 Note 0O off 1 on Mapping the phase voltages corresponding to the eight combinations onto the d q plane by performing a d g transformation which is equivalent to an orthogonal projection of the 3 vectors a b c onto the two dimensional plane perpendicular to the vector 1 1 1 the d q plane results in six nonzero vectors and two zero vectors The nonzero vectors form the axes of a hexagonal The angle between two adjacent vectors is 60 degrees The two zero vectors are at the origin These eight vectors are called the basic space vectors and are denoted by Uo Ugo U120 U180 U240 U300 Oooo an
329. g register B EVBIFRB EVB interrupt flag register C EVBIFRC EVA interrupt mask registers EVA interrupt mask register A EVAIMRA EVA interrupt mask register B EVAIMRB EVA interrupt mask register C EVAIMRC EVB interrupt mask register A EVBIMRA EVB interrupt mask register B EVBIMRB EVB interrupt mask register C EVBIMRC functional blocks general purpose GP timers double buffering of GP timer compare and period registers GP timer block diagram GP timer inputs GP timer interrupts GP timer outputs GP timer period register GP timer synchronization individual GP timer control register TxCON overall GP timer control register GPTCONA B QEP based clock input 6 20 starting the A D converter with a timer event timer clock timer counting direction timer functional blocks generation of PWM outputs using GP timers PWM operation generation of PWM outputs with event manager asymmetric and symmetric PWM generation GP timer compare operation active inactive time calculation Index 7 Index asymmetric waveform generation asymmetric symmetric waveform generator compare PWM output in up down counting mode compare PWM output in up counting mode compare PWM transition output logic symmetric waveform generation GP timer counting operation compare output in continuous up down counting mode table compare output in continuous up counting mode table continuous up counting mode
330. generate additional wait states If m is the number of CLKOUT cycles required for a particular read or write operation and w is the number of wait states added the operation will take m w cycles At reset all WSGR bits are set to 1 making seven wait states the default for every memory space Memory 3 19 3 20 Chapter 4 Clocks and Low Power Modes The 240xA devices use the phase locked loop PLL circuit embedded in the 240xA CPU core to synthesize the on chip clocks from a lower frequency external clock Topic Page ACTED iS Serene E AN E ME RM ME 4 2 42 Phase l eckediEoop PEL 3 lt ode aloe commen De te eee 4 2 43 Watchdog Timer Clock sna sani Enna EEEE m 4 7 44 Low Power Modes LC LUI 4 8 4 1 Pins Phase Locked Loop PLL 4 1 Pins There are three device pins associated with clocks XTAL1 CLKIN This is the clock input from the external crystal to the on chip oscillator If an external oscillator is used its output must be con nected to this pin J XTAL2 This is the clock output from the on chip oscillator to drive the external crystal 1 CLKOUT IOPEO This is the clock output pin It is multiplexed with GPIO pin IOPEO This pin can be used to output the device CPU clock or the watchdog timer clock The clock select control bits are in System Control and Status Register 1 SCSR1 described in section 2 2 1 on page 2 3 This pin is configured to output CLKOUT from th
331. gic takes a snapshot of this pin and if this pin is a low lev el then the Boot ROM appears in the memory map as shown in Figure D 2 on page D 5 Otherwise the on chip flash memory is en abled and the program counter begins execution at 0000h This pin can be driven high low or through a jumper via a resistor allowing control of the boot sequence of the DSP The resistor must be present since the XF pin is an output at all other times 3 PLL Multiplier selection available on LF240xA only Bootloader code sets the PLL to multiply the incoming clock by either x2 or x4 This selec tion is made by looking at the state of the IOPAO pin at reset If this pin is pulled low the PLL is set to multiply by x2 If the pin is pulled high the PLL is set to multiply the incoming clock by a factor of x4 It is recommended that this pin be pulled high or low through a resistor since this pin will be an output when set to the primary function Refer to Table D 1 on Introduction page D 8 for the effect on the SCI bootload lock Also note that the com bination of the PLL multiplication factor chosen and the input clock fre quency must result in a clock rate less than or equal to the maximum CPU clock rate allowed for the device On the LF240x devices the PLL multiplication factor is always set to x4 by the Boot ROM initialization code SCI or SPI selection The bootloader code selects the source of the in coming code depending on the state of
332. gram of the QEP circuit for EVB Figure 6 36 Quadrature Encoder Pulse REP Circuit Block Diagram for EVA GPT2 clock CLKIN GP timer 2 CLKOUT 2 T2CON 8 9 10 T2CON 4 5 2 CLK TDIRA GPT2 dir 2 CAP1 QEP1 CAP2 QEP2 Capture unit 1 2 CAPCONA 13 14 6 80 Quadrature Encoder Pulse QEP Circuit Figure 6 37 Quaarature Encoder Pulse QEP Circuit Block Diagram for EVB GPTA clock CLKIN GP timer 4 CLKOUT 2 T4CON 8 9 10 T4CONI4 5 2 LK TDIRB GPT4 dir 2 CAP4 QEP3 CAP5 QEP4 Capture unit 4 5 CAPCONB 13 14 6 9 3 Decoding Quadrature encoded pulses are two sequences of pulses with a variable frequency and a fixed phase shift of a quarter of a period 90 degrees When generated by an optical encoder on a motor shaft the direction of rotation of the motor can be determined by detecting which of the two sequences is the leading sequence The angular position and speed can be determined by the pulse count and pulse frequency QEP Circuit The direction detection logic of the QEP circuit in the EV module determines which one of the sequences is the leading sequence It then generates a direction signal as the direction input to GP timer 2 or 4 The timer counts up if CAP1 QEP1 CAP4 QEP3 for EVB input is the leading sequence and counts down if CAP2 QEP2 CAP5 QEP4 for EVB is the leading sequence Both edges of the pulses of the two quadrature encoded inputs are counte
333. h SCICTL1 Enable TX RX internal SCICLK Disable RX ERR SLEEP TXWAKE SPLK 0000h SCICTL2 Disable RX amp TX INTs SPLK SPLK SPLK XMIT CHAR LACL MAR SACL XMIT RDY BIT BCND RCV RDY BIT BCND READ CHR LACL SACL BANZ LOOP B LOOP end 0002h SCIHBAUD 0008h SCILBAUD 0023h SCICTL1 55h ARO AR1 SCICTL2 BIT7 XMIT RDY NTC SCIRXST BIT6 RCV RDY NTC AR3 AR2 XMIT CHAR Program Examples Baud Rate 9600 b s 40 MHz SYSCLK Relinguish SCI from Reset Load ACC with xmit character Write xmit char to TX buffer Test TXRDY bit If TXRDY 0 then repeat loop Test TXRDY bit If RXRDY 0 then repeat loop The received echoed character is stored in 60h This loop is executed 20h times Repeat the loop again Program idles here after executing transmit loops Program Examples C 15 Program Examples PC ECHO asm File Name Description PROGRAM TO ECHO RECEIVED CHARACTERS BACK TO THE SOURCE The SCI is set up to bounce back any character received through the serial link When connected to a PC running a terminal emulation program the PC sees the transmitted characters bounce back This code is useful to determine the health of the communication channel between the SCI and any other serial device such as PC s serial port include 240x h MACHR O Definitions KICK DOG macro Watchdog reset macro LDP 00EOh SPLK
334. haracter by the time the next complete character has been received the new character is 9 10 SPI Interrupts written into SPIRXBUF and the RECEIVER OVERRUN Flag bit SPISTS 7 is set 9 4 1 3 OVERRUN INT ENA Bit SPICTL 4 Setting the overrun interrupt enable bit allows the assertion of an interrupt whenever the RECEIVER OVERRUN Flag bit SPISTS 7 is set by hardware Interrupts generated by SPISTS 7 and by the SPI INT FLAG bit SPISTS 6 share the same interrupt vector 0 Disable RECEIVER OVERRUN Flag bit interrupts 1 Enable RECEIVER OVERRUN Flag bit interrupts 9 4 1 4 RECEIVER OVERRUN FLAG Bit SPISTS 7 The RECEIVER OVERRUN Flag bit is set whenever a new character is received and loaded into the SPIRXBUF before the previously received character has been read from the SPIRXBUF The RECEIVER OVERRUN Flag bit must be cleared by software 9 4 1 5 SPI PRIORITY Bit SPIPRI 6 9 4 2 Data Format The value of the SPI PRIORITY bit determines the priority of the interrupt request from the SPI 0 Interrupts are high priority requests 1 Interrupts are low priority requests Four bits SPICCR 3 0 specify the number of bits 1 to 16 in the data character This information directs the state control logic to count the number of bits received or transmitted to determine when a complete character has been processed The following statements apply to characters with fewer than 16 bits Data must be left justified when written to S
335. hardware interrupt triggered by an external event sending an input through an interrupt pin Glossary F 5 Glossary FIFO buffer First in first out buffer A portion of memory in which data is stored and then retrieved in the same order in which it was stored The synchronous serial port has two four word deep FIFO buffers one for its transmit operation and one for its receive operation flash memory Electrically erasable and programmable nonvolatile read only memory general purpose input output pins Pins that can be used to accept input signals or send output signals These pins are the input pin BIO the out put pin XF and the GPIO pins hardware interrupt An interrupt triggered through physical connections with on chip peripherals or external devices IFR See interrupt flag register IFR immediate addressing One of the methods for obtaining data values used by an instruction the data value is a constant embedded directly into the instruction word data memory is not accessed immediate operand immediate value A constant given as an operand in an instruction that is using immediate addressing IMR See interrupt mask register IMR indirect addressing One of the methods for obtaining data values used by an instruction When an instruction uses indirect addressing data memory is addressed by the current auxiliary register See also direct adaressing input clock signal See CLKIN input shifter A 16
336. have no effect T4PIN Polarity of GP timer 4 compare output 00 Forced low 01 Active low 10 Active high 11 Forced high TSPIN Polarity of GP timer 3 compare output 00 Forced low 01 Active low 10 Active high 11 Forced high Event Manager EV 6 37 General Purpose GP Timers 6 3 4 Generation of PWM Outputs Using the GP Timers PWM Operation Each GP timer can independently be used to provide a PWM output channel Thus up to two PWM outputs may be generated by the GP timers To generate a PWM output with a GP timer a continuous up or up down counting mode can be selected Edge triggered or asymmetric PWM waveforms are generated when a continuous up count mode is selected Centered or symmetric PWM waveforms are generated when a continuous up down mode is selected To set up the GP timer for the PWM operation do the following Setup TxPR according to the desired PWM carrier period 1 Setup TxCON to specify the counting mode and clock source and start the operation Load TxCMPR with values corresponding to the on line calculated widths duty cycles of PWM pulses The period value is obtained by dividing the desired PWM period by the period of the GP timer input clock and subtracting one from the resulting number when the continuous up counting mode is selected to generate asymmetric PWM waveforms When the continuous up down counting mode is selected to generate symmetric PWM waveforms this value is obtain
337. he device fetches the reset vector from external memory Accesses to program memory addresses 0000h 7FFFh will be made to off chip memory of the 2407A Refer to the respective memory maps for other devices Regardless of the value of MP MC the 240xA fetches its reset vector at location 0000h in program memory Note that there is no MP MC pin avail able on devices that lack an external memory interface Memory 3 7 Data Memory 3 6 Data Memory 3 8 Data memory space addresses up to 64K of 16 bit words 32K words are internal memory 0000h to 7FFFh Internal data memory includes memory mapped registers DARAM and peripheral memory mapped registers The remaining 32K words of memory 8000h to FFFFh form part of the external data memory Note that addresses 8000h FFFFh are not accessible in 2406A 2404A and 2402A Figure 3 2 shows the data memory map for the 2407A Each device has three on chip DARAM blocks BO B1 and B2 BO is configurable as data memory or program memory It is the same memory block accessible either as data memory or program memory depending on the CNF bit Blocks B1 and B2 are available for data memory only External data memory is available only on the 2407A Data memory can be addressed with either of two addressing modes direct addressing or indirect addressing When direct addressing is used data memory is addressed in blocks of 128 words called data pages Figure 3 3 shows how these blocks are address
338. he Address bit format is for transfers of 11 bytes or less As a general rule the address bit format is typically used for data frames of 11 bytes or less This format adds one bit value 1 for an address frame 0 for a data frame to all data bytes transmitted The idle line format is typically used for data frames of 12 bytes or more I Serial Communications Interface SCI 8 13 SCI Multiprocessor Communication Figure 8 5 Address Bit Multiprocessor Communication Format Blocks of frames Pins SCIRXD SCITXD lil RENE Idle periods of no significance E CHEM One block E E E Data format expanded a Addr 1 a Data 0 Addr 1 First frame within Frame within block Next frame is address block is address Address bit is 0 for next block 7 Address bit is 1 b Address bit is 1 Idle time is of Ne no significance Address bit X E T T TT TI EE Address bit mode frame example 8 14 SCI Communication Format 8 4 SCI Communication Format The SCI asynchronous communication format uses either single line one way or two line two way communications In this mode the frame consists of a start bit one to eight data bits an optional even odd parity bit and one or two stop bits shown in Figure 8 6 There are eight SCICLK periods per data bit The receiver begins operation on receipt of a valid start bit A valid start bit is identified by four consecutive internal SCICLK periods of ze
339. he flash in powerdown mode OUT 60h OFFOFh Puts the FLASH in control reg access mode LACL 0h 0000h is the address of the Pump Control Register TBLW 60h This write powers down the flash kkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkxk The LPM2 mode can be exited by using either the RS or PDPINTx signals While RS automatically powers up the Flash module the following sequence of instructions should be executed if PDPINTx is used to exit LPM2 to power up the Flash module kkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkxk Flash module power up routine LDP 0h Set DP 0 SPLK 0000h 60h 0000 pulls the flash out of powerdown mode OUT 60h OFFOFh Puts the FLASH in control reg access mode LACL 0h 0000h is the address of the Pump Control Register TBLW 60h This write powers up the FLASH IN 60h OFFOFh Puts the FLASH in Array access mode kkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkxk Clocks and Low Power Modes 4 11 Low Power Modes 442 After the Flash is powered up a read of a known location in Flash may be done to ensure that the Flash is ready for application use For example 0000h in Program memory usually has a branch instruction whose opcode is 7980h Therefore address 0000h could be read and checked for 7980h to validate Flash power up Chapter 5 Digital Input Output I O The digital I O ports module
340. he same time as they are being updated because of a capture event the write data takes precedence The write operation to the CAPFIFOx registers can be used as a programming advantage For example if a 01 is written into the CAPnFIFO bits the EV module is led to believe that there is already an entry in the FIFO Subsequently every time the FIFO gets a new value a capture interrupt will be generated Figure 6 35 Capture FIFO Status Register B CAPFIFOB Address 7522h 15 14 13 12 11 10 9 8 CAP6FIFO CAP5FIFO CAP4FIFO R 0 RW 0 RW 0 RW 0 7 0 R 0 Note R Read access W Write access 0 value after reset Bits 15 14 Reserved Reads return zero writes have no effect Bits 13 12 CAP6FIFO CAP6FIFO Status 00 Empty 01 Has one entry 10 Has two entries 11 Had two entries and captured another one first entry has been lost Bits 11 10 CAP5FIFO CAP5FIFO Status 00 Empty 01 Has one entry 10 Has two entries 11 Had two entries and captured another one first entry has been lost Event Manager EV 6 77 Capture Units Bits 9 8 Bits 7 0 CAP4FIFO CAP4FIFO Status 00 Empty 01 Has one entry 10 Has two entries 11 Had two entries and captured another one first entry has been lost Reserved Reads return zero writes have no effect 6 8 4 Capture Unit FIFO Stacks First Capture Second Capture 6 78 Each capture unit has a dedicated 2 level deep FIFO stack The top stack consists of CAP1FIFO CAP2FIFO a
341. hed on the falling edge of the SPICLK signal Bits 5 4 Reserved Reads return zero writes have no effect Bits 3 0 SPI CHAR3 SPI CHARO Character Length Control Bits 3 0 These four bits determine the number of bits to be shifted in or out as a single character during one shift sequence Table 9 3 lists the character length selected by the bit values Table 9 3 Character Length Control Bit Values SPI SPI SPI SPI CHAR3 CHAR2 CHAR1 CHARO Character Length 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 16 9 20 SPI Module Registers 9 5 2 SPI Operation Control Register SPICTL SPICTL controls data transmission the SPI s ability to generate interrupts the SPICLK phase and the operational mode slave or master Figure 9 8 SPI Operation Control Register SPICTL Address 7041h 7 5 4 3 2 1 0 B r OVERRUN CLOCK MASTER SPI INT S INT ENA PHASE SLAVE ENA R 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bits 7 5 Reserved Reads return zero writes have no effect Bit 4 OVERRUN INT ENA Overrun Interrupt Enable Setting this bit causes an in terrupt to be generated when the RECEIVER OVERRUN Flag bit SPISTS 7 is set by hardware Interrupts generated by the RECEIVER OVERRUN Flag bit and the SPI INT FLAG bit SPISTS 6 share the same interrupt vec
342. heral initialization This requirement does not apply to 24x devices since clock to the peripherals is always on Table 13 2 New or Modified Features Peripherals in 240xA DSPs New Modified Features Peripherals in 240xA Reference Document Chapter 1 Flash Memory Map and Flash Wrapper Chapter 13 TMS320LF2407A TMS320LF2406A TMS320LF2403A TMS320LF2402A 2 On Chip SARAM TMS320LC2406A TMS320LC2404A TMS320LC2402A DSP Controllers Data Sheet literature number SPRS145 3 Peripheral Register Map Appendix A 4 ADC Chapter 7 5 Interrupt Vector Table Chapter 2 6 PIE Peripheral Interrupt Expansion Unit Chapter 2 7 EVB Event Manager B Chapter 6 8 Digital I O Chapter 5 9 PLL Chapter 4 For additional reference materials see the application report 3 3 V DSP for Digital Motor Control literature number SPRA550 or go to http www ti com and search for a list of 24x application notes 240xA 24x Family Compatibility 13 3 24x 240xA DSP Overview 13 2 24x 240xA DSP Overview Table 13 3 Features of 24x and 240xA DSPs Device Feature C2xLP CPU Core CSM DARAM SARAM Program Data Operating Voltage Flash Sectors Boot ROM Event Manager EVA Event Manager EVB CAN SPI SCI 10 bit ADC Channels WD General Purpose Digital I O External Interrupts External Memory IF Package Notes LF2407A Yes Yes 544 words 2K words 3 3 V Core 3 3 V I O 32K x 16 4K 12K 12K 4K Yes Yes Yes Yes Yes Yes 16
343. hip dual access RAM DARAM and on chip single access program data RAM SARAM 3 1 14 Dual Access On Chip RAM All Lx240xA devices have 544 words x 16 bits of on chip DARAM which can be accessed twice per machine cycle The 544 words are divided into three blocks BO B1 and B2 This memory is primarily intended to hold data but in the case of BO can also hold programs BO can be configured in one of two ways depending on the value of the CNF bit CNF 0 maps BO in data memory while CNF 1 maps BO in program memory In the pipeline operation the CPU reads data on the third cycle and writes data on the fourth cycle However DARAM allows the CPU to write and read in one cycle the CPU writes to DARAM on the master phase of the cycle and reads from DARAM on the slave phase For example suppose two instructions A and B store the accumulator value to DARAM and load the accumlator with a new value from DARAM Instruction A stores the accumulator value during the master phase of the CPU cycle and instruction B loads the new value to the accumulator during the slave phase Because part of the dual access operation is a write it only applies to RAM 3 1 2 Single Access On Chip Program Data RAM 3 2 Some of the Lx240xA devices have up to 2K 16 bit words of single access RAM SARAM The addresses associated with the SARAM can be used for both data memory and program memory and are software configurable to either external memory or the in
344. ht side of the equation does not affect the vector sum Ug The generation of Ugyr is beyond the scope of this context For more details on space vector PWM and motor control theory see The Field Orientation Principle in Control of Induction Motors by Andrzej M Trzynadlowski The Kluwer International Series in Engineering and Computer Science Vol 258 Power The above approximation means that the upper transistors must have the on and off pattern corresponding to Uy and Uy go for the time duration of T4 and To respectively in order to apply voltage Uout to the motor The inclusion of zero basic vectors helps to balance the turn on and off periods of the transistors and thus their power dissipation 6 7 2 Space Vector PWM Waveform Generation with Event Manager The EV module has built in hardware to greatly simplify the generation of symmetric space vector PWM waveforms Software is used to generate space vector PWM outputs Software Space Vector PWM To generate space vector PWM outputs the user software must m m m Configure ACTRx to define the polarity of the compare output pins Configure COMCONXx to enable compare operation and space vector PWM mode and set the reload condition for CMPRx to be underflow Put GP timer 1 or GP timer 3 in continuous up down counting mode to start the operation The user software then needs to determine the voltage Ug to be applied to the motor phases in the two dimensional d q pla
345. ic logic unit CALU carry bit Bit 9 of status register ST1 used by the CALU for extended arithmetic operations and accumulator shifts and rotates The carry bit can be tested by conditional instructions central arithmetic logic unit CALU The 32 bit wide main arithmetic logic unit for the 24x CPU that performs arithmetic and logic operations It accepts 32 bit values for operations and its 32 bit output is held in the accumulator CLKIN nput clock signal A clock source signal supplied to the on chip clock generator at the CLKIN X2 pin or generated internally by the on chip oscillator The clock generator divides or multiplies CLKIN to produce the CPU clock signal CLKOUT CLKOUT Master clock output signal The output signal of the on chip clock generator The CLKOUT high pulse signifies the CPU s logic phase when internal values are changed and the CLKOUT low pulse signifies the CPU s latch phase when the values are held constant CNF bit DARAM configuration bit Bit 12 in status register ST1 CNF is used to determine whether the on chip RAM block BO is mapped to program space or data space codec A device that codes in one direction of transmission and decodes in another direction of transmission COFF Common object file format system of files configured according to a standard developed by AT amp T These files are relocatable in memory space context saving restoring Saving the system status when the devi
346. ice is secured i e programming a password at the appropriate locations is the action that secures the device From that time on access to debug the contents of flash ROM by any means via JTAG code running off external on chip memory etc requires the supply of a valid password A password is not needed to run the code out of flash ROM such as in a typical end customer usage however access to flash ROM contents for debug purpose requires a password Technical Definitions E 2 Technical Definitions u Secure CPU s read access to the on chip Flash ROM memory locations is blocked This is also referred to as the Code Secure mode of the device This in effect blocks the JTAG debugger read access to on chip flash or ROM locations Furthermore the flash cannot be cleared erased or programmed while the device is in the secure mode The device must be unsecured before these operations can commence Unsecure CPU s read access to on chip Flash ROM memory locations is not blocked All program memory locations are unprotected and therefore allows unhindered CPU read and flash programming operations Password 64 bit data four 16 bit words that is used to secure or unsecure the device Password locations PWL Code security password locations in Flash ROM memory 0040h 0041h 0042h and 0043h These locations store the password pre determined by the system designer In flash devices the password can be changed anyti
347. ienen aa tate ebbbaduepBquesSaere dea Transmission of Bit from SPIRXBUF Maximum Baud Rate Calculation Contents XXV Notes Re enabling Interrupts sz cranes carr cetur eget encor s etin x AU AR UR by dd en Do Not Write to Test Emulation Addresses cece teen eens Do Not Write to Test Emulation Addresses 000 cece teen eh Validating Resonator Crystal Vendors sssssssssssssssssse nne Failure to Clear the Interrupt Flag Bit 0 0 cece I Dual Sequencer Mode sssssssluuussssessls eh rh Using the RESET Bit in the ADCTRL1 Register ccc eects The Address bit format is for transfers of 11 bytes or less Unused Message Mailboxes 0 00 cece eee n Power on reset POR and WDFLAG sssssssssssse ee Power on reset POR and WDFLAG sssssssssssee eens xxvi Chapter 1 Introduction The TMS320Lx240xA series of devices are members of the TMS320 family of digital signal processors DSPs designed to meet a wide range of digital motor control DMC and other embedded control applications This series is based on the C2xLP 16 bit fixed point low power DSP CPU and is complemented with a wide range of on chip peripherals and on chip ROM or flash program memory plus on chip dual access RAM DARAM This reference guide describes the following 240xA devices 2407A 2406A 2404A 2403A 2402A and 2401A This chapter provides an
348. ime DSP applications Trademarks Trademarks 320 Hotline On line is a trademark of Texas Instruments cDSP is a trademark of Texas Instruments Code Composer Studio is a trademark of Texas Instruments HP UX is a trademark of Hewlett Packard Company MS DOS is a registered trademark of Microsoft Corporation OS 2 is a trademark of International Business Machines Corporation PC is a trademark of International Business Machines Corporation PC DOS is a trademark of International Business Machines Corporation Solaris is a trademark of Sun Microsystems Inc SunOS is a trademark of Sun Microsystems Inc TMS320 is a trademark of Texas Instruments TMS320C24x is a trademark of Texas Instruments Windows is a registered trademark of Microsoft Corporation XDS is a trademark of Texas Instruments XDS510 is a trademark of Texas Instruments XDS510PP is a trademark of Texas Instruments XDS510WS is a trademark of Texas Instruments XDS511 is a trademark of Texas Instruments All trademarks are the property of their respective owners Read This First vii viii 1 Contents IMIrOGUCHON DER 1 1 Summarizes the TMS320 family of products Introduces the TMS320x240xA DSP controllers and lists their key features 1 1 TMS320 Family Overview 0 cece teeta 1 2 TMS320C240xA Series of DSP Controllers 1 8 Peripheral Overview rr 1 4 New Features in 240xA Devices eee 1 5 240xA Highlights 2 sob exe md aee ed
349. in high priority mode SPI interrupt in high priority mode SCI receiver interrupt in high priority mode SCI transmitter inter rupt in high priority mode CAN mailbox interrupt high priority mode CAN error interrupt high priority mode System Configuration and Interrupts 2 9 Interrupt Priority and Vectors Table 2 2 240xA Interrupt Source Priority and Vectors Continued b INT2 level 2 Overall Priority 2 10 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Interrupt Name CMP1INT CMP2INT CMP3INT T1PINT T1CINT T1UFINT T1OFINT CMPAINT CMP5INT CMP6INT T3PINT T3CINT T3UFINT T3OFINT CPU Interrupt Vector INT2 0004h INT2 0004h INT2 0004h INT2 0004h INT2 0004h INT2 0004h INT2 0004h INT2 0004h INT2 0004h INT2 0004h INT2 0004h INT2 0004h INT2 0004h INT2 0004h Peripheral Interrupt Vector 0021h 0022h 0023h 0027h 0028h 0029h 002Ah 0024h 0025h 0026h 002Fh 0030h 0031h 0032h Maskable Y Y Source Peripheral EVA EVA EVA EVA EVA EVA EVA EVB EVB EVB EVB EVB EVB EVB Description Compare 1 interrupt Compare 2 interrupt Compare 3 interrupt Timer 1 period interrupt Timer 1 compare interrupt Timer 1 underflow interrupt Timer 1 overflow interrupt Compare 4 interrupt Compare 5 interrupt Compare 6 interrupt Timer 3 period interrupt Timer 3 compare interrup
350. inous Up Down counting x 128 OF UF CMPR amp PERIOD toggles IOPB0 1 2 3 interrupts that title EV test routine Title include 240xA h Variable and register declaration include vector h Vector label declaration MACRO Definitions KICK DOG macro Watchdog reset macro LDP 00E0h DP gt 7000h 707Fh SPLK 05555h WDKEY SPLK HOAAAAh WDKEY LDP Koh DP gt 0000h 007Fh endm text START LDP Koh set DP 0 SETC INTM Disable interrupts SPLK 0000h IMR Mask all core interrupts LACC IFR Read Interrupt flags SACL IFR Clear all interrupt flags LDP WDKEY gt gt 7h Peripheral page SPLK 0004h SCSR1 EVA module clock enable SPLK 006Fh WDCR Disable WD KICK DOG MAR ARO LDP 0E1h Peripheral page SPLK 1111111100000000b PBDATDIR Load TIMER 1 registers LDP SPLK SPLK SPLK SPLK SPI LK SPLK C 30 GPTCONA gt gt 7h set IOPBn as outputs 0 Peripheral page 0000000000000000b GPTCONA 0000000000000000b T1CNT 0000111101000010b T1CON 000 01 Cont Up Down 111 x 128 01 Tenable reserved for T1 00 Internal clk 00 LD CMPR whencntr 0 1 enable compare 0 use own period register 1111111111111111b T1PR 0000000011111111b T1CMPR 0000011110000000b EVAIMRA zero timer 1 count Enable OV U C P interrupt bits wait GISR2 SISR2a SISR29 SISR28 SPL LDP SPL CLR K K C LDP SPL
351. inputs that can be enabled disabled The valid input triggers for SEQ1 SEQ2 and cascaded SEQ is as follows SEQ1 sequencer 1 SEQ2 sequencer 2 Cascaded SEQ Software trigger software SOC Software trigger software SOC Software trigger software SOC Event manager A EVA SOC Event manager B EVB SOC Event manager A EVA SOC External SOC pin ADC SOC Event manager B EVB SOC External SOC pin ADC SOC Note that d An SOC trigger can initiate an autoconversion sequence whenever a se quencer is in an idle state An idle state is either CONVOO prior to receiving a trigger or any state which the sequencer lands on at the completion of a conversion sequence i e when SEQ CNTR n has reached a count of Zero If an SOC trigger occurs while a current conversion sequence is under way it sets the SOC SEQn bit which would have been cleared on the com mencement of a previous conversion sequence in the ADCTRL2 register If yet another SOC trigger occurs it is lost i e when the SOC SEQn bit is already set SOC pending subsequent triggers will be ignored Once triggered the sequencer cannot be stopped halted in mid se quence The program must either wait until an End of Sequence EOS or initiate a sequencer reset which brings the sequencer immediately back to the idle start state CONVOO for SEQ1 and cascaded cases CONVOS for SEQ2 When SEQ1 2 are used in cascaded mode triggers going to SEQ2 are ig nored while S
352. instruc tions See also memory mapped register IR See instruction register IR IS O space select pin The 24x asserts IS to indicate an access to external I O space ISR See interrupt service routine ISR ISWS O space wait state bit s A value in the wait state generator control register WSGR that determines the number of wait states applied to reads from and writes to off chip I O space latch phase The phase of a CPU cycle during which internal values are held constant See also logic phase CLKOUT 1 logic phase The phase of a CPU cycle during which internal values are changed See also latch phase CLKOUT1 long immediate value A 16 bit constant given as an operand of an instruction that is using immediate addressing LSB Least significant bit The lowest order bit in a word When used in plural form LSBs refers to a specified number of low order bits beginning with the lowest order bit and counting to the left For example the four LSBs of a 16 bit value are bits 0 through 3 See also MSB machine cycle See CPU cycle maskable interrupt A hardware interrupt that can be enabled or disabled through software See also nonmaskable interrupt Glossary master clock output signal See CLKOUTT master phase See ogic phase memory mapped register One of the on chip registers mapped to addresses in data memory See also O mapped register microcontroller mode A mode in which the on chip ROM or
353. interrupts Most of these multiplexed digital I O pins come up in their digital I O pin mode as an input following a device reset For a detailed description of the architecture and instruction set refer to the TMS320F C24x DSP Controllers Reference Guide CPU and Instruction Set SPRU160 Figure 2 1 240xA Device Architecture C2xx CPU JTAG 544 x 16 DARAM P bus I F Event Managers EVA and EVB Flash ROM SARAM up to 32K x 16 up to 2K x 16 Mem I F Synthesized ASIC gates P bus SPI SCI CAN WD ADC Interrupts VO control reset etc registers ADC Configuration Registers 2 2 Configuration Registers 2 2 4 System Control and Status Registers 1 and 2 SCSR1 SCSR2 baia 2 2 System Control and Status o 1 SCSH1 Address 07018h 14 11 CLKSRC LPM1 LPMO CLKPS2 CLKPS1 CLKPSO RW 0 RW 0 RW 0 RW 1 RW 1 RW 1 ADC SCI SPI CAN EVB EVA CLKEN CLKEN CLKEN CLKEN CLKEN CLKEN er RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access C Clear 0 value after reset Bit 15 Reserved Bit 14 CLKSRC CLKOUT pin source select 0 CLKOUT pin has CPU Clock 40 MHz on a 40 MHz device as the output 1 CLKOUT pin has Watchdog clock as the output Bits 13 12 LPM 1 0 Low power mode select These bits indicate which low power mode is entered when the CPU executes the IDLE instruction See Table 2 1 for a description of the low power modes Table 2 1 Description of Low Power Modes LPM
354. into the working active register only when a certain timer event specified by TxCON occurs For the period register the working register is reloaded with the value in its shadow register only when the value of the counter register TxCNT is 0 The condition on which a compare register is reloaded can be one of the following j Immediately after the shadow register is written On underflow that is when the GP timer counter value is 0 j On underflow or period match that is when the counter value is 0 or when the counter value equals the value of the period register The double buffering feature of the period and compare registers allows the application code to update the period and compare registers at any time during General Purpose GP Timers a period in order to change the timer period and the width of the PWM pulse for the period that follows On the fly change of the timer period value in the case of PWM generation means on the fly change of PWM carrier frequency p M eeOeaeely o r1 Note The period register of a GP timer should be initialized before its counter is initialized to a non zero value Otherwise the value of the period register will remain unchanged until the next underflow I Note that a compare register is transparent the newly loaded value goes directly into the active register when the associated compare operation is disabled This applies to all Event Manager compare registers GP Timer Co
355. iod register the timer counts down to zero and continues again as if the initial value was zero If the initial value of the timer is between zero and the contents of the period register the timer counts up to the period value and continues to finish the period as if the initial counter value was the same as that of the period register The period underflow and overflow interrupt flags interrupts and associated actions are generated on respective events in the same manner as they are generated in continuous up counting mode The counting direction indication bit for this timer in GPTCONA B is one when the timer counts upward and zero when the timer counts downward Either the external clock from the TCLKINA B pin or the internal device clock can be selected as the input clock TDIRA B input is ignored by the timer in this mode Figure 6 9 shows the continuous up down counting mode of the GP timer Figure 6 9 GP Timer Continuous Up Down Counting Mode TxPR 3 or 2 Timer value TxPR 3 TxPR 2 Timer period 2x TxPR Timer 3 period TxCON 6 timer clock FF TF LE LELELELELELELELELELELELU Continuous up down counting mode is particularly useful in generating centered or symmetric PWM waveforms found in a broad range of motor motion control and power electronics applications General Purpose GP Timers 6 3 2 GP Timer Compare Operation Each GP timer has an associated compare register TxCMPR and a PWM
356. ion ISR interrupt service routine definition ISR code sample LAM local acceptance mask 10 16 LAMn_H local acceptance mask register n 0 1 high word 10 17 LAMn_L local acceptance mask register n 0 1 low word 10 18 latch phase of CPU cycle local data memory logic phase of CPU cycle low power modes clock domains exiting low power modes examples summary table Index 11 Index wake up from low power modes mailbox CAN controller area network RAM layout table 10 44 CAN mailbox addresses table CAN mailbox configuration details CAN mailbox layout 10 10 CAN mailbox RAM 10 10 mailbox configurations 10 15 mailbox RAM layout table 10 44 MCR master control register 10 23 MCRA I O mux control register A configuration table MCRB I O mux control register B MCRB I O mux control register B configuration table MCRC I O mux control register C 5 7 configuration table MDER mailbox direction enable register 10 19 memory factory masked on chip ROM flash embedded flash EEPROM flash control register access global data O space I O space address map for 2407A local data 3 8 1d 3 11 2407A peripheral memory map configuration memory pages data page 0 address map data page 0 address map table on chip RAM dual access on chip RAM DARAM single access on chip program data RAM SARAM on chip advantages overview of memory and I O spaces program 3 6 o 3 7 prog
357. ion and detection is not enabled the PE flag is disabled and read as 0 The PE bit is reset by an active SW RESET or a system reset 0 No parity error or parity is disabled 1 Parity error is detected Serial Communications Interface SCI 8 29 SCI Module Registers Bit 1 RXWAKE Receiver wakeup detect flag A value of 1 in this bit indicates detection of a receiver wakeup condition In the address bit multiprocessor mode SCICCR 3 1 RXWAKE reflects the value of the address bit for the character contained in SCIRXBUF In the idle line multiprocessor mode RXWAKE is set if the SCIRXD data line is detected as idle RXWAKE is a read only flag cleared by one of the following The transfer of the first byte after the address byte to SCIRXBUF The reading of SCIRXBUF An active SW RESET _j A system reset Bit 0 Reserved Reads return zero writes have no effect Figure 8 16 Register SCIRXST Bit Associations Address 7055h 7 6 5 4 3 2 1 0 VV RXRDY or BRKDT causes an interrupt if RX BK INT ENA SCICTL2 1 1 jj LEE RX ERROR 1 when any of bits 5 through 2 is a 1 value 8 7 06 Receiver Data Buffer Registers SCIRXEMU SCIRXBUF Received data is transferred from RXSHF to SCIRXEMU and SCIRXBUF When the transfer is complete the RXRDY flag bit SCIRXST 6 is set indicating that the received data is ready to be read Both registers contain the same data they have separate addresses but are not physically separa
358. ion session always starts with the initial state and continues sequentially until the end state if allowed The result buffer is filled in a sequential order Any number of conversions between 1 and MAX CONVn 1 can be programmed for a session Example 7 3 MAXCONV Register Bit Programming If only five conversions are required then MAX CONVn is set to four Case 1 Dual mode SEQ and cascaded mode Sequencer goes from CONVOO to CONV04 and the five conversion results are stored in the registers Result 00 to Result 04 of the Conversion Result Buffer Case 2 Dual mode SEQ2 Sequencer goes from CONV08 to CONV 12 and the five conversion results are stored in the registers Result 08 to Result 12 of the Conversion Result Buffer MAX CONV1 Value gt 7 for Dual Seguencer Mode If a value for MAX CONV1 which is greater than 7 is chosen for the dual sequencer mode i e two separate 8 state sequencers then SEQ CNTR n will continue counting past seven causing the sequencer to wrap around to CONVOO and continue counting 7 32 Register Bit Descriptions Table 7 6 Bit Selections for MAX CONV for Various Number of Conversions MAX CONV1 3 0 Number of conversions 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 7 5 4 Autoseguence Status Register AUTO SEQ SR Figure 7 12 Autosequence Status Register AUTO SEQ SH Address 70A7h 15 12 11 10 9 8
359. iority SCI RX interrupt RXRDY RX BKINTENA Note All SCI registers are eight bits wide These eight bits are mapped to the lower eight bits of the 16 bit words 8 4 C240 SCI vs LF LC240xA SCI 8 1 2 Architecture The major elements used in full duplex operation are shown in Figure 8 1 SCI Block Diagram and include Atransmitter TX and its major registers upper half of Figure 8 1 B SCITXBUF transmitter data buffer register Contains data loaded by the CPU to be transmitted B TXSHF register transmitter shift register Accepts data from regis ter SCITXBUF and shifts data onto the SCITXD pin one bit at a time Areceiver RX and its major registers lower half of Figure 8 1 m RXSHF register receiver shift register Shifts data in from SCIRXD pin one bit at a time B SCIRXBUF receiver data buffer register Contains data to be read by the CPU Data from a remote processor is loaded into register RXSHF and then into registers SCIRXBUF and SCIRXEMU L A programmable baud generator _j Data memory mapped control and status registers see section 8 1 3 SCI Module Register Addresses The SCI receiver and transmitter can operate either independently or simultaneously 8 1 3 SCI Module Register Addresses Table 8 1 on page 8 6 lists the addresses of the SCI registers Serial Communications Interface SCI 8 5 C240 SCI vs LF LC240xA SCI Table 8 1 Overview o
360. isters 7500 7508 Compare PWM and deadband registers 7511 7519 Capture and QEP registers 7520 7529 Interrupt mask vector and flag registers 7520 7531 Reserved 7532 753F Memory 3 9 Data Memory Figure 3 3 Data Memory Pages DP Value Offset Data memory 0000 0000 0 000 0000 0000 0000 0 111 1111 0000 0000 1 000 0000 Page 1 0080h 00FFh 0000 0000 1 111 1111 0000 0001 0 000 0000 0000 0001 0 111 1111 1111 1111 1 000 0000 Page 511 FF80h FFFFh 41114 11111 111 1111 Data Page 0 Address Map 3 10 The data memory also includes the device s memory mapped registers MMR which reside at the top of data page 0 addresses 0000h 007Fh Note the following The two registers that can be accessed with zero wait states are B Interrupt mask register IMR B Interrupt flag register IFR The test emulation reserved area is used by the test and emulation sys tems for special information transfers Note Do Not Write to Test Emulation Addresses Writing to the test emulation addresses can cause the device to change its operating mode and therefore affect the operation of an application Data Memory The scratch pad RAM block B2 includes 32 words of DARAM that pro vide for variable storage without fragmenting the larger RAM blocks whether internal or external This RAM block supports dual access opera tions and can be addressed via any data mem
361. it buffer register SPITXBUF SPICLK phase and polarity control static and control logic SPI module registers overview register addresses SPI baud rate register SPIBRR SPI configuration control register SPICCR character length control bit values SPI emulation buffer register SPIRXEMU SPI example waveforms CLOCK POLARITY 0 CLOCK PHASE 0 CLOCK POLARITY 0 CLOCK PHASE 1 CLOCK POLARITY 1 CLOCK PHASE 0 CLOCK POLARITY 1 CLOCK PHASE 1 SPISTE behavior in master mode SPISTE behavior in slave mode SPI operation control register SPICTL SPI priority control register SPIPRI SPI serial data register SPIDAT SPI serial receive buffer register SPIRXBUF SPI serial transmit buffer register SPITXBUF SPI status register SPISTS SPIO pins 240xA devices 13 11 SRR CAN data frame suspend mode CAN controller area network 10 41 system configuration and interrupts 240xA architectural summary figure configuration registers device identification number register DINR system control and status register 1 sesat es low power modes system control and status register 2 SCSR2 Index 21 Index interrupt priority and vectors 240xA interrupt source priority and vectors table peripheral interrupt expansion PIE controller block diagram interrupt acknowledge hierarchy NMI nonmaskable operation sequence 2 request structure request figure vectors 2 17 vectors phantom vectors
362. it to the frame The idle line mode does not add this extra bit and is compatible with RS 232 type communications Bits 2 0 SCI CHAR2 0 Character length control bits 2 0 These bits select the SCI character length from one to eight bits Characters of less than eight bits are right justified in SCIRXBUF and SCIRXEMU and are padded with leading zeros in SCIRXBUF SCITXBUF doesn t need to be padded with leading zeros Table 8 4 lists the bit values and character lengths for SCI CHAR2 0 bits Table 8 4 SCI CHAR2 0 Bit Values and Character Lengths SCI CHAR2 0 Bit Values Binary 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 8 22 SCI Module Registers 8 7 2 SCI Control Register 1 SCICTL1 SCICTL1 controls the receiver transmitter enable TXWAKE and SLEEP functions and the SCI software reset Figure 8 11 SCI Control Register 1 SCICTL1 Address 7051h RX ERR SW INT ENA RESET TXWAKE SLEEP TXENA RXENA RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access S Set only 0 value after reset Bit 7 Reserved Reads return zero writes have no effect Bit 6 RX ERR INT ENA SCI receive error interrupt enable Setting this bit enables an interrupt if the RX ERROR bit SCIRXST 7 becomes set because of errors occurring 0 Receive error interrupt disabled 1 Receive error interrupt enabled Bit 5 SW RESET SCI software reset active low Writing a 0 to this bit initializes the SCI stat
363. itching patterns and basic space vectors space vector PWM boundary conditions space vector PWM waveform generation with event manager hardware software space vector PWM waveforms 6 66 unused compare register 6 66 symmetric PWM waveform generation timer control registers TXCON and GPTCONA B individual GP timer control register TxCON overall GP timer control register A GPTCONA overall GP timer control register B GPTCONB event manager A EVA block diagram pins register addresses EVA capture registers EVA compare control registers EVA interrupt registers EVA timer registers EVB capture registers EVB timer registers event manager B EVB block m ram pins EVB compare control registers register addresses EVB interrupt registers examples of 240xA program code executable files procedure for generating external interrupt control registers external memory interface XMIF I O space program and data space wait state generator 2407A wait state generator control register WSGR setting the number of wait states with the 2407A WSGR bits with the 2407A wait state generator with the READY signal XMIF qualifier signal description data address data visibilit functional timing program address data visibility functional timing XMIF signal descriptions factory masked on chip ROM flash embedded flash EEPROM flash control register access powering down the flash Flash ROM code securit
364. ite O No effect 1 Resets flag CMP5INT FLAG Compare 5 interrupt Read 0 Flag is reset 1 Flagis set Write O No effect 1 Resets flag CMP4INT FLAG Compare 4 interrupt Read O Flag is reset 1 Flag is set Write O No effect 1 Resets flag PDPINTB FLAG Power drive protection interrupt Read O Flagis reset Flag is set Write No effect Oo Resets flag Event Manager EV 6 95 Event Manager EV Interrupts EVB Interrupt Flag Register B EVBIFRB Figure 6 46 EVB Interrupt Flag Register B EVBIFRB Address 7530h 15 4 3 2 1 0 E r T4OFINT T4UFINT T4CINT T4PINT gree FLAG FLAG FLAG FLAG R 0 RW1C 0 RW1C 0 RWIC 0 RW1C 0 Note R Read access W1C Write 1 to clear 0 value after reset Bits 15 4 Reserved Reads return zero writes have no effect Bit 3 T4OFINT FLAG GP timer 4 overflow interrupt Read 0 Flag is reset 1 Flagis set Write 0 No effect 1 Resets flag Bit 2 TAUFINT FLAG GP timer 4 underflow interrupt Read 0 Flagis reset 1 Flagis set Write 0 No effect 1 Resets flag Bit 1 T4CINT FLAG GP timer 4 compare interrupt Read 0 Flagis reset 1 Flagis set Write O No effect 1 Resets flag Bit 0 T4PINT FLAG GP timer 4 period interrupt Read 0 Flagis reset 1 Flagis set Write O No effect 1 Resets flag 6 96 Event Manager EV Interrupts EVB Interrupt Flag Register C EVBIFRC Figure 6 47 EVB Interrupt Flag Register C EVBIFRC Address 7531h 15 3 2 1 0 CAP6INT C
365. iting reading from the mailbox RAM is always wordwise 16 bits and the RAM always presents the full 16 bit word on the bus Table 10 1 shows the configuration details of the mailboxes Table 10 1 Mailbox Configuration Details Mailbox 0 1 a O N Operating Mode LAM Used Receive only LAMO Receive only LAMO Transmit Receive configurable LAM1 Transmit Receive configurable LAM1 Transmit only Transmit only CAN Controller Module 10 5 Overview of the CAN Network 10 2 3 Memory Map Figure 10 3 shows memory space and Table 10 2 and Table 10 3 give the register and mailbox locations in the CAN module respectively Figure 10 3 TMS320x240xA CAN Module Memory Space 240xA Data Space 2 MDER TCR 0000 7100 ai RCR MCR i CAN BCR1 BCR2 registers ESR GSR 710F CEC CAN IFR E CAN_IMR LAMO H Reserved LAMO L LAM1 H 7100 S n LAM1_L Reserved CAN 7230 7200 Mailbox 0 f Mailbox 1 gt E MSG IDOL MSG IDOH Jn Mailbox 2 a MSG CTRLO Reserved En Mailbox 3 E MBX0A MBX0B ET Mailbox 4 E MBXOC MBXOD FFFF 7230 E P MSG ID5L MSG ID5H 4 MSG CTRL5 Reserved MBX5A MBX5B E MBX5C MBX5D 10 6 Table 10 2 Register Addresses Note Address 7100h 7101h 7102h 7103h 7104h 7105h 7106h 7107h 7108h 7109h 710Ah 710Bh 710Ch 710Dh 710Eh 710Fh Name MDER TCR RCR MCR BCR2 BCR1 ESR
366. itions for some multiplexed pins such as XF CLKOUT etc are different from those of the 24x See Chapter 5 for more details Note that when multiplexed I O pins are in input mode the pin is connected to both the I O data register and the shared peripheral The I O Mux control register MCRx in 240xA devices is synonymous to the OCRx in 24x devices Both MCRx and OCRx have the same function in 240xA and 24x devices respectively 13 5 1 Digital I O and Shared Pin Functions for the 240xA LF2407 device has a total of 41 pins shared between primary functions and I Os Table 13 7 lists all the pins that are shared between the primary functions and the dedicated I O Ports A B C D E F 240xA 24x Family Compatibility 13 11 Digital I O GPIO Pins Table 13 7 LF2407A Shared Pin Configuration Shared Pin Functions Primary Function 1 SCITXD SCIRXD XINT1 CAP1 QEP1 CAP2 QEP2 CAP3 PWM1 PWM 2 PWM3 PWM4 PWM5 PWM6 T1PWM CMP T2PWM CMP TDIRA TCLKINA W R BIO SPISIMO SPISOMI SPICLK SPISTE CANTX CANRX 18 12 1 O 0 IOPAO IOPA1 IOPA2 IOPA3 IOPA4 IOPA5 IOPA6 IOPA7 IOPBO IOPB1 IOPB2 IOPB3 IOPB4 IOPB5 IOPB6 IOPB7 IOPCO IOPC1 IOPC2 IOPC3 IOPC4 IOPC5 IOPC6 IOPC7 Mux Control Register MCRA MCRA MCRA MCRA MCRA MCRA MCRA MCRA MCRA MCRA MCRA MCRA MCRA MCRA MCRA MCRA MCRB MCRB MCRB MCRB MCRB MCRB MCRB MCRB Mux Control Bit 4 0 1 10 12 13 14 15 N o oc A
367. its 4 and 5 FIFO stacks retain their contents 01 Enables Capture Units 4 and 5 10 Reserved 11 Reserved Bit 12 CAP6EN Capture Unit 6 control 0 Disables Capture Unit 6 FIFO stack of Capture Unit 6 retains its contents 1 Enables Capture Unit 6 Bit 11 Reserved Reads return zero writes have no effect Bit 10 CAP6TSEL GP timer selection for Capture Unit 6 0 Selects GP timer 4 1 Selects GP timer 3 Bit 9 Bit 8 Bits 7 6 Bits 5 4 Bits 3 2 Bits 1 0 Capture Units CAP45TSEL GP timer selection for Capture Units 4 and 5 0 Selects GP timer 4 1 Selects GP timer 3 CAP6TOADC Capture Unit 6 event starts ADC 0 No action 1 Starts ADC when the CAP6INT flag is set CAP4EDGE Edge detection control for Capture Unit 4 00 No detection 01 Detects rising edge 10 Detects falling edge 11 Detects both edges CAP5EDGE Edge detection control for Capture Unit 5 00 No detection 01 Detects rising edge 10 Detects falling edge 11 Detects both edges CAP6EDGE Edge detection control for Capture Unit 6 00 No detection 01 Detects rising edge 10 Detects falling edge 11 Detects both edges Reserved Reads return zero writes have no effect Capture FIFO Status Register A CAPFIFOA CAPFIFOA contains the status bits for each of the three FIFO stacks of the capture units The bit description of CAPFIFOA is given in Figure 6 34 If a write occurs to the CAPnFIFOA status bits at the same time as they are being updated be
368. ity Functional Timing DECODE FETCH OPERAND FETCH EXECUTE i B KA BRS GNE NEL os LLLI idi UR STRB N N 3 14 XMIF Qualifier Signal Description Figure 3 6 Data Address Data Visibility Functional Timing DECODE FETCH OPERAND FETCH EXECUTE V MN s X ees ELA ore as ED VIS OE N N Memory 3 15 Program and Data Spaces I O Space 3 9 Program and Data Spaces 3 10 I O Space 3 16 PS and STRB are inactive high for accesses to on chip program memory and data memory The external data and address busses are active only when accesses are made to external memory locations except when in bus visibility BVIS mode see section 3 11 Wait State Generation Two cycles are required on all external writes including a half cycle before WE goes low and a half cycle after WE goes high This prevents data contention on the external buses O space accesses are distinguished from program and data memory accesses by IS going low All 64K I O words external I O port and on chip I O registers are accessed via the IN and OUT instructions While accesses are made to the on chip I O mapped registers signals IS and STRB are made inactive that is driven to the high state The external address and data bus is only active when accesses are made to external I O memory locations Two cycles are required on all external writes including a half cycle before WE goes low
369. k Figure 6 23 on page 6 54 shows the block diagram of the dead band logic for one compare unit Table 6 13 Dead Band Generation Examples DBT3 DBTO m DBTCONx 11 8 0 k mnm UO O U gt o N O a A CQ PD 110 and 1x1 P 32 0 0 8 1 6 2 4 3 2 4 4 8 5 6 6 4 72 8 8 8 9 6 10 4 11 2 12 Note Table values are given in us 100 P 16 0 0 4 0 8 1 2 1 6 2 2 4 2 8 3 2 3 6 4 4 4 4 8 5 2 5 6 6 PWM Circuits Associated With Compare Units DBTPS2 DBTPSO p DBTCONx 4 2 011 P 8 0 0 2 0 4 0 6 0 8 1 2 1 4 1 6 1 8 2 2 2 2 4 2 6 2 8 3 010 P 4 0 0 0 1 0 05 0 2 0 1 0 3 0 15 0 4 0 2 0 5 0 25 0 6 0 3 0 7 0 35 0 8 0 4 0 9 0 45 1 0 5 1 1 0 55 1 2 0 6 1 3 0 65 1 4 0 7 1 5 0 75 001 P 2 000 P 1 0 0 025 0 05 0 075 0 1 0 125 0 15 0 175 0 2 0 225 0 25 0 275 0 3 0 325 0 35 0 375 Event Manager EV 6 53 PWM Circuits Associated With Compare Units Figure 6 23 Dead Band Unit Block Diagram x 1 2 or 3 Internal CPU clock DBTCONx Y dead band control register LK PHx d from waveform generators SV state machine EN Counter Compare logic DBTCONx dead band control register DTPHx DTPHx_ DTPHx Dead band DTPHx_ Note Signals such as PHx DTPHx and DTPHx are internal to the device and as such external monitoring control of these signals is not possible 6 54 PWM Circuits Associate
370. k k k k k k k kc kc k k k k k k k k k k k ck ck ck k k k k k Select the Serial EEPROM i by driving the select line low PRR RRR RRR KR KKK RRR e he ke KERR KKK KERR e e he KR ke he he KERR KR KKK e he he ke che he kkk he ke che he ke e he he ke che he kkk ke ke he he ke e e kkk CS ACTIVE CLRC XF Drive CS XF Low f PRR RRR RRR K kk k k ke e k ke k k k ke k k k k k he ke e k k k k he e e k he k K k k e k k k k he k k k k k k k k e k k k k he k k k k k k k k e k k k k Next send the Serial EEPROM a Read Command it is then read out in burst mode two bytes at a time by using GET WORD Note that CS stays low all the time PRR RRR KERR ke K ke ce k ke e k k k k k e k k he k k k ke e k ke ke K he ke e K he k K k k e k he ke K he k e k he K K k ke e k k K K he k e che he ke k k k e k k k k LACC READ COMMAND Load Read Command for EEPROM CALL XMIT VALUE Transmit Read Command r r p RR KR k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k kc kc k k k k k k k k k k ck ck ck ck ck ck k k k Now send a word 16 bits to the EEPROM as address Hard coded zero bytes are sent by the GET WORD but this is fine Since the EEPROM is defined to contain boot code at origin i i i PRR RRR RRR kkk k KKK e k ke A K he e e k he k k k ke e k ke K K he ke e k KER k ke k k ke k k k k e k he k k k ke e k k ke ce he KE e k ke ke ke k k e k k k k CALL GET WORD Get word sends two zero chars
371. k ke k k ke ke K he ke k k k k k k ke e k k ke k k k e k k K k k KKK k k include 240x h j EK K k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k KK Variable Declarations for on chip RAM Blocks bss GPR0 1 General purpose registers bss GPR1 1 bss GPR2 1 bss GPR3 1 bss DEST 1 bss LENGTH 1 bss Stk0 1 bss Stk1 1 bss data buf 1 bss VBR CNTR 1 bss DELAY 1 bss CHAR RETRY CNTR 1 bss BAUD TBL PTR 1 p RR KR RR k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k MACRO Definitions PRR RRR RRR KKK KK RRR KKK KERR KKK KK RRR kk kkk kkk kkk kkk kkk kkk kkk kkk kk e he ke kkk kkk kkk kkk k kkk POINT_B1 macro LDP 06h endm Protocol Definitions POINT PF1 macro LDP 0EOh endm y EKK k k k k k k k k k k k k k k k k k k k k k k k k k k k ck ck kck ck ck kck ck ck k k kck kck kck kck ck ck kck ck ck kck ck ck ck ck ckck ck ck k k ck ck k k ck ck ck ck k MAIN CODE starts here PRR RRR RRR ke kc ke ke e he ke ehe he ke e he ke ke K he ke K he e ke K he e e he ke e che he ke K he ke e che he ke e he ke ke che he ke ce he ke ke che he ke e he ke ke che he ke he he ke e e e e text START SELECT PLLMULT LDP PADATDIR gt gt 7 SPLK 0000H PADATDIR Config all I O to be inputs LACC PADATDIR Read I
372. ke k he ke che ke ke e k ke k ke he k e k k k k sect vectors RSVECT B START Reset Vector INT1 B GISR1 Interrupt Level 1 INT2 B GISR2 Interrupt Level 2 INT3 B GISR3 Interrupt Level 3 INT4 B GISR4 Interrupt Level 4 INT5 B GISR5 Interrupt Level 5 INT6 B GISR6 Interrupt Level 6 RESERVED B PHANTOM Reserved SW INT8 B PHANTOM Software Interrupt SW INT9 B PHANTOM Software Interrupt SW INT10 B PHANTOM Software Interrupt SW INT11 B PHANTOM Software Interrupt SW INT12 B PHANTOM Software Interrupt SW INT13 B PHANTOM Software Interrupt SW INT14 B PHANTOM Software Interrupt SW INT15 B PHANTOM Software Interrupt SW INT16 B PHANTOM Software Interrupt TRAP B PHANTOM Trap vector NMI B NMI Non maskable Interrupt EMU TRAP B PHANTOM Emulator Trap SW INT20 B PHANTOM Software Interrupt SW INT21 B PHANTOM Software Interrupt SW INT22 B PHANTOM Software Interrupt SW INT23 B PHANTOM Software Interrupt SW INT24 B PHANTOM Software Interrupt SW INT25 B PHANTOM Software Interrupt SW INT26 B PHANTOM Software Interrupt SW INT27 B PHANTOM Software Interrupt SW INT28 B PHANTOM Software Interrupt SW INT29 B PHANTOM Software Interrupt SW INT30 B PHANTOM Software Interrupt SW INT31 B PHANTOM Software Interrupt Code security passwords are stored from 40h 43h word 0000h Replace values with word 0000h code security passwords word 0000h word 0000h Program Examples C
373. ke ke k k ke k k ke k k ke k k ke ke k ke ke k ke ke k ke k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k SPLK 0000000000000000b CANMDER aa aa a EL A L C 24 E FEDCBA9876543210 y EK k k k k k k k k o ke k Lo KERR ERR KERR KERR KERR KERR KER KK ERK KER KERR KERR k k k k k k k k k k k k k k p RRR RRR k k k k Write CAN Mailboxes KR KKK KK ke ke ke OI IO IO IO IO IO III III III III e e Fe e e Fe e H He IO IO IO IO IO IOI IO IOI II II II I Ik Ik e LDP DP_CAN2 SPLK 1011111111111111b CANMSGID2H LTEELEEEEHL HL T H FEDCBA9876543210 bit 0 12 upper 13 bits of extended identifier bit 13 Auto answer mode bit bit 14 Acceptance mask enable bit bit 15 Identifier extension bit SPLK 1111111111111111b CANMSGID2L MA OAO H FEDCBA9876543210 bit 0 15 lower part of extended identifier SPLK 0000000000001000b CANMSGCTRL2 LTEEHEEEEHEL HL T H FEDCBA9876543210 bit 0 3 Data length code 1000 8 bytes bit 4 0 data frame LDP HDP CAN SPLK 0000000100000000b CANMCR Set CDR bit before writing H FEDCBA9876543210 LDP HDP CAN2 SPLK OBEBEh ANMBX2A Message to transmit SPLK 0OBABAh CANMBX2B SPLK 4HODEDEh CANMBX2C SPLK 0DADAh CANMBX2D LDP DP_CAN SPLK 0000000000000000b CANMCR Clear CDR bit after writing i IVETE EEE F FEDCBA9876543210 y EOK k k k ke ke de ke ke ke k ke ke ke ke ke ke ke ke ke ke ke ke ke ke e ke ke e ke ke e ke ke ke ke ke ke k ke ke k ke ke ke ke ke ke ke ke
374. l data through the SPI port Program to check the SCI module in 240xA Program to echo received characters back to the source Program to check ADC of 240xA Program that checks GPIO pins of 240xA as outputs Program that checks GPIO pins of 240xA as inputs Programs that perform RTR Remote Transmission Request operations in the CAN module Program to check the operation of timer 1 in EVA Program to check the operation of capture units in the EV modules Program Examples C 3 Program Examples C 2 Program Examples EEEk kkk kkk kkk kkk kk kk k k kk k k k k k k k k k k k KR k k k k k k k k k k k k k kk kk kk KR RR KK RK e e File Name Description 2407 PM cmd Linker command file to place user code sections beginning at 0000h of external program memory This file should be modified if it is desired to load code in BO memory or if on chip SARAM is to be used This example file is applicable for 2407A It needs to be modified to make it suitable for other devices vectors amp in MP mode BORK KK KK KR RK KR KK KK KR KKK KK KR KR KR OR RR RR RRR RK MEMORY PAGE 0 PM ORIGIN 0H 1 SARAM_P ORIGIN 08000H EX1_PM ORIGIN 08800H BO PM ORIGIN 0FF00h PAGE 1 REGS ORIGIN 0h BLK B2 ORIGIN 60h BLK BO ORIGIN 200h BLK B1 ORIGIN 300h SARAM D ORIGIN 0800H ORIGIN 7000h ORIGIN 8000h PERIPH EX2_DM PAGE 2 IO EX ORIGIN 0000h r r
375. l instead of RD W R is essentially an inverted R W signal from the core In the LF2407A device the W R signal will remain low all the time after reset and will go high during external write cycles In other LF240xA devices the W R signal will remain low all the time after reset until the application configures it as a GPIO pin and drives it to the desired level During reset this pin floats and gets pulled up by the internal pullup circuitry If an application needs this pin to be low even during reset then an external pulldown resistor may be added In LC240xA devices the W R signal will remain pulled up all the time from reset until the application configures it as a GPIO pin and drives it to the desired level See the External Memory Interface timings in the TMSS20LF2407A TMS320LF2406A TMS320LF2403A TMS320LF2402A TMS320LC2406A TMS320LC2404A TMS320LC2402A DSP Controllers data sheet literature number SPRS145 240xA 24x Family Compatibility 13 9 System Features Figure 13 4 Functional Block Diagram of XMIF Signals on LF2407 External pins Address bus A0 A15 C2xx i CPU core Data bus l D0 D15 XMIF module Control bus b PS DS IS STRB R W WR RD R W W R IOPCO LF2407 DSP 13 10 Digital I O GPIO Pins 13 5 Digital I O GPIO Pins Some members of the 240xA family have more GPIO pins than the 24x devices This necessitates additional registers The bit defin
376. l these bits to read interim results before an EOS Note The AUTO SEQ SR register and the RESULTn registers of the 240xA ADC module are Read only Any attempt to write to these registers causes an NMI Register Bit Descriptions 7 5 5 ADC Input Channel Select Sequencing Control Registers CHSELSEQn Figure 7 13 ADC Input Channel Select Sequencing Control Registers CHSELSEQn Bits 15 12 Bits 11 8 Bits 7 4 Bits 3 0 70A3h CONVO03 CONVO2 CONVO1 CONVO0O CHSELSEQ1 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bits 15 12 Bits 11 8 Bits 7 4 Bits 3 0 70A4h CONVO7 CONVO06 CONVO05 CONV04 CHSELSEQ2 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bits 15 12 Bits 11 8 Bits 7 4 Bits 3 0 70A5h CONV11 CONV10 CONVO09 CONVO08 CHSELSEQS3 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bits 15 12 Bits 11 8 Bits 7 4 Bits 3 0 70A6h CONV15 CONV14 CONV13 CONV12 CHSELSEQ4 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Each of the 4 bit fields CONVnn selects one of the sixteen muxed analog input ADC channels for an autosequenced conversion Analog to Digital Converter ADC 7 35 Register Bit Descriptions Table 7 8 CONVnn Bit Values and the ADC Input Channels Selected CONVnn Value ADC Input Channel Selected 0000 Channel 0 0001 Channel 1 0010 Channel 2 0011 Channel 3 0100 Channel 4 0101
377. lash run time execution at 3 3 V Flash programming requires a 5 V supply 5 at Vccp pin Flash has multiple sectors that can be protected while erasing Flash programming registers are similar to those on the 24x devices Flash programming is done through CPU U 240xA devices come with JTAG interface to aid programming and emula tion A256 word Boot ROM is available on 240xA devices to enable program ming through SCI or SPI ports The following sections explain the Flash programming registers and their bit functions Flash programming utilities will be provided by Texas Instruments Tl Refer to the Tl S web page www ti com under 24x Flash tools for revisions of these utilities 3 3 2 Flash Control Mode Register FCMR The Flash control mode register is in internal I O space FFOFh This register is a dummy register address to enable the Flash in Flash array mode or in Flash control register mode Memory 3 3 Flash The Flash control registers are used to program the Flash array These registers are a part of the Flash wrapper and are mapped at the same start address as the Flash array itself These registers are not visible disabled during Flash array mode i e Flash read During the Flash control register mode the Flash program control registers are enabled and the Flash array is disabled i e not accessible to CPU 3 3 3 Flash Control Register Access In addition to the flash memory array the
378. lations SCI serial communications interface asynchronous baud register values for common SCI bit rates BCRT1 bit configuration register 1 BCR2 bit configuration register 2 BCRn bit configuration registers bit timing CAN controller area network examples bit reversed indexed addressing block diagrams autosequenced ADC in cascaded mode autosequenced ADC with dual sequencers Boot EN XF feature CAN module TMS320x240xA Index 2 capture units EVA capture units EVB compare unit EVA EVB dead band unit EV general purpose timer event manager A EVA event manager B EVB output logic for PWM mode peripheral interrupt expansion PIE PWM circuits QEP circuit for EVA QEP circuit for EVB SCI serial communication interface block diagram watchdog timer WD module XMIF signals on LF2407 block start signal SCI serial communications inter face sending a block start signal Boot EN XF pin operation boot ROM loader introduction boot load sequence example hardware configuration for LF240xA boot ROM operation memory maps for the LF2407A devices in micro controller modeA protocol definitions SCI asynchronous transfer protocol and data formats baud rate protocol clock speeds at which baud rate locks data transfer flow chart for the serial loader baud rate match algorithm flowchart for FETCH SCI WORD flowchart for serial asynchronous loader and the fetch header routine SCI data transfer completion D 8 SP
379. lights Figure 1 1 provides a graphical overview of the devices Figure 1 1 240xA Device Overview XINT1 IOPA2 RS CLKOUT IOPEO TMS2 BIO IOPC1 MP MC BOOT EN XF Vpp 3 3 V Vss TP1 DARAM BO 256 Words PLL clock DARAM B1 256 Words 10 Bit ADC with twin autosequencer DARAM B2 32 Words SARAM 2K Words TP2 VccP SV A0 A15 D0 D15 PS DS IS R W RD READY STRB WE ENA 144 VIS OE WIR IOPCO PDPINTA CAP1 QEP1 IOPA3 CAP2 QEP2 IOPA4 CAP3 IOPA5 PWM1 IOPA6 PWM2 IOPA7 PWM3 IOPBO PWM4 IOPB1 PWMBS IOPB2 PWM6 IOPB3 T1PWM T1CMP IOPB4 T2PWM T2CMP IOPB5 TDIRA IOPB6 TCLKINA IOPB7 Flash ROM 82K Words 4K 12K 12K 4K Digital I O shared with other pins External memory interface JTAG port Event manager A Event manager B e 3 x Capture input 6 x Compare PWM output 2x GP timers PWM e 3 x Capture input e 6 x Compare PWM output 2 x GP timers PWM PLLF PLLVCCA PLLF2 XTAL1 CLKIN ADCINO8 ADCIN15 VCCA VSSA VREFHI VREFLO XINT2 ADCSOC IOPDO SCITXD IOPAO SCIRXD IOPA1 SPISIMO IOPC2 SPISOMI IOPC3 SPICLK IOPC4 SPISTE IOPC5 CANTX IOPC6 CANRX IOPC7 Port A 0 7 IOPA 0 7 Port B 0 7 IOPB 0 7 Port C 0 7
380. low timeout selections WD reset key register WDKEY WD timer control register WDCR WD timer clock watchdog timer clock waveforms SPI serial peripheral interface examples CLOCK POLARITY 0 CLOCK PHASE 0 CLOCK POLARITY 0 CLOCK PHASE 1 CLOCK POLARITY 1 CLOCK PHASE 0 CLOCK POLARITY 1 CLOCK PHASE 1 SPISTE behavior in master mode SPISTE behavior in slave mode WDCNTR watchdog counter register 11 8 Index WDCR watchdog timer control XINT2CR XINT2 control register register XMIF qualifier signal description WDKEY watchdog reset key data address data visibilit register functional timing WSGR 2407A wait state generator program address data visibility control register functional timing signal description table XINT1CR XINT1 control register Index 23 Index Index 24
381. ls Keep the loop filter R1 C2 and C2 components close to their pins PLLF and PLLF2 This is the primary entry point for noise which can result in increased jitter All PCB traces pertaining to the PLL circuit must be kept as short as possible In addition the loop area formed by the loop filter components PCB traces and DSP chip should be as small as possible A bypass capacitor 0 1 uF to 0 01 uF ceramic should be connected between the PLLVcca and Vss pins 4 2 2 4 Power Connections The diagram of Figure 4 2 illustrates how to minimize jitter and EMI by properly filtering Vpp and by using private traces up to the pins as much as possible While Cpypass is required for proper circuit operation the T filter is optional and is needed only if minimal CPU CLOCK jitter is required in the application This is a function of the amount of system noise on the circuit board Because this noise is difficult to quantify optimal results are obtained experimentally Figure 4 2 Power and Ground Connections PLLF Loop filter components Make no other connections to T PLLF PLLF2 pins PLLF2 Clock module Optional filter circuit fc 10 MHz Vpp SY ee gt E L2 PLLVCCA Cf p Cbypass e e V Vss Pick Vss pin nearest to PLLVCCA pin Clocks and Low Power Modes 4 5 Phase Locked Loop PLL You should adhere to the following guidelines when connecting the PLL pins 1 2 3 Connect the
382. ls and may contain on chip registers These spaces provide a total address space of 192K words The 240xA devices include on chip memory to aid in system performance and integration The advantages of operating from on chip memory are _j Higher performance than external memory because the wait states re quired for slower external memories are avoided Lower cost than external memory Lower power consumption than external memory The advantage of operating from external memory is the ability to access a larger address space Only the 2407A has an external memory interface Other devices have only on chip memory Refer to the device data sheets for the corresponding memory maps Memory 3 5 Program Memory 3 5 Program Memory In addition to storing the user code the program memory also stores immediate operands and table information A maximum of 64K 16 bit words can be addressed in the program memory for 240xA This number includes on chip DARAM and flash EEPROM ROM Whenever an off chip memory location needs to be accessed the appropriate control signals for external access PS DS STRB etc are automatically generated Figure 3 1 shows the LF2407A program memory map Figure 3 1 Program Memory Map for LF2407A Reset Interrupt level 1 Interrupt level 2 Interrupt level 3 Interrupt level 4 Interrupt level 5 Interrupt level 6 Reserved TRAP NMI
383. ls can be chosen in any desired order and the same channel may be selected multiple times Analog to Digital Converter ADC 7 7 ADC Overview 7 2 2 Uninterrupted Autosequenced Mode The following description applies to the 8 state sequencers SEQ1 or SEQ2 In this mode SEQ1 SEQ2 can autosequence up to eight conversions of any channel in a single sequencing session The result of each conversion is stored in one of the eight result registers RESULTO RESULT7 for SEQ1 and RESULT8 RESULT15 for SEQ2 These registers are filled from the lowest address to the highest address The number of conversions in a sequence is controlled by MAX CONVn a 3 bit or 4 bit field in the MAXCONV register which is automatically loaded into the sequencing counter status bits SEQ CNTR3 0 in the autosequence status register AUTO SEQ SR at the start of an autosequenced conversion session The MAX CONVn field can have a value ranging from zero to seven SEQ ONTRn bits count down from their loaded value as the sequencer starts from state CONVOO and continues sequentially CONVO1 CONVO2 and so on until SEQ CNTRn has reached zero The number of conversions completed during an autosequencing session is equal to MAX CONVn 1 Example 7 1 Conversion in Dual Sequencer Mode Using SEQ1 7 8 Suppose seven conversions are desired from SEQ i e Channels 2 3 2 3 6 7 and 12 need to be converted as part of the autosequenced session then MAX
384. m the TMODE1 0 bits has changed and this code will have to be modified when porting code from the 240 to the 240xA The 32 bit timer mode cannot be used Capture 4 on the 240 cannot be used when porting code from the 240 to the 240xA The capture units can use either GP Timer 1 or 2 as a time base When porting code from the the 240 to the 240xA the capture interrupt code needs to allow for the fact that an interrupt is usually generated after every second capture and not every capture as on the 240 The GEP logic can clock GP timer 1 or 2 The three simple compare units cannot be used The compare mode of the full compare units cannot be used only the PWM mode can be used Software must change from 240 to 240xA to comprehend the changes to the dead band counters and dead band prescaler All general interrupt service routines must be changed to get their periph eral interrupt vectors from the PIVR 701Eh and not one of EVIVRA EVIVRB or EVIVRC Reading from PIVR does not clear interrupt flags In terrupt flags must be cleared manually Some pins in the EV have an input qualification circuitry See the TMS320LF2407A TMS320LF2406A TMS320LF2403A TMS320LF2402A TMS320LC2406A TMS320LC2404A TMS320LC2402A DSP Controllers Data Sheet literature number SPRS145 for more details 240xA 240 Family Compatibility 12 3 Analog to Digital Converter Serial Communications Interface Serial Peripheral Interface Watchdog Timer
385. mary of Programmable Registers on the 240xA Table B 1 Summary of Programmable Registers on the 240xA Continued B 4 Data Memory Address 70A5h 70A6h 70A7h 70A8h 70A9h 70AAh 70ABh 70ACh 70ADh 70AEh 70AFh 70BOh 70B1h 70B2h 70B3h 70B4h 70B5h 70B6h 70B7h 70B8h 7100h 7101h 7102h 7103h 7104h 7105h 7106h 7107h 7108h Register Mnemonic CHSELSEQ3 CHSELSEQ4 AUTO_SEQ_SR RESULTO RESULT1 RESULT2 RESULT3 RESULT4 RESULT5 RESULT6 RESULT7 RESULT8 RESULT9 RESULT10 RESULT11 RESULT12 RESULT13 RESULT14 RESULT15 CALIBRATION Register Name Channel Select Sequencing Control Register 3 Channel Select Sequencing Control Register 4 Autosequence Status Register Conversion Result Buffer Register 0 Conversion Result Buffer Register 1 Conversion Result Buffer Register 2 Conversion Result Buffer Register 3 Conversion Result Buffer Register 4 Conversion Result Buffer Register 5 Conversion Result Buffer Register 6 Conversion Result Buffer Register 7 Conversion Result Buffer Register 8 Conversion Result Buffer Register 9 Conversion Result Buffer Register 10 Conversion Result Buffer Register 11 Conversion Result Buffer Register 12 Conversion Result Buffer Register 13 Conversion Result Buffer Register 14 Conversion Result Buffer Register 15 Calibration result which is used to correct subsequent conversions Controller Area Network CAN MDER TCR RCR MCR BCR2 BCR1 ESR GSR CEC Mailbox Di
386. me if the old password is known In ROM devices the password cannot be changed after the device is manufactured by Texas Instruments TI If PWL have all 64 bits as ones or zeros the device is unsecure Since new flash devices have erased flash all ones the device comes up in unsecure mode To summarize a device with a cleared erased flash array is unsecure KEY registers User accessible registers four 16 bit words which will be used to secure or unsecure the device These registers are mapped in the data memory space at addresses 77FOh 77F1h 77F2h and 77F3h Flash ROM Code Security For LF LC240xA DSP Devices E 5 Technical Definitions Table E 2 Code Security Module CSM Registers Data Memory Address 77F0h 77F1h 77F2h 77F3h Program Memory Address 0040h 0041h 0042h 0043h E 6 Register Name Reset Values KEY3 KEY2 KEY1 KEYO PWLS PWL2 PWL1 PWLO FFFFh FFFFh FFFFh FFFFh 0000 FFFFh or user defined 0000 FFFFh or user defined 0000 FFFFh or user defined 0000 FFFFh or user defined Register Description High word of the 64 bit KEY register KEY registers Accessible by the user Third word of the 64 bit KEY register Second word of the 64 bit KEY register Low word of the 64 bit KEY register PWL in program memory Reserved for passwords only High word of the 64 bit password Third word of the 64 bit password Second word of the 64 bit password Low word
387. mer reset are ORed together to drive the reset input to the CPU 2 12 Illegal Address Detect The decode logic has the capability to detect accesses to illegal addresses all unimplemented addresses including reserved registers in each peripheral s memory map The occurrence of an illegal access sets the illegal address flag ILLADR in System Control and Status Register 1 SCSR1 See section 2 2 1 System Control and Status Registers 1 and 2 SCSH1 SCSR2 on page 2 3 The detection of an illegal address generates a nonmaskable interrupt NMI The illegal address condition is asserted whenever illegal addresses are accessed The illegal address flag ILLADR remains set following an illegal address condition until it is cleared by software A common reason for illegal address access and hence NMI is incorrect data page initialization External Interrupt Control Registers 2 13 External Interrupt Control Registers The two external interrupt control registers that control and monitor XINT1 and XINT2 pin activities are XINT1CR and XINT2CR In the 240xA devices the XINT1 and XINT2 pins must be held low for six or 12 CLKOUT cycles before they are recognized by the core 2 13 1 External Interrupt 1 Control Register XINT1CR Figure 2 17 External Interrupt 1 Control Register XINT1CR Address 7070h 15 14 3 2 1 0 XINT1 flag XINT1 polarity XINT1 priority XINT1 enable RC 0 R 0 RW 0 RW 0 RW 0 Note R Read access W Write a
388. mission Ch1 Period 398 ns SPISIMO SPISTE 300v ths 200v MT Oops Chi 7 1 52V Serial Peripheral Interface SPI 9 35 Chapter 10 CAN Controller Module This chapter describes the controller area network CAN module available on some members of the 24x 240xA family The interface signals configuration registers and mailbox RAM are described in detail however the CAN protocol itself is not discussed in depth For details on the protocol refer to CAN Specification Version 2 0 by Robert Bosch GmBH Germany The CAN module is a full CAN controller designed as a 16 bit peripheral and is fully compliant with the CAN protocol version 2 0B Topic Page 10 1 Introduction vetere rutru eir ee EE 10 2 10 2 Overview of the CAN Network eeeeeeeeennnnn 10 3 10 32 Message Objeciss c ele 10 9 10 4 GAN GontroliRegisters 252 099 2925 929222 20 9 922 cows 10 19 10 5uStatus Registers a E 30 5 InferruptEogic 5 enor emcee as ee aera ed 10 35 107 Configuration Mode E 10 39 10 8 Power Down Mode PDM 0ecceeeeeceeeeeeeeeaees 10 40 10 9 Suspend Mode R EE 10 41 10 1 Introduction 10 1 Introduction The CAN peripheral supports the following features E L LE E g E Full implementation of CAN protocol version 2 0B m Standard and extended identifiers m Data and remote frames Six mailboxes for objects with data lengths of 0 to 8
389. mitted or in a mailbox of anoth er CAN module if it is configured for this frame data frame Receive mailbox RMP 1 remote frame RTR 1 Receive mailbox RFP 1 RMP 1 CPU handles situation remote frame RTR 1 Receive mailbox P TRS 0 TAremains 0 no mailbox interrupt asserted The receive mailbox contains the ID RTR DLC and TRS of this mailbox 2 or 3 1 The answer is received in this receive mailbox if permitted or in a mailbox of another CAN module if it is configured for this frame 10 3 8 Acceptance Filter The identifier of the incoming message is first compared to the message identifier of the receive mailbox which is stored in the mailbox in MSGIDnH and MSGIDnL registers Then the appropriate acceptance mask is used to mask out the bits of the identifier that should not be compared The local acceptance mask can be disabled by setting the acceptance mask enable AME bit to 0 in the message identifier high word MSGIDn field Local Acceptance Mask LAM 10 16 The local acceptance filtering allows the user to locally mask that is treat as a don t care any identifier bit of the incoming message Local acceptance mask register LAM1 is used for mailboxes 2 and 3 while local acceptance mask register LAMO is used for mailboxes 0 and 1 During Message Objects a reception mailboxes 3 and 2 are checked before mailboxes 1 and O Figure 10 9 illustrates the LAMn H high word and
390. mpare Output The compare output of a GP timer can be specified active high active low forced high or forced low depending on how the GPTCONA B bits are configured It goes from low to high high to low on the first compare match when it is active high low It then goes from high to low low to high on the second compare match if the GP timer is in an up down counting mode or on period match if the GP timer is in up counting mode The timer compare output becomes high low right away when it is specified to be forced high low Timer Counting Direction Timer Clock The counting directions of the GP timers are reflected by their respective bits in GPTCONAPB during all timer operations as follows _j 1represents the up counting direction Orepresents the down counting direction The input pin TDIRA B determines the direction of counting when a GP timer is in directional up down counting mode When TDIRA B is high upward counting is specified when TDIRA B is low downward counting is specified The source of the GP timer clock can be the internal device clock or the external clock input TCLKINA B The frequency of the external clock must be less than or equal to one fourth of that of the device clock GP timer 2 EVA and GP timer 4 EVB can be used with the QEP circuits in directional Event Manager EV 6 19 General Purpose GP Timers up down counting mode In this case the QEP circuits provide both the clock
391. n a value of 55h is written to the WDKEY When the next AAh value is written to the WDKEY then the WDCNTR actually is reset Any value written to the WDKEY other than 55h or AAh causes a system reset Any sequence of 55h and AAh values can be written to the WDKEY without causing a system reset only a write of 55h followed by a write of AAh to the WDKEY resets the WDCNTR Watchdog WD Timer 11 5 Watchdog Timer Operations Table 11 1 shows a typical sequence written to WDKEY after power up Table 11 1 Typical WDKEY Register Power Up Sequence 11 2 4 3 WD Reset Sequential Value Written Step to WDKEY Result 1 AAh No action 2 AAh No action 3 55h WDONTR is enabled to be reset by the next AAh 4 55h WDONTR is enabled to be reset by the next AAh 5 55h WDONTR is enabled to be reset by the next AAh 6 AAh WDCNTR is reset 7 AAh No action 8 55h WDONTR is enabled to be reset by the next AAh 9 AAh WDCNTR is reset 10 55h WDONTR is enabled to be reset by the next AAh 11 23h System reset due to an improper key value writ ten to WDKEY Step 3 above is the first action that enables the WDCNTR to be reset The WDCNTR is not actually reset until step 6 Step 8 re enables the WDCNTR to be reset and step 9 resets the WDCNTR Step 10 again re enables the WDCNTR to be reset Writing the wrong key value to the WDKEY in step 11 causes a system reset A WDONTR overflow or an incorrect key value written to the WDKEY also sets the WD flag W
392. n extended identifier 29 bits The message to be sent has an extended identifier 29 bits T In case of a receive mailbox t In case of a transmit mailbox Bit 14 AME Acceptance Mask Enable Bit 0 No acceptance mask will be used All identifier bits in the received message and the receive MBOX must match in order to store the message 1 The corresponding acceptance mask is used This bit will not be affected by a reception This bit is relevant for receive mailboxes only Hence it is applicable for MBOXO0 and MBOX1 and also for MBOX2 and MBOX3 if they are configured as receive mailboxes It is a don t care for mailboxes 4 and 5 10 10 Message Objects Bit 13 AAM Auto Answer Mode Bit 0 Transmit The mailbox does not reply to remote requests mailbox automatically If a matching identifier is received it is not stored Receive No influence on a receive mailbox mailbox 1 Transmit If a matching remote request is received the CAN mailbox peripheral answers by sending the contents of the mailbox Receive No influence on a receive mailbox mailbox This bit is only used for mailboxes 2 and 3 This bit will not be affected by a reception Bits 12 0 IDH 28 16 Upper 13 Bits of extended identifier For a standard identifier the 11 bit identifier will be stored in bits 12 to 2 of the MSGID s upper word Figure 10 6 Message Identifier for Low Word Mailboxes 0 5 MSGIDnL 15 0 RW Note R Read access W Write access
393. n mode of the compare units is determined by the bits in COMCONx These bits determine 1 Whether the compare operation is enabled Whether the compare outputs are enabled The condition on which the compare registers are updated with the values in their shadow registers L Whether space vector PWM mode is enabled The following paragraph describes the operation of the EVA compare unit The operation of the EVB compare unit is identical For EVB GP timer 3 and ACTRB are used The value of the GP timer 1 counter is continuously compared with that of the compare register When a match is made a transition appears on the two outputs of the compare unit according to the bits in the action control register ACTRA The bits in ACTRA can individually specify each output to be toggled active high or toggled active low if not forced high or low on a compare match The compare interrupt flag associated with a compare unit is set when a compare match is made between GP timer 1 and the compare register of this Compare Units compare unit if compare is enabled A peripheral interrupt request is generated by the flag if the interrupt is unmasked The timing of output transitions setting of interrupt flags and generation of interrupt requests are the same as that of the GP timer compare operation The outputs of the compare units in compare mode are subject to modification by the output logic dead band units and the space vector PWM logic
394. n result used to correct Subsequent conversions SPI registers SPICCR set 7040h SPI Config Control register SPICTL set 7041h SPI Operation Control register SPISTS set 7042h SPI Status register SPIBRR set 7044h SPI Baud rate control register SPIRXEMU set 7046h SPI Emulation buffer register SPIRXBUF set 7047h SPI Serial receive buffer register SPITXBUF set 7048h SPI Serial transmit buffer register SPIDAT set 7049h SPI Serial data register SPIPRI set 704Fh SPI Priority control register SCI registers SCICCR set 7050h SCI Communication control register SCICTL1 set 7051h SCI Control register 1 SCIHBAUD set 7052h SCI Baud Rate MS byte register SCILBAUD set 7053h SCI Baud Rate LS byte register SCICTL2 set 7054h SCI Control register 2 SCIRXST set 7055h SCI Receiver Status register SCIRXEMU set 7056h SCI Emulation Data Buffer register SCIRXBUF set 7057h SCI Receiver Data buffer register SCITXBUF set 7059h SCI Transmit Data buffer register SCIPRI set 705Fh SCI Priority control register Event Manager A EVA registers GPTCONA set 7400h GP Timer control register A T1CNT set 7401h GP Timer 1 counter register TLCMPR set 7402h GP Timer 1 compare register T1PR set 7403h GP Timer 1 period register T1CON set 7404h GP Timer 1 control register T2CNT set 7405h GP Timer 2 counter register T2CMPR set 7406h
395. n the SPIRXBUF was overwritten by the SPI module before the previous character was read by the user application The SPI requests Bit 6 Bit 5 Bits 4 0 SPI Module Registers one interrupt sequence each time this bit is set if the OVERRUN INT ENA bit SPICTL 4 is set high The bit is cleared in one of three ways L Writing a 1 to this bit L Writing a 0 to SPI SW RESET SPICCR 7 4 Resetting the system If the OVERRUN INT ENA bit SPICTL 4 is set the SPI requests only one interrupt upon the first occurrence of setting the RECEIVER OVERRUN Flag bit Subsequent overruns will not request additional interrupts if this flag bit is already set This means that in order to allow new overrun interrupt requests the user must clear this flag bit by writing a 1 to SPISTS 7 each time an overrun condition occurs In other words if the RECEIVER OVERRUN Flag bit is left set not cleared by the interrupt service routine another overrun interrupt will not be immediately re entered when the interrupt service routine is exited However the RECEIVER OVERRUN Flag bit should be cleared during the interrupt service routine because the RECEIVER OVERRUN Flag bit and SPI INT FLAG bit SPISTS 6 share the same interrupt vector This will alleviate any possible doubt as to the source of the interrupt when the next byte is received SPI INT FLAG SPI Interrupt Flag SPI INT FLAG is a read only flag The SPI hardware sets this bit to indicate that it has
396. ncrement decrement or compare the contents of the auxiliary registers Its primary function is manipulating auxiliary register values for indirect addressing auxiliary register pointer ARP A 3 bit field in status register STO that points to the current auxiliary register auxiliary register pointer buffer ARB A 3 bit field in status register ST1 that holds the previous value of the auxiliary register pointer ARP BO Anon chip block of dual access RAM that can be configured as either data memory or program memory depending on the value of the CNF bit in status register ST1 B1 Anon chip block of dual access RAM available for data memory B2 Anon chip block of dual access RAM available for data memory BIO pin A general purpose input pin that can be tested by the conditional branch instruction BCND that causes a branch when BIO is driven low externally bit reversed indexed addressing A method of indirect addressing that allows efficient I O operations by resequencing the data points in a radix 2 fast Fourier transform FFT program The direction of carry propagation in the ARAU is reversed bootloader A built in segment of code that transfers code from an external source to a 16 bit external program destination at reset branch A switching of program control to a nonsequential program memory address BRR The value in the baud select registers SPI Glossary C bit See carry bit CALU See central arithmet
397. nd CAP3FIFO in the case of EVA or CAP4FIFO CAP5FIFO and CAP6FIFO in the case of EVB The bottom stack consists of CAP1FBOT CAP2FBOT and CAP3FBOT in the case of EVA or CAP4FBOT CAP5FBOT and CAP6FBOT in the case of EVB The top level register of any of the FIFO stacks is a read only register that always contains the oldest counter value captured by the corresponding capture unit Therefore a read access to the FIFO stack of a capture unit always returns the oldest counter value stored in the stack When the oldest counter value in the top register of the FIFO stack is read the newer counter value in the bottom register of the stack if any is pushed into the top register If desired the bottom register of the FIFO stack can be read Reading the bottom register of the FIFO stack causes the FIFO status bits to change to 01 has one entry if they were previously 10 or 11 If the FIFO status bits were previously 01 when the bottom FIFO register is read they will change to 00 empty The counter value of the selected GP timer captured by a capture unit when a specified transition happens on its input pin is written into the top register of the FIFO stack if the stack is empty At the same time the corresponding status bits are set to 01 The status bits are reset to 00 if a read access is made to the FIFO stack before another capture is made If another capture occurs before the previously captured counter value is read the newl
398. nd Timer Control Register A DBTCONA Address xx15h Dead Band Timer Control Register B DBTCONB Address xx15h Dead Band Unit Block Diagram x 1 2 OF 3 22 1 eee eee Output Logic Block Diagram x 1 2 or 3 y 1 2 3 4 5 or 6 2 eee Asymmetric PWM Waveform Generation With Compare Unit and PWM Circuits OCS TEIL MCCC E Symmetric PWM Waveform Generation With Compare Units and PWM Circuits x 1 3 ODB sss da gie mr RE E REEN REAR RESO De d d aad oad 3 Phase Power Inverter Schematic Diagram eunan en annann Basic Space Vectors and Switching Patterns 0 cece eee ee eee Symmetric Space Vector PWM Waveforms 6 cece eee ees Capture Units Block Diagram EVA 00 cece eee eee eee Capture Units Block Diagram EVB 0000 cece eee teens Capture Control Register A CAPCONA Address 7420h 02000 0c eee Capture Control Register B CAPCONB Address 7520h 0c eee Capture FIFO Status Register A CAPFIFOA Address 7422h uuu Capture FIFO Status Register B CAPFIFOB Address 7522h uuu Quadrature Encoder Pulse QEP Circuit Block Diagram for EVA uuu Quadrature Encoder Pulse QEP Circuit Block Diagram for EVB Figures Quadrature Encoded Pulses and Decoded Timer Clock and Direction EVA Interrupt Flag Regist
399. nd literature number Many of these documents are located on the In ternet at http www ti com TMS320C24x DSP Controllers CPU and Instruction Set Reference Guide literature number SPRU160 describes the TMS320C24x 16 bit fixed point digital signal processor controller Covered are its architecture internal register structure data and program addressing and instruction set Also includes instruction set comparisons and design considerations for using the XDS510 emulator TMS320LF2407 TMS320LF2406 TMS320LF2402 DSP Controllers literature jell Saba data sheet contains the electrical and timing specifications for these devices as well as signal descriptions and pinouts for all of the available packages TMS320LF2407A TMS320LF2406A TMS320LF2403A TMS320LF2402A TMS320LC2406A TMS320LC2404A TMS320LC2402A DSP Controllers literature number SPRS145 data sheet contains the electrical and timing specifications for these devices as well as signal descriptions and pinouts for all of the available packages TMS320LF2401A TMS320LC2401A DSP Controllers literature number data sheet contains the electrical and timing specifications for these devices as well as signal descriptions and pinouts for available packages Read This First V Helated Documentation From Texas Instruments vi TMS320C 1x C2x C2xx C5x Code Generation Tools Release 6 60 Getting Started Guide literature number SPRU121 describes how to install the TMS320C1x
400. ne decompose Ugyt and perform the following for each PWM period m m m m Determine the two adjacent vectors Uy and U 60 Determine the parameters T4 To and To Write the switching pattern corresponding to Ux in ACTRx 14 12 and 1 in ACTRx 15 or the switching pattern of Ux 60 in ACTRx 14 12 and 0 in ACTRx 15 Put 1 2 T1 in CMPR1 and 1 2 T1 1 2 T2 in CMPR2 Space Vector PWM Hardware The space vector PWM hardware in the EV module does the following to complete a space vector PWM period Ll m At the beginning of each period sets the PWM outputs to the new pattern Uy defined by ACTRx 14 12 On the first compare match during up counting between CMPR1 and GP timer 1 at 1 2 T1 switches the PWM outputs to the pattern of Uy eo if ACTRx 15 is 1 or to the pattern of Uy if ACTRx 15 is 0 Ug 60 Uaoo U360 60 U60 On the second compare match during up counting between CMPR2 and GP timer 1 at 1 2 T1 1 2 T2 switches the PWM outputs to the pattern 000 or 111 whichever differs from the second pattern by one bit On the first compare match during down counting between CMPR2 and GP timer 1 at 1 2 T1 1 2 T2 switches the PWM outputs back to the sec ond output pattern On the second compare match during down counting between CMPR1 and GP timer 1 at 1 2 T1 switches the PWM outputs back to the first pat tern Event Manager EV 6 65 Space Vector PWM Space Vector PWM Waveforms
401. ng an arbitration protocol and an error detection mechanism for a high level of data integrity 10 2 1 CAN Protocol Overview The CAN protocol supports four different frame types for communication Data frames that carry data from a transmitter node to receiver node s _ Remote frames that are transmitted by a node to request the transmis sion of a data frame with the same identifier Error frames that are transmitted by any node on a bus error detection Overload frames that provide an extra delay between the preceding and the succeeding data frames or remote frames In addition CAN Specification Version 2 0B defines two different formats that differ in the length of the identifier field standard frames with an 11 bit identifier and extended frames with a 29 bit identifier CAN standard data frames contain from 44 to 108 bits and CAN extended data frames contain 64 to 128 bits Furthermore up to 23 stuff bits can be inserted in a standard data frame and up to 28 stuff bits in an extended data frame depending on the data stream coding The overall maximum data frame length is 131 bits for a standard frame and 156 bits for an extended frame In Figure 10 1 bit fields within the data frame identify Start of the frame Arbitration field containing the identifier and the type of message being sent Control field containing the number of data Up to 8 bytes of data Cyclic redundancy check CRC Acknowledgment End of
402. ng interrupt condition occurs The appropriate mailbox interrupt request is asserted only if the corresponding interrupt mask in CAN IMR register is set The peripheral interrupt request stays active until the interrupt flag is cleared by the CPU by writing a 1 to the appropriate bit An interrupt acknowledge does not clear the interrupt flags The MIFx flags cannot be cleared by writing to the IF register instead they must be cleared by writing a 1 to the appropriate TA bit in the TCR register for a transmit mailbox mailboxes 2 to 5 or the RMP bit in the RCR register for the receive mailbox mailboxes 0 to 3 In order to recognize future interrupts the flag bit of the current interrupt s must be cleared immediately upon entering the ISR One method of implementing this is to copy the CAN_IFR register in a memory variable and then clear the set bits in CAN IFR The memory variable could then be read to determine the appropriate routines to be executed Figure 10 21 CAN Interrupt Flag Register CAN IFR Address 7109h 15 14 13 12 11 10 9 8 MIF5 MIF4 MIF3 MIF2 MIF1 MIFO 0 R 0 0 R 0 R 0 R 0 R R 7 6 5 4 3 2 1 0 RMLIF AAIF WDIF WUIF BOIF EPIF WLIF RC 0 RC 0 RC 0 RC 0 RC 0 RC 0 RC 0 Note R Read access C Clear value following dash value after reset Bits 15 14 Reserved Bits 13 8 MIFx Mailbox Interrupt Flag receive transmit 0 No message was transmitted or received 1 The corresponding mailbox transmitted or rec
403. nit if desired can also generate a PWM output based on its own timer Asymmetric and Symmetric PWM Generation Both asymmetric and symmetric PWM waveforms can be generated by every compare unit on the EV module In addition the three compare units together can be used to generate 3 phase symmetric space vector PWM outputs PWM generation with GP timer compare units has been described in the GP timer sections Generation of PWM outputs with the compare units is discussed in this section 6 6 2 Register Setup for PWM Generation All three kinds of PWM waveform generations with compare units and associated circuits require configuration of the same Event Manager registers The setup process for PWM generation includes the following steps Setup and load ACTRx Setup and load DBTCONXx if dead band is to be used Initialize CMPRx Setup and load COMCONx LE E LE Q Setup and load T1CON for EVA or T3CON for EVB to start the opera tion Rewrite CMPRx with newly determined values L PWM Waveform Generation With Compare Units and PWM Circuits 6 6 3 Asymmetric PWM Waveform Generation The edge triggered or asymmetric PWM signal is characterized by modulated pulses which are not centered with respect to the PWM period as shown in Figure 6 25 The width of each pulse can only be changed from one side of the pulse Figure 6 25 Asymmetric PWM Waveform Generation With Compare Unit and PWM Circuits x 1 3 or 5 Timer Time
404. ns interface compare action control register A ACTRA 6 44 compare action control register B ACTRB 6 46 compare control register A COMCONA compare control register B COMCONB compare operation GP timer active inactive time calculation asymmetric waveform generator asymmetric symmetric waveform generator compare PWM output in up down counting mode figure compare PWM output in up counting mode figure output logic PWM transition symmetric waveform generation compare units block diagram compare inputs outputs compare operation modes event manager interrupts operation register setup for compare unit operation registers reset lt compatibility 240xA 240 analog to digital converters event manager general serial communication interface serial peripheral interface watchdog timer 24x 240xA family compat 12 24x 240xA DSP overview 13 4 3 4 features of 24x and 240xA hae table 13 4 compatible O table 13 2 digital O GPIO pins 13 11 LF2407A shared pin configuration shared pin functions for the 240xA Teer event manager module EVB 13 14 event manager module and signal names for EVA and EVB introduction memory map LF2407A memory map for program space migrating code form 24x to 240x 240xA devices new or modified features peripherals in 240xA DSPs table system features oscillator and PLL frequency input specication ise oscilla
405. nterrupt flag of the timer is set A peripheral interrupt request is generated by the flag if it is unmasked An ADC start is sent to the ADC module at the same time if the underflow interrupt flag of this timer has been selected by appropriate bits in GPTCONAJPB to start ADC The overflow interrupt flag is set one clock cycle after the value in TxCNT matches FFFFh A peripheral interrupt request is generated by the flag if it is unmasked The duration of the timer period is TxPR 1 cycles of the scaled clock input except for the first period The duration of the first period is the same if the timer counter is zero when counting starts The initial value of the GP timer can be any value between Oh and FFFFh inclusive When the initial value is greater than the value in the period register the timer counts up to FFFFh resets to zero and continues the operation as if the initial value was zero When the initial value in the timer counter is the same as that of the period register the timer sets the period interrupt flag resets to zero sets the underflow interrupt flag and then continues the operation again as if the initial value was zero If the initial value of the timer is between zero and the contents of the period register the timer counts up to the period value and continue to finish the period as if the initial counter value was the same as that of the period register The counting direction indication bit in GPTCONAV B is one for
406. nterrupt flag register B EVBIFRC EVB interrupt flag register C EVBIMRA EVB interrupt mask register A EVBIMRB EVB interrupt mask register B EVBIMRC EVB interrupt mask register C event manager 240xA to 240 family compatibility event manager EV 6 1 asymmetric PWM waveform generation capture interrupts capture unit FIFO stacks first capture second capture third capture capture unit registers capture control register A CAPCONA capture control register B CAPCONB capture FIFO status register A CAPFIFOA capture FIFO status register B CAPFIFOB capture units block diagram EVA 6 69 block diagram EVB features compare unit interrupts compare unit registers compare action control registers ACTRn compare control registers COMCONA and COMCONB compare unit reset compare units compare inputs outputs compare operation modes operation register setup for compare unit operation comparison to C240 EV 6 5 EV interrupts 6 9 6 84 conditions for interrupt generation EV interrupt request and service EVA interrupts table EVB interrupts table flag registers interrupt flag register and corresponding interrupt mask register table interrupt generation interrupt vector EVA interrupt flag registers EVA interrupt flag register A EVAIFRA EVA interrupt flag register B EVAIFRB EVA interrupt flag register C EVAIFRC EVB interrupt flag register A EVBIFRA Index EVB interrupt fla
407. nterrupt request register 0 PIRQR 1 peripheral interrupt request register 1 PIRQR2 peripheral interrupt request register 2 PIVR peripheral interrupt vector register PLL pin names 240xA port A data and direction control register PADATDIR 5 8 I O pin designation table port B data and direction control register PBDATDIR 5 9 I O pin designation table port C data and direction control register PCDATDIR O pin designation table port control registers 240xA digital I O port control registers implementation port D data and direction control register PDDATDIR I O pin designation table port E data and direction control register PEDATDIR I O pin designation table port F data and direction control register PFDATDIR pin designation table port interrupts SCI serial communications interface Index 14 devices power down mode CAN controller area network 10 40 prescaler clock ADC ADC conversion time in 240xA ADC program address register PAR definition program and data spaces program examples 240x register definitions bit codes for bit instruction common files for all example programs linker command file to place user code sections beginning at 0000h of external program memory overview program to check GPIO pins of 240xA as inputs program to check the capture units of 240x program to check the GPIO pins of 240xA as outputs program to check the operation of TIMER1 in EVA
408. ntrol Register A GPTCONA Address 7400h 14 12 11 10 9 8 7 15 13 T2STAT TISTAT T2TOADC T1TOADC R 1 R 1 RW 0 RW 0 RW 0 RW 0 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access n value after reset Bit 15 Reserved Reads return zero writes have no effect Bit 14 T2STAT GP timer 2 Status Read only 0 Counting downward 1 Counting upward Bit 13 T1STAT GP timer 1 Status Read only 0 Counting downward 1 Counting upward Bits 12 11 Reserved Reads return zero writes have no effect Bits 10 9 T2TOADC Start ADC with timer 2 event 00 No event starts ADC 01 Setting of underflow interrupt flag starts ADC 10 Setting of period interrupt flag starts ADC 11 Setting of compare interrupt flag starts ADC Bits 8 7 T1TOADC Start ADC with timer 1 event 00 No event starts ADC 01 Setting of underflow interrupt flag starts ADC 10 Setting of period interrupt flag starts ADC 11 Setting of compare interrupt flag starts ADC Bit 6 TCOMPOE Compare output enable If PDPINTx is active this bit is set to zero 0 Disable all GP timer compare outputs all compare outputs are put in the high impedance state 1 Enable all GP timer compare outputs Event Manager EV 6 35 General Purpose GP Timers Bits 5 4 Reserved Reads return zero writes have no effect Bits 3 2 T2PIN Polarity of GP timer 2 compare output 00 Forced low 01 Active low 10 Active high 11 Forced high Bits 1 0 T1PIN Polarity of GP
409. o be set in GSR SPLK 0000000000000000b CANBCR2 For 1 Mbps 20 MHz CLKOUT SPLK 0000000000000001b CANBCR2 For 1 Mbps 40 MHz CLKOUT H FEDCBA9876543210 bit 0 7 Baud rate prescaler bit 8 15 Reserved SPLK 0000000011111010b CANBCR1 For 1 Mbps 85 samp pt FEDCBA9876543210 bit 0 2 TSEG2 bit 3 6 TSEG1 bit 7 Sample point setting 1 3 times 0 once bit 8 9 Synchronization jump width bit A F Reserved SPLK 0000000000000000b CANMCR i LLEEEELELEE TT T I FEDCBA9876543210 C 28 Program Examples bit 12 Change conf register W NCCE BIT CANGSR 0Bh Wait for Change config disable BCND W NCCE TC y EK k k k k ke o ke KERR KERR KERR KERR ke ke ke ke ke RK KER RK ERK ERK KERR KER ERE k k k k k k k k k k k k y Ek kkk kkk kkk TRANSMIT kckckckckckck ko kk PE d LL ke k k ke ke k ke ke k ke ke k ke ke k ke k k k k k k k k k LC RK KERR KERR KERR KERR k k k k k k k k k k k k k k k k k k SPLK 0020h CANTCR Transmit request for MBX3 W TA BIT CANTCR 2 Wait for transmission acknowledge BCND W TA NTC SPLK 2000h CANTCR reset TA RX LOOP W_RA BIT CANRCR BIT7 Wait for data from remote node BCND W_RA NTC to be written into MBX3 LOOP B LOOP GISR1 GISR2 GISR3 GISR4 GISR5 GISR6 PHANTOM RET end Program Examples C 29 Program Examples EV T1INT P File name Description Mode Output asm PROGRAM TO CHECK THE OPERATION OF TIMER1 IN EVA Cont
410. o the GPIO pins of 240xA It ouputs a total of 8 bit patterns to the five GPIO ports A B C E F Each bit pattern forces a particular bit low and forces the other 7 pits high This goes on in an endless loop title 240xA GPIO data Loaded 9 300h in data memory bo word OFFFEh Turn on GPIOO bi word OFFFDh Turn on GPIO1 b2 word OFFFBh Turn on GPIO2 b3 word OFFF7h Turn on GPIO3 b4 word OFFEFh Turn on GPIO4 b5 word OFFDFh Turn on GPIO5 b6 word OFFBFh Turn on GPIO6 b7 word OFF7Fh Turn on GPIO7 GPRO word 0 Gen purp reg include 240xA h MACRO Definitions KICK DOG macro Watchdog reset macro LDP 00E0h DP gt 7000h 707Fh SPLK 05555h WDKEY SPLK HOAAAAh WDKEY LDP 0h DP gt 0000h 007Fh endm text START LDP 0h Set DP 0 SETC INTM Disable interrupts SETC CNF SPLK 0000h IMR Mask all core interrupts LACC IFR Read Interrupt flags SACL IFR Clear all interrupt flags LDP 00E0h E0 224 E0 80 7000 SPLK 0000h SCSR1 SPLK 006Fh WDCR Disable WD KICK DOG SPLK 0h GPRO Set wait state generator for OUT GPRO WSGR external address space LDP 00E1h SPLK 00000h MCRA Select IOPAn amp IOPBn as GPIO pins SPLK HOFF00h MCRB Select IOPCn as GPIO pins SPLK 00000h MCRC Select IOPEn amp IOPFn as GPIO pins SPLK OFFFFh PADATDIR All pins are o p s C 20 MAIN LOOP DELAY D LOOP PHANTOM SPLK HOFFFFh SPLK HOFFFFh SPLK OFFFFh SPLK OFFF
411. ocessor mode program memory On chip flash ROM and bootloader disabled Using TI debugger Secure Debugging testing the ex Code Composer device with the aid of a JTAG connector While running BOOT XF BOOT EN 0 Secure On chip bootloader is ROM code upon reset invoked Flash ROM Security Feature Mode 1 This is the typical mode that would be employed in the end customer application The application code stored in on chip flash ROM free runs In this mode the device is unsecure since the core should be able to read the contents of on chip flash ROM to be able to execute it The JTAG port is left unconnected Connecting the JTAG connector would immediately secure the device thereby thwarting any attempt to read the contents of flash ROM To reiterate during run time execution of the application the device will run the application without any impact from the Code Security Module CSM which is inactive If visibility to flash ROM contents is desired the device must be first unsecured Mode 2 If the DSP is powered up in microprocessor mode the device is immediately secured If a code running in external memory needs to access the on chip flash memory the device must be first unsecured Mode 3 If access to on chip flash ROM is desired using a debugger via JTAG the device must be first unsecured Mode 4 If the on chip bootloader is invoked the device is immediately secured If the bootloader transfers any code that needs
412. ock Diagram ssssssssssssess General Purpose Timer Block Diagram x 2 or 4 when x 2 y 21 andn 22 whenx 4 y 3andn 4 Timer x Counter Register TxCNT where x 1 2 3 or 4 lt Timer x Compare Register TXCMPR where x 1 2 3 or 4 o Timer x Period Register TxPR where x 1 2 3 0r 4 2 0002 c eee ee eee GP Timer Continuous Up Counting Mode TxPR 30r2 o GP Timer Directional Up Down Counting Mode Prescale Factor 1 and TxPR 3 GP Timer Continuous Up Down Counting Mode TXPR 3 or 2 GP Timer Compare PWM Output in Up Counting Mode GP Timer Compare PWM Output in Up Down Counting Modes Timer x Control Register TxCON x 1 2 3 or 4 Addresses 7404h T1CON 7408h T2CON 7504h T3CON and 7508h TACON 2 GP Timer Control Register A GPTCONA Address 7400h nnn GP Timer Control Register B GPTCONB Address 7500h nn nn Compare Unit Block Diagram For EVA x 21 2 3 y 1 3 5 z f For EVB x 4 567 27 9 11 29 3 xou des DE exe oc edd Bd ede di Compare Control Register A COMCONA Address 7411h 000 ee Compare Control Register B COMCONB Address 7511h annn Compare Action Control Register A ACTRA Address 7413h Luuue Compare Action Control Register B ACTRB Address 7513h PWM Circuits Block Diagram lt seana sannau apana I I Dead Ba
413. of 64K serial clock rates for the communication modes The SCI baud rate is calculated using the following equation CLKOUT SCI Asynchronous Baud BRR 1 X 8 Alternatively BRR CLKOUT 1 SCI Asynchronous Baud x 8 Note that the above formulas are applicable only when 1 lt BRR lt 65535 If BRR 0 then CLKOUT SCI Asynchronous Baud 16 Where BRR the 16 bit value in decimal in the baud select registers SCI Module Registers 8 7 4 SCI Control Register 2 SCICTL2 SCICTL2 enables the receive ready break detect and transmit ready interrupts as well as transmitter ready and empty flags Figure 8 14 SCI Control Register 2 SCICTL2 Address 7054h 7 6 5 2 1 0 TXRDY TX EMPTY RX BK INT ENA TX INT ENA R 1 R 1 R 0 RW 0 RW 0 Note R Read access W Write access n value after reset Bit 7 TXRDY Transmitter buffer register ready flag When set this bit indicates that the transmit data buffer register SCITXBUF is ready to receive another character Writing data to the SCITXBUF automatically clears this bit When set this flag asserts a transmitter interrupt request if the interrupt enable bit TX INT ENA SCICTL2 0 is also set TXRDY is set to 1 by enabling the SW RESET bit SCICTL 2 or by a system reset 0 SCITXBUF is full 1 SCITXBUF is ready to receive the next character Bit 6 TX EMPTY Transmitter empty flag This flag s value indicates the contents of the transmitter s buff
414. of DSP Controllers Designers have recognized the opportunity to redesign existing digital motor control DMC systems to use advanced algorithms that yield better performance and reduce system component count DSPs enable Design of robust controllers for a new generation of inexpensive motors such as AC induction DC permanent magnet and switched reluctance motors Full variable speed control of brushless motor types that have lower manufacturing cost and higher reliability Energy savings through variable speed control saving up to 25 of the energy used by fixed speed controllers Increased fuel economy improved performance and elimination of hydraulic fluid in automotive electronic power steering EPS systems J Reduced manufacturing and maintenance costs by eliminating hydraulic fluid in automotive electronic braking systems More efficient and quieter operation due to diminished torque ripple re sulting in less loss of power lower vibration and longer life Elimination or reduction of memory lookup tables through real time poly nomial calculation thereby reducing system cost Use of advanced algorithms that can reduce the number of sensors required in a system J Control of power switching inverters along with control algorithm processing L Single processor control of multimotor systems Control Based Applications The 240xA DSP controllers are designed to meet the needs of control based a
415. of programmable registers on communication format the 240xA receiver signals in communication system control and status register 1 modes SCSR1 2 3 RX signals in communication modes low power modes figure system control and status register 2 transmitter signals in communication f SCSR2 2 5 modes timer control register TxCON TX signals in communication modes b 1 23 or 4 635 figure transmission control register TCR 10 20 transmit data buffer register SCITX WD counter register WDCNTR WD reset key register WDKEY WD timer control register WDCR XINT1 control register XINT1CR XINT2 control register XINT2CR 31 multiprocessor and asynchronous communication modes multiprocessor on modes 53 address byte 8 9 block start signal sending a block start signal controlling the SCI TX and RX features remote frames idle line mode steps remote requests idle line multiprocessor communication receiving tonnat sending idle line multiprocessor mode reset receipt sequence wake up from low power modes receiver operation RFPn remote frame pending register for recognizing the address byte mailbox n Sleep bit RMLn receive message lost for mailbox n wake up temporary WUT double buffered RMPn receive message pending for WUT and TXSHF mailbox n wake up temporary WUT flag ROM factory masked on chip ROM ae sermon f port interrupts 8 18 i mire data vane programmable data format RX signals in comm
416. of the PWM output is the opposite of that of the output of the associated asymmetric symmetric waveform generator when the PWM output is specified active low The PWM output is set to one or zero immediately after the corresponding bits in GPTCONA B are set and the bit pattern specifies that the state of PWM output is forced high or low In summary during a normal counting mode transitions on the GP timer PWM outputs happen according to Table 6 11 for the continuous up counting mode and according to Table 6 12 for the continuous up down counting mode assuming compare is enabled Setting active means setting high for active high and setting low for active low Setting inactive means the opposite The asymmetric symmetric waveform generation based on the timer counting mode and the output logic is also applicable to the compare units General Purpose GP Timers Table 6 11 GP Timer Compare Output in Continuous Up Counting Modes Time in a period State of Compare Output Before compare match Inactive On compare match Set active On period match Set inactive Table 6 12 GP Timer Compare Output in Continuous Up Down Counting Modes Time in a period State of Compare Output Before 1st compare match Inactive On 1st compare match Set active On 2nd compare match Set inactive After 2nd compare match Inactive All GP timer PWM outputs are put in the high impedance state when any of the following events occurs GPTCONA B
417. of the two sequences needed to assert an interrupt 7 28 Bit 9 Bit 8 Bit 7 Bit 6 Register Bit Descriptions INT FLAG SEQ1 ADC interrupt flag bit for SEQ1 This bit indicates whether an interrupt event has occurred or not This bit must be cleared by the user writing a 1 to it 0 No interrupt event 1 An interrupt event has occurred EVA SOC SEQ1 Event Manager A SOC mask bit for SEQ1 0 SEQ cannot be started by EVA trigger 1 Allows SEQ1 SEQ to be started by Event Manager A trigger The Event Manager can be programmed to start a conversion on vari ous events See chapter 6 Event Manager EV for details EXT SOC SEQ1 External signal start of conversion bit for SEQ1 0 No action 1 Setting this bit enables an ADC autoconversion sequence to be started by a signal from the ADCSOC device pin RST SEQ2 Reset SEQ2 0 No action 1 Immediately resets SEQ to an initial pretriggered state i e waiting for a trigger at CONVO8 A currently active conversion se quence will be aborted Analog to Digital Converter ADC 7 29 Register Bit Descriptions Bit 5 SOC SEQ2 Start of conversion trigger for Sequencer 2 SEQ2 Only applicable in dual sequencer mode ignored in cascaded mode This bit can be set by the following triggers O S W Software writing of 1 to this bit O EVB Event Manager B When a trigger occurs there are three possibilities Case 1 SEQ idle and SOC bit clear SEQ starts immedia
418. ogrammable Register Address Summary Table B 1 starting on page B 2 shows the peripheral register map for 240xA devices The shaded table entries represent the registers that are in addition to the 24x registers These additions are also explained in the data sheet titled TMS320LF2407A TMS320LF2406A TMS320LF2403A TMS320LF2402A TMS320LC2406A TMS320LC2404A TMS320LC2402A DSP Controllers literature number SPRS145 and TMS320LF2401A DSP Controller literature number SPRS161 Note that The ADC registers are completely different from those in the 24x J The ADC register map has been moved from 7030h to 70A0h The second event manager EVB has been placed at 7500h Table B 2 on page B 9 shows the code security module CSM registers B 1 Summary of Programmable Registers on the 240xA Table B 1 Summary of Programmable Registers on the 240xA Data Memory Register Address Mnemonic Register Name Data Page Page Interrupt and System 7010h PIRQRO Peripheral Interrupt Request Register 0 EOh 224 2 31 7011h PIRQR1 Peripheral Interrupt Request Register 1 EOh 224 2 32 7012h PIRQR2 Peripheral Interrupt Request Register 2 EOh 224 2 33 7014h PIACKRO Peripheral Interrupt Acknowledge EOh 224 2 34 Register 0 7015h PIACKR1 Peripheral Interrupt Acknowledge EOh 224 2 35 Register 1 7016h PIACKR2 Peripheral Interrupt Acknowledge EOh 224 2 36 Register 2 7018h SCSR1 System Control and Status Register 1 EOh 224 2 3 7019h SCSR2
419. on e er er ERR dt Ro a dod REPRE A B A Ba Block Diagram of the WD Module cece eee eee WD Counter Register WDCNTR Address 7023h WD Reset Key Register WDKEY Address 7025h WD Timer Control Register WDCR Address 7029h LF2407A Memory Map for Program Space 240xA Watchdog Clock Generation Logic e ennnen Functional Block Diagram for Boot EN XF Feature Functional Block Diagram of XMIF Signals on LF2407 Procedure for Generating Executable Files 0 0005 Example Hardware Configuration for LF240xA Boot ROM Operation Memory Maps for the LF240xA LF240x Devices in Microcontroller Mode SPI Data Packet Definition 0 0 cece cece eee Flowchart for the Serial Loader Baud Rate Match Algorithm Flowcharts for Serial Asynchronous Loader and the Fetch Header Routine Flowchart for FETCH SCI WORD 000 toe saa uia eee Password Match Flow PMP 00 eee eee eee I Figures Contents xxi Tables Qogogogogogornmrmrmnmmnmrmrnmmc C e Doo o gre 9 Iu ce m d qu qe m o x O I zi Cee act ehe m CO OONOG ROT gt xxii Hardware Features of 240xA Devices lt een Description of Low Power Modes 24 ranana 240xA Interrupt Source Priority and Vectors 1 eee ees Peripheral Interrupt Request Descriptions PI
420. on I O mux control register A MCRA 5 4 configuration table I O mux control register B MCRB configuration table O mux control register C MCRC 5 7 configuration table mux control registers MCRn 5 4 input output I O ports module digital I O ports register implementation on 240xA devices instruction register IR definition interrupt acknowledge definition hierarch latency nonmaskable operation sequence peripheral interrupt acknowledge descriptions PIACKRO PIACKR1 PIACKR2 peripheral interrupt request descriptions PIRQRO PIRQH1 PIRQR2 request structure requests figure vectors phantom software hierarchy interrupt flag register IFR 2 26 to 2 42 interrupt latency definition interrupt logic CAN controller area network 10 35 interrupt mask register IMR 2 28 to 2 42 interrupt priority and vectors 240xA interrupt source priority and vectors table System configuration and interrupts interrupt service routine ISR definition interrupts event manager EV 6 9 6 84 conditions for interrupt generation EV interrupt flag registers EV interrupt request and service EVA interrupt flag register A EVAIFRA EVA interrupt flag register B EVAIFRB EVA interrupt flag register C EVAIFRC EVA interrupt mask register A EVAIMRA EVA interrupt mask register A EVAIMRC EVA interrupt mask register B EVAIMRB EVA interrupts table EVB interrupt flag register A
421. on the dynamic shift count for the LACT ADDT and SUBT instructions or the dynamic bit position for the BITT instruction TOS Top of stack Top level of the 8 level last in first out hardware stack TREG See temporary register TREG TTL Transistor transistor logic vector See interrupt vector vector location See interrupt vector location wait state A CLKOUT cycle during which the CPU waits when reading from or writing to slower external memory wait state generator An on chip peripheral that generates a limited number of wait states for a given off chip memory space program data or I O Wait states are set in the wait state generator control register WSGR WE Write enable pin The 24x asserts WE to request a write to external pro gram data or I O space WSGR Wait state generator control register This register which is mapped to O memory controls the wait state generator XF bit XF pin status bit Bit 4 of status register ST1 that is used to read or change the logic level on the XF pin Glossary XF pin External flag pin A general purpose output pin whose status can be read or changed by way of the XF bit in status register ST1 XINT1 XINT2 External pins used to generate general purpose hardware interrupts zero fill A way to fill the unused low or high order bits in a register by insert ing Os Glossary F 15 A D converter starting with a timer event AAn abort acknowledge for mailbo
422. on interrupt occurs Emulation suspend occurs when the device clock is stopped by the emulator for example when the emulator encounters a break point GP Timer Interrupts There are sixteen interrupt flags in the EVAIFRA EVAIFRB EVBIFRA and EVBIFRB registers for the GP timers Each of the four GP timers can generate four interrupts upon the following events Overflow TxOFINT x 1 2 3 or 4 j Underflow TxUFINT x 1 2 3 or 4 J Compare match TxCINT x 1 2 3 or 4 Period match TxPINT x 1 2 3 or 4 A timer compare event match happens when the content of a GP timer counter is the same as that of the compare register The corresponding compare interrupt flag is set one clock cycle after the match if the compare operation is enabled Event Manager EV 6 21 General Purpose GP Timers An overflow event occurs when the value of the timer counter reaches FFFFh An underflow event occurs when the timer counter reaches 0000h Similarly a period event happens when the value of the timer counter is the same as that of the period register The overflow underflow and period interrupt flags of the timer are set one clock cycle after the occurrence of each individual event Note that the definition of overflow and underflow is different from their conventional definitions 6 3 1 GP Timer Counting Operation Stop Hold Mode Each GP timer has four possible modes of operation Stop Hold mode Contin
423. or Change config disable BCND W NCCE TC ELOOP B ELOOP Wait for Receive Interrupt GISR5 LOOP2 MAR ARO SETC XF CALL DELAY CLRC XF CALL DELAY B LOOP2 DELAY LAR ARO 0FFFFh LOOP RPT 080h NOP BANZ LOOP RET GISR1 RET GISR2 RET GISR3 RET GISR4 RET GISR6 RET PHANTOM RET end When data in MBX2 is transmitted in response to a Remote frame request XF is toggled Note that TRS bit is not set for MBX2 The transmission of MBX2 data is automatic in response to a Remote frame request C 26 Program Examples This program transmits a remote frame and expects a data frame in response Transmission of a remote frame by and reception of the data frame in MBX3 To be used along with REM ANS asm File name REM REQ asm i PROGRAM TO TRANSMIT A REMOTE FRAME REQUEST IN THE 24x 240xA CAN This program transmits a remote frame and expects a data frame in response Transmission of a remote frame by and reception of the data frame in MBX3 To be used along with REM ANS asm title REM REQ Title include 240x h Variable and register declaration include vector h Vector table takes care of dummy password global START Other constant definitions DP PFI set OEOh Page 1 of peripheral file 7000h 80h DP_CAN set 0E2h Can Registers 7100h DP CAN2 set 0E4h Can RAM 7200h MAC R O Definitions KICK DOG macro Watchdog reset macro LDP 00E0Oh SPLK 05555h WDKEY SPLK H
424. ort Acknowledge Interrupt Mask CAN_IMR 5 AAM Auto Answer Mode MSGIDnH 13 ABO Auto Bus On MCR 7 ACKE Acknowledge Error ESR 3 AME Acceptance Mask Enable MSGIDnH 14 BEF Bit Error Flag ESR 7 BO Bus Off Status ESR 2 BOIF Bus Off Interrupt Flag CAN IFR 2 BOIM Bus Off Interrupt Mask CAN IMR 2 BRP Baud Rate Prescaler BCR2 7 0 CCE Change Configuration Enable GSR 4 CCR Change Configuration Request MCR 12 CDR Change Data Field Request MCR 8 CRCE CRC Error ESR 5 DBO Data Byte Order MCR 10 DLC Data Length Code MSGCTRLn 3 0 EIL Error Interrupt Priority Level CAN IMR 7 EP Error Passive Status ESR 1 EBRIE Error Passive Interrupt Flag CAN_IFR 1 EPIM Error Passive Interrupt Mask CAN_IMR 1 EW Warning Status ESR 0 FER Form Error Flag ESR 8 IDE Identifier Extension MSGIDnH ilb IDH Upper Bits 28 16 of Extended Identifier MSGIDnH 12 0 IDL Lower Bits 15 0 of Extended Identifier MSGIDnH 15 0 LAMI Local Acceptance Mask Identifier LAM 15 MBNR Mailbox Number MCR 1 0 ME Mailbox Enable MDER 5 0 MD Mailbox Direction MDER 7 6 MIF Mailbox Interrupt Flag CAN IFR 13 8 MIL Mailbox Interrupt Priority Level CAN IMR 15 10 42 Table 10 5 CAN Notation Continued Notation MIM OPC PDA PDR REC ED RM RML RMLIF RMLIM RMP RTR SA1 SAM SBG SER SJW SMA STM SUSP TA TEC TM TRS TRR TSEG1 TSEG2 WDIF WDIM WLIF WLIM WUBA WUIF WUIM Signification Mailbox Interrupt Mask Overwrite Protection Control Power Down Mode Acknowledge Power Down Mode Requ
425. ory Space 00 eee eee eee CAN Data Frame Structure 0 0 tents Message Identifier for High Word Mailboxes 0 5 MSGIDnH Message Identifier for Low Word Mailboxes 0 5 MSGIDnL lt Message Control Field MSGCTRLn 0c cece eee eee eae Remote Frame Requests 00 0 cece cece eee ee nnne Local Acceptance Mask Register n 0 1 High Word LAMn H Addresses 710Bh 710DN s ee nee en a Local Acceptance Mask Register n 0 1 Low Word LAMn_L Addresses 710Ch 710Eh wu ccc cc cic ccs eee rh mh rh ya a hao rana Mailbox Direction Enable Register MDER Address 7100h Transmission Control Register TCR Address 7101h seus Receive Control Register RCR Address 7102h 00 ccc cece esses ub S ee ee TOO e OD Master Control Register MCR Address 7103h Bit Configuration Register 2 BCR2 Address 7104h Bit Configuration Register 1 BCR1 Address 7105h s CAN Bit TIMING iai rere or ier ct eon od st ad A nabo Error Status Register ESR Address 7106h 005 Global Status Register GSR Address 7107h uuu CAN Error Counter Register CEC Address 7108h CAN Interrupt Flag Register CAN IFR Address 7109h CAN Interrupt Mask Register CAN IMR Address 710Ah CAN initializati
426. ory addressing mode Table 3 1 shows the address map of data page 0 Table 3 1 Data Page 0 Address Map Address Name Description 0000h 0003h Reserved 0004h IMR Interrupt mask register 0005h Reserved 0006h IFR Interrupt flag register 0023h 0027h Reserved 002Bh 002Fh Reserved for test emulation 0060h 007Fh B2 Scratch pad RAM DARAM B2 Data Memory Configuration Two factors that contribute to the configuration of data memory are CNF bit The CNF bit bit 12 of status register ST1 determines whether the on chip DARAM BO is mapped to data space or program space B CNF 1 BO is used for program space B CNF 0 BO is used for data space At reset BO is mapped into data space CNF 0 3 6 1 Global Data Memory Note Global Data Memory is not available in the 240xA Hence the global memory allocation register GREG is a reserved location and should not be ac cessed Memory 3 11 VO Space 3 7 I O Space The l O space memory addresses up to 64K 16 bit words Figure 3 4 shows the I O space address map for the 2407A Figure 3 4 I O Space Address Map for 2407A 0000h External FEFF FF00 Reserved FFOE Flash control FFOR mode registert FF10 Reserved FFFE Wait state generator FFFF control register T Available only on Flash devices t Available only on LF2407A Note There is no I O space in ROM devices 3 12 3 8 XMIF Qualifier Signal Description XMIF
427. ounter Register CEC Address 7108h 15 8 R 0 7 0 R 0 Note R Read access value following dash value after reset After exceeding the error passive limit 128 REC is not increased any further When a message is received correctly the counter is set again to a value between 119 and 127 After reaching the bus off status TEC is undefined while REC is cleared and its function is changed It will be incremented after every 11 consecutive recessive bits on the bus These 11 bits correspond to the gap between two telegrams on the bus If the receive counter reaches 128 the module changes automatically back to the status bus on if the ABO bit in MCR is set Otherwise it changes when the recovery sequence of 11 x 128 bits has finished and the CCR bit in the MCR register is reset by the DSP All internal flags are reset and the error counters are cleared The configuration registers keep the programmed values After the power down mode the error counters stay unchanged They are cleared when entering the configuration mode 10 34 Interrupt Logic 10 6 Interrupt Logic There are two interrupt requests from the CAN peripheral to the peripheral interrupt expansion PIE controller the mailbox interrupt and the error interrupt Both interrupts can assert either a high priority request or a low priority request to the CPU The following events may initiate an interrupt Mailbox Interrupt m A message was transmitted or re
428. overview of the current TMS320 family describes the background and benefits of the 240xA DSP controller products and introduces the 240xA devices These low cost DSPs are intended to enable multiple applications for a nominal price Throughout this book all devices are referred to as 240xA devices This book is applicable for both the 240x and 240xA families of devices and will be applicable for future derivatives of the 240xA family Any feature that is not applicable for the 240x family is highlighted as appropriate This book should be used in conjunction with the TMS320F C24x DSP Controllers Reference Guide CPU and Instruction Set literature number SPRU160 and the appropriate device data sheet Device errata are updated as and when an exception to functional specification of the silicon is discovered Refer to the latest errata for exceptions to functional specifications and possible workarounds Topic Page A TMS320 Family Overview 5 9 2500 E EE PEE 1 2 1 2 TMS320C240xA Series of DSP Controllers 1 3 13 Peripheral Overviews 26 cen eee ce E ICE EREMO seas 1 5 14 New Features in 240xA Devices lt lt 44 444 44 1 6 15x240xA1Highlightsmsm rU 1 7 TMS320 Family Overview 1 1 TMS320 Family Overview The TMS320 family consists of fixed point floating point multiprocessor digital signal processors DSPs and fixed point DSP controllers TMS320 DSPs have an architecture de
429. pheral Interrupt Registers The peripheral interrupt registers include the following Peripheral interrupt vector register PIVR Peripheral interrupt request register 0 PIRQRO Peripheral interrupt request register 1 PIRQR1 Peripheral interrupt request register 2 PIRQR2 Peripheral interrupt acknowledge register 0 PIACKRO Peripheral interrupt acknowledge register 1 PIACKR1 Peripheral interrupt acknowledge register 2 PIACKR2 O O O O O L L DAETA Note PIRQRO 1 2 and PIACKRO 1 2 are control registers internal to the PIE module used for generating interrupts INT1 INT6 to the CPU While programming these registers can be ignored since they monitor the internal operation of the PIE These registers are used for test purposes and are not intended for user applications ice hyp aa 2 10 1 Peripheral Interrupt Vector Register PIVR The peripheral interrupt vector register PIVR is a 16 bit read only register It is located at address 701Eh in data space During the peripheral interrupt acknowledge cycle the PIVR is loaded with the interrupt vector of the highest priority pending interrupt associated with the CPU interrupt INTn being acknowledged or the phantom interrupt vector The PIVR is shown in Figure 2 10 Figure 2 10 Peripheral Interrupt Vector Register PIVR Address 701Eh 15 1 11 4 13 12 10 9 8 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Note R Re
430. pies the position as RTR would in a standard frame IDE Identifier Extension bit differentiates standard and extended frames Lj r0 r1 reserved DLC Data Length Code denotes the number of bytes 0 to 8 in a data frame A4 Data Four 16 bit words are used to store the maximum 8 byte data field of a CAN message CAN Controller Module 10 9 Message Objects J CRC contains a 16 bit checksum calculated on most parts of the mes sage This checksum is used for error detection ACK Data Acknowledge EOF End of Frame 10 3 1 Mailbox Layout 1 Mailbox RAM The mailbox RAM is the area where the CAN frames are stored before they are transmitted and after they are received Each mailbox has four 16 bit registers which can store a maximum of 8 bytes MBXnA MBXnB MBXnC and MBXnD Mailboxes that are not used for storing messages may be used as normal memory by the CPU 2 Message Identifiers Each one of the six mailboxes has its own message identifier stored in two 16 bit registers Figure 10 5 shows the message identifier high word and Figure 10 6 shows the message identifier low word Figure 10 5 Message Identifier for High Word Mailboxes 0 5 MSGIDnH 15 14 13 12 0 RW RW RW RW Note R Read access W Write access Bit 15 IDE Identifier Extension Bit 0 The received message has a standard identifier 11 bits The message to be sent has a standard identifier 11 bits 1 The received message has a
431. port available for the 240xA devices reduces development time and provides the same ease of use as traditional 8 and 16 bit microcontrollers The instruction set also allows you to retain your software investment when moving from other general purpose TMS320 fixed point DSPs It is source and object code compatible with the other members of the 24x generation source code compatible with the C2x generation and upwardly source code compatible with the C5x generation of DSPs from Texas Instruments The 240xA architecture is also well suited for processing control signals It uses a 16 bit word length along with 32 bit registers for storing intermediate results and has two hardware shifters available to scale numbers independently of the CPU This combination minimizes quantization and truncation errors and increases processing power for additional functions Such functions might include a notch filter that could cancel mechanical resonances in a system or an estimation technique that could eliminate state sensors in a system The 240xA DSP controllers take advantage of an existing set of peripheral functions that allow Texas Instruments to quickly configure various series members for different price performance points or for application optimization This library of both digital and mixed signal peripherals includes Event manager Controller Area Network CAN Serial communications ports SCI SPI Analog to digital converters ADC Safe
432. pplications By integrating the high performance of a DSP core and the on chip peripherals of a microcontroller into a single chip solution the 240xA series yields a device that is an affordable alternative to traditional microcontroller units MCUs and expensive multichip designs At 40 million instructions per second MIPS the 240xA DSP controllers offer significant performance over traditional 16 bit microcontrollers and microprocessors 240x devices operate at 30 MIPS Introduction 1 3 TMS320C240xA Series of DSP Controllers The 16 bit fixed point DSP core of the 240xA device provides analog designers a digital solution that does not sacrifice the precision and performance of their systems In fact system performance can be enhanced through the use of advanced control algorithms for techniques such as adaptive control Kalman filtering and state control The 240xA DSP controllers offer reliability and programmability Analog control systems on the other hand are hardwired solutions and can experience performance degradation due to aging component tolerance and drift Reduced Development Time The high speed central processing unit CPU allows the digital designer to process algorithms in real time rather than approximate results with look up tables The instruction set of these DSP controllers which incorporates both signal processing instructions and general purpose control functions coupled with the extensive development sup
433. program control logic Logic circuitry that decodes instructions manages the pipeline stores status of operations and decodes conditional operations program counter PC A register that indicates the location of the next instruction to be executed program read bus PRDB A 16 bit internal bus that carries instruction code and immediate operands as well as table information from program memory to the CPU PS Program select pin The 24x asserts PS to indicate an access to external program memory PSLWS Lower program space wait state bits A value in the wait state generator control register WSGR that determines the number of wait states applied to reads from and writes to off chip lower program space addresses 0000h 7FFFh See also PSUWS PSUWS Upper program space wait state bits A value in the wait state generator control register WSGR that determines the number of wait states applied to reads from and writes to off chip upper program space addresses 8000h FFFFh See also PSLWS RD Read select pin The 24x asserts RD to request a read from external pro gram data or I O space RD can be connected directly to the output en able pin of an external device READY External device ready pin Used to create wait states externally When this pin is driven low the 24x waits one CPU cycle and then tests READY again After READY is driven low the 24x does not continue pro cessing until READY is driven high repeat coun
434. provides a flexible method for controlling both dedicated I O and shared pin functions All I O and shared pin functions are controlled using nine 16 bit registers These registers are divided into two types I I O MUX Control registers MCRx Used to control the multiplexor selec tion that chooses between the primary function of a pin or the general purpose I O function Data and Direction Control registers PXDATDIR Used to control the data and data direction of bidirectional I O pins The GPIO pins are controlled through data memory mapped registers Note that there is no relationship between the GPIO pins and the I O space of the device Topic Page 5 1 Digital I O Ports Register Implementation on 240xA Devices 5 2 5 2 Differences in GPIO Implementation in the 240xA 5 4 5 3 VO MUX Control Registers oree a aane aecsdecne es nescence ners 5 4 5 4 Data and Direction Control Registers 4 5 8 5 1 Digital I O Ports Register Implementation on 240xA Devices 5 1 Digital I O Ports Register Implementation on 240xA Devices Table 5 1 lists the registers available to the digital I O module as implemented on the 240xA devices These registers are memory mapped to data space from 7090h through 709Fh All reserved bits are unimplemented reads return zero and writes have no effect Note that when multiplexed I O pins are configured for peripheral functions or as
435. quired speed and torque of the motor In this case the command voltage or current to be applied to the motor is the modulating signal The frequency of the modulating signal is typically much lower than the PWM carrier frequency PWM Signal Generation Dead Band To generate a PWM signal an appropriate timer is needed to repeat a counting period that is the same as the PWM period A compare register is used to hold the modulating values The value of the compare register is constantly compared with the value of the timer counter When the values match a transition from low to high or high to low happens on the associated output When a second match is made between the values or when the end of a timer period is reached another transition from high to low or low to high happens on the associated output In this way an output pulse is generated whose on or off duration is proportional to the value in the compare register This process is repeated for each timer period with different modulating values in the compare register As a result a PWM signal is generated at the associated output In many motion motor and power electronics applications two power devices an upper and a lower are placed in series on one power converter leg The turn on periods of the two devices must not overlap with each other in order to avoid a shoot through fault Thus a pair of non overlapping PWM outputs is often required to properly turn on and off th
436. r PWM PWM period 1 period 1 a Compare value greater than period Timer value PWM active high Dead band PWMy 1 active low Compare matches To generate an Asymmetric PWM signal GP timer 1 is put in the continuous up counting mode and its period register is loaded with a value corresponding to the desired PWM carrier period The COMCONXx is configured to enable the compare operation set the selected output pins to be PWM outputs and enable the outputs If dead band is enabled the value corresponding to the required dead band time should be written by software into the DBT 3 0 bits in DBTCONx 11 8 This is the period for the 4 bit dead band timers One dead band value is used for all PWM output channels By proper configuration of ACTRx with software a normal PWM signal can be generated on one output associated with a compare unit while the other is held low or off or high or on at the beginning middle or end of a PWM period Such software controlled flexibility of PWM outputs is particularly useful in switched reluctance motor control applications Event Manager EV 6 59 PWM Waveform Generation With Compare Units and PWM Circuits After GP timer 1 or GP timer 3 is started the compare registers are rewritten every PWM period with newly determined compare values to adjust the width the duty cycle of PWM outputs that control the switch on and off duration of the power de
437. r I O port D Data amp Direction register I O port E Data amp Direction register I O port F Data amp Direction register WD Counter register WD Key register WD Control register ADC Control register 1 ADC Control register 2 Maximum conversion channels register Channel select Sequencing control register 1 Channel select Sequencing control register 2 Channel select Sequencing control register 3 Program Examples C 5 Program Examples CHSELSEQ4 set 70A6h Channel select Sequencing control register 4 AUTO_SEQ SR Set 70A7h Auto sequence status register RESULT set 70A8h Conversion result register 0 RESULT1 set 70A9h Conversion result register 1 RESULT2 set 70Aah Conversion result register 2 RESULT3 set 70Abh Conversion result register 3 RESULT4 set 70Ach Conversion result register 4 RESULT5 set 70Adh Conversion result register 5 RESULT6 set 70Aeh Conversion result register 6 RESULT7 set 70Afh Conversion result register 7 RESULT8 set 70BOh Conversion result register 8 RESULT9 set 70B1h Conversion result register 9 RESULT10 set 70B2h Conversion result register 10 RESULT11 set 70B3h Conversion result register 11 RESULT12 set 70B4h Conversion result register 12 RESULT13 set 70B5h Conversion result register 13 RESULT14 set 70B6h Conversion result register 14 RESULT15 set 70B7h Conversion result register 15 CALIBRATION set 70B8h Calibratio
438. r Directional Up Down Counting Mode Prescale Factor 1 and TxPR 3 The directional up down counting mode of GP timer 2 4 can be used with the quadrature encoder pulse QEP circuits in the EV module The QEP circuits provide both the counting clock and direction for GP timer 2 4 in this case This mode of operation can also be used to time the occurrence of external events in motion motor control and power electronics applications Continuous Up Down Counting Mode This mode of operation is the same as the directional up down counting mode but the TDIRA B pin has no effect on the counting direction The counting direction only changes from up to down when the timer reaches the period value or FFFFh if the initial timer value is greater than the period The timer direction only changes from down to up when the timer reaches zero The period of the timer in this mode is 2 TxPR cycles of the scaled clock input except for the first period The duration of the first counting period is the same if the timer counter is zero when counting starts The initial value of the GP timer counter can be any value between Oh and FFFFh inclusive When the initial value is greater than that of the period register the timer counts up to FFFFh resets to zero and continues the Event Manager EV 6 25 General Purpose GP Timers operation as if the initial value was zero When the initial value in the timer counter is the same as that of the per
439. r EVA and COM CONB for EVB RW One 16 bit action control register ACTRA for EVA and ACTRB for EVB with an associated shadow register RW Six PWM 3 state output compare output pins PWMy y 1 2 3 4 5 6 for EVA and PWMZz z 7 8 9 10 11 12 for EVB J Control and interrupt logic The functional block diagram of a compare unit is shown in Figure 6 15 Figure 6 15 Compare Unit Block Diagram For EVA x 1 2 3 y 1 3 5 z 1 For EVB x 4 5 6 y 7 9 11 z 3 TZCNT GPTz counter ACTR Compare full compare logic action control register shadowed Output logic Event Manager EV 6 39 CMPRx full compare register shad PWM circuits owed Compare Units The time base for the compare units and the associated PWM circuits is provided by GP timer 1 for EVA or GP timer 3 for EVB which can be in any of its counting modes when the compare operation is enabled Transitions occur on the compare outputs Compare Inputs Outputs The inputs to a compare unit include J Control signals from control registers GP timer 1 3 TI CNT T3CNT and its underflow and period match signals 1 RESET The output of a compare unit is a compare match signal If the compare operation is enabled this match signal sets the interrupt flag and causes transitions on the two output pins associated with the compare unit Compare Operation Modes Operation 6 40 The operatio
440. r as a result of initialization changes clear the SPI SW RESET bit SPICCR 7 before making initialization changes and then set this bit after initialization is complete p BB B m iili rl Note Do not change SPI configuration when communication is in progress k 9 4 6 Data Transfer Example 9 16 The timing diagram shown in Figure 9 5 illustrates an SPI data transfer between two devices using a character length of five bits with the SPICLK being symmetrical The timing diagram with SPICLK unsymmetrical Figure 9 4 shares similar characterizations with Figure 9 5 except that the data transfer is one CLKOUT cycle longer per bit during the low pulse CLOCK POLARITY 0 or during the high pulse CLOCK POLARITY 1 of the SPICLK Figure 9 5 Five Bits per Character is applicable for 8 bit SPI only and is not for 24x devices that are capable of working with 16 bit data The figure is shown for illustrative purposes only SPI Interrupts Figure 9 5 Five Bits per Character C T0OmTmoourn A Master SPI 1l Fr Int flag Slave SPI Int flag sd ABC DEFG H l J K SPISOMI from slave zx A ee ed 7 6 5 4 3 7 6 5 4 3 SPISIMO TTL 1r from master SPICLK signal options 7 3 7 CLOCK POLARITY 0 JUULU UL F CLOCK PHASE 0 groeps I LE LILILI L TUUU CLOCK PHASE 1 ee LLL Le CLOCK PHASE 0 CLOCK POLARITY 1 LRL U UUU U CLOCK PHASE 1 SPISTE EE Slave writes
441. r full duplex operation Double buffered receive and transmit functions A transmitter and a receiver that can be operated by interrupts or by polling status flags B Transmitter TXRDY flag indicates when the transmitter buffer regis ter is ready to receive another character from the CPU core and TX EMPTY flag indicates when the transmit shift register is empty B Receiver RXRDY flag indicates when the receiver buffer register is ready to receive another character from the external world BRKDT flag indicates when a break condition occurs and RX ERROR mon itors four interrupt conditions Separate enable bits for transmitter and receiver interrupts Separate error interrupts for multiple error conditions NRZ non return to zero format Serial Communications Interface SCI 8 3 C240 SCI vs LF LC240xA SCI Figure 8 1 SCI Block Diagram Frame format and mode SCICTL1 3 Parity Even odd Enable SCIHBAUD 7 0 Baud rate MSbyte register SCILBAUD 7 0 Baud rate LSbyte register RXSHF register RXWAKE o RXERRINTENA d EE oO Receiver data buffer register SCITXBUF 7 0 Transmitter data buffer register TXSHF register SCI TX interrupt TXRDY TXINTENA Scicuz7 o 0 TXINT TXEMPTY External connections O SCI priority level Low INT priority 1o High INT priority 20 SCITX priority Low INT priority to High INT priority 20 SCIRX pr
442. r reset Bit 15 Reserved Bits 14 8 FnDIR 0 Configure corresponding pin as an input 1 Configure corresponding pin as an output Bit 7 Reserved Digital Input Output I O 5 13 Data and Direction Control Registers Bits 6 0 IOPFn If FnDIR O then 0 Corresponding I O pin is read as a low 1 Corresponding I O pin is read as a high If FnDIR 1 then 0 Set corresponding I O pin low 1 Set corresponding I O pin high Table 5 10 PFDATDIR VO Pin Designation Assuming Pins Have Been Selected as I O i e Secondary Function I O Port Data Bit Pin Name IOPFO CAP5 QEP4 IOPFOT IOPF1 CAP6 IOPF1t IOPF2 T3PWM T3CMP IOPF2t IOPF3 T4PWM T4CMP IOPF3t IOPF4 TDIR2 IOPFAT IOPF5 TCLKIN2 IOPF5t IOPF6 IOPF6t Reserved Reserved These pins are not available on 2402A devices Chapter 6 Event Manager EV This chapter describes the 240xA Event Manager EV module Most of the EV pins are shared with general purpose digital I O signals This pin sharing and how it is controlled is described in Chapter 5 Digital Input Output I O The EV module provides a broad range of functions and features that are particularly useful in motion control and motor control applications There are differences in terms of the functionality between the EV module of 240xA devices and the EV module of 240 devices However the EV modules in the 24x and 240xA families of DSPs are exactly identical in terms of functionality Note that all devices of the 240
443. ram memory configuration program and data spaces program memory map for LF2407A i25 segments 3 total address range Index 12 wait state generation setting the number of wait states with the 2407A WSGR bits with the 2407A wait state generator with the READY signal XMIF qualifier signal description data address data visibility functional timing program address data visibility functional timing signal description table memory map CAN controller area network CAN module memory space TMS320x240xA LF2407A memory map for program space message buffers message identifiers message objects CAN controller area network acceptance filter 10 16 local acceptance mask LAM 10 16 handling of remote frames 10 14 mailbox layout message buffers 10 12 receive mailbox 10 13 transmit mailbox 10 13 write access to mailbox RAM 10 12 MSGCTRLn CAN message control field 10 11 MSGIDnH message identifier for high word mailboxes 0 5 MSGIDnL message identifier for low word mailboxes 0 5 multiprocessor communication SCI serial communications interface address byte controlling the SCI TX and RX Features receipt sequence recognizing the address byte 59 sleep bit new features 240xA devices 16 hardware features of the 240xA devices next program address register NPAR definition nonmaskable interrupt NMI 17 notation CAN controller area network 10 42 NPAR n
444. rd capture 6 79 79 capture unit registers capture units 6 68 block nis ees EVA 6 69 block diagram EVB features operation capture unit setup time base selection quadrature encoder pulse QEP circuit decoding decoding erample 6 82 QEP circuit 6 81 QEP circuit block diagram for EVA QEP circuit block diagram for EVB QEP counting operation with GP timer interrupt and associated compare outputs QEP pins register setio for the QEP circuit 6 82 Index space vector PWM 3 phase power inverter approximation of motor voltage with space vectors basic space vectors and switching patterns power inverter switching patterns and basic space vectors schematic diagram table of switching patterns waveform boundary conditions 6 66 waveform generation with event manager software space vector PWM hardware space vector PWM waveforms 6 66 the unused compare register 6 66 symmetric PWM waveform generation with compare unit and PWM circuits figure symmetric space vector PWM waveforms figure with compare units and PWM circuits asymmetric and symmetric PWM generation asymmetric PWM waveform generation dead band PWM output generation with event manager PWM signal generation register setup for PWM generation symmetric PWM waveform generation 6 60 QEP circuit 6 80 6 81 block diagram QEP counting QEP decoding example QEP pins register setup time base QEP
445. re development tools The following documents cover these tools in detail TMSS320C 1x C2x C2xx C5x Assembly Language Tools User s Guide literature number SPRUO18 TMS320C2x C2xx C5x Optimizing C Compiler User s Guide literature number SPRUO24 TMS320C2xx C Source Debugger User s Guide literature number SPRU151 For further information about ordering these documents see Helated Documentation From Texas Instruments on page v of the Preface Topic Page C 1 About These Program Examples C 2 C 2ProgramlExamples 7 anne ee etetcleteyatofay yey C 4 C 1 About These Program Examples C 1 About These Program Examples Figure C 1 illustrates the basic process for generating executable COFF files 1 Use any ASCII editor to create An assembly language program test asm in the figure Lj A linker command file 240xA cmd in the figure that defines address ranges according to the architecture of the particular device and where the various sections of the user code should be located 2 Assemble the program The command shown under Step 2 in the figure generates an object file obj and list file Ist containing a listing of as sembler messages 3 Use the linker to bring together the information in the object file and the command file and create an executable file test out in the figure The command shown also generates a map file which explains how the linker assigned the individual se
446. re Units Capture Unit Setup For a capture unit to function properly the following register setup must be performed 1 Initialize the CAPFIFOx and clear the appropriate status bits 2 Setthe selected GP timer in one of its operating modes 3 Setthe associated GP timer compare register or GP timer period register if necessary 4 Setup CAPCONA or CAPCONB as appropriate 6 8 3 Capture Unit Registers The operation of the capture units is controlled by four 16 bit control registers CAPCONA B and CAPFIFOA B TxCON x 1 2 3 or 4 registers are also used to control the operation of the capture units since the time base for capture circuits can be provided by any of these timers Table 6 7 and Table 6 8 on page 6 12 show the addresses of these registers Capture Control Register A CAPCONA Figure 6 32 Capture Control Register A d Adaress 7420h 15 14 13 11 W 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 gi 1 0 RW 0 RW 0 RW 0 R 0 Note R Read access W Write access 0 value after reset Bit 15 CAPRES Capture reset Always reads zero Writing O clears the capture registers 0 Clear all registers of capture units to 0 1 No action Bits 14 13 CAP12EN Capture Units 1 and 2 control 00 Disables Capture Units 1 and 2 FIFO stacks retain their contents 01 Enables Capture Units 1 and 2 10 Reserved 11 Reserved Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bits 7 6 Bits 5 4 Capture Units CAP3EN Capture Unit 3 control
447. re a device Code examples are also listed for clarity E 3 1 Password Match Flow Password match flow PMF is essentially a sequence of four dummy reads from password locations PWL followed by four writes to KEY registers Figure E 1 explains how PMF helps to initialize the security logic registers and disable security logic See the flowchart boxes for the actual instructions that accomplish the PMF Flash ROM Code Security For LF LC240xA DSP Devices E 7 Environments that Require Security Unlocking Figure E 1 Password Match Flow PMF Flash ROM Device secure after reset or runtime KEY Undefined Do dummy Read of PWL 0040 0043h M Yes Is PWL Example code for dummy read LDP BLPD BLPD BLPD BLPD 0 40h 60h update high word 41h 60h third word 42h 60h second word 43h 60h low word 240xA instructions Example to update KEY register Assume xpwd has password all 0 s or F s LDP 0EFh page EFh SPLK hpwd 77FOh highword amp SPLK tpwd 77Fih third word x seuk spwd 77F2h second word m SPLK Hipwd 77F3h low word Write the Password J to KEY registers Correct Password Device unsecure CPU can access on chip Flash ROM Unsecuring Considerations for Devices With Without Code Security E 4 Unsecuring Considerations for Devices With Without Code Security Case 1 and Case 2 provide unsecuring consid
448. rection Enable Register Transmission Control Register Receive Control Register Master Control Register Bit Configuration Register 2 Bit Configuration Register 1 Error Status Register Global Status Register Transmit and Receive Error Counters Data Page E1h 225 Eth 225 Page 7 35 7 35 7 33 10 19 10 20 10 22 10 23 10 26 10 27 10 30 10 32 10 34 Summary of Programmable Registers on the 240xA Table B 1 Summary of Programmable Registers on the 240xA Continued Data Memory Address 7109h 710Ah 710Bh 710Ch 710Dh 710Eh 7200h 7201h 7202h 7204h 7205h 7206h 7207h 7208h 7209h 720Ah 720Ch 720Dh 720Eh 720Fh 7210h 7211h 7212h 7214h 7215h Register Mnemonic CAN IFR CAN IMR LAMO_H LAMO_L LAM1_H LAM1_L MSGIDOL MSGIDOH MSGCTRLO MBOX0A MBOXOB MBOX0C MBOXOD MSGID1L MSGID1H MSGCTRL1 MBOX1A MBOX1B MBOX1C MBOX1D MSGID2L MSGID2H MSGCTRL2 MBOX2A MBOX2B Register Name Interrupt Flag Register Interrupt Mask Register Local Acceptance Mask MBOX 0 and MBOX 1 Local Acceptance Mask MBOX 0 and MBOX 1 Local Acceptance Mask MBOX 2 and MBOX 3 Local Acceptance Mask MBOX 2 and MBOX 3 CAN Message ID for Mailbox 0 lower 16 bits CAN Message ID for Mailbox 0 upper 16 bits MBOX 0 RTR and DLC CAN 2 of 8 bytes of Mailbox 0 CAN 2 of 8 bytes of Mailbox 0 CAN 2 of 8 bytes of Mailbox 0 CAN 2 of 8 bytes of Mailbox 0 CAN Messag
449. red the moment the on chip boot loader is invoked DOs and DON Ts to Protect Security Logic LF2407A is the only device that has external memory interface XMIF This device can execute code in microprocessor mode using external memory If the device powers up in microprocessor mode MP MC pin 1 the on chip flash memory will be disabled and the flash access will remain secure If on chip flash access is desired it can be done only if the password is known The CPU has to initiate a PMF and flash access will be granted if the password is valid However if the device powers up in micro controller mode MP MC pin 0 and branches to an external memory address the flash memory cannot be protected A hacker could potentialy have code in the external memory that could read the flash ROM contents Similarly code running in flash should not transfer control to on chip boot ROM A hacker could potentially transfer a piece of code that could read the flash contents Flash ROM Code Security For LF LC240xA DSP Devices E 11 CSM Features Summary E 6 CSM Features Summary E 12 1 The flash is unsecured after a reset if the following conditions are met m The JTAG connector is not connected Bi The device is powered up in microcomputer mode MP MC pin is low B The on chip boot ROM is not invoked Violating any one of the three conditions mentioned above would immedi ately secure the device The standard way of running
450. ree compare units described in section 6 4 on page 6 39 Pulse width modulation PWM circuits that include space vector PWM circuits dead band generation units and output logic described in sec tion 6 5 on page 6 48 section 6 6 on page 6 57 and section 6 7 on page 6 62 respectively Three capture units described in section 6 8 on page 6 68 Quadrature encoder pulse QEP circuit described in section 6 9 on page 6 80 Interrupt logic described in section 6 10 on page 6 84 Figure 6 1 shows a block diagram of the EVA module and Figure 6 2 shows a block diagram of the EVB module Figure 6 1 Event Manager A EVA Block Diagram 240xA DSP core ADDR bus Reset INT1 2 3 4 Clock EV control registers Data bus k o 16 16 Event Manager EV Functional Blocks and control logic Output logic 16 GP timer 1 CE GP timer 1 3 SVPWM m Full compare state units oum Prescaler T1CON 45 T1CON 8 9 10 3 Output logic 16 GP timer 2 Output compare logic 4 GP timer 2 4 4 4 T2CON 4 5 Prescaler T2CON 8 9 10 is QEP circuit 2 Event Manager EV ADC start of conversion T1CMP T1PWM TDIRA TCLKINA CLKOUT PWM1 PWM6 T2CMP T2PWM TCLKINA CLKOUT TDIRA CAPCONA 14 13 2 CAP1 QEP1 CAP2 QEP2 CAP3 6 3 Event Manager EV Functional Blocks Figure 6 2 Event Manager B EVB Block Diagram 240xA DSP core
451. ridge enable Together with the HI LO bit BRG ENA allows a reference voltage to be converted in calibration mode See the description of the HI LO bit for reference voltage selections during calibration 0 Full reference voltage is applied to the ADC input 1 A reference midpoint voltage is applied to the ADC input HI LO VREFH VREFLO selection When the fail self test mode is enabled STEST ENA 1 HI LO defines the test voltage to be connected In calibration mode HI LO defines the reference Source polarity see Table 7 5 In normal operating mode HI LO has no effect 0 VnErLo is used as precharge value at ADC input 1 VREFHI is used as precharge value at ADC input Table 7 5 Reference Voltage Bit Selection BRG ENA 0 0 1 1 Bit 0 CAL ENA 1 STEST ENA 1 HI LO Reference voltage V Reference voltage V 0 VREFLO VREFLO 1 VREFHI VREFHI 0 KVREFHI VREFLO 2 VREFLO 1 VREFLO VREFHI 2l VREFHI STEST ENA Self test function enable 0 Self test mode disabled 1 Self test mode enabled Analog to Digital Converter ADC 7 25 Register Bit Descriptions 7 5 2 ADC Control Register 2 ADCTRL2 Figure 7 10 ADC Control Register 2 ADCTRL2 Adaress 70A1h 15 14 13 12 11 10 9 8 INT ENA INT ENA See GAL SOCSEQI SEQIBSY SEQr SEQ1 e QM Mode 1 Mode 0 RW 0 RS 0 RW 0 R 0 RC 0 7 6 5 4 1 INT ENA INT ENA oro RSTSEQ2 SOCSEQ2 SEO2BSY SEQ SEQ2 urge Mode 1 Mode 0 RW 0 RS 0 RW 0 R 0 RW 0
452. ripheral Interrupt Expansion PIE Controller 2 4 Peripheral Interrupt Expansion PIE Controller The 240xA CPU supports one nonmaskable interrupt NMI and six maskable prioritized interrupt requests INT1 INT6 at the core level The 240xA devices have many peripherals and each peripheral is capable of generating one or more interrupts in response to many events at the peripheral level Because the C240xA CPU does not have sufficient capacity to handle all peripheral interrupt requests at the core level a centralized interrupt controller PIE is required to arbitrate the interrupt requests from various sources such as peripherals and other external pins see Figure 2 5 System Configuration and Interrupts 2 13 Peripheral Interrupt Expansion PIE Controller Figure 2 5 Peripheral Interrupt Expansion Block Diagram 2 14 PIRQRO PIROR1 PDPINTA PDPINTB 73 ADCINT 77 XINT1 77 XINT2 77 SPIINT 1 RXINT 1 TXINT CANMBINT 1 CANERINT 1 CMP1INT 1 CMP2INT 1 CMPSINT 1 T1PINT T1CINT T1UFINT T1OFINT CMPAINT 1 CMPS5INT 1 CMP6INT 1 T3PINT 3 T3CINT J T3UFINT T3OFINT T2PINT 77 T2CINT 77 T2UFINT 73 T2OFINT 777 T4PINT 77 T4CINT 773 T4UFINT T4OFINT 777 CAP1INT 1 CAP2INT 1 CAP3INT 1 CAPAINT 1 CAPSINT 1 GAP6INT 1 SPIINT RXINT 1 TXINT CANMBINT 1 CANERINT 1 ADCINT XINT1 XINT2
453. rnal memory interface XMIF signals O0 XMIF signals in normal driven mode i e not Hi Z high impedance 1 All XMIF signal are forced to Hi Z state p M M71 Note This bit is a reserved bit on all devices other than LF2407 2407A and must be written only as a zero mmm mmm mmm Boot Enable This bit reflects the state of the BOOT EN XF pin at the time of reset After reset and device has Booted up this bit can be changed in software to re enable Flash memory visibility or return to active Boot ROM 0 Enable Boot ROM Address space 0000 OOFF is now occu pied by the on chip Boot ROM Block Flash memory is totally dis abled in this mode Note There is no on chip boot ROM in ROM devices i e LC240xA 1 Disable Boot ROM Program address space 0000 7FFF is mapped to on chip Flash Memory in the case of LF2407A and LF2406A In the case of LF2402A addresses 0000 1FFF are mapped Bit 2 Bits 1 0 Configuration Registers Microprocessor Microcontroller Select This bit reflects the state of the MP MC pin at time of reset After reset this bit can be changed in software to allow dynamic mapping of memory on and off chip 0 Set to Microcontroller mode Program Address range 0000 7FFF is mapped internally i e Flash Set to Microprocessor mode Program Address range 0000 7FFF is mapped externally i e Customer provides external
454. ro bits as shown in Figure 8 6 If any bit is not zero then the processor starts over and begins looking for another start bit For the bits following the start bit the processor determines the bit value by making three samples in the middle of the bits These samples occur on the fourth fifth and sixth SCICLK periods and bit value determination is on a majority two out of three basis Figure 8 6 illustrates the asynchronous communication format for this with a start bit showing how edges are found and where a majority vote is taken Since the receiver synchronizes itself to frames the external transmitting and receiving devices do not have to use a synchronized serial clock The clock can be generated locally Figure 8 6 SCI Asynchronous Communications Format Falling edge Majority SCICLK internal detected vote 12 34 5 6 7 8 12 3 4 5 6 7 8 1 Start bit LSB of data 6M 8 SCICLK periods per data bit 8 SCICLK periods per data bit Serial Communications Interface SCI 8 15 SCI Communication Format 8 4 1 Receiver Signals in Communication Modes Figure 8 7 illustrates an example of receiver signal timing that assumes the following conditions Address bit wake up mode address bit does not appear in idle line mode Six bits per character Figure 8 7 SCI RX Signals in Communication Modes RXENA l Frame Notes 1 Flag bit RXENA SCICTL1 0 goes high to enable the receiver 2 Data a
455. rrives on the SCIRXD pin start bit detected 3 Data is shifted from RXSHF to the receiver buffer register SCIRXBUF an interrupt is requested Flag bit RXRDY SCIRXST 6 goes high to signal that a new character has been received 4 The program reads SCIRXBUF flag RXRDY is automatically cleared 5 The next byte of data arrives on the SCIRXD pin the start bit is detected then cleared 6 Bit RXENA is brought low to disable the receiver Data continues to be assembled in RXSHF but is not transferred to the receiver buffer register 8 16 SCI Communication Format 8 4 2 Transmitter Signals in Communication Modes Figure 8 8 illustrates an example of transmitter signal timing that assumes the following conditions _j Address bit wake up mode address bit does not appear in idle line mode Three bits per character Figure 8 8 SCI TX Signals in Communications Mode TXENA l 1 6 TXRDY l l 23 4 5 TX EMPTY l First Character Second Character 7 SCITXD pin start 0 1 2 Aa Pal stop stat of 1 2 Ad Pal stop D p Frame Frame Notes 1 Bit TXENA SCICTL1 1 goes high enabling the transmitter to send data 2 SCITXBUF is written to thus 1 the transmitter is no longer empty and 2 TXRDY goes low 3 The SCI transfers data to the shift register TXSHF The transmitter is ready for a second character TXRDY goes high and it requests an interrupt to enable an interrupt bit TX INT ENA SCICTL2
456. s 0 0 eens 11 3 1 WD Counter Register tee eens 11 3 2 WD Reset Key Register 0 cee es 11 3 3 WD Timer Control Register 12 240xA 240 Family Compatibility 0 0 0 c cee Describes compatibility issues between the 240xA and the 240 family of processors 12 4 General 5 22 seLIi addi O tad O tide ee O en deed 12 2 12 2 Event Manager xus cin deciadeuadhtuaehens pra RARO RAN ER aaa geet RR UNE Ru 12 3 12 3 Analog to Digital Converter etn e 12 4 12 4 Serial Communications Interface 44400 ees 12 5 Serial Peripheral Interface ccc ccc ccc aa 12 4 12 6 Watchdog TimMer sc ro reda dete debile doo dok edax ba ep 208 Vn LENSES CQ 12 4 13 240xA 24x Family Compatibility 52252 0 lei eod qucm FU MA du bn x dua ipu 13 1 Describes the major differences between the 24x and the 240xA family of processors 13 1 nttoductliOn s 0 250c 0000000 sone O O Y 13 1 1 Migrating Code from 24x to 240x 240xA Devices nrnna 13 2 24x 240xA DSP Overview sssessseese s 15 3 Memory Map sardori rarer agin EE dea RR Rectum Renate odd IR EE TAEA 13 3 1 Program Space sess Locas ead ente Pe a a dod eU tp aura QUARC d a hoang 19 4 System FeatuneS x ld ced tones okr dk odd ga dais Dod e ered 19 41 Osocillator and PLE relicto ae aa ace elles ot tectae 6 19 42 Watchdog Clock ocius re bbb S bod k n 800 G ka RP E B A TRES 13 4 3 System Control Registers neuan
457. s Bits 8 to 3 are error bits that can be read and cleared by writing a 1 to them Bits 2 to 0 are status bits that cannot be cleared only read Figure 10 18 Error Status Register ESR Address 7106h 15 9 8 RC 0 we Tw T ETE TER Om To T RC 0 RC 1 RC 0 RC 0 RC 0 Note R Read access C Clear value following dash value after reset Bits 15 9 Reserved Bit 8 FER Form Error Flag 0 The CAN module was able to send and receive correctly 1 A Form Error occurred on the bus This means that one or more of the fixed form bit fields had the wrong level on the bus Bit 7 BEF Bit Error Flag 0 The CAN module was able to send and receive correctly 1 The received bit does not match the transmitted bit outside of the arbitration field or during transmission of the arbitration field a dominant bit was sent but a recessive bit was received 10 30 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Status Registers SA1 Stuck at Dominant Error 0 The CAN module detected a recessive bit 1 The CAN module did not detect a recessive bit The SA1 bit is always 1 after a hardware or a software reset or a bus off condition CRCE CRC Error 0 The CAN module did not receive a wrong CRC 1 The CAN module received a wrong CRC SER Stuff Error 0 No stuff bit error occurred 1 The stuff bit rule was violated ACKE Acknowledge Error 0 The CAN module received an acknowledge 1 The CAN module did not receive an acknowledge
458. s the 16 pins are used in par allel to address external data memory program memory or I O space ACC See accumulator ACCH Accumulator high word The upper 16 bits of the accumulator See also accumulator ACCL Accumulator low word The lower 16 bits of the accumulator See also accumulator accumulator A 32 bit register that stores the results of operations in the central arithmetic logic unit CALU and provides an input for subsequent CALU operations The accumulator also performs shift and rotate opera tions address The location of program code or data stored in memory addressing mode A method by which an instruction interprets its operands to acquire the data it needs See also direct addressing immediate addressing indirect addressing analog to digital A D converter A circuit that translates an analog signal to a digital signal AR See auxiliary register ARO ART Auxiliary registers 0 through 7 See auxiliary register ARAU See auxiliary register arithmetic unit ARAU ARB See auxiliary register pointer buffer ARB ARP See auxiliary register pointer ARP auxiliary register One of eight 16 bit registers AR7 ARO used as point ers to addresses in data space The registers are operated on by the aux iliary register arithmetic unit ARAU and are selected by the auxiliary register pointer ARP F 1 Glossary auxiliary register arithmetic unit ARAU A 16 bit arithmetic unit used to i
459. s character A step by step description of the sequence follows 1 The SPI is initialized 2 The XF pin is now used as a chip select for the EEPROM 3 The SPI outputs a read command for the EEPROM 03h 4 The SPI sends the EEPROM an address 0000h that is the host requires that the EEPROM must have the downloadable packet beginning at ad dress 0000h in the EEPROM 5 From this point onward the next two bytes fetched constitute the destina tion address The most significant byte of this word is the byte read first and the least significant byte is the next byte fetched This is true of all word transfers on the SPI 6 The next word two bytes fetched is the length N 7 The destination is checked to see if it is in the range FEOOh to FFFFh If necessary the DARAM block BO is configured in program memory space 8 From now on N words are fetched and stored in program memory at the address pointed to by destination The EEPROM is read off in one continu ous burst 9 Finally once the last word is stored a simple branch is made into the code at the destination address therefore the entry point for the boot loaded code must be at the destination address Protocol Definitions Figure D 3 SPI Data Packet Definition ByteO Byte1 Destination Byte2 Byte3 Length n Byte4 Byte5 Opcode 0 Byte6 Byte7 Opcode 1 Opcode n 1 D 2 2 SCI Asynchronous Transfer Protocol and Data Formats The SCl bas
460. s not allowed to WUIF Wake Up Interrupt Flag 0 The module is still in the sleep mode or in normal operation 1 The module has left the sleep mode BOIF Bus Off Interrupt Flag 0 The CAN module is still in the bus on mode 1 The CAN has entered the bus off mode EPIF Error Passive Interrupt Flag 0 The CAN module is not in the error passive mode 1 The CAN module has entered the error passive mode WLIF Warning Level Interrupt Flag 0 None of the error counters has reached the warning level 1 At least one of the error counters has reached the warning level CAN Controller Module 10 37 Interrupt Logic 10 6 2 CAN Interrupt Mask Register CAN IMR The setup for the interrupt mask register see Figure 10 22 is the same as for the interrupt flag register CAN IFR with the addition of the interrupt priority selection bits MIL and EIL If a mask bit is set the corresponding interrupt request to the PIE controller is enabled Figure 10 22 CAN Interrupt Mask Register CAN IMR Address 710Ah 15 14 13 12 11 10 9 8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access value following dash value after reset Two additional control bits are included in this register Bit 15 MIL Mailbox Interrupt Priority Level For the mailbox interrupts MIF5 MIFO 0 The mailbox interrupts generate high priority requests 1 The mailbox interrupts gener
461. s of the PLL 4 2 4 4 Resonaltor Crystal Oscillator The oscillator requires two external pins XTAL1 CLKIN and XTAL2 which are connected to the resonator crystal and load capacitors Figure 4 1 The oscillator is a single stage inverter held in bias by an integrated bias resistor This resistor is disabled only during leakage test measurements and HALT mode Figure 4 1 Reference Resonator Crystal Vss near osc pins To reduce EMI l Board ground keep allof CA XTAL1 CLKIN these routes short and minimize loop Resonator areas Y1 Resonator oscillator T XTAL2 Pis Cb Clock Module Q s Note Validating Resonator Crystal Vendors Texas Instruments strongly encourages each customer to submit samples of the device to the resonator crystal vendor for validation They are equipped to determine which load capacitors will best tune their resonator crystal to the DSP for optimum start up and operation over temperature voltage extremes They also factor in a margin for the device process variations T 4 2 2 2 External Oscillator The PLL can also be driven by an external oscillator whose output is connected to XTAL1 CLKIN pin XTAL2 is left open in this case Phase Locked Loop PLL 4 2 2 3 Loop Filter Components The 240xA PLL needs external R C components for the loop filter see device data sheet for more detai
462. s the corresponding flag in the CPU s interrupt flag register IFR If the CPU interrupt has been enabled by setting the corresponding bit in the CPU s interrupt mask register IMR the CPU stops what it is doing masks all other maskable interrupts by setting the INTM bit saves some context and starts executing the general interrupt service routine GISR for that interrupt priority level INTn The CPU generates an interrupt acknowledge automatically which is accompanied by a value on the program address bus PAB corresponding to the interrupt priority level being responded to For example if INT3 is asserted its vector 0006h is loaded in the PAB This is the interrupt vector corresponding to INTn refer to Table 2 2 240xA Interrupt Source Priority and Vectors on page 2 9 The PIE controller decodes the PAB value and generates a peripheral interrupt acknowledge to clear the PIRQ bit associated with the CPU interrupt being acknowledged The PIE controller then loads the peripheral interrupt vector register PIVR with the appropriate peripheral interrupt vector or the phantom interrupt vector from the table stored in the PIE controller When the GISR has completed any necessary context saves it reads the PIVR and uses that interrupt vector to branch to the specific interrupt service routine SISR for the interrupt event which occurred in the peripheral
463. s the flag for interrupts connected to interrupt level INT3 0 NoINT3 interrupt is pending 1 At least one INT3 interrupt is pending Write a 1 to this bit to clear it to O and clear the interrupt request Bit 1 INT2 Interrupt 2 flag This bit is the flag for interrupts connected to interrupt level INT2 O0 NoINT2 interrupt is pending 1 At least one INT2 interrupt is pending Write a 1 to this bit to clear it to 0 and clear the interrupt request Bit 0 INT1 Interrupt 1 flag This bit is the flag for interrupts connected to interrupt level INT1 0 NoINTI1 interrupt is pending 1 At least one INT1 interrupt is pending Write a 1 to this bit to clear it to O and clear the interrupt request System Configuration and Interrupts 2 27 CPU Interrupt Registers 2 9 2 Interrupt Mask Register IMR The IMR is a 16 bit memory mapped register located at address 0004h in data memory space The IMR contains mask bits for all the maskable interrupt levels INT1 INT6 Neither NMI nor RS is included in the IMR thus IMR has no effect on these interrupts You can read the IMR to identify masked or unmasked interrupt levels and you can write to the IMR to mask or unmask interrupt levels To unmask an interrupt level set its corresponding IMR bit to one To mask an interrupt level set its corresponding IMR bit to zero When an interrupt is masked it is not acknowledged regardless of the value of the INTM bit When an interrupt is unmasked it
464. sequence is the first of the two sequences needed to assert an interrupt Bit 1 INT FLAG SEQ2 ADC interrupt flag bit for SEQ2 This bit indicates whether an interrupt event has occurred or not This bit must be cleared by the user writing a 1 to it 0 No interrupt event 1 An interrupt event has occurred Bit 0 EVB SOC SEQ2 Event Manager B SOC mask bit for SEQ2 0 SEQ cannot be started by EVB trigger 1 Allows SEQ to be started by Event Manager B trigger The Event Manager can be programmed to start a conversion on various events See chapter 6 Event Manager EV for details 7 5 3 Maximum Conversion Channels Register MAXCONV Figure 7 11 Maximum Conversion Channels Register MAXCON V Address 70A2h 15 8 Reserved R x R F MAX MAX MAX MAX MAX MAX MAX aces CONV 2 CONV2 1 CONV20 CONV13 CONV12 CONV1_1 CONV1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access x undefined 0 value after reset Analog to Digital Converter ADC 7 31 Register Bit Descriptions Bits 15 7 Reserved Bits 6 0 MAX CONVn MAX CONVn bit field defines the maximum number of conver sions executed in an autoconversion session The bit fields and their operation vary according to the sequencer modes dual cascaded For SEQ1 operation bits MAX CONV1 2 0 are used For SEQ2 operation bits MAX CONV2 2 0 are used For SEQ operation bits MAX CONV1 3 0 are used An autoconvers
465. sersa ERR insna ASEN EEA DEEA 10 4 CAN Control Registers een eee 10 4 1 Mailbox Direction Enable Register MDER 10 4 2 Transmit Control Register TCR 00 cece eee eee eens 10 4 8 Receive Control Register RCR 0 00 cece ee tenes 10 4 4 Master Control Register MCR 0c cece eee eee ees 10 4 5 Bit Configuration Registers BCRn 0 10 5 Status Registers 0 ccc eet E eens 10 5 1 Error Status Register ESR lt eee 10 5 2 Global Status Register GSR 2 10 5 83 CAN Error Counter Register CEC 00 0 ccc eee eee ees 10 6 Interrupt LOGIC ioa Deere eme eR bh ade eU RET OE UU 10 6 1 CAN Interrupt Flag Register CAN IFR 10 6 2 CAN Interrupt Mask Register CAN IMR ssssasasaaaaanaaan ea 10 7 Configuration Mode 0 0 ccc ehh 10 8 Power Down Mode PDM 0 2 00 cece e nee 10 9 Suspend Mode 0 06 cece eee hn Watchdog WD Timer onec deda don dro da woe RO Describes the features and operation of the watchdog WD timer module Covers the architec ture and the registers used to implement WD functions 11 1 Watchdog Timer Features es nn 11 2 Watchdog Timer Operations 0 00 cece eet 11 2 1 Overview of WD Timer Operations 0 0000 eee e eee 11 2 2 Watchdog Timer Clock ees Contents 11 2 8 Watchdog Suspend ssssssesssssssessss n 11 2 4 Operations of the WD Timer 11 8 Watchdog Control Register
466. set the old message is overwritten by the new one 10 4 4 Master Control Register MCR MCR is used to control the behavior of the CAN core module Figure 10 14 Master Control MCR Address 7103h 15 14 11 OC RW 0 RW 1 RW 0 RW 0 RW 0 7 6 5 2 1 0 RW 0 RW 0 RW 0 Note R Read access W Write access value following dash value after reset Bits 15 14 Reserved Bit 13 SUSP Action on emulator suspend The value of the SUSP bit has no effect on the receive mailboxes 0 Soft mode The peripheral shuts down during suspend after the current transmission is completed 1 Free mode The peripheral continues to run in suspend CAN Controller Module 10 23 CAN Control Registers Bit 12 CCR Change Configuration Request 0 The CPU requests normal operation It also exits the bus off state after the obligatory bus off recovery sequence 1 The CPU requests write access to the bit configuration registers BCRn Flag CCE in the GSR indicates if the access is granted CCR must be set while writing to bit timing registers BCR1 and BCR2 This bit will automatically be set to 1 if the bus off condition is valid and the ABO bit is not set Thus it has to be reset to exit the bus off mode Bit 11 PDR Power Down Mode Request Before the CPU enters its IDLE mode if IDLE shuts off the peripheral clocks it must request a CAN power down by writing to the PDR bit The CPU must then poll the PDA bit in the GSR and enter IDLE only after
467. set clear this bit until EOS has occurred for valid action to be taken In the continuous conversion mode there is no need to reset the sequencer however the sequencer must be reset in the start stop mode to put the converter in state CONVOO 0 Start stop mode Sequencer stops after reaching EOS This is used for multiple time sequenced triggers 1 Continuous conversion mode After reaching EOS the sequencer starts all over again from state CONVOO for SEQ1 and cascaded or CONVO8 for SEQ2 Bit 5 INT PRI ADC interrupt request priority 0 High priority 1 Low priority Bit 4 SEQ CASC Cascaded sequencer operation This bit determines whether SEQ1 and SEQ 2 operate as two 8 state sequencers or as a single 16 state sequencer SEQ 0 Dual sequencer mode SEQ1 and SEQ operate as two 8 state sequencers 1 Cascaded mode SEQ1 and SEQ operate as a single 16 state sequencer SEQ Bit 3 CAL ENA Offset calibration enable When set to 1 CAL ENA disables the input channel multiplexer and connects the calibration reference selected by the bits HI LO and BRG ENA to the ADC core inputs The calibration conversion can then be started by setting bit 14 of ADCTRL2 register STRT CAL to 1 Note that CAL ENA should be set to 1 first before the STRT CAL bit can be used Note This bit should not be set to 1 if STEST ENA 1 0 Calibration mode disabled 1 Calibration mode enabled 7 24 Bit 2 Bit 1 Register Bit Descriptions BRG ENA B
468. sferred to the SPIRXBUF buffered receiver for the CPU to read Data is stored right justified in SPIRXBUF When the specified number of data bits has been shifted through SPIDAT the following events occur SPIDAT contents are transferred to SPIRXBUF J SPI INT FLAG bit SPISTS 6 is set to 1 Slave Mode SPI Operation If there is valid data in the transmit buffer SPITXBUF as indicated by the TXBUF FULL bit in SPISTS this data is transferred to SPIDAT and is transmitted otherwise SPICLK stops after all bits have been shifted out of SPIDAT Ifthe SPI INT ENA bit SPICTL O is set to 1 an interrupt is asserted In a typical application the SPISTE pin serves as a chip enable pin for a slave SPI device and drives this pin high again after transmitting the master data This pin is driven low by the master before transmitting data to the slave and is taken high after the transmission is complete In the slave mode MASTER SLAVE 0 data shifts out on the SPISOMI pin and in on the SPISIMO pin The SPICLK pin is used as the input for the serial shift clock which is supplied from the external network master The transfer rate is defined by this clock The SPICLK input frequency should be no greater than the CLKOUT frequency divided by 4 Data written to SPIDAT or SPITXBUF is transmitted to the network when appropriate edges of the SPICLK signal are received from the network master Data written to the SPITXBUF register
469. sh control mode register BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 0000h 0001h 0002h 0003h 0004h 0005h set set set set set set Bit Bit Bit Bit Bit Bit Code Code Code Code Code Code 15 14 13 12 11 10 for for for for for for Bit codes for Test bit instruction BIT 15 Loads bit 0 into TC Program Examples bits bits bits bits bits bits C 9 Program Examples IT9 IT8 IT7 IT6 IT5 ITA IT3 IT2 ITI ITO UJ UJ UJ UU UJ UJ UU UJ tU w set set set set set set set Get set set 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Code Code Code Code Code Code Code Code Code Code for for for for for for for for for for O HB N 0 df UI O 1 O WO Program Examples PRR RRR RK RK RK KKK KKK KK KK KK KK RK KK KK KK KK k k k KKK ck kck ck ck ck ck ck ck k k ck ck ck ck k k ko File name vector h Interrupt Vector declarations This section contains the vectors for various interrupts in the 240x Unused interrupts are shown to branch to a phantom interrupt service routine which loops on itself Users should replace the label PHANTOM with the label of their interrupt subroutines in case these interrupts are used PRR RRR k k k ke k k ke k e he ke k k ke ke e he ke k ke he ke e he ke k k he ke k he ke k k he
470. signed specifically for real time signal processing The 240xA series of DSP controllers combines this real time processing capability with controller peripherals to create an ideal solution for control system applications The following characteristics make the TMS320 family the right choice for a wide range of processing applications _j Very flexible instruction set Inherent operational flexibility O High speed performance _j Innovative parallel architecture Cost effectiveness In 1982 Texas Instruments introduced the TMS32010 the first fixed point DSP in the TMS320 family Before the end of the year Electronic Products magazine awarded the TMS32010 the title Product of the Year Today the TMS320 family consists of these generations C1x C2x C20x C24x C5x C54x and C6x fixed point DSPs C3x and C4x floating point DSPs and C8x multiprocessor DSPs The 240xA devices are considered part of the 24x generation of fixed point DSPs and members of the C2000 platform Devices within a generation of a TMS320 platform have the same CPU structure but different on chip memory and peripheral configurations Spin off devices use new combinations of on chip memory and peripherals to satisfy a wide range of needs in the worldwide electronics market By integrating memory and peripherals onto a single chip TMS320 devices reduce system costs and save circuit board space TMSS320C240xA Series of DSP Controllers 1 2 TMS320C240xA Series
471. sions figure maximum conversion channels register MAXCONV bit selections for MAX CONV for various number of conversions MAX CONV value gt 7 for dual sequencer mode register bit programming overview register addresses register bit descriptions single and cascaded operating modes comparison address bit multiprocessor communication format SCI serial communications interface address bit multiprocessor mode SCI serial com munications interface sending an address addressing bit reversed indexed addressing modes definition Index 1 Index analog to digital converter ADC 240xA to 240 family compatibility architectural summary 240xA devices figure asynchronous communication format SCI serial communications interface autoconversion sequencer basic operation conversion in dual sequencer mode using SEQ1 7 8 block diagram of autoseguenced ADC in cascaded mode block diagram of autoseguenced ADC with dual seguencers comparison of single and cascaded operating modes input trigger description interrupt operation during seguenced conversions figure principle of operation sequencer start stop operation with multiple time seguenced triggers example of event manager triggers to start the seguencer example of seguencer start stop operation with multiple time seguenced triggers uninterrupted autoseguenced mode auxiliary register pointer ARP auxiliary register pointer buffer ARB baud rate calcu
472. software hierarchy system control registers 240xA devices Boot EN XF pin operation fast RD strobe operation 13 9 TAn transmission acknowledge for mailbox n TCR transmission control register timer control register TXCON M 1 2 3 or 4 TMS320 family 1 2 1o 1 6 advantages development history 1 2 overview 1 2 transmit mailboxes 10 13 transmitter signals in communication modes SCI serial communications interface TRRn transmission request reset for mailbox n TRSn transmission request set for mailbox n 10 21 wait state definition wait state generation setting the number of wait states with the 2407A WSGR bits with the 2407A wait state generator with the READY signal Index 22 wake up from low power modes external interrupts reset wake up interrupts wake up temporary WUT SCI serial communications interface double buffered WUT and TXSHF wake up temporary WUT flag SCI serial communications interface watchdog clock 240xA devices watchdog suspend watchdog timer 240xA to 240 family compatibility 12 4 watchdog timer WD features block diagram of the WD module operation overview watchdog suspend watchdog timer clock WDCLK operations operations of the WD timer servicing the WD timer WD check bit logic WD prescale select WD reset WD setup WDKEY register power up sequence typical watchdog control registers table WD counter register WDCNTR WD overf
473. sor communication format allows one processor to efficiently send blocks of data to other processors on the same serial link On one serial line there should be only one transfer at a time In other words there can be only one talker on a serial line at a time The first byte of a block of information that the talker sends contains an address byte that is read by all listeners Only listeners with the correct address can be interrupted by the data bytes that follow the address byte The listeners with an incorrect address remain uninterrupted until the next address byte All processors on the serial link set their SCl s SLEEP bit SCICTL1 2 to 1 so that they are interrupted only when the address byte is detected When a processor reads a block address that corresponds to the CPU s device address as set by your application software your program must clear the SLEEP bit to enable the SCI to generate an interrupt on receipt of each data byte Although the receiver still operates when the SLEEP bit is 1 it does not set RXRDY RXINT or any of the receiver error status bits to 1 unless the address byte is detected and the address bit in the received frame is a 1 applicable to address bit mode The SCI does not alter the SLEEP bit your software must alter the SLEEP bit Recognizing the Address Byte A processor recognizes an address byte differently depending on the multiprocessor mode used For example The idle line mode section 8 3
474. stem Configuration and Interrupts 2 11 Interrupt Priority and Vectors Table 2 2 240xA Interrupt Source Priority and Vectors Continued e INT5 level 5 CPU Peripheral Overall Interrupt Interrupt Interrupt Source Priority Name Vector Vector Maskable Peripheral Description 42 SPIINT INT5 0005h Y SPI SPI interrupt 000Ah low priority 43 RXINT INT5 0006h Y SCI SCI receiver interrupt 000Ah low priority mode 44 TXINT INT5 0007h Y SCI SCI transmitter interrupt 000Ah low priority mode 45 CANMBINT INT5 0040h Y CAN CAN mailbox interrupt 000Ah low priority mode 46 CANERINT INT5 0041h Y CAN CAN error interrupt 000Ah low priority mode f INT6 level 6 CPU Peripheral Overall Interrupt Interrupt Interrupt Source Priority Name Vector Vector Maskable Peripheral Description 47 ADCINT INT6 0004h Y ADC ADC interrupt 000Ch low priority 48 XINT1 INT6 0001h Y External External interrupt pins 000Ch interrupt logic low priority mode 49 XINT2 INT6 0011h Y External External interrupt pins 000Ch interrupt logic low priority mode Reserved 000Eh N A Y CPU Analysis interrupt N A TRAP 0022h N A N A CPU TRAP instruction N A Phantom N A 0000h N A CPU Phantom interrupt Interrupt vector Vector Note Shaded interrupts are new interrupts added to 240xA by virtue of EVB Interrupts of nonexistent peripherals may not be applicable to a particular device For example SPI and CAN interrupts are not applicable to the 2402A device 2 12 Pe
475. ster next auxiliary register The register that is pointed to by the auxiliary regis ter pointer ARP when an instruction that modifies ARP is finished executing See also auxiliary register current auxiliary register Glossary F 9 Glossary nonmaskable interrupt An interrupt that can be neither masked by the interrupt mask register IMR nor disabled by the INTM bit of status register STO NPAR Next program address register Part of the program address genera tion logic This register provides the address of the next instruction to the program counter PC the program address register PAR the micro stack MSTACK or the stack operand A value to be used or manipulated by an instruction specified in the instruction operand fetch phase The third phase of the pipeline the phase in which an operand or operands are fetched from memory See also pipeline instruction fetch phase instruction decode phase instruction execute phase output shifter 32 to 16 bit barrel left shifter Shifts the 32 bit accumulator output from O to 7 bits left for quantization management and outputs either the 16 bit high or low half of the shifted 32 bit data to the data write bus DWEB OV bit Overflow flag bit Bit 12 of status register STO indicates whether the result of an arithmetic operation has exceeded the capacity of the accumulator overflow in a register A condition in which the result of an arithmetic operation exceeds
476. ster IFR a 16 bit memory mapped register at address 0006h in data memory space is used to identify and clear pending interrupts The IFR contains flag bits for all the maskable interrupts INT1 INT6 When a maskable interrupt is requested the flag bit in the corresponding peripheral control register is set to 1 If the corresponding mask bit is also 1 the interrupt request is sent to the CPU setting the corresponding flag in the IFR This indicates that the interrupt is pending or waiting for acknowledgement You can read the IFR to identify pending interrupts and write to the IFR to clear pending interrupts To clear a single interrupt write a one to the corresponding IFR bit All pending interrupts can be cleared by writing the current contents of the IFR back into the IFR The following events also clear an IFR flag Li The CPU acknowledges the interrupt The 240xA is reset Notes 1 To clear an IFR bit you must write a one to it not a zero 2 When a maskable interrupt is acknowledged only the IFR bit is cleared automatically The flag bit in the corresponding peripheral control regis ter is not cleared If an application requires that the control register flag be cleared the bit must be cleared by software 3 When an interrupt is requested by an INTR instruction and the corre sponding IFR bit is set the CPU does not clear the bit automatically If an application requires that the IFR bit be cleared the bit
477. t Timer 3 underflow interrupt Timer 3 overflow interrupt Table 2 2 240xA Interrupt Source Priority and Vectors Continued c INT3 level 3 Overall Priority 28 29 30 31 32 33 34 35 Interrupt Name T2PINT T2CINT T2UFINT T2OFINT TAPINT T4CINT T4UFINT T4OFINT a INT4 level 4 Overall Priority 36 37 38 39 40 41 Interrupt Name CAP1INT CAP2INT CAPSINT CAPAINT CAPBINT CAP6INT CPU Interrupt Vector INT3 0006h INT3 0006h INT3 0006h INT3 0006h INT3 0006h INT3 0006h INT3 0006h INT3 0006h CPU Interrupt Vector INT4 0008h INT4 0008h INT4 0008h INT4 0008h INT4 0008h INT4 0008h Peripheral Interrupt Vector 002Bh 002Ch 002Dh 002Eh 0039h 003Ah 003Bh 003Ch Peripheral Interrupt Vector 0033h 0034h 0035h 0036h 0037h 0038h Maskable Y Y Maskable Y Y Source Peripheral EVA EVA EVA EVA EVB EVB EVB EVB Source Peripheral EVA EVA EVA EVB EVB EVB Interrupt Priority and Vectors Description Timer 2 period interrupt Timer 2 compare interrupt Timer 2 underflow interrupt Timer 2 overflow interrupt Timer 4 period interrupt Timer 4 compare interrupt Timer 4 undeflow interrupt Timer 4 overflow interrupt Description Capture 1 interrupt Capture 2 interrupt Capture 3 interrupt Capture 4 interrupt Capture 5 interrupt Capture 6 interrupt Sy
478. t is optional As this syntax shows if you use the optional second parameter you must precede it with a comma Square brackets are also used as part of the pathname specification for VMS pathnames in this case the brackets are actually part of the path name they are not optional Braces indicate a list The symbol read as or separates items with in the list Here s an example of a list 11 This provides three choices or Unless the list is enclosed in square brackets you must choose one item from the list Some directives can have a varying number of parameters For example the byte directive can have up to 100 parameters The syntax for this di rective is byte value values This syntax shows that byte must have at least one value parameter but you have the option of supplying additional value parameters separated by commas Related Documentation From Texas Instruments Information About Cautions and Warnings This document may contain cautions This is an example of a caution statement A caution statement describes a situation that could potentially damage your software or equipment Related Documentation From Texas Instruments The following books describe the C24x and related support tools To obtain a copy of any of these TI documents call the Texas Instruments Literature Re sponse Center at 800 477 8924 When ordering please identify the book by its title a
479. t Descriptions Table 7 4 ADC Clock Prescale Factors for CLK 40 MHz Source Source ACQ ACQ ACQ ACQ hol Acquisition Time eps GPS 4 PS3 PS2 PS1 PSO div by Window Q Q 0 0 0 0 0 1 2xTy 58 29 1 0 0 0 1 2 4 X Tok 291 767 2 0 0 1 0 3 6 x Tolk 529 1244 3 0 0 1 1 4 8 x Tolk 767 1720 4 0 1 0 0 5 10 x Tg 1005 2196 5 0 1 0 1 6 12 x Telk 1244 2672 6 0 1 1 0 7 14 x Tok 1482 3148 7 0 1 1 1 8 16 x Tg 1720 3625 8 1 0 0 0 9 18 x Tolk 1958 4101 9 1 0 0 1 10 20 x Tolk 2196 4577 A 1 0 1 0 11 22 x Tolk 2434 5053 B 1 0 1 1 12 24 x Talk 2672 5529 C 1 1 0 0 13 26 x Tok 2910 6005 D 4 1 0 1 14 28 x Tg 3148 6482 E 1 1 1 0 15 30 x Tolk 3386 6958 F 1 1 1 1 16 32 x Talk 3625 7434 Notes 1 Period of Toi is dependent on the Conversion Clock Prescale bit Bit 7 i e CPS 0 Tok CLK example for CLK 40 MHz Telk 25 ns CPS 1 Telk 2 x 1 CLK example for CLK 40 MHz Telk 50 ns 2 Source impedance Z is a design estimate only Analog to Digital Converter ADC 7 23 Register Bit Descriptions Bit 7 CPS Conversion clock prescale This bit defines the ADC conversion logic clock prescale 0 Fok CLK 1 1 Fo CLK 2 CLK CPU clock frequency Bit 6 CONT RUN Continuous run This bit determines whether the sequencer operates in continuous conversion mode or start stop mode This bit can be written while a current conversion sequence is active This bit will take effect at the end of the current conversion sequence i e software can
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481. t the TRS bit See Figure 10 8 F In this case the module sends a remote frame request and receives the data frame in the same mailbox that sent the request Therefore only one mailbox is necessary to do a remote request 10 3 7 Mailbox Configurations A mailbox can be configured in four different ways _j Transmit mailbox mailboxes 4 and 5 or 2 and 3 configured as transmit can only transmit messages _j Receive mailbox mailboxes 0 and 1 can only receive messages J Mailboxes 2 and 3 configured as receive mailboxes can transmit a remote request frame and wait for the corresponding data frame if the TRS bit is set Mailboxes 2 and 3 configured as transmit mailboxes can transmit a data frame wherever a remote request frame is received for the corresponding identifier if the AAM bit is set Note After successful transmission of a remote frame the TRS bit is reset but no transmit acknowledge TA or mailbox interrupt flag is set LLLLLS S OM AAEIAOA AMA OON CAN Controller Module 10 15 Message Objects Figure 10 8 Remote Frame Requests Situation at mailbox Setting of corresponding flags remote frame RTR 1 Transmit mailbox AAM 1 data frame p TRS 1 TA 1 Transmit mailbox remote frame RTR 1 AAM 0 4 not received remote frame RTR 1 Transmit mailbox gt The answer is received in this receive mailbox if per
482. tant definitions DP PF1 set OEOh Page 1 of peripheral file 7000h 80h DP_CAN set 0E2h CAN Register 7100h DP CAN2 set 0E4h CAN RAM 7200h MACRO Definitions KICK DOG macro Watchdog reset macro LDP 00EOh SPLK 05555h WDKEY SPLK HOAAAAh WDKEY LDP 0h endm MAIN CODE starts here text START KICK DOG Reset Watchdog counter SPLK 0 60h OUT 60h WSGR Set waitstates for external memory if used LDP 0EOh SPLK 006Fh WDCR Disable WD SPLK 0010h SCSR1 Enable clock to CAN module For 240xA only LDP 225 SPLK 00COH MCRB Configure CAN pins p RRR RRR KERR e e he e e e he e e RRR e he e e e he e He e he e ke he he e RRR e e che he e e RRR KER KERR RE RRR He He He e ke ke he ke ke ke ke e ke Enable 1 core interrupt p RRR ke ke ke e ce e e e he e e e he e e e he e e e he e e e he e ke e he e e he he e ehe he e e He he e e che e e He e he ke e He ke He He He ke kc ke che ke He ke he e ke ke ke e ke LDPK 0 SPLK 0000000000010000b IMR core interrupt mask register i PLL Enable INT5 for CAN E FEDCBA9876543210 SPLK 000FFh IFR Clear all core interrupt flags CLRC INTM enable interrupt LDP HDP CAN SPLK 1011111111111111b CANIMR Enable all CAN interrupts Hid dod k ke ke k ke de k ke ke KERR RRR RRR RRR RRR KERR RRR RK ERR KERR KK ERR KERR RRR REE RRR ERR EE k k k k k k k k pee DISABLE MBX BEFORE WRITING TO MSGID MSGCTRL OF MBX2 k y EK K k k k ke k k ke ke k ke ke k ke ke k ke ke k
483. tate generator must be programmed to generate at least one wait state Note The READY pin has no effect on accesses to internal memory 3 11 2 Generating Wait States With the 2407A Wait State Generator The software wait state generator can be programmed to generate zero to seven wait states for a given off chip memory space program data or I O This wait state generator has the bit fields shown in Figure 3 7 and described after the figure Memory 3 17 Wait State Generation Figure 3 7 2407A Wait State Generator Control Register WSGR O Space Address FFFFh 2407A 15 11 10 9 8 6 5 3 2 0 0 W 11 W 111 W 111 W 111 Note 0 Always read as zeros W Write access n value after reset Bits 15 11 Reserved Bits 15 11 are reserved and always read as Os Bits 10 9 Bus visibility modes Bits 10 9 allow selection of various bus visibility modes while running from internal program and or data memory These modes pro vide a method of tracing internal bus activity Bit 10 Bit9 Visibility mode 0 O Busvisibility OFF reduces power and noise 0 1 Bus visibility OFF reduces power and noise 1 O JData address bus output to external address bus Data data bus output to external data bus 1 1 Program address bus o p to external address bus Program data bus output to external data bus Note On the 2407A device the bus visibility is turned off until the device is unsecured Bits 8 6 ISWS l O space wait state bits Bits
484. te buffers The only difference is that reading SCIRXEMU does not clear the RXRDY flag however reading SCIRXBUF clears the flag 8 7 6 1 Emulation Data Buffer Normal SCI data receive operations read the data received from the SCIRXBUF register The SCIRXEMU register is used principally by the emulator EMU because it can continuously read the data received for screen updates without clearing the RXRDY flag SCIRXEMU is cleared by a system reset This is the register which should be used in an emulator watch window to view the contents of SCIRXBUF register 8 30 SCI Module Registers SCIRXEMU is not physically implemented it is just a different address location to access the SCIRXBUF register without clearing the RXRDY flag Figure 8 17 Emulation Data Buffer Register SCIRXEMU Address 7056h Y 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Note R Read access 0 value after reset 8 7 6 2 Receiver Data Buffer SCIRXBUF When the current data received is shifted from RXSHF to the receiver buffer flag bit RXRDY is set and the data is ready to be read If the RX BK INT ENA bit SCICTL2 1 is set this shift also causes an interrupt When SCIRXBUF is read the RXRDY flag is reset SCIRXBUF is cleared by a system reset Figure 8 18 Receiver Data Buffer SCIRXBUF Address 7057h 7 6 5 4 3 2 1 0 RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDTO R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Note R Read access 0 value after reset
485. te Calculations 8 6 SCI Baud Rate Calculations The internally generated serial clock is determined by the device clock frequency CLKOUT and the baud select registers The SCI uses the 16 bit value of the baud select registers to select one of the 64K different serial clock rates possible for a given device clock See the bit descriptions in section 8 7 3 Baud Select Registers on page 8 26 for the formula to use when calculating the SCI asynchronous baud Table 8 3 shows the baud select values for common SCI bit rates Table 8 3 Asynchronous Baud Register Values for Common SCI Bit Rates Device Clock Frequency 40 MHz Ideal Baud BRR Actual Baud Error 2400 2082 822h 2400 0 4800 1040 411h 4803 0 06 9600 520 208h 9597 0 03 19200 259 103h 19231 0 16 38400 129 81h 38462 0 16 Note The maximum CLKOUT frequency for 240xA devices is 40 MHz Serial Communications Interface SCI 8 19 SCI Module Registers 8 7 SCI Module Registers The functions of the SCI are software configurable Sets of control bits organized into dedicated bytes are programmed to initialize the desired SCI communications format This includes operating mode and protocol baud value character length even odd parity or no parity number of stop bits and interrupt priorities and enables The SCI is controlled and accessed through registers listed in Figure 8 9 and described in the sections that follow Figure 8 9 SCI Registers Bit N it N
486. tely under arbiter control and the bit is cleared allowing for any pending trigger requests Case2 SEQ busy and SOC bit clear Bit is set signifying a trigger request is pending When SEQ finally starts after completing current conversion this bit will be cleared Case 3 SEQ busy and SOC bit set Any trigger occurring in this case will be ignored lost 0 Clears a Pending SOC trigger Note If the sequencer has already started this bit will automatical ly be cleared and hence writing a zero will have no effect i e an already started sequencer cannot be stopped by clearing this bit 1 Software trigger Start SEQ2 from currently stopped position i e Idle mode Bit 4 SEQ2 BSY SEQ2 Busy This bit is set to a 1 while the ADC autoconversion sequence is in progress It is cleared when the conversion sequence is complete 0 Sequencer is idle i e waiting for trigger 1 Conversion sequence is in progress 7 30 Register Bit Descriptions Bits 3 2 INT ENA SEQ2 Interrupt mode enable control for SEQ2 Bit 3 Bit 2 Operation Description 0 0 Interrupt is Disabled 0 1 Interrupt Mode 1 Interrupt requested immediate on INT FLAG SEQ flag set 1 0 Interrupt Mode 2 Interrupt requested only if INT FLAG SEQ flag is already set If cleart INT FLAG SEQ flag is set and INT request is suppressed This mode allows Interrupt requests to be generated for every other EOS 1 1 Reserved T This means that the last completed
487. ter RPTC A 16 bit register that counts the number of times a single instruction is repeated RPTC is loaded by an RPT instruction reset A way to bring the processor to a Known state by setting the registers and control bits to predetermined values and signaling execution to start at address 0000h reset pin RS A pin that causes a reset reset vector The interrupt vector for reset return address The address of the instruction to be executed when the CPU returns from a subroutine or interrupt service routine Glossary RPTC See repeat counter RPTC RS Reset pin When driven low causes a reset on any 24x device R W Read write pin Indicates the direction of transfer between the 24x and external program data or I O space scratch pad RAM Another name for DARAM block B2 in data space 32 words short immediate value An 8 9 or 13 bit constant given as an operand of an instruction that is using immediate addressing sign bit The MSB of a value when it is seen by the CPU to indicate the sign negative or positive of the value sign extend Fill the unused high order bits of a register with copies of the sign bit in that register sign extension mode SXM bit Bit 10 of status register ST1 enables or disables sign extension in the input shifter It also differentiates between logic and arithmetic shifts of the accumulator slave phase See atch phase software interrupt An interrupt caused by the execu
488. ternal SARAM When configured as external these addresses can be used for off chip program memory SARAM is accessed only once per CPU cycle When the CPU requests multiple accesses the SARAM schedules the accesses by providing a not ready condition to the CPU and then executing the accesses one per cycle For example if the instruction sequence involves storing the accumulator value and then loading a value to the accumulator it would take two cycles to complete in SARAM compared to one cycle in DARAM Factory Masked On Chip ROM Flash 3 2 Factory Masked On Chip ROM 3 3 Flash The on chip ROM in ROM devices is mapped in program memory space This ROM is always enabled since these devices lack an external memory interface This ROM is programmed with customer specific code The on chip flash in flash devices is mapped in program memory space This flash memory is always enabled in devices that lack an external memory interface For the 2407A which has an external memory interface the MP MC pin determines whether the on chip program memory flash or the off chip program memory customer design specific is accessed 3 3 1 Flash Program Memory The Flash module is used to provide permanent program storage The Flash can be programmed and electrically erased many times to allow code development The 240xA Flash is similar to that on the 24x devices with some key differences and enhancements 240xA Flash features are as follows F
489. terrupt l4 slo X V4 V5 V3 i l4 lox V4 V5 V5 t Sampling request Case 3 SEQ interrupt ADC Clock Prescaler 7T 3 ADC Clock Prescaler The S H block in the 240xA ADC can be tailored to accomodate the variation in source impedances This is achieved by the ACQ PS3 ACQ PS0 bits and the CPS bit in the ADCTR1 register The analog to digital conversion process can be divided into two time segments as shown in Figure 7 6 Figure 7 6 ADC Conversion Time 2 PS S H window i Conversion 11 Agi 1 complete ADC conversion gt PS a prescaled CPU clock PS will be the same as the CPU clock if the prescaler 1 i e ACA PS3 ACQ PSO bits are all zero and if CPS 0 For any other value of the prescaler the magnitude of PS will be magnified effectively increasing the S H window time as described by the Acquisition Time Window column in the bit description for ACQ PS3 ACQ PSO If the CPS bit is made 1 the S H window is doubled This doubling of the S H window is in addition to the stretching provided by the prescaler Figure 7 7 shows the role played by the various prescaler bits in the ADC module Note that PS and Ac will be equal to CPU clock if CPS 0 Analog to Digital Converter ADC FAL ADC Clock Prescaler Figure 7 7 Clock Prescalers in 240xA ADC ACQ PS3 ACQ PSO Divide by 2 CPS 1 CLK Q9 AcLK Divide by CPU clock L o 1 19 18 CPS
490. terrupt High priority INT1 IRQ 0 6 TXINT SCI transmitter interrupt High priority INT1 IRQ 0 7 CANMBINT CAN mailbox interrupt High priority INT1 IRQ 0 8 CANERINT CAN error interrupt High priority INT1 IRQ 0 9 CMP1INT Compare 1 interrupt INT2 System Configuration and Interrupts 2 31 Peripheral Interrupt Registers Table 2 3 Peripheral Interrupt Request Descriptions PIRQRO Continued RQ0 10 CMP2INT X Compae2inemup dI IRQ 0 11 CMPSINT Compare 3 interrupt INT2 IRQ 0 12 T1PINT Timer 1 period interrupt INT2 IRQ 0 13 T1CINT Timer 1 compare interrupt INT2 IRQ 0 14 T1UFINT Timer 1 underflow interrupt INT2 IRQ 0 15 T1OFINT Timer 1 overflow interrupt INT2 Figure 2 12 Peripheral Interrupt Request Register 1 PIRQR1 Address 7011h 15 11 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bit 15 Reserved Reads return zero writes have no effect Bits 14 0 IRQ1 14 IRQ1 0 0 Corresponding peripheral interrupt is not pending 1 Peripheral Interrupt is pending Note Writing a 1 sends IRQ to core writing a 0 has no effect Peripheral Interrupt Registers Table 2 4 Peripheral Interrupt Request Descriptions PIRQR1 Bit position Interrupt Interrupt Description Interrupt Level IRQ 1 0 T2PINT Timer 2 period interrupt INT3 IRQ 1 1 T2CINT Timer 2 compare interrupt INT3 IRQ 1 2 T2UFINT Timer 2 underflow interrupt INT3 IR
491. terrupt request If a peripheral has this capability the value of its interrupt priority bit is also transmitted to the interrupt controller The interrupt request PIRQ continues to be asserted until it is either automatically cleared by an interrupt acknowledge or cleared by the software At the upper level of the hierarchy the ORed PIRQs generate interrupt INTn requests to the CPU The request to the C240xA CPU is a low going pulse of two CPU clock cycles The PIE controller generates an INTn pulse when any of the PIRQ s controlling the INTn become active If any of the PIRQ s capable of asserting the CPU interrupt request are still active in the cycle following an interrupt acknowledge for the INTn another INTn pulse is generated An interrupt acknowledge clears the highest priority pending PIRQ Note that the interrupts are automatically cleared only at the core level and not at the peripheral level The interrupt controller not the peripherals defines the following Which CPU interrupt request gets asserted by which peripheral _ Relative priority of each peripheral interrupt requests This is shown in Table 2 2 240xA Interrupt Source Priority and Vectors on page 2 9 System Configuration and Interrupts 2 15 Peripheral Interrupt Expansion PIE Controller 2 4 3 2 16 Interrupt Acknowledge The hierarchical interrupt expansion scheme requires one interrupt acknowledge signal for each peripheral interrupt request to
492. terrupt service routine if the interrupt is used If an interrupt is not desired either the interrupt flag or the status bits can be polled to determine if two captures have occurred allowing the captured counter values to be read The write operation to the CAPFIFOx registers can be used as a programming advantage For example if a 01 is written into the CAPnFIFO bits the EV module is led to believe that there is already an entry in the FIFO Subsequently every time the FIFO gets a new value a capture interrupt will be generated Event Manager EV 6 79 Quaarature Encoder Pulse QEP Circuit 6 9 Quadrature Encoder Pulse QEP Circuit Each Event Manager module has a quadrature encoder pulse QEP circuit The QEP circuit decodes and counts the quadrature encoded input pulses on pins CAP1 QEP1 and CAP2 QEP2 in case of EVA or CAP4 QEP3 and CAP5 QEP4 in case of EVB The QEP circuit can be used to interface with an optical encoder to get position and speed information from a rotating machine 6 9 1 QEP Pins The two QEP input pins are shared between capture units 1 and 2 or 3 and 4 for EVB and the QEP circuit 6 9 2 QEP Circuit Time Base The time base for the QEP circuit is provided by GP timer 2 GP timer 4 in case of EVB The GP timer must be put in directional up down count mode with the QEP circuit as the clock source Figure 6 36 shows the block diagram of the QEP circuit for EVA and Figure 6 37 shows the block dia
493. the GPIO function is always chosen There are no ex ceptions as in the case of 24x where XF BIO and CLKOUT pins have a different configuration Also some pins such as XF and CLKOUT are paired with different GPIO pins compared to the 24x i e the primary function GPIO pin mapping pairing is not exactly identical to the 24x Due to the addition of two GPIO ports E and F a new MUX Control register MCRC has been added 5 3 I O Mux Control Registers There are three I O mux control registers I O mux control register A MCRA I O mux control register B MCRB and I O mux control register C MCRC 5 3 4 I O Mux Control Register A Figure 5 2 I O Mux Control Register A MCRA Address 7090h 15 14 13 12 11 10 9 8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset I O Mux Control Registers Table 5 2 I O Mux Control Register A MCRA Configuration Pin Function Selected Bit Name bit MCAn 1 MCAn 0 Primary Secondary 0 MCRA 0 SCITXD IOPAO 1 MCRA 1 SCIRXD IOPA1 2 MCRA 2 XINT1 IOPA2 3 MCRA 3 CAP1 QEP1 IOPA3 4 MCRA 4 CAP2 QEP2 IOPA4 5 MCRA 5 CAP3 IOPA5 6 MCRA 6 PWM1 IOPA6 7 MCRA 7 PWM2 IOPA7 8 MCRA 8 PWM3 IOPBO 9 MCRA 9 PWM4 IOPB1 10 MCRA 10 PWM5 IOPB2 11 MCRA 11 PWM6 IOPB3 12 MCRA 12 T1PWM T1CMP IOPB4 13 MCRA 13 T2PWM T2CMP IOPB5 14 MCRA 14 TDIRA IOPB6 15 MCRA 15 TCLKINA
494. the WD reset key register clears WDCNTR and prevents a system reset However it does not clear the free running counter Figure 11 2 WD Counter Register WDCNTR Address 7023h 7 6 5 4 3 2 1 0 Tore ee R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Note R Read access 0 value after reset Bits 7 0 D7 DO Data Values These read only data bits contain the 8 bit WD counter value Writing to this register has no effect Watchdog Control Registers 11 3 2 WD Reset Key Register The WD reset key register clears the WDCNTR register when a 55h followed by an AAh is written to WDKEY Any combination of AAh and 55h is allowed but only a 55h followed by an AAh resets the counter Any other value causes a system reset Figure 11 3 WD Reset Key Register WDKEY Address 7025h RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bits 7 0 D7 DO Data Values These write only data bits contain the 8 bit WD reset key value When read the WDKEY register does not return the last key value but rather returns the contents of the WDCR register 11 3 3 WD Timer Control Register WDCR contains control bits used for watchdog configuration These include flag bits that indicate if the WD timer initiated a system reset check bits that assert a system reset if an incorrect value is written to the WDCR register and watchdog prescale select bits that select the counter overflow tap which is used to clock the WD
495. the capacity of the register used to hold that result overflow mode The mode in which an overflow in the accumulator causes the accumulator to be loaded with a preset value If the overflow is in the positive direction the accumulator is loaded with its most positive number If the overflow is in the negative direction the accumulator is filled with its most negative number OVM bit Overflow mode bit Bit 11 of status register STO enables or disables overflow mode See also overflow mode PAB See program address bus PAB PAR Program address register A register that holds the address currently being driven on the program address bus for as many cycles as it takes to complete all memory operations scheduled for the current machine cycle Glossary PC See program counter PC PCB Printed circuit board pending interrupt A maskable interrupt that has been successfully requested but is awaiting acknowledgement by the CPU pipeline A method of executing instructions in an assembly line fashion The 24x pipeline has four independent phases During a given CPU cycle four different instructions can be active each at a different stage of completion See also instruction fetch phase instruction decode phase operand fetch phase instruction execute phase PLL Phase lock loop circuit PM bits See product shift mode bits PM power down mode The mode in which the processor enters a dormant state and dissipates considerabl
496. tifier does not match the message is not stored The RMPn bit has to be reset by the CPU after reading the data CAN Controller Module 10 13 Message Objects If a second message has been received for this mailbox and the RMP bit is already set the corresponding receive message lost RML bit is set In this case the stored message is overwritten with the new data if the overwrite protection control OPC bit is cleared Otherwise the next mailboxes are checked Note For the mailbox interrupt flag MIFn bits in the CAN IFR register to be set the corresponding bits in the CAN IMR register must be enabled If polling is desired to complete transmission or reception of messages as opposed to interrupts the following bits must be used For transmission TAn bits in the TCR register J For reception RMPn bits in the RCR register 10 3 6 Handling of Remote Frames Remote frame handling can only be done with mailboxes 0 to 3 mailboxes 4 and 5 cannot handle remote frames Receiving a Remote Request 10 14 If a remote request is received the incoming message has the remote transmission request bit RTR 1 the CAN module compares the identifier to all identifiers of the mailboxes using the appropriate masks in descending order starting with the highest mailbox number In case of a matching identifier with the message object configured as a transmit mailbox and the auto answer mode bit AAM in the message set
497. time sequenced triggers to synchronize conversions EVA and EVB can independently trigger SEQ1 and SEQ2 respectively This is applicable for dual sequencer mode only Sample and hold acquisition time window has separate prescale control Calibration mode The 240x 240xA ADC is not compatible with the 24x ADC Therefore code written for the 24x ADC cannot be ported to a 240x 240xA device Features Table 7 1 Addresses of ADC Registers Address Register Name 70A0h ADCTRL1 ADC control register 1 70A1h ADCTRL2 ADC control register 2 70A2h MAXCONV Maximum conversion channels register 70A3h CHSELSEQ1 Channel select sequencing control register 1 70A4h CHSELSEQ2 Channel select sequencing control register 2 70A5h CHSELSEQ3 Channel select sequencing control register 3 70A6h CHSELSEQ4 Channel select sequencing control register 4 70A7h AUTO SEQ SR Autosequence status register 70A8h RESULTO Conversion result buffer register 0 70A9h RESULT1 Conversion result buffer register 1 70AAh RESULT2 Conversion result buffer register 2 70ABh RESULT3 Conversion result buffer register 3 70ACh RESULT4 Conversion result buffer register 4 70ADh RESULT5 Conversion result buffer register 5 70AEh RESULT6 Conversion result buffer register 6 70AFh RESULT7 Conversion result buffer register 7 70BOh RESULT8 Conversion result buffer register 8 70B1h RESULT9 Conversion result buffer register 9 70B2h RESULT10 Conversion result buffer register 10 70B3h RESULT1
498. tion If the software goes into an improper loop or if the CPU becomes temporarily disrupted the WD timer overflows to assert a system reset Most conditions that temporarily disrupt chip operation and inhibit proper CPU function can be cleared and reset by the watchdog function By its consistent performance the watchdog increases the reliability of the CPU thus ensuring system integrity All registers in this peripheral are eight bits in width and are attached to the lower byte of the peripheral data bus of the 16 bit CPU The only difference between the 240xA WD timer and that of the C240 is the lack of real time interrupt capability This implementation of the WD timer generates its own watchdog clock locally by dividing down the CLKOUT from CPU Topic Page 11 1 Watchdog Timer Features rnm ana aaa 11 2 Watchdog Timer Operations 11 3 Watchdog Control Registers Watchdog Timer Features 11 1 Watchdog Timer Features The WD module includes the following features m m Lj a 8 bit WD counter that generates a system reset upon overflow 6 bit free running counter that feeds the WD counter via the WD counter prescale A WD reset key WDKEY register that clears the WD counter when the correct combination of values are written and generates a reset if an in correct value is written to the register WD check bits that initiate a system reset if the WD timer is corrupted Automatic activation o
499. tion i e the current conversion is complete Soft Free 0 0 Immediate stop on suspend 1 0 Complete current conversion before stopping X 1 Free run continue operation regardless of suspend ACQ PS3 ACQ PSO Acquisition time window prescale bits 3 0 These bits define the ADC clock prescale factor applied to the acquisition portion of the conversion The prescale values are defined in Table 7 3 and Table 7 4 Analog to Digital Converter ADC 7 21 Register Bit Descriptions Table 7 3 ADC Clock Prescale Factors for CLK 30 MHz Source Source ACQ ACQ ACQ ACQ scaler Acquisition Time ore eres PS3 PS2 PS1 PSO divby Window 9 Q 0 0 0 0 0 1 2 X Icik 67 385 1 0 0 0 1 2 4 x Tok 385 1020 2 0 0 1 0 3 6 x Tok 702 1655 3 0 0 1 1 4 8 x Tok 1020 2290 4 0 1 0 0 5 10 x Tai 1337 2925 5 0 1 0 1 6 12 x Telk 1655 3560 6 0 1 1 0 7 14 x Tak 1972 4194 7 0 1 1 1 8 16 x Tolk 2290 4829 8 1 0 0 0 9 18 x Tolk 2607 5464 9 1 0 0 1 10 20 x Tolk 2925 6099 A 1 0 1 0 11 22 x Tok 3242 6734 B 1 0 1 1 12 24 x Talk 3560 7369 C 1 1 0 0 13 26 X Telk 3877 8004 D 1 1 0 1 14 28 x Tg 4194 8639 E 1 1 1 0 15 30 x Talk 4512 9274 F 1 1 1 1 16 32 x Tolk 4829 9909 Notes 1 Period of Tcik is dependent on the Conversion Clock Prescale bit Bit 7 i e CPS 0 Telk 1 CLK example for CLK 30 MHz Telk 33 ns CPS 1 Telk 2 x 1 CLK example for CLK 30 MHz Telk 66 ns 2 Source impedance Z is a design estimate only Register Bi
500. tion of an INTR NMI or TRAP instruction software stack A program control feature that allows you to extend the hardware stack into data memory with the PSHD and POPD instructions The stack can be directly stored and recovered from data memory one word at time This feature is useful for deep subroutine nesting or protec tion against stack overflow STO and ST1 See status registers STO and ST1 stack A block of memory reserved for storing return addresses for subrou tines and interrupt service routines The 24x stack is 16 bits wide and eight levels deep status registers STO and ST1 Two 16 bit registers that contain bits for determining processor modes addressing pointer values and indicating various processor conditions and arithmetic logic results These regis ters can be stored into and loaded from data memory allowing the status of the machine to be saved and restored for subroutines Glossary F 13 Glossary STRB External access active strobe The 24x asserts STRB during ac cesses to external program data or I O space SXM bit See sign extension mode bit SXM TC bit Test control flag bit Bit 11 of status register ST1 stores the results of test operations done in the central arithmetic logic unit CALU or the auxiliary register arithmetic unit ARAU The TC bit can be tested by conditional instructions temporary register TREG A 16 bit register that holds one of the oper ands for a multiply operati
501. tion of one device clock cycle Minimum PWM pulsewidth and pulsewidth increment decrement of one clock cycle 16 bit maximum PWM resolution On the fly change of PWM carrier frequency double buffered period reg isters On the fly change of PWM pulsewidths double buffered compare regis ters Power Drive Protection Interrupt Programmable generation of asymmetric symmetric and space vector PWM waveforms Minimum CPU overhead because of the auto reloading of the compare and period registers Event Manager EV 6 49 PWM Circuits Associated With Compare Units 6 5 2 Programmable Dead Band Dead Time Unit EVA and EVB have their own programmable dead band units DBTCONA and DBTCONB respectively The programmable dead band unit features One 16 bit dead band control register DBTCONx RW One input clock prescaler x 1 x 2 x 4 etc to x 32 Device CPU clock input Three 4 bit down counting timers Control logic Dead Band Timer Control Registers A and B DBTCONA and DBTCONB The operation of the dead band unit is controlled by the dead band timer control registers DBTCONA and DBTCONB The bit description of DBTCONA is given in Figure 6 21 and that of DBTCONB is given in Figure 6 22 Figure 6 21 Dead Band Timer Control Register A DBTCONA Address xx15h 15 12 11 10 9 8 R 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R 0 Note R Read access W Write access 0
502. to 32 bit left barrel shifter that shifts incoming 16 bit data from 0 to 16 positions left relative to the 32 bit output Glossary instruction decode phase The second phase of the pipeline the phase in which the instruction is decoded See also pipeline instruction fetch phase operand fetch phase instruction execute phase instruction execute phase The fourth phase of the pipeline the phase in which the instruction is executed See also pipeline instruction fetch phase instruction decode phase operand fetch phase instruction fetch phase The first phase of the pipeline the phase in which the instruction is fetched from program memory See also pipeline instruction decode phase operand fetch phase instruction execute phase instruction register IR A 16 bit register that contains the instruction being executed instruction word A 16 bit value representing all or half of an instruction An instruction that is fully represented by 16 bits uses one instruction word An instruction that must be represented by 32 bits uses two instruction words the second word is a constant internal interrupt A hardware interrupt caused by an on chip peripheral interrupt A signal sent to the CPU that when not masked or disabled forces the CPU into a subroutine called an interrupt service routine ISR This signal can be triggered by an external device an on chip peripheral or an instruction INTR NMI or TRAP interrupt flag r
503. tor 0 Disable RECEIVER OVERRUN Flag bit SPISTS 7 interrupts 1 Enable RECEIVER OVERRUN Flag bit SPISTS 7 interrupts Bit 3 CLOCK PHASE SPI Clock Phase Select This bit controls the phase of the SPICLK signal 0 Normal SPI clocking scheme depending on the CLOCK POLAR ITY bit SPICCR 6 1 SPICLK signal delayed by one half cycle polarity determined by the CLOCK POLARITY bit CLOCK PHASE and CLOCK POLARITY SPICCR 6 make four different clocking schemes possible see Figure 9 3 When operating with CLOCK PHASE high the SPI master or slave makes the first bit of data available after SPIDAT is written and before the first edge of the SPICLK signal regardless of which SPI mode is being used Bit 2 MASTER SLAVE SPI Network Mode Control This bit determines whether the SPI is a network master or slave During reset initialization the SPI is auto matically configured as a network slave 0 SPI configured as a slave 1 SPI configured as a master Bit 1 TALK Master Slave Transmit Enable The TALK bit can disable data trans mission master or slave by placing the serial data output in the high impedance state If this bit is disabled during a transmission the transmit shift Serial Peripheral Interface SPI 9 21 SPI Module Registers register continues to operate until the previous character is shifted out When the TALK bit is disabled the SPI is still able to receive characters and update the status flags TALK is cleare
504. tor and PLL pin names other low power management features peripheral clock enable bits system control registers Boot EN XF pin operation fast RD strobe operation watchdog clock configuration registers system configuration and interrupts control based applications 1 3 controller area network CAN abort IUE for RS n AAn 10 20 acceptance filter architecture bit configuration register 1 BCR1 bit configuration register 2 BCR2 bit configuration registers BCRn bit timing figure block diagram CAN bit timing examples 10 29 CAN data frame figure CAN error counter register CEC CAN initialization diagram CAN interrupt flag register CAN IFR 10 36 CAN interrupt mask register CAN IMR 10 38 CAN notation table power down mode CAN protocol overview data remote error and overload frames Index co configuration mode 10 3 control registers 10 SR error status register ES E 30 global status register G E 32 interrupt logic 10 35 introduction local Mir mask LAM 10 16 16 local acceptance mask register n 0 1 high word LAMn H local Pere n mask register n 0 1 low word LAMn L S addresses mailbox configuration details table mailbox configurations mailbox direction enable register MDER 10 19 mailbox layout mailbox RAM write access mailbox RAM layout mailboxes receive transmit master control register MCR 10 23 23 memory map message buffers
505. transmit data must be written in left justified form and received data read in right justified form SPI Module Registers 9 5 9 SPI Priority Control Register SPIPRI SPIPRI selects the interrupt priority level of the SPI interrupt and controls the SPI operation on the XDS emulator during program suspends such as hitting a breakpoint Figure 9 15 SPI Priority Control Register SPIPRI Address 704Fh 7 6 5 4 3 0 R d SPI SPI SUSP SPI SUSP Reserved eserved PRIORITY SOFT FREE R 0 RW RW RW 0 R 0 Note R Read access W Write access 0 value after reset Bit 7 Reserved Reads return zero writes have no effect Bit 6 SPI PRIORITY Interrupt Priority Select This bit specifies the priority level of the SPI interrupt 0 Interrupts are high priority requests 1 Interrupts are low priority requests Bits 5 4 SPI SUSP SOFT and SPI SUSP FREE bits These bits determine what oc curs when an emulation suspend occurs for example when the debugger hits a breakpoint The peripheral can continue whatever it is doing free run mode or if in stop mode it can either stop immediately or stop when the cur rent operation the current receive transmit sequence is complete Bit5 Bit4 Soft Free 0 0 Immediate stop on suspend 1 0 Complete current receive transmit sequence before stop ping X 1 Free run continue SPI operation regardless of suspend Bits 3 0 Reserved Reads return zero writes have no effect Serial Peripheral Interf
506. ts on the RX pin and goes to bus active afterwards The first message which initiates the bus activity cannot be received When WUBA is enabled the error interrupt WUIF is asserted automatically to the PIE controller which will handle it as a wake up interrupt and restart the device clocks if they are stopped After leaving the sleep mode with a wake up the PDR and PDA are cleared The CAN error counters remain unchanged Suspend Mode 10 9 Suspend Mode The suspend mode can operate in either Free mode where the CAN peripheral continues to operate regardless of the suspend signal being active or Soft mode where the CAN peripheral stops operation at the end of the current transmission Suspend mode is entered when the CPU activates the SUSPEND signal The SUSP bit in MCR determines which of the two suspend modes Free or Soft is entered When the module enters the Soft suspend mode the status bit SMA in GSR is set If the module is actually transmitting a message when the SUSPEND signal is activated the transmission is continued until a successful transmission a lost arbitration or an error condition on the CAN bus line occurs Otherwise it enters suspend mode immediately and sets the SMA bit In Free mode the peripheral ignores the suspend signal and continues to operate receiving and transmitting messages Either way the module causes no error condition on the CAN bus line When suspended in Soft mode the module do
507. ture eet eens System Control and Status Register 1 SCSR1 Address 07018h System Control and Status Register 2 SCSR2 Address 07019h Device Identification Number Register DINR Address 701Ch Peripheral Interrupt Expansion Block Diagram lt Interrupt Requests rea E a k 240xA Interrupt Response and Flow 2 ees Interrupt Flag Register IFR Address 0006h 0 ccc cece eens Interrupt Mask Register IMR Address 0004h 000 c eee ee eee Peripheral Interrupt Vector Register PIVR Address 701Eh Peripheral Interrupt Request Register 0 PIRQRO Address 7010h Peripheral Interrupt Request Register 1 PIRQR1 Address 7011h Peripheral Interrupt Request Register 2 PIRQR2 Address 7012h Peripheral Interrupt Acknowledge Register 0 PIACKRO Address 7014h Peripheral Interrupt Acknowledge Register 1 PIACKR1 Address 7015h Peripheral Interrupt Acknowledge Register 2 PIACKR2 Address 7016h External Interrupt 1 Control Register XINT1CR Address 7070h External Interrupt 2 Control Register XINT2CR Address 7071h Program Memory Map for LF2407A ssssssssseee ete ee 2407A Peripheral Memory Map 0 cece eee RII HH Data Memory Pages esser eR ER RR Rb RETE E FA n DU
508. ty features such as watchdog timer and power drive protection O O O O L The DSP controller peripheral library is continually growing and changing to suit the needs of tomorrow s embedded control marketplace Peripheral Overview 1 3 Peripheral Overview The peripheral set for the 240xA devices includes Event Manager Timers and PWM generators for digital motor control L CAN Interface Controller Area Network CAN 2 0b compatible with six mailboxes 1 A D 10 bit analog to digital converter J SPI Serial Peripheral Interface synchronous serial port SCI Serial Communications Interface asynchronous serial port univer sal asynchronous receiver and transmitter UART _ Watchdog timer J General purpose bidirectional digital O GPIO pins Note For device pinouts electrical characteristics and timing specifications of LF240x devices see the following data sheet TMS320LF2407 TMS320LF2406 TMS320LF2402 DSP Controllers Data Sheet literature number SPRSO94 For LF LC240xA devices see the following data sheets TMS320LF2407A TMS320LF2406A TMS320LF2403A TMS320LF2402A TMS320LC2406A TMS320LC2404A TMS320LC2402A DSP Controllers Data Sheet literature number SPRS145 TMS320LF2401A TMS320LC2401A DSP Controllers Data Sheet literature number SPRS161 Introduction 1 5 New Features in 240xA Devices 1 4 New Features in 240xA Devices The following new features were added in the 2
509. ty odd even selection If the PARITY ENABLE bit SCICCR 5 is set PARITY bit 6 designates odd or even parity odd or even number of bits with the value of 1 in both transmitted and received characters 0 Odd parity 1 Even parity Bit 5 PARITY ENABLE SCI parity enable This bit enables or disables the parity function If the SCI is in the address bit multiprocessor mode set using bit 3 of this register the address bit is included in the parity calculation if parity is enabled For characters of less than eight bits the remaining unused bits should be masked out of the parity calculation 0 Parity disabled no parity bit is generated during transmission or is expected during reception 1 Parity is enabled Bit 4 LOOP BACK ENA Loop Back test mode enable This bit enables the Loop Back test mode where the Tx pin is internally connected to the Rx pin 0 Loop Back test mode disabled 1 Loop Back test mode enabled Serial Communications Interface SCI 8 21 SCI Module Registers Bit 3 ADDR IDLE MODE SCI multiprocessor mode control bit This bit selects one of the multiprocessor protocols 0 Idle line mode protocol selected 1 Address bit mode protocol selected Multiprocessor communication is different from the other communication modes because it uses SLEEP and TXWAKE functions bits SCICTL1 2 and SCICTL1 3 respectively The idle line mode is usually used for normal communications because the address bit mode adds an extra b
510. ud Rate Register SPIBRR cece eee eee eee 9 5 5 SPI Emulation Buffer Register SPIRXEMU 000022 eee 9 5 6 SPI Serial Receive Buffer Register SPIRXBUF 9 5 7 SPI Serial Transmit Buffer Register SPITXBUF 9 5 8 SPI Serial Data Register SPIDAT 0c cece eee eee ee Contents 10 11 xiv 9 5 9 SPI Priority Control Register SPIPRI 00 cece eee eee eee 9 29 9 6 SPlI Example Waveforims 3 z s s 8 Bled 48 u aee a rev das a yv eee aed Beda da 9 30 CAN Controller Module lt lt lt lt lt lt eee eee eee eee Describes the CAN controller module interface signals CAN peripheral registers and mailbox RAM layout and operations 10 1 Introduction i22 poddan d en ee RE ob deta deed beeen ER eas 10 2 Overview of the CAN Network 0 000 c cece hn 10 2 1 CAN Protocol Overview sssssssessss eet ene eees 10 2 2 CAN Controller Architecture nene 10 2 3 Memory Map 14 2i eum ehem edm eR tm eR eee i 10 3 Message Objects 20 cece ete nent eens 10 3 1 Mailbox Layout lsssssssssssssse III n E a 10 3 2 Message Buffers 2 0 0 nne 10 3 3 Write Access to Mailbox RAM lt ences 10 34 Transmit Mailbox 5 verde Edu rE APINE INEEN REPIS ERA 10 3 5 Receive Mailbox me 10 3 6 Handling of Remote Frames 0 cece eee nes 10 3 7 Mailbox Configurations nsii tesis ia iri taiias duaia a aiden es 10 3 8 Acceptance Filter
511. ug capabilities when secure mode is used No Once the device is unsecured the CSM has no impact on debug capabilities Are all of the Real Time capabilities still available Yes CSM does not impact the Real Time capabilities Does the addition of Secure Mode require any modifications to the Application Code itself The only requirement is the presence of passwords in the PWL E 16 CSM Frequently Asked Questions Are there any bad practices which should be avoided which compromise security Please refer to section E 5 DOs and DON Ts to Protect Security Logic of this reference guide In mass production can the Flash be programmed and made secure in ONE fast operation There is no special operation needed to secure a device other than ensuring the presence of passwords in the PWL Do the BLPD and TBLR instructions still work when in secure mode If so what pre vents a Trojan Horse program attached to the external bus from copying from Pro gram to Data space then allowing data space to be copied to the UART or being vis ible via JTAG No BLPD and TBLR do not work when the device is in secure mode Using the external bus implies Microprocessor mode The device is secured in MP mode The device will also be secured immediately when the JTAG connector is connected Flash ROM Code Security For LF LC240xA DSP Devices E 17 Appendix F Glossary A0 A15 Collectively the external address bu
512. umber Register Register Address 7050h sciccm STOP opo PARTY Back Stl Sel ME a BITS PARITY ENABLE ENA CHAR2 CHAR1 CHARO control RX ERR SW SCI control 7051h SCICTL1 Reserved INT ENA RESET TXWAKE SLEEP TXENA RXENA registerd BAUD15 Baud rate 7052h SCIHBAUD MSB BAUD14 BAUD13 BAUD12 BAUD11 BAUD10 BAUD9 BAUD8 MSbyte BAUDO Baud rate 7053h SCILBAUD BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 LSB LSbyte TX RX BK TX SCI control M SCICTL2 TXRDY EMPTY FEIRET INT ENA INTENA register 2 RX Receiver 7056h SCIRXEMU ERXDT7 ERXDT6 ERXDT5 ERXDT4 ERXDT3 ERXDT2 ERXDT1 ERXDTO muse Receiver 7057h SCIRXBUF RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDTO data buffer Transmitter data buffer 7059h SCITXBUF TXDT7 TXDT7 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDTO Ed Reserved me NN CS se ee mem Rem 00 ey SCITX SCIRX SCI SCI Priority 8 20 SCI Module Registers 8 7 4 SCI Communication Control Register SCICCR SCICCR defines the character format protocol and communications mode used by the SCI Figure 8 10 SCI Communication Control Register SCICCH Address 7050h 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read access W Write access 0 value after reset Bit 7 STOP BITS SCI number of stop bits This bit specifies the number of stop bits transmitted The receiver checks for only one stop bit 0 One stop bit 1 Two stop bits Bit 6 PARITY SCI pari
513. unication modes SCI data frame formats typical fae Curs A interface programming using SCICCR SCI RX signals in communication modes ne block nagram igure SCI module registers address table baud select LSbyte register g SCILBAUD baud select MSbyte register sample ISR code SCIHBAUD SCI serial communications interface 8 1 emulation data buffer register address bit multiprocessor mode SCIRXEMU communication format overview sending an address receiver data buffer register architecture SCIRXBUF asynchronous communication format receiver data buffer registers SCIRXEMU baud rate calculations SCIRXBUF asynchronous baud register values for receiver status register SCIRXST common SCI bit rates bit associations Index 18 SCI communication control register SCICCR SCI control register 1 SCICTL1 SCI control register 2 SCICTL2 SCI priority control register SCIPRI transmit data buffer register SCITXBUF SCI physical description error detection flags half or full duplex operation VO pins non return to zero format 8 3 programmable bit rates programmable data word length programmable number of stop bits receive and transmit functions separate enable bits for TX and RX interupts separate error interrupts for multiple error conditions serial clock internally generated transmitter and receiver operation wake up multiprocessor modes SCSR1 system control and status register 1 2
514. unted down to zero the timer reloads its counter with the value in the period register and starts counting down again The initial value of the timer can be any value between 0000h to FFFFh When the initial value of the timer counter is greater than that of the period register the timer counts up to FFFFh before resetting itself to zero and counting up to the period If TDIRA B is low when the timer starts with a value greater than the period register it counts down to the value of the period register and continues counting down to zero at which point the timer counter gets reloaded with the value from the period register as normal The period underflow and overflow interrupt flags interrupts and associated actions are generated on respective events in the same manner as they are generated in the continuous up counting mode The latency from a change of TDIRA B to a change of counting direction is one clock cycle after the end of the current count that is after the end of the current prescale counter period General Purpose GP Timers The direction of counting is indicated for the timer in this mode by the corresponding direction indication bit in GPTCONA B 1 means counting up 0 means counting down Either the external clock from the TCLKINA B pin or the internal device clock can be used as the input clock for the timer in this mode Figure 6 8 shows the directional up down counting mode of the GP timers Figure 6 8 GP Time
515. uous Up Counting mode Directional Up Down Counting mode Continuous Up Down Counting mode The bit pattern in the corresponding timer control register TXCON determines the counting mode of a GP timer The timer enabling bit TxCON 6 enables or disables the counting operation of a timer When the timer is disabled the counting operation of the timer stops and the prescaler of the timer is reset to x 1 When the timer is enabled the timer starts counting according to the counting mode specified by other bits of TXCON In this mode the GP timer stops and holds at its current state The timer counter the compare output and the prescale counter all remain unchanged in this mode Continuous Up Counting Mode The GP timer in this mode counts up according to the scaled input clock until the value of the timer counter matches that of the period register On the next rising edge of the input clock after the match the GP timer resets to zero and starts counting up again The period interrupt flag of the timer is set one clock cycle after the match between the timer counter and period register A peripheral interrupt request is generated if the flag is not masked An ADC start is sent to the ADC module at the same time the flag is set if the period interrupt of this timer has been selected by the appropriate bits in GPTCONA B to start the ADC General Purpose GP Timers One clock cycle after the GP timer becomes 0 the underflow i
516. upt group caused the interrupt Since the PIVR value is unique it can be used to branch to the interrupt service routine specific to this interrupt condition m Level 2 SISR This level is optional and could reside as a part of lev el 1 However at this stage the interrupt software has explicit respon sibility to avoid improper interrupt response After executing the inter rupt specific code the routine should clear the interrupt flag in the EVxIFRA EVxIFRB or EVxIFRC that caused the serviced interrupt Code will return after enabling the CPU s global interrupt bit INTM clear INTM bit Event Manager EV Register Addresses 6 2 Event Manager EV Register Addresses Table 6 3 through Table 6 10 display the addresses of the Event Manager registers Table 6 3 Addresses of EVA Timer Registers Address Register 7400h GPTCONA 7401h T1CNT 7402h T1CMPR 7403h T1PR 7404h T1CON 7405h T2CNT 7406h T2CMPR 7407h T2PR 7408h T2CON Name Timer control register Timer 1 counter register Timer 1 compare register Timer 1 Timer 1 period register Timer 1 control register Timer 2 counter register Timer 2 compare register Timer 2 Timer 2 period register Timer 2 control register Table 6 4 Adaresses of EVB Timer Registers Address Register 7500h GPTCONB 7501h T3CNT 7502h T3CMPR 7503h T3PR 7504h T3CON 7505h T4CNT 7506h T4CMPR 7507h T4PR 7508h T4CON Name Timer control register Timer 3 counter register Timer
517. ure 7 1 and Figure 7 2 respectively In both cases the ADC has the ability to autosequence a series of conversions For every conversion any one of the available 16 input channels can be selected through the analog mux After conversion the digital value of the selected channel is stored in the appropriate result register RESULTn The first result is stored in RESULTO the second result in RESULT1 and so on It is also possible to sample the same channel multiple times allowing the user to perform over sampling which gives increased resolution over traditional single sampled conversion results p Note Dual Sequencer Mode In the dual sequencer mode the SOC request from the inactive sequencer will be taken up as soon as the sequence initiated by the active sequencer is completed For example assume that the A D converter is busy catering to SEQ2 When SEQ initiates an SOC the A D converter takes up the re quest from SEQ1 after completing the sequence initiated by SEQ2 i e the SEQ1 conversion starts immediately after the current SEQ2 conversion fin ishes LLLLLLL LL L L ADC Overview Figure 7 1 Block Diagram of Autosequenced ADC in Cascaded Mode Analog MUX Result MUX ADCINO RESULTO ADCINI RESULT1 ADCIN2 10 bit RESULT2 S H A D e converter e ADCIN15 MUX Result RESULT15 select select MAX CONV1 State Ch
518. ure control register A Capture FIFO status register A Capture Capture Capture Channel 1 FIFO Channel 2 FIFO Channel 3 FIFO Top Top Top Bottom reg of capture FIFO stack 1 Bottom reg of capture FIFO stack 2 Bottom reg of capture FIFO stack 3 Group A Interrupt Mask Register Group B Interrupt Mask Register Group C Interrupt Mask Register Group A Interrupt Flag Register Group B Interrupt Flag Register Group C Interrupt Flag Register GP Timer control register B GP Timer 3 counter register GP Timer 3 compare register GP Timer 3 period register GP Timer 3 control register GP Timer 4 counter register GP Timer 4 compare register GP Timer 4 period register GP Timer 4 control register Compare control register B Full compare Action control register B Dead band timer control register B Full compare unit compare register4 Full compare unit compare register5 Full compare unit compare register6 Capture control register B Capture FIFO status register B Capture Channel 4 FIFO Top Capture Channel 5 FIFO Top Program Examples C 7 Program Examples CAP6FIFO set 7525h Capture Channel 6 FIFO Top CAPAFBOT set 7527h Bottom reg of capture FIFO stack 4 CAP5FBOT set 7527h Bottom reg of capture FIFO stack 5 CAP6FBOT set 7527h Bottom reg of capture FIFO stack 6 EVBIMRA set 752Ch Group A Interrupt Mask Register EVBIMRB set 752Dh Group B Interrupt Mask Register EVBIMRC set 752Eh Group C
519. use a bold version of the special typeface to distinguish commands that you enter from items that the system displays such as prompts command output error messages etc Here is a sample program listing 0011 0005 0001 field 1 2 0012 0005 0003 field 3 4 0013 0005 0006 field bp 3 0014 0006 even Here is an example of a system prompt and a command that you might enter C esr a user ti simuboard utilities Notational Conventions In syntax descriptions the instruction command or directive is in a bold typeface and parameters are in an italic typeface Portions of a syntax that are in bold should be entered as shown portions of a syntax that are in italics describe the type of information that should be entered Here is an example of a directive syntax asect section name address asect is the directive This directive has two parameters indicated by sec tion name and address When you use asect the first parameter must be an actual section name enclosed in double guotes the second parameter must be an address Square brackets identify an optional parameter If you use an optional parameter you specify the information within the brackets you don t enter the brackets themselves Here s an example of an instruction that has an optional parameter LACC 16 bit constant shift The LACC instruction has two parameters The first parameter 16 bit con stant is required The second parameter shif
520. vices Since the compare registers are shadowed a new value can be written to them at any time during a period For the same reason new values can be written to the action and period registers at any time during a period to change the PWM period or to force changes in the PWM output definition 6 6 4 Symmetric PWM Waveform Generation A centered or symmetric PWM signal is characterized by modulated pulses which are centered with respect to each PWM period The advantage of a symmetric PWM signal over an asymmetric PWM signal is that it has two inactive zones of the same duration at the beginning and at the end of each PWM period This symmetry has been shown to cause less harmonics than an asymmetric PWM signal in the phase currents of an AC motor such as induction and DC brushless motors when sinusoidal modulation is used Figure 6 26 shows two examples of symmetric PWM waveforms Figure 6 26 Symmetric PWM Waveform Generation With Compare Units and PWM Circuits x 1 3 or 5 aa Timer value PWM activelow Dead time PWMx 1 active high Compare matches The generation of a symmetric PWM waveform with a compare unit is similar to the generation of an asymmetric PWM waveform The only exception is that GP timer 1 or GP timer 3 now needs to be put in continuous up down counting mode PWM Waveform Generation With Compare Units and PWM Circuits There are usually two compare matches in a PWM period in symmetric P
521. w Power Management Features CLKOUT WDCLK Watchdog module All 240xA devices have a clock enable bit in the SCSR1 register to save power and selectively enable peripheral functions At reset these peripheral clock enable bits are disabled and the applications software should enable the required modules The peripheral clocks of the following peripherals can be independently enabled disabled See section 2 2 1 on page 2 3 for bit descriptions of the SCSR1 register Table 13 6 Peripheral Clock Enable Bits Peripheral SCSR1 Bits Description EVA SCSR1 2 Event Manager A EVB SCSR1 3 Event Manager B CAN SCSR1 4 Controller Area Network SPI SCSR1 5 Serial Peripheral Interface SCI SCSR1 6 Serial Communications Interface ADC SCSR1 7 Analog to Digital Converter 240xA 24x Family Compatibility 13 7 System Features 13 4 3 System Control Registers 240xA devices have two system control and status registers SCSR1 and SCSR2 see section 2 2 1 on page 2 3 These registers have control and status bits for several on chip modules These register bits should be initialized after reset to enable disable on chip functionality for the selected application 24x has only one SCSR register and all its on chip peripherals are powered up after reset The SCSR2 register is unique to 240xA and its peripherals are disabled after reset 13 4 3 1 Boot EN XF Pin Operation During the Reset phase i e RS low this pin functions as a Boot EN input pin
522. write a 1 to TXWAKE then write data to register SCITXBUF to generate an idle period of 11 data bits In address bit mode write a 1 to TXWAKE then write data to SCITXBUF to set the address bit for that frame to 1 TXWAKE is not cleared by the SW RESET bit SCICTL1 5 it is cleared by a system reset or the transfer of TXWAKE to the WUT flag Bit 2 SLEEP SCI sleep In a multiprocessor configuration this bit controls the receiver sleep function Clearing this bit brings the SCI out of the sleep mode 0 Sleep mode disabled 1 Sleep mode enabled Bit 1 Bit 0 SCI Module Registers The receiver still operates when the SLEEP bit is set however operation does not update the receiver buffer ready bit SCIRXST 6 RXRDY or the error status bits SCIRXST 5 2 BRKDT FE OE and PE unless the address byte is detected SLEEP is not cleared when the address byte is detected TXENA SCI transmitter enable Data is transmitted through the SCITXD pin only when TXENA is set If reset transmission is halted but only after all data previously written to SCITXBUF has been sent 0 Transmitter disabled 1 Transmitter enabled RXENA SCI receiver enable Data is received on the SCIRXD pin and is sent to the receiver shift register and then the receiver buffers This bit enables or disables the receiver transfer to the buffers 0 Prevent received characters from transfer into the SCIRXEMU and SCIRXBUF receiver buffers 1 Send received char
523. x n 10 20 acceptance filter 10 16 accumulator definition ACK CAN data frame 10 10 ACQ acquisition time active inactive time calculation compare operation GP timer ACTRn compare action control registers ACTRA and ACTRB ADC analog to digital converter ADC control register 1 ADCTRL1 ADC control register 2 ADCTRL2 autoconversion sequencer basic operation conversion in dual sequencer mode using SEQ1 principle of operation sequencer start stop operation with multiple time sequenced triggers example of event manager triggers to start the sequencer example of sequencer start stop operation with multiple time sequenced triggers uninterrupted autosequenced mode ES autosequence status register AUTO SEQ SR autosequenced ADC in cascaded mode block diagram autosequenced ADC with dual sequencers block diagram calibration CALIBRATION register clock prescaler ADC conversion time in 240xA ADC Index conversion clock cycles ACQ values when ACQ PS 1 2 and 3 calculating the conversion time for a multiple conversion sequence with CPS 0 and ACQ 0 calculating the conversion time for a single conversion sequence with CPS 1 and ACQ 1 conversion phases vs CLKOUT cycles conversion result buffer registers for dual sequencer mode r2 features input channel select sequencing control registers CHSELSEQn input trigger description interrupt operation during sequenced conver
524. xA family with the exception of the 2402A have two EV modules as opposed to one EV module in the 241 242 243 devices Topic Page 6 1 Event Manager EV Functional Blocks 6 2 6 2 Event Manager EV Register Addresses 6 3 General Purpose GP Timers uuuuu e 6 4 GCompareUnils er rrr exten 6 5 PWM Circuits Associated With Compare Units 6 6 PWM Waveform Generation With Compare Units and PWM Circuits nur e mrs Teen evere Ter eceleloua sale elma 6 7 Space Vector PWM RI ERE Ee E 6 8 Capture Units ELT prese ERIT 6 9 Quadrature Encoder Pulse QEP Circuit 6 10 Event Manager EV Interrupts eee 6 1 Event Manager EV Functional Blocks 6 1 Event Manager EV Functional Blocks 6 2 All devices of the 240xA family with the exception of the 2402A have two event managers EVA and EVB These two event managers are exactly identical to each other in terms of functionality and register mapping bit definition For the sake of brevity only the functionality of EVA is explained Minor differences such as naming conventions and register addresses are highlighted as appropriate Each EV module in the 240xA device contains the following functional blocks m E m m Two general purpose GP timers described in section 6 3 on page 6 14 Th
525. xes 0 5 MSGIDnH 10 10 message identifier for low word mailboxes 0 5 MSGIDnL Index message identifiers message objects CAN data frame structure figure overview of the CAN network overwrite protection control for mailbox n OPCn power down mode 10 40 receive control register RCR receive message lost for mailbox n RMLn receive message pending for mailbox n RMPn register addresses table remote frame handling remote frame pending register for mailbox n RFPn remote frame reguests figure remote requests receiving sending status registers suspend mode transmission acknowledge for mailbox n TAn 10 20 transmission control register TCR 10 20 transmission request reset for mailbox n TRRn 10 21 transmission request set for mailbox n TRSn 10 21 CAN bit timing figure 10 29 CAN bit timing examples CAN configuration mode 10 39 CAN control registers CAN initialization diagram CAN interrupt logic CAN notation CAN power down mode CAN status registers CAN suspend mode CAN IFR CAN interrupt flag register 10 36 CAN IMR CAN interrupt mask register 10 38 CAPCONA capture control register A 6 72 CAPCONB capture control register B 6 74 CAPFIFOA capture FIFO status register A CAPFIFOB capture FIFO status register B 6 77 CEC CAN error counter register CLKOUT signal definition Index 3 Index clock cycles conversion ADC analog to digital converter
526. y captured counter value goes to the bottom register In the meantime the corresponding status bits are set to 10 When the FIFO stack is read before another capture happens the older counter value in the top register is read out the newer counter value in the bottom register is pushed up into the top register and the corresponding status bits are set to 01 Capture Units The appropriate capture interrupt flag is set by the second capture A peripheral interrupt request is generated if the interrupt is not masked Third Capture If a capture happens when there are already two counter values captured in the FIFO stack the oldest counter value in the top register of the stack is pushed out and lost the counter value in the bottom register of the stack is pushed up into the top register the newly captured counter value is written into the bottom register and the status bits are set to 11 to indicate that one or more older captured counter values have been lost The appropriate capture interrupt flag is also set by the third capture A peripheral interrupt request is generated if the interrupt is not masked 6 8 5 Capture Interrupt When a capture is made by a capture unit and there is already at least one valid value in the FIFO indicated by CAPXxFIFO bits not equal to zero the corresponding interrupt flag is set and if unmasked a peripheral interrupt request is generated Thus a pair of captured counter values can be read by an in
527. y for LF LC240xA DSP devices Flash ROM code security for LF LC240xA DSP devices code security module CSM registers table DOs and DON Ts to protect security logic DON Ts DOs environments that require security unlocking password match flow flowchart features functional description Index programming considerations devices with code security devices without code security security mode table technical definitions frames CAN protocol acceptance filter 10 16 local acceptance mask LAM CAN data frame structure figure CAN data frame figure data remote error and overload frame contents handling of remote frames remote frame requests figure general purpose GP timers counting operation compare output in continuous up down counting mode table compare output in continuous up counting mode table continuous up down counting mode figure continuous up counting mode figure 6 24 directional up down counting mode figure stop hold mode GP timer compare and period registers double buffering GP timer compare output GP timer compare registe GP timer period register GP timer synchronization in emulation suspend individual GP timer control register TxCON interrupts overall GP timer control register GPTCONA B QEP based clock input 6 2 reset starting the A D converter with a timing event timer clock timer counting direction 6 19 timer functional blocks 6 14 timer inputs timer outputs
528. y less power than during normal opera tion This mode is initiated by the execution of an IDLE instruction During a power down mode all internal contents are maintained so that opera tion continues unaltered when the power down mode is terminated The contents of all on chip RAM also remains unchanged PRDB See program read bus PRDB PREG See product register PREG product register PREG A 32 bit register that holds the results of a multi ply operation product shifter A 32 bit shifter that performs a 0 1 or 4 bit left shift or a 6 bit right shift of the multiplier product based on the value of the product shift mode bits PM product shift mode One of four modes no shift shift left by one shift left by four or shift right by six used by the product shifter product shift mode bits PM Bits 0 and 1 of status register ST1 they iden tify which of four shift modes no shift left shift by one left shift by four or right shift by six will be used by the product shifter program address bus PAB A 16 bit internal bus that provides the addresses for program memory reads and writes program address generation logic Logic circuitry that generates the addresses for program memory reads and writes and an operand address in instructions that require two registers to address operands This circuitry can generate one address per machine cycle See also data address generation logic Glossary F 11 Glossary
529. y one slave device is selected at a time Serial Peripheral Interface SPI 9 9 SPI Interrupts 9 4 SPI Interrupts 9 4 1 SPI Interrupt Control Bits Five control bits are used to initialize the SPs interrupts SPI INT ENA bit SPICTL O SPI INT FLAG bit SPISTS 6 OVERRUN INT ENA bit SPICTL 4 L O LE L5 RECEIVER OVERRUN FLAG bit SPISTS 7 SPI PRIORITY bit SPIPRI 6 9 4 1 1 SPI INT ENA Bit SPICTL 0 When the SPI interrupt enable bit is set and an interrupt condition occurs the corresponding interrupt is asserted 0 Disable SPI interrupts 1 Enable SPI interrupts 9 4 1 2 SPI INT FLAG Bit SPISTS 6 This status flag indicates that a character has been placed in the SPI receiver buffer and is ready to be read When a complete character has been shifted into or out of SPIDAT the SPI INT FLAG bit SPISTS 6 is set and an interrupt is generated if enabled by the SPI INT ENA bit SPICTL O The interrupt flag remains set until it is cleared by one of the following events The interrupt is acknowledged this is different from the C240 Lj The CPU reads the SPIRXBUF reading the SPIRXEMU does not clear the SPI INT FLAG bit The device enters IDLE2 or HALT mode with an IDLE instruction Software clears the SPI SW RESET bit SPICCR 7 L A system reset occurs When the SPI INT FLAG bit is set a character has been placed into the SPIRXBUF and is ready to be read If the CPU does not read the c
530. ze ADC registers LDP SPLK NOP SPLK OE1h 0100000000000000b ADCTRL1 Reset ADC module 0011000000010000b ADCTRL1 Take ADC out of reset PPL 5432109876543210 15 RSVD 14 Reset 1 13 12 Soft amp Free 11 10 9 8 Acq prescalers 7 Clock prescaler 6 Cont run 1 5 Int priority Hi 0 4 Seq casc 0 dual Setup a maximum of 16 conversions Program the conversion sequence SPLK 15 MAXCONV be used for the 16 conversions CHK EOS1 LOOP GISR1 GISR2 GISR3 GISR4 GISR5 GISR6 PHANTOM SPLK SPLK SPLK SPLK SPLK NOP NOP NOP NOP BIT BCND RPT NOP RET RET RET RET RET RET RET end r 03210h CHSELSEQ1 07654h CHSELSEQ2 0BA98h CHSELSEO3 0FEDCh CHSELSEQ4 0010000000000000b LLEEEEL HEEL 5432109876543210 ADCTRL2 BIT12 CHK EOS1 TC 8 LOOP F Program Examples Setup for 16 conversions This is the seguence of channels that will Convert Channels 0 1 2 3 Convert Channels 4 5 6 7 Convert Channels 8 9 10 11 Convert Channels 12 13 14 15 ADCTRL2 Start the conversions Wait for SEQ1 Busy bit to clear If TC 1 keep looping The conversion results are now available in the RESULTSn regs Program Examples C 19 Program Examples GPIO OUT asm File name Description PROGRAM TO CHECK THE GPIO PINS OF 240xA as outputs This program writes a running pattern of 0 s t

TMS320LF/LC240xA DSP Controllers System and Peripherals RG

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