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HSP50214BVC

1. ENI z 1 5 l IN 13 0 gt 2 29 x gt i 9 DATARDY INTRRP 5TH ORDER 255 TAP LEVEL 0 TO 5 HALFBAND FILTER PROGRAMMABLE NTERPOLATE 2 2 AOUT 15 0 DETECT i DECIMATION UP 32 FIR FILTER RE SAMPLER ee BOUT 15 0 DECIMATE UP 16 FILTERS TO ui EAL uPROCESSOR E JESH INTERFACE 5 i E OEBL E ot 2 n 2 COF INTRRP FSYN COFSYNC T PROGRAMMABLE SEL 2 0 FIR FILTER CARRIER TRACKING SYMBOL TRACKING SEROUTA SOF SEROUTB SOFSYNC NCO TIMING ERROR SERCLK REFCLK DIFFERENCE SERSYNC O AGCOUT SEROE MICROPROCESSOR OUTPUT SECTION CEKIN CHIP 2 READ WRITE DISCRIMINATOR SECTION SYNCHRONIZATION SYNCOUT RD INPUT SECTION PROCCLK BIRGHETEIE MSYNCO WE LEVEL DETECT SECTION CONTROL SYNCHRONIZATION SECTION BACK END 2 0 SECTION CARRIER NCO SECTIONS ENTON 2 C 7 0 CIC HALFBAND FILTER AND FIR SECTIONS DIGITAL AGC SECTION RE SAMPLER INTERPOLATION HALFBAND SECTION SYNCHRONIZATION PONE TIMING NCO CIRCUITRY FIGURE 1 FUNCTIONAL BLOCK DIAGRAM OF THE HSP50214B PROGRAMMABLE DOWNCONVERTER S8t1c0SdSH HSP50214B Functional Description The HSP50214B Programmable Downconverter PDC is an agile digital tuner designed to meet the requirements of a wide variety of communications industry standards The PDC cont
2. The frequency control N is interpreted as two s complement because the output of the NCO is quadrature Negative frequency L O s select the upper sideband positive frequency L O s select the lower sideband The range of the NCO is fg 2 to 15 2 The frequency resolution of the NCO is 5 232 or approximately 0 015Hz when is 65 5 and is tied low 13 intersil FN4450 4 May 1 2007 HSP50214B The phase of the Carrier NCO can be shifted by adding a 10 bit phase offset to the MSB s modulo 360 of the output of the phase accumulator This phase offset control has a resolution of 0 35 and can be interpreted as two s complement from 180 to 180 x to or as binary from 0 to 360 0 to 2x The phase offset is given by bore 27 x PO 2 29 lt PO lt 29 _1 EQ 4 512 to 511 or in terms of the parameter to be programmed 10 PO INT 2 joFF 2r HEx 1 lt popp lt 7 EQ 4A where PO is the 10 bit two s complement value loaded into the Phase Offset Register Control Word 4 Bits 9 0 For example a value of 32 decimal loaded into the Phase Offset Register would produce a phase offset of 11 259 and a value of 512 would produce an offset of 1809 The phase offset is loaded via the microprocessor interface See the Microprocessor Write Section on instructions for writing Control Word 4 The most significant 18 bits from the phase adder are used as the ad
3. 2 18344 2 18344 DETECTOR TE T SERIAL 16 MSB 0 TE 13 i OUT 9 I MANTISSA c 4 I I I I 16 2 msB o0 ee LIMIT D l I 11 MANTISSA 1 I T 4 EXPONENT 1 EN UE T I 11 I LOAD I 11 m I I log UPPER LIMIT nuoc LOWERLIMITT SHES SS a a ku 4 T 2 11 we iu lt NT lt 2 I S oll S E lt I I a 11 F I I pd o INI 5 oz 20 I a lt O16 lt 21 I 20 I lt I I INI L 4 16 MANTISSA MAGNITUDE 01 XXXXXXXXXXXXXX RANGE 0 TO 2 3 RANGE 0 TO 1 ral MITER pem 8 Ys F i 5 C LIMIT WI L QFIR i SQ i SHIFTER LI RESAMPLING FIR FILTERS AND CARTESIAN TO POLAR COORDINATE CONVERTER G 1 64676 INTERPOLATING HALFBAND FILTERS FTER O SHI QAGC LIMITER AGC MULTIPLIER SHIFTER Controlled via microprocessor interface FIGURE 23 AGC BLOCK DIAGRAM Using AGC loop gain the AGC range and expected error The loop gain determines the growth rate of the sum in the detector output the gain adjustments per output sample for loop accumulator which in turn determines how quickly the the Loop Filter Section of the Digital AGC can be given by AGC gain tra
4. ACHIEVED EXCEEDED WITH CIC FILTER BYPASS PATH 500kHz 85dB Without Interpolation the CIC bypass path exceeds the HB FIR filter input sample rate and the CIC filter path will not yield the desired 85dB dynamic range band width of 500kHz FIGURE 4 STATEMENT OF THE PROBLEM 18 0 STUFF 40MHz AMHz HB FIR FILTER CLKIN 40MHz FIGURE 5 BLOCK DIAGRAM OF THE INTERPOLATION APPROACH CIC FILTER R 410 5MHz 500kHz 85dB BANDWIDTH 10 intersil FN4450 4 May 1 2007 HSP50214B sss FILTER FREQUENCY RESPONSE SSS 4 2 SSS fs 40MHz SS 5 10 lt 75 8 35 2 DETECTOR 24 BIT ERROR VALUE THRESH INPUT LEVEL FIGURE 8 PROCESSOR BASED EXTERNAL IF AGC 3MHz 3f s 4 30MHz 5f g 8 25MHz 2MHz CIC FILTER ALIAS PROFILE f g 2 20MHz e INTERPOLATE BY 8 THE INPUT DATA WITH ZERO STUFFING SAMPLE AT RATE f s THE INPUT DATA SPECTRUM SAMPLED AT RATE 15 3f s 8 15MHz 12 2 16 2 20MHz 24MHz 28MHz 32MHz 36MHz 40MHz 1MHz z lt a 2 4 tc 9 z lt z a a DECIMATE BY 10 AND CIC FILTER SAMPLE AT RATE R 8MHz f g 4 10MHz FIGURE 7 ALIAS PROFILE AND THE 85dB DYNAMIC RANGE BANDWIDTH Bi O 5MHz f s 8 5MHz INTERPOLATION SPECTRUM FIGURE 6 FN4450
5. Data Transitions The transition rate of the parallel output data is dependent on which of the three types of data is selected for the AOUT Output channel real symbols r magnitude or f frequency Q quadrature symbols phase or r magnitude are available on the BOUT output When selected as an output the Q r and outputs transition at the symbol rate The f frequency output transitions at the discriminator FIR filter output rate AOUT DIRECT PAR OUTPUT MODE DATA SOURCE gt DATARDY 16 15 2s COMPLEMENT 15 8 AOUT 15 8 MAG _ 16 UNSIGNED BINARY OUT 7 0 FREQ 16 RAM 15 8 2 s COMPLEMENT BOUT DIRECT PAR OUTPUT MODE DATA SOURCE Q 25 COMPLEMENT B 15 9 BOUT 15 8 PHAS 2 s COMPLEMENT MAG RAM 7 0 UNSIGNED BINARY RAM 15 0 DATA SOURCE FOR LSB T Controlled via microprocessor interface FIGURE 30 PARALLEL OUTPUT BLOCK DIAGRAM 32 intersil FN4450 4 May 1 2007 HSP50214B Data Ready Signal Assertion Rate Note that the BOUT data word may be at a different rate and The assertion rate of the DATARDY signal Is the data skewed in time with respect to DATARDY depending on the transition rate of the Aour output data either r f The type of data selected for output This is because of the timing time alignment of parallel data words available for output are relationships defin
6. COFSYNC SYNCIN1 WR gt FIGURE 51 OUTPUT RISE AND FALL TIMES FIGURE 52 TIMING RELATIVE TO CLKIN 60 intersil FN4450 4 May 1 2007 HSP50214B Waveforms OEAH OEAL OEBH OEBL toEBL OUTA 15 8 OUTA 7 0 OUTB 15 8 OUTB 7 0 PROCCLK t posee AGCGNSEL 055 DHS MCSYNC1 SOF SOFSYNC SYNCIN2 15 0 BOUT 15 0 DATARDY INTRRP MCSYNCO SYNCOUT SEROUTA SEROUTB I ipo OUT 00 _ MCSYNCO ipo SYNCO SERSYNC gt 50 FIGURE 54 TIMING RELATIVE TO PROCCLK RCP trop trop 5 gt 2 FIGURE 55 REFCLK 61 intersil FN4450 4 May 1 2007 HSP50214B Metric Plastic Quad Flatpack Packages MQFP PQFP lt D Q120 28x28 JEDEC MO 108DA 1 ISSUE D1 120 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 00 407 A1 0 010 0 25 2 5 2 0 125 0 144 3 17 3 67 B 0 012 0 018 0 30 0 45 6 B1 0 012 0 016 0 30 0 40 D 1 219 1 238 30 95 31 45 3 D1 1 098 1 106 27 90 28 10 4 5 E 1 219 1 238 30 95 31 45 3 E1 1 098 1 106 27 90 28410 4 5 L 0 006 0 037 0 65 0 95 120 120 7 0 032 BSC 0 80 5 0 1 94 NOTES 1 Controlling dimension MILLIMETER Converted inch dimensions
7. 1 AGC Loop 4 000 0 149 Gain 1 is selected Possible applications include 3 750 0 138 acquisition tracking no burst present burst present strong signal weak signal track hold or fast slow AGC values 3 500 0 127 3 250 0 116 The AGC loop filter consists of an accumulator with a built in CETT B WE limiting function The maximum and minimum AGC gain limits are provided to keep the gain within a specified range 2 750 0 95 and are programed by 12 bit Control Words using Equation 17 2 500 0 85 AGC Gain Limit 1 2 EQ 17 2 250 0 13 2 000 0 66 AGC Gain Limit dB 6 02 eeee 20log 1 0 0 mmmmmmmm 1 750 0 57 1 500 0 48 where m is 8 bit mantissa value between 0 and 255 and e 1 250 0 39 is the 4 bit exponent ranging from 0 to 15 Control Word 9 1 000 0 31 Bits 16 27 are used for programming the upper limit while bits 0 750 0 23 0 11 are used to program the lower threshold The ranges and 0 500 0 15 format for these limit values are shown in Tables 6A through 0 250 0 7 6C bit weightings for the AGC Loop Feedback elements 0 020 B are detailed in Table 9A FN4450 4 22 intersil 1 2007 HSP50214B TABLE 6C AGC LIMIT DATA FORMAT CONTROL WORD 9 BIT 27 26 25 24 23 22 21 20 19 18 17 16 FORMAT e e e e m m m m m m m AGC LOOP FILTER ERROR SCALING I AGC I I 1 I
8. 1 Halfband Note 3 Filter Polyphase and 23 55 23 2 39 4 9 56 2 Halfband Note 3 Filters 1 Halfband 7 55 7 7 86 2 15 72 Filter 2 Halfband 17 55H7 3 24 4 12 94 Filters NOTE 3 This frequency is set by the Resampler NCO In burst systems such as TDMA time resolution is needed for quickly identifying the optimum sample point The timing is adjusted by shifting the decimation in the DSP uP to the closest sample Use of timing error in this way may yield a faster acquisition than a phase locked loop coherent bit synchronization Finding the optimum sample point minimizes intersymbol interference Fine time resolution is needed in CDMA systems to resolve different multipath rays In CDMA systems the demands on the programmable FIR can only be relieved by the resampler interpolation halfband filters Assume the chip rate for a baseband CDMA system is 1 2288MHz and PROCCLK is limited to 55MHz Using the symmetric filter pre sum approach PROCCLK limits the programmable FIR to 110MIPS millions of instructions per second effective due to symmetry If the CDMA filter loaded into the programmable FIR Section requires an impulse response with a span of 12 chips the filter at 2x the chip rate would need 24 taps The 24 taps would translate into 59 5 1 2288 2 2 24 To get the same filtering at 8x the chip rate would require 944MIPS 1 2288 2 8 96 Direct 8x filtering can not be accomplished with the programmabl
9. 11 9 Link Following Phase The serial data word or link following the PHAS data word is selected using Table 12 Data see Output Section 8 6 Link Following The serial data word or link following the FREQ data word is selected using Table 12 Frequency Data see Output Section 5 3 Link Following AGC The serial data word or link following the AGC data word is selected using Table 12 Level Data see Output Section 2 0 Link Following Timing The serial data word or link following the TIMER data word is selected using Table 12 Error Data see Output Section CONTROL WORD 20 BUFFER RAM DIRECT PARALLEL AND DIRECT SERIAL OUTPUT CONFIGURATION SYNCHRONIZED WITH PROCCLK BIT POSITION FUNCTION DESCRIPTION 31 26 Reserved Reserved 25 Data Source for Least Output LSBytes bits 7 0 of AOUT and BOUT can provide Significant Bytes of 0 Buffer RAM Mode Output or AOUT and BOUT 1 Parallel Direct Mode Output 24 Buffered Output Mode Buffered Mode Output interfaces to either Interface 0 8 bit uP address ASEL 5 CLK uP RAM read 1 16 bit uP address SEL 2 0 CLK OEBL 23 22 AOUT Direct Parallel The data word sent by the Direct Parallel Output Mode to AOUT is Output Mode Data 00 I Data 2 s complement Source 01 Magnitude O unsigned binary 1X Frequency 2 s complement 21 20 BOUT Direct Parallel The data word sent by the Direct Parallel Output Mode to BOUT is Output Mode Data 00 Q Data 2 s complement S
10. ADDRESS e wn gt J RD lt wn BE THE THIRD INTERRUPT HAS ONLY 1 NEW DATA ENTRY INSTEAD OF 3 AT INTRRP B FALSE TRIGGERED INTERRUPT READ WRITE SEQUENCE FIGURE 44 AVOIDING FALSE INTRRP ASSERTIONS Microprocessor Write Section The Microprocessor Write Section uses an indirect addressing scheme where a 32 bit data word is first loaded in a four 8 bit byte master registers using four writes via C 7 0 The desired destination register address is then written to another address using C 7 0 Writing this address triggers a circuit that generates a pulse synchronous to clock that loads the Destination Register The sync circuits and data words are synchronized to different clocks CLKIN or PROCCLK depending on the Destination Registers A 2 0 determines the destination for the data on bus C 7 0 Table 19 shows the address map for microprocessor interface Figure 45 shows the Control Register loading sequence The data in C 7 0 and address map in A 2 0 is loaded into the PDC on the rising edge of WR and is latched into the Master Register on the rising edge of WR and A 2 0 100 Four clocks must pass before loading the next Control Word to guarantee that the data has been transferred Some registers can be loaded i e transferred from the Master Register to a Configuration Register or from a Holding Register to an active register by initiating a sync For example to load the AGC Gain the value of the
11. GAINADJ2 is the MSB See Using the Input Gain Adjust Control Signals Section PROCCLK Processing Clock PROCCLK is the clock for all processing functions following the CIC Section Processing is performed on PROCCLK s rising edge All output timing is derived from this clock This clock may be asynchronous to CLKIN AGCGNSEL AGC Gain Select This pin selects between two AGC loop gains This input is setup and held relative to PROCCLK Gain setting 1 is selected when AGCGNSEL 1 COF Carrier Offset Frequency Input This serial input pin is used to load the carrier offset frequency into the Carrier NCO see Serial Interface Section The offset may be 8 16 24 or 32 bits The setup and hold times are relative to CLKIN This input is compatible with the output of the HSP50210 Costas loop 1 COFSYNC Carrier Offset Frequency Sync This signal is asserted one CLK before the most significant bit MSB of the offset frequency word see Serial Interface Section The setup and hold times are relative to CLKIN This input is compatible with the output of the HSP50210 Costas loop 1 SOF Re Sampler Offset Frequency Input This serial input pin is used to load the offset frequency into the Re Sampler NCO see Serial Interface Section The offset may be 8 16 24 or 32 bits The setup and hold times are relative to PROCCLK This input is compatible with the output of the HSP50210 Costas loop 1 SOFSYNC Re Samp
12. R floor Taps 2 EQ 128 for complex filters where floor x PROCCLK fs amp Decimation Factor SYM and ODD are defined as in Equation 11A Use Equation 13 to calculate the maximum output sample rate for both real and complex filters FriRoUT Fsamp R EQ 13 The coefficients are 22 bits and are loaded using writes to Control Words 128 through 255 see Microprocessor Write Section For real filters the same coefficients are used by and Q paths If the filter is configured as a symmetric filter using Control Word 17 Bit 9 then coefficients are loaded starting with the center coefficient in Control Word 128 and proceeding to last coefficient in Control Word 128 n The filter symmetry type can be set to even or odd symmetric and the number of filter coefficients can be even or odd as illustrated in Figure 20 Note that complex filters can also be realized but are only allowed to be asymmetric Only the coefficients that are used need to be loaded 5 E E E E 5 5 5 CN 1 5 COEFFICIENT i COEFFICIENT NUMBER NUMBER EVEN SYMMETRIC 9 EVEN TAP FILTER ODD SYMMETRIC EVEN TAP FILTER 3 3 5 CN 1 2 co COEFFICIENT ic COEFFICIENT NUMBER NUMBER o EVEN SYMMETRIC ODD SYMMETRIC ODD TAP FILTER FILTER z 3 lt lt gt gt E E a 8 CN 1 C0 CN 1 COEFFICIENT i COEFFICIENT 5 NUMBER NUMB
13. internal SERCLK The external clock polarity of SERCLK is programmable via Control Word 20 Bit 18 A sync signal is provided for detection of the start or end of each word in the serial sequence Control Word 20 Bit 17 sets the SERSYNC signal location as either preceding the MSB typical for interfacing with microprocessors or following the LSB typical for interfacing to D A converters Control Word 20 Bit 19 sets the SERSYNC polarity as active low or high The LSB of each data word can be configured as either the true LSB data or set at a fixed logic 1 or 0 for use as a tag bit Control Word 20 Bits 0 13 set the LSB of each of the 7 types of data words that can be configured in the serial output stream Control Word 19 Bits 21 24 set the number of serial data words that will be linked to form the serial outputs Up to 7 data words can be linked to form the serial output SEROUTA and SEROUTB will have an identical number of words in the serial output streams The 16 bit magnitude phase frequency timing error AGC level and zeros data words are loaded into their respective shift registers The Magnitude and AGC Level data word are unsigned binary format with a leading zero while the remaining signals are 2 s complement format Any of the eight data sources can be selected as the first serial word for SEROUTA or SEROUTB Control Word 19 Bits 25 30 set the data type for the first serial word for SEROUTA and SER
14. resolution at the output 12 bits less than the full scale 16 bits The potential increase in the bit resolution due to processing gain of the filters can be lost without the use of the AGC Figure 23 shows the Block Diagram for the AGC Section The FIR filter data output is routed to the Resampling and Halfband filters after passing through the AGC multipliers and Shift Registers The outputs of the Interpolating Halfband filters are routed to the Cartesian to Polar coordinate converter The magnitude output of the coordinate converter is routed through the AGC error detector the AGC error scaler and into the AGC loop filter This filtered error term is used to drive the AGC multiplier and shifters completing the AGC control loop The AGC Multiplier Shifter portion of the AGC is identified in Figure 23 The gain control from the AGC loop filter is sampled when new data enters the Multiplier Shifter The limit detector detects overflow in the shifter or the multiplier and saturates the output of and Q data paths independently The shifter has a gain from 0 to 90 31dB in 6 021dB steps where 90 31dB 200910 2 when 15 The mantissa provides an additional 6dB of 0 0338dB steps where 6 0204dB 20logio 1 X 2 13 where X 219 1 Thus the AGC multiplier shifter transfer function is expressed as AGC Mult Shift Gain 2711 09275 EQ 14 where the shifter exponent has a range of 0 lt N lt 15 and X the mant
15. 24 21 Number of Serial Word This parameter determines the number of SERSYNC pulses generated It can be set from 1 to 7 If this Links in a Chain parameter matches the number of serial words that are linked together to form a serial output chain then there will be a sync pulse for every word in the serial output In applications where a processor is receiving the serial data it may be desirable to have a single SERSYNC pulse for the whole serial output chain instead of a SERSYNC for each word in the data chain The processor then parses out the various data words As an example if the and Q are chained together and a single SERSYNC pulse is generated for this serial output chain no ambiguity exists in the processor about which two data samples one from and one from Q are related 20 18 Link Following Data The serial data word or link following the data word is selected using Table 12 see Output Section 52 FN4450 4 1 2007 HSP50214B CONTROL WORD 19 SERIAL OUTPUT ORDER SYNCHRONIZED TO PROCCLK Continued BIT POSITION FUNCTION DESCRIPTION 17 15 Link Following Q Data The serial data word or link following the Q data word is selected using Table 12 see Output Section 14 12 Link Following The serial data word or link following the MAG data word is selected using Table 12 Magnitude Data see Output Section
16. 4 May 1 2007 tersil 11 HSP50214B IN 13 0 GATING INPUT THRESHOLD INTEGRATION INTERVALT START INTEGRATION MODE f CLKIN ADDR 2 0 Y TO 78 24 NNN NN Controlled via microprocessor interface OUTPUT INPUT MAGNITUDE THESHOLD ACCUMULATOR uPROC READ PORTS READ CODE A 2 0 A D 12dB 18dB 24dB 30dB 36dB 42dB 48dB 54dB 60dB 66dB 72dB 78dB FIGURE 10 INPUT THRESHOLD DETECTOR BIT WEIGHTING CONTINUOUS SINGLE FIGURE 9 The integration period counter can be set up to run continuously or to count down and stop Continuous integration counter operation lets the counter run with sampling occurring every time the counter reaches zero Because the processor samples the detector read port asynchronous to the CLKIN data can be missed unless the status bit is monitored by the processor to ensure that a sample is taken for every integration count down sequence Additionally in the HSP50214B the ability to align the start restart of the input level detector integration period with an external event is provided This allows the sync signals which are synchronized to external events to be used to align all of the gain adjustments or measurements If Control Word 27 Bit 17 is set to a logic one the SYNCIN1 signal will cause the input level detector to start restart its integration period If
17. Integrator Microprocessor Write Section CONTROL WORD 3 CARRIER NCO CENTER FREQUENCY SYNCHRONIZED TO CLKIN BIT POSITION FUNCTION DESCRIPTION 31 0 Carrier Center These bits control the frequency of the Carrier NCO The frequency range of the NCO is 5 2 where Frequency fs is the input sample rate The bits are computed by the equation fg 23 Bit 31 is the MSB This location is a holding register After loading a transfer to the active register is done by writing to Control Word 5 or by generating a SYNCIN1 with Control Word 0 Bit 20 set to 1 The Carrier NCO only updates ENI is active NOTE In the HSP50214B if the SYNCIN1 occurs when the NCO is not updating the load signal is held internal to the part until the next NCO update CONTROL WORD 4 CARRIER PHASE OFFSET SYNCHRONIZED TO CLKIN BIT POSITION FUNCTION DESCRIPTION 31 10 Reserved Reserved 9 0 Carrier Phase Offset These bits PO are used to offset the phase of the carrier NCO The bits are computed by the Equation PO 219 2n uEgx n lt lt for 10 bit 2 5 complement representation or from 0 to 2 for 10 bit offset binary representation Bit 9 is the MSB This location is a holding register After loading a transfer to the active register is done by writing to Control Word 6 or by generating a SYNCIN1 with Control Word 0 Bit 20 set to 1 The carrier NCO only updates when is acti
18. Q LINK FOLLOWING DATA T LINK FOLLOWING Q DATA f PHASE LINK FOLLOWING MAG DATA LINK FOLLOWING PHASE DATA T FREQUENCY LINK FOLLOWING FREQ DATA T TIMING ERROR LINK FOLLOWING TIMING DATA T AGC LINK FOLLOWING AGC DATA T ZERO 1 15 0 FOLLOWS 225 COMP SHIFT REG SHIFT REG FOLLOWS Q 15 0 SHIFT REG 2 s COMP SHIFT REG FOLLOWS SHIFT REG 15 0 0 UNSIGNED BINARY FOLLOWS SHIFT REG 15 0 225 COMP FOLLOWS f f 15 0 2 s COMP SHIFT REG 55 MATRIX SWITCH TE FOLLOWS TE Y nea nec SHIFT REG 15 0 SHIFT REG 2 s COMP FOLLOWS AGC SHIFT REG ase EEM aes UNSIGNED BINARY SEROUTA ZERO SHIFT REG ZZZZZZE SOURCE 6 5 4 3 2 1 0 V mx SERIAL OUTPUT SHIFT REGISTER DATA SOURCE FOR SEROUTB T SEROUTA SEROUTB l l l l SOURCE 6 5 4 3 2 1 0 PROCCLK ee SERIAL OUTPUT SHIFT REGISTER SEROUTB NUM OF SER WORD LINKS IN A CHAIN T SERIAL OUT CLOCK DIVIDER T SERIAL OUTPUT SYNC POSITION T SERIAL OUTPUT CLOCK POLARITY T SERIAL OUTPUT SYNC POLARITY T SERSYNC T Controlled via microprocessor interface t Polarity is programmable FIGURE 34 SERIAL OUTPUT FORMATTER BLOCK DIAGRAM 35 intersil FN4450 4 9 ay 1 2007 HSP50214B Serial Output Configuration Example 1 It is desired to output the data word followe
19. Select 1 Backend reset clears the timing NCO phase accumulator 19 18 Discriminator FIR 00 18 bits of delayed and subtracted optionally shifted phase Input 01 18 bits of magnitude from coordinate converter 1X 18 bits of resampler halfband filer output 17 Input Level Detector 0 No external sync control of input end detector start restart of integration period 22 Start 1 SYNCIN causes the input level detector to start restart its integration period elec 16 AGC Average 0 AGC settles to mean Control 1 AGC settles to median 15 AGC Clear Inhibit When set to zero this bit will clear the AGC loop filter accumulator SYNCIN2 assertion or a WRITE to CW25 When set to one a WRITE to CW25 will not clear the AGC loop filter accumulator 14 Input to Coordinate 0 enabled to coordinate converter Converter see bits 19 Q input to coordinate converter is zeroed 15 13 Coordinate Converter 0 The Resampler HB filter output is routed to coordinate converter Input 1 The output of 255 tap FIR is routed to coordinate converter 12 0 Reserved A fixed value 0 0010 0111 1000 0278 hex is loaded here for normal operation A fixed value 0 0010 0111 1010 027A hex is loaded here for setting the Sin Cos Generator outputs to 7FFF 56 intersil FN4450 4 May 1 2007 HSP50214B CONTROL WORDS 64 95 DISCRIMINATOR COEFFICIENT REGISTERS SYNCHRONIZED TO PROCCLK BIT P
20. The 12 bit Reference Divide parameter is set in Control Word 18 Bits 0 11 and is the preload for the counter that is clocked by the Reference clock Figure 26 details the block diagram of the timing error generation circuit The 16 bits of timing error are available both as a PDC serial output and as a processor read parameter See the Processor Read Section for more details on accessing this value TIMING NCO ACC NCO DIVIDE PROGRAMMABLE DIVIDER REFERENCE DIVIDE PROGRAMMABLE REFCLK DIVIDER Controlled via microprocessor interface FIGURE 27 TIMING ERROR GENERATION NCO DIVIDE 2 PHASE 31 28 Figure 27A illustrates an application where the Timing Error Generator is used to lock the receiver samples with a transmit data rate In this example the receive samples are at four times the transmit data rate An external loop filter is required whose frequency error output is fed into the Timing NCO This allows the loop to track out the long term drift between the receive sample rate and the transmit data clock TIMING NCO NCO DIVIDE 2 PHASE 31 28 PROGRAMMABLE DIVIDER REFERENCE DIVIDE NT PROGRAMMABLE DIVIDER TOTAL DECIMATION CIC HB FILTERS AND FIR Tx DATA CLK REFCLK TO Tx BLOCK MODULATOR T Controlled via microprocessor interface FIGURE 27A TIMING ERROR APPLICATION 29 intersil FN4450 4 May 1 2007 HSP50214B Ca
21. The PDC offers 0 012Hz resolution on tuning to the desired receive channel and excellent rejection of the portions of the band not being processed via the halfband and 255 tap programmable 22 bit coefficient FIR filter Traditional Modulation Formats AM ASK FM AND FSK The PDC has the capability to fully demodulate AM and FM modulated waveforms The PDC outputs 15 bits of amplitude or 16 bits of frequency for these modulation formats The FM discriminator has a 63 tap programmable 22 bit coefficient FIR filter for additional signal conditioning of the FM signal Digital versions of these formats ASK and FSK are also readily processed using the PDC Just as in the AM modulated case ASK signals will use 15 bit magnitude output of the Cartesian to Polar Coordinate converter Multi tone FSK can be processed several ways The frequency information out of the discriminator can be used to identify the received tone or the filter can be used to identify and power detect a specific tone of the received signal AMPS is an example of an FM application PM AND PSK The PDC provides the downconversion demodulation matched filtering and coordinate conversion required for demodulation of PM and PSK modulated waveforms These modulation formats will require external carrier and symbol timing recovery loop filters to complete the receiver design The PDC was designed to interface with the HSP50210 Digital Costas Loop to implement the carrier ph
22. The design goal for the PDC is to tune to and filter out a single 200kHz FDM channel from the FDM band passing only baseband samples onto the baseband processor at a multiple of the 270 8 KBPS bit rate 124 CHANNELS gt FREQUENCY 200kHz CHANNEL lt gt FREQUENCY FIGURE 47 RECEIVE SIGNAL FREQUENCY SPECTRUM RF IF Considerations The input frequency to the PDC is dependent on the A D converter selected the RF IF frequency the bandwidth of interest and the sample rate of the converter If the A D converter has sufficient bandwidth then undersampling techniques can be used to downconvert IF RF frequencies as part of the digitizing process using the PDC to process a lower frequency alias of the input signal For example a 70MHz IF can be sampled at 40MHz and the resulting 10MHz signal alias can be processed by the PDC to perform the desired downconversion tuning and filtering If the IF signal is less than 1 2 the sample frequency then standard oversampling techniques can be used to process the signal Of the two techniques only undersampling allows part of the down conversion function to be brought into the digital domain just through sampling assuming that a sampling frequency can be found that keeps the alias signals low and that the A D converter has the bandwidth to accept the unconverted analog signal 44 FN4450 4 May 1 2007 HSP50214B PDC Configuration For this example
23. VQ SELECTED L I DATARDY SELECTED LI WRITES TO SNAPSHOT XL X oO X R X X XA RAM FIGURE 42 RAM LOAD SEQUENCE Snap Shot Operation value programmed plus 1 If bits 11 4 11111111 then the The snapshot mode takes sets of adjacent samples at programmed intervals It is provided for tracking algorithms that do not require processing of every sample but do require sets of adjacent samples For example bit sync algorithms have narrow loop bandwidths that may not need to be updated every sample Computing the bit phase may require 4 adjacent samples at 2 times the baud rate The snapshot mode allows the processor to implement the tracking algorithms for high speed data without having to handle every data sample The interval from the start of one snapshot to the start of a second snapshot is programmed into bits 11 4 where bit 11 is the MSB of Control Word 21 The actual interval is the interval is set to 256 If sample sets are to be taken every 4 samples then bits 11 4 00000011 Figure 43 shows the relationship between the snapshot samples and the snapshot interval ADJACENT SAMPLES 52 63 64 X_65 SAMPLES 4 INTERVAL 64 FIGURE 43 SNAP SHOT SAMPLING 41 intersil FN4450 4 May 1 2007 HSP50214B The PDC begins to fill the buffer each time an interval number of samples have passed The number of sample sets the PDC writes into the buffer and is programmed into bits 3 0 of Contro
24. WITH OUTPUTS I Q AND FREQUENCY SENT TO AOUT 7 0 AND BOUT 7 0 Suppose the depth of the Buffer RAM Output Section is programmed for an INTRRP pointer depth of 4 If the output is at 4 times the baud rate the processing routine for the microprocessor may only need to read the buffer when the Buffer RAM had 4 samples since processing is usually on a baud by baud basis Figure 39 illustrates the conceptual view of the FIFO as a circular buffer with the Write address one step ahead of the Read Address Figure 40A deals with clockwise read and write address incrementing The FIFO depth is the difference between the Write and Read pointers modulo 8 Figure 40B illustrates a FIFO status of Full while Figure 40C illustrates a FIFO empty status condition Figure 40D illustrates a programmed FIFO depth of 3 and the INTRRP signal indicating that the buffer has sufficient data to be read Following some simple rules for operating the FIFO will eliminate most operational errors Rule 1 The Read and Write Pointers cannot point at the same address the circuitry will not allow this Rule 2 The FIFO is full when the Write Address Read Address 1 no more data will be written until some samples are read or the FIFO is reset Rule 3 The FIFO is empty when the Read Address Write Address 1 the circuitry will not allow the read pointer to be incremented Rule 4 You cannot write over what you have not read Rule 5 RE
25. XXXXXXXXXX 19 19 19 19 18 18 20 S 20 XXXXXXXXXX 20 20 20 20 19 19 21 S 21 XXXXXXXXXX 21 21 21 21 20 20 22 S 22 XXXXXXXXXX 22 22 22 21 21 23 S 23 XXXXXXXXXX 23 23 23 22 22 24 S 24 XXXXX Rnd Rnd Rnd 23 23 25 25 S 25 XXXXX SAT SAT SAT 24 24 26 26 26 XXXXX 25 Rnd 27 27 27 XXXXX 26 SAT 28 28 28 XXXXX 27 29 29 29 XXXXX 28 30 30 30 XXXXX 29 31 31 31 XXXXX 30 32 32 32 31 33 33 33 32 34 34 34 of Mult 35 35 35 36 36 36 x 37 37 37 x 38 38 38 x 39 39 39 x NOTES 1 SRnd Symmetric Round Rnd Round SAT Saturation 2 NBW out of the CIC filter is 0 5 x fsour If the NBWIN fs 4 and NBWOUT fsouT 2 then the processing gain for a decimation x 16 CIC should 8 9dB or 1 5 bits versus A D noise the processing gain should be 10log BWIN BWoUT 27 intersil M ay 1 2007 HSP50214B MAGNITUDE dB 0 0625 0 125 0 1875 0 25 0 3125 0 375 0 4375 0 5 FREQUENCY RELATIVE TO fs FIGURE 24 POLYPHASE RESAMPLER FILTER EXPANDED RESOLUTION PASSBAND FREQUENCY RESPONSE TABLE 10 POLYPHASE AND INTERPOLATING HALFBAND FILTER MAXIMUM CLOCKING RATES RE SAMPLER INPUT INTER OUTPUT CLOCK RATE POLATION RATE MODE CYCLES MHz RATE MHz Bypass 0 55 00 55 00 Polyphase Filter 6 55 6 9 17 9 17 Note 3 Polyphase and 13 55 13 4 23 2 8 46
26. division multiple access TDMA applications such as North American TDMA 15136 where 2 is the received band of interest for the PCS basestation the PDC offers 0 012Hz frequency resolution in downconversion in addition to o 2 0 35 matched programmable filtering capability The 4 DPSK modulation can be processed using the PDC Cartesian to Polar coordinate converter and d dt detector circuitry or by processing the samples in the DSP uP The PDC provides FN4450 4 May 1 2007 HSP50214B the ability to change the received signal gain and frequency synchronous with burst timing The synchronous gain adjustment allows the user to measure the power of the signal at the A D at the end of a burst and synchronously reload that same gain value at the arrival of the next user burst For applications other than cellular phones where the preambles are not changed the PDC frequency discriminator output can be used to obtain correlation on the preamble pattern to aid in burst acquisition TABLE 2 CELLULAR BASESTATION APPLICATIONS USING TDMA STANDARD GSM PCN 15 54 TYPE Cellular Cellular Cellular BASESTATION RX 935 960 1805 1880 824 849 BAND MHz CHANNEL BW kHz 200 200 30 TRAFFIC CHANNELS 8 16 3 VOICE MODULATION GMSK GMSK 4 DQPSK CHANNEL RATE Kbps 270 8 270 8 48 6 CONTROL GMSK GMSK 4 MODULATION DQPSK CHANNEL RATE Kbps 270 8 270 8 48 6 Several applic
27. shift counter 2 Reloads Number of Words counter 3 Reloads counter for sync for early or late 4 Reloads counter for dividing down SERCLK 5 In the HSP50214B the Control Word 25 reset signal is designed such that the front end reset is 10 CLKIN periods wide and the back end reset is 10 PROCCLK periods wide This guarantees that no enables will be caught in the pipelines 55 e FN4450 4 intersil May 1 2007 HSP50214B CONTROL WORD 26 LOAD AGC GAIN SYNCHRONIZED TO PROCCLK BIT POSITION FUNCTION DESCRIPTION 15 12 eeee AGC Exponent AGC LOAD Writing to this location generates a strobe to load the AGC loop accumulator with bits 11 5 mmmmmmm AGC Mantissa 15 5 to the master registers These bits are loaded into the MSBs of the AGC loop filter accumulator 5 0 000000 Not Used Bits 15 12 are the exponent associated with the AGC gain shifter while bits 11 5 are the mantissa associated with the AGC multiplier The weighting of the AGC mantissa is 01 mmmmmmm When considering Figure 23 the AGC Block Diagram note the mux between the Register and the Limiter in the AGC Loop filter The AGC LOAD controls the mux Normally the mux would select the limiter output When the AGC LOAD is asserted via the write command the mux selects the Write Master Registers for data input See Table 20 Figure 45 and the associated text of the data sheet for a
28. the PDC Control Word 16 Bits 2 0 identify the filter configuration Control Word 16 Bit 3 is used to bypass the polyphase re sampler filter For proper data output from the interpolation filters the data ready signal must account for the interpolation process Figure 25 illustrates the insertion of additional data ready pulses to provide sufficient pulses for the new output sample rate The Re sampler Output Pulse Delay parameter is set in Control Word 16 Bits 4 11 These bits set the delay between the output samples when interpolation is utilized Program this distance between pulses using EQ 20 11 A value of at least 5 is required to have sufficient time to update the Output Buffer Register Writing 5 samples requires 5 clock cycles A value of at least 16 is required for proper serial output from the part Conversion from 16 bit parallel to serial The value is programmed in numbers of PROCCLK s MAGNITUDE dB 50 60 70 80 on G q qK MON OM G 9 O Grom Sot 9 9 5 FREQUENCY RELATIVE TO fs FIGURE 24B POLYPHASE RESAMPLER FILTER PASS BAND FREQUENCY RESPONSE There is a 65dB limitation in SNR using the Re Sampler Filte
29. the PDC is configured as follows CLINE a hibet eR ne 39MHz Modei Gated Input Format As required by Digital Source Carrier NCO Fe As determined by Channel Freq Carrier NCO Phase Offset 0 Carrier NCO Offset Frequency Disabled CIC Fillet inicium ERE bulan RERO Enabled Decimation 18 PROCGLK 28 2 Band HB3 5 Enabled PIR Filter iones gsmtemp file fg 541 667kHz qaa Se ee ork Rand See dio patched Decimation 1 eat mw ere C ae Passband 90kHz fied ives esas Ap bee ae ae Transition Band 25kHz bd puqi Passband Atten 3dB Stop Band Atten 111 25713 a eee amu ee he FIR Order 90 TUE FIR Symmetry Even Resampling Filter 1 Enabled basis for this configuration is Sampling Rate Select a high rate PROCCLK Output Rate 1 083MHz 4x Bit Rate 8x Baud Rate CIC Filtering Primarily Rate Reduction 39 18 2 166MHz HB Filtering Flat passband with rate reduction by 4 low enough 541 66kHz for sufficient FIR Taps to be used FIR Filtering Primary shaping filter set final out of band suppression Polyphase HalfBand Filtering Interpolate by two
30. 000 0 000000000 0 000000000 C4 0 281280518 0 29309082 0 06055069 0 019245148 0 010158539 C5 0 000000000 0 499969482 0 000000000 0 000000000 0 000000000 C6 0 031303406 0 29309082 0 299453735 0 069904327 0 03055191 C7 0 000000000 0 499954224 0 000000000 0 000000000 C8 0 049036026 0 299453735 0 304092407 0 081981659 C9 0 000000000 0 000000000 0 500000000 0 000000000 C10 0 005929947 0 06055069 0 304092407 0 309417725 C11 0 000000000 0 000000000 0 500000000 C12 0 012379646 0 069904327 0 309417725 C13 0 000000000 0 000000000 0 000000000 C14 0 00130558 0 019245148 0 081981659 C15 0 000000000 0 000000000 C16 0 003810883 0 03055191 C17 0 000000000 0 000000000 C18 0 000378609 0 010158539 C19 0 000000000 C20 0 00251317 C21 0 000000000 C22 0 000347137 NOTE While Halfband filters are typically selected starting with the last stage in the filter chain to give the maximum alias free bandwidth a higher throughput rate may be obtained using other filter combinations See Application Note 9720 Calculating Maximum Processing Rates of the PDC Depending on the number of halfbands used PROCCLK must operate at a minimum rate above the input sample rate to the halfband This relationship depends on the number of multiplies for each of the halfband filter stages The filter calculations take 3 4 5 6 and 7 multiplies per input for HB1 HB2 4 and HB5 respectively If we keep the assumption that fs is the input
31. 15 0 DATARDY SEROUTA OUT 8 ns SEROUTB INTRRP PROCCLK to SYNCOUT tpo_SYNCI ns PROCCK to MCSYNCO tpo_SYNCO 5 ns PROCCLK to SERCLK SERSYNC Valid tpos 12 ns WR High twRH 15 ns WR Low twRL 8 ns RD Low 20 ns Address Setup to Read Low tas 3 ns RD LOW to Data Valid 1800 18 ns RD HIGH to Output Disable trop 10 ns Note 8 Output Enable Time toE 6 ns Output Enable Time FIFO Read Mode tOEBL 15 ns Output Disable Time top 8 ns Note 8 Output Rise Fall Time 3 ns Note 8 NOTES 7 AC tests performed with 40pF 0 2mA and 400uA Input reference level for CLK is 2 0V all other inputs 1 5V Test 3 0V Vinc 4 0V OV 8 Controlled via design or process parameters and not directly tested Characterized upon initial design and at major process or design changes 9 Setup time required to ensure action initiated by WR will be seen by a particular CLKIN 59 intersil FN4450 4 May 1 2007 HSP50214B AC Test Load Circuit DUT 51 T CL NOTE SWITCH S1 OPEN FOR AND NOTE Test head capacitance Waveforms lt lt tni 3 RD twRL twRH tas e WR A 2 0 twsa twHA twsc twHc C 0 7 C 0 7 A 0 2 tRpo gt gt FIGURE 49 TIMING RELATIVE WR FIGURE 50 TIMING RELATIVE TO RD tcp teL gt lt tcn CLKIN tps tpH IN 13 0 COF GAINADJ 2 0
32. 23 0101 210 1101 22 0110 29 1110 21 0111 28 1111 20 For example if Mj 0101 and Ej 1100 the AGC Loop Gain 0 3125 2 The loop gain mantissas and exponents are set in the AGC Loop Parameter Control Register Control Word 8 Bits 0 15 Two AGC loop gains are provided in the Programmable Down Converter for quick adjustment of the AGC loop The AGC Gain select is a control input to the device selecting Gain 0 when AGCGNSEL 0 and selecting Gain 1 when AGCGNSEL 1 In the HSP50214 a reset event caused by SYNCIN2 or CW25 would clear the AGC loop filter accumulator In the HSP50214B if Control Word 27 Bit 15 is set to zero the AGC loop filter accumulator will clear as in the original HSP50214 If Control Word 27 Bit 15 is set to one the backend reset from CW25 will not clear the AGC loop filter accumulator In the HSP50214 the settling mode of the AGC forces the mean of the signal magnitude error to zero The gain error is scaled and used to adjust the gain up or down This proportional scaling mode causes the AGC to settle to the final gain value asymptotically This AGC settling mode is preferred in many applications because the loop gain adjustments get smaller and smaller as the loop settles reducing any AM distortion caused by the AGC With this AGC settling mode the proportional gain error causes the loop to settle more slowly if the threshold is small This is because the maximum
33. 2_q Ck 2 im Xn 1 2 i Ck 2 re Xn_q CO_im Xni Qout Xn k 1 i Ck 1 Xn k 1_q Ck 1 re Xn k 2 i Ck 2 im Xn 1 2_q Ck 2 re epus Xni CO_im Xn_q 60 57 intersil E FN4450 4 wa ay 1 2007 HSP50214B Absolute Maximum Ratings Supply 7 0V Input Output or I O Voltage GND 0 5V to Voc 0 5V ESD Class 2 Operating Conditions Voltage Temperature Range 4 75V to 5 25V Comercial san Seeger 0 C to 70 C cise Sse ace Lo a erc xm keke 40 C to 85 C Input Low Voltage OV to 0 8V Input High 2V to Vcc Input Rise and Fall Time 1V ns Max Thermal Information Thermal Resistance Typical Note 4 Oya C W MQFP Package 28 Maximum Junction 150 C Maximum Storage Temperature Range 65 C to 150 C Pb free reflow profile see link below http www intersil com pbfree Pb FreeReflow asp CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device a
34. 6 HB2 Enable Setting this bit enables HB filter number 2 15 HB1 Enable Setting this bit enables HB filter number 1 14 11 FIR Decimation Load decimation from 1 16 where 0000 16 Bit 14 is the MSB 0001 1 1001 9 0010 2 1010 10 0011 3 1011 11 0100 4 1100 12 0101 5 1101 13 0110 6 1110 14 0111 7 1111 15 1000 8 0000 16 10 FIR Real Complex 0 Complex Filter 1 Dual Real Filters 9 FIR Sym Type 0 Odd Symmetry 1 Even Symmetry 8 FIR Symmetry 0 Symmetric Filters 1 Asymmetric Filters 7 0 FIR Taps Number of taps in the FIR filter Range is 1 to 255 where 0000000 is invalid CONTROL WORD 8 AGC CONFIGURATION 1 SYNCHRONIZED TO PROCCLK BIT POSITION FUNCTION DESCRIPTION 31 30 Reserved Reserved 29 Sync AGC Updates to When this bit is 1 the SYNCIN2 pin loads the contents of the master registers into the AGC accumulator SYNCIN2 28 16 Threshold The magnitude measurement out of the cartesian to polar converter is subtracted from this value to get the gain error A gain of 1 647 in the cartesian to polar conversion that must be taken into account when computing this threshold These bits are weighted 22 down to 2710 Bit 28 is the MSB 15 12 Loop Gain 1 Selected when AGCGNSEL 1 These bits MMMM together with the exponent bits EEEE 11 8 set Mantissa the loop gain for the AGC loop The gain adjustment per output sample is 1 5dB Threshold Magnitude 1 6 0 MMMM 2 19 EEEE where magnitude ranges from 0 t
35. ADDRynirg ADDRggap EQ 23 FIFO Operation Via 16 Bit Processor Interface Figure 37 shows the conceptual configuration of the 16 bit yu Processor interface This interface looks like a 16 bit pu Processor read only microprocessor interface The SEL 2 0 lines are the address bus and the OEAL and OEBL lines are the read lines The address is decoded as shown in Table 17 Use of the 16 bit interface for Buffer RAM output requires Control Word 20 Bit 25 to be set to a logic 0 and Control Word 20 Bit 24 to be set to a logic 1 Once the Control Word 20 has been set to route data to AOUT 7 0 and BOUT 7 0 then the microprocessor must place a value on the PDC input pins SEL 2 0 to choose which data type will be output on AOUT 7 0 and 6BOUT 7 0 Table 17 defines the data types in terms of SEL 2 0 With the control lines set the selected data is read MSByte on AOUT 7 0 and LSByte on BOUT 7 0 when OEAL and OEBL are low New data only read when OEBL goes low so use uP for 8 bit modes Programming SEL 2 0 110 outputs a 16 bit status signal on AOUT and BOUT The FIFO status includes FULL EMPTY FIFO Depth and READYB These status signals are defined in Table 18 OUTPUT DATA m 2 n 2 lt lt OEBL SEL 2 0 ADDRESS SEQUENCER WRITE SET OF WORDS SEQUENCER INCR INCR WR RD NEW DATA FIGURE 37 16 BIT MICROPROCESSOR INTERFACE BUFFER RAM MO
36. AGC gain is first loaded into the Holding Registers then a transfer is initiated SYNCIN2 if Control Word 8 Bit 29 1 This allows the AGC gain to be loaded by detecting a system event such as a start of a new burst Bit 20 of Control Word 0 has the same effect on the Carrier NCO center frequency for assertion of SYNCIN1 except it transfers from a dedicated holding register not the Master Register TABLE 19 DEFINITION OF ADDRESS MAP A2 0 REGISTER DESCRIPTION 0 Holding Register 0 Transfers to bits 7 0 of the 32 bit Destination Register Bit 0 is the LSB of the 32 bit register 1 Holding Register 1 Transfers to bits 15 8 of a 32 bit Destination Register 2 Holding Register 2 Transfers to bits 23 16 of a 32 bit Destination Register 3 Holding Register 3 Transfers to bits 31 24 of a 32 bit Destination Register Bit 31 is the MSB of the 32 bit register 4 Thisisthe Destination Address Register On the fourth CLK following a write to this register the contents of the Holding Registers are transferred to the Destination Register All 8 bits written to this register are decoded into the Destination Register Address The configuration destination address map is given in the tables in the Control Word Section 5 Selects data source for reading See Microprocessor Read Section Suppose a 0018D038 H needs to be loaded into Control Word 0 then Table 20 details the steps to be taken 42 i
37. AIN FROM PROCESSOR 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 DECIMATION R FIGURE 15 CIC SHIFT GAIN VALUES The decimation factor of the CIC filter is programmed in Control Word 0 Bits 12 7 The CIC Shift Gain is programmed in Control Word 0 Bits 16 13 The CIC Bypass is set in Control Word 0 Bit 6 When bypassing the CIC filter the ENI signal must be de asserted between samples i e the CLKIN rate must be gt 2 e fs TABLE 3 GAIN ADJUST CONTROL AND CIC DECIMATION AGAIN VALUE MAX CIC dB GAIN ADJ 2 0 DECIMATION 0 000 32 6 001 27 12 010 24 18 011 21 24 100 18 30 101 16 36 110 12 42 111 10 CIC Gain Calculations The gain through the CIC filter increases with increased decimation The programmable barrel shifter that precedes the first integrator in the CIC is used to offset this variation Gain variations due to decimation should be offset using the 4 bit CIC Shift Gain word This allows the input signal level to be adjusted in 6dB steps to control the CIC output level The gain at each stage of the CIC is k RN EQ 6 where R is the decimation factor and N is the number of stages The input to the CIC from the mixer is 15 bits and the bit widths of the accumulators for the five stages in the HSP50214B are 40 36 32 32 and 32 as shown in Figure 16 This limits the maximum decimation in the CIC to 32 for a full sca
38. ASE I ase ACCUMULATOR TIMING NCO PH ACC LOAD ON SCF UPDATET ENABLE SOF f TIMING FREQ SOFSYNC STROBE f SOF NUMBER OF SOF BITS T TIMING NCO CENTER FREQUENCY Controlled via microprocessor interface FIGURE 26 TIMING NCO BLOCK DIAGRAM The programmable parameters for the Timing NCO include an Enable External Timing NCO Sync Control Word 11 Bit 5 the serial word width Number of Offset Frequency Bits Control Word 11 Bits 3 4 an Enable Offset Frequency control Control Word 11 Bit 2 a Clear NCO Accumulator control Control Word 11 Bit 1 a Timing NCO Phase Accumulator Load On Update control Control Word 11 Bit 0 the Timing NCO Center Frequency Control Word 12 a Timing Phase Offset Control Word 13 Bits 0 7 a Timing Frequency Strobe Control Word 14 and a Timing Phase Strobe Control Word 15 Refer to the Carrier Synthesizer Mixer Section for a detailed discussion of the serial interface for the Timing NCO offset frequency word A timing error detector is provided for measuring the phase difference between the timing NCO and a external clock input REFCLK Timing Error is generated by comparing the values of two programmable counters One counter is clocked with the Timing NCO carry out and the other is clocked by the REFCLK The 12 bit NCO Divide parameter is set in Control Word 18 Bits 16 27 The NCO Divide parameter is the preload to the counter that is clocked by the Timing NCO carry out
39. Bits 17 and 19 set the functionality of the LSB of each data word These bits may be programmed to be either a logic 0 logic 1 or as normal data The fixed states are designed to allow the microprocessor to synchronize to the serial data stream 36 intersil FN4450 4 May 1 2007 HSP50214B CONTROL WORD 19 BITS 24 21 011 3 DATA WORDS IN EACH SERIAL OUTPUT DATA WORD 3 DATA WORD 2 DATA WORD 1 DATA WORD 3 THE REMAINING CHOICES FOR THE THIRD LINK ON SEROUTB ARE PHASE FREQUENCY AGC LEVEL AND TIMING ERROR DATA WORD 2 TBD MAGNITUDE DATA WORD 1 NOTE Once magnitude is identified to follow Q it must be that way on both serial outputs FIGURE 35 EXAMPLE 2 SERIAL OUTPUT DATA STREAM NORMAL 0 1 SERSYNC FOLLOWS LSB MODE INVERTED 0 1 2 LATE SERSYNC NORMAL 1 2 3 EARLY SERSYNC PRECEDES MSB INVERTED 1 2 LSB WORDO MSB WORD1 lt DATA SHIFT MSB FIRST LSB WORD1 SERSYNC 3 MODE MSB WORD2 MSB WORD3 LSB WORD2 FIGURE 36 VALID SERSYNC CONFIGURATION OPTIONS The serial direct output can be programmed to output less than 16 bits New output data preempts old output data so if SERSYNC is programmed to precede the MSB then data will shift out until new data comes along Note that if SERSYNC is programmed to follow the LSB then a sync will never occur Buffer RAM Output Port The
40. Buffer RAM parallel output mode utilizes a RAM to store output data for future retrieval by either the 8 bit microprocessor that is configuring the PDC or by a 16 bit baseband processing engine which could also be a microprocessor Data is output from the RAM only on request and can be obtained from either the 8 bit uP interface or from a 16 bit interface that uses the two LSBytes of AOUT and BOUT The RAM holds up to eight 80 bit sample sets Each sample set includes 16 bits of each Q magnitude phase and frequency data The RAM samples are mapped as shown in Table 16 The Buffer RAM controller supports both FIFO and Snapshot modes TABLE 16 RAM DATA STORAGE MAP RAM lri F SAMPLE DATA DATA DATA DATA DATA SET 000 001 010 011 100 0 10 15 0 Qo 15 0 Irlo 15 0 15 0 f 15 0 1 14 15 0 Q4 15 0 1 15 0 4 15 0 15 0 2 15 15 0 Qo 15 0 rlo 15 0 2 15 0 15 0 3 13 15 0 15 0 15 0 3 15 0 fa 15 0 4 14 15 0 Q4 15 0 14 15 0 4 15 0 f4 15 0 5 15 15 0 5 15 0 5 15 0 5 15 0 15 0 6 16 15 0 06 15 0 16 15 0 6 15 0 15 0 7 15 15 0 Qz 15 0 17 15 0 7 15 0 5 15 0 NOTE l and Q are sample aligned time r and sample aligned in time but one sample delayed from I The frequency sample is delayed in time from or Q by 1 sample ti
41. Control Word 27 Bit 17 is set to a logic zero control of the start restart of the input level detector integration period does not respond to SYNCIN1 In the count down and stop mode the microprocessor read commands can be synchronized to system events such as the start of a burst for a TDMA application The integration counter can be started at any time by writing to Control Word 2 At the end of the integration period counter 0000 the upper 23 bits of the accumulator are transferred to a holding register for reading by the microprocessor Note that it is not the restarting of the counter by writing to Control Word 2 that latches the current value but the end of the integration count When the accumulator results are latched a bit is set in the Status Register to notify the processor Reading the most significant byte of the 23 bits clears the status bit See the Microprocessor Read Section Figure 11 illustrates a typical AGC detection process 12 intersil FN4450 4 May 1 2007 HSP50214B Typically the average input error is read from the Input Level Detector port for use in AGC Applications By setting the threshold to 0 however the average value of the input signal can be read directly The calculation is dBFSpyg 20 log 1 111 level N 16 EQ 2 where level is the 24 bit value read from the 3 level Detector Registers and is the number of samples to be integrated Note that to get th
42. D 12 TIMING NCO CENTER FREQUENCY SYNCHRONIZED TO PROCCLK BIT POSITION FUNCTION DESCRIPTION 31 0 Timing NCO Center These bits control the frequency of the timing NCO The frequency range of the NCO is from 0 to Frequency FnEsAMP where Fresawp is the sample rate to the resampling filter The bits are computed by the equation foyt FRESAMP 232 Bit 31 is the MSB This location is a holding register After loading a transfer to the Active Register is done by writing to Control Word 14 or by generating a SYNCIN2 with Control Word 11 Bit 5 set to 1 50 intersil FN4450 4 May 1 2007 HSP50214B CONTROL WORD 13 TIMING PHASE OFFSET SYNCHRONIZED TO PROCCLK BIT POSITION FUNCTION DESCRIPTION 31 8 Reserved Reserved 7 0 Timing NCO Phase These bits are used to offset the phase of the Timing NCO The range is 0 to 1 times the resampler input Offset period interpreted either as T 2 2 s complement or 0 to T offset binary Bit 7 is the MSB This location is a holding register After loading a transfer to the Active Register is done by writing to Control Word 15 or by generating a SYNCIN2 with Control Word 11 Bit 5 set to 1 CONTROL WORD 14 TIMING FREQUENCY STROBE SYNCHRONIZED PROCCLK BIT POSITION FUNCTION DESCRIPTION N A Timing Frequency Writing to this address updates the active timing NCO Frequency Register in the timing NCO see Timing Strobe NCO Section CONTRO
43. DE BLOCK DIAGRAM PROCCLK TABLE 17 BUFFER RAM OUTPUT SELECT DEFINITIONS SEL 2 0 OUTPUT DATA TYPE 000 Data 001 Q Data 010 Magnitude 011 Phase 100 Frequency 101 Unused 110 Memory Status 111 Reading this address increments to the next sample set TABLE 18 STATUS BIT DEFINITIONS AOUT BIT LOCATION INFORMATION 7 5 FIFO depth When in FIFO mode these bits are the current depth of the FIFO 4 EMPTY When in FIFO mode the FIFO is empty and the read pointer cannot be advanced Active High 3 FULL When in FIFO mode the FIFO is full and new samples will not be written Active High 2 READYB When in FIFO mode the output buffer has reached the programmed threshold In the snapshot mode the programmed number of samples have been taken Active Low 1 0 GND NOTE In the Status output BOUT 7 0 are all GND 38 intersil FN4450 4 May 1 2007 HSP50214B Figure 37 shows the interface between a 16 bit microprocessor or other baseband processing engine and the Buffer RAM Output Section of the Programmable Down Converter configured for data output via the parallel outputs AOUT and BOUT In the 16 bit microprocessor interface configuration the Buffer RAM pointer is incremented when the uProcessor reads address SEL 2 0 7 OEBL 0 After reset the FIFO must be incremented to read the first sample set This is because the RAM re
44. DJO 22 BOUT5 23 GND COFSYNC L 24 BOUT4 GND 25 NC SOF 26 BOUT3 SOFSYNC 27 BOUT2 Vec 28 BOUT1 SYNCIN1 29 BOUTO SYNCIN2 30 OEBL SYNCOUT 31 1 1 32 GND 50 SEL2 51 SEL1 52 SELO 53 GND 54 SEROUTA 55 SEROUTB 56 SERSYNC 57 SEROE 58 SERCLK 59 Vcc 60 3 intersil FN4450 4 May 1 2007 HSP50214B Pin Descriptions NAME DESCRIPTION Positive Power Supply Voltage GND Ground CLKIN Input Clock This clock should be a multiple of the input sample rate All input section processing occurs on the rising edge of CLKIN The frequency of CLKIN is designated IN 13 0 Input Data The format of the input data may be set to offset binary or 2 s complement IN13 is the MSB see Control Word 0 ENI Input Enable Active Low This pin enables the input to the part in one of two modes gated or interpolated see Control Word 0 In gated mode one sample is taken per CLKIN when ENI is asserted The input sample rate is designated fs which can be different from fci when is used GAINADJ 2 0 GAINAD Input Adds an offset to the gain via the shifter following the mixer GAINADJ value is added to the shift code from the microprocessor uP interface The shift code is saturated to a maximum code of F The gain is offset by 60B GAINADJ 000 0dB gain adjust 111 42dB gain adjust
45. ER o o ASYMMETRIC ASYMMETRIC EVEN TAP FILTER ODD TAP FILTER REAL FILTERS Ca CQo N 1 COEFFICIENT NUMBER Ci N 1 IMAGINARY COEFFICIENT VALUE Cio R EAL COEFFICIENT VALUE COMPLEX FILTERS Definitions Even Symmetric h n h N n 1 for n 0 to N 1 Odd Symmetric h n h N n 1 for n 0 to N 1 Asymmetric A filter with no coefficient symmetry Even Tap filter filter where is an even number Odd Tap filter filter where is odd number Real Filter A filter implemented with real coefficients Complex Filters A filter with quadrature coefficients FIGURE 20 DEMONSTRATION OF DIFFERENT TYPES OF DIGITAL FIR FILTERS CONFIGURED IN THE PROGRAMMABLE DOWNCONVERTER Automatic Gain Control AGC The AGC Section provides gain to small signals after the large signals and out of band noise have been filtered out to ensure that small signals have sufficient bit resolution in the Resampling Interpolating Halfband filters and the Output Formatter The AGC can also be used to manually set the gain The AGC optimizes the bit resolution for a variety of input amplitude signal levels The AGC loop automatically adds gain to bring small signals from the lower bits of the 26 bit programmable FIR filter output into the 16 bit range of the 20 intersil FN4450 4 May 1 2007 HSP50214B output section Without gain control a signal at 72dBFS 201090 2712 at the input would have only 4 bits of
46. Enabled 100 Not Valid 101 Not Valid 110 Both Halfband Filters Enabled 111 Re Sampler and Both Halfband Filters Enabled 51 intersil FN4450 4 May 1 2007 HSP50214B CONTROL WORD 17 DISCRIMINATOR FILTER CONTROL DISCRIMINATOR DELAY SYNCHRONIZED TO PROCCLK BIT POSITION FUNCTION DESCRIPTION 31 17 Reserved Reserved 16 15 Phase Multiplier These bits program allow the phase output of the cartesian to polar converter to be multiplied by 1 2 4 or 8 modulo 27 to remove phase modulation before the frequency is measured 00 No Shift on Phase Input to frequency discriminator 01 Shift Phase Input to frequency discriminator up 1 one bit discarding the MSB and zero filling the LSB 10 Shift Phase Input to frequency discriminator up 2 two bits discarding the MSB and zero filling the LSB 11 Shift Phase Input to frequency discriminator up 3 three bits discarding the MSB and zero filling the LSB 14 Discriminator Enable 0 Disable Discriminator 1 Enable Discriminator 13 11 Discriminator FIR The decimation can be programmed from 1 to 8 where 000 decimate by 8 001 decimate by 1 010 Decimation decimate by 2 011 decimate by 3 100 decimate by 4 101 decimate by 5 110 decimate by 6 and 111 decimate by 7 10 FIR Symmetry Type 0 Odd Symmetry 1 Even Symmetry 9 FIR Symmetry 0 Symmetric 1 Asymmetric 8 3 Number of FIR Tap
47. G ground 0 2 1 64676 42 1 1 5dB 3 275dB output sample time 2 1 64676 2 1 1 5dB 0 000106dB output sample time Thus the expected range for the AGC rate is 0 000106 to 3 275dB output sample time 26 FN4450 4 intersil May 1 2007 HSP50214B TABLE 9B PDC BIT WEIGHTING BIT CIC IN CIC IN WERGHIS HB DATA FIR Sp FIR WEIGHT INPUT SIN COS MIXOUT SHIFT 0 SHIFT 15 CIC OUT HBDATAIN OUT FIR IN COEF ACC OUT o s 85 xxx 1 1 1 1 5 XXXXXXXXXX 1 1 1 1 0 0 2 2 2 2 5 5 XXXXXXXXXX 2 2 2 2 1 1 3 3 3 3 5 5 XXXXXXXXXX 3 3 3 3 2 2 4 4 4 4 5 5 XXXXXXXXXX 4 4 4 4 3 3 5 5 5 5 5 5 XXXXXXXXXX 5 5 5 5 4 4 6 6 6 6 S S XXXXXXXXXX 6 6 6 6 5 5 7 7 7 7 S S XXXXXXXXXX 7 7 7 7 6 6 8 8 8 8 5 5 XXXXXXXXXX 8 8 8 8 7 7 9 9 9 9 5 5 XXXXXXXXXX 9 9 9 9 8 8 10 10 10 10 5 10 5 XXXXXXXXXX 10 10 10 10 9 9 11 11 11 11 S 11 XXXXXXXXXX 11 11 11 11 10 10 12 12 12 12 S 12 XXXXXXXXXX 12 12 12 12 11 11 13 13 13 13 S 13 XXXXXXXXXX 13 13 13 13 12 12 14 14 14 S 14 XXXXXXXXXX 14 14 14 14 13 13 15 15 SRnd 5 15 XXXXXXXXXX 15 15 15 15 14 14 16 16 5 16 XXXXXXXXXX 16 16 16 16 15 15 17 17 S 17 XXXXXXXXXX 17 17 17 17 16 16 18 S 18 XXXXXXXXXX 18 18 18 18 17 17 19 S 19
48. J 2 0 CONTROL WORD 0 INPUT LEVEL DETECTOR STATUS 0 t INPUT THRESH f INTG MODE t INTG INTEVAL INPUT MODE f programmed via the microprocessor interface as shown in Figure 9 The bit weighting of the data path through the input threshold detector is shown in Figure 10 The threshold is a signed number so it should be set to the inverse of the desired input level The threshold can be set to zero if the average input level is desired instead of the error The sum of the threshold and the absolute value of the input is accumulated in a 32 bit accumulator The accumulator can handle up to 218 samples without overflow The integration time is controlled by an 18 bit counter The integration counter preload ICPrel is programmed via the microprocessor interface through Control Word 1 Only the upper 16 bits are programmable The 2 LSBs are always zero Control Word 1 Bits 29 14 are programmed to ICPrel N 44 1 EQ 1 where N is the desired integration period defined as the number of input samples to be integrated N must be a multiple of 4 0 4 8 12 16 218 BYPASS T CONTROL WORD 1 CONTROL Sees T LOGIC INPUT THRESHT T Controlled via microprocessor interface INTG_MODE CLKIN INTG INTEVAL 1 tt See NCO Section for more details FIGURE 3 BLOCK DIAGRAM OF THE INPUT SECTION BYPASS cic FILTER MIN R 4 CLKIN 5MHz PROCCLK 28MHz HB FIR FILTER BANDWIDTH MAX fs
49. Ks after the Buffer RAM pointer has been incremented Control Word 22 is used to reset the Read and Write pointers of the Buffer RAM output to the first sample to 000 and 007 for write and read respectively 40 intersil FN4450 4 May 1 2007 HSP50214B DATA INPUT n 2 lt lt SET OF WORDS R1 RO A1 ADDRESS SEQUENCER 5 INCR INCR WR RD NEW DATA CONTROL WORD 23 A 2 0 0 1 Q 225 COMP 1 r O UNSIGNED BINARY 275 COMP 2 f 2 s COMPLEMENT 4 INPUT AGC UNSIGNED BINARY 5 AGC TIMING UNSIGNED BINARY 2 s COMP 2 1 0 R2 R1 RO 2 Al AO SELECTION 0 0 O RAMILSB MSB QLSB RAM r LSB RAM r MSB LSB RAM MSB RAM f LSB RAM MSB NOT USED INPUT INTEG LSB INPUT INTEG NMSB INPUT INTEG MSB AGC LSB AGC MSB TIMING LSB TIMING MSB NOT USED STATUS OUTPUT DATA x O O O O O O O O O x O O O O O x lt O O O O X O O O O O O O x lt O O 0 04 FIGURE 41 8 BIT MICROPROCESSOR INTERFACE BUFFER RAM MODE BLOCK DIAGRAM PRoccuik LJ LJ LI LI LJ LJ LJ LJ LI LI LI Li X DELAY DATARDY DEPENDS ON LENGTH OF FIR IF FREQ CHOSEN DATARDY
50. L WORD 15 TIMING PHASE STROBE SYNCHRONIZED TO PROCCLK BIT POSITION FUNCTION DESCRIPTION N A Timing Phase Strobe Writing to this address updates the active timing NCO Phase Offset Register in the timing NCO see Timing NCO Section CONTROL WORD 16 RESAMPLING FILTER CONTROL SYNCHRONIZED TO PROCCLK BIT POSITION FUNCTION DESCRIPTION 31 12 Reserved Reserved 11 4 Re Sampler Output NOTE These bits program the delay between output samples when interpolating The extra outputs can Pulse Delay be delayed from 2 to 255 clocks from the first output A delay of 2 equals 255 clocks of delay A delay of 0 or 1 is an invalid mode When interpolating by 2 one extra output is generated when interpolating by 4 extra outputs are generated Program by the equation PROCCLK fgyr 1 Bit 11 is the MSB NOTE If less than 5 is programmed there will not be sufficient time to fully update the output buffer If less than 16 is programmed the serial output may be preempted This means that it won t finish and if the sync is programmed to follow the data there may never be a sync 3 Re Sampler Bypass 0 Resampling Filter Enabled A valid combination of bits 2 0 must also be selected 1 Resampling Filter Section including Interpolation halfband filters is bypassed 2 0 Filter Mode Select 000 Not Valid 2 HB2 Enabled 1 HB1 Enabled 0 Re Sampler Enabled 001 Re Sampler Enabled 010 Halfband 1 Enabled 011 Re Sampler and Halfband Filter 1
51. ORD 1 INPUT LEVEL DETECTOR SYNCHRONOUS TO CLKIN BIT POSITION FUNCTION DESCRIPTION 31 Reserved Reserved 30 Integration Mode 0 Integration of magnitude error stops when the interval counter times out 1 Integration runs continuously When the interval counter times out the integrator reloads and the results of the integration is sent to a register for the processor to read 29 14 Integration Interval These are the top 16 bits of the 18 bit integration counter ICPrel ICPrel N 4 1 where is the desired integration period in CLKIN cycles defined as the number of input samples to be integrated N must be a multiple of 4 0 4 8 12 16 218 Bit 29 is the MSB If the input is interpolated then the zeros must be accounted for as they will be added to the threshold If the gated input mode is used the same input sample will be accumulated multiple times 13 0 Input Threshold Input Magnitude Threshold Bits 12 0 correspond to input bits 12 0 The magnitude of the input is added to this threshold where the threshold is a signed number Bit 13 is the MSB CONTROL WORD 2 INPUT LEVEL DETECTOR START STROBE SYNCHRONIZED TO CLKIN BIT POSITION FUNCTION DESCRIPTION N A Start Input Level Writing to this location starts restarts the input AGC error integrator The integrator will either restart or Detector AGC stop when the integration interval counter times out depending on bit 30 of Control Register 1 see
52. OSITION FUNCTION DESCRIPTION 31 10 Discriminator FIR The discriminator FIR coefficients are 22 bit two s complement If the filter is symmetric the coefficients Coefficient are loaded from the center coefficient at address 64 to the last coefficient If the filter is asymmetric the coefficients Cg to are loaded with Cg in address 64 up to 64 where is number of asymmetric coefficients CONTROL WORDS 128 255 255 PROGRAMMABLE COEFFICIENT REGISTERS BIT POSITION FUNCTION DESCRIPTION 31 10 Programmable FIR The programmable FIR coefficients are 22 bit two s complement If the filter is symmetric the Coefficient coefficients are loaded from the center coefficient at address 128 to the last coefficient If the filter is asymmetric the coefficients Co to CN are loaded with Cg in address 128 up to 128 N where N is number of asymmetric coefficients Real Filters are computed as Xn k 1 Xn k 2 Ck 2 0 where CO is the coefficient in address 128 and is the oldest data sample Complex filters outputs are computed as follows Xn is the most recent data sample k is the number of samples number of complex taps CO re is the coefficient loaded into CW128 CO im is the coefficient loaded into CW129 The convolution starts with the oldest data times the last complex coefficient and ends with the newest data times the first complex coefficient loaded lout Xn k 1 q Ck 1 im Xn k 1 i Ck 1 re Xn k
53. OUTB The three bit data type identifier is shown both in Table 13 and in Figure 34 to the right of the controls for the cross matrix switch Serial output data word sequences are formed by linking data words by programming the data source for each shift requester s shift input signal This programming links the Shift Registers together in one or two serial chains Thus the Control Word 19 term Link follows X data where X is one of the seven data types Once the data source data word is selected by programming a three bit word representing one of the data types into Control Word 19 Bits 25 27 SEROUTA and 28 30 SEROUTB the process for identifying the next word is to select a three bit data type identifier which represents the data type to follow the source data type Program these bits into the Control Word 19 field representing the Link following X data where X the source data type defines the second word in the sequence Likewise the third data word is linked by selecting the Control Word 19 bits that identify the Link following X data where X the data type of the second word in the serial chain The process continues until all the desired data words have been linked NOTE I Q are sample aligned in time r and are sample aligned in time but one sample delayed from I Q The frequency sample is delayed in time from or Q by 1 sample time 63 tap FIR impulse response If the FIR is set to decimate
54. SET places the Write address pointer 000 and Read address pointer 111 Rule 6 The best addressing scheme is to read the FIFO until it is empty This avoids erroneous INTRRP assertions and provides for simple FIFO depth monitoring The interrupt is generated when the depth increments past the threshold 39 intersil FN4450 4 May 1 2007 HSP50214B FIGURE 40 FIFO DEPTH IS WRITE READ WRITE FIGURE 40B FIFO FULL IS WHEN WRITE READ 7 READ e 23 WRITE FIGURE 40C FIFO EMPTY IS WHEN WRITE READ 1 READ READY FIGURE 40D FIFO READY IS WHEN WRITE READ gt DEPTH FIGURE 40 FIFO Operation Via 8 Bit Processor Interface The Buffer RAM Output may also be accessed via the 8 bit microprocessor interface C 7 0 Figure 41 shows the conceptual configuration of the 8 bit uprocessor interface Control Word 20 Bit 24 must be set to 0 in order to obtain Buffer RAM data to this output The Microprocessor Read Section describes how to read the data from each sample out of the C 7 0 interface Recall that INTRRP stays low for 8 PROCCLK cycles The FIFO can be read before the INTRRP signal goes low the number of samples in the FIFO must be monitored by the user The timing relationship of the INTRRP to the snapshot data is shown in Figure 42 The read pointer of the FIFO is incremented when Control Word 23 is written to The data cannot be read from the next sample until 4 PROCCL
55. Section and Microprocessor Write Section SEROUTB Serial Output Bus Data Contents be related to SEROUTA magnitude phase frequency timing error and AGC information can be sequenced in programmable order See Output Section and Microprocessor Write Section SERCLK Output Clock for Serial Data Derived from PROCCLK as given by Control Word 20 the Microprocessor Write Section SERSYNC Serial Output Sync Signal Serves as serial data strobes See Output Section and Microprocessor Write Section SEROE Serial Output Enable When high the SEROUTA SEROUTB SERCLK and SERSYNC signals are to a high impedance C 7 0 yo Processor Interface Data Bus See Microprocessor Write Section C7 is the MSB A 2 0 Processor Interface Address Bus See Microprocessor Write Section A2 is the MSB WR Processor Interface Write Strobe 7 0 is written to Control Words selected by 2 0 in the Programmable Down Converter on the rising edge of this signal See Microprocessor Write Section RD Processor Interface Read Strobe C 7 0 is read from output or status locations selected by A 2 0 in the Programmable Down Converter on the falling edge of this signal See Microprocessor Read Section REFCLK Reference Clock Used as an input clock for the timing error detector The timing error is computed relative to REFCLK REFCLK frequency must be less than or equal to PROCCLK 2 MSYNCO Multiple Chip Sync Output Provided for
56. UNCTION The Cartesian to Polar Coordinate converter accepts and Q data and generates magnitude and phase data The magnitude output is determined by the Equation 15 1 64676 I7 02 EQ 15 where the magnitude limits are determined by the maximum and signal levels into the Cartesian to Polar converter Taking fractional 2 s complement representation magnitude ranges from 0 to 2 329 where the maximum output is I 1 64676 1 0 1 0 1 64676 x 1 414 2 329 The AGC loop feedback path consists of an error detector error scaling and an AGC loop filter The error detector subtracts the magnitude output of the coordinate converter from the programmable AGC THRESHOLD value The bit weighting of 21 intersil FN4450 4 May 1 2007 HSP50214B the AGC THRESHOLD value Control Word 8 Bits 16 28 is shown in Table 5 Note that the MSB is always zero The range TABLE 6A AGC LIMIT EXPONENT vs GAIN GAIN dB EXPONENT MANTISSA of the AGC THRESHOLD value is 0 to 43 9995 The AGC F 96 332 15 255 Error Detector output has the identical range TABLE 5 AGC THRESHOLD CONTROL WORD 8 BIT 30 393 19 2 WEIGHTING 84 288 14 0 78 268 13 0 72 247 12 0 66 227 11 0 The loop gain is set in the AGC Error Scaling circuitry usi
57. WORD 7 BIT 17 FN CONTROL WORD 7 BIT 18 FN OR 2 HALFBAND FILTER 5 CONTROL WORD BIT 19 4 0 1 Fs OR 2 HALFBAND FILTER OUTPUT T Each halfband section decimates by 2 FIGURE 17 BLOCK DIAGRAM OF HALFBAND FILTER SECTION 17 intersil FN4450 4 May 1 2007 HSP50214B MAGNITUDE dB MAGNITUDE dB 0 6dB BANDWIDTH 20 40 60 HALFBAND FILTER 5 HALFBAND FILTER 4 HALFBAND FILTER 3 HALFBAND FILTER 2 HALFBAND FILTER 1 100 120 0 125 0 25 0 375 NORMALIZED FREQUENCY Fy 0 5 FIGURE 18 HALFBAND FILTER FREQUENCY RESPONSE ALIAS PROFILES 6dB BANDWIDTH HALFBAND FILTER 5 HALFBAND FILTER 4 HALFBAND FILTER 3 HALFBAND FILTER 2 HALFBAND FILTER 1 0 125 0 25 0 375 NORMALIZED FREQUENCY Fy FIGURE 19 HALFBAND FILTER ALIAS CONSIDERATIONS 18 _imtersil FN4450 4 May 1 2007 HSP50214B TABLE 4 HALFBAND FILTER COEFFICIENTS COEFFICIENTS HALFBAND 1 HALFBAND 2 HALFBAND 3 HALFBAND 4 HALFBAND 5 0 031303406 0 005929947 0 00130558 0 000378609 0 000347137 C1 0 000000000 0 000000000 0 000000000 0 000000000 0 000000000 C2 0 281280518 0 049036026 0 012379646 0 003810883 0 00251317 C3 0 499954224 0 000000000 0 000000
58. Y fs R R FIGURE 48A CIC FILTER RESPONSE FIGURE 48B HB3 FILTER RESPONSE 10 10 15 CIC INPUT RATE 10 10 730 _ 30 50 a 50 E 2 2 70 70 lt 5 5 90 90 110 110 fg CIC INPUT RATE 130 130 FREQUENCY fs FREQUENCY fs R R FIGURE 48C HB5 FILTER RESPONSE FIGURE 48D 255 FIR TAP FILTER RESPONSE a 2 E z FREQUENCY 5 FIGURE 48 COMPOSITE FILTER RESPONSE FIGURE 48 PDC FILTER FREQUENCY SPECTRUMS EXAMPLE NORMALIZED TO SAME SCALE 46 FN4450 4 May 1 2007 HSP50214B Configuration Control Word Definitions Note that in the Configuration Control Register Tables some of the available 32 bits in a Control Word are not used Unused bits do not need to be written to the Master Register If the destination only has 16 bits then only 2 bytes need to for proper operation of the Microprocessor Write Section Bits identified as Reserved should be programmed to a zero NOTE CLKIN or PROCCLK must be present to properly load control words Note in the header which is applicable be written to the Master Register Figure 45 details the timing CONTROL WORD 0 CHIP CONFIGURATION INPUT SECTION CIC GAIN SYNCHRONOUS TO CLKIN BIT POSITION FUNCTION DESCRIPTION 31 21 Reserved Reserved 20 Carrier NCO External 0 The SYNCIN1 pin has no effect on the Carrier NCO Sync Enable 1 When the SYNCIN1 pin is ass
59. ad and write pointers cannot point to the same address Thus the FIFO pointer must move to the next address before reading the next set of data I Q r and i samples 4 PROCCLK cycles required after an increment before reading can resume The FIFO write pointer is reset to zero the first data sample when Control Word 22 is written to via the 8 bit microprocessor interface See the Microprocessor Read Section for more detail on how to obtain the Buffer RAM output with this technique Figure 39 shows the timing diagram required for parallel output operations In this diagram only the I Q and Frequency data are taken from each sample before incrementing to the next sample Figure 39 assumes that the pointer has already been incremented into a sample NOTE For the very first sample read the pointer must be incremented first and 4 PROCCLKs must pass before this sample can be read Figure 38 shows INTRRP going low before the FIFO is read The FIFO can be read before the number of samples reaches the INTRRP pointer The number of samples in the FIFO must be monitored by the user via a status read PDC OEAL AOUT 7 0 OEBL a N n o wam FIGURE 38 INTERFACE BETWEEN A 16 BIT MICROPROCESSOR AND PDC IN FIFO BUFFER 8 5 INTRRP gt 4CLKS OEAL OEBL SEL 0 2 1 D 7 4 C LKAA PROCCLK nnn fmm UTI FIGURE 39 TIMING DIAGRAM FOR PDC IN FIFO MODE
60. ains the processing functions needed to convert sampled IF signals to baseband digital samples These functions include LO generation mixing decimation filtering programmable FIR shaping bandlimiting filtering resampling Automatic Gain Control AGC frequency discrimination and detection as well as multi chip synchronization The HSP50214B interfaces directly with a DSP microprocessor to pass baseband and status data A top level functional block diagram of the HSP50214B is shown in Figure 1 The diagram shows the major blocks and multiplexers used to reconfigure the data path for various architectures The HSP50214B can be broken into 13 sections Synchronization Input Input Level Detector Carrier Mixer Numerically Control Oscillator NCO CIC Decimating Filter Halfoand Decimating Filter 255 Tap Programmable FIR Filter Automatic Gain Control AGC Re sampler Halfband Filter Timing NCO Cartesian to Polar Converter Discriminator and Output Sections All of these sections are configured through a microprocessor interface The HSP50214B has three clock inputs two are required and one is optional The input level detector carrier NCO and CIC decimating filter sections operate on the rising edge of the input clock CLKIN The halfband filter programmable FIR filter AGC Re Sampler Halfband filters timing NCO discriminator and output sections operate on the rising edge of PROCCLK The third clock REFCLK is used to generate ti
61. are not necessarily exact 2 All dimensions and tolerances per ANSI Y14 5M 1982 3 Dimensions D and E to be determined at seating plane 4 Dimensions D1 E1 to be determined at datum plane 5 Dimensions D1 and 1 do not include mold protrusion Allowable protrusion is 0 25mm 0 010 inch per side 0 13 0 17_ 0 005 0 007 6 Dimension B does not include dambar protrusion Allowable dambar protrusion shall be 0 08mm 0 003 inch total T BASE METAL WITH PLATING 7 N is the number of terminal positions 0 13 0 23 0 005 0 009 All Intersil U S products are manufactured assembled and tested utilizing 1509000 quality systems Intersil Corporation s quality certifications be viewed at www intersil com design quality Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsi
62. ase and symbol timing recovery loop filters for continuous PSK signals not burst Digital modulation formats that combine amplitude and phase for symbol mapping such as m ary QAM can also be downconverted demodulated and matched filtered The received symbol information is provided with 16 bits of resolution in either Cartesian or Polar coordinates to facilitate remapping into bits and to recover the carrier phase External Symbol mapping and Carrier Recovery Loop Filtering is required for this waveform Resampling and Interpolation Filters Two key features of the resampling FIR filter are that the re sampler filter allows the output sample rate to be programmed with millihertz resolution and that the output sample rate can be phase locked to an independent separate clock The re sampler frees the front end sampling clocks from having to be synchronous or integrally related in rate to the baseband output The asynchronous relationship between front end and back end clocks is critical in applications where ISDN interfaces drive the baseband interfaces but the channel sample rates are not related in any way The interpolation halfband filters can increase the rate of the output when narrow frequency bands are being processed The increase in output rate allows maximum use of the programmable FIR while preserving time resolution in the baseband data 8 intersil FN4450 4 May 1 2007 HSP50214B 14 Bit Input and Processing R
63. ations are combinations of frequency and time domain multiple access schemes For example GSM is a TDMA signal that is frequency hopped The individual channels contain Gaussian MSK modulated signals The PDC again offers the 0 012Hz tuning resolution for de hopping the received signal The combination of halfband and 256 tap programmable 22 bit coefficient FIR filters readily performs the necessary matched filtering for demodulation and optimum detection of the GMSK signals CDMA Based Standards and Applications For Code Division Multiple Access CDMA type signals the PDC offers the ability to have a single wideband RF front end from which it can select a single spread channel of interest The synchronization circuitry provides for easy control of multiple PDC for applications where multiple received signals are required such as base stations In IS 95 CDMA the receive signal bandwidth is approximately 1 2288MHz wide with many spread spectrum channel in the band The PDC supplies the downconversion and filtering required to receive a single RF channel in the presence of strong adjacent interference Multiple PDC s would be sourced from a single receive RF chain each processing a different receive frequency channel The despreader would usually follow the PDC In some very specific applications with short fixed codes the filtering and despreading may be possible with innovative use of the programmable 22 bit coefficient FIR filter
64. band Filters 4 Clears input available strobe 5 Resets Halfband control logic 255 Tap FIR 1 Resets FIR read and write address pointers 2 Zero s coefficient read address AGC Loop 1 Clears accumulator in loop filter Re Sampler and Interpolation Halfband Filters 1 Resets counters for Halfoand addresses for writing 2 Resets output enable 3 Reset controller for Re Sampler Timing NCO 1 Initializes counters for inserting extra pulses when interpolating halfbands are enabled In the HSP50214B a configuration control word bit determines if a Timing NCO reset is executed If Control Word 27 Bit 20 is set to a logic one a reset will clear the feedback in the timing NCO phase accumulator If Control Word 27 Bit 20 is zero a reset will not clear the timing NCO phase accumulator feedback which is how the HSP50214 operated Discriminator 1 Resets read and write address pointers 2 Zero s coefficient read address Cartesian to Polar Coordinate Counter 1 Resets Cordic counters stops current computation FIFO Control 1 Resets decoder for controlling FIFO Resets write address for FIFO Clears RD and INTRRPT Resets depth and full flags Sets the empty flag Sets the read address to 7 write address to 0 Snapshot Control 1 Zeros the group number 2 Load interval counter 3 Resets write address and read address for FIFO Output Serial Control 1 Reloads
65. ble 22 in the Output Section is sent to C 7 0 This state was provided so that the user could obtain the status bits quickly Refer to the Timing Diagram in Figure 46 Suppose the input level detector has a hex value of 321AF5 H then Table 21 details the steps to be taken RD A2 0 OUTPUT DATA C 7 0 A READ CODE C 2 0 LOAD ADDRESS THREE STATE ASSERT RD OF TARGET INPUTBUS ENABLE DATA CONTROL REGISTER OUTPUT 0 7 FIGURE 46 READING THE CONTROL REGISTERS USING A LATCH CODE EQUAL TO A 5 A READ ADDRESS AND A READ CODE TABLE 21 PROCESSOR READ SEQUENCE INPUT LEVEL SELECTOR STEP A 2 0 C 7 0 COMMENT 1 101 100 Write Read Code 100 to Address 5 WR pulled high to generate rising edge 2 000 1111 1000 Drop RD low Read AGC LSB F4 H 3 001 0001 1010 Pull RD high then drop low 1A H Read AGC NLSB 4 010 00110010 Pull RD high then drop low 32 H Read AGC MSB TABLE 22 DEFINITION OF ADDRESS MAP READ STATUS CODE C 2 0 TYPE READ ADDRESS A 2 0 000 Buffer RAM 000 LSB land Q 001 MSB 010 Q LSB 011 Q MSB See Output Section 001 Buffer RAM 000 MAG LSB 7 0 Output 001 MAG MSB 15 8 and 010 PHASE LSB 7 0 011 PHASE MSB 15 8 See Output Section 010 Buffered 000 FREQ LSB Frequency 001 FREQ MSB See Output Section 011 Not Used 100 Input Level Input AGC Det
66. ces the transfer function given in Figures 21 and 22 Since the log of the gain response is roughly linear AGC Slew Rate 1 5dB THRESH MAG 1 64676 x 91 the loop response be approximated by multiplying the 15 Max 2 9 EQ 18 maximum AGC gain error by the loop gain The expected 23 intersil FN4450 4 May 1 2007 HSP50214B range for the AGC rate is 0 000106 to 3 275dB output sample time for a threshold of 1 2 scale See the notes at the bottom of Table 9A for calculation of the AGC response times The maximum AGC Response is given by AGC Response Input Cart Polar Gain Error Det Gain AGC Loop Gain AGC Output Weighting EQ 19 Since the AGC error is scaled to adjust the gain the loop settles asymptotically to its final value The loop settles to the mean of the signal TABLE 7 AGC LOOP GAIN BINARY MANTISSA TO GAIN SCALE FACTOR MAPPING BINARY BINARY CODE SCALE CODE SCALE MMMM FACTOR MMMM FACTOR 0000 0 0000 1000 0 5000 0001 0 0625 1001 0 5625 0010 0 1250 1010 0 6250 0011 0 1875 1011 0 6875 0100 0 2500 1100 0 7500 0101 0 3125 1101 0 8125 0110 0 3750 1110 0 8750 0111 0 4375 1111 0 9375 TABLE 8 AGC LOOP GAIN BINARY EXPONENT GAIN SCALE FACTOR MAPPING BINARY BINARY CODE SCALE CODE SCALE EEEE FACTOR EEEE FACTOR 0000 215 1000 27 0001 214 1001 26 0010 213 1010 25 0011 212 1011 24 0100 211 1100
67. d by the Q data word followed by the Phase data word on the SEROUTA output Similarly it is desired to output the Magnitude data word followed by the Frequency data word followed by the Timing Error data word followed by the AGC Level data word on the SEROUTB output Table 14 illustrates how Control Word 19 should be programmed TABLE 14 EXAMPLE 1 SERIAL OUTPUT CONTROL SETTINGS CONTROL WORD 19 BIT BIT POSITION FUNCTION VALUE RESULT 30 28 SEROUTA Data Source 000 I 27 25 SEROUTB Data Source 010 24 21 Number of Serial Word 100 4 Links in a Chain 20 18 Link following data 001 Q 17 15 Link following Q data 011 0 14 12 Link following r data 100 f 11 9 Link following data 111 Zeros 8 6 Link following f data 101 Timing 5 3 Link following AGC data XXX N A 2 0 Link following Timing 110 AGC Error data NOTE Because all but the first data word in the serial output is identified by the data type that it follows SEROUTB can only be fully independent of the sequence in SEROUTA if it does not use any of the same data word types This implies a partition as described in Example 1 Once a data word that is used in SEROUTA is called out in SEROUTB the remaining sequence in SEROUTB will be identical to that portion of SEROUTA sequence that follows the duplicate data type This follows from using the Link follows data type data for word linkage NOTE Each ty
68. d to offset the signal gain through the part i e to keep the CIC filter output level constant as the analog front end attenuation is changed The gain adjust offset is 6dB code so the gain adjust range is 0 to 42dB For example if 12dB of attenuation is switched in at the receiver RF front end a code of 2 would increase the gain at the input to the CIC filter up 12dB so that the CIC filter output would not drop by 12dB This fixed gain adjust eliminates the need for the software to continually normalize One must exercise care when using this function as it can cause overflow in the CIC filter Each gain adjust in the shifter from the gain adjust control signals is the equivalent of an extra bit of input The maximum decimation in the CIC is reduced accordingly With a decimation of 32 all 40 bits of the CIC are needed so no input offset gain is allowed As the decimation is reduced the allowable offset gain increases Table 3 shows the decimation range versus desired offset gain range Table 3 assumes that the CIC Shift Gain has been programmed per Equation 7 or 8A The CIC filter decimation counter can be loaded synchronous with other PDC chips using the SYNCIN1 signal and the CIC External Sync Enable bit The CIC external Sync Enable is set via Control Word 0 Bit 19 Halfband Decimating Filters The Programmable Down Converter has five halfband filter stages as shown in Figure 17 Each stage decimates by 2 and filters ou
69. delayed and subtracted and optionally shifted phase This is the Discriminator FIR filter input found in the HSP50214 2 18 bits of magnitude from the coordinate converter block This was added to provide for post detection filtering of AM signals 3 18 bits from the output of the resampler interpolation halfband filter block This was added to provide for processing of SSB signals The shift delay and subtract functions are bypassed for items 2 and 3 In addition to the FIR input selections the Q input to the coordinate converter block can be zeroed so that the magnitude output is the magnitude of only Again this was added to provide for processing SSB signals 31 FN4450 4 May 1 2007 HSP50214B The Discriminator FIR filter input selections are made in Control Word 27 Bits 18 and 19 The bit definitions are 00 Item 1 described above 01 Item 2 described above 1X Item 3 described above Control Word 27 Bit 14 is used to control the Q input to the coordinate converter The bit definitions is 0 and enabled to the to R Theta block 1 The Q input to the I Q to R Theta block is zeroed The enable signals associated with the various input selections to the Discriminator FIR filter are 1 The data ready strobe from the coordinate con verter block 2 The data ready strobe from the coordinate con verter block The enable signals associated with the various input selecti
70. diaries For information regarding Intersil Corporation and its products see www intersil com 62 H 4450 4 intersil May 1 2007
71. dress a sin cos lookup table This lookup table maps phase into sinusoidal amplitude The sine and cosine values have 18 bits of amplitude resolution The spurious components in the sine cosine generation are at least 102dBc The sine and cosine samples are routed to the mixer section where they are multiplied with the input samples to translate the signal of interest to baseband The mixer multiplies the 14 bit input by the 18 bit quadrature sinusoids The mixer equations are lout lin 00 5 Qout lin x sin EQ 5A The mixer output is rounded symmetrically to 15 bits To allow the frequency and phase of multiple parts to be updated synchronously two sets of registers are used for latching the center frequency and phase offset words The offset phase and center frequency Control Words are first loaded into holding registers The contents of the holding registers are transferred to active registers in one of two ways The first technique involves writing to a specific Control Word Address A processor write to Control Word 5 transfers the center frequency value to the active register while a processor write to Control Word 6 transfers the phase offset value to the active register The second technique designed for synchronizing updates to multiple parts uses the SYNCIN1 pin to update the active registers When Control Word 1 Bit 20 is set to 1 the SYNCIN1 pin causes both the center frequency and Phase Offset Ho
72. e Output Tag Bit 5 4 Frequency Data Serial See Data Serial Output Tag selection above Output Tag Bit 3 2 AGC Data Serial See Data Serial Output Tag selection above Output Tag Bit 1 0 Timing Error Data See Data Serial Output Tag selection above Serial Output Tag Bit CONTROL WORD 21 BUFFER RAM OUTPUT CONTROL REGISTER SYNCHRONIZED TO PROCCLK BIT POSITION FUNCTION DESCRIPTION 31 16 Reserved Reserved 15 Output Buffer Mode 0 The output buffer operates in snapshot mode 1 The output buffer operates in FIFO mode 14 12 FIFO Mode Depth In FIFO mode when the FIFO depth reaches this threshold an interrupt is generated and the READY Threshold flag is asserted The threshold may be set from 0 to 7 Bit 14 is the MSB The interrupt is generated when the FIFO depth reaches the threshold as the FIFO fills 11 4 Snapshot Mode In snapshot mode the interval between snapshots in the output sample times is determined by this 8 Interval bit binary number i e 256 28 sample time counts between snapshot samples Program this parameter to 1 less than the desired interval Bit 11 is the MSB 3 0 Snapshot Mode In snapshot mode the number of samples stored each time the snapshot interval counter times out is Number of Samples equal to the decimal version of this 4 bit number The range is 1 8 Bit 3 is the MSB CONTROL WORD 22 BUFFER RAM OUTPUT FIFO RESET SYNCHRONIZED TO PROCCLK BIT POSITION FUNCTION DESCRIPTION N A FIFO reset A write to t
73. e RMS value of a sinusoid multiply the average value of the rectified sinusoid by 1 111 For a full scale input sinusoid this yields an RMS value of approximately 3dBfs NOTE 1 111 scales the rectified sinusoid average 2 1 to 1 42 A INPUT SIGNAL B RECTIFIED SIGNAL 2 2 m n n lt lt THRESHOLD 0 ACCUMULATOR INPUTS 9 a 5 a lt lt p om w E DETECTOR OUTPUT F CLOSED LOOP STEADY STATE CONSTANT INPUT AMPLITUDE AMPLITUDE FIGURE 11 SIGNAL PROCESSING WITHIN LEVEL DETECTOR In the HSP50214B the polarity of the LSB s of the integration period pre load is selectable If Control Word 27 Bit 23 is set to a logic one the two LSB s of the integration period preload are set to logic ones This allows a power of two to be set for the integration period for easy normalization in the processor If Control Word 27 Bit 23 is set to a logic zero then the two LSB s of the integration period preload are set to zeros as in the HSP50214 Carrier Synthesizer Mixer The Carrier Synthesizer Mixer Section of the HSP50214B is shown in Figure 12 The NCO has a 32 bit phase accumulator a 10 bit phase offset adder and a sine cosine ROM frequency of the NCO is the sum of a center frequency Control Word loaded via the microprocessor interface Control Word 3 Bits 0 to 31 and an
74. e different sources are used for CLKIN and PROCCLK PDC A is the Master sync through MSO PDC B configures the CLKIN sync through SYNCIN1 PDC A configures the PROCCLK sync through SYNCIN2 HSP50214B HSP50214B MSYNCO MSYNCO MSYNCI MASTER SYNCIN2 SYNCOUT SYNCIN2 SYNCIN1 ALL OTHER SYNCIN1 ALL OTHER SYNCIN2 ALL OTHER MSI FIGURE 2 SYNCHRONIZATION CIRCUIT SYNCOUT for PDC B should be set to be synchronous with CLKIN Control Word 0 Bit 3 0 See the Microprocessor Write Section SYNCOUT for PDC B is tied to the SYNCIN1 of all the PDCs The SYNCIN1 can be programmed so that the carrier NCO and or the 5th order CIC filter of all PDCs can be synchronously loaded updated using SYNCIN1 See Control Word 0 Bits 19 and 20 in the Microprocessor Write Section for details SYNCOUT for one of the PDC s other than PDC B should be set for PROCCLK bit 3 1 in Control Word 0 This output signal is tied to the SYNCIN2 of all PDCs The SYNCIN2 can be programmed so that the AGC updates its accumulator with the contents in the master registers Control Word 8 Bit 29 in the Microprocessor Write Section SYNCIN is also used to load or reset the timing NCO using bit 5 Control Word 11 The halfband and FIR filters can be reset on SYNCIN2 using Control Word 7 Bit 21 The MSYNCO of one of the PDCs is then used to drive the MSYNCI of all the PDCs including its own For application configurations where CLKIN and PROCCLK ha
75. e filter alone because 944MIPS are much greater that the 60MIPs effective limit set by PROCCLK It is necessary to decimate down to 2x the chip rate to get a realistic number of filter taps Both interpolation halfband filters are then used to obtain the 3x CDMA output 944MIPS is a lot of MIPS The HSP50214B gets the equivalent processing by decimating down and interpolating backup POLYPHASE RESAMPLER FILTER HALFBAND FILTER 2 HALFBAND FILTER 1 RESAMPLER NCO PULSE DELAY PROCCLK COUNTER PROCCLK N tr lt EXTRA nmt PULSES THIS BLOCK GENERATES EXTRA olo 10 0 BYPASS DATA READY PULSES FOR THE 0 0 1 0 NEW OUTPUTS FROM THE 2 1 9 1 INTERPOLATION PROCESS 1 0 0 3 NV 110 1 3 NV 111 0 3 NV INVALID MODE 11111 3 FIGURE 25 GENERATING DATA READY PULSES FOR OUTPUT DATA Timing NCO The Timing NCO is very similar to the carrier NCO Phase Accumulator Section It provides the NCO driven sample pulse and associated phase information to the resampling filter process described in the Re sampler Filter Section The Timing NCO does not include the SIN COS Section found in the Carrier NCO The top level block diagram is shown in Figure 26 28 FN4450 4 May 1 2007 HSP50214B EN EXT TIMING NCO SYNC d FILTER PHASE T I setecr CARRY OUT RUN FILTER STROBE SYNCIN2 TIMING PHASE STROBE T TIMING NCO n PHASE OFFSET CLEAR PH
76. e rate and to zero stuff the data prior to filtering This zero stuffing effectively interpolates the input signal up to the rate of the input clock CLKIN This interpolated mode allows the part to be used at rates where the sampling frequency is above the maximum input rate range of the halfband filter section and where the desired output bandwidth is too wide to use a Cascaded Integrator Comb CIC filter without significantly reducing the dynamic range 9 intersil FN4450 4 May 1 2007 HSP50214B See Figures 4 to 7 for an interpolated input example detailing the associated spectral results Interpolation Example The specifications for the interpolated input example are CLKIN 40MHz Input Sample Rate 5MSPS PROCCLK 28MHz Interpolate by 8 Decimate by 10 Desired 85dB dynamic range output bandwidth 500kHz Input Level Detector The Input Level Detector Section measures the average magnitude error at the PDC input for the microprocessor by comparing the input level against a programmable threshold and then integrating the result It is intended to provide a gain error for use in an AGC loop with either the RF IF or A D converter stages see Figure 8 The AGC loop includes Input Level Detector the microprocessor and an external gain control amplifier or attenuator The input samples are rectified and added to a threshold LEVEL DETECT IN 13 0 INPUT FORMAT INPUT FORMAT T GAINAD
77. e the same as the Direct Output Port mode FN4450 4 4 i i intersil May 1 2007 HSP50214B Pin Descriptions continued NAME TYPE DESCRIPTION DATARDY Output Strobe Signal Active Low Indicates when new data from the Direct Output Port Section is available DATARDY is asserted for one PROCCLK cycle during the first clock cycle that data is available on the parallel out busses See Output Section OEAH Output enable for the MSByte of the AOUT bus Active Low The AOUT MSByte outputs are three stated when OEAH is high OEAL Output enable for the LSByte of the AOUT bus Active Low The AOUT LSByte outputs are three stated when OEAL is high OEBH Output enable for the MSByte of the BOUT bus Active Low The BOUT MSByte outputs are three stated when OEBH is high OEBL Output enable for the LSByte of the BOUT bus Active Low The BOUT LSByte outputs are three stated when OEBL is high SEL 2 0 Select Address is used to choose which information in a data set from the Buffer RAM Output Port is sent to the least significant bytes of AOUT and BOUT SEL2 is the MSB INTRRP Interrupt Output Active Low This output is asserted for 8 PROCCLK cycles when the Buffer RAM Output Port is ready for reading SEROUTA Serial Output Bus A Data magnitude phase frequency timing error and AGC information can be sequenced in programmable order See Output
78. ector 000 input AGC LSB 0 7 001 input AGC NLSB 8 15 010 input AGC MSB 16 23 43 intersil FN4450 4 May 1 2007 HSP50214B TABLE 22 DEFINITION OF ADDRESS MAP Continued READ STATUS CODE C 2 0 TYPE READ ADDRESS A 2 0 101 AGC Data AGC must write to location 10 to and Timing sample Error 000 AGC LSB lower 8 bits of linear Control Word 3 used by multiplier mmmmmmmm LSB 001 AGC MSB 4 shift control bits and first three bits of linear Control Word oeeeemmm MSB This yields 011 Timing error MSB not stabilized 11 bits of the linear control mantissa 010 Timing error LSB not stabilized 110 Not Used 111 Not Used Don t Care Status 111 Status 6 0 consisting of 6 4 FIFO depth when output is in FIFO Buffer RAM Output Mode 3 EMPTY signalling the FIFO is empty and the read pointer cannot be advanced Active High 2 FULL signalling the FIFO is full and new samples will not be written Active High 1 READYB Output buffer has reached the programmed threshold in FIFO mode or the programmed number of samples have been taken in snapshot mode Active Low 0 INTEGRATION has been completed in the input level detector and is ready to be read Active High Applications Composite Filter Response Example For this example consider a total receive band roughly 25MHz wide containing 124 200kHz wide FDM channels as shown in Figure 47
79. ed above and because the DATARDY is as follows driven by the AOUT signal Figure 32 details such a configuration and are aligned in time When the f frequency word is selected for output on AOUT rl and o are time aligned but one sample clock delayed the DATARDY signal is asserted at the discriminator FIR from the associated and Q samples filter output rate which will be a reduced rate when DATARDY Is asserted time aligned with and at the same decimation is engaged in the filter The f frequency S output rate as the data type selected for the AOUT output is delayed from the associated and Q samples one sample Figure 31 details the timing of the AOUT and DATARDY for time plus the discriminator FIR filter impulse response time an AOUT data selection Figure 33 details the timing of this configuration for a FIR filter that decimates by 4 AOUT PROCCLK DATARDY NOTE The number of PROCCLKS per output symbol is not representative but shown to be small for clarity of establishing timing with respect to the DATARDY signal For each application the relationship of the output symbol rate to PROCCLK must be properly illustrated to determine the exact nature of the timing FIGURE 31 DATARDY WAVEFORMS WHEN I READ DATA IS SELECTED AS BOUT AOUT PROCCLK DATARDY FIGURE 32 DATARDY WAVEFORMS WHEN r MAGNITUDE IS SELECTED AS AOUT lt 1 FIR Delay gt BOUT 9339 T aou
80. eratures that meet or exceed the Pb free requirements of IPC JEDEC J STD 020 HSP50214B Block Diagram MICROPROCESSOR READ WRITE CONTROL C 7 0 AGC LOOP FILTER AGC LEVEL DETECT tc o an Ls ml sour c d E HALFBAND SEROUTB FIBI E AOUT 15 0 IN 13 0 2E lt m m z BOUT 15 0 POLYPHASE GAIN Q H EIR AND CONVERTER TEM E HALFBAND E L FILTERS CARRIER 5 COF 5 FREQ RESAMPLING M PROCCLK TIMING ERROR REFCLK A 2 FN4450 4 intersil May 1 2007 HSP50214B Pinout HSP50214B 120 LD MQFP TOP VIEW 117 AGCGNSEL 116 1 115 7 REFCLK 114 GND 113 0 OEAH 112 1 AOUT15 111 AOUT14 110 AOUT13 109 1 AOUT12 108 AOUT11 107 1 AOUT10 106 GND 104 AOUT9 103 71 AOUT8 102 1 AOUT7 101 6 100 5 99 98 NC 97 1 AOUTA 96 1 AOUT3 95 AOUT2 94 AOUT1 93 AOUTO 92 GND 120 7 IN11 119 7 IN12 118 IN13 105 NC 10 DATARDY 2 8 13 BOUT15 GND 4 BOUT14 IN7 5 6 NC 7 BOUT13 IN5 8 BOUT12 IN4 9 BOUT11 IN3 10 BOUT10 IN2 J 11 BOUT9 GND L 12 IN1 13 GND INO C 14 GND Vec 15 PROCCLK CLKIN 16 GND 17 MSYNCI 18 MSYNCO 19 GND GAINADJ2 20 BOUT7 GAINADJ1 21 BOUT6 GAINA
81. erted the carrier center frequency and phase are updated from the holding registers to the active register Also if bit 0 of this word is active the carrier phase accumulator feedback will be zeroed to set the Carrier NCO to a known phase allowing the NCOs of multiple parts to be initialized and updated synchronously 19 CIC External Sync 0 The SYNCIN1 pin has no effect on the CIC filter Enable 1 When the SYNCIN1 pin is asserted the decimation counter is loaded allowing the decimation counters in multiple chips to be synchronized When CW27 bit 22 is set to a 1 SYNCIN1 will reset both front end and back end circuitry 18 Input Format 0 Two s Complement Input Format 1 Offset Binary Input Format 17 Input Mode 0 Input operates in Gated Mode 1 Input operates in Interpolated Mode 16 13 CIC Shift Gain These bits control the barrel shifter at the input to the CIC filter These bits are added to the GAINADJ 2 0 pins to determine the total shift The sum is saturated at 15 See the CIC Decimation Filter Section for values to be programmed in this field based on CIC filter Decimation Bit 16 is the MSB SG Floor 39 number of input bits 5logo R for 4 lt lt 31 SG 15 for 4 SG 0 for 32 12 7 CIC Decimation These bits control the decimation in the CIC filter Program this field to R 1 where R is the desired Counter Preload decimation factor in the filter The decimation factor range is 4 32 See CIC Filter Section for e
82. erter is either the AGC data ready signal or the resampler data ready signal If the resampler is bypassed the AGC data ready signal is used and there is a delay of 6 clock cycles between the FIR data being ready and the coordinate converter block sampling it If the resampler is enabled its data ready signal will be delayed by 6 clocks for the plus the compute delay of the resampler block This may cause the to r O output sample alignment to shift with decimation For this reason it is recommended that the resampler halfband filter block be bypassed when using this new data path To select the output of the 255 tap programmable FIR filter to be routed to the coordinate converter set Control Word 27 Bit 13 to a logic one For routing as in the HSP50214 set Control Word 27 Bit 13 to a logic zero Frequency Discriminator The discriminator block delays phase from the Cartesian to Polar Section and subtracts it from the latest sample This delay and subtract can be modeled as a programmable delay comb filter The output of the filter is dO dt or frequency The transfer function of the discriminator is set by Hz 1 27 EQ 21 where D is the programmable discriminator delay expressed in number of sample clock delays The discriminator output frequency is then filtered with a programmable FIR filter The Block Diagram of the Frequency Discriminator is shown in Figure 29 The range of delay in the discriminator is fr
83. es are outputting data in the direct output mode For this mode the output formats are the same as the Direct Output Port mode BOUT 15 0 Parallel Output Bus B Two parallel output modes are available on the HSP50214B The first is called the Direct Output Port where the source is selected through Control Word 20 see the Microprocessor Write Section and comes directly from the Output MUX Section see Output Control Section The most significant byte of BOUT always outputs the most significant byte of the Parallel Direct Output Port whose data type is selected via uP interface BOUT15 is the MSB In this mode the BOUT 15 0 bus is updated as soon as data is available DATARDY is asserted to indicate new data For this mode the output choices are Q or r The format is 2 s complement except for magnitude which is unsigned binary with a zero as the MSB The second mode for parallel data is called the Buffer RAM Output Port The Buffer RAM Output Port acts like a FIFO for blocks of information called data sets Within a data set is Q magnitude phase and frequency information a particular information is selected using SEL 2 0 Up to 7 data sets is stored in the Buffer RAM Output Port The least significant byte of BOUT can be used to either output the least significant byte of the B Parallel Direct Output Port or the least significant byte of the Buffer RAM Output Port See Output Section For this mode the output formats ar
84. esolution The PDC maintains a minimum of 14 bits of processing resolution through to the output providing over 84dB of dynamic range The 18 bits of resolution on the internal references provide a spurious floor that is better than 98dBc Furthermore the PDC provides up to 42dB of gain scaling to compensate for any change in gain in the RF front end as well as up to 96dB of gain in the internal PDC AGC This gain maximizes the output resolution for small signals and compensates for changes in the RF front end gain to handle changes in the incoming signal Summary The greatest feature of the PDC is its ability to be reconfigured to process many common standards in the communications industry Thus a single hardware element can receive and process a wide variety of signals from PCS to traditional cellular from wireless local loop to SATCOM The high resolution frequency tuning and narrowband filtering are instrumental in almost all of the applications Multiple Chip Synchronization Multiple PDCs are synchronized using a MASTER SLAVE configuration One part is responsible for synchronizing the front end internal circuitry using CLKIN while another part is responsible for synchronizing the backend internal circuitry using PROCCLK The PDC is synchronized with other PDCs using five control lines SYNCOUT SYNCIN1 SYNCIN2 MSYNCO and MSYNCI Figure 2 shows the interconnection of these five signals for multiple chip synchronization wher
85. ffective decimation range relative to the CIC Shift Gain value Bit 12 is the MSB While this field allows values from 0 63 the valid values are in the range from 4 32 6 CIC Bypassed Active high this bit routes the output of the input shifter to the output of the CIC with no filtering When the CIC filter is bypassed CLKIN must be at least twice the input sample rate should be toggled to achieve this When the CIC filter is bypassed the bottom 24 bits of the barrel shifter output are routed to the halfband filters 5 4 Number of Offset 00 8 bits Frequency Bits 01 16 10 24 11 32 3 Syncout CLK Select This bit selects whether the SYNCOUT signal is generated from CLKIN of from PROCCLK 0 CLKIN 1 PROCLK 2 Clear Phase Accum 0 Enable accumulator in Carrier NCO 1 Zero feedback in accumulator 1 Carrier NCO Offset When set to 1 this bit enables the offset frequency word to be added to the center frequency Control Frequency Enable Word The offset is loaded serially via the COF and COFSYNC pins 0 Carrier NCO Load When this bit is set to 1 the uP update to the Carrier NCO frequency or an external carrier NCO load Phase Accum On Update using SYNCIN1 will zero the feedback of the phase accumulator as well as update the phase or frequency This function can be used to set the NCO to a known phase synchronized to an external event 47 intersil FN4450 4 May 1 2007 HSP50214B CONTROL W
86. his address increments the output FIFO RAM address pointers to READ 111 and WRITE 000 CONTROL WORD 23 INCREMENT OUTPUT FIFO SYNCHRONIZED TO PROCCLK BIT POSITION FUNCTION DESCRIPTION N A FIFO Strobe write to this address increments the output FIFO buffer to the next sample set CONTROL WORD 24 SYNCOUT STROBE OUTPUT PIN SYNCHRONIZED TO CLKIN OR PROCCLK DEPENDING ON PROGRAMMING IN CONTROL WORD 0 BIT POSITION FUNCTION DESCRIPTION N A SYNCOUT Strobe A write to this address generates a one clock period wide strobe on the SYNCOUT pin that is synchronized to the clock This strobe may be synchronized to CLKIN or PROCCLK based on the programming of bit 3 of Control Word 0 54 intersil FN4450 4 May 1 2007 HSP50214B CONTROL WORD 25 COUNTER AND ACCUMULATOR RESET SYNCHRONIZED TO BOTH CLKIN AND PROCCLK BIT POSITION N A FUNCTION Counter and Accumulator Reset DESCRIPTION write to this address initializes the counters and accumulators for testing Items that are reset are Carrier NCO 1 Loads phase offset lt 9 0 gt into register to be used for adding to accumulator 2 Enables feedback on the accumulator CIC Filter 1 Resets the decimation counter 2 Clears enables to CIC 3 Clears accumulators in CIC 4 Clears enable leaving CIC Halfband Filters 1 Resets compute counter in Halfband control 2 Resets read address for all Halfband Filters 3 Resets write address for all Half
87. ial design and at major process or design changes AC Electrical Specifications Vcc 5 5 TA 0 to 70 C Commercial Note 7 40 C to 85 C Industrial Note 7 65MHz PARAMETER SYMBOL MIN MAX UNITS CLKIN Clock Period tcp 15 ns CLKIN High tcH 6 5 ns CLKIN Low 6 ns PROCCLK Period tpcp 18 ns PROCCLK High tPCH 7 ns PROCCLK Low tPCL 7 ns REFCLK Clock Frequency fRcP i PROCCLK 2 Hz REFCLK High 7 ns REFCLK Low tRCL 7 ns Setup Time GAINADJ 2 0 IN 13 0 COFSYNC and tps 7 ns SYNCIN1 to CLKIN FN4450 4 58 intersil May 1 2007 HSP50214B AC Electrical Specifications Voc 5 5 Ta 0 to 70 C Commercial Note 7 40 C to 85 C Industrial Note 7 Continued 65MHz PARAMETER SYMBOL MIN MAX UNITS Hold Time GAINADJ 2 0 IN 13 0 COF COFSYNC and SYNCIN1 tpH 0 ns from CLKIN Setup Time AGCGNSEL SOF MCSYNCI SOFSYNC and 2 to tpss 7 5 ns PROCCLK Hold Time AGCGNSEL SOF MCSYNCI SOFSYNC and SYNCIN2 tpHs 0 ns from PROCCLK Setup Time A 2 0 to Rising Edges of WR ns Setup Time A 2 0 C 7 0 to Rising Edges of WR twsc 10 ns Hold Time A 2 0 from Rising Edges of WR ns Hold Time A 2 0 C 7 0 from Rising Edges of WR twHc ns WR to CLKIN two 14 ns Note 9 PROCCLK to AOUT 15 0 BOUT
88. ilter The mixer output may be filtered with the CIC filter or it may be routed directly to the halfband filters The CIC filter is used to reduce the sample rate of a wideband signal to a rate that the halfoands and programmable filters can process given the maximum computation speed of PROCCLK See Halfband and FIR Filter Sections for techniques to calculate this value Prior to the CIC filter the output of the mixer goes through a barrel shifter The shifter is used to adjust the gain in 6dB steps to compensate for the variation in CIC filter gain with decimation See Equation 6 Fine gain adjustments must be done in the AGC Section The shifter is controlled by the sum of a 4 bit CIC Shift Gain word from the microprocessor and a 3 bit gain word from the GAINADJ 2 0 pins The three bit value is pipelined to match the delay of the input samples The sum of the 3 and 4 bit shift gain words saturates at a value of 15 Table 1 details the permissible values for the GAINADJ 2 0 barrel shifter control while Figure 15 shows the permissible CIC Shift Gain values The CIC filter structure for the HSP50214B is fifth order that is it has five integrator comb pairs A fifth order CIC has 84dB of alias attenuation for output frequencies below 1 8 the CIC output sample rate 8 BIT INPUT _ ALLOWABLE CIC SHIFT 10 BIT INPUT GAINS ARE BELOW THE 12 BIT INPUT __ CURVES 14 BIT INPUT CIC SHIFT G
89. intersil Data Sheet Programmable Downconverter The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor The Programmable Downconverter PDC performs down conversion decimation narrowband low pass filtering gain scaling resampling and Cartesian to Polar coordinate conversion The 14 bit sampled IF input is down converted to baseband by digital mixers and a quadrature NCO as shown in the Block Diagram A decimating 4 to 32 fifth order Cascaded Integrator Comb CIC filter can be applied to the data before it is processed by up to 5 decimate by 2 halfband filters The halfband filters are followed by a 255 tap programmable FIR filter The output data from the programmable FIR filter is scaled by a digital AGC before being re sampled in a polyphase FIR filter The output section can provide seven types of data Cartesian I polar 0 filtered frequency d0 dt Timing Error TE AGC level in either parallel or serial format Ordering Information HSP50214B FN4450 4 May 1 2007 Features Up to 65MSPS Front End Processing Rates CLKIN and 55MHz Back End Processing Rates PROCCLK Clocks May Be Asynchronous Processing Capable of gt 100dB SFDR Up to 255 Tap Programmable FIR Overall Decimation Factor Ranging from 4 to 16384 Output Samples Rates to 12 94MSPS with Output Bandwidths to 982kHz Lowpas
90. ion for details Bit 11 is the MSB The gain is in dB G 6 02 eeee 20100 10 1 0 0o mnmmmmmm GAIN 98 20 eeee Floor logo 10 mmmmmmmm Floor 256 10GAIN 20 2 CONTROL WORD 10 AGC SAMPLE GAIN CONTROL STROBE SYNCHRONIZED TO PROCCLK BIT POSITION FUNCTION DESCRIPTION N A Sample AGC Gain Writing to this location samples the output of the AGC loop filter to stabilize the value for uP reading Level CONTROL WORD 11 TIMING NCO CONFIGURATION SYNCHRONIZED TO PROCCLK BIT POSITION FUNCTION DESCRIPTION 31 6 Reserved Reserved 5 Enable External 0 SYNCIN2 has no effect on the timing NCO Timing NCO Sync 1 When SYNCIN2 is asserted the timing NCO center frequency and phase are updated with the value loaded in their holding registers If bit O of this word is set to 1 the phase accumulator feedback is also zeroed 4 3 Number of Offset 00 8 bits Frequency Bits 01 16 10 24 11 32 2 Enable Offset 0 Zero Offset Frequency to Adder Frequency 1 Enable Offset Frequency 1 Clear Phase 0 Enable Accumulator Accumulator 1 Zero Feedback in Accumulator 0 Timing NCO Phase When this bit is set to 1 the uP update to the timing NCO frequency or an external timing NCO load Accumulator Load On using SYNCIN2 will zero the feedback of the phase accumulator as well as update the phase and Update frequency This function can be used to set the NCO to a known phase synchronized to an external event CONTROL WOR
91. issa has a range of 0 lt lt 215 1 Equation 14 be expressed AGC Mult Shift Gain dB 20log 2 1 00271 14 The full AGC range of the Multiplier Shifter is from 0 to 96 331dB 20log4o 1 215 1 2715 2010g49 2 5 96 331 Figure 21 illustrates the transfer function of the AGC multiplier versus mantissa control for N 0 Figure 22 illustrates the complete AGC Multiplier Shifter Transfer function for all values of exponent and mantissa control The resolution of the mantissa was increased to 16 bits in the A Version to provide a theoretical AM modulation level of 96dBc depending on loop gain settling mode and SNR This effectively eliminates AM spurious caused by the AGC resolution For fixed gains either set the upper and lower AGC limits to the same value or set the limits to minimum and maximum gains and set the AGC loop gain to zero G dB 2 G LINEAR GAIN LINEAR AND dB 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 AGC CONTROL 55 VALUES TIMES 256 FIGURE 21 AGC MULTIPLIER LINEAR AND dB TRANSFER FUNCTION 100 _ _ 80 12 ee N 10 N N 9 8 7 a N 5 4 3 2 1 GAIN dB N 0 0 64 128 192 AGC CONTROL WORD MANTISSA x 256 FIGURE 22 AGC GAIN CONTROL TRANSFER F
92. l Word 21 The number of samples stored is the programmed value and may be from 1 to 8 sample sets A sample set consists of I Q r and f In snap shot operations the buffer is read the same as for FIFO operations Figures 37 and 39 describe the Design Blocks and Timing required to output data on AOUT 7 0 and BOUT 7 0 Table 17 summarizes the selectable output signals The method for reading data through the Microprocessor Section in snap shot mode is identical to the method described in the FIFO mode subsection and the Microprocessor Read Section Avoiding Timing Pitfalls When Using the Buffer RAM Output Port In snapshot mode the whole buffer is written whenever the interval counter has timed out After time out old data can be written over Thus the data contained within the buffer must be retrieved before time out to avoid data loss It may be desirable to disable the INTRRPT into the controlling microprocessor during read cycles to avoid the generating extra interrupts Figure 44 details how the WRITE address can trigger extra interrupts Care must be taken to either read sufficient data out of memory or RESET the addressing to ensure that a complete set of data is the cause of the interrupt INTRRP INTRRP WRITE ADDRESS TIME lt WR gt e RD lt WR gt lt WR RD gt COMPLETE SET OF 3 DATA SAMPLES IS IN MEMORY AT INTRRP A NORMAL READ WRITE SEQUENCE WRITE
93. lding Registers to be transferred to active registers Additionally when Control Word 0 Bit 0 is set to 1 the feedback in the phase accumulator is zeroed when the transfer from the holding to active register occurs This feature provides synchronization of the phase accumulator starting phase of multiple parts It can also be used to reset the phase of the NCO synchronous with a specific event The carrier offset frequency is loaded using the COF and COFSYNC pins Figure 13 details the timing relationship between COF COFSYNC and CLKIN The offset frequency word can be zeroed if it is not needed Similarly the Sample Offset Frequency Register controlling the Re Sampler NCO is loaded via the SOF and SOFSYNC pins The procedure for loading data through the two pin NCO interfaces is identical except that the timing of SOF and SOFSYNC is relative to PROCCLK CLKIN 1 1 COF NOTE Data must be loaded MSB first FIGURE 13 SERIAL INPUT TIMING FOR COF AND SOF INPUTS Each serial word has a programmable word width of either 8 16 24 or 32 bits See Control Word 0 Bits 4 and 5 for the Carrier NCO programming and Control Word 11 Bits 3 and 4 for Timing NCO programming On the rising edge of the clock data on COF or SOF is clocked into an input shift register The beginning of a serial word is designated by asserting either COFSYNC or SOFSYNC high
94. le input If R is 32 the gain through all five integrator stages is 32 225 The gain through the last four CIC stages is 220 through the 15 intersil FN4450 4 May 1 2007 HSP50214B last 3 it is 215 etc The sum the input bits and the growth bits cannot exceed the accumulator size This means that for a decimation of 32 and 15 input bits the first accumulator must be 15 25 40 bits Thus the value of the CIC Shift Gain word can be calculated SG FLOOR 39 IIN log R for 4 R 32 EQ 7 15 forR 4 NOTE The number of input bits is IIN If the number of bits into the CIC filter is used the value 40 replaces 39 For 14 bits Equation 7 becomes SG FLOOR 25 09 gt for 4 lt R 32 EQ 8A 15 forR 4 For 12 bits Equation 7 becomes SG FLOOR 27 log R 5 lt R 40 EQ 8B 215 for4 lt R lt 5 For 10 bits Equation 7 becomes SG FLOOR 29 for 6 lt R lt 52 EQ 8C 15 for4 lt R lt 6 For 8 bits Equation 7 becomes SG FLOOR 31 log for 9 lt R lt 64 EQ 8D 15 for4 lt R lt 9 Figure 15 is a plot of Equations 8A through 8D The 4 bit CIC Shift Gain word has a range from 0 to 15 The 6 bit Decimation Factor counter preload field R 1 has a range from 0 to 63 limited by the input resolution as cited above Using the Input Gain Adjust Control Signals The input gain offset control GAINADJ 2 0 is provide
95. ler Offset Frequency Sync This signal is asserted one CLK before the MSB of the offset frequency word see Serial Interface Section The setup and hold times are relative to PROCCLK This input is compatible with the output of the HSP50210 Costas loop 1 AOUT 15 0 Parallel Output Bus A Two parallel output modes are available on the HSP50214B The first is called the Direct Output Port where the source is selected through Control Word 20 see the Microprocessor Write Section and comes directly from the Output MUX Section see Output Control Section The most significant byte of AOUT always outputs the most significant byte of the Parallel Direct Output Port whose data type is selected via uP interface AOUT15 is the MSB In this mode the AOUT 15 0 bus is updated as soon as data is available DATARDY is asserted to indicate new data For this mode the output choices are r or f The format is 25 complement except for magnitude which is unsigned binary with a zero as the MSB The second mode for parallel data is called the Buffer RAM Output Port The Buffer RAM Output Port acts like a FIFO for blocks of information called data sets Within a data set is magnitude phase and frequency information a data type is selected using SEL 2 0 Up to 7 data sets are stored in the Buffer RAM Output Port The LSBytes of the AOUT and BOUT busses form the 16 bits for the buffered output mode and can be used for buffered mode while the MSByt
96. ler are two interpolation halfband filters The halfband filters allow the user to up sample by 2 or 4 to recover time resolution lost by decimating Interpolating by 2 or 4 gives 1 4 or 1 8 baud time resolution assuming 2x baud at the re sampler output The halfband filters use the same coefficients as HB3 and HB5 from the Halfband Filters Section If one halfband is used the 23 tap filter is chosen If two are used the 23 tap filter runs first MAGNITUDE dB 100 120 4 L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FREQUENCY RELATIVE TO fs FIGURE 24A POLYPHASE RESAMPLER FILTER BROADBAND FREQUENCY RESPONSE followed by the 15 tap filter operating at twice the first halfband s rate The 23 tap filter requires 7 multiplies and the 15 tap filter requires 5 multiplies to complete a filter calculation Using the interpolation halfband filters allows for reduction in the FIR filter sample rate This optimizes the use of the programmable FIR filter by allowing the FIR output sample rate to be closer to the Nyquist rate of the desired bandwidth Optimizing the FIR filter performance provides better use of the programmable FIR taps Table 10 details the maximum clocking rates for the possible resampling and interpolation halfband filter configurations of this section of
97. me 63 tap FIR impulse response If the FIR is set to decimate the FIR output will be repeated every sample time until a new value appears at the filter output i e the frequency samples are clocked out at the I Q sample rate regardless of decimation 37 intersil FN4450 4 May 1 2007 HSP50214B The FIFO mode allows the processor to service the interface only when enough samples are present in the RAM This mode is provided so that the uProcessor does not have to service the PDC every output sample An interrupt INTRRPT is asserted when the desired number of samples are available The PDC can be programmed to assert the interrupt when up to 7 samples are available Control Word 21 Bit 15 is used to set the Buffer RAM controller to the FIFO mode while Control Word 21 Bits 12 14 set the number of RAM samples to be stored 0 to 7 before the interrupt INTRRPT is asserted Control Word 20 Bit 24 determines whether the RAM output interface is the 8 bit microprocessor interface or the 16 bit processor interface In the 16 bit interface the MSByte is sent to AOUT 7 0 while the LSByte is sent to BOUT 7 0 The INTRRP output signal goes low for 8 PROCCLK cycles when the number of samples in the Buffer RAM depth reaches the programmed depth The depth of the RAM is calculated using Equation 23 A DSP microprocessor or the data processing engine can use the INTRRP signal to know that the RAM is ready to be read Dram
98. ming error information NOTE All of the clocks may be asynchronous PDC Applications Overview This section highlights the motivation behind the key programmable features from a communications system level perspective These motivations will be defined in terms of ability to provide DSP processing capability for specific modulation formats and communication applications The versatility of the Programmable Downconverter can be intimidating because of the many Control Words required for chip configuration This section provides system level insight to help allay reservations about this versatile DSP product It should help the designer capitalize on the greatest feature of the PDC VERSATILITY THROUGH PROGRAMMABILITY It is this feature when fully understood that brings the greatest return on design investment by offering a single receiver design that can process the many waveforms required in the communications marketplace FDM Based Standards and Applications Table 1 provides an overview of some common frequency division multiplex FDM base station applications to which the PDC can be applied The PDC provides excellent selectivity 7 intersil for frequency division multiple access FDMA signals This high selectivity is achieved with 0 012Hz resolution frequency control of the NCO and the sharp filter responses capable with a 255 tap 22 bit coefficient FIR filter The 16 bit resolution out of the Cartesian to Polar Coordinate C
99. n explanation of how data is loaded into the Master Registers for use internal to the part Note that for the AGC LOAD only the lower 16 bits require data be valid to ensure a proper write of an AGC Value that will be loaded on write to CONTROL WORD 26 CONTROL WORD 27 TEST REGISTER SYNCHRONIZED TO CLKIN BIT POSITION FUNCTION DESCRIPTION 31 25 Reserved A fixed value of 0000 000 is loaded here for normal operation 24 RAM Test Enable 0 Normal Operation 1 RAM Test Enabled The B Version includes test circuitry for the ROM and RAM blocks that was not present in the original release part This circuitry must be disabled before loading the coefficient This is done by setting bit 24 to zero Because the HSP50214 did not require a write to Control Word 27 and the HSP50214B does require that Control Word 27 Bit 24 be set to zero for normal operation software that was written for the HSP50214 will require modification to work properly with the HSP50214B 23 Input Level Detector 0 The two LSB s of the interpolation period preload are set to zero 22 Preload 1 The two LSB s of the interpolation period preload are set to one elec 22 SYNCIN1 Reset 0 SYNCIN1 causes only front end reset Control 1 SYNCIN1 causes front end and back end resets 21 Timing Error Input 0 Operates as HSP50214 Select 1 Corrects an error in the 4 LSB s 20 Timing NCO Reset 0 Backend reset will not clear the timing NCO phase accumulator feedback Control
100. ng 60 206 10 0 the two programmable mantissas and exponents The 54 185 9 0 mantissa M is a 4 bit value which weights the loop filter 48 165 8 0 input from 0 0 to 0 9375 The exponent E ue a a 42 144 7 0 factor that provides additional weighting from 2 to 2 36 124 6 0 Together the mantissa and exponent define the loop gain as given by 30 103 5 0 24 082 4 0 AGC Loop Gain M a2 205 407 EQ 16 2 1 where M is 4 bit binary value ranging from 0 to 15 and 12 041 2 0 is a 4 bit binary value ranging from 0 to 15 Table 7 and 6 021 1 0 8 detail the binary values and the resulting scaling effects of 0 000 0 0 the AGC scaling mantissa and exponent The composite shifter and multiplier AGC scaling Gain range is from TABLE 6B AGC LIMIT MANTISSA vs GAIN 0 0000 to 2 329 0 9375 2 0 0000 to 2 18344 The scaled GAIN dB EXPONENT MANTISSA gain error can range depending on threshold from 0 s000 7 E 2 18344 which maps to a gain change per sample range of 0 to 3 275dB sample 5 750 0 240 5 500 0 226 The AGC Gain mantissa and exponent values are i 215 programmed into Control Word 8 Bits 0 15 The PDC provides for the storing of two values of AGC Scaling Gain 5 000 0 199 both exponent and mantissa This allows for quick 4 750 0 185 adjustment of the loop gain by simply asserting the external 4 500 0 173 control line AGCGNSEL When AGCGNSEL 0 then AGC 4 250 0 161 GAIN 0 is selected and when AGCGNSEL
101. ng the coefficient 1 and all other coefficients CN 0 19 intersil FN4450 4 May 1 2007 HSP50214B Additionally the Programmable FIR filter provides for decimation factors R from 1 to 16 The processing rate of the Filter Compute Engine is PROCCLK As a result the frequency of PROCCLK must exceed a minimum value to ensure that a filter calculation is complete before the result is required for output In configurations which do not use decimation one input sample period is available for filter calculation before an output is required For configurations which employ decimation up to 16 input sample periods may be available for filter calculation For real filter configurations use Equations 11A and 11B to calculate the number of taps available at a given input filter sample rate TAPS fleorr PROCCLK Fgaup R R 1 11A SYM ODD for real filters and TAPS floor PROCCLK Fgayp R R 2 EQ 11B for complex filters where floor is defined as the integer portion of a number PROCCLK is the compute clock fs AMP the FIR input sample rate Decimation Factor SYM 1 for symmetrical filter 0 for asymmetrical filter ODD 1 for an odd number of filter taps 0 2 an even number of taps Use Equation 12A to calculate the maximum input rate Foamp PROCCLK R R floor Taps EQ 12A SYM ODD 1 SYM J for real filters and PROCCLK R
102. ntersil FN4450 4 May 1 2007 HSP50214B TABLE 20 EXAMPLE PROCESSOR WRITE SEQUENCE STEP A 2 0 C 7 0 COMMENT 1 000 0011 1000 Loads 38 into Master Register 7 0 on rising edge of WR 2 001 1101 0000 Loads DO into Master Register 15 8 on rising edge of WR 3 010 0001 1000 Loads 18 into Master Register 23 16 on rising edge of WR 4 011 0000 0000 Loads 00 into Master Register 31 24 on rising edge of WR 5 100 0000 0000 Load 0018D038 into Configuration Control Register O 6 Wait 4 CLKS CLK 1 2 WR l l l A20 KO AI A AS 0 2 seo a V V u LOAD LOAD ADDRESS OF LOAD NEXT CONFIGURATION TARGET CONTROL CONFIG DATA REGISTER AND URATION WAIT 4 CLKs REGISTER FIGURE 45 LOADING THE CONTROL REGISTERS WITH 32 BIT CONTROL WORDS Microprocessor Read Section The microprocessor read uses both read and write procedures to obtain data from the PDC A write must be done to location 5 to select the source of data to be read The read source is determined by the value placed on the lower three bits of C 7 0 The output from a particular read code is selected using a read address placed on A 2 0 The output is sent to C 7 0 on the falling edge of RD If the Read Address is equal to 111 the Read Code is ignored and the status bits shown in Ta
103. o 1 414 and the threshold is programmed in bits 28 16 The decimal value for the mantissa is calculated as DEC MMMM 16 Bit 15 is the MSB 11 8 Loop Gain 1 Selected when AGCGNSEL 1 These bits are EEEE See description of bits 15 12 Bit 11 is the MSB Exponent 7 4 Loop Gain 0 Mantissa Selected when AGCGNSEL 0 These bits are MMMM See description for bits 15 12 Same equations are used for Loop 0 Bit 7 is the MSB 3 0 Loop Gain 0 Selected when AGCGNSEL 0 These bits are EEEE See description for bits 15 12 Same equations Exponent are used for Loop 0 Bit 3 is the MSB 49 intersil FN4450 4 May 1 2007 HSP50214B CONTROL WORD 9 AGC CONFIGURATION 2 SYNCHRONIZED TO PROCCLK BIT POSITION FUNCTION DESCRIPTION 31 28 Reserved Reserved 27 16 Upper Limit Maximum Gain Minimum Signal The upper four bits are used for exponent the remaining bits form the mantissa in the fractional offset binary See the AGC Section for details Bit 27 is the MSB The gain is in dB G 6 02 eeee 20100 10 1 0 0 mnmmmmmmm GAIN dB 20 eeee Floor logo 10 J mmmmmmmm Floor 256 10GAIN 20 2 _ 1 15 12 Reserved Reserved 11 0 Lower Limit Minimum Gain Maximum Signal The upper four bits are used for exponent the remaining bits form the mantissa in the fractional offset binary eeeemmmmmmmn See the AGC Sect
104. offset frequency loaded serially via the COF and COFSYNC pins The offset frequency can be zeroed in Control Word 0 Bit 1 Both frequency control terms are 32 bits and the addition is modulo 232 The output frequency of the NCO is computed as 88 EQ 3 fo EQ 3 or in terms of the programmed value N INT IG 232 1 where is the 32 bit sum of the center and offset frequency terms fc is the frequency of the carrier NCO sinusoids fs is the input sampling frequency and INT is the integer of the computation See the Microprocessor Write Section on instructions for writing Control Word 3 TO MIXERS cos SIN CARRIER PHASE STROBET CARRIER PHASE OFFSET T CLEAR PHASE ACCUMT ENI COF ENABLE f CARRIER FREQUENCY STROBE 1 F d COFSYNC CARRIER LOAD ON COF SHIFT REG UPDATET CARRIER SYNC FREQUENCY SYNCIN1 CIRCUITRY fc Controlled via microprocessor interface FIGURE 12 BLOCK DIAGRAM OF NCO SECTION For example if is 3267 decimal and fs is 65MHz then fc is 49 44Hz If received data is modulated at a carrier frequency of 10MHz then the synthesizer mixer should be programmed for 27627627 hex 08908908 hex Because the input enable ENI controls the operation of the phase accumulator the NCO output frequency is computed relative to the input sample rate fs not to
105. oks like SEROUTA CONTROL WORD 19 FIELD start data word gt Q data word gt r data word gt end gt SEROUTA source data 000 Link following data 001 Link following Q data 010 SEROUTB CONTROL WORD 19 FIELD start Q data word gt r data word gt TBD data word gt end gt SEROUTB source data 001 Link following Q data 010 Link following r data TBD As shown by this example once Q was linked to r in the SEROUTA chain the SEROUTB chain must have r following Q if Q is selected Figure 35 illustrates the construction of the serial output streams If the serial data stream was changed to be a length of four data words then by default the SEROUTA would be whatever is selected for SEROUTB data word 3 SEROUTB would need to identify the fourth data word Thus SEROUTA and SEROUTB are not fully independent because they share the Q data word and by default the MAGNITUDE follows Q data link and whatever is selected for data word 3 to follow MAGNITUDE data in SEROUTB The other signals provided with the SEROUTA and SEROUTB are the SERSYNC and the SERCLK The SERSYNC signal can be programmed in either early or late sync mode The sync signal is pulsed active low or active high for each information word link of the chain of data created using Control Word 19 Figure 36 shows the four possible configurations of SERSYNC as programmed using Control Word 20 As previously discussed Control Word 20
106. om 1 to 8 samples Modulo 2 subtraction eliminates rollover problems in the subtraction at 2 The alias free discriminator frequency range is given by Rangerreapisc CW 0 1 EQ 22 where D is the discriminator delay defined in Equation 21 1 lt D lt 8 fSaMpouT is the Discriminator FIR filter output sample rate and CW is the desired center frequency When the phase multiplier is set to a value other than 20 the discriminator range is reduced proportionally The phase multiplier can be 1 2 4 or 8 20 to 23 Thus a multiply of 21 reduces the range by 2 a multiply of 2 reduces the range by 4 and a multiply of 23 reduces the range by 8 The FIR filter can be configured with up to 63 symmetric taps and up to 32 asymmetric taps In the symmetric mode the FIR can be configured for even or odd symmetry as well as with an even or odd number of filter taps Decimation is provided to allow more processing time for longer i e more taps filter structures PHASE INPUT PHASE MULTIPLIER 7 DISCRIMINATOR DELAY DISCRIMINATOR EN FIR COEFFICIENTS DISC FIR DECIMATION 63 FIR SYMMETRY TYPE FIR FIR SYMMETRY 1 FILTER FIR TAPS FREQ 15 0 2 s COMPLEMENT Controlled via microprocessor interface FIGURE 29 FREQUENCY DISCRIMINATOR BLOCK DIAGRAM The HSP50214B offers an expanded choice of signals to be filtered by the discriminator FIR The choices are 1 18 bits of
107. one CLK period prior to the first data bit 321 ASSERTION COFSYNC SOFSYNC DATA TRANSFERRED TO HOLDING REGISTER SHIFT COUNTER VALUE o 4 10 14 18 22 26 30 34 38 42 4 CLK TIMES lt Toti j gt B lt Tpit gt Tott gt Tott gt 6 50 54 Serial word width can be 8 16 24 32 bits wide TT Tp is determined by the COFSYNC COFSYNC rate FIGURE 14 HOLDING REGISTERS LOAD SEQUENCE FOR COF AND SOF SERIAL OFFSET FREQUENCY DATA NOTE Serial Data must be loaded MSB first and COFSYNC or SOFSYNC should not be asserted for more than one CLK cycle 14 intersil FN4450 4 May 1 2007 HSP50214B NOTE COF loading and timing is relative to CLKIN while SOF loading and timing is relative to PROCCLK NOTE Tp can be 0 and the fastest rate is with 8 bit word width The assertion of the COFSYNC or SOFSYNC starts a count down from the programmed word width On following CLKs data is shifted into the register until the specified number of bits have been input At this point the contents of the register are transferred from the Shift Register to the respective 32 bit Holding Register The Shift Register can accept new data on the following CLK If the serial input word is defined to be less than 32 bits it will be transferred to the MSBs of the 32 bit Holding Register and the LSBs of the Holding Register will be zeroed See Figure 14 for details CIC Decimation F
108. ons to the coordinate converter are 3a The data ready signal to the coordinate converter block when the resampler is bypassed This is the AGC output data ready signal 3b The data ready to the coordinate converter block when the resampler halfband filters are enabled This is the resampler halfband filter block output data ready signal The discriminator input is 18 bits and the output is rounded asymmetrically to 16 bits The phase into the discriminator can be multiplied by 20 21 22 or 23 modulo 2 to remove PSK data modulation All programmable parameters for the Frequency Discriminator are set in Control Word 17 Bits 15 and 16 are the phase multiplier which represents the shift applied to the input phase For CW the multiply should equal 20 00 BPSK QPSK 8PSK the multiply should equal 21 01 22 10 or 23 11 respectively Bit 14 is used to enable or disable the discriminator Bits 11 13 set the decimation in the programmable FIR filter Bit 10 sets the filter symmetry type as either odd or even bit 9 sets whether the filter is asymmetric or symmetric and bits 3 8 set the number of FIR filter taps Bits 0 2 set the number of delays in the frequency discriminator Output Section The Output Section routes the 7 types of processed signals to output pins in three basic modes These basic modes are Parallel Direct Output Serial Direct Output and the Buffer RAM Output The Serial and Parallel Direct Outp
109. onverter are routed to the frequency detector which is followed by a 63 tap 22 bit coefficient FIR filter structure for facilitating FM and FSK detection The 14 bit input resolution is the smallest bit resolution found throughout the conversion and filtering sections providing excellent dynamic range in the DSP processing A unique input gain scaler adds an additional 42 of range to the input level variation to compensate for changes in the analog RF front end receive equipment Synchronization circuitry allows precise timing control of the base station reconfiguration for all receive channels simultaneously Portions of this table were corroborated with reference 2 TABLE 1 CELLULAR PHONE BASE STATION APPLICATIONS USING FDMA AMPS MCS L1 NMT 400 ETACS STANDARD IS 91 MCS L2 NMT 900 C450 NTACS RX BAND 824 849 925 940 453 458 451 456 871 904 MHz 890 915 915 925 CHANNEL 30 25 0 25 20 0 25 0 BW kHz 12 5 12 5 10 0 12 5 4 TRAFFIC 832 600 200 222 1240 CHANNELS 1200 1999 444 800 VOICE FM FM FM FM FM MODULA TION PEAK 12 5 5 4 9 5 DEVIATION kHz CONTROL FSK FSK FSK FSK FSK MODULA TION PEAK 8 4 5 3 5 2 5 6 4 DEVIATION kHz CONTROL 10 0 3 1 2 5 3 8 CHANNEL RATE Kbps TDM Based Standards and Applications Table 2 provides an overview of some common Time Division Multiplexed TDM base station applications to which the PDC can be applied For time
110. ource 01 Phase 2 s complement 1X Magnitude O unsigned binary 19 Serial Output Sync 0 Normal Sync Mode active high Polarity 1 Sync Inverted active low 18 Serial Output Clock 0 Output Clock Inverted rising edge aligns with data transitions Polarity 1 Output Clock Normal falling edge aligns with data transitions 0 1 17 Serial Output Sync 0 Sync is asserted one bit time after the last bit of the serial word Late Mode Position 1 Sync is asserted one bit time prior to the first bit of the serial word Early Mode 16 14 Serial Out Clock 000 Serial Output at PROCCLK 16 Divider 001 Serial Output at PROCCLK 8 010 Serial Output at PROCCLK 4 011 Serial Output at PROCCLK 2 1XX Serial Output at PROCCLK rate 13 12 Data Serial Output 00 No Tag Bit LSB of word is passed Tag Bit 01 0 Tag Bit LSB of word is set to zero 1X 1 Tag Bit LSB of word is set to one 53 intersil FN4450 4 May 1 2007 HSP50214B CONTROL WORD 20 BUFFER RAM DIRECT PARALLEL AND DIRECT SERIAL OUTPUT CONFIGURATION SYNCHRONIZED WITH PROCCLK Continued BIT POSITION FUNCTION DESCRIPTION 11 10 Q Data Serial Output See Data Serial Output Tag selection above Tag Bit 9 8 Magnitude Data Serial See Data Serial Output Tag selection above Output Tag Bit 7 6 Phase Data Serial See Data Serial Output Tag selection abov
111. pe of data word should be used only once in each data stream If the Link following data is programmed with the data type identifier for I then the part will repeat the 1 data word until all of the data word locations are filled In Example 1 if bits 20 18 were erroneously programmed to 000 1 data then the SEROUTA would be four sequential repeats of the I data word Serial Output Configuration Example 2 It is desired to output only three data words on each serial output The data word followed by the Q data word followed by the Magnitude data word is to be output on SEROUTA The Q data word followed by the Magnitude data word followed by the one other data word to be output on SEROUTB The choices for the remaining data word in the SEROUTB signal are phase frequency AGC level and timing error Table 15 illustrates how Control Word 19 should be programmed TABLE 15 EXAMPLE 2 SERIAL OUTPUT CONTROL SETTINGS CONTROL WORD 19 BIT BIT POSITION FUNCTION VALUE RESULT 30 28 SEROUTA Data Source 000 1 27 25 SEROUTB Data Source 001 Q 24 21 Number of Serial Word 011 3 Links Chain 20 18 Link following data 001 Q 17 15 Link following Q data 010 14 12 Link following r data TBD TBD 11 9 Link following data XXX N A 8 6 Link following f data XXX N A 5 3 Link following AGC data XXX N A 2 0 Link following Timing XXX N A Error data The serial data stream lo
112. r ______ 0 8 4 _ PROCCLK DATARDY DRO NOTE land Q are sample aligned in time r and are sample aligned in time but one sample delayed from I The frequency sample is delayed in time from l or by 1 sample time 63 tap FIR impulse response If the FIR is set to decimate and frequency is selected for AOUT the DATARDY signal will be at the discriminator FIR output decimated rate FIGURE 33 DATARDY WAVEFORMS WHEN f FREQUENCY IS SELECTED AS AOUT 33 FN4450 4 intersil May 1 2007 HSP50214B Serial Direct Output Port Mode The Serial Direct Output Port Mode offers the ability to construct two serial output data streams SEROUTA AND SEROUTB from 16 bit magnitude phase frequency timing error and AGC level data words The total number of data words 1 to 8 for serial output and the sequential order of these data word components of the serial output are programmable Each data word may be used once in either the SEROUTA or SEROUTB data streams Figure 34 illustrates the conceptual implementation of the Serial Direct Output Port Mode In the Serial Direct Mode the output data is loaded into Serial Shift Registers and routed to two serial output pins SEROUTA and SEROUTB The serial output shift clock SERCLK is PROCCLK divided by 1 2 4 8 or 16 The divide down ratio is programmed using Control Word 20 Bits 14 16 The data is shifted out on the rising edge of the
113. r When only the Interpolation FIRs are used the full SNR range is passed FIGURE 24 25 intersil FN4450 4 May 1 2007 HSP50214B TABLE 9A BIT WEIGHTING FOR AGC LOOP FEEDBACK PATH AGC LOOP AGC AGC GAIN FILTER OUTPUT ACCUM GAIN ERROR AGC LOOP GAIN AND AGC AGC GAIN BIT ERROR BIT FILTER GAIN MULTIPLIER SHIFT SHIFT SHIFT SHIFT LIMITS BIT RESOLUTION POSITION INPUT WEIGHT MANTISSA OUTPUT 0 15 WEIGHT dB 31 2 2 2 2 0 30 2 2 2 2 E 3 48 29 2 2 2 2 E 2 24 28 2 2 2 2 E 1 12 27 12 2 2 2 2 2 2 E 0 6 26 11 1 2 2 2 1 1 3 25 10 0 0 0 2 2 2 0 M 2 1 5 24 9 zd x 1 2 2 2 1 M 3 0 75 23 8 2 x 2 2 2 2 2 M 4 0 375 22 7 3 x 3 2 2 2 3 M 5 0 1875 21 6 4 x 4 2 2 2 4 M 6 0 09375 20 5 5 5 2 2 2 5 7 0 04688 19 4 6 6 2 2 1 6 X 8 0 02344 18 3 7 7 2 2 0 7 9 0 01172 17 2 8 8 2 2 1 8 10 0 00586 16 1 9 9 2 2 2 9 11 0 00293 15 0 10 10 2 1 3 10 12 0 00146 14 11 2 0 4 11 13 0 000732 13 12 2 1 5 12 14 0 000366 12 13 2 2 6 13 15 0 000183 11 14 1 3 7 14 16 0 0000916 10 0 4 8 G 17 0 0000458 9 1 5 9 18 0 0000229 8 2 6 10 G 19 0 0000114 7 3 7 11 G 20 0 00000572 6 4 8 12 G 21 0 00000286 5 5 9 13 G 4 6 10 14 G 3 7 11 G G 2 8 12 G G 1 9 13 G G 0 10 14 G G AGC Input Cart PolarGain Error Det Gain AGC Loop Output Weighting
114. rtesian to Polar Converter The Cartesian to Polar converter computes the magnitude and phase of the vector The and inputs 18 bits The converter phase output is 18 bits truncated with the 16 MSB s routed to the output formatter and all 18 bits routed to the frequency discriminator The 16 bit output phase can be interpreted either as two s complement 0 5 to approximately 0 5 or unsigned 0 0 to approximately 1 0 as shown in Figure 28 The phase conversion gain is 1 27 The phase resolution is 16 bits The 16 bit magnitude is unsigned binary format with a range from 0 to 2 32 The magnitude conversion gain is 1 64676 The magnitude resolution is 16 bits The MSB is always zero Table 11 details the phase and magnitude weighting for the 16 bits output from the PDC The magnitude and phase computation requires 17 clocks for full precision At the end of the 17 clocks the magnitude and phase are latched into a register to be held for the next stage either the output formatter or frequency discriminator If a new input sample arrives before the end of the 17 cycles the results of the computations up until that time are latched This latching means that an increase in speed causes only a decrease in resolution Table 12 details the exact resolution that can be obtained with a fixed number of clock cycles up to the required 17 The input magnitude and phase errors induced by normal SNR values will almost always be worse
115. s 32 Bit Programmable NCO for Channel Selection and Carrier Tracking Digital Resampling Filter for Symbol Tracking Loops and Incommensurate Sample to Output Clock Ratios Digital AGC with Programmable Limits and Slew Rate to Optimize Output Signal Resolution Fixed or Auto Gain Adjust Serial Parallel and FIFO 16 Bit Output Modes Cartesian to Polar Converter and Frequency Discriminator for AFC Loops and Demodulation of AM FM FSK and DPSK Input Level Detector for External AGC Support Pb Free Plus Anneal Available ROHS Compliant Applications Single Channel Digital Software Radio Receivers Base Station Rx s AMPS NA TDMA GSM and CDMA Compatible with HSP50210 Digital Costas Loop for PSK Reception Evaluation Platform Available PART NUMBER PART MARKING TEMP RANGE C PACKAGE PKG DWG NO HSP50214BVC HSP50214BVC 0 to 70 120 4 Q120 28x28 HSP50214BVCZ Note HSP50214BVCZ to 70 120 Ld MQFP Pb free 0120 28 28 HSP50214BVI HSP50214BVI 40 to 85 120 4 MQFP Q120 28x28 HSP50214BVIZ Note HSP50214BVIZ 40 to 85 120 Ld MQFP Pb free 0120 28 28 NOTE Intersil Pb free plus anneal products employ special Pb free material sets molding compounds die attach materials and 100 matte tin plate termination finish which are RoHS compliant and compatible with both SnPb and Pb free soldering operations Intersil Pb free products are MSL classified at Pb free peak reflow temp
116. s Number of FIR taps from 1 to 63 where 00000 is not valid 00001 1 tap 00010 2 taps etc up to 11111 63 taps Bit 8 is the MSB 2 0 Discriminator Delay Sets the number of delays from 1 to 8 in the discriminator Set delay ddd to delay minus 1 where 000 represents 1 delay 001 represents 2 delays 010 represents 3 delays 011 represents 4 delays 100 represents 5 delays 101 represents 6 delays 110 represents 7 delays and 111 represents 8 delays If ddd the decimal representation bits 2 0 then the discriminator a transfer function H Z 1 z ddd 1 CONTROL WORD 18 TIMING ERROR PRELOADS SYNCHRONIZED PROCCLK BIT POSITION FUNCTION DESCRIPTION 31 28 Reserved Reserved 27 16 NCO Divide The Re Sampler NCO output is divided down by the value loaded into this register plus 1 Load with a value that is one less than the desired period Bit 27 is the MSB 11 0 Reference Divide The reference clock is divided down by the value loaded into this register plus 1 Load with a value that is one less than the desired period Bit 27 is the MSB A minimum preload of I is required CONTROL WORD 19 SERIAL OUTPUT ORDER SYNCHRONIZED TO PROCCLK BIT POSITION FUNCTION DESCRIPTION 31 Reserved Reserved 30 28 Data Source for Serial Output A Source The serial data source is selected using Table 12 see Output Section SEROUTA 27 25 Data Source for Serial Output B Source The serial data source is selected using Table 12 see Output Section SEROUTB
117. sampling frequency then Equation 10 shows the minimum ratio needed fPROCCLK fs gt 7 HB5 2 P5 EQ 10 where HB1 1 if this section is selected and 0 if it is bypassed HB2 1 if this section is selected and 0 if it is bypassed HB3 1 if this section is selected and 0 if it is bypassed 4 1 if this section is selected and O if it is bypassed HB5 1 if this section is selected and O if it is bypassed T number of Halfband Filters Selected The range for T is from 0 to 5 Examples of PROCCLK Rate Calculations Suppose we enable HB1 HB3 and HB5 Using Figure 16 HB1 1 HB3 1 and HB5 1 Since stage 2 and stage 4 are not used 2 and HB4 0 PROCCLK must operate faster than 7x2 5x4 3x8 8 7 25 times faster than fs If all five halfoands are used then PROCCLK must operate at 7 2 6 4 5 8 4 16 3 32 32 7 4375 times faster than 255 Tap Programmable FIR Filter The Programmable FIR filter can be used to implement real filters with even or odd symmetry using up to 255 filter taps or complex filters with up to 64 taps The FIR filter takes advantage of symmetry in coefficients by summing data samples that share a common coefficient prior to multiplication In this manner two filter taps are calculated per multiply accumulate cycle Asymmetric filters cannot share common coefficients so only one tap per multiply accumulate cycle is calculated The filter can be effectively bypassed by setti
118. synchronizing multiple parts when CLKIN and PROCCLK asynchronous MSYNCO is the synchronization signal between the input section operating under CLKIN and the back end processing operating under PROCCLK This output sync signal from one part is connected to the MSYNCI signal of all the HSP50214Bs MSYNCI Multiple Chip Sync Input The MSYNCI pin of all the parts should be tied to the MSYNCO of one part NOTE MSYNCI must be connected to an MSYNCO signal for operation SYNCIN1 CIC Decimation Carrier NCO Update Sync Can be used to synchronize the CIC Section carrier NCO update or both See the Multiple Chip Synchronization Section and Control Word 0 in the Microprocessor Write Section Active High SYNCIN2 FIR Timing NCO Update AGC Gain Update Sync Can be used to synchronize the FIR Timing NCO update AGC gain update or any combination of the above See the Multiple Chip Synchronization Section and Control Words 7 8 and 10 in the Microprocessor Write Section Active High SYNCOUT Strobe Output This synchronization signal is generated by the uP interface for synchronizing multiple parts be generated by PROCLK or CLKIN see Control Word 0 and Control Word 24 in the Microprocessor Write Section Active High FN4450 4 5 i i intersil May 1 2007 9 JESU 2002 v OSPPNA AGCGNSEL TO OUTPUT FORMATTER PROCCLK AND MICROPROCESSOR INTERFACE GAINADJ 2 0
119. t allows the output of the 255 tap programmable FIR filter to be routed directly to the coordinate converter Rather than having to select only 18 bits out of the available 26 bit output all 26 bits of the FIR output are routed to the coordinate converter This change eliminates quantization effects to give more accuracy in the phase and frequency discriminator outputs The AGC settling time is not a factor because the AGC is effectively bypassed for the magnitude phase and frequency computations NOTE The most significant 18 bits of the computed phase are still routed to the discriminator 30 intersil FN4450 4 May 1 2007 HSP50214B One caveat to selecting the FIR outputs to be routed directly to the coordinate converter is that because the samples for the coordinate conversion are chosen from before the resampler the magnitude and phase samples will not align with the samples if the resampler or interpolation halfband filters are used This optional signal routing mode was intended for FM or for burst PSK where a fixed decimation can be used It is also applicable when resampling or timing adjustments on the demodulated samples are done in a processor following PDC The magnitude resolution may suffer because there is no gain adjustment before computing the magnitude If the signal is lt 90dBFS it will be below the LSB of the magnitude output The enable signal for gating data into the coordinate conv
120. t half of the available bandwidth The first halfband or HB1 has 7 taps The remaining halfbands HB2 HB3 HB4 and HB5 have 11 15 19 and 23 taps respectively The coefficients for these halfbands are given in Table 4 Figure 18 shows the frequency response of each of the halfband filters with respect to normalized frequency FN Frequency normalization is with respect to the input sampling frequency of each filter section Each stage is activated by their respective bit location 15 20 in Control Word 7 Any combination of halfband filters may be used or all may be bypassed 16 intersil FN4450 4 May 1 2007 HSP50214B 15 LN E EF zo zo oo OUTPUT SHIFTER BITS TAKEN WHEN IS BYPASSED NOTE If 14 input bits are not needed the gain adjust can be in creased by one for each bit that the input is shifted down at the input For example if only 12 bits are needed an offset range of 24dB is possible for a decimation of 24 FIGURE 16 CIC FILTER BIT WEIGHTING Since each halfband filter section decimates by 2 the total decimation through the halfband filter is given by 2 EQ 9 where Number of Halfband Filters Selected 1 5 HALFBAND FILTER INPUT FN fs HALFBAND FILTER 1 CONTROL WORD 7 BIT 15 FN fs OR 5 2 CONTROL WORD 7 BIT 16 FN Fug2 CONTROL
121. t these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE 4 Oja is measured with the component mounted on an evaluation PC board in free air DC Electrical Specifications Voc 5 5 Ta 0 C to 70 C Commercial 40 C to 85 C Industrial PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage Vcc 5 25 2 0 V Logical Zero Input Voltage Voc 4 75V E 0 8 V Clock Input High Voc 5 25V 3 0 V Clock Input Low Voc 4 75V 0 8 V Output High Voltage VoH loH 400 Voc 4 75V 2 6 V Output Low Voltage VoL loL 2 0mA Voc 4 75V 0 4 V Input Leakage Current Vin Voc GND Vcc 5 25V 10 10 Standby Power Supply Current Vcc 5 25V Outputs Not Loaded 500 Output Leakage Current lo Vin Voc or GND 5 25V 10 10 Operating Power Supply Current CLK PROCCLK 52 2 Vin Vcc or 420 mA GND Note 5 Voc 5 25V Outputs Not Loaded Input Capacitance Cin Freq 1MHz Vcc open all measurements 8 pF Output Capacitance Cour are referenced to device ground Note 6 NOTES 5 Power Supply current is proportional to operation frequency Typical rating for is 7MA MHz 6 Capacitance Ta 25 C controlled via design or process parameters and not directly tested Characterized upon init
122. than the Cartesian to Polar conversion TABLE 12 MAG PHASE ACCURACY vs CLOCK CYCLES TABLE 11 MAG PHASE BIT WEIGHTING MAGNITUDE PHASE PHASE ERROR ERROR ERROR CLOCKS 26 fg DEG fg 6 0 065 3 5 2 T 0 016 1 8 1 8 0 004 0 9 0 5 9 0 004 0 45 0 25 10 0 004 0 22 0 12 11 lt 0 004 0 11 0 062 12 lt 0 004 0 056 0 03 13 lt 0 004 0 028 0 016 14 lt 0 004 0 014 0 008 15 lt 0 004 0 007 0 004 16 lt 0 004 0 0035 0 002 17 lt 0 004 0 00175 0 001 BIT MAGNITUDE PHASE 15 MSB 22 Always 0 180 14 21 90 13 20 45 12 21 22 5 11 2 11 25 10 23 5 625 9 24 2 8125 8 25 1 40625 7 26 0 703125 6 27 0 3515625 5 28 0 17578125 4 29 0 087890625 3 2 10 0 043945312 2 271 0 021972656 1 212 0 010986328 0 LSB 2 13 0 005483164 4000 40004 Sfff bfff 000 bfff 000 2 2 FIGURE 28 PHASE BIT MAPPING OF COORDINATE CONVERTER OUTPUT Assumes 180 fs In the HSP50214 the input to the coordinate converter to r 0 block is 18 bits If the signal range is large and the AGC is not used the quantization noise can become a contributing factor in the phase and frequency computations For example if the signal range is 84dB and the maximum signal is set at full scale the minimum signal would have only 4 bits each for and Q In the HSP50214B an additional data path option was added tha
123. the FIR output will be repeated every sample time until a new value appears at the filter output i e the frequency samples are clocked out at the I Q sample rate regardless of decimation TABLE 13 LINKING CONTROL WORDS FOR SERIAL OUTPUT DATA TYPE IDENTIFIER DATA TYPE 000 Data 001 Q Data 010 Magnitude MAG Data 011 Phase PHAS Data 100 Frequency FREQ Data 101 Timing Error TIMER Data 110 AGC Gain 111 Zeros Two examples will illustrate the process of configuring a serial output using the Serial Output mode The serial data stream looks like SEROUTA CONTROL WORD 19 FIELD start data word gt SEROUTA source data 000 Q data word gt Link following data 001 data word gt Link following Q data 011 Zero data word gt Link following data 111 end gt SEROUTB CONTROL WORD 19 FIELD start r data word gt SEROUTB source data 010 f data word gt Link following r data 100 TE data word gt AGC data word gt Link following f data 101 Link following TE data 110 34 intersil FN4450 4 May 1 2007 HSP50214B SEROUTB CONTROL WORD 19 FIELD end gt AGC DATA SERIAL OUTPUT TAG BIT T TIMING ERROR DATA SERIAL OUTPUT TAG BIT T FREQUENCY DATA SERIAL OUTPUT TAG BIT T PHASE DATA SERIAL OUTPUT TAG BIT T MAGNITUDE DATA SERIAL OUTPUT TAG BIT T Q DATA SERIAL OUTPUT TAG BIT T SOURCE I DATA SERIAL OUTPUT TAG BIT T DATA SOURCE FOR SEROUTA T
124. to output 8x baud rate or 4x bit rate The CIC and halfband filter responses are shown in Figures 48A and 48B The composite filter response constrained primarily by halfband filter 5 and the FIR filter are shown in Figure 48C and 48D For a more detailed discussion of design approaches and trades when designing with the PDC refer to AN9720 3 Calculating the Maximum Processing Rates of the PDC References For Intersil documents available on the web see www intersil com 1 HSP50210 Data Sheet Intersil Corporation FN3652 2 Cellular Radio and Personal Communications A Book of Selected Readings Theodore S Rappaport 1995 by IEEE Inc 3 AN9720 Application Note Intersil Corporation Calculating Maximum Processing Rates of the PDC HSP5021 4B 4 FO 007 Block Diagram of HSP50214 45 intersil FN4450 4 May 1 2007 HSP50214B intersil 10 10 10 10 730 30 m m lt B a 50 8 50 5 5 5 5 g 70 g 70 90 90 110 110 fg CIC INPUT RATE fg CIC INPUT RATE 130 130 FREQUENCY fs FREQUENC
125. ut modes were designed to output data strobes and real time continuous streams of data The Buffer RAM Output mode outputs data upon receipt of an asynchronous request from an external DSP processor or other baseband processing engine The use of the interrupt signal from the Programmable Down Converter in conjunction with the request strobes from the controller ensures that data is transferred only when both the controller and the Programmable Down Converter are ready The Buffer RAM output can be operated in a First In First Out FIFO or SNAPSHOT mode with the data output either via the 8 bit processor interface or a 16 bit processor interface Parallel Direct Output Port Mode The Parallel Direct Output Port Mode outputs two 16 bit words AOUT and BOUT of real time data Figure 30 details the parallel output circuitry Selection of the data source for the AOUT and BOUT parallel outputs is done via Control Word 20 Bits 22 23 and 20 21 respectively The AOUT port can output Magnitude or Frequency data The BOUT port can output Phase or Magnitude data The upper bytes of AOUT and BOUT are always in the parallel direct mode The 16 bit parallel direct mode is selected by setting Control Word 20 Bit 25 to zero The DATARDY output is asserted during the first clock cycle of the new data on the AOUT bus The rate at which the data out of the HSP50214 transitions and the rate at which DATARDY is asserted can be different
126. value of the threshold minus the magnitude is smaller Also the settling can be asymmetric where the loop may settle faster for over range signals than for under range signals or vice versa In some applications such as burst signals or TDMA signals a very fast settling time and or a more predictable settling time is desired The AGC may be turned off or slowed down after an initial AGC settling period To minimize the settling time a median AGC settling mode has been added to the HSP50214B This mode uses a fixed gain adjustment with only the direction of the adjustment controlled by the gain error This makes the settling time independent of the signal level For example if the loop is set to adjust 0 5dB per output sample the loop gain can slew up or down by 16 in 16 symbol times assuming a 2 samples per symbol output sample rate This is called a median settling mode because the loop settles to where there is an equal number of magnitude samples above and below the threshold The disadvantage of this mode is that the loop will have a wander dither equal to the programmed step size For this reason it is advisable to set one loop gain for fast settling at the beginning of the burst and the second loop gain for small adjustments during tracking The median settling mode is enabled by setting Control Word 27 Bit 16 to a logic one If Control Word 27 Bit 16 is zero the mean loop settling mode is selected and the loop
127. ve CONTROL WORD 5 CARRIER FREQUENCY STROBE SYNCHRONIZED TO CLKIN BIT POSITION FUNCTION DESCRIPTION N A Carrier Frequency Writing to this address updates the carrier frequency Control Word from the Holding Register Strobe CONTROL WORD 6 CARRIER PHASE STROBE SYNCHRONIZED TO CLKIN BIT POSITION FUNCTION DESCRIPTION N A Carrier Phase Strobe Writing to this address updates the carrier phase offset Control Word with the value written to the phase offset PO register 48 Intersil FN4450 4 May 1 2007 HSP50214B CONTROL WORD 7 HB FIR CONFIGURATION SYNCHRONIZED TO PROCCLK BIT POSITION FUNCTION DESCRIPTION 31 22 Reserved Reserved 21 Enable External 0 The 2 pin has no effect on the halfband and FIR filters Filter Sync 1 When the SYNCIN2 pin is asserted the filter control circuitry in the halfband filters the FIR the resampler and the discriminator are reset SYNCIN2 can be used to synchronize the computations of the filters in multiple parts for the alignment see Synchronization Section 20 Halfband HB 1 Bypass Halfband Filters Bypass 0 Enable HB Filters at least one HB must be enabled 19 HB5 Enable 0 Disables HB number 5 the last in the cascade 1 Enables HB filter number 5 18 HB4 Enable Setting this bit enables HB filter number 4 17 HB3 Enable Setting this bit enables HB filter number 3 1
128. ve the same source SYNCIN1 and SYNCIN can be tied together However if different enabling is desired for the front end and backend processing of the PDC s these signals can still be controlled independently In the HSP50214B the Control Word 25 reset signal has been extended so that the front end reset is 10 CLKIN periods wide and the back end reset is 10 PROCCLK periods wide This guarantees that no enables will be caught in the pipelines In addition the SYNCIN1 internal reset signal which is enabled by setting Control Word 7 Bit 21 1 has been extended to 10 cycles In summary SYNCIN1 is used to update carrier phase offset update carrier center frequency reset CIC decimation counters and reset the carrier NCO clear the feedback in the NCO SYNCIN2 is used to reset the HB filter FIR filter re sampler HB state machines and the output FIFO load a new gain into the AGC and load a new re sampler NCO center frequency and phase offset Input Section The block diagram of the input controller is provided in Figure 3 The input can support offset binary or two s complement data and can be operated in gated or interpolated mode see Control Word 0 from the Microprocessor Write Section The gated mode takes one sample per clock when the input enable ENI is asserted The gated mode allows the user to synchronize a low speed sampling clock to a high speed CLKIN The interpolated mode allows the user to input data at a low sampl
129. works identically to the HSP50214 In the median mode the loop works as follows The sign of the true gain error selects a fixed gain error of 0010000000000 1110000000000 24 intersil FN4450 4 May 1 2007 HSP50214B These gain error values are scaled by the programmable AGC loop gains to adjust the data path gain The maximum slew rate is 1 5dB per output sample See Equation 18 In order to fully evaluate the dynamic range of the PDC Table 9B is provided which details the bit weighting from the input to the AGC Multiplier Re Sampler Halfband Filter The re sampler is an NCO controlled polyphase filter that allows the output sample rate to have a non integer relationship to the input sample rate The filter engine can be viewed conceptually as a fixed interpolation filter followed by an NCO controlled decimator The prototype polyphase filter has 192 taps designed at 32 times the input sample rate Each of the 32 phases has 6 filter taps 6 32 192 The stopband attenuation of the prototype filter is greater than 60dB as shown in Figure 24 The signal to total image power ratio is approximately 55dB due to the aliasing of the interpolation images The filter is capable of decimation factors from 1 to 4 If the output is at least 2x the baud rate the 32 interpolation phases yield an effective sample rate of 64x the baud rate or approximately 1 5 1 64 maximum timing error Following the Re samp

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