Boot Sequencer
Contents
1. Course Introduction Purpose e This course introduces the PowerQUICC III 12C bus and describes some uses and features of the boot sequencer for the PowerQUICC III Objectives e Describe the PowerQUICC III 12C bus e Initialize the boot sequencer e Identify the EEPROM format to use with the boot sequencer e Compare and contrast standard 12C and extended IC e Identify the boot sequencer generator tool e Explain the importance of the boot sequencer tool to PowerQUICC lll using a burstable flash example Content e 23 pages e 4 questions Learning Time e 35 minutes This course introduces the PowerQUICC III 12C bus and describes some uses and features of the boot sequencer for the PowerQUICC III Next this course shows how to initialize the boot sequencer what kind of EEPROM format is required to use the boot sequencer and some of the differences between standard I C and extended I C Also this course introduces the boot sequencer generator which helps simplify data for translation into the proper EEPROM format Finally the course contains a general burstable flash example to demonstrate why you might want to use the boot sequencer on the PowerQUICC III I2C Controller Features e Two wire serial bi directional bus e Multi master operational e Arbitration lost interrupt with automatic switch from master to slave e Calling address identification interrupt e START and STOP signal generation and detection2. UPM Programming Wj Mmm adatos gt gt E poa AMA A XO OOH _E lt X COE A SST ey Burst Read x32 UPM Programming BRO addr FF70 5000 ORO addr FF70 5004 Program RAM array e MAMR addr FF70 5070 e MDR addr FF70 5088 Here you can see a burstable flash example If we want to program the UPM to talk to the burstable flash you need to set the BRO register and the ORO register Then you program the RAM array Here you can see sample addresses shown These are the addresses for the BRO register the ORO register and two others that you need to program the RAM array UPM Bus Signals De mux Here you can see one example of how to connect to the burstable flash The UPM bus signals are on the left and connected to the burstable flash on the right Question Which of the following options describe the boot sequencer generator Select all that apply and then click Done It enables PowerQUICC II to use burstable flash It makes it easier to program the EEPROM in the specified format declared in the user manual and in this course It enables use of burstable flash on PowerQUICC III It generates only one file a raw data file with the correct EEPROM format preamble and a CRC Consider this question regarding the boot sequencer generator Correct The boot sequencer generator makes it easier to program the EEPROM in the sp
3. 64 KB 1 block only Number of registers we are able to configure is limited by size of EEPROM Procedure Addresses first CONT must be set If last register is not detected before EEPROM and reads to 1 for first read wrapping back to first address entire memory up to then 0 after read error condition is detected and 64KB hreset_req is triggered Here you can see the extended I C mode which is only available on the boot sequencer not on the regular I2C block Extended I2C mode supports a maximum of one EEPROM and has 16 address bits The maximum size is 64 KB in one block only The number of registers you can configure in this mode is only limited by the EEPROM s size up to 64 KB The procedure is quite similar to the standard I C mode It starts at the first EEPROM and it reads the entire memory up to 64 KB The difference is it will never go on to the other EEPROM since it only supports one EEPROM on the bus What it will read is the CONT bit and the CONT bit is always one if you have more registers to program At the last frame it will see that the CONT bit will be zero Once again if the last register is not detected before wrapping back to the first address an error condition will be on the hreset_req pin Question What is one of the important differences between standard I C and extended I C Select the correct response and then click Done a Extended I C can support several EEPROMs standard 12C can
4. boot sequencer is initialized if enabled Finally wait for the boot sequencer to complete then simultaneously perform the remaining four activities Boot Sequencer EEPROM Format ACS BYTE_EN CONT ADDRJ0 1 ADDR 2 9 ADDR 10 17 z Byte gt DATA 0 7 DATA 8 15 AA DATA 16 23 DATA 24 31 55 AA Preamble 0000 0000 0000 0000 Device specific reference manuals that 0000 0000 can be ordered or downloaded from the CRC 0 7 web CRC 8 15 e MPC8560 PowerQUICC III Integrated CRC 16 23 Communications Processor Reference Manual CRC 24 31 e MPC8540 PowerQUICC III Integrated Host Last Frame Processor Reference Manual Here you can see the format in which you need to program the EEPROM to run the boot sequencer Three bytes make up the preamble The first data that the boot sequencer must see are these three bytes AA 55 and then AA Next are the register inputs and each register input has 7 bytes So you can think of it as a set of 7 bytes for each register For example if you have seven registers then you need 49 bytes for these register preloads After you finish the last register you re going to end the transmission and the EEPROM data with this last frame format This last frame format is very specific and the first three bytes must be zero The last four bytes will be a 32 bit CRC val
5. can set the bits ALTCAR 0 8 11 31 en TRGT_ID TRGT_ID Identifies device ID to target when a transaction hits in the 1 MB address range defined 0000 PCI PCI X 0100 Local bus controller 1100 RapidlO 1111 Local memory DDR SDRAM SRAM This is the Alternate Configuration Attribute Register ALTCAR which declares which device will be targeted when the transaction hits whether it s a register in the PCI space in the RapidlO or going on the local bus Click TRGT ID to see a table showing how you can set the bits BYTE_EN Bit and CONT Bit ACS ADDR 0 1 Byte gt ADDR 2 9 ADDR 10 17 AA DATA 0 7 DATA 8 15 as AREA AA ATA 24 31 Preamble 0000 0000 0000 0000 Byte enable support 0000 0000 Continue CONT clear for last CRC 0 7 transaction with CRC CRC 8 15 Only 18 bit address offset needed CRC 16 23 Big Endian CRC 24 31 12 bits will be prepended dependent on Last Frame ACS or entry in CCSRBAR Remaining bits are covered by the Byte enables Let s look at the byte enable BYTE_EN bit and the continue CONT bit The BYTE_EN is four bits and it lets you choose the byte you want to program If you have extra registers to program you need to set the CONT bit to one In the l
6. Ms must be addressed sequentially from that address I2C EEPROM Addressing MPC85x0 12C Here you can see an example of how the EEPROM would look on the 1 C bus EEPROM is on the left and then on the right are the DDR DIMMs which also have some SPD pins that hook into the 12C bus The EEPROM address is going to start at zero and some of the memories you have on the bus such as DDR DIMMs may start from seven or six Standard 12C Procedure Mouse over each box to learn more For standard I C the C will first address the first EEPROM address zero and it will read 256 bytes Then it will send a repeated start command and it will address the next EEPROM address at address one Next it will continue until it reads the last register and gets the last frame format If that last frame happens to be on the second or third EEPROM then at the end of the first EEPROM it will see the CONT bit set If the last register isn t detected before wrapping back to the first address and before the I C tries to get back to the first EEPROM it creates another error condition that will manifest on the hreset_req pin Seco ote EEPROM map Here you can see the I C standard procedure Roll your mouse pointer over each box in the diagram to learn more about each step in the procedure Extended I C Available in Boot Sequencer Mode Support for 1 EEPROM on bus 16 address bits Maximum size
7. ast frame the first three bytes including the continue bit is zero This will tell the boot sequencer that this is the last frame A 32 bit CRC follows after the three bytes of zeros A standard address is 32 bits Only 18 bits of address are needed here because 12 bits are either coming from the CCSRBAR register or the ALTCBAR register The remaining two bits are covered by the four bits of byte enable earlier in the packet CRC 32 CRC 32 1 x1 x24 x 44 54 74 8 1041 1 x 124 164224 234426432 e CRC should cover all bits stored in EEPROM prior to the CRC including Preamble Register preloads First 3 bytes of last frame all 0 s e If preamble or CRC fails IC asserts error signal Error triggers external hard reset request hreset_req pin In the last frame format the last 32 bits are CRC The boot sequencer s EEPROM format uses a 32 bit CRC and this is the polynomial that describes it The polynomial can also be found in the reference manual The CRC calculation should start with a value of OxFFFF FFFF The final XOR value is 0x0000 0000 It s important to note that when you calculate the CRC the CRC should cover all the bits stored in the EEPROM including the preamble all the register preloads and the first three bytes of the last frame If for any reason the CRC does not match up with what the PowerQUICC III expects the 1 C bus will assert an error signal and this error signal wil
8. ddress e It can configure the chip to perform non standard operations Initialize external memories Change default register values Boot from burstable flash DDR L2 Standard I C support e Extended I2C support Alternate Configuration Space ACS Mapping Can be used to write to external memories Boot sequencer executes before time zero if enabled What is the boot sequencer and why would you use it This functionality is new in PowerQUICC III It is used before the boot code is loaded into the chip It allows you to configure the registers in any memory mapped address This is a powerful feature because you can change any memory mapped register before you run boot code For example you can configure the chip to perform any non standard operation such as initializing external memories changing default register values or configuring it to boot from burstable flash double data rate DDR or L2 cache Previously PowerQUICC did not support these boot methods The boot sequencer supports the extended I2C and the standard 12C protocols The Alternate Configuration Space ACS Mapping feature is used to write to external memory It allows you to write to a register that does not reside in the chip t is still a memory mapped register but it resides in some external memory If the start of boot code execution is time zero then the boot sequencer executes before time zero With the boot sequencer y
9. e Bus busy detection e Software programmable clock divider from 160 to 32 768 Core Complex Bus CCB cycles e Software selectable acknowledge bit e On chip filtering of SDA and SCL inputs e Standard I C support Boot sequencer mode support Standard I C Extended IC Let s look at the features of the I C controller The 1 C bus is a very simple very direct two wire serial bi directional bus It has a data signal and a clock signal It can operate with multi masters and if you lose arbitration you will receive a lost arbitration interrupt with an automatic switch from master to slave It also provides a calling address identification interrupt In addition there is a standard START and STOP signal generation and detection and a bus busy detection A software programmable clock divider allows you to divide down from the Core Complex Bus CCB clock You can choose a divider between 160 and 32 768 Choose whichever divider you like and you re ready to go In addition some other standard features are a software selectable acknowledge bit and on chip filtering of the data and clock inputs SDA corresponds to the serial data signal and the SCL is the serial clock Standard I C protocol is supported on the I C block When it is in boot sequencer mode however it supports both standard I2C and extended 1 C mode Boot Sequencer e It is used before boot code is loaded to configure registers in any memory mapped a
10. ecified format declared in the reference manual and in this course It also enables use of burstable flash on PowerQUICC III Finally it generates two files a raw data file with the correct EEPROM format preamble and a CRC and a second file which is the same except in S record format Course Summary Boot sequencer Runs before boot code Used to change default register values Supports Standard or Extended 12C Boot sequencer generator Produces S record format and raw EEPROM format files Allows PowerQUICC III to support burstable flash This course introduced the PowerQUICC III I C bus and described some uses and features of the boot sequence for the PowerQUICC III You can run the boot sequencer before boot code is run to change the values of default registers Next this course described the power on sequence and how to initialize the boot sequencer as well as the EEPROM format and some of the differences between standard I C and extended I C Finally this course demonstrated how the boot sequence generator which helps simplify data for translation into the proper EEPROM format can be used advantageously to facilitate PowerQUICC IIl s use of burstable flash
11. er on reset configuration The two power on reset configuration pins that control the boot sequencer are called LGPL3 and LGPL5 and together they tell PowerQUICC III whether to enable the boot sequencer in standard I C addressing mode enable the boot sequencer in extended I C mode or disable the boot sequencer The default setting for these pins is 11 which indicates it will not use the boot sequencer at all or it will be disabled Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Question Order the steps of the power on sequence by dragging the items on the left to their corresponding boxes on the right and then click Done Power is applied to meet the voltage specifications HRESET is negated after required hold time HRESET is asserted and TRST is asserted E Stable SYSCLK is applied PLLs and DLLs to e500 core and CPM are locked Wait for boot sequencer to complete then simultaneously enable external PCI accesses initiate RapidlO training enable e500 core to begin its boot process and assert Ready Signal Boot sequencer is initialized if enabled Done Show nesel Solution Let s review the power on sequence Correct First power is applied to meet the voltage specifications second HRESET and TRST are asserted Third stable SYSCLK is applied and fourth HRESET is negated after required hold time Fifth PLLs and DLLs to e500 core and CPM are locked and sixth the
12. l be on the hreset_req pin If the preamble fails right away then it will also assert the same error signal on the hreset_req pin At this point the boot sequencer will halt A hard reset is required to restart the boot sequencer Question Is the following statement true or false Click Done when you are finished The ACS bit allows the boot sequencer to access any kind of register not in the local memory The normal base address is set by a register called CCSRBAR but with ACS the base address set by the ALTCBAR is used True False Consider this question regarding EEPROM formatting Correct The ACS bit allows the boot sequencer to access any kind of register not in the local memory The normal base address is set by a register called CCSRBAR but with ACS the base address set by the ALTCBAR is used Standard I2C Supports up to eight EEPROM blocks on bus 3 Chip Enable bits Maximum EEPROM size 2KB 256B each block First EEPROM must be addressed 0x1010 0000 Other EEPROMs must be addressed sequentially Here are some of the basic features of standard IC bus How much data can be put into the boot sequencer In standard 1 C mode it supports up to eight EEPROM blocks on the bus using three chip enable bits The maximum EEPROM size is 2 KB with 256 bytes for each of the eight blocks The addressing is sequential The first block must be addressed with 0x1010 0000 and the other EEPRO
13. only support one EEPROM b Standard I C can support several EEPROMs extended I2C can only support one EEPROM c Extended I C can support one EEPROM standard 12C can support no more than three EEPROMs Consider this question regarding the extended IC and standard I C Correct Standard I C can support several EEPROMs extended IC can only support one EEPROM Boot Sequencer Generator e Required information for use Register to be programmed ACS data byte enables address data in Big Endian e Format of input file Separated by spaces ACS BYTE_EN 0 3 ADDR 0 17 DATA 0 31 ACS BYTE_EN 0 3 ADDR 0 17 DATA 0 31 ACS BYTE_EN 0 3 ADDR 0 17 DATA 0 31 e Output Raw data file with correct EEPROM format preamble and CRC S record format for customer s convenience The boot sequencer generator tool tries to make it easier to program the EEPROM in the specified format declared in the user manual and in this course If you tell the boot sequencer generator in a simple text file the ACS bit the data byte enables the address of the register you want to program and the data you want to program it with then it can calculate all the rest of the information for you Here you can see the format of a sample input file It contains the four byte enables a space 18 bits of address a space and then 32 bits of data You will proceed to the nex
14. ou can change register information before time zero Power On Sequence Power is applied to meet the voltage specifications HRESET is asserted and TRST is asserted Stable SYSCLK is applied HRESET is negated after required hold time PLLs and DLLs to e500 core and CPM are locked Boot sequencer is initialized if enabled Wait for boot sequencer to complete then simultaneously Enable external PCI accesses Initiate RapidlO training Enable e500 core to begin its boot process Assert Ready Signal NOOR WN gt Here you can see an abridged version of the power on sequence The complete power on sequence can be found in the device specific reference manual which is available on the Web First power is applied then you go through the regular hard reset sequence where you assert HRESET and TRST A stable SYSCLK is applied and then HRESET is negated after the required hold time The next step after that is to allow the phase locked loops PLLs and the delay lock loops DLLs to the core and the CPM to lock At this point the boot sequencer if you enable it will run Note that the boot sequencer runs before you enable external PCI accesses before RapidlO starts training and before the e500 core begins its boot process Boot Sequencer Initialization Mode determined at power up Default gt You need to do some configuration on the chip before you power on This is called pow
15. t line until you have your last register Next you run this text file through the tool and you get two output files The first is a raw data file with the correct EEPROM format preamble and a CRC just as you see it in the data book The boot sequencer generator will tack on the preamble and it will also calculate the CRC The second file will be the same except in S record format in case you want to program the EEPROM with an S record file Burstable Flash Example e Supported on PowerQUICC III as a boot device through boot sequencer e PowerQUICC III talks to flash via UPM e Procedure 1 Use Boot Sequencer to program UPM 2 Configure PowerQUICC III to boot from local bus Burstable flash is not supported on the PowerQUICC III as a boot device except through the boot sequencer We can configure the PowerQUICC III to talk to this burstable flash through the user programmable machine UPM You can t use the general purpose chip select machine GPCM to talk to the burstable flash because it does not support bursting capability Looking at the high level procedure you can see here that the first step is to use the boot sequencer to program the UPM After this point the UPM will know how to talk to the burstable flash Next you configure the PowerQUICC III to boot from the local bus through the LCSO through LCS2 pins These pins allow you to choose from PCI PCI X DDR local bus GPCM 8 bit 16 bit and 32 bit
16. ue which can be calculated using the polynomial found in the device specific reference manual ALTCBAR and CCSRBAR Registers Mouse over the ALTCBAR 12bit BASE ADDR to learn more Alternate Configuration Space ACS If set boot sequencer will access any memory space that is pointed to by the ALTCBAR registers ACS 1 ALTCBAR 12bit BASE_ADDR EEPROM 18bit Address ACS 0 CCSRBAR 12bit BASE _ADDR EEPROM 18bit Address ALTCBAR 0 BASE ADDR BASE_ADDR 12 most significant address bits of an alternate window used for configuration accesses You ll notice that one of the fields in the first byte of the register format is called the ACS bit This bit allows the boot sequencer to access a register that is not in the local memory When enabled it tells the boot sequencer it wants to access this register in an alternate memory space So instead of the normal base address which is set by a register called Configuration Control and Status Base Address Register CCSRBAR it uses the base address set by the Alternate Configuration Base Address Register ALTCBAR Roll your mouse pointer over the ALTCBAR 12bit BASE ADDR to learn more These are the first 12 bits of the base address The next bits are the 18 bit address This is in the EEPROM format ALTCAR Register Click TRGT ID to see a table showing how you
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