V850E/Dx3 - DJ3/DL3 - Renesas Electronics
Contents
1. SLEEP Mode of AFCAN is used and the possibility to wake up AFCAN by CAN Bus events is given see remark 1 below During SLEEP mode of the AFCAN macro a CAN Bus wakeup condition occurs while the AFCAN macro is supplied with clock see remark 2 below and after waking up from SLEEP mode of the AFCAN macro the application software does not wait until the SLEEP mode is released by polling the CnCTRL PSMODE register before continuing operation with the AFCAN macro see remark 3 below and the CPU can reach instructions where AFCAN registers are accessed while the AFCAN macro is still in SLEEP mode due to the missing waiting condition During SLEEP mode of the AFCAN macro a CAN Bus wakeup condition occurs while the AFCAN macro is supplied with clock see remark 2 below and after waking up from SLEEP mode of the AFCAN macro the CAN Bus Transceiver generates a long lasting or permanent dominant level to the CRXD input of the AFCAN macro instead of the propagated CAN Bus level Remarks 1 If the CAN Bus Transceiver does not propagate the CAN Bus signal while the AFCAN macro is in SLEEP mode and also does not forward a wakeup signal to CRXD this Operating Precaution is not applicable The clock supply to the AFCAN macro can be stopped depending on the features of the device and the system design of the application If the clock supply to the AFCAN macro is stopped while a wakeup condition occurs this Operating Precau2. FFFF F30Cy FFFF F32C PDSC8 FFFF F30Ey FFFF F310 FFFF F32E FFFF F330 PDSC9 FFFF F312 FFFF F332 PDSC10 FFFF F314 FFFF F334 Though the PDSCn registers are accessible via both addresses the original address is refer enced as the only address For instance the mirror addresses will not be listed in the devices header files Code Protection and Security Limitation of flash memory extra area and reset vector reprogramming Specification change notice Details The security function which limits reprogramming of the flash memory s extra area and reset vector via an external programmer is not provided with uPD70F3425 DS1 1 Workaround There is no workaround available Customer Notification RO1TU0012ED0400 12 Operating Precautions for V850E Dx3 DJ3 DL3 No 5 External Interrupt Input Filter Timing Port P07 INTP6 Shortened pulse rejection time Details The pulse rejection time for the analogue input filter of the port P07 INTP6 s external inter rupt input filter is shorter than for the other external interrupt input channels The effective pulse rejection time for the port P07 INTP6 is min 25 30 ns and max 163 08 ns Workaround There is no workaround available External Interrupt Input Filter Timing All external interrupt input channels except Port PO7 INTP6 Shortened pulse rejection time Details The pulse rejection time for the analo
3. Customer Notification RO1TU0012ED0400 2 A B C A 1 A 2 A 3 Table of Contents Table of Operating Precautions 5 uPD70F3421 uPD70F3422 UPDZOF3423 sssss s s 5 uPD70F3424 IPD70F3425 occorre eee eee See ale Re te ea 7 uPD70F3426 uPD70F3426A pPD70F3427 sees nnne 9 Description of Operating Precautions 11 No 1 Flash Memory Flash memory block operations Technical Limitation s ssssssssssssessvol 11 No 2 CPU RAM mirror access uPD70F3425 only Specification change notice 11 No 3 Ports PDSCn registers mirrors Specification change notice 12 No 4 Code Protection and Security Limitation of flash memory extra area and reset vector reprogramming Specification change notice _ 12 No 5 External Interrupt Input Filter Timing Port PO7 INTP6 Shortened pulse rejection S T 13 No 6 External Interrupt Input Filter Timing All external interrupt input channels except Port P07 INTP6 Shortened pulse rejection time 13 No 7 AFCAN Sleep Mode Wakeup Specification change notice 14 No 8 On Chip Debug Unit Maximum input clock for the Debug Control Unit DCU is limited 1010 MHZ t Rene ie ai du
4. iRAM operation Flash Memory Flash Access Timing Violation after System Clock Supply Switch CPU HALT instruction 1 uPD70F3426 only Specification change notice CPU HALT instruction 2 Specification change notice Customer Notification RO1TU0012ED0400 7 Operating Precautions for V850E Dx3 DJ3 DL3 _ uPD70F3424 _ uPD70F3425 Linear code execution across address 0x00010000 and 0x00008000 when the boot sectors are swapped Direction of CPU Speed limitation 1 uPD70F3426 only Technical limi tation CPU Speed limitation 2 uPD70F3427 only Technical limi tation LCD I F Reading the LBCTL0 TPF0 status flag may result in wrong information Specification change notice LCD I F Writing to the LBDATAOW LBDATAO LBDATAOL register may lead to a corrupt data transfer Technical limita X Not applicable X Applicable Note The rank is indicated by the letter appearing at the 5th position from the left in the lot number marked on each product Customer Notification RO1TU0012ED0400 8 Operating Precautions for V850E Dx3 DJ3 DL3 A 3 uPD70F3426 uPD70F3426A uPD70F3427 _ UPD70F3426 HPD70F3426A _ HPD70F3427 Flash Memory Flash memory block operations Technical Limitation CPU RAM mirror access uPD70F3425 only Specification change notice Ports PDSCn registers mirrors Specification change notice Code Pro
5. 3 sam o lt lt Q m 3 o lt lt Q m 3 g o TR LCD No 22 transfer Technical limitation uPD70F3427 farrr aror arro golo 8100 8000 arr GLOL arro golo 8100 8000 farrr aror arro golo L ALLL GLOL ALLO aroo o 2 SdSEA SdOS goto o z SdSEA SdOS 8000 0 ZISASIN SADS 8100 8000 golo 8100 8000 o zleasds sdOs o LloSOg1011081 9S2 26L 8ZL W1OOSS 8 9g v SH10dS 96 1199SS SW10dS 9v W109SS SW10dS c 1 1998S SX 19dS 3 ber 91 MIOOSS 8 9 t ZW 1OdS cH ATOSS eW19dS 8 19988 2 eM 19dS t M199SS ox 19dS 91 ZL 8 W199SS 8 9 v LYTOJS 9 W199SS PX T19dS v M1998S 9 MIDJS 2 M199SS PX T19dS 8 9g v W100SS 8 9 v Ow 10dS M199SS OW 1OdS 2 MIOOSS 0W19dS 8 9 v ZI W1OSS WIOSS X10SS W 198A 49019 Wa1SAS Ndd UONEAIN IJUOJ M199SS 01 19dS 49019 sng 491 ato 0 11s49 909d att o L Ha3SsdsS 09S ZHIN 9 ZHN 8b M109SS 33 Customer Notification R01TU0012ED0400 Operating Precautions for V850E Dx3 DJ3 DL3 C Valid Specification Date published February 2004 Document No U14559EJ3V1UM00 Document Title V850E1 32 Bit Microprocessor Core Architec
6. R01TU0012ED0400 Renesas Electronics Corporation Feb 27 2012
7. Switch cont Operating Precautions for V850E Dx3 DJ3 DL3 Workaround For any application requesting a switch of the system clock from Sub Oscillator clock fcpu 32 kHz to any other clock e g Main Oscillator or SSCG or PLL do implement all of the fol lowing measures Do never directly change the system clock from Sub Oscillator clock fcpu 32 kHz to the clock of the Main Oscillator or any clock of the SSCG or PLL by executing the con cerned instructions from the internal flash memory In case the application requests to enter the Sub Watch Mode Do never enter the Sub WATCH mode with the following configuration of the Power save mode register PSM PSM OSCDIS 0 Main Oscillator enabled Do always enter the Sub WATCH mode with the following configuration of the Power save mode register PSM PSM OSCDIS 1 Main Oscillator disabled After the Sub WATCH standby mode has been released by an appropriate wake up event and furthermore the application requires another system clock fcpy than the clock of the Sub Oscillator first do enable the Main Oscillator by clearing the bit OSCDIS of the Power Save Mode register PSM PSM OSCDIS 0 Main Oscillator enabled Do wait until the Main Oscillator has stabilized by verifying the status flag OSCSTAT in the Clock Generator Status register CGSTAT In case any clock of the SSCG or PLL should be used as the system clock fcpy d enable the desired clock sou
8. a clearance of the WAKEUP interrupt flag Doing so the AFCAN macro will start its synchronous operation right after these accesses In the following C code example replace the objects in lt gt brackets by the hardware loca tions within your implementation Use the appropriate access types as described in the User s Manual WAKEUP INTERRUPT VECTOR gt CnCTRL PSMODE 0 Clear SLEEP Mode CnINTS CINTS5 1 Clear INTS5 following other parts of interrupt routine Remark Clearing INTS5 is required to get another WAKEUP interrupt anyway by specifi cation Customer Notification RO1TU0012ED0400 16 Operating Precautions for V850E Dx3 DJ3 DL3 No 7 AFCAN Sleep Mode Wakeup Specification change notice 4 2 Other WAKEUP Handling Hints 4 2 1 Switching off the Clock Supply to AFCAN while in SLEEP Mode If the clock supply to the AFCAN macro is stopped while it is in SLEEP mode the synchroni sation of the WAKEUP works without any restriction To achieve this the documentation of clock controlling unit of the User s Manual must be consulted Usually this is performed by setting the STOP WATCH Sub WATCH mode of the CPU of the target device However the user has to consider that there must not be any WAKEUP condition dominant level on the CAN Bus while the software is executing between setting SLEEP mode and stopping the AFCAN clock 4 2 2 Using a Waiting Loop within the WAKE
9. 2 9 o c g o ES 5 E I 2 2 o lt lt a m 3 sam o lt lt Q m 3 o lt lt Q m 3 g o TR LCD No 22 transfer Technical limitation uPD70F3426 26A farrr aror arro golo 8100 8000 arr GLOL arro golo 8100 8000 farrr aror arro golo aLLL alo arro groo 0 ZISASIN SADS 80L0 o z SdSEA SdOS 8000 0 ZISASIN SADS 8100 8000 golo 8100 8000 o zleasds sdOs 0 Hl0041011981 9S2 26L 8ZL W1OOSS 8 9g v SH10dS 96 1199SS SW10dS 9v W109SS SW10dS c 1 1998S SX 19dS 3 ber 91 MIOOSS 8 9 t ZW 1OdS cH ATOSS eW19dS 8 19988 2 eM 19dS t M199SS ox 19dS 91 ZL 8 W199SS 8 9 v LYTOJS 9 W199SS PX T19dS v M1998S 9 MIDJS 2 M199SS PX T19dS 8 9g v W100SS 8 9 v Ow 10dS M199SS OW 1OdS 2 MIOOSS 0W19dS 8 9 v ZI W1OSS WIOSS X10SS W 198A 49019 Wa1SAS Ndd UONEAIN IJUOJ M199SS 01 19dS 49019 sng 491 ato 0 11s49 909d att o L Ha3SsdsS 09S ZHIN 9 ZHN 8b M109SS 32 Customer Notification R01TU0012ED0400 Operating Precautions for V850E Dx3 DJ3 DL3 g w o a 2 9 o c g o ES 5 E I 2 2 o lt lt a m
10. 2ED0400 Operating Precautions for V850E Dx3 DJ3 DL3 g w o a 2 9 o c g o ES 5 E I 2 2 o lt lt a m 3 sam o lt lt Q m 3 o lt lt Q m 3 g o TR LCD No 22 transfer Technical limitation uPD70F3425 gilli GLOL arro golo 8100 8000 arr GLOL arro golo 8100 8000 farrr aror arro golo ALLL alo arro aroo o z lsdasa sdos 80L0 o z SdSEA SdOS 8000 0 ZISASIN SADS 8100 8000 golo 8100 8000 o zleasds sdOs o LloSOg1011081 9S2 26L 8ZL W1OOSS 8 9g v SH10dS 96 1199SS SW10dS 9v W109SS SW10dS c 1 1998S SX 19dS 3 ber 91 MIOOSS 8 9 t ZW 1OdS cH ATOSS eW19dS 8 19988 2 eM 19dS t M199SS ox 19dS 91 ZL 8 W199SS 8 9 v LYTOJS 9 W199SS PX T19dS v M1998S 9 MIDJS 2 M199SS PX T19dS 8 9g v W100SS 8 9 v Ow 10dS M199SS OW 1OdS 2 MIOOSS 0W19dS 8 9 v ZI W1OSS WIOSS X10SS W 198A 49019 Wa1SAS Ndd UONEAIN IJUOJ M199SS 01 19dS 49019 sng 491 ato 0 11s49 909d att o L Ha3SsdsS 09S ZHIN 9 ZHN 8b M109SS 31 Customer Notification R01TU0012ED0400 Operating Precautions for V850E Dx3 DJ3 DL3 g w o a
11. 3 DJ3 DL3 g w o a 2 9 o c g o ES 5 E I 2 2 o lt lt a m 3 sam o lt lt Q m 3 o lt lt Q m 3 g o TR Q O z No 22 transfer Technical limitation When CPU system clock VBCLK and LCD bus clock are supplied by SSCG pPD70F3421 22 23 24 gilli GLOL arro goto 8L00 8000 ALLL GLOL arro goto 8L00 8000 ALLL GLOL arro goto gilli alo arro groo o 2 SdSEA SdOS goto o 2 SdSEA SdOS 8000 o z lsdasa sdos 8L00 8000 akr aro ALLO goto 8L00 8000 o zledSdS SdOS 0 oog To 11581 9S2 26L 821 WIOOSS 8 9 v SW 10dS 96 1199885 SW10dS 9v W199SS SW10dS c 11928S SWT19dS 3 Vc 91 W1900SS 8 9 r eM 1OdS cL M1ID90SS 11948 8 19988 2 eX 19dS t MIOOSS eX T19dS 91 ZL 8 W109SS 8 9 v LX 10dS 9 W109SS IMI9dAS t M1998S c MIIDJS M199SS MI13JS 8 9 v W10OSS 8 9 v OW 1OdS M1998SS OW 1OdS MIOOSS 2 OW1OdS M199SS ON 19dS 49019 sng q91 8 9 p W1OSS M19SS X10SS W 198A 49019 wuals s NAO uom einBijuoS ato 0 LISMO 00d all o 1 13SdS 20S ZHIN v9 ZH 8v W109SS 30 Customer Notification RO1TU001
12. 434 NE SAS Customer Notification V850E Dx3 DJ3 DL3 32 Bit Single Chip Microcontrollers Operating Precautions uPD70F3421 uPD70F3422 uPD70F3423 uPD70F3424 uPD70F3425 uPD70F3426 uPD70F3426A uPD70F3427 Renesas Electronics RO1TU0012ED0400 Ver 4 00 www renesas com eb 27 2012 10 11 12 Operating Precautions for V850E Dx3 DJ3 DL3 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and othe
13. D I F Reading the LBCTLO TPFO status flag may result in wrong information Specification change notice _ 28 No 22 LCD I F Writing to the LBDATAOW LBDATAO LBDATAOL register may lead to a corrupt data transfer Technical limitation llle 29 Valid Specification scans isis Goede ee 34 Customer Notification RO1TU0012ED0400 3 D Operating Precautions for V850E Dx3 DJ3 DL3 Revision History Customer Notification R01TU0012ED0400 Operating Precautions for V850E Dx3 DJ3 DL3 A Table of Operating Precautions A 1 uPD70F3421 uPD70F3422 uPD70F3423 _ uPD70F3421 uPD70F3422 _ uPD70F3423 o Flash Memory Flash memory block operations Technical Limitation CPU RAM mirror access uPD70F3425 only Specification change notice Ports PDSCn registers mirrors Specification change notice Code Protection and Security Limitation of flash memory extra area and reset vector reprogramming Specification change notice External Interrupt Input Filter Timing Port PO7 INTP6 Shortened pulse rejection time External Interrupt Input Filter Timing All external interrupt input channels except Port PO7 INTP6 Shortened pulse rejection time AFCAN Sleep Mode Wakeup Specification change notice On Chip Debug Unit Maximum input clock for the Debug Control Unit DCU is limited to 10 MHz On Chip Debug Unit Execution of BRO
14. FH respectively 80y to FF Example by using functions of the self programming library SelfLib Erase 0x10 0xff has to be separated into SelfLib Erase 0x10 0x7f and SelfLib Erase 0x80 Oxff No 2 CPU RAM mirror access uPD70F3425 only Specification change notice Details The 32 KB RAM area 3FF 0000 to SFF 7FFFy is mirrored to the 32 KB address range 3FF 8000 to SFF FFFFH Since the upper 4 KB 3FF F000 to 3FF FFFF y overlaps the fixed peripheral I O area the RAM can not be accessed via this address range Following an overview of the RAM areas and it s images RAM RAM image address range accessibility address range accessibility 3FF 0000 SFF 3FFFy 3FF 8000 SFF BFFFy 3FF 40004 3FF 6FFFy 3FF C000 3FF EFFFy SFF 70004 SFF 7FFFy 3FF F000y 3FF FFFFy Workaround Do not access the RAM area 3FF 7000y 3FF 7FFF y via it s mirror area 3FF F000 SFF FFFFH Customer Notification RO1TU0012ED0400 11 Operating Precautions for V850E Dx3 DJ3 DL3 No 3 Ports PDSCn registers mirrors Specification change notice Details The port drive strength control registers PDSCn are mirrored to a second address Following an overview of the PDSCEn register addresses Original address Mirror address Workaround FFFF F300y FFFF F320 FFFF F302 FFFF F322 FFFF F304 FFFF F324 FFFF F306 FFFF F326 FFFF F308 FFFF F328 FFFF F30Ay FFFF F32Ay
15. K1 BRGn Customer Notification RO1TU0012ED0400 19 Operating Precautions for V850E Dx3 DJ3 DL3 No 10 CSIB CSIB may stop operating No 11 cont Master Mode Operation Workaround 2 In order to avoid the CSIBn stuck condition in master mode set bit CBnCTL1 CBnDAP to 1 Pls be aware of the changed CSIB communication type that comes along with this measure By choosing workaround 2 no dedicated clock combination like in workaround 1 must be followed or Master Mode Operation Workaround 3 Detection of CSIBn Stuck Condition In order to avoid a permanent stop of the CSIBn communication that may be caused by the CSIBn stuck limitation the application software must be able to detect the CSIBn stuck con dition by itself in order to restart the interrupted data transfer The stop of the CSIBn communication can be recognized by missing interrupt generation of INTCBnR or INTCBnT before the actual data transfer has finished INTCBnR INTCBnT according to the selected operation mode Continuous Single transfer By choosing this method in order to detect a CSIBn stuck condition no dedicated clock com bination as described in workaround 1 and no dedicated configuration of the bit CBnCTL1 CBnDAP as explained in workaround 2 must be followed Workaround Slave Mode Operation In order to avoid the CSIBn stuck condition in slave mode take the following precautions Transmit mode or transmit receive mode Mak
16. M Startup Code can be unintentionally interrupted at User S W Breakpoint Addresses CSIB CSIB may stop operating On Chip Debug Unit Reconfiguration of N Wire pins during N Wire debug mode uPD70F3427 only Flash Memory Increased Power Consumption when CPU is operating on the Sub Oscillator Clock uPD70F3426 only Flash Memory Increased Power Consumption when CPU is operating on the Sub Oscillator Clock iRAM operation Flash Memory Flash Access Timing Violation after System Clock Supply Switch CPU HALT instruction 1 uPD70F3426 only Specification change notice Customer Notification RO1TU0012ED0400 5 Operating Precautions for V850E Dx3 DJ3 DL3 _ uUPD70F3421 _ uPD70F3422 _ HPD70F3423 CPU HALT instruction 2 Specification change notice DMA MLE Bit Usage Specification change notice Linear code execution across address 0x00010000 and 0x00008000 when the boot sectors are swapped Direction of CPU Speed limitation 1 uPD70F3426 only Technical limi tation CPU Speed limitation 2 uPD70F3427 only Technical limi tation LCD I F Reading the LBCTL0 TPF0 status flag may result in wrong information Specification change notice LCD I F Writing to the LBDATA0W LBDATAO LBDATAOL register may lead to a corrupt data transfer Technical limita X Not applicable X Applicable Note The rank is indicated by the lett
17. PU clock VBCLK of uPD70F3427 must not be set above 48 MHz 5 typical fre quency modulation range of the SSCG dithering function Workaround There is no workaround available Customer Notification RO1TU0012ED0400 27 Operating Precautions for V850E Dx3 DJ3 DL3 LCD I F Reading the LBCTL0 TPF0 status flag may result in wrong information Specification change notice Details The LBCTLO register of the LCD bus interface LCD I F provides the status bit TPF0 that indicates whether 0 The external LCD bus interface is idle or 1 Data is transferred on the external LCD bus interface Reading the TPF0 flag may indicate by accident a wrong status Workaround None Instead of polling the TPF0 flag use an interrupt procedure INTLCD or a DMA transfer Polling of the IF flag of the corresponding interrupt control register is not affected and can be applied as well Customer Notification R01TU0012ED0400 28 No 22 Operating Precautions for V850E Dx3 DJ3 DL3 LCD I F Writing to the LBDATAOW LBDATAO LBDATAOL register may lead to a corrupt data transfer Technical limitation Details When writing to the LBDATAOXx register while a transfer on the LCD data bus is ongoing a corrupt data transfer may be the result The critical situation can occur under certain clock constellations Workaround The application software may choose one of the following workarounds Do not write to the LBDATAOXx register while a
18. UP interrupt routine Within the WAKEUP interrupt routine create a waiting loop which tests the capability of clearing the WAKEUP interrupt flag within AFCAN by checking the actual power save mode In the following C code example replace the objects in lt gt brackets by the hardware loca tions within your implementation Use the appropriate access types as described in the User s Manual do AFCAN_SleepStatus lt CnCTRL_PSMODE gt if AFCAN_SleepStatus 0 macro is still in SLEEP mode waiting for latency time lt CnINTS_CINTS5 gt 1 repeated trying to clear CINTS5 while AFCAN_SleepStatus 0 This improvement hint cannot be applied if a CAN Bus Transceiver is attached to AFCAN which generates a permanent or long lasting dominant level to the FCRXDn receive input pin if a wakeup condition occurs Missing another dominant edge on the bus the synchroni sation will not happen and the loop could run endlessly 4 2 3 Using INIT Mode instead of SLEEP Mode In this case the waking up by CAN bus activity must be performed via another free external interrupt The CAN receive signal must be distributed on the FCRXDn pin and to another external interrupt pin in parallel Using this external interrupt the AFCAN macro can be restored into the previous operation mode This implementation will not use the SLEEP mode of AFCAN at all and use the INIT mode instead Customer Notificatio
19. b m Y e RR 18 No 9 On Chip Debug Unit Execution of BROM Startup Code can be unintentionally interrupted at User S W Breakpoint Addresses 18 No 10 CSIB CSIB may stop operating 19 No 11 On Chip Debug Unit Reconfiguration of N Wire pins during N Wire debug mode UPD70F3427 ONIy s rs 20 No 12 Flash Memory Increased Power Consumption when CPU is operating on the Sub Oscillator Clock UPD70F3426 only 21 No 13 Flash Memory Increased Power Consumption when CPU is operating on the Sub Oscillator Clock iRAM operation 21 No 14 Flash Memory Flash Access Timing Violation after System Clock Supply Switch 22 No 15 CPU HALT instruction 1 uPD70F3426 only Specification change notice _ 24 No 16 CPU HALT instruction 2 Specification change notice 25 No 17 DMA MLE Bit Usage Specification change notice 26 No 18 Linear code execution across address 0x00010000 and 0x00008000 when the boot sectors are swapped Direction of USC 2 rs 27 No 19 CPU Speed limitation 1 uPD70F3426 only Technical limitation RII Ih 27 No 20 CPU Speed limitation 2 uPD70F3427 only Technical limitation llle mh 27 No 24 LC
20. bit the previous interrupt enable state may be restored The workaround should be written in inline assembler to avoid disturbing the register access sequence di Avoid interruption of following sequence Id DCHCn_ADRIr0O ro Four dummy read accesses of DCHCn register ld DCHCn_ADR r0 ro Id DCHCn ADRI rO ro ld DCHCn ADRI rO ro clri 3 DCHCn ADR rO Clear MLEn Bit ei Restore previous interrupt enable state Customer Notification RO1TU0012ED0400 26 Operating Precautions for V850E Dx3 DJ3 DL3 No 18 Linear code execution across address 0x00010000 and 0x00008000 when the boot sectors are swapped Direction of use Details When the boot sectors of the flash memory are swapped make sure that no linear code exe cution across the addresses 0x00010000 or 0x00008000 is done because this can lead to unexpected behaviour Workaround None No 19 CPU Speed limitation 1 uPD70F3426 only Technical limitation Details The CPU clock VBCLK of uPD70F3426 must not be set above 48 MHz 5 typical fre quency modulation range of the SSCG dithering function if a peripheral clock base SPCLKO of 16 MHz must be maintained If necessary the given limit can be extended to 56 MHz 5 typical frequency modulation range of the SSCG dithering function Workaround There is no workaround available No 20 CPU Speed limitation 2 uPD70F3427 only Technical limitation Details The C
21. cleared either by polling the PSMODE flag or by retrying to clear CnINTS 5 this operat ing precaution is not applicable In this case the improvement hint according to 4 2 2 is followed implicitly If during the wakeup dead time the CPU does not perform any access to the AFCAN macro in any case this operating precaution is not applicable 3 3 2 Applications using Bus Transceivers generating long lasting dominant CAN Bus Sig nals If bus transceivers are used in conjunction with AFCAN which generate a permanent or long lasting dominant level when waking up from a power save mode the operating precau tion must be considered in any case In this case the wakeup dead time lasts from the first recessive to dominant edge of the CAN bus signal which generates the wake up until the next recessive to dominant edge of the CAN bus signal depending on the behaviour of the CAN bus transceiver If no further dominant edge on the CAN bus occurs in case of some CAN transceivers which only provide one single edge on waking up the time until SLEEP mode is left may become endless Therefore the waking up procedure of AFCAN regarding software must be adjusted according to 4 1 1 4 Software Improvement Hints 4 1 Recommended WAKEUP Handling by Software 4 1 1 Clearing the SLEEP Mode by Software Within the WAKEUP interrupt routine before accessing any other register or area of AFCAN the SLEEP mode can be canceled by software followed by
22. current consumption in this operating mode Workaround In case the CPU need to start operation using the Sub Oscillator clock as CPU clock supply fcpy 32 kHz and furthermore the CPU does not apply any access to its internal flash memory the flash memory must be accessed at least once by CPU DMAC in order to enable the low current operating mode of the flash memory For the derivative uPD70F3426 both of the device s flash clusters must be accessed at least once by CPU DMAC in order to enable the concerned low current operation mode for both flash clusters Customer Notification RO1TU0012ED0400 21 Operating Precautions for V850E Dx3 DJ3 DL3 No 14 Flash Memory Flash Access Timing Violation after System Clock Supply Switch Details In case the system clock fcpy is changed from the clock of the Sub Oscillator fcpy 32 kHz to the clock of the Main Oscillator or to any clock of SSCG or PLL a CPU access to the internal flash memory may violate the flash timing As a consequence to that the concerned read data respectively the read instruction code may be corrupted This behaviour will appear in case one of the below described sequences is applied from the application Precondition The CPU operates using the sub oscillator as the clock source fcpy 32 KHz As a conse quence of that the flash memory is operating in the low current operating mode In case of HPD70F3426 it s assumed that both flash clusters are operating in t
23. ding to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster syst
24. e sure the external CSIBn clock is not input in parallel when writing to the CBnTXO register after a transmission sequence is finished Receive mode Make sure the external CSIBn clock is not input in parallel when reading from the CBnRXO register after a reception sequence is finished On Chip Debug Unit Reconfiguration of N Wire pins during N Wire debug mode uPD70F3427 only Details During N Wire debug mode the configuration of the N Wire interface pins can be changed by the concerned port mode register PM5 That register contents will not be ignored in case of an active N Wire debug mode OCDMO 1 As a consequence the application software is able to disable the N Wire operation in case the concerned port mode register is enabling output configuration for the concerned N Wire interface pins Workaround The application software must check whether the device is operating in the N wire debug mode or not If it is operating in N wire debug mode any modifications to the related port mode register should be omitted N wire debug mode should be identified by checking whether the OCDM bit of the reset controller is set and PPRO5 is high Customer Notification RO1TU0012ED0400 20 Operating Precautions for V850E Dx3 DJ3 DL3 No 12 Flash Memory Increased Power Consumption when CPU is operating on the Sub Oscillator Clock uPD70F3426 only Details The device uPD70F3426 is equipped with two separate flash clusters Each of th
25. ems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety d
26. er appearing at the 5th position from the left in the lot number marked on each product Customer Notification RO1TU0012ED0400 6 Operating Precautions for V850E Dx3 DJ3 DL3 A 2 uPD70F3424 uPD70F3425 _ HPD70F3424 _ HPD70F3425 Rev RankNote Flash Memory Flash memory block operations Technical Limitation CPU RAM mirror access uPD70F3425 only Specification change notice Ports PDSCn registers mirrors Specification change notice Code Protection and Security Limitation of flash memory extra area and reset vector reprogramming Specification change notice External Interrupt Input Filter Timing Port PO7 INTP6 Shortened pulse rejection time External Interrupt Input Filter Timing All external interrupt input channels except Port PO7 INTP6 Shortened pulse rejection time AFCAN Sleep Mode Wakeup Specification change notice On Chip Debug Unit Maximum input clock for the Debug Control Unit DCU is limited to 10 MHz On Chip Debug Unit Execution of BROM Startup Code can be unintentionally interrupted at User S W Breakpoint Addresses CSIB CSIB may stop operating On Chip Debug Unit Reconfiguration of N Wire pins during N Wire debug mode uPD70F3427 only Flash Memory Increased Power Consumption when CPU is operating on the Sub Oscillator Clock uPD70F3426 only Flash Memory Increased Power Consumption when CPU is operating on the Sub Oscillator Clock
27. er system error mask rom area Workaround Implement all of the following measures when debugging with the On Chip Debug Unit Do not set any kind of breakpoint either S W or H W Breakpoint within any of the address ranges mentioned below 0x0000 OxOOOF Ox06D0 Ox2B23 Special hint Reserve the address range 0x06DO 0x2B23 for constant data placement In case using NEC s directive files which are part of the Device File package this is the default assignment If the program requires less constant data than that address space offers modify the linker directive file in a way that program code does not start before the address Ox2B24 Customer Notification RO1TU0012ED0400 18 Operating Precautions for V850E Dx3 DJ3 DL3 No 10 CSIB CSIB may stop operating Details Master Mode Operation When any channel of CSIB is operated with a peripheral clock source different to the clock source of the CPU the CSIB may stop operating Depending on the CSIB operating configu ration the CSIB behaves as described below Transmit mode or transmit receive mode Any write to the related CBnTXO register will no longer start a transmission sequence Furthermore the related transmission interrupt request will not be generated Receive mode Any read from the related CBnRXO register will no longer start a receive sequence Furthermore the related receive interrupt request will not be generated The described CSIBn st
28. esign for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics
29. gue input filter of the port PO7 INTP6 s external inter rupt input filter is shorter than for the other external interrupt input channels The effective pulse rejection time for the port PO7 INTP6 is min 25 30 ns and max 163 08 ns Workaround There is no workaround available Customer Notification RO1TU0012ED0400 13 Operating Precautions for V850E Dx3 DJ3 DL3 No 7 AFCAN Sleep Mode Wakeup Specification change notice 1 Description When the AFCAN macro is set into SLEEP mode it can be waken up by CAN bus activity This waking up is asynchronous to the operation of the macro and the CPU By configuration setting a WAKEUP interrupt can be generated by the AFCAN macro on the wakeup event While the interrupt is generated asynchronously the AFCAN macro may need another domi nant edge on the CAN bus or software clearing of the SLEEP mode in order to restart its synchronous operation During the time after the interrupt already has been indicated and before the CAN macro has restarted its synchronous operation the registers of the AFCAN macro will not operate because the AFCAN macro still remains in SLEEP mode This time we will refer to as wakeup dead time in the following context To resolve from the wakeup dead time software and or hardware measures are required 2 Exclusions This Operating Precaution is only applicable to applications which are fulfilling at least one of the following three conditions
30. he low current operating The system clock fcpu that is the clock of the Sub Oscillator fcpy 32 kHz is switched to another clock source Main Oscillator or any clock of the SSCG or PLL by immediate configuration of PCC A read fetched data instruction is corrupted due to a timing violation on the flash clus ter The CPU enters the STOP standby mode After the standby mode has been released by an appropriate wake up event the CPU starts operation using the Main Oscillator clock as the system clock fcpy 4 MHz after having passed the oscillator stabilization time This is the default configuration after having been released from the STOP mode A read fetched data instruction is corrupted due to a timing violation on the flash clus ter The CPU enables and enters the Sub WATCH standby mode with the following config uration of the Power save mode register PSM PSM OSCDIS 0 Main Oscillator enabled After the standby mode has been released by an appropriate wake up event the CPU starts operation using the Main Oscillator clock as the system clock fcpy 4 MHz after having passed the oscillator stabilization time This is according to the configura tion of the Power save mode register PSM PSM OSCDIS 0 The read fetched data instruction is corrupted due to a timing violation on the flash cluster Customer Notification RO1TU0012ED0400 22 No 14 Flash Memory Flash Access Timing Violation after System Clock Supply
31. ined data passes through the data latches that are transpar ent and finally will be fetched by the cpu as sequential instruction code Workaround Avoid sequential code execution after HALT instruction This can be achieved by one of the following measures 1 Non sequential code execution due to ISR execution after HALT instruction The HALT mode may be only released with enabled interrupts El by a non masked maskable interrupt request or a non maskable interrupt request NMI In this case the cpu does not execute the instructions located after the HALT instruction but does an initial access to the interrupt handler address Note Take care that no interrupt request is generated that is masked when the corre sponding xxMK bit is set to 1 in the xxIC registers since the cpu would not branch to the interrupt handler address in that case 2 Branch after HALT instruction Place a branch immediately after the HALT instruction that is fetched before the cluster is going to standby and executed when standby is released Example EvenAligned align 8 EvenAligned halt br UserCode nop nop nop align 8 UserCode Note align 8 means placing the code to the even flash memory addresses 0x 0 and Ox 8 Customer Notification RO1TU0012ED0400 25 Operating Precautions for V850E Dx3 DJ3 DL3 No 17 DMA MLE Bit Usage Specification change notice Details Do not modify the setting of the MLEn bit i
32. le interrupts This can be achieved with the following configuration of the processor s Program Status Word PSW PSW ID 0 Enables maskable interrupts PSW NP 0 Enables non maskable interrupts Do jump back to the internal flash memory and continue execution of the application soft ware Workaround In case the application requires that the CPU enters the STOP standby mode do never enter the STOP standby mode in case the clock of the Sub oscillator is used as the system clock fopu 32 kHz No 15 CPU HALT instruction 1 uPD70F3426 only Specification change notice Details Data read from upper 1 MB code flash internal VSB flash memory located from 00100000H to 001FFFFFH becomes invalid when a HALT instruction is executed immediately after wards Workaround To avoid the critical situation both following conditions must be applied The last 4 instructions before the halt execution may not perform a data access to the upper 1 MB code flash internal VSB flash memory located from 00100000H to 001FFFFFH HALT instructions may be only executed from lower 1 MB code flash internal VFB flash memory located from 00000000H to OOOFFFFFH Customer Notification RO1TU0012ED0400 24 Operating Precautions for V850E Dx3 DJ3 DL3 No 16 CPU HALT instruction 2 Specification change notice Details When the cpu executes a HALT instruction the successive output of the flash memory may become undefined The undef
33. n RO1TU0012ED0400 17 Operating Precautions for V850E Dx3 DJ3 DL3 No 8 On Chip Debug Unit Maximum input clock for the Debug Control Unit DCU is limited to 10 MHz Description On chip debugging is not possible in case that the input clock for the Debug Control Unit DCU has been set to 20 MHz Workaround Implement all of the following measures While debugging with any N Wire based emulator do limit the maximum input clock of the DCU to 10 MHz Do consult the latest concerned tool documentation in order to verify that no OCD option is configured in your environment that will configure a higher DCU input clock than 10 MHz Set the following environment variable IE850 JCNDREGINIT 320 Special hint for 850Eserv Above mentioned configuration can be achieved by setting the On Chip Debugger OCD emulator option 2m Do never set the OCD emulator option dck20 since it would configure a DCU input clock of 20 MHz No 9 On Chip Debug Unit Execution of BROM Startup Code can be unintentionally interrupted at User S W Breakpoint Addresses Description If during program execution a Reset occurs either from any internal Reset source or from the external Reset pin the On Chip Debugger may stop on the address of a previously con figured S W or HAW Breakpoint during the execution of the BROM s startup code In this case the following error message may be output Couldn t read flash memory at xxx 0xc25 us
34. n the DCHCn register while the DMA channel n is activated and DMA transfers of channel n are executed in the background Modify the MLEn bit when the corresponding channel n is one of the following periods The operation is not guaranteed if modified at another timing Time from system reset to the generation of the first DMA transfer request of channel n Time from DMA transfer end while MLEn 0 after terminal count to the generation of the next DMA transfer request Time from the forcible termination after the INITn bit has been set to 1 to the generation of the next DMA transfer request The DMA channel transfer may stuck if the MLEn bit is modified It may continue at the next DMA transfer request when dummy read accesses of the DCHCn register are performed to clear the TCn bit In this case DMA transfers may be lost if dummy read accesses are per formed too late Workaround If the application require to clear the MLEn bit while DMA transfers are executed in the back ground following workaround must be applied The workaround is independent of VSWC register setting NPB access retries code location or the use of other DMA channels Four successive dummy read accesses to the DCHCn register should be performed directly before the MLEn bit is cleared This sequence must not be disrupted or interrupted To avoid a possible interrupt the interrupt disable state should be entered by the di instruction After clearing the MLEn
35. ose clusters does contain 1 MB of flash memory One flash cluster is accessible via the VFB V850 Fetch Bus Address range 0000 0000y to 000F FFFFy The other flash cluster is accessible via the VSB Address range 0010 0000y to 001F FFFF The Flash cluster that is not accessed by CPU DMAC when CPU starts operating on the Sub Oscillator clock fcpu 32 kHz will not enter the dedicated low current operating mode that is normally active during that operating mode As a consequence of that the device s current consumption will exceed the specified current consumption for this operating mode Workaround In case the CPU need to operate using the Sub Oscillator clock as CPU clock both of the device s flash clusters must be accessed at least once by CPU DMAC in order to enable the concerned low current operation mode for both flash clusters No 13 Flash Memory Increased Power Consumption when CPU is operating on the Sub Oscillator Clock iRAM operation Details In case the CPU starts operation using the Sub Oscillator clock as CPU clock fcpy 32 kHz and is only executing instructions and reading data that are not located within the inter nal flash memory so the accessed instructions data are located within the internal RAM or external memory in case of uPD70F3427 the internal flash memory will not enter the dedi cated low current operating mode As a consequence of that the device s current consump tion will exceed the specified
36. r related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified accor
37. rce and wait for the specified stabilization time The instructions that will configure the system clock fcpy must be executed from the internal RAM Do not execute any of those configurations by executing the concerned instructions from the internal flash memory As the consequence do jump to the internal RAM memory and execute the con cerned instructions from this memory location Disable the generation of any maskable or non maskable interrupt This is achieved with the following configuration of the processors Program Status Word PSW PSW ID 1 Disables maskable interrupts PSW NP 1 Disables non maskable interrupts Do configure the desired clock source as system clock fcpu by configuring the Processor clock control register PCC PCC CKSO and PCC CKS1 Customer Notification RO1TU0012ED0400 23 Operating Precautions for V850E Dx3 DJ3 DL3 No 14 Flash Memory Flash Access Timing Violation after System Clock Supply Switch cont Do apply a dummy read access to the flash cluster For the derivative HPD70F3426 do apply a dummy read access to each of both flash clusters As a consequence to that the flash cluster is enabling high speed operation mode Do wait for at least 28 5 us before applying any new access to the internal flash memory This wait time can be realized by execution of an appropriate software loop With regards to the application needs do enable the generation of maskable and non maskab
38. s 0x00010000 and 0x00008000 when the boot sectors are swapped Direction of use CPU Speed limitation 1 uPD70F3426 only Technical limi tation CPU Speed limitation 2 uPD70F3427 only Technical limi tation LCD I F Reading the LBCTLO TPFO status flag may result in wrong information Specification change notice LCD I F Writing to the LBDATAOW LBDATAO LBDATAOL register may lead to a corrupt data transfer Technical limita tion X Not applicable X Applicable Note The rank is indicated by the letter appearing at the 5th position from the left in the lot number marked on each product Customer Notification RO1TU0012ED0400 10 Operating Precautions for V850E Dx3 DJ3 DL3 B Description of Operating Precautions No 1 Flash Memory Flash memory block operations Technical Limitation Details When calling flash operations based on blocks e g BlockErase this operation is not exe cuted correctly for certain combinations of start and end blocks This applies only to block combinations where the area between the start block and the end block exceeds the 128 blocks boundary 7Fy For example a block operation with start block 10 and end block FF will fail since the 128 blocks boundary 7F y is exceeded Workaround Flash block operations have to be separated into two steps such that the operations are sep arately executed within a single 128 blocks area 004 to 7
39. s waken up from SLEEP mode this operating precaution is not applicable This means if the user selects a power save mode of the target device which switches off the clock of the AFCAN macro immediately after it had been set into SLEEP mode like the CPU STOP mode the precaution needs not to be considered This is associated with the software improvement hints below Customer Notification RO1TU0012ED0400 15 Operating Precautions for V850E Dx3 DJ3 DL3 No 7 AFCAN Sleep Mode Wakeup Specification change notice 3 3 Affected Applications 3 3 1 Applications not waiting until SLEEP mode is left If bus transceivers are used in conjunction with AFCAN which will propagate the CAN bus signal to AFCAN permanently not switched off or not in power saving modes or if bus transceivers are used in conjunction with AFCAN which will propagate the unmodified CAN Bus signal when waking up from a power save mode the wakeup dead time lasts from the first recessive to dominant edge of the CAN Bus signal which generates the wake up until the next recessive to dominant edge of the CAN Bus signal The worst case maximum length of the wakeup dead time is given by the CAN bus speed and the rule of the CAN bus about the frequency of recessive to dominant edges Given by the stuffing rule at least every 10 bits a recessive to dominant edge must occur If during the wakeup dead time the CPU waits until the SLEEP mode is indicated to be
40. tection and Security Limitation of flash memory extra area and reset vector reprogramming Specification change notice External Interrupt Input Filter Timing Port PO7 INTP6 Shortened pulse rejection time External Interrupt Input Filter Timing All external interrupt input channels except Port PO7 INTP6 Shortened pulse rejection time AFCAN Sleep Mode Wakeup Specification change notice On Chip Debug Unit Maximum input clock for the Debug Control Unit DCU is limited to 10 MHz On Chip Debug Unit Execution of BROM Startup Code can be unintentionally interrupted at User S W Breakpoint Addresses CSIB CSIB may stop operating On Chip Debug Unit Reconfiguration of N Wire pins during N Wire debug mode uPD70F3427 only Flash Memory Increased Power Consumption when CPU is operating on the Sub Oscillator Clock uPD70F3426 only Flash Memory Increased Power Consumption when CPU is operating on the Sub Oscillator Clock iRAM operation Flash Memory Flash Access Timing Violation after System Clock Supply Switch CPU HALT instruction 1 uPD70F3426 only Specification change notice CPU HALT instruction 2 Specification change notice Customer Notification R01TU0012ED0400 9 Operating Precautions for V850E Dx3 DJ3 DL3 Outline _ uPD70F3426 uPD70F3427 DMA MLE Bit Usage Specification change notice Linear code execution across addres
41. tion is not applicable The maximum waiting time for this loop can be up to 10 bits of the CAN Bus Baudrate Waiting while retrying to clear CnINTS Bit 5 can be used alternatively All other applications are not affected by this Operating Precaution Customer Notification RO1TU0012ED0400 14 Operating Precautions for V850E Dx3 DJ3 DL3 No 7 AFCAN Sleep Mode Wakeup Specification change notice 3 Application Dependency 3 1 Overview The following flowchart illustrates how and whether additional measures have to be taken in software to avoid the wakeup dead time Figure Additional Measures in case AFCAN clock is active when waking up AFCAN sleep mode In case AFCAN Clock is disabled In case AFCAN Clock is active Releasing AFCAN sleep mode Releasing AFCAN sleep mode by CAN bus activity by CAN bus activity Releasing AFCAN sleep mode After detected dominant edge by user PSMODEO 0 CINTS5 1 3 2 Not affected Applications 3 2 1 Applications not using SLEEP mode If SLEEP mode is not used this Operating Precaution is not applicable 3 2 2 Applications waking up from SLEEP mode by User Request only If there is no condition when SLEEP mode can be left by CAN Bus activity but only on User Request by clearing the PSMODE flag by software this Operating Precaution is not applicable 3 2 3 Applications using a CPU Power Save Mode If the clock to the AFCAN macro is disabled while it i
42. transfer is ongoing To ensure this oper ate the LBDATAOx register upon the occurrence of the LCD Bus Interface interrupt INTLCD with LBCTLO TCISO set to 1 Use one of the following clock setups in order to avoid the failure mode The following markers are used valid clock combination critical clock combination where the LBDATAOx register may be captured incorrectly combination which is invalid since it injures the specification LCD bus clock must be less or equal 16 MHz is marked by orange filling combination which is invalid only above 48 MHz is marked by yellow filling When CPU system clock VBCLK and LCD bus clock are supplied by PLL uPD70F3421 22 23 24 PLLCLK 32 MHz SCC SPSEL 1 0 01B SPCLKO PLLCLK 2 SPCLK1 PLLCLK A 16 MHz LBCTLO LBCO 1 0 00B 8 MHz LBCTLO LBCO 1 0 01B CPU System Clock VBCLK 32 MHz 16 MHz PCC CKS 1 0 11B PCC CKS 1 0 10B Y x X x pPD70F3425 26 26A PLLCLK 32 MHz SCC SPSEL 1 0 01B SPCLKO PLLCLK 2 SPCLK1 PLLCLK A CPU System Clock VBCLK 32 MHz 16 MHz PCC CKS 1 0 11B PCC CKS 1 0 10B uPD70F3427 PLLCLK 32 MHz SCC SPSEL 1 0 01B SPCLKO PLLCLK 2 SPCLK1 PLLCLK A 16 MHz LBCTLO LBCO 1 0 00B CPU System Clock VBCLK 32 MHz 16 MHz PCC CKS 1 0 11B PCC CKS 1 0 10B 8 MHz LBCTLO LBCO 1 0 01B Customer Notification RO1 X x X x TU0012ED0400 29 Operating Precautions for V850E Dx
43. ture User s Manual Oct 21 2010 Jun 1 2011 R01UH0129ED0601 R01DS0049ED0210 V850E Dx3 DJ3 DL3 Hardware User s Manual V850E Dx3 DJ3 DL3 Data Sheet Customer Notification R01TU0012ED0400 34 Operating Precautions for V850E Dx3 DJ3 DL3 D Revision History Date published October 2006 Document No EASE LL 0003 0 1 Comment First release February 2007 EASE LL 0003 0 2 Operating precautions no 11 to 16 were added May 2007 EASE LL 0003 0 3 Compiler information on operating precautions no 2 and 3 was updated Operating precaution no 17 was added November 2007 U19052EE1V0IF00 Operating precautions no 1 to 3 of former docu ment EASE LL 0003 0 3 were removed since these are already described in the valid specifca tion The remaining operating precautions were renumbered from 1 to 14 Operating precautions no 15 and 16 were added May 2008 U19052EE1V1IF00 Operating precaution no 17 was added December 2008 U19052EE2V0IF00 Operating precaution no 18 was added Jan 19 2011 R01TU0012ED0300 Operating precautions no 19 and 20 were added Feb 27 2012 R01TU0012ED0400 Customer Notification R01TU0012ED0400 Markers of operating precaution no 4 in tables of operating precautions A 1 and A 2 were added only uPD70F3425 DS1 1 was affected Operating precautions no 21 and 22 were added 35 LE NI ESAS
44. uck condition can be escaped by initiating a system reset or by a sequential clear and set of the CBnCTLO CBnPWR bit Details Slave Mode Operation When any channel of CSIB is operated in slave mode and an external clock signal is input via the SCKBn pin while no transmission or reception sequence is in progress the CSIB may stop operating Depending on the CSIB operating configuration the CSIB behaves as described below Transmit mode or transmit receive mode Any further write to the CBnTXO register followed by an external input clock signal input will no longer start a transmission sequence Furthermore the related transmission interrupt request will not be generated Receive mode Any read from the related CBnRXO register followed by an external input clock signal input will no longer start a receive sequence Furthermore the related receive interrupt request will not be generated The described CSIBn stuck condition can be escaped by initiating a system reset or by a sequential clear and set of the CBnCTLO CBnPWR bit Workaround Master Mode Operation 1 In order to to avoid the CSIBn stuck condition in master mode use only the following CPU clock to CSIBn input clock combinations CPU Clock Source SPSELO PERIC SPCLK1 BRGn Source CSIB Clock Input 4 MHz Main Osc 4 MHz Main OSC PCLK6 1 BRGn 4 MHz Main OSC PCLK6 2 BRGn PLL PCLK6 1 PEL PCLK6 2 PLL Divided BRGn PCL
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