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MIPS32® M14K™ Processor Core Software User`s Manual

1. 31 30 29 28 27 26 25 24 23 22 21 20 19 DBD DM NoDCR LSNM Doze Halt CountDM IBusEP MCheckP CacheEP DBusEP IEXI rie 18 17 15 14 10 9 8 7 6 5 4 3 2 1 0 DOBLI Ver DExcCode NoSSt SSt R BEI DINT DIB DDBS DDBL DBp DSS mpr mpr MIPS32 M14K Processor Core Software User s Manual Revision 02 03 133 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core Table 5 31 Debug Register Field Descriptions Fields Name Bit s Description Read Write Reset State DBD 31 Indicates whether the last debug exception or exception R Undefined in debug mode occurred in a branch delay slot Encoding Meaning 0 Not in delay slot 1 In delay slot DM 30 Indicates that the processor is operating in debug mode R 0 Encoding Meaning 0 Processor is operating in non debug mode 1 Processor is operating in debug mode NoDCR 29 Indicates whether the dseg memory segment is present R 0 and the Debug Control Register is accessible Encoding Meaning 0 dseg is present 1 No dseg present LSNM 28 Controls access of load store between dseg and main R W 0 memory Encoding Meaning 0 Load stores in dseg address range goes to dseg 1 Load stores in dseg address range goes to main memory Doze 27 I
2. Instruction Description Function BLTZAL Branch on Less Than Zero And Link GPR 31 PC 8 if Rs 31 PC int offset BLTZALL Branch on Less Than Zero And Link Likely GPR 31 PC 8 if Rs 31 PC int offset else Ignore Next Instruction BLTZL Branch on Less Than Zero Likely if Rs 31 PC int offset else Ignore Next Instruction BNE Branch on Not Equal if Rs Rt PC int offset BNEL Branch on Not Equal Likely if Rs Rt PC int offset else Ignore Next Instruction BREAK Breakpoint Break Exception CACHE Cache Operation See Cache Description CFC2 Move Control Word From Coprocessor 2 Rt CCR 2 n CLO Count Leading Ones Rd NumLeadingOnes Rs CLZ Count Leading Zeroes Rd NumLeadingZeroes Rs COPO Coprocessor 0 Operation See Coprocessor Description COP2 Coprocessor 2 Operation See Coprocessor 2 Description CTC2 Move Control Word To Coprocessor 2 CCR 2 n Rt DERET Return from Debug Exception PC DEPC Exit Debug Mode DI Disable Interrupts Rt Status Statusyp 0 DIV Divide LO int Rs int Rt HI int Rs int Rt DIVU Unsigned Divide LO uns Rs uns Rt HI uns Rs uns Rt EHB Execution Hazard Barrier Stall until execution hazards are cleared EI Enable Interrupts Rt Status Statusyp 1 ERET Return from Exception if SR 2 PC ErrorEPC else PC EPC SR 1 0 SR 2 0 LL 0 244 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010
3. POOL32B AO ASET t 001000 0 bi base 0011 offset 6 2 3 5 4 12 Format ASET bit offset base microMIPS AND MCU ASE Purpose Atomically Set Bit within Byte Description Disable interrupts temp memory GPR base offset temp lt temp or 1 lt lt bit memory GPR base offset lt temp Enable Interrupts The contents of the byte at the memory location specified by the effective address are fetched The specified bit within the byte is set to one The modified byte is stored in memory at the location specified by the effective address The 12 bit signed offset is added to the contents of GPR base to form the effective address The read modify write sequence cannot be interrupted Transactions with locking semantics occur in some memory interconnects busses It is implementation specific whether this instruction uses such locking transactions Restrictions The operation of the processor is UNDEFINED if an ASET instruction is executed in the delay slot of a branch or jump instruction Operation vAddr lt sign extend offset GPR base pAddr CCA lt AddressTranslation vAddr DATA STORE pAddr pAddrpgrzn 1 2 pAddr 9 xor ReverseEndian TempIE Statusrp Status p amp 0 memword lt LoadMemory CCA BYTE pAddr vAddr DATA byte vAddr 9 xor BigEndianC PU temp amp memword7 8 byte 8tbyte temp temp or 1 obit dataword temp o 5vte StoreMem
4. 202 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 5 EJTAG TAP Registers Table 8 31 EJTAG Control Register Descriptions Continued Fields Read Name Bit s Description Write Reset State PrAcc 18 Processor Access PA R WO 0 Read value of this bit indicates if a Processor Access PA to the EJTAG memory is pending Encoding Meaning 0 No pending processor access 1 Pending processor access The probe s software must clear this bit to 0 to indicate the end of the PA Write of 1 is ignored A pending Processor Access is cleared when Rocc is set but another PA may occur just after the reset if a debug exception occurs Finishing a Processor Access is not accepted while the Rocc bit is set This is to avoid that a Processor Access occurring after the reset is finished due to indication of a Processor Access that occurred before the reset The FASTDATA access can clear this bit Res 17 reserved R 0 PrRst 16 Processor Reset Implementation dependent behavior R W 0 When the bit is set to 1 then it is only guaranteed that this setting has taken effect in the system when the read value of this bit is also 1 This is to ensure that the setting from the TCK clock domain gets effect in the CPU clock domain and in peripherals When the bit is written to 0 then the bit must also b
5. Table 8 24 Priming Conditions and Register Values for 81 4D Configuration Break Condo Cond1 Cond2 Cond3 PrCndA Value dide InstO Bypass Data0 Insti Ox1211 2000 0x8300 Inst1 Bypass Data InstO 0x1210 2000 0x8320 Inst2 Bypass Datal Inst3 0x1413 2100 0x8340 Inst3 Bypass Datal Inst2 0x1412 2100 0x8360 Inst4 Bypass Data2 Inst5 Inst6 0x1615_2200 0x8380 184 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints Break Condo Cond1 Cond2 Cond3 PrCndA Value ee Inst5 Bypass Data2 Inst4 0x83a0 Inst6 Bypass Data3 Inst7 0x1017_2300 0x83c0 Inst7 Bypass Data3 Inst6 0x1016_2300 0x83e0 Data0 Bypass InstO Insti 0x2111 1000 0x84e0 Datal Bypass Inst2 Inst3 0x2213 1200 0x8500 Data2 Bypass Inst4 Inst5 0x2315 1400 0x8520 Data3 Bypass Inst6 Inst7 0x2017_1600 0x8540 8 2 8 3 Stopwatch Timer Control STCil Register 0x8900 Compliance Level Implemented if stopwatch timer is implemented The Stopwatch Timer Control STCtI register gives configuration information about how the stopwatch timer register is controlled On an M14K core the break channels that control the stopwatch timer are fixed and this register is read only Figure 8 20 STCtl Register Format 31 18 17 14 13 10 9 8 5 4 1 0 Res StopChanl StartChanl En1 StopChanO StartChanO Eno
6. a Based on actual hardware implemented b In case of fewer than 8 Instruction breakpoints the upper bits become reserved 8 2 6 2 Instruction Breakpoint Address n IBAn Register 0x1100 n 0x100 Compliance Level Implemented only for implemented instruction breakpoints The nstruction Breakpoint Address n IBAn register has the address used in the condition for instruction breakpoint n Figure 8 3 IBAn Register Format 31 0 IBA Table 8 4 IBAn Register Field Descriptions Fields Read W Name Bit s Description rite Reset State IBA Instruction breakpoint address for condition R W Undefined 8 2 6 3 Instruction Breakpoint Address Mask n IBMn Register 0x1108 n 0x100 Compliance Level Implemented only for implemented instruction breakpoints The Instruction Breakpoint Address Mask n IBMn register has the mask for the address compare used in the condi tion for instruction breakpoint n A 1 indicates that the corresponding address bit will not be considered in the match A mask value of all 0 s would require an exact address match while a mask value of all 1 s would match on any address Figure 8 4 IBMn Register Format 81 0 IBM MIPS32 M14K Processor Core Software User s Manual Revision 02 03 171 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Table 8 5 IBMn Register Field Descriptions
7. Table 8 25 STCtl Register Field Descriptions Fields Read Wr Name Bit s Description ite Reset State Res 31 18 Must be written as zero returns zero on read R 0 StopChan1 17 14 Indicates the instruction breakpoint channel that will R 0 stop the counter if the timer is under pairl breakpoint control StartChan1 13 10 Indicates the instruction breakpoint channel that will R 0 start the counter if the timer is under pair breakpoint control Enl 9 Enables the second pair pair1 of breakpoint registers to R 0 control the timer when under breakpoint control If the stopwatch timer is configured to be under breakpoint control by setting CBTControlSTM yand this bit is set the breakpoints indicated in the StartChanl and StopChanl fields will control the timer The M14K core only supports 1 pair of stopwatch con trol breakpoints so this field is not writable and will read as 0 StopChan0 8 5 Indicates the instruction breakpoint channel that will R Ox4 stop the counter if the timer is under pairO breakpoint control MIPS32 M14K Processor Core Software User s Manual Revision 02 03 185 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Table 8 25 STCtl Register Field Descriptions Fields Read Wr Name Bit s Description ite Reset State StartChanO 4 1 Indicates the instruction breakpoint channel that will R 0x1 s
8. sss 196 Figure 8 24 TDI to TDO Path When in Shift DR State and FASTDATA Instruction is Selected 197 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 9 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Figure 8 25 Figure 8 26 Figure 8 27 Figure 8 28 Figure 8 29 Figure 8 30 Figure 8 31 Figure 8 32 Figure 8 33 Figure 8 34 Figure 8 35 Figure 8 36 Figure 8 37 Figure 8 38 Figure 8 39 Figure 8 40 Figure 8 41 Figure 8 42 Figure 8 43 Figure 9 1 Instruction Formats Figure 11 1 Figure 11 2 Figure 11 3 Device Identification Register FOrMal cccciissseccessssececedisansccecesasedccctsapsececedivueiduecisisscecedauacccenaenccctagys 198 Implementation Register FOrmMat ccsn sisccsvsslasessancidasesun ddscadecaricdaagthas uet tn dtes trettnanGruaidatauncledeuenes 199 EJI AG Gontrol Register EOIImal 25 2 2 et petet uiribus asit E sgeant Su eet Me cascade R 200 EndianiFormats torthe PAD Register 3 5 Dedi eet up etta en boue du Set RARE ede En AN 207 Pasidata Register meli 207 RACES koogi ar Rm 216 Gohtrol Status RBgISIOE s toes e dates E E e usse qui Poste ES 218 li TG BTW Register FOITgalss a cae toco idento N s Eu nite Seti px Sue oaE M Desc SReRdS 220 lTOBRDPiIBSSISIGE FORTIQE s cde bet ttu urn EEp eid eta Sas feste ve ede te shah tacts a TOEREN 221 II CBWRF Register EO tIdls spero beide a tr a deu dee dd
9. eesesssisesesesessessee ennt ntn nnne 124 5 2 21 Configi Register CPO Register 16 Select 1 126 5 2 22 Gonfig2 Register CPO Register 16 Select 2 2 2 etae rd genie et E ette eode tese e e Suet EE 127 5 2 23 Config3 Register CPO Register 16 Select 3 sss nnns 128 5 2 24 Configuration Register 4 CPO Register 16 Select 4 131 5 2 25 Config5 Register CPO Register 16 Select 5 nennen 132 5 2 26 Contig Register CPO Register 16 Select 7 ure erdt aiaa 132 5 2 27 Debug Register CPO Register 23 Select 0 sirrinin a an aaa 133 5 2 28 Trace Control Register CPO Register 23 Select 1 esssssssseenenene 137 5 2 29 Trace Control2 Register CPO Register 23 Select 2 sess 139 5 2 30 User Trace Data1 Register CPO Register 23 Select 3 User Trace Data2 Register CPO Register 24 Selec3 enisi A XR a RUER Dice e sa D iesu dt E Dessus M exea RA Re bdse uM LaseA ER hs 141 5 2 31 TraceBPC Register CPO Register 23 Select 4 sse 142 5 2 32 Debug2 Register CPO Register 23 Select 6 eesssssssssssssesesenee enne 143 5 2 33 Debug Exception Program Counter Register CPO Register 24 Select 0 sssss 144 5 2 34 Performance Counter Register CPO Register 25 select 0 3 ssssssssssssss 145 5 2 35 ErrCt Register GPO Register 26 Select 0 rtp ent bii petenti praec eti une epe kun 1
10. Fields Read W Name Bit s Description rite Reset State IBM 31 0 Instruction breakpoint address mask for condition Undefined Encoding Meaning 0 Corresponding address bit not masked 1 Corresponding address bit masked 8 2 6 4 Instruction Breakpoint ASID n IBASIDn Register 0x1110 n 0x100 Compliance Level Implemented only for implemented instruction breakpoints For processors with a TLB based MMU this register is used to define an ASID value to be used in the match expres sion On the M14K processor this register is reserved and reads as 0 Figure 8 5 IBASIDn Register Format 31 8 7 0 Res ASID Table 8 6 IBASIDn Register Field Descriptions Fields Read Wr Name Bit s Description ite Reset State ASID 7 0 Instruction breakpoint ASID value for a compare R 0 8 2 6 5 Instruction Breakpoint Control n IBCn Register 0x1118 n 0x100 Compliance Level Implemented only for implemented instruction breakpoints The nstruction Breakpoint Control n IBCn register controls the setup of instruction breakpoint n Figure 8 6 IBCn Register Format 81 24 23 22 7 6 5 4 3 2 1 0 Res ASIDuse Res hwarts excl hwart Res TE Res BE Table 8 7 IBCn Register Field Descriptions Fields Name Bits Description Read Write Reset State 31 24 Must be written as zero returns zero on read R 009
11. MIPS32 M14K Processor Core Software User s Manual Revision 02 03 65 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M14KT Core Table 4 2 shows the current interrupt mode of the processor as a function of the Coprocessor 0 register fields that can affect the mode Table 4 2 Interrupt Modes 4 3 1 1 Interrupt Compatibility Mode gt Sig 4 oa Bale pb o o r eo eo l5 0 2 SISE IE o o 616 Interrupt Mode 1 x x x x Compatibly x JO x x x Compatibility x x 0 x x Compatibility 0 1 0 1 O Vectored Interrupt O 1 0 x 1 External Interrupt Controller 0 1 0 O O Can t happen IntCtlys can not be non zero if neither Vectored Interrupt nor External Interrupt Controller mode is implemented x denotes don t care This is the default interrupt mode for the processor and is entered when a Reset exception occurs In this mode inter rupts are non vectored and dispatched though exception vector offset 1631180 if Causey 0 or vector offset 16 200 if Causey 1 This mode is in effect if any of the following conditions are true e Causey 0 e Slatusggy 1 e niCtlys 0 which would be the case if vectored interrupts are not implemented or have been disabled Here is a typical software handler for interrupt compatibility mode the interrupt exception would have to be isolated from the g
12. 18 17 Enables Data Address Sampling Data address sampling is not supported so this bit will read as 0 Encoding Meaning 0 Data Address sampling disabled 1 Data Address sampling enabled Indicates if the Data Address Sampling feature is imple mented Data address sampling is not supported so this bit will read as 0 Encoding Meaning 0 No DA Sampling implemented 1 DA Sampling implemented LT ndicates if the fast debug channel is implemented Encoding Meaning 0 No fast debug channel implemented 1 Fast debug channel implemented Indicates if data hardware breakpoint is implemented Encoding Meaning 0 No data hardware breakpoint imple mented 1 Data hardware breakpoint imple mented u R Preset InstBrk 16 Indicates if instruction hardware breakpoint is imple mented Encoding Meaning 0 No instruction hardware breakpoint implemented 1 Instruction hardware breakpoint implemented R Preset MIPS32 M14K Processor Core Software User s Manual Revision 02 03 161 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Table 8 1 DCR Register Field Descriptions Continued Fields Read Reset Name Bits Description Write State IVM 15 Indicates if inverted data value match on data hardware R Preset b
13. 2009 2010 MIPS Technologies Inc All rights reserved 8 3 Complex Breakpoint Usage 2 Read the DebugNoDCR bit to check for the presence of the Debug Control Register DCR The DCR will always be implemented on an M14K core 3 Read the DCRCBT bit to check for the presence of any complex break and trigger features 4 Read the CBTControl register to check for the presence of each individual feature If an M14K core implements any complex break and trigger features it will implement all of them 5 If Pass Counters are implemented they may not be implemented for all break channels and may have different counter sizes To determine the size and presence of each pass counter software can write 1 to each of the IBPCn and DBPCn registers and read it back If an M14K core implements pass counters it will implement an 8b counter for each instruction breakpoint and a 16b counter for each data breakpoint 6 Iftuples are implemented they may only be supported on a subset of the data breakpoint channels This can be checked by seeing if the DBBCnTUP bit can be set to 1 Additionally some cores may support dynamically changing which instruction breakpoint is associated with a given data breakpoint This can be checked by attempting to write the DBCCnTIBrkNum field If an M14K core implements tuple support it will support it for all data breakpoint channels and the instruction breakpoint association will be fixed 7 If Priming Conditions are supp
14. 2009 2010 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M14KT Core 72 The external interrupt controller prioritizes its interrupt requests and produces the priority level and the vector num ber of the highest priority interrupt to be serviced The priority level called the Requested Interrupt Priority Level RIPL is an 8 bit encoded value in the range 0 255 inclusive A value of 0 indicates that no interrupt requests are pending The values 1 255 represent the lowest 1 to highest 255 RIPL for the interrupt to be serviced The inter rupt controller passes this value on the 8 hardware interrupt lines which are treated as an encoded value in EIC inter rupt mode There are two implementation options available for the vector offset 1 The first option is to send a separate vector number along with the RIPL to the processor 2 Asecond option is to send an entire vector offset along with the RIPL to the processor This option is enabled through the core s configuration GUI and it is not affected by software The M14K core does not support the option to treat the RIPL value as the vector number for the processor Statusjp which overlays Statuslyo qw is interpreted as the Interrupt Priority Level IPL at which the processor is currently operating with a value of zero indicating that no interrupt is currently being serviced When the interrupt controller requests service for an interrupt the proc
15. MIPS32 M14K Processor Core Software User s Manual Revision 02 03 151 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core Figure 5 39 ErrorEPC Register Format 31 0 ErrorEPC Table 5 44 ErrorEPC Register Field Description Fields Bit s Description Read Write Reset State 31 0 Error Exception Program Counter Undefined ErrorEPC 5 2 38 DeSave Register CPO Register 31 Select 0 The Debug Exception Save DeSave register is a read write register that functions as a simple memory location This register is used by the debug exception handler to save one of the GPRs that is then used to save the rest of the context to a pre determined memory area such as in the EJTAG Probe This register allows the safe debugging of exception handlers and other types of code in which the existence of a valid stack for context saving cannot be assumed Figure 5 40 DeSave Register Format 31 0 DESAVE Table 5 45 DeSave Register Field Description Fields Name Bit s Description Read Write Reset State DESAVE 31 0 Debug exception save contents R W Undefined 152 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 6 Hardware and Software Initialization of the M14K Core An M14K processor core contains only a min
16. Preset Compliance Level Required if any optional feature described by this register is implemented Release 2 of the Architecture Optional otherwise The Config4 register encodes additional capabilities Figure 5 25 shows the format of the Config4 register Table 5 28 describes the Config4 register fields Figure 5 25 Config4 Register Format 31 30 0 M 000 000 Table 5 28 Config4 Register Field Descriptions Fields Read Reset Name Bits Description Write State Compliance M 31 This bit is reserved to indicate that a Config5 register is R 1 Required present 0 30 0 Must be written as zeros returns zeros on read 0 0 Reserved MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 131 CPO Registers of the M14K Core 5 2 25 Config5 Register CPO Register 16 Select 5 Compliance Level Required if any optional feature described by this register is implemented Release 2 of the Architecture Optional otherwise The Config5 register encodes additional capabilities Figure 5 26 shows the format of the Config5 register Table 5 29 describes the Conf g5 register fields Figure 5 26 Config5 Register Format 31 30 WM M 000 000 NF Table 5 29 Config5 Register Field Descriptions Fields Name Description i Compliance This bit is reserved to indicate th
17. Refer to the EJTAG Specification 11 for the general details on FDC The remainder of this section describes imple mentation specific behavior and register values The FDC memory mapped registers are located in the common device memory map CDMM region FDC has a device ID of OxFD MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 10 Fast Debug Channel 8 10 1 Common Device Memory Map Software on the M14K accesses FDC through memory mapped registers located within the Common Device Mem ory Map CDMM The CDMM is a region of physical address space that is reserved for mapping IO device configu ration registers within a MIPS processor The base address and enabling of this region is controlled by the CDMMBase CPO register as described in5 2 19 CDMMBase Register CPO Register 15 Select 2 on page 123 Refer to Volume III of the MIPS Architecture Reference Manuals 11 for full details on the CDMM 8 10 2 Fast Debug Channel Interrupt The FDC block can generate an interrupt to inform software of incoming data being available or space being avail able in the outgoing FIFO This interrupt is handled similarly to the timer or performance counter interrupts The CauseFDCI bit indicates that the interrupt is pending The interrupt is also sent to the core output S FDCI where it is combined with one of the S Int pins For non EIC mode the S PFDC
18. 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Figure 8 15 DBCCn Register Format 31 20 8 5 43 210 19 16 15 14 13 10 9 E msan roe fre mew oor psano ol ve Table 8 17 DBCCn Register Field Descriptions Fields Name Bits Description Read Write Reset State Res Must be written as zero returns zero on read R 0 TIBrkNum Tuple Instruction Break Number Indicates which R 6I 2D Complex Breakpoint instruction breakpoint will be paired with this data break Configuration point to form a tuple breakpoint DBCCO 0 DBCCI 3 SI AD Complex Breakpoint Configuration DBCCO 0 DBCCI 2 DBCC2 4 DBCC3 6 TUP Tuple Enable Qualify this data breakpoint with a match R W 0 on the TIBrkNum instruction breakpoint on the same instruction PrCnd Upper bits of priming condition for D breakpoint n R 0 MIAK only supports 4 priming conditions so the upper 2 bits are read only as 0 PrCnd Priming condition for D Breakpoint n R W 0 00 Bypass no priming needed Other vary depending on the break number refer to Table 8 20 for mapping CBE 9 Complex Break Enable enables this breakpoint for use R W 0 as a priming or qualifying condition for another break point DQBrkNum 8 5 Indicates which data breakpoint channel is used to qualify R 0 this data breakpoint Data qualification of data breakpoints is not supported on an M14K core and this field will read as 0 and cann
19. Byte access ignore controls ignore of access to a specific R W Undefined byte BAI 0 ignores access to byte at bits 7 0 of the data bus BAI 1 ignores access to byte at bits 15 8 etc Encoding Meaning 0 Condition depends on access to corre sponding byte 1 Access for corresponding byte is ignored 13 Controls if condition for data breakpoint is not fulfilled R W Undefined on a store transaction Encoding Meaning 0 Condition may be fulfilled on store transaction 1 Condition is never fulfilled on store transaction NoLB Res BLM 178 12 Controls if condition for data breakpoint is not fulfilled R W Undefined on a load transaction Encoding Meaning 0 Condition may be fulfilled on load transaction 1 Condition is never fulfilled on load transaction 11 8 Must be written as zero returns zero on reads R 0 7 4 Byte lane mask for value compare on data breakpoint R W Undefined BLM O masks byte at bits 7 0 of the data bus BLM 1 masks byte at bits 15 8 etc Encoding Meaning 0 Compare corresponding byte lane 1 Mask corresponding byte lane MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints Table 8 15 DBCn Register Field Descriptions Continued Fields Name Bits Descriptio
20. Figure 1 3 Figure 1 4 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Address Translation During a SRAM ACCESS 2 aoreet oett hee eter tere edet tuiutiobetblu epe tani Qu Det E EP beSE 23 Reference Design Block Diaa uuu tot oret ent rene tete NENN inperediasinonevesanewedeasiaveceessieed 25 FDC OV CIIGW rounen n E O E a a a 27 COTAGUSUDDORL 25 0 rr iaa EE E E cr eet tierce erst reer rere rer terre eee 28 M14K Core Pipeline Stages with high performance MDU ssseme n 32 M14K Core Pipeline Stages with area efficient MDU sssseeseseeeeeeenen nnns 32 MDU Pipeline Behavior During Multiply Operations ssseeeeenennnn 36 MDU Pipeline Flow During a 32x16 Multiply Operation essssseeeseseeneenenn nnns 37 Figure 2 5 MDU Pipeline Flow During a 32x32 Multiply Operation sssseeeeeeeennes 38 Figure 2 6 High Performance MDU Pipeline Flow During a 8 bit Divide DIV Operation sss 38 Figure 2 7 High Performance MDU Pipeline Flow During a 16 bit Divide DIV Operation 38 Figure 2 8 High Performance MDU Pipeline Flow During a 24 bit Divide DIV Operation 39 Figure 2 9 High Performance MDU Pipeline Flow During a 32 bit Divide DIV Operation 39 Figure 2 10 M14K Area Efficient MDU Pipeline Flow During a Multiply O
21. MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints The instruction causing the debug data break exception does not update any registers due to the instruction and the following applies to the load or store transaction causing the debug exception e A store transaction is not allowed to complete the store to the memory system e A load transaction with no data value compare i e where the DB no value compare is true for the match is not allowed to complete the load e A load transaction for a breakpoint with data value compare must occur from the memory system since the value is required in order to evaluate the breakpoint The result of this is that the load or store instruction causing the debug data break exception appears as not executed with the exception that a load from the memory system does occur for a breakpoint with data value compare but the register file is not updated by the load If both data breakpoints without and with data value compare would match the same transaction and generate a debug exception then the following rules apply with respect to updating the BS n bits e On both a load and store the BS n bits are required to be set for all matching breakpoints without a data value compare e Onastore the BS n bits are allowed but not required to be set for all matching breakpoints with a data value
22. MMU Type 3 Fixed Mapping 0 2 4 7 Reserved Must be written as zeros returns zeros on reads Kseg0 coherency algorithm Refer to Table 5 24 for the field encoding K23 KU 0 UDI SB MDU 0 DS AT AR MT 0 KO MIPS32 M14K Processor Core Software User s Manual Revision 02 03 125 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core 126 Table 5 24 Cache Coherency Attributes C 2 0 Value Cache Coherency Attribute Uncached Cached Core treats as uncached but passes attribute to the system for use with any exter nal caching mechanisms 5 2 21 Config Register CPO Register 16 Select 1 The Config register is an adjunct to the Config register and encodes additional information about capabilities present on the core All fields in the Config1 register are read only Figure 5 22 Config1 Register Format Select 1 31 30 25 24 22 21 19 18 16 15 13 12 10 9 7 6 5 4 3 2 1 0 M MMU Size IS IL IA DS DL DA C2 MD PC WR CA EP FP Table 5 25 Config1 Register Field Descriptions Select 1 Description Read Write Reset State M This bit is hardwired to 1 to indicate the presence of the R 1 Config2 register MMU Size This field contains the number of entries in the TLB minus R 0 one This field contains the number of instruction cache sets per R 0 way Because the M14K core does not include caches this field is always
23. SWR Store Word Right See SWR instruction description SYNC Synchronize See SYNC instruction below SYNCI Synchronize Caches to Make Instruction Writes Nop Effective SYSCALL System Call SystemCallException TEQ Trap if Equal if Rs Rt TrapException TEQI Trap if Equal Immediate if Rs int Immed TrapException TGE Trap if Greater Than or Equal if int Rs gt int Rt TrapException TGEI Trap if Greater Than or Equal Immediate if int Rs gt int Immed TrapException TGEIU Trap if Greater Than or Equal Immediate if uns Rs gt uns Immed Unsigned TrapException TGEU Trap if Greater Than or Equal Unsigned if uns Rs gt uns Rt TrapException TLT Trap if Less Than if int Rs lt int Rt TrapException TLTI Trap if Less Than Immediate if int Rs lt int Immed TrapException TLTIU Trap if Less Than Immediate Unsigned if uns Rs lt uns Immed TrapException TLTU Trap if Less Than Unsigned if uns Rs lt uns Rt TrapException TNE Trap if Not Equal if Rs Rt TrapException Copyright 2009 2010 MIPS Technologies Inc All rights reserved 247 M14K Processor Core Instructions Table 10 10 Instruction Set Continued Instruction Description Function TNEI Trap if Not Equal Immediate if Rs Gnt Immed TrapException WAIT Wait for Interrupts Stall until interrupt occurs WRPGPR Write to GPR in Previous Shadow Set SGPR SRSCtlpss Rd Rt WSBH Word Swap Bytes within Halfwords RdzSwapBytesWithinHalfs Rt
24. This begins a RMW sequence on the current processor There can be only one active RMW sequence per processor When an LL is executed it starts an active RMW sequence replacing any other sequence that was active The RMW sequence is completed by a subsequent SC instruction that either completes the RMW sequence atomically and suc ceeds or does not and fails Executing LL on one processor does not cause an action that by itself causes an SC for the same block to fail on another processor An execution of LL does not have to be followed by execution of SC a program is free to abandon the RMW sequence without attempting a write Restrictions The addressed location must be synchronizable by all processors and I O devices sharing the location if it is not the result in UNPREDICTABLE Which storage is synchronizable is a function of both CPU and system implementa tions See the documentation of the SC instruction for the formal definition The addressed location may be uncached for the M14K core The effective address must be naturally aligned If either of the 2 least significant bits of the effective address is non zero an Address Error exception occurs Operation vAddr lt sign extend offset GPR base if vAddr 0 then SignalException AddressError endif pAddr CCA AddressTranslation vAddr DATA LOAD memword lt LoadMemory CCA WORD pAddr vAddr DATA GPR rt lt memword LLbit 1 Exceptions TLB R
25. User mode load reference to kernel address Store address alignment error User mode store to kernel address 64 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 3 Interrupts Table 4 1 Priority of Exceptions Continued Exception Description DSRAM Parity Error Parity error on D SRAM access DBE Load or store bus error DDBL EJTAG data hardware breakpoint matched in load data compare CBrk EJTAG complex breakpoint 4 3 Interrupts In the MIPS32 Release 1 architecture support for exceptions included two software interrupts six hardware inter rupts and a special purpose timer interrupt The timer interrupt was provided external to the CoreType lc and was typically combined with hardware interrupt 5 in a system dependent manner Interrupts were handled either through the general exception vector offset 0x180 or the special interrupt vector 0x200 based on the value of CauselV Software was required to prioritize interrupts as a function of the Cause bits in the interrupt handler prologue Release 2 of the Architecture implemented by the M14K core adds a number of upward compatible extensions to the Release 1 interrupt architecture including support for vectored interrupts and the implementation of a new inter rupt mode that permits the use of an external interrupt controller The M14K core also includes th
26. XOR Exclusive OR RdzRs Rt XORI Exclusive OR Immediate Rt Rs uns Immed 248 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 31 26 25 21 20 16 15 14 12 11 4 3 0 REGIMM ATOMIC A 000001 base 00111 0 Bit offset 6 5 5 3 12 Format ACLR bit offset base MIPS32 and MCU ASE Purpose Atomically Clear Bit within Byte Description Disable interrupts temp memory GPR base offset temp lt temp and 1 lt lt bit memory GPR base offset lt temp Enable Interrupts The contents of the 8 bit byte at the memory location specified by the effective address are fetched The specified bit within the byte is cleared to zero The modified byte is stored in memory at the location specified by the effective address The 12 bit signed offset is added to the contents of GPR base to form the effective address The read modify write sequence cannot be interrupted Transactions with locking semantics occur in some memory interconnects busses It is implementation specific whether this instruction uses such locking transactions Restrictions The operation of the processor is UNDEFINED if an ACLR instruction is executed in the delay slot of a branch or jump instruction Operation vAddr lt sign extend offset GPR base pAddr CCA lt AddressTranslation vAddr DATA STORE pAddr pAddrpgrzn 1 2 pAddr
27. sssssssssssssssseeeeee entente etnies 56 Figute 3 5 Debug Mode Virtual Address Space i 2 irte tr secte reset EN er AR ER E ENE 58 Figure 3 6 FM Memory Map ERL 0 in the M14K Processor Core sssssseeenemennns 60 Figure 3 7 FM Memory Map ERL 1 in the M14K Processor Core sssssseeeeeemeeennnens 61 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Interrupt Generation for Vectored Interrupt Mode sssssesssssseseseeeenne entente nenas 70 Interrupt Generation for External Interrupt Controller Interrupt Mode eese 73 General Exception Handler EV uico siipecc ii terio ders tcs Eesn oou irtua su Reha e Feed xpe std Sa ERR DE DNE eae 92 General Exception Servicing Guidelines SW sssssssssssssseeeeeeeennee entente 93 Reset Soft Reset and NMI Exception Handling and Servicing Guidelines sssss 94 UserLocal Register Format 2 2i irre tereti Er oecen et Ee rea Vb bon EE ERE RR REESE REM bas 97 HWhEna Register FOTmal ssiei dete top esto O Urtri desse tetbrsda Pica dep utem eesE Hu entes Eu Doe 98 BadVAddr Register B gro do e 99 Cotnt Register FOITflgl aco acoitiixt oett ides altis asc uu ER Rcx al iten usu E 99 compare Hegister ONial 5 22 2 ecu eher aae tiende ton E E cee NA PL enu Tm tcc re
28. 17 SW16 4 rb 2 7 16 17 rs1 0 2 7 17 0 15 2 SWSP 5bit 1 5 rs1 5 bit field 0 31 2 SWM16 2 bit list 1 4 0 15 lt lt 2 XORI6 0 rs1 2 7 16 17 rd 2 7 16 17 11 3 2 16 bit Instru ction Register Set Many of the 16 bit instructions use 3 bit register specifiers in their binary encodings The register set used for most of these 3 bit register specifiers is listed in Table 11 4 The register set used for SB16 SH16 SW16 source register is listed in Table 11 5 These register sets are a true subset of the register set available in 32 bit mode the 3 bit register specifiers can directly access 8 of the 32 registers available in 32 bit mode which uses 5 bit register specifiers In addition specific instructions in the 16 bit instruction set implicitly reference the stack pointer register sp global pointer register gp the return address register ra the integer multiplier divider output registers HI LO and the program counter PC Of these Table 11 6 lists sp gp and ra Table 11 7 lists the microMIPS special purpose regis ters including PC HI and LO The microMIPS also contains some 16 bit instructions that use 5 bit register specifiers Such 16 bit instructions pro vide access to all 32 general purpose registers Table 11 4 16 Bit Instruction General Purpose Registers 2 7 16 17 16 Bit 32 Bit MIPS Symbolic Name Register Register From Encoding Encoding ArchDefs h D
29. An instruction flow of this is shown in Figure 2 16 Figure 2 16 IU Pipeline A to E Data bypass One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle Load Instruction l E w M A Data bypass from A to E p M A Consumer of Load Data Instruction LLL One Clock Load Delay 2 6 2 Move from HI LO and CPO Delay As indicated in Figure 2 30 not only load data but also data moved from the HI or LO registers MFHI MFLO and data moved from CPO MFCO enters the IU Pipeline in the A stage That is data is not available in the integer pipe line until early in the A stage The A to E bypass is available for this data But as for Loads an instruction following immediately after one of these move instructions must be paused for one cycle if the target of the move is among the MIPS32 M14K Processor Core Software User s Manual Revision 02 03 43 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Pipeline of the M14K Core sources of the following instruction and this causes an interlock slip in the E stage see 2 10 Instruction Interlocks on page 46 An interlock slip after a MFHI is illustrated in Figure 2 17 MFHI to R3 ADD R4 R34R5 Figure 2 17 IU Pipeline Slip after a MFHI One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle M A w Data bypass from A to E E slip E M A W 2 7
30. BadVA is set only for AdEL S exceptions Note Set Cause EXCCode CE not set if itis a Bus Error BadVA VA Check if exception within another exception Yes Instr in Br Dly Slot EPC lt PC 4 EPC PC CauseBD 1 Causegp lt 0 Processor forced to Kernel Mode Ginterrupt disabled 0 normal 1 bootstrap PC lt 0x8000_0000 180 PC lt OxBFCO 0200 180 unmapped cached unmapped uncached To General Exception Servicing Guidelines 92 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 9 Exception Handling and Servicing Flowcharts Figure 4 4 General Exception Servicing Guidelines SW Comments EXL 1 so Watch Interrupt exceptions disabled OS System to avoid all other exceptions Only Reset Soft Reset NMI exceptions possible MFCO EPC Status Cause AMA MTCO Set Status bits UM e 0 EXL 0 IE 1 Optional only to enable Interrupts while keeping Kernel Mode d boe amp J ump to appropriate After EXL 0 all exceptions allowed except ervice Code interrupt if masked by IE PIENA AL A i Service Code i l MTCO EPC STATUS ERET is not allowed in the branch delay slot of another ump Instruction Processor does notexecute the instruction which is in the ERET s branch delay slot ERET PC EPC EXL 0 LLbit 0
31. DCFipcg and written to a TAP register The old value in the TAP register is overwritten by the new value even if this register has not been read out by the debug probe The presence or absence of Data Address Sampling is indicated by the DAS Data Address Sample bit in the Debug Control Register and enabled by the DASe Data Address Sampling Enable bit in the Debug Control Register The sample rate is specified by the 3 bit PCR PC Sample Rate field bits 8 6 in the Debug Control Register DCR These three bits encode a value 2 to 2 in a manner similar to the specification of SyncPeriod When the implemen tation allows these bits to be written the internal PC sample counter will be reset by each write so that counting for the requested sample rate is immediately restarted The sample format includes a New data bit the sampled value the ASID of the sampled value if not disabled by PCnoASID bit 25 in DCR Figure 8 35shows the format of the sampled values in the PCSAMPLE TAP register for MIPS32 The New data bit is used by the probe to determine if the sampled data just read out is new or has already been read and must be discarded Figure 8 35 PCSAMPLE TAP Register Format MIPS32 40 33 32 1 0 ASID if enabled PC or Data Address New The sampled PC value is the PC of the graduating instruction in the current cycle If the processor is stalled when the PC sample counter overflows then the sampled PC is the PC of the next grad
32. GPR 29 temp29 if IntCtleo gy 1 Statusgy amp 0 Statusgksg 0 endif Causerc amp 1 ClearHazards PC CalcIntrptAddress endif endif function LoadStackWord vaddr if vAddr o 0 then SignalException AddressError endif pAddr CCA lt AddressTranslation vAddr DATA LOAD memword lt LoadMemory CCA WORD pAddr vAddr LoadStackWord lt memword endfunction LoadStackWord function CalcIntrptAddress if StatusBEV 1 vectorBase OxBFC0 0200 else if ArchitectureRevision 2 2 vectorBase EBase 4 45 013 else vectorBase 0x8000 0000 endif endif if Causey 0 vectorOffset 0x180 else MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 259 if Statuspggy 1 or IntCtlyg 0 vectorOffset 0x200 else if Config3yg c 1 and EIC Option 1 VectorNum Causeprpr elseif Config3yg o 1 and EIC Option 2 VectorNum EIC VectorNum elseif Config3yprc 0 VectorNum VIntPriorityEncoder endif if Config3yg c 1 and EIC Option 3 vectorOffset EIC VectorOffset else vectorOffset 0x200 VectorNum x IntCtlyg 0 endif endif endif CalcIntrptAddress vectorBase vectorOffset endfunction CalcIntrptAddress Exceptions Coprocessor Unusable Exception TLB Refill TLB Invalid Address Error Watch Cache Error Bus Error Exceptions
33. In this example two clocks 3 and 4 are required to fetch the I4 instruction from memory After the cache miss has been resolved in clock 4 and the instruction is bypassed to the E stage the pipeline is restarted causing IL to finally execute it s E stage operations 2 10 Instruction Interlocks 46 Most instructions can be issued at a rate of one per clock cycle In order to adhere to the sequential programming model the issue of an instruction must sometimes be delayed to ensure that the result of a prior instruction is avail MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 2 11 Hazards able Table 2 5 details the instruction interactions that prevent an instruction from advancing in the processor pipe line Table 2 5 Instruction Interlocks Instruction Interlocks Issue Delay in First Instruction Second Instruction Clock Cycles Slip Stage LB LBU LH LHU LL LW LWL LWR Consumer of load data 1 E stage MFCO Consumer of destination regis 1 E stage ter MULTx MADDx MSUBx 16bx32b MFLO MFHI 0 high performance MDU 32bx32b 1 M stage MUL 16bx32b Consumer of target data 2 E stage high performance MDU 32bx32b 3 E stage MUL 16bx32b Non Consumer of target data 1 E stage high performance MDU 32bx32b 2 E stage MFHI MFLO Consumer of target data 1 E stage MULTx MADDx MSUBx 16bx32b MULT MUL MADD MSUB oll E
34. MIPS Document MD00047 12 MIPS cJTAG Adapter User s Manual MIPS Document MD00862 13 Security Features of the M14K Processor Family MIPS document MD00896 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 291 Copyright 2009 2010 MIPS Technologies Inc All rights reserved References 292 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Appendix B Revision History Change bars vertical lines in the margins of this document indicate significant changes in the document since its last release Change bars are removed for changes that are more than one revision old This document may refer to Architecture specifications for example instruction set descriptions and EJTAG register definitions and change bars in these sections indicate changes since the previous version of the relevant Architecture document Revision Date Description 01 00 March 25 2010 Initial 1_0_0 release 02 00 December 17 2010 e 2 0_0 Maintenance release 02 01 September 30 2011 e 2 1 0 Maintenance release 02 02 March 12 2012 e 2 a O0 Patch release 02 03 April 30 2012 22 0Maintenance release MIPS32 M14K Processor Core Software User s Manual Revision 02 03 293 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Revision History 294 MIPS32 M14K Processor Core Software User s Manual Revision 02 0
35. RegRd KACI 1 AC2 ALU Op D AC D SRAM Align RegW MUL Multiply Divide MDU Res Rdy Us SRAM read Instruction Decode Register file read Instruction Address Calculation stage 1 and 2 Arithmetic Logic and Shift operations Data Address Calculation D SRAM read Load data aligner Register file write MUL instruction Multiply Multiply Acc And Divide Result can be read from MDU One or more cycles 32 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 2 1 Pipeline Stages e If both MIPS32 and microMIPS ISAs are supported microMIPS instructions are converted to MIPS32 like instructions If the MIPS32 ISA is not supported 16 bit microMIPS instructions will be first recoded into 32 bit microMIPS equivalent instructions and then decoded in native microMIPS ISA format 2 1 2 E Stage Execution During the Execution stage e Operands are fetched from the register file e Operands from the M and A stage are bypassed to this stage e The Arithmetic Logic Unit ALU begins the arithmetic or logical operation for register to register instructions e The ALU calculates the data virtual address for load and store instructions and the MMU performs the fixed vir tual to physical address translation e The ALU determines whether the branch condition is true and calculates the virtual
36. Table 8 15 DBGM Register Field Deserpliorte io oes sens etes ane oet E REM RIDE E RES SEMI DESSEN RRRGS 178 Table 8 16 BBV mn Register Field DescriptOns aerei eene eaten pae rta reper ta terere xat EINE 179 Table 8 17 DBCCn Register Field Descriptions iieri dextera a Ere sin ee riacnad gee SIR E MSS 180 Table 9 18 DBBPCn Register Field BescriptiOTiS xac co cet Ete sepa better tu te aen o terat etr Gere boc a t a iaaii 181 Table 8 19 DVM Register Field D amp SCIIDTOFIS s 3 51 25 1o easiest bce eas ee es 181 Table 8 20 Addresses for Complex Breakpoint Registers ccccceeeeeececeeeeeeeeeeeeeeeeeeaaeeeceeeeeeaaeseeeeeeseaaeeneneeeee 182 Table 8 21 GBTO Register Field DescriptioI S scooter seca a sad sten nera a e de cRE d EXPO RES U RAS 182 Table 8 23 Priming Conditions and Register Values for 61 2D Configuration ssssseees 184 Table 8 24 Priming Conditions and Register Values for 81 4D Configuration sse 184 Table 8 22 PrCndA Register Field Descriptions sssssssssssssessesesses ener nitentes stent 184 Table 8 25 STGIl Begister Field DescriptiOlls ocupa iod oper uisu dea cu o dre a usc pte nes meae E pUF P RR MSS 185 Table 8 26 ST GU Register Field BescriptiOhs aio petet io eee trea sen et ieri ense ardaig 186 Table 8 27 EJTAG lite mace IP ins acci eoo ep otim De tete tu Gu d Epist DEED Ide erbu e Socaideebeadeceeattnneioceiiese 190 Table 8 28 Implemented
37. atic od ecrire reir eger mx de de e dr ted ds 100 52 7 Intell Register CPO Register 12 Select 1 aieo cen tirare eei n ea aae 104 5 2 8 SRSCtl Register CPO Register 12 Select 2 sssssssssssssssssseseeneeeeeen e 108 5 2 9 SRSMap Register CPO Register 12 Select 3 i etae ore ic iris te HEEL eo de pU Get eaves 111 5 2 10 View IPLE Register CPO Register 12 Select 4 sedere eere teri erede reta dan 112 5 2 11 SHSMap2 Register GPO Register 12 Select b eter eiecti ix retia eie oce uiuos iuba 112 5 2 12 Cause Register CPO Register 13 Select 0 nennen 113 5 2 13 View RIPE Register CPO Register 19 Select 4 rire tiae tee nies 118 5 2 14 NestedExe CPO Register 193 Select 5 eerie tte Mia cerea tei tak epe teda feu tud aes 118 5 2 15 Exception Program Counter CPO Register 14 Select O rissies esanen 119 4 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 16 NestedEPC CPO Register 14 Select 2 sc cccisiesccttesseedictstenscoccdensstnecetieaandceevensnoesttavanceeeadsh enenctenae 120 5 2 17 Processor Identification CPO Register 15 Select 0 ec i ecesceeeeeeeeeeneeeeeeeeeeeaaeseeeeeeeeaaeeneneeeess 121 5 2 18 EBase Register GPO Register 15 Select T uai e e ier e e 122 5 2 19 CDMMBase Register CPO Register 15 Select 2 123 5 2 20 Config Register CPO Register 16 Select 0
38. c retener to xr re atro YR areara 124 Figure 5 21 Config Register Field DescriptlOis ouai orte tene a yis acdeyedsvieanegdanaleantces 124 Figure 5 22 Configi Register Format Seleti 2 d tete tte aaa aea Ia 126 Figure 5 28 Contig2 Register Format Select 28 i um ete pie Ie Un Debut test udiptetaisea oc edd uia 127 Figure 5 24 Contigs Register ORTTiab secun Snedesedtceseoectus o i aeaaaee 128 Figure 5 25 Gontig4 Register FON ates au ooi oce iee Dea etti ater on ipte decia Mes ua Uno bebe Rr aa d NEN REP A dgRaS 131 Figure 5 26 Contigo Register Oma arisi Tarnania aan apa et as oem toman utere es tud RE MI e ott Exe pP IdpfeA UIS 132 Figure 5 27 Gontigz Register FORMAL sires noa ter esu aen odore ned pekte Senoegil tne alise ped peces eua ceto eu aes 132 Figure 5 28 Debug Register FOFITSL oai der oett iab iti indes LANNO tener ae RR pede a rp ned eR mance 133 Figure 5 29 TraceControl Register FORMAL 2 dre roberto icem tnde iee pibe aimed ate auc iren d rremazS ERI RUE dERS 137 1gure 5 90 TraceContol2 Register FFOHTIal 22 5 0 aeter i e taseeu ioter ie tasted De usate hse o eai 139 Figure 5 31 User Trace Datal User Trace Data2 Register Format eeseeeeeeee 141 Figure 5 32 Trace BPG Register OMA uaria roche iba ie ea bas daana 142 Figure 5 33 Debuga2 Register FFOITIBU ooo curtesidereei R ERR 143 Figuite 5 34 biz extenuat m re 144 Figure 5 35 Performance Counter Control Register eet ante uere hikes aspe en
39. indicates to the trace disassembler that Extended Filtered Data Tracing mode is enabled CYC Delta Cycle Mode This mode can be set in combination Optional for with the EST special trace modes When set a delta cycle iFlowTrace rev value is included in each of the trace messages and indi 2 0 cates the number of cycles since the last message was gen erated If this tracing mode is not implemented the field is read only and read as zero FDT Filtered Data Trace mode If set on a data breakpoint Optional for match the data value of the matching breakpoint is traced iFlowTrace rev Normal tracing is inhibited when this mode is active If 2 0 this tracing mode is not implemented the field is read only and read as zero BM Breakpoint Match If set only instructions that match Optional for instruction or data breakpoints are traced Normal tracing iFlowTrace rev is inhibited when this mode is active If this tracing mode 2 0 is not implemented the field is read only and read as zero ER Trace exceptions and exception returns If set trace Optional for includes markers for exceptions and exception returns iFlowTrace rev Can be used in conjunction with the FCR bit Inhibits nor 2 0 mal tracing If this tracing mode is not implemented the field is read only and read as zero FCR Trace Function Calls and Returns If set trace includes Optional for markers for function calls and returns Can be used in con iFlowTrace rev junction with the ER bit
40. the controller transitions to the Capture IR state A 192 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 4 Test Access Port TAP HIGH on TMS causes the controller to transition to the Test Reset Logic state The instruction cannot change while the TAP controller is in this state 8 4 2 5 Capture_DR State In this state the boundary scan register captures the value of the register addressed by the Instruction register and the value is then shifted out in the Shift_DR If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Shift_DR state A HIGH on TMS causes the controller to transition to the Exit _DR state The instruction can not change while the TAP controller is in this state 8 4 2 6 Shift_DR State In this state the test data register connected between TD and TDO as a result of the current instruction shifts data one stage toward its serial output on the rising edge of TCK If TMS is sampled LOW on the rising edge of TCK the con troller remains in the Shift_DR state A HIGH on TMS causes the controller to transition to the Exit _DR state The instruction cannot change while the TAP controller is in this state 8 4 2 7 Exit1 DR State This is a temporary controller state in which all test data registers selected by the current instruction retain their previ ous state If TMS is sampled LOW at the rising edge
41. um eo 8 4 21 Test Logic Reset State In the Test Logic Reset state the boundary scan test logic is disabled The test logic enters the Test Logic Reset state when the TMS input is held HIGH for at least five rising edges of TCK The BYPASS instruction is forced into the instruction register output latches during this state The controller remains in the 7est Logic Reset state as long as TMS is HIGH 8 4 2 2 Run Test Idle State The controller enters the Run Test Idle state between scan operations The controller remains in this state as long as TMS is held LOW The instruction register and all test data registers retain their previous state The instruction cannot change when the TAP controller is in this state When TMS is sampled HIGH on the rising edge of TCK the controller transitions to the Select_DR state 8 4 2 3 Select DR Scan State This is a temporary controller state in which all test data registers selected by the current instruction retain their previ ous state If TMS is sampled LOW at the rising edge of TCK then the controller transitions to the Capture DR state A HIGH on TMS causes the controller to transition to the Select IR state The instruction cannot change while the TAP controller is in this state 8 4 2 4 Select IR Scan State This is a temporary controller state in which all test data registers selected by the current instruction retain their previ ous state If TMS is sampled LOW on the rising edge of TCK
42. 0 thereby causing a 0 to 1 transition If such a transi tion is caused by software it is UNPREDICTABLE whether hardware ignores the write accepts the write with no side effects or accepts the write and initiates a watch exception once Statusgy and Statusppy are both zero Because watch registers are not implemented on the M14K core this bit is ignored on writes and reads as zero Undefined MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 115 CPO Registers of the M14K Core Table 5 15 Cause Register Field Descriptions Continued Fields Name Bits Description Read Write Reset State FDCI 21 Fast Debug Channel Interrupt This bit denotes whether R Undefined a FDC Interrupt is pending analogous to the IP bits for other interrupt types Encoding Meaning 0 No Fast Debug Channel interrupt is pending 1 Fast Debug Channel interrupt is pend ing IPO IP2 17 10 Indicates an interrupt is pending R Undefined for IP7 IP2 Meaning Hardware Interrupt 7 0 for IP9 IP8 Hardware Interrupt 6 Hardware interrupt 5 Hardware interrupt 4 Hardware interrupt 3 Hardware interrupt 2 Hardware interrupt 1 Hardware interrupt 0 In implementations of Release 1 of the Architecture timer and performance counter interrupts are combined in an implementation dependen
43. 0 31 4 Reserved 0 0 Prm 3 Primed indicates whether a complex breakpoint with R Undefined an active priming condition was seen on the last debug exception DQ 2 Data Qualified indicates whether a complex break R Undefined point with an active data qualifier was seen on the last debug exception Tup 1 Tuple indicates whether a tuple breakpoint was seen R Undefined on the last debug exception PaCo 0 Pass Counter indicates whether a complex breakpoint R Undefined with an active pass counter was seen on the last debug exception MIPS32 M14K Processor Core Software User s Manual Revision 02 03 143 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core 144 5 2 33 Debug Exception Program Counter Register CPO Register 24 Select 0 The Debug Exception Program Counter DEPC register is a read write register that contains the address at which processing resumes after a debug exception or debug mode exception has been serviced For synchronous precise debug and debug mode exceptions the DEPC contains either e The virtual address of the instruction that was the direct cause of the debug exception or e The virtual address of the immediately preceding branch or jump instruction when the debug exception causing instruction is in a branch delay slot and the Debug Branch Delay DBD bit in the Debug register is set For asynchronous debug exceptions debug interrupt complex break
44. 1 Statusggy 1 Act as ERET read Operation section of ERET description else if ISAMode EPC lt PC4 1 in case of memory exception else EPC PC in case of memory exception endif temp lt 0x4 GPR 29 tempStatus LoadStackWord temp ClearHazards if IntCtlyog 0 IntCtlyog 1 amp tempStatusyp gt EICRIPL temp 0x8 GPR 29 tempSRSCtl lt LoadStackWord temp temp 0x0 GPR 29 tempEPC LoadStackWord temp endif Status lt tempStatus if IntCtlicg 0 IntCtlu eg 1 amp tempStatusyp gt EICprpy GPR 29 GPR 29 DecodedValue IntCtlg xpec SRSCtl tempSRSCtl EPC tempEPC temp lt EPC StatuSpy amp 0 if ArchitectureRevision 2 2 and SRSCtlgss gt 0 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved and StatuSpry 0 then SRSCtloggs SRSCtlpgg endif if IsMicroMIPSImplemented then PC amp temp 4 0 ISAMode tempo else PC temp endif LLbit lt 0 Causezrc amp 0 ClearHazards else Signal EIC for Next Interrupt wait for EIC outputs to update CauSegrip ElCgrip SRSCtlgi cgg ElCgg temp29 GPR 29 GPR 29 lt GPR 29 DecodedValue IntCtletxpec StatuSyp lt Causeprpy SRSCtlogs SRSCtleress NewShadowSet lt SRSCtlgicss
45. 10 6 2 FDC Configuration FDCFG Register Offset 0x8 The FDC configuration register holds information about the current configuration of the Fast Debug Channel mecha nism Figure 8 39 has the format of the FDC Configuration register and Table 8 45 describes the register fields Figure 8 39 FDC Configuration Register 31 20 19 18 17 16 15 8 7 0 0 Tx_IntThresh Rx_IntThresh TxFIFOSize RxFIFOSize Table 8 45 FDC Configuration Register Field Descriptions Fields Read Reset Name Bits Description Write State 0 31 20 Reserved for future use Read as zeros must be written as R Zeros MIPS32 M14K Processor Core Software User s Manual Revision 02 03 229 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Table 8 45 FDC Configuration Register Field Descriptions Continued Fields Read Reset Name Bits Description Write State TxIntThresh 19 18 Controls whether transmit interrupts are enabled and the R W state of the TxFIFO needed to generate an interrupt Encoding Meaning 0 Transmit Interrupt Disabled 1 Empty 2 Not Full 3 Almost Empty zero or one entry in use see 8 10 2 for specifics RxIntThresh 17 16 Controls whether receive interrupts are enabled and the R W state of the RxFIFO needed to generate an interrupt 0 Encoding Meaning 0 Receive Interrupt Disabled 1 Full
46. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IVM DVM 0 RD CBT PCS PCR PCSe IntE NMIE NMI SRstE Prob Vec pend En Table 8 1 DCR Register Field Descriptions Fields Read Reset Name Bits Description Write State ENM 29 Endianess in which the processor is running in kernel R Preset and Debug Mode Encoding Meaning 0 Little endian 1 Big endian PCIM 26 Configure PC Sampling to capture all executed R addresses or only those that miss the instruction cache This feature is not supported and this bit will read as 0 Encoding Meaning 0 All PCs captured 1 Capture only PCs that miss the cache PCnoASID 25 Controls whether the PCSAMPLE scan chain includes R or omits the ASID field ASID is always included so this bit will read as 0 Encoding Meaning 0 ASID included in PCSAMPLE scan 1 ASID omitted from PCSAMPLE scan 160 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Fields 8 1 Debug Control Register Table 8 1 DCR Register Field Descriptions Continued Name Bits Description Read Write Reset State DASQ 24 Qualifies Data Address Sampling using a data break point Data address sampling is not supported so this bit will read as 0 Encoding Meaning 0 All data addresses are sampled 1 Sample matches of data breakpoint 0 R DASe DAS FDCImpl DataBrk 23 22
47. 2 Not empty 3 Almost Full zero or one entry free TxFIFOSize 15 8 This field holds the total number of entries in the transmit R Preset FIFO RxFIFOSize 7 0 This field holds the total number of entries in the receive R Preset FIFO 8 10 6 3 FDC Status FDSTAT Register Offset 0x10 The FDC Status register holds up to date state information for the FDC mechanism Figure 8 40 shows the format of the FDC Status register and Table 8 46 describes the register fields Figure 8 40 FDC Status Register 31 24 23 16 15 8 T 4 3 2 1 0 Tx_Count Rx_Count 0 RxChan RxE RxF TxE TxF Table 8 46 FDC Status Register Field Descriptions Fields Name Bits Description Tx Count 31 24 This optional field is not implemented and will read as 0 Rx Count 23 16 This optional field is not implemented and will read as 0 0 15 8 Reserved for future use Must be written as zeros and read as Zeros RxChan T 4 This field indicates the channel number used by the top R Undefined item in the receive FIFO This field is only valid if RxE 0 230 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 10 Fast Debug Channel Table 8 46 FDC Status Register Field Descriptions Continued Fields poo Read Name Bits Description Write RxE 3 If RxE is set the receive FIFO is empty If RxE is not set R the FIFO is not empty RxF 2 If RxF is s
48. 260 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 31 26 25 6 5 0 POOL32A POOL32AXf 000000 000 0000 0011 0100 1101 111100 6 20 6 Format IRET microMIPS and MCU ASE Purpose Interrupt Return with automated interrupt epilogue handling Optionally jump directly to another interrupt vector without returning to original return address Description IRET automates some of the operations that are required when returning from an interrupt handler and can be used in place of the ERET instruction at the end of interrupt handlers IRET is only appropriate when using Shadow Register Sets and the EIC Interrupt mode The automated operations of this instruction can be used to reverse the effects of the automated operations of the Auto Prologue feature If the EIC interrupt mode and the Interrupt Chaining feature are used the IRET instruction can be used to shorten the time between returning from the current interrupt handler and handling the next requested interrupt If the Automated Prologue feature is disabled then IRET behaves exactly like ERET If either the StatuSgg or Statusggy bits are set then IRET behaves exactly like ERET If Interrupt Chaining is disabled Interrupts are disabled COPO Status SRSCtl and EPC registers are restored from the stack GPR 29 is incre mented for the stack frame size IRET then clears execution and
49. 32 bit encoded instructions the instruction mnemonic can be optionally extended with the suffix 16 or 32 respectively This suffix is placed at the end of the instruction before the first if there is one For example ADD16 ADD32 ADD32 PS If these suffixes are omitted the assembler automatically chooses the smallest instruction size For each instruction the tables in this chapter provide all necessary information about the bit fields The formats of the instructions are defined in Section 9 1 CPU Instruction Formats Together with the major and minor opcode encod ings which can be derived from the tables in Section 10 2 M14K Opcode Map the complete instruction encoding is provided Most register fields have a width of 5 bits 5 bit register fields use linear encoding r0 00000 r1 00001 etc For 16 bit instructions whose register field size is variable the register field width is explicitly stated in the instruction table Table 11 1 and Table 11 2 and the individual register and immediate encodings are shown in Table 11 3 The other fields are defined by the respective column with the order of these fields in the instruction encoding defined by the order in the tables 11 3 1 16 Bit Category 11 3 1 1 Frequent MIPS32 Instructions These are frequent MIPS32 instructions with reduced register and immediate fields containing frequently used regis ters and immediate values MOVE is
50. 5 Branch Delay The pipeline has a branch delay of one cycle The one cycle branch delay is a result of the branch decision logic oper ating during the E pipeline stage This allows the branch target address to be used in the I stage of the instruction fol lowing 2 cycles after the branch instruction By executing the 1st instruction following the branch instruction sequentially before switching to the branch target the intervening branch delay slot is utilized This avoids bubbles being injected into the pipeline on branch instructions Both the address calculation and the branch condition check are performed in the E stage The pipeline begins the fetch of either the branch path or the fall through path in the cycle following the delay slot After the branch decision is made the processor continues with the fetch of either the branch path for a taken branch or the fall through path for the non taken branch The branch delay means that the instruction immediately following a branch is always executed regardless of the branch direction If no useful instruction can be placed after the branch then the compiler or assembler must insert a NOP instruction in the delay slot Figure 2 13 illustrates the branch delay MIPS32 M14K Processor Core Software User s Manual Revision 02 03 41 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Pipeline of the M14K Core Figure 2 13 IU Pipeline Branch Delay One Cycle One C
51. 9 xor ReverseEndian TempIE Statusrp Status p amp 0 memword lt LoadMemory CCA BYTE pAddr vAddr DATA byte vAddr 9 xor BigEndianC PU temp lt memword s pyte 8 byte temp lt temp and 1 0Pi xor OxFF dataword temp o8 byte StoreMemory CCA BYTE dataword pAddr vAddr DATA Statusyp lt TempIlE Exceptions TLB Refill TLB Invalid TLB Modified Address Error Watch Programming Notes Upon a TLB miss a TLBS exception is signalled in the ExcCode field of the Cause register For address error a ADES exception is signalled in the ExcCode field of the Cause register For other data stream related exceptions such as Debug Data Break exceptions and Watch exceptions it is implementation specific whether this instruction is treated as a load or as a store MIPS32 M14K Processor Core Software User s Manual Revision 02 03 249 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 250 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 31 26 25 24 23 21 20 16 15 12 11 0 POOL32B AO ACLR t 001000 0 bi base 1011 offset 6 2 3 5 4 12 Format LR bit offset base microMIPS and MCU ASE Purpose Atomically Clear Bit within Byte Description Disable interrupts temp memory GPR base offset temp lt temp and 1 lt lt bit memory GPR b
52. Although there are 255 EIC priority interrupts only 64 vectors are provided There is no one to one mapping for each EIC interrupt to its interrupt vector The 255 priority interrupts will share the 64 interrupt vectors as specified by the SI ElCVector 5 0 input pins However as mentioned in option 2 of Section 4 3 1 3 External Interrupt Controller Mode the S Offset 17 1 input pins can be used to provide each EIC interrupt with a unique interrupt handler loca tion 4 3 3 MCU ASE Enhancement for Interrupt Handling The MCU ASE extends the microMIPs MIPS32 Architecture with a set of new features designed for the microcon troller market The MCU ASE contains enhancements in two key areas interrupt delivery and interrupt latency For more details refer to the The MCU Privileged Resource Architecture chapter of the MIPS32 Architecture for Pro grammers Volume IV h The MuCon Application Specific Extension to the MIPS32 and microMIPS32 Architectures 10 4 3 3 1 Interrupt Delivery The MCU ASE extends the number of hardware interrupt sources from 6 to 8 For legacy and vectored interrupt mode this represents 8 external interrupt sources For EIC mode the widened PL and RIPL fields can now represent 256 external interrupt sources 4 3 3 2 Interrupt Latency Reduction The MCU ASE includes a package of extensions to microMIPS MIPS32 that decrease the latency of the processor s response to a signalled interrupt Interrupt Vector Prefetc
53. As such the Simple Interrupt code shown above need not save the GPRs A nested interrupt is similar to that shown for compatibility mode but may also take advantage of running the nested exception routine in the GPR shadow set dedicated to the interrupt or in another shadow set It also need only copy CaUuSepgyp to Status to prevent lower priority interrupts from interrupting the handler Such a routine might look as follows NestedException Nested exceptions typically require saving the EPC Status and SRSCtl registers setting up the appropriate GPR shadow set for the routine disabling the appropriate IM bits in Status to prevent an interrupt loop putting the processor in kernel mode and re enabling interrupts The sample code below can not cover all nuances of this processing and is intended only to demonstrate the concepts y Use the current GPR shadow set and setup software context mfcO k1 CO Cause Read Cause to get RIPL value mfcO k0 CO EPC Get restart address srl k1 k1 S CauseRIPL Right justify RIPL field sw k0 EPCSave Save in memory mfcO k0 CO Status Get Status value MIPS32 M14K Processor Core Software User s Manual Revision 02 03 73 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M14KT Core 74 sw k0 StatusSave ins k0 k1 S StatusIPL mfcO k1 CO SRSCtl1 sw k1 SRSCtlSave If
54. Behavior for Access to dmseg EJTAG Memory The behavior of CPU access to the dmseg address range at OxFF20_0000 to OxFF2F_FFFF is determined by the table shown in Table 3 5 Table 3 5 CPU Access to dmseg Address Range ProbEn bit in LSNM bit in Transaction DCR register Debug register Access Load Store Don t care 1 Kernel mode address space kseg3 Fetch 1 Don t care dmseg Load Store 1 0 Fetch 0 Don t care See comments below Load Store 0 0 The case with access to the dmseg when the ProbEn bit in the DCR register is 0 is not expected to happen Debug software is expected to check the state of the ProbEn bit in DCR register before attempting to reference dmseg If such a reference does happen the reference hangs until it is satisfied by the probe The probe can not assume that there will never be a reference to dmseg if the ProbEn bit in the DCR register is 0 because there is an inherent race between the debug software sampling the ProbEn bit as and the probe clearing it to 0 3 3 Fixed Mapping MMU The M14K core implements a simple Fixed Mapping FM memory management unit that is smaller than the a full translation lookaside buffer TLB and more easily synthesized Like a TLB the FM performs virtual to physical address translation and provides attributes for the different memory segments Those memory segments which are unmapped in a TLB implementation ksegO and kseg1 are translated identically by the
55. Coprocessor 2 Instructions 44 If a coprocessor 2 is attached to the M14K core a number of transactions must take place on the CP2 Interface for each coprocessor 2 instruction First if the CU 2 bit in the CPO Status register is not set then no coprocessor 2 related instruction will start a transaction on the CP2 Interface instead a Coprocessor Unusable exception will be signaled If the CU 2 bit is set and a coprocessor 2 instruction is fetched the following transactions will occur on the CP2 Interface 1 The Instruction is presented on the instructions bus in E stage Coprocessor 2 can do a decode in the same cycle 2 The Instruction is validated from the core in M stage From this point the core will accept control and data sig nals back from coprocessor 2 All control and data signals from coprocessor 2 are captured on input latches to the core 3 Ifall the expected control and data signals were presented to the core in the previous M stage the core will pro ceed to execute the A stage If some return information is missing the A stage will not advance and cause a slip in all I E and M stages see 2 9 Slip Conditions on page 46 If this instruction sent data from the core to coprocessor 2 this data is sent in the A stage 4 The instruction completion is signaled to coprocessor 2 in the W stage Potential data from the coprocessor is written to the register file Figure 2 18 shows the timing relationship between th
56. Coprocessor 2 Rt CPR 2 n sels 0 MFHC2 Move From High Word Coprocessor2 Rt CPR 2 n sel g5 3 MFHI Move From HI Rd HI MFLO Move From LO Rd LO MOVN Move Conditional on Not Zero if GPR rt 4 0 then GPR rd GPR rs MOVZ Move Conditional on Zero if GPR rt 0 then GPR rd GPR rs MSUB Multiply Subtract HI LO int Rs int Rt MSUBU Multiply Subtract Unsigned HI LO uns Rs uns Rt Copyright 2009 2010 MIPS Technologies Inc All rights reserved 245 M14K Processor Core Instructions Table 10 10 Instruction Set Continued Instruction Description Function MTCO Move To Coprocessor 0 CPR O n sel Rt MTC2 Move To Coprocessor 2 CPR 2 n sel 3 9 Rt MTHC2 Move To High Word Coprocessor 2 CPR 2 n sel g5 35 Rt MTHI Move To HI HI Rs MTLO Move To LO LO Rs MUL Multiply with register write HI LO Unpredictable Rd LO MULT Integer Multiply HI LO int Rs int Rd NOP No Operation Assembler idiom for SLL r0 r0 r0 NOR Logical NOR Rd Rs Rt OR Logical OR Rd zRsIRt ORI Logical OR Immediate Rt Rs Immed PREF Prefetch Nop RDHWR Read HardWare Register Rt HWR Rd RDPGPR Read GPR from Previous Shadow Set RdzSGPR SRSCtlpss Rt ROTR Rotate Word Right Rd Rtj4 1 0 l Rt3 sa ROTRV Rotate Word Right Variable Rd Rtg 9l Rts p SB Store Byte byte Mem Rs offset Rt SC Store Conditional Word if LL 1 mem Rxoffs Rt Rt LL SDBBP Software Debug
57. Copyright 2009 2010 MIPS Technologies Inc All rights reserved 11 3 microMIPS Re encoded Instructions The compact instruction JRC is to be used instead of JR when the jump delay slot after JR cannot be filled This saves code size Because JRC may execute as fast as JR with a NOP in the delay slot JR is preferred if the delay slot can be filled The breakpoint instructions BREAK and SDBBP include a 16 bit variant that allows a breakpoint to be inserted at any instruction address without overwriting more than a single instruction Table 11 1 16 Bit Re encoding of Frequent MIPS32 Instructions Major Opcode Name Register Number of Immediate Field Register Field Size Width Fields bit Total Size of Other Fields Empty 0 Field Size Minor Opcode Size bit Comment ADDIUS5 POOL16D Add Immediate Unsigned Word Same Register ADDIUSP POOL16D ADDIUR2 POOLI6E Add Immediate Unsigned Word to Stack Pointer Add Immediate Unsigned Word Two Registers ADDIURISP POOLI16E Add Immediate Unsigned Word One Registers and Stack Pointer ADDUI6 POOLI16A AND16 POOL16C Add Unsigned Word AND Immediate ANDII6 ANDII6 B16 B16 BREAK16 POOL16C Branch Cause Breakpoint Exception JALR16 POOL16C Jump and Link Register 32 bit delay slot Jump and Link Register 16 bit delay slot JALRS16 POOL16C JR16 POOL16C Jump Register Load Byte Unsigned Load Halfwor
58. Core 96 Table 5 1 CPO Registers Continued Register Name Function Status IntCtl SRSCtl SRSMap1 View_IPL SRSMAP2 Cause View_RIPL NestedExc Processor status and control interrupt control and shadow set control Cause of last exception EPC NestedEPc PRId EBase CDMMBase Config Config1 Config2 Config3 Config4 Config5 Config7 Reserved Program counter at last exception Processor identification and revision exception base address Common Device Memory Map Base register Configuration registers Reserved in the MIAK core Debug Debug2 TraceControl TraceControl2 UserTraceData1 TraceBPC EJTAG Debug register EJTAG Debug register 2 EJTAG Trace Control register EJTAG Trace Control register2 EJTAG User Trace Datal register EJTAG Trace Breakpoint Register DEPC UserTraceData2 PerfCtlo PerfCntO PerfCtl1 PerfCnt1 ErrCtl Program counter at last debug exception EJTAG User Trace Data2 register Performance counter 0 control Performance counter 0 Performance counter control Performance counter 1 Software parity check enable CacheErr Records information about SRAM parity errors Reserved ErrorEPC Reserved in the M14K core Program counter at last error DeSAVE Debug handler scratchpad register 1 Registers used in exception processing 2 Registers used in debug MIPS32 M14K Processor Core Software User
59. EJ FAG INStUCHONG us iiu prote e PE plo seen Pr rer o ddiet naeia 195 12 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Table 8 30 Implementation Register Descriptions ssssessssssssesesss esent nnne nnns snnt 199 Table 8 29 Device Idenurcation BegISIBE iudicent iine cuuo diis reco xd ess uude pc dar bo csedis tu dins etre 199 Table 8 91 EJTAG Control Register Desclpltiohs ooi ioo Eee a Pise eti iue eo deu boc ie Eee 201 Table 8 32 Fastdata Register Field DescrlpllOnm oio Lo staccaets ato see Deo DERE SUO eR EcL DURO NAKANE ER 207 Table 8 33 Operation of the FASTDATA access sssssssssssseeseeeenenen nennen nnne nennen nnne enne nennen ennt 208 Table 8 34 EJ DisableProbeDebug Signal Overview sss esee eene enne nnns tenen 211 Table 8 35 Data Bus Encoding cuire rtt i iaa E Lo sgh viuo apa sabecestusscdcesh boston EREEREER 217 Taole 8 36 Tag BLEN OOM een N ices ctek iataeetin deena reek is 218 Table 8 37 Control Status Register Field Descriptions sssessssiessseseeeseeen enne 219 Table 8 38 ITCBTW Register Field Descriptions erint eene atre a eR sees M n REM ARRAS 220 Table 8 99 TCBRDP Register Field Descrlplloris cori seat retenu ate t hse te e bci Satu RE iaaea 221 Table 8 40 ITCBWRP Register Field Descriptions ooa etnia a R 221 Table 8 41 drseg Re
60. EJTAGBOOT option is used to boot into DebugMode see Chapter 8 EJTAG Debug Support in the M14K Core on page 159 for details MIPS32 M14K Processor Core Software User s Manual Revision 02 03 153 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Hardware and Software Initialization of the M14K Core e Debug sym cleared to 0 on Reset SoftReset e DebugijgysEp cleared to 0 on Reset SoftReset e DebugpgusEp cleared to 0 on Reset SoftReset e Debugygy cleared to 0 on Reset SoftReset e Debugss cleared to 0 on Reset SoftReset 6 1 2 Bus State Machines All pending bus transactions are aborted and the state machines in the SRAM interface unit are reset when a Reset or SoftReset exception is taken 6 1 3 Static Configuration Inputs All static configuration inputs should only be changed during Reset 6 1 4 Fetch Address Upon Reset SoftReset unless the EJTAGBOOT option is used the fetch is directed to VA OXBFCO00000 PA Ox1FC00000 This address is in KSeg1 which is unmapped and uncached 6 2 Software Initialized Processor State 154 Software is required to initialize the following parts of the device 6 2 1 Register File The register file powers up in an unknown state with the exception of r0 which is always 0 Initializing the rest of the register file is not required for proper operation in hardware However when simulating the operation of the core unknown values can cause problems Thus
61. Execution Exception Integer Overflow The integer overflow exception is one of the nine execution exceptions All of these exceptions have the same prior ity An integer overflow exception occurs when selected integer instructions result in a 2 s complement overflow Cause Register ExcCode Value Ov Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 8 20 Execution Exception Trap The trap exception is one of the nine execution exceptions All of these exceptions have the same priority A trap exception occurs when a trap instruction results in a TRUE value Cause Register ExcCode Value Tr Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 8 21 Debug Data Break Exception A debug data break exception occurs when a data hardware breakpoint matches the load store transaction of an exe cuted load store instruction The DEPC register and DBD bit in the Debug register will indicate the load store instruc tion that caused the data hardware breakpoint to match The load store instruction that caused the debug exception has not completed e g not updated the register file and the instruction can be re executed after returning from the debug handler Debug Register Debug Status Bit Set DDBL for a load instruction or DDBS for a store instruction MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 201
62. FM MMU The FM also determines the cacheability of each segment These attributes are controlled via bits in the Config regis ter Table 3 6 shows the encoding for the K23 bits 30 28 KU bits 27 25 and KO bits 2 0 of the Config register The M14K core does not contain caches and will treat all references as uncached but these Config fields will be sent out to the system with the request and it can choose to use them to control any external caching that may be present Table 3 6 Cacheability of Segments with Block Address Translation Virtual Address Range Cacheability useg kuseg 0x0000_0000 Controlled by the KU field bits 27 25 of the Config register Ox7FFF_FFFF ksegO 0x8000_0000 Ox9FFF_FFFF Controlled by the KO field bits 2 0 of the Config register MIPS32 M14K Processor Core Software User s Manual Revision 02 03 59 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Memory Management of the M14K Core Table 3 6 Cacheability of Segments with Block Address Translation Continued Virtual Address Segment Range ksegl 0xA000 0000 OxBFFF FFFF Always uncacheable Cacheability kseg2 0xC000_0000 OxDFFF FFFF kseg3 OxE000 0000 OxFFFF FFFF Controlled by the K23 field bits 30 28 of the Config register Controlled by K23 field bits 30 28 of the Config register The FM performs a simple translation to map from virtual addresses to physical addres
63. Get restart address Sw k0 EPCSave Save in memory mfcO k0 CO Status Get Status value sw k0 StatusSave Save in memory mfcO k0 CO SRSCt1 Save SRSCtl if changing shadow sets sw k0 SRSCtlSave MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 3 Interrupts li k1 IMbitsToClear Get Im bits to clear for this interrupt FE this must include at least the IM bit JR for the current interrupt and may include o others and k0 kO k1 Clear bits in copy of Status If switching shadow sets write new value to SRSCtlpss here ins k0 zero S StatusEXL W StatusKSU W StatusERL W StatusEXL Clear KSU ERL EXL bits in k0 mtcO k0 CO Status Modify mask switch to kernel mode re enable interrupts Tf switching shadow sets clear only KSU above write target address to EPC and do execute an eret to clear EXL switch shadow sets and jump to routine uA Process interrupt here including clearing device interrupt To complete interrupt processing the saved values must be restored and the original interrupted code restarted KY di Disable interrupts may not be required lw k0 StatusSave Get saved Status including EXL set lw k1 EPCSave JE and EPC mtcO k0 CO Status Restore the original value lw k0 SRSCtlSave Get
64. IRET instruction which is introduced in this ASE Interrupt Chaining An optional feature of the Automated Interrupt Epilogue this feature allows handling a second interrupt after a pri mary interrupt is handled without returning to non exception mode and the related pipeline flushes that would nor mally be necessary 4 4 GPR Shadow Registers 76 Release 2 of the Architecture optionally removes the need to save and restore GPRs on entry to high priority inter rupts or exceptions and to provide specified processor modes with the same capability This is done by introducing multiple copies of the GPRs called shadow sets and allowing privileged software to associate a shadow set with entry to kernel mode via an interrupt vector or exception The normal GPRs are logically considered shadow set zero The number of GPR shadow sets is a build time option on the M14K core Although Release 2 of the Architecture defines a maximum of 16 shadow sets the core allows one the normal GPRs two four eight or sixteen shadow sets The highest number actually implemented is indicated by the SRSCthysg field If this field is zero only the normal GPRs are implemented Shadow sets are new copies of the GPRs that can be substituted for the normal GPRs on entry to kernel mode via an interrupt or exception Once a shadow set is bound to a kernel mode entry condition reference to GPRs work exactly as one would expect but they are redirected to registers
65. Kernel virtual address space kseg0 Unmapped 512MB seg 0x8000_0000 Ox7FFF FFFF Fixed Mapped 2048MB kuseg 0x0000 0000 Table 3 2 Kernel Mode Segments Status Register Is One of These Values Address Bit Segment Segment Values UM EXL ERL Name Address Range Size A 31 20 UM 0 0x0000 0000 2 GBytes 23 Or through bytes EXL 1 Ox7FFF FFFF A 31 29 1005 re 0x8000_0000 512 MBytes ERL 1 a through 27 bytes DM 0 Ox9FFF FFFF A 31 29 1015 O0xA000 0000 512 MBytes through 279 bytes OxBFFF FFFF A 31 29 1105 0xCO000 0000 512 MBytes through 2 bytes OxDFFF FFFF A 31 29 1115 kseg3 OxEO00 0000 512 MBytes through 2 bytes OxFFFF FFFF 56 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 3 2 Modes of Operation 3 2 3 1 Kernel Mode User Space kuseg In Kernel mode when the most significant bit of the virtual address A31 is cleared the 32 bit kuseg virtual address space is selected and covers the full g bytes 2 GBytes of the current user address space mapped to addresses 0x0000 0000 Ox7FFF FFFF When ERL 1 in the Status register the user address region becomes a 2 byte unmapped and uncached address space While in this setting the kuseg virtual address maps directly to the same physical address 3 2 3 2 Kernel Mode Kernel Space 0 kseg0 In Kernel mode when the most sign
66. M14K Core 2 11 1 Types of Hazards With one exception all hazards were eliminated in Release of the Architecture for unprivileged software The exception occurs when unprivileged software writes a new instruction sequence and then wishes to jump to it Such an operation remained a hazard and is addressed by the capabilities of Release 2 In privileged software there are two types of hazards execution hazards and instruction hazards Execution hazards are those created by the execution of one instruction and seen by the execution of another instruc tion Table 2 6 lists execution hazards Table 2 6 Execution Hazards Spacing Producer gt Consumer Hazard On Instructions MTCO gt Coprocessor instruction execution depends on the new value of Sta Statuscy 1 tuscy MTCO gt ERET EPC 1 DEPC ErrorEPC MTCO gt ERET Status 0 MTCO EI DI gt Interrupted Instruction Statusyp 1 MTCO gt Interrupted Instruction Causeyp 3 MTCO gt RDPGPR SRSCtlpss 1 WRPGPR MTCO gt Instruction not seeing a Timer Interrupt Compare 4 update that clears Timer Interrupt MTCO gt Instruction affected by change Any other CPO 2 register 1 This is the minimum value Actual value is system dependent since it is a function of the sequential logic between the S Timerlnt output and the external logic which feeds S _ Timerint back into one of the S Int inputs or a function of the method for handling SI Timerlntin an extern
67. MDU and a higher performance 32x16 array The MDU consists of an iterative or 32x16 Booth encoded multiplier result accumulation registers HI and LO multiply and divide state machines and all multiplexers and control logic required to perform these functions The high performance pipelined MDU supports execution of a 16x16 or 32x16 multiply operation every clock cycle 32x32 multiply operations can be issued every other clock cycle Appropriate interlocks are implemented to stall the issue of back to back 32x32 multiply operations Divide operations are implemented with a simple 1 bit per clock iterative algorithm and require 35 clock cycles in worst case to complete Early in to the algorithm detects sign extension of the dividend if it is actual size is 24 16 or 8 bit the divider will skip 7 15 or 23 of the 32 iterations An attempt to issue a subsequent MDU instruction while a divide is still active causes a pipeline stall until the divide operation is completed The area efficient non pipelined MDU consists of a 32 bit full adder result accumulation registers HI and LO a combined multiply divide state machine and all multiplexers and control logic required to perform these functions It performs any multiply using 32 cycles in an iterative 1 bit per clock algorithm Divide operations are also imple mented with a simple 1 bit per clock iterative algorithm no early in and require 35 clock cycles to complete An attempt to issue a subsequent
68. MDU instruction while a multiply divide is still active causes a pipeline stall until the operation is completed The M14K implements an additional multiply instruction MUL which specifies that lower 32 bits of the multiply result be placed in the register file instead of the HI LO register pair By avoiding the explicit move from LO MFLO instruction required when using the LO register and by supporting multiple destination registers the throughput of multiply intensive operations is increased Two instructions multiply add MADD MADDU and multiply subtract MSUB MSUBU are used to perform the multiply add and multiply subtract operations The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers Similarly the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers The MADD MADDU and MSUB MSUBU operations are commonly used in Digital Signal Processor DSP algorithms 2 1 4 System Control Coprocessor CPO In the MIPS architecture CPO is responsible for the virtual to physical address translation the exception control sys tem the processor s diagnostics capability operating mode selection kernel vs user mode and the enabling dis abling of interrupts Configuration information such as presence of build time options like microMIPS CorExtend ASE or Coprocessor 2 interface is also available by accessing the CPO regis
69. MIPS32 M14K Processor Core Software User s Manual Revision 02 03 93 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M14KT Core 94 Figure 4 5 Reset Soft Reset and NMI Exception Handling and Servicing Guidelines Reset Soft Reset amp NMI Exception Handling HVV Reset Soft Reset amp NMI Servicing Guidelines SWV Reset Exception Config Reset state Soft Reset or NMI Exception Status RP lt 0 BEV 1 BEV 1 TS 0 TS lt 0 SR 1 0 SR 0 NMI 0 1 NMI 0 ERL 1 ERL 1 ErrorEPC PC PC lt OxBFCO 0000 zZz wn e 1 a D O o 2 D Soft Reset Service Code l Reset Service Code l lon e i a E ur Se See eee ee Se ee Optional MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers of the M14K Core The System Control Coprocessor CPO provides the register interface to the M14K processor core and supports memory management address translation exception handling and other privileged operations Each CPO register has a unique number that identifies it this number is referred to as the register number For instance the PageMask regis ter is register number 5 For more information on the EJTAG registers refer to Chapter 4 Exceptions and Interrupts in the M
70. MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 34 Performance Counter Register CPO Register 25 select 0 3 The M14K processor defines two performance counters and two associated control registers which are mapped to CPO register 25 The select field of the MTCO MFCO instructions are used to select the specific register accessed by the instruction as shown in Table 5 38 Table 5 38 Performance Counter Register Selects Select 2 0 Register 0 Register 0 Control 2 Register 1 Control 3 Register 1 Count Each counter is a 32 bit read write register and is incremented by one each time the countable event specified in its associated control register occurs Each counter can independently count one type of event at a time Bit 31 of each of the counters are ANDed with an interrupt enable bit E of their respective control register to deter mine if a performance counter interrupt should be signalled The two values are then OR ed together to create the SI PCl output This signal is combined with one of the S nt pins to signal an interrupt to the M14K Counting is not affected by the interrupt indication This output is cleared when the counter wraps to zero and may be cleared in soft ware by writing a value with bit 31 0 to the Performance Counter Count registers NOTE the performance counter
71. REENA ER 119 Table 5 19 EPC Register Field DescFIpHOTIs soin ote PE eti teer CERE NEC eBe uir eec EA 120 Table 5 20 NestedEPC Register Field Descriptions essssisssssssesieseseeene enne nnns tenen 121 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 11 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Table 5 21 PRid Register Field DescrlpllOlig s ciucie ro Eph oboe hp rdan a eea orar a A AAEEen 121 Table 5 22 EBase Register Field Descriptioris o oot fe deep eise bar dies bto taddec ino edis dias ds 123 Table 5 23 CDMMBase Register Field Descriptions iarciet E sen trier ce Roc A 123 Table 5 24 Cache Coherency ALTIDUEOS cii Roscoe metus Get Rin aee eacdicds Urt DeS UE Fes RUE pE Sechs ie pLateMsuS EP aaaiedinte 126 Table 5 25 Config1 Register Field Descriptions Select 1 ssssssssssseeeeeeeneenes 126 Table 5 26 Config2 Register Field Descriptions Select 1 sssssssssssseeeeeeeneens 127 Table 5 27 Contigs Register Field Descriptions cioe o esas ose E to dta ipetao ed go esta eet e etate aout aE reete Aaaa 128 Table 5 28 Config4 Register Field DescriptiOtis ure octets eene teen Sero EEEE R a 131 Table 5 29 Config5 Register Field Descriptions 132 Table 5 90 Config Register Field Descripliolis eiii deese dpt Eaa 133 Table 5 91 Debug Register Field DescriptiOriss irte irrita apres a a taii Satu TE 134 Table 5 32 Trace
72. Saved None Entry Vector Used General exception vector offset 0x180 4 8 17 Execution Exception Coprocessor 2 Exception The Coprocessor 2 exception is one of the nine execution exceptions All of these exceptions have the same priority A Coprocessor 2 exception occurs when a valid Coprocessor 2 instruction cause a general exception in the Coproces sor 2 Cause Register ExcCode Value C2E Additional State Saved Depending on the Coprocessor 2 implementation additional state information of the exception can be saved in a Coprocessor 2 control register Entry Vector Used General exception vector offset 0x180 4 8 18 Execution Exception Implementation Specific 1 Exception The Implementation Specific 1 exception is one of the nine execution exceptions All of these exceptions have the same priority An implementation specific 1 exception occurs when a valid coprocessor 2 instruction cause an imple mentation specific 1 exception in the Coprocessor 2 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 89 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M14KT Core 90 Cause Register ExcCode Value IS1 Additional State Saved Depending on the coprocessor 2 implementation additional state information of the exception can be saved in a coprocessor 2 control register Entry Vector Used General exception vector offset 0x180 4 8 19
73. Soft Reset exception the state of the processor is not defined with the following exceptions e The Config register is initialized with its boot state e The RP BEV TS SR NMI and ERL fields of the Status register are initialized to a specified state e The ErrorEPC register is loaded with PC 4 if the state of the processor indicates that it was executing an instruc tion in the delay slot of a branch Otherwise the ErrorEPC register is loaded with PC Note that this value may or may not be predictable PC is loaded with OXBFCO 0000 Cause Register ExcCode Value None Additional State Saved None Entry Vector Used Reset OXBFCO 0000 82 M IPS326 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 8 Exception Descriptions Operation Config ConfigurationState StatuSpp amp 0 StatuSpry amp 1 Statusgs 0 Statusgg lt 0 1 depending on Reset or SoftReset Statusuy lt 0 StatuSpp 1 if InstructionInBranchDelaySlot then ErrorEPC PC 4 else ErrorEPC lt PC endif PC OxBFCO 0000 4 8 2 Debug Single Step Exception A debug single step exception occurs after the CPU has executed one two instructions in non debug mode when returning to non debug mode after debug mode One instruction is allowed to execute when returning to a non jump branch instruction otherwise t
74. Vectored Interrupt Mode Relative Priority Interrupt Type Interrupt Source Interrupt Vector Number Request Generated by Calculated From Priority Encoder Highest Priority Lowest Priority IP9 and IM9 IP8 and IM8 IP7 and IM7 IP6 and IM6 IP5 and IM5 IP4 and IM4 IP3 and IM3 IP2 and IM2 Software IP1 and IM1 IPO and IMO The priority order places a relative priority on each hardware interrupt and places the software interrupts at a priority lower than all hardware interrupts When the priority encoder finds the highest priority pending interrupt it outputs an encoded vector number that is used in the calculation of the handler for that interrupt as described below This is shown pictorially in Figure 4 1 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 69 Exceptions and Interrupts in the M14K Core 70 Figure 4 1 Interrupt Generation for Vectored Interrupt Mode Latch Mask Encode Generate IntCtlpry HW7 wipo To Any Interrupt o IM9 Request x Request HWS W IPS gt IMs Statusg HW5 8 W IP7 W IM7 B InCtlys 5 Hwa E pomi pha desse g HW gt I ips p gt IMS Ww 5 Vector g Exception 2t Number Vector Offset HW2
75. amp 0 endif MIPS32 M14K Processor Core Software User s Manual Revision 02 03 81 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M14K Core Debugp pits Debug Debugyait HaltStatusAtDebugl Debugpoze DozeStatusAtDebugl Debugpy amp 1 ExceptionType Exception Exception if EJTAGControlRegisterpyoptrap 1 then PC OxFF20 0200 else PC OxBFCO 0480 endif The same debug exception vector location is used for all debug exceptions The location is determined by the Prob Trap bit in the EJTAG Control register ECR as shown in Table 4 9 Table 4 9 Debug Exception Vector Addresses ProbTrap bit in ECR Register Debug Exception Vector Address 0 OxBFCO 0480 OxFF20 0200 in dmseg 4 8 Exception Descriptions The following subsections describe each of the exceptions listed in the same sequence as shown in Table 4 1 4 8 1 Reset SoftReset Exception A reset exception occurs when the S ColdReset signal is asserted to the processor a soft reset occurs when the SI Resetsignal is asserted These exceptions are not maskable When one of these exceptions occurs the processor performs a full reset initialization including aborting state machines establishing critical state and generally placing the processor in a state in which it can execute instructions from uncached unmapped address space On a Reset
76. and optionally also as a Debug exception breakpoint This register is only implemented if hardware breakpoints and the EJTAG PDTrace capability are both present Figure 5 32 Trace BPC Register Format 31 30 18 17 16 15 14 6 5 0 DE 0 DBPOn IE 0 IBPOn Table 5 35 TraceBPC Register Field Descriptions Fields Name Bits Description Read Write Reset State DE 31 Used to specify whether the trigger signal from R W 0 EJTAG data breakpoint should trigger tracing func tions or not 0 disables trigger signals from data breakpoints 1 enables trigger signals from data breakpoints 0 30 18 Reserved 0 0 DBPOn 17 16 Each of the 2 bits corresponds to the 2 possible R W 0 EJTAG hardware data breakpoints that may be imple mented For example bit 16 corresponds to the first data breakpoint If 2 data breakpoints are present in the EJTAG implementation then they correspond to bits 16 and 17 The rest are always ignored by the tracing logic because they will never be triggered A value of one for each bit implies that a trigger from the corresponding data breakpoint should start tracing And a value of zero implies that tracing should be turned off with the trigger signal IE 15 Used to specify whether the trigger signal from R W 0 EJTAG instruction breakpoint should trigger tracing functions or not Encoding Meaning 0 Disables trigger signals from instruc tion breakpoints 1 Enables t
77. be retained in the cache MIPS32 M14K Processor Core Software User s Manual Revision 02 03 267 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 268 Values of hint Field for PREF Instruction Reserved writeback_invalidate also known as nudge Restrictions None Operation vAddr lt GPR base sign extend offset pAddr CCA AddressTranslation vAddr DATA LOAD Prefetch CCA pAddr vAddr DATA hint Exceptions Bus Error Cache Error Prefetch does not take any TLB related or address related exceptions under any circumstances Programming Notes Prefetch cannot move data to or from a mapped location unless the translation for that location is present in the TLB Locations in memory pages that have not been accessed recently may not have translations in the TLB so prefetch may not be effective for such locations Prefetch does not cause addressing exceptions A prefetch may be used using an address pointer before the validity of the pointer is determined without worrying about an addressing exception It is implementation dependent whether a Bus Error or Cache Error exception is reported if such an error is detected as a byproduct of the action taken by the PREF instruction Typically this only occurs in systems which have high reliability requirements Prefetch operations have no effect on cache lines that were previously locked with the CACHE ins
78. branch target address for branch instructions e nstruction logic selects an instruction address and the MMU performs the fixed virtual to physical address translation e All multiply and divide operations begin in this stage 2 1 3 M Stage Memory Fetch During the Memory fetch stage e The arithmetic ALU operation completes e The data SRAM access is performed for load and store instructions e A 16x16 or 32x16 multiply calculation completes high performance MDU option e A 32x32 multiply operation stalls the MDU pipeline for one clock in the M stage high performance MDU option e A multiply operation stalls the MDU pipeline for 31 clocks in the M stage area efficient MDU option e Amultiply accumulate operation stalls the MDU pipeline for 33 clocks in the M stage area efficient MDU option e Adivide operation stalls the MDU pipeline for a maximum of 34 clocks in the M stage Early in sign extension detection on the dividend will skip 7 15 or 23 stall clocks only the divider in the fast MDU option supports early in detection 2 1 4 A Stage Align During the Align stage e Load data is aligned to its word boundary MIPS32 M14K Processor Core Software User s Manual Revision 02 03 33 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Pipeline of the M14K Core e A multiply divide operation updates the HI LO registers area efficient MDU option e Multiply operation performs th
79. by BE bit in the BCn register then a debug instruction break exception occurs if the IB match equation is true The corresponding BS n bit in the BS register is set when the breakpoint generates the debug exception The debug instruction break exception is always precise so the DEPC register and DBD bit in the Debug register point to the instruction that caused the IB match equation to be true The instruction receiving the debug exception does not update any registers due to the instruction nor does any load or store by that instruction occur Thus a debug exception from a data breakpoint can not occur for instructions receiving a debug instruction break exception The debug handler usually returns to the instruction causing the debug instruction break exception whereby the instruction is executed Debug software is responsible for disabling the breakpoint when returning to the instruction otherwise the debug instruction break exception reoccurs 8 2 4 2 Debug Exception by Data Breakpoint If the breakpoint is enabled by BE bit in the DBCn register then a debug exception occurs when the DB match con dition is true The corresponding BS n bit in the DBS register is set when the breakpoint generates the debug excep tion A debug data break exception occurs when a data breakpoint indicates a match In this case the DEPC register and DBD bit in the Debug register points to the instruction that caused the DB match equation to be true
80. compare but either all or none of the BS n bits must be set for these breakpoints e Ona load then none of the BS n bits for breakpoints with data value compare are allowed to be set since the load is not allowed to occur due to the debug exception from a breakpoint without a data value compare and a valid data value is therefore not returned Any BS n bit set prior to the match and debug exception are kept set since BS n bits are only cleared by debug soft ware The debug handler usually returns to the instruction causing the debug data break exception whereby the instruction is re executed This re execution may result in a repeated load from system memory since the load may have occurred previously in order to evaluate the breakpoint as described above I O devices with side effects on loads may not be re accessible without changing the system behavior The Load Data Value register was introduced to capture the value that was read and allow debug software to synthesize the load instruction without re accessing memory Debug software is responsible for disabling breakpoints when returning to the instruction otherwise the debug data break exception will reoccur 8 2 5 Breakpoint Used as Triggerpoint Both instruction and data hardware breakpoints can be setup by software so that a matching breakpoint does not gen erate a debug exception but only an indication through the BS n bit The TE bit in the BCn or DBCn register con trols if
81. ctc ados E priua fi aD D pag bdrEde 237 9 7 6 MSUBU Multiply and Subtract Unsigned Word tei reet tan tere tte Peine aon taeda 238 9 7 T MUE Multiply WEG ca eiosca en tte rN N E EE 238 9 7 8 SSNOP Superscalar inhibit NOP auci ooa bcd te Ferrar prece eid aA Yet eee rsen E 238 9 9 MCU ASE InstEle MOINS cosi ecd un disini een E E E S 238 Se IIT 238 902 cage Emm 238 succum Q 238 Chapter 10 M14K Processor Core Instructions eese nennen nnne 239 10 1 Understanding the Instruction DescrIplOFiSu erede tutae de Qeruetaed ta a tenancies 239 10 2 MIAK Opcode Mi zlo PEE 239 10 3 MIPS32 Instruction Set for the M14K core nnne ens 242 lel EM 249 ASGETS tes esse ieee cate coast AIME EE UMP LL ee 253 IRET cities eh UM SIL Eds dM ad epeteettaeesaaeet MM REN MIRI UE 257 E cunctum ueDn EDI MM MM ERU A cre errr III SUL err ree ERES 265 PE auesicidiecctiienecr denies Hx I EIN DIM E D UE 267 E AAA EE cece E ce me eee Pe 269 SING os p EUR 272 VAN ipeeereretercrrcnter rene ret reece tier er orrteer tren rerer srr ttre A A T E rr cree rete EE 273 Chapter 11 microMIPS Instruction Set Architecture eere 275 Ue ire a E N a S A fiabaeesed Dea edeaed tiene 275 WATS MIP SES TM Arhitecti esci paca cett tt ere Renee a iaai 275 13 1 2 Default ISA MOde aoreet aer ice ere bos edes a ou inane aedi d Aine eee 276 jus Bopeeton E r aBsire
82. fields in the TraceControl2 register are read only but have a reset state of Undefined This is because these values are loaded from the Trace Control Block TCB see Section 8 8 6 ITCB Register Interface for Software Configurability As such these fields in the TraceControl2 register will not have valid values until the TCB asserts these values This register is only implemented if the EJTAG PDTrace capability is present Figure 5 30 TraceControl2 Register Format 31 7 6 5 4 3 2 0 Valid 0 Modes TBI TBU SyP Table 5 33 TraceControl2 Register Field Descriptions Fields Name Bits Description Read Write Reset State 0 31 5 Reserved for future use Must be written as zero returns zero on read MIPS32 M14K Processor Core Software User s Manual Revision 02 03 139 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core 140 Table 5 33 TraceControl2 Register Field Descriptions Continued Fields Name Bits Description Read Write Reset State ValidModes 6 5 This field specifies the type of tracing that is supported R 10 by the processor Encoding Meaning 00 PC tracing only 01 PC and load and store address tracing only 10 PC load and store address and load and store data 11 Reserved TBI 4 This bit indicates how many trace buffers are imple R Per implementation mented by the
83. from the sum of them because cycles when both stalls are active will only be counted once Specific stalls these events will count the number of cycles lost due to this This will include bubbles introduced by replays within the pipe If multiple stall sources are active simultaneously the counters for each of the active events will be incremented Uncached stall cycles Cycles in which the processor is stalled on an uncached fetch load or store MDU stall cycles Counts all cycles in which the integer pipeline waits on MDU return data Cp2 stall cycles Counts all cycles in which the integer pipeline waits on CP2 return data CorExtend stall cycles Counts all cycles in which the integer pipeline waits on CorExtend return data Load to Use stall cycles Counts all cycles in which the integer pipeline waits on Load return data Other interlocks stall cycles Counts all cycles in which the integer pipeline waits on return data from MFCO and RDHWR instructions Implementation A events Modules that can be by the customer will have an event signal associated with them Set to 1 if COP2 is implemented The performance counter resets to a low power state in which none of the counters will start counting events until software has enabled event counting using an MTCO instruction to the Performance Counter Control Registers Figure 5 36 Performance Counter Count Register 31 0 Counter Table 5 41 Pe
84. includes the following instructions 236 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 9 7 Enhancements to the MIPS Architecture e CLOCount Leading Ones e CLZCount Leading Zeros e MADDMultiply and Add Word e MADDUMultiply and Add Unsigned Word e MSUBMiultiply and Subtract Word e MSUBUMultiply and Subtract Unsigned Word e MULMultiply Word to Register SSNOPSuperscalar Inhibit NOP 9 7 1 CLO Count Leading Ones The CLO instruction counts the number of leading ones in a word The 32 bit word in the GPR rs is scanned from most significant to least significant bit The number of leading ones is counted and the result is written to the GPR rd If all 32 bits are set in the GPR rs the result written to the GPR rd is 32 9 7 2 CLZ Count Leading Zeros The CLZ instruction counts the number of leading zeros in a word The 32 bit word in the GPR rs is scanned from most significant to least significant bit The number of leading zeros is counted and the result is written to the GPR rd If all 32 bits are cleared in the GPR rs the result written to the GPR rd is 32 9 7 3 MADD Multiply and Add Word The MADD instruction multiplies two words and adds the result to the HI LO register pair The 32 bit word value in the GPR rs is multiplied by the 32 bit value in the GPR rt treating both operands as signed values to produce a 64 bit result The p
85. initializing the register file in the boot code may avoid simulation prob lems 6 2 2 Coprocessor 0 State Miscellaneous COPO states need to be initialized prior to leaving the boot code There are various exceptions which are blocked by ERL 1 or EXL 1 and which are not cleared by Reset These can be cleared to avoid taking spurious exceptions when leaving the boot code e Cause WP Watch Pending SW0 1 Software Interrupts should be cleared e Config Typically the KO KU and K23 fields should be set to the desired Cache Coherency Algorithm CCA value prior to accessing the corresponding memory regions But in the M14K core all CCA values are treated identically so the hardware reset value of these fields need not be modified e Count Should be set to a known value if Timer Interrupts are used MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 6 2 Software Initialized Processor State e Compare Should be set to a known value if Timer Interrupts are used The write to compare will also clear any pending Timer Interrupts Thus Count should be set before Compare to avoid any unexpected interrupts e Status Desired state of the device should be set e Other COPO state Other registers should be written before they are read Some registers are not explicitly write able and are only updated as a by product of instruction execution or a taken
86. instruction hazards conditionally restores SRHSCtlcss from SRSCtlpsg and returns at the completion of interrupt processing to the interrupted instruction pointed to by the EPC register If Interrupt Chaining is enabled Interrupts are disabled COPO Status register is restored from the stack The priority output of the External Inter rupt Controller is compared with the IPL field of the Status register If Statusjp has a higher priority than the External Interrupt Controller value COPO SRSCt and EPC registers are restored from the stack GPR 29 is incremented for the stack frame size IRET then clears execution and instruction hazards conditionally restores SHSCtlc ss from SHSCtlpss and returns to the interrupted instruction pointed to by the EPC register at the completion of interrupt processing If Statusjyp has a lower priority than the External Interrupt Controller value The value of GPR 29 is first saved to a temporary register and then GPR 29 is incremented for the stack frame size The EIC is signalled that the next pending interrupt has been accepted This signalling will update the Caus pypy and SRSCtlgjcss fields from the EIC output values The SE SCtlgjcss field is copied to the SRSCtl ss field while the Cause pypy field is copied to the Status py field The saved temporary reg ister is copied to the GPR 29 of the current SRS The KSU and EXL fields of the Status register are option ally set to zero No barrier f
87. instruction is executed If either of the following events occurs between the execution of LL and SC the SC may succeed or it may fail the success or failure is not predictable Portable programs should not cause one of these events e A memory access instruction load store or prefetch is executed on the processor executing the LL SC e The instructions executed starting with the LL and ending with the SC do not lie in a 2048 byte contiguous region of virtual memory The region does not have to be aligned other than the alignment required for instruc tion words The following conditions must be true or the result of the SC is UNPREDICTABLE e Execution of SC must have been preceded by execution of an LL instruction e An RMV sequence executed without intervening events that would cause the SC to fail must use the same address in the LL and SC The address is the same if the virtual address physical address and cache coherence algorithm are identical Restrictions The effective address must be naturally aligned If either of the 2 least significant bits of the address is non zero an Address Error exception occurs MIPS32 M14K Processor Core Software User s Manual Revision 02 03 269 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Operation vAddr sign extend offset GPR base if vAddr o 0 then SignalException AddressError endif pAddr CCA lt AddressTranslation vAddr DATA STOR
88. interrupts Encoding Meaning 0 Interrupt request disabled 1 Interrupt request enabled In implementations of Release 2 of the Architecture in which EIC interrupt mode is enabled these bits are writ able but have no effect on the interrupt system Reserved This field is ignored on writes and reads as 0 This bit denotes the base operating mode of the processor See Section 3 2 Modes of Operation for a full discus sion of operating modes The encoding of this bit is Encoding Meaning 0 Base mode is Kernel Mode 1 Base mode is User Mode Note that the processor can also be in kernel mode if ERL or EXL is set regardless of the state of the UM bit Undefined 0 Undefined This bit is reserved This bit is ignored on writes and reads as Zero MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 103 CPO Registers of the M14K Core Table 5 8 Status Register Field Descriptions Continued Fields Name Bits Description Read Write Reset State ERL EXL IE 2 Error Level Set by the processor when a Reset Soft Reset NMI or Cache Error exception are taken Encoding 0 Normal level Meaning 1 Error level When ERL is set The processor is running in kernel mode Interrupts are disabl
89. interrupts are maskable for non debug mode with the NTE bit which works in addition to the other mechanisms for interrupt masking and enabling NMI is maskable in non debug mode with the NMIE bit and a pending NMI is indicated through the NMIP bit MIPS32 M14K Processor Core Software User s Manual Revision 02 03 159 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core The SRE bit allows implementation dependent masking of none some or all sources for soft reset The soft reset masking may only be applied to a soft reset source if that source can be efficiently masked in the system thus result ing in no reset at all If that is not possible then that soft reset source should not be masked since a partial soft reset may cause the system to fail or hang There is no automatic indication of whether the SRE is effective so the user must consult system documentation The PE bit reflects the ProbEn bit from the EJTAG Control register ECR whereby the probe can indicate to the debug software running on the CPU if the probe expects to service dmseg accesses The reset value in the table below takes effect on both hard and soft resets Figure 8 1 DCR Register Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PCno FDC Data Inst 0 ENM 0 PCIM ASID DASQ DASe DAS 0 Impl Bek Brk 15
90. is shown pictorially in Figure 4 2 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 3 Interrupts Figure 4 2 Interrupt Generation for External Interrupt Controller Interrupt Mode External Interrupt Controller Encode Latch Compare Generate RIPL Any Causey E E Request Interrupt Causepcy e P E Request Causerp E p IPL Statusgg Causeypg nv Interrupt Exception Interrupt Service Started Load IntCtlys Fields p Option 1 4 c Requested a 5 Exception Vector I e Offset M 2 9 x amp m 2 iN p Option 1 Explicit Vector Number iS Ez a wei SOSA 5 p cwcw cw c9 979 7979 79 79 79 79 79 79 79 79 79 079 79 9 79 79 79 79 09 79 79 79 7979 799 79S RSS RE WM Interrupt Sources Option2 Explicit Vector Offset Shadow Set Number Jd n Shadow Set Mapping SRSCtlgrcss A typical software handler for EIC interrupt mode bypasses the entire sequence of code following the IV exception label shown for the compatibility mode handler above Instead the hardware performs the prioritization dispatching directly to the interrupt processing routine Unlike the compatibility mode examples an EIC interrupt handler may take advantage of a dedicated GPR shadow set to avoid saving any registers
91. locking transactions Restrictions The operation of the processor is UNDEFINED if an ASET instruction is executed in the delay slot of a branch or jump instruction Operation vAddr lt sign extend offset GPR base pAddr CCA lt AddressTranslation vAddr DATA STORE pAddr pAddrpgrzn 1 2 pAddr 9 xor ReverseEndian TempIE Statusrp Status p amp 0 memword lt LoadMemory CCA BYTE pAddr vAddr DATA byte vAddr 9 xor BigEndianC PU temp amp memword7 8 byte 8tbyte temp temp or 1 obit dataword temp o 5vte StoreMemory CCA BYTE dataword pAddr vAddr DATA Statusyp lt TempIE Exceptions TLB Refill TLB Invalid TLB Modified Address Error Watch Programming Notes Upon a TLB miss a TLBS exception is signalled in the ExcCode field of the Cause register For address error a ADES exception is signalled in the ExcCode field of the Cause register For other data stream related exceptions such as Debug Data Break exceptions and Watch exceptions it is implementation specific whether this instruction is treated as a load or as a store MIPS32 M14K Processor Core Software User s Manual Revision 02 03 253 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 254 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 31 26 25 24 23 21 20 16 15 12 11 0
92. matching condition is seen this value will be decremented by 1 Once the value reaches 0 subse quent matches will cause a break or trigger as requested and the counter will stay at 0 The break or trigger action is imprecise if the PassCnt register was last written to a non zero value It will remain imprecise until this register is written to 0 by soft ware The instruction pass counter should not be set on instruc tion breakpoints that are being used as part of a tuple breakpoint 8 2 7 Data Breakpoint Registers The registers for data breakpoints are described below These registers have implementation information and are used the setup the data breakpoints All registers are in drseg and the addresses are shown in Table 8 10 Table 8 10 Addresses for Data Breakpoint Registers Register Offset in drseg Mnemonic Register Name and Description 0x2000 DBS Data Breakpoint Status 0x2100 0x100 n DBAn Data Breakpoint Address n 0x2108 0x100 n DBMn Data Breakpoint Address Mask n 0x2110 0x100 n DBASIDn Data Breakpoint ASID n 0x2118 0x100 n DBCn Data Breakpoint Control n 0x2120 0x100 n DBVn Data Breakpoint Value n 0x2128 0x100 n DBCCn Data Breakpoint Complex Control n 0x2130 0x100 n DBPCn Data Breakpoint Pass Counter n Ox2ff0 DVM Data Value Match Register nis breakpoint number as 0 1 2 or 3 or just 0 depending on the implemented hardware An exampl
93. modify an older revision of the pro R Preset cessor this field will be incremented 5 2 18 EBase Register CPO Register 15 Select 1 The EBase register is a read write register containing the base address of the exception vectors used when Statusgry equals 0 and a read only CPU number value that may be used by software to distinguish different processors in a multi processor system The EBase register provides the ability for software to identify the specific processor within a multi processor sys tem and allows the exception vectors for each processor to be different especially in systems composed of heteroge neous processors Bits 31 12 of the EBase register are concatenated with zeros to form the base of the exception vectors when Statusppy is 0 The exception vector base address comes from the fixed defaults see Section 4 5 Exception Vector Locations when S atusggy is 1 or for any EJTAG Debug exception The reset state of bits 31 12 of the EBase register initialize the exception base register to 1648000 0000 providing backward compati bility with Release 1 implementations Bits 31 30 of the EBase Register are fixed with the value 2 10 to force the exception base address to be in the ksegO or kseg unmapped virtual address segments If the value of the exception base register is to be changed this must be done with Statusgry equal 1 The operation of the processor is UNDEFINED if the Exception Base field is written
94. multiply operation Figure 2 5 MDU Pipeline Flow During a 32x32 Multiply Operation Clock 1 2 3 4 5 Ie E DPE Muy Muu Auu Wu gt Gk Rena 2 3 3 Divide High Performance MDU Divide operations are implemented using a simple non restoring division algorithm This algorithm works only for positive operands hence the first cycle of the Mypy stage is used to negate the rs operand RS Adjust if needed Note that this cycle is spent even if the adjustment is not necessary During the next maximum 32 cycles 3 34 an iterative add subtract loop is executed In cycle 3 an early in detection is performed in parallel with the add subtract The adjusted rs operand is detected to be zero extended on the upper most 8 16 or 24 bits If this is the case the following 7 15 or 23 cycles of the add subtract iterations are skipped The remainder adjust Rem Adjust cycle is required if the remainder was negative Note that this cycle is spent even if the remainder was positive A sign adjust is performed on the quotient and or remainder if necessary The sign adjust stage is skipped if both operands are positive In this case the Rem Adjust is moved to the Aypy stage Figure 2 6 Figure 2 7 Figure 2 8 and Figure 2 9 show the latency for 8 16 24 and 32 bit divide operations respec tively The repeat rate is either 11 19 27 or 35 cycles one less if the sign adjust stage is skipped as a second divide can be in the RS Adju
95. oot at Ae eh eda a ee TE 61 Chapter 4 Exceptions and Interrupts in the M14K COre ssaaassssssssnnnnnenrnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn 63 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 3 Copyright 2009 2010 MIPS Technologies Inc All rights reserved die EXceptonm COMMONS at sccetesasaecataatednsecebesnadedenssasiedetanadvedsedeeonehindetusssocsdetidesevedse AOE AE E 63 4 2 EX CO DUOM FIO succi oie does e uocare a a ba tcs rcf e bed oda dae dor tes 64 23 Interr pte root nac T A E Eae Sto Has T i sceau Rasse det eral asset e vea Dae Fu bs sed TAT 65 AS imanupi MONGE ati TEL 65 4 3 2 Generation of Exception Vector Offsets for Vectored Interrupts ccceeeeeeeeeeeseeeeeeeeeseeeeeeeeees 74 4 3 3 MCU ASE Enhancement for Interrupt Handling ssssseseseee eene 75 quU GPR Shadow RESINS reiia ec ba paces teta enu os darse a RES 76 4 5 Exception Vector EoCallOfis s doi aire aeree N Pet eub Pena dec eob ost isuei Cl UR EE Wdadaaenaund 77 4 6 General Exception PROCESSING deae ctt haie SERE xor anduceenzhs esr ep ba xoti xdi dua secca ne ea REED exe adea 79 4 7 Debug Exception PIOCESSING ssoxcuduse n cesgetrecixisderuldatubr a a a ER 81 4 9 EXCe pum DGSCHPHOMS escort abet tecei iet esasi rs e edes ottes I ratu Du RU e eIS cu EMI L LEES S LECHE 82 40 12 Reset softHeset EXOGDIOIT 5 oie toad ebbe o bo E ted pLeta desi een ede 82 4 82 Debug Single Step EXCODIIOR aiaac
96. opcode Regardless of access type or byte ordering endianness the address given specifies the low order byte in the addressed field For a big endian configuration the low order byte is the most significant byte for a little endian configuration the low order byte is the least significant byte 234 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 9 3 Computational Instructions The access type together with the three low order bits of the address define the bytes accessed within the addressed word as shown in Table 9 1 Only the combinations shown in Table 9 1 are permissible other combinations cause address error exceptions Table 9 1 Byte Access Within a Word Bytes Accessed Low Order Big Endian Little Endian Address Bits 31 0 31 0 Access Type Word Triplebyte Halfword 9 3 Computational Instructions Computational instructions can be either in register R type format in which both operands are registers or in imme diate I type format in which one operand is a 16 bit immediate Computational instructions perform the following operations on register values e Arithmetic e Logical e Shift e Multiply e Divide These operations fit in the following four categories of computational instructions e ALU Immediate instructions e Three
97. operand Register type Instructions e Shift Instructions e Multiply And Divide Instructions MIPS32 M14K Processor Core Software User s Manual Revision 02 03 235 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Instruction Set Overview 9 3 1 Cycle Timing for Multiply and Divide Instructions Any multiply instruction in the integer pipeline is transferred to the multiplier as remaining instructions continue through the pipeline the product of the multiply instruction is saved in the HI and LO registers If the multiply instruction is followed by an MFHI or MFLO before the product is available the pipeline interlocks until this product does become available Refer to Chapter 2 Pipeline of the M14K Core on page 31 for more information on instruction latency and repeat rates 9 4 Jump and Branch Instructions Jump and branch instructions change the control flow of a program All jump and branch instructions occur with a delay of one instruction that is the instruction immediately following the jump or branch this is known as the instruction in the delay slot always executes while the target instruction is being fetched from storage 9 4 1 Overview of Jump Instructions Subroutine calls in high level languages are usually implemented with Jump or Jump and Link instructions both of which are J type instructions In J type format the 26 bit target address shifts left 2 bits and combines with the high order 4
98. operation must pass through the mul tiplier array The 16x16 and 32x16 operations pass through the multiplier array once A 32x32 operation passes through the multiplier array twice MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 2 3 MDU Pipeline High Performance MDU The MDU supports execution of a 16x16 or 32x16 multiply operation every clock cycle 32x32 multiply operations can be issued every other clock cycle Appropriate interlocks are implemented to stall the issue of back to back 32x32 multiply operations Multiply operand size is automatically determined by logic built into the MDU Divide operations are implemented with a simple 1 bit per clock iterative algorithm with an early in detection of sign exten sion on the dividend rs Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed Table 2 1 lists the latencies number of cycles until a result is available for multiply and divide instructions The latencies are listed in terms of pipeline clocks In this table latency refers to the number of cycles necessary for the first instruction to produce the result needed by the second instruction Table 2 1 MDU Instruction Latencies High Performance MDU Instruction Sequence Size of Operand Latency 1st Ins
99. or interrupt that occurs with Statusgx 1 or StatuSppy 1 Neither is it updated on an ERET with StatuSgpy 1 or Statusggy 1 This field is not updated on an exception that occurs while Sfatusgg 1 The value of CSS can be changed directly by software only by writing the PSS field and executing an ERET instruction 110 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 9 SRSMap Register CPO Register 12 Select 3 Table 5 11 Sources for new SRSCtlcess on an Exception or Interrupt Exception Al SRSChs Non Vectored SRSCtlgss Treat as exception Interrupt Vectored Interrupt Causejy 1 and SRSMapyecryom Source is internal map register Config3ygyc 0 and for VECTNUM see Table 4 3 Contig3yint 1 Vectored EIC Inter Causey 1 and SRSCtlgicss Source is external interrupt con rupt Config3yg c 1 troller The SRSMap register contains 8 4 bit fields that provide the mapping from a vector number to the shadow set num ber to use when servicing such an interrupt The values from this register are not used for a non interrupt exception or a non vectored interrupt Causery 0 or IntCtlys 0 In such cases the shadow set number comes from SRSCtlgss If SHSCtlgss is zero the results of a software read or write of this register are UNPREDICTABLE The operation of the processor i
100. pending to be serviced The control of the processor can jump directly from the current ISR to the next ISR without IAE and IAP Refer to Chapter 5 CPO Registers of the MIAKTM Core on page 95 for more information on the CPO registers Refer to Chapter 8 EJTAG Debug Support in the M14K Core on page 159 for more information on EJTAG debug registers 1 2 1 5 Memory Management Unit MMU The M14K core contains an MMU that interfaces between the execution unit and the SRAM controller shown in Figure 1 1 The M14K implements an FMT based MMU The FMT performs a simple translation to obtain the physical address from the virtual address Refer to Chapter 3 Memory Management of the M14K Core on page 51 for more infor mation on the FMT Figure 1 1 shows how the address translation mechanism interacts with SRAM access 22 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 1 2 M14K Core Block Diagram Figure 1 1 Address Translation During a SRAM Access Virtual Physical Instruction Addres Address Address o Inst Calculator SRAM FMT Data Dala r SRAM a M Virtual A Address gen 1 2 1 6 SRAM Interface Controller Instead of caches the M14K core contains an interface to SRAM style memories that can be tightly coupled to the core This permits deterministic response time with less area than is ty
101. read as 0 This field contains the instruction cache line size Because R 0 the M14K core does not include caches this field is always read as 0 This field contains the level of instruction cache associativ R 0 ity Because the M14K core does not include caches this field is always read as 0 This field contains the number of data cache sets per way R 0 Because the M14K core does not include caches this field is always read as 0 This field contains the data cache line size Because the R 0 M14K core does not include caches this field is always read as 0 This field contains the type of set associativity for the data R 0 cache Because the M14K core does not include caches this field is always read as 0 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 25 Config1 Register Field Descriptions Select 1 Continued Fields Name Bit s Description Read Write Reset State Coprocessor 2 present R Preset 0 No coprocessor is attached to the COP2 interface 1 A coprocessor is attached to the COP2 interface If the Cop2 interface logic is not implemented this bit will read 0 MDMxX implemented This bit always reads as 0 because R 0 MDMX is not supported Performance Counter registers implemented R Preset Watch registers implemented R 0 0 No Watch re
102. register Again this mode is architecturally optional On the M14K core the VEIC bit is set externally by the static input S _E CPresent to allow system logic to indicate the presence of an external interrupt controller The reset state of the processor is interrupt compatibility mode such that a processor supporting Release 2 of the Architecture the M14K core for example is fully compatible with implementations of Release 1 of the Architecture VI or EIC interrupt modes can be combined with the optional shadow registers to specify which shadow set should be used on entry to a particular vector The shadow registers further improve interrupt latency by avoiding the need to save context when invoking an interrupt handler In the M14K core interrupt latency is greatly improved over the M4K by e Speculative interrupt vector prefetching during the pipeline flush e Interrupt Automated Prologue IAP by hardware Shadow Register Sets remove the need to save GPRs and IAP removes the need to save specific Control Registers when handling an interrupt e Interrupt Automated Epilogue IAE by hardware Shadow Register Sets remove the need to restore GPRs and IAE removes the need to restore specific Control Registers when returning from an interrupt e Allow interrupt chaining When servicing an interrupt and interrupt chaining is enabled there is no need to return from the current Interrupt Service Routine ISR if there is another valid interrupt
103. results of the first Table 2 3 M14K Core Instruction Latencies Area Efficient MDU Operand Signs of Instruction Sequence 1st Instruction Latency Rs Rt 1st Instruction 2nd Instruction Clocks any any MULT MULTU MADD MADDU 32 MSUB MSUBU or MFHI MFLO any any MADD MADDU MADD MADDU 34 MSUB MSUBU MSUB MSUBU or MFHI MFLO any any MUL Integer operation 32 any any DIVU MFHI MFLO 33 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 39 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Pipeline of the M14K Core Table 2 3 M14K Core Instruction Latencies Area Efficient MDU Operand Signs of Instruction Sequence 1st Instruction Latency Rs Rt 1st Instruction 2nd Instruction Clocks pos pos MFHI MFLO 33 any neg MFHI MFLO 34 neg pos MFHI MFLO 35 any any MFHI MFLO Integer operation 2 any any MTHI MTLO MADD MADDU 1 MSUB MSUBU 1 Integer Operation refers to any integer instruction that uses the result of a previous MDU operation 2 4 1 Multiply Area Efficient MDU Multiply operations are executed using a simple iterative multiply algorithm Using Booth s approach this algorithm works for both positive and negative operands The operation uses 32 cycles in Mypy stage to complete a multiplica tion The register writeback to HI and LO are done in the A stage For MUL operations the register file writeback is don
104. rights reserved 8 8 iFlowtrace Mechanism Suggested implementation of the EJ_DisableProbeDebug signal is for a microcontroller to provide a bit within non volatile memory outside the core that is pre programmed to set or clear this control signal Table 8 34 EJ DisableProbeDebug Signal Overview Description Direction Compliance EJ DisableProbeDebug When asserted Input Required for e ProbEn 0 SecureDebug e ProbTrap 0 BjtagBrk is disabled EJTAGBOOT is disabled PC Sampling is disabled DINT signal is ignored An override is provided 8 7 1 2 Override for EjtagBrk and DINT disable An override for the EjtagBrk and DINT disable caused by the EJ DisableProbeDebug signal is provided by the Mem ory Protection Unit MPU Config register field EjtagBrk Override This override feature is only available if the Mem ory Protection Unit is implemented Refer to the MPU chapter of Security Features of the MIAKTM Processor Family MD00896 for further informa tion on the Memory Protection Unit The override can be asserted by the CPU during the trusted boot process Its purpose is to allow a probe to assert EjtagBrk or the assertion of the DINT signal which requests a Debug Interrupt exception thus providing a means of recovering the CPU from a crash or hang This feature allows a Debug Executive if one is provided in target firm ware to communicate with the probe over the Fast Debug Channel
105. s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 CPO Register Descriptions The CPO registers provide the interface between the ISA and the architecture Each register is described below with the registers presented in numerical order first by register number then by select field number For each register described below field descriptions include the read write properties of the field and the reset state of the field The read write access properties of the field are described in Table 5 2 Table 5 2 CPO Register Field Types Read Write Notation Hardware Interpretation Software Interpretation R W A field in which all bits are readable and writable by software and potentially by hardware Hardware updates of this field are visible by software reads Software updates of this field are vis ible by hardware reads If the reset state of this field is Undefined either software or hardware must initialize the value before the first read will return a predictable value This should not be confused with the formal definition of UNDEFINED behavior R A field that is either static or is updated only by A field to which the value written by software is hardware ignored by hardware Software may write any If the Reset State of this field is either O or value to this field without affecting hardware Preset hardware initializes this field
106. sent to the SRAM interface for an external memory reference In the M14K processor core the MMU is based on a simple algorithm to translate virtual addresses into physical addresses via a Fixed Mapping FM mechanism These translations are different for various regions of the virtual address space useg kuseg kseg0 kseg1 kseg2 3 Figure 3 1 shows how the memory management unit interacts with the SRAM access in the M14K core Figure 3 1 Address Translation During SRAM Access Virtual Instruction Address Address Calculator Physical Address a Instn SRAM SRAM FMT Interface Data SRAM Data Address Calculator Physical Address s Virtual Address 3 2 Modes of Operation An MI4K processor core supports three modes of operation MIPS32 M14K Processor Core Software User s Manual Revision 02 03 51 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Memory Management of the M14K Core 52 e User mode e Kernel mode e Debug mode User mode is most often used for application programs Kernel mode is typically used for handling exceptions and privileged operating system functions including CPO management and I O device accesses Debug mode is used for software debugging and most likely occurs within a software development tool The address translation performed by the MMU depends on the mode in which the processor is operating 3 2
107. that are dedicated to that condition Privileged software may need to reference all GPRs in the register file even specific shadow registers that are not visible in the current mode The RDPGPR and WRPGPR instructions are used for this purpose The CSS field of the SRSCt register provides the number of the current shadow register set and the PSS field of the SRSCt register provides the number of the previ ous shadow register set that which was current before the last exception or interrupt occurred If the processor is operating in VI interrupt mode binding of a vectored interrupt to a shadow set is done by writing to the SRSMap register If the processor is operating in EIC interrupt mode the binding of the interrupt to a specific shadow set is provided by the external interrupt controller and is configured in an implementation dependent way Binding of an exception or non vectored interrupt to a shadow set is done by writing to the ESS field of the SRSCItI register When an exception or interrupt occurs the value of SRSCtlcss is copied to SESCtlpss and SHSCtless is set to the value taken from the appropriate source On an ERET the value of SESCtlpss is copied back into SHSCtless to restore the shadow set of the mode to which control returns More precisely the rules for updating the fields in the SHSCII register on an interrupt or exception are as follows 1 No field in the SRSCtl register is updated if any of the following conditions is tru
108. the DEPC contains the virtual address of the instruction where execution should resume after the debug handler code is executed In processors that implement microMIPS a read of the DEPC register via MFCO returns the following value in the destination GPR GPR rt lt DebugExceptionPC3 ISAModeg That is the upper 31 bits of the debug exception PC are combined with the lower bit of the SAMode field and written to the GPR Similarly a write to the DEPC register via MTCO takes the value from the GPR and distributes that value to the debug exception PC and the SAMode field as follows DebugExceptionPC GPR rt 4 0 ISAMode lt 2 0 GPRIrt g That is the upper 31 bits of the GPR are written to the upper 31 bits of the debug exception PC and the lower bit of the debug exception PC is cleared The upper bit of the SAMode field is cleared and the lower bit is loaded from the lower bit of the GPR Figure 5 34 DEPC Register Format 31 0 DEPC Table 5 37 DEPC Register Formats Fields Name Bit s Description Read Write Reset DEPC 31 0 The DEPC register is updated with the virtual address of Undefined the instruction that caused the debug exception If the instruction is in the branch delay slot then the virtual address of the immediately preceding branch or jump instruction is placed in this register Execution of the DERET instruction causes a jump to the address in the DEPC
109. the MIPS32 Architecture Reference Manual for more information about the instruction descriptions That document contains a description of the instruction fields definition of terms and functional nota tion 10 2 M14K Opcode Map Key e CAPITALIZED text indicates an opcode mnemonic e Italicized text indicates to look at the specified opcode submap for further instruction bit decode e Entries containing the amp symbol indicate that a reserved instruction fault occurs if the core executes this instruc tion Entries containing the D symbol indicate that a coprocessor unusable exception occurs if the core executes this instruction MIPS32 M14K Processor Core Software User s Manual Revision 02 03 239 Copyright 2009 2010 MIPS Technologies Inc All rights reserved M14K Processor Core Instructions Table 10 1 Encoding of the Opcode Field opcode bits 28 26 110 Special BLEZ ADDI XORI P p BEQL BNEL BLEZL a o o o Sw aan o LBU LWR SWR a a Table 10 2 Special Opcode encoding of Function Field function bits 2 0 bits 5 3 0 000 1 001 2 010 3 5011 4 100 5 6 7 101 110 111 Table 10 3 Special2 Opcode Encoding of Function Field function bits 2 0 000 1 CorExtend instructions are a build time option of the M14K Pro core if not implemented this inst
110. the entire array in order If it is cleared then the read pointer can be set to 0 to read up to the write pointer position The format of the TCBWHP register is shown below and the field is described in Table 8 40 The value of n depends on the size of the on chip trace memory As the address points to a 64 bit TW lower three bits are always zero Figure 8 34 ITCBWRP Register Format Copyright 2009 2010 MIPS Technologies Inc All rights reserved 31 30 n l n 0 Wrap 0 Address Table 8 40 ITCBWRP Register Field Descriptions Fields Description Read Reset Compliance Write State Names Wrap 31 m that the entire array has been written at least R W Undefined Required 0 30 n 1 Reserved Must be written zero reads back zero 0 0 Required Address xil s address of the next on chip trace memory word to R W Undefined Required e written MIPS32 M14K Processor Core Software User s Manual Revision 02 03 221 EJTAG Debug Support in the M14K Core 8 8 7 ITCB iFlowtrace Off Chip Interface The off chip interface consists of a 4 bit data port TR DATA and a trace clock TR CLK TR_CLK can be a DDR clock that is both edges are significant TR DATA and TR CLK follow the same timing and have the same output structure as the PDtrace TCB described in MIPS specifications The trace clock is synchronous to the system clock but running at a divided frequency The OfCIk bit in the Control Status register in
111. this format on the bus between the core tracing logic and the ITCB is 3 0 4 b0011 11 4 PCdelta 8 1 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 8 iFlowtrace Mechanism e 1101 followed by 16 bits of 1 bit shifted offset from the last PC The bit assignments of this format on the bus between the core tracing logic and the ITCB is 3 0 4 b1011 19 4 PCdelta 16 1 e 11 10 followed by 31 of the most significant bits of the PC value followed by a bit NCC that indicates no code compression Note that for a MIPS32 or MIPS64 instruction NCC 1 and for microMIPS instruction NCC 0 This trace record will appear at all transition points between MIPS32 MIPS64 and microMIPS instruction execution This form is also a special case of the 11 format and it is used when the instruction is not a branch or jump but nevertheless the full PC value needs to be reconstructed This is used for synchronization purposes sim ilar to the Sync in PDtrace In iFlowtrace rev 2 0 onwards the sync period is user defined and is counted down and when an internal counter runs through all the values this format is used The bit assignments of this format on the bus between the core tracing logic and the ITCB is 3 0 4 b0111 34 4 PC 31 1 35 2 NCC e 1111 Used to indicate trace resumption after a discontinuity occurred The next format is
112. timer interrupt is pending 1 Timer interrupt is pending The state of the TI bit is available on the external core interface as the S Timerlnt signal CE 29 28 Coprocessor unit number referenced when a Coproces R Undefined sor Unusable exception is taken This field is loaded by hardware on every exception but is UNPREDICT ABLE for all exceptions except for Coprocessor Unus able DC 27 Disable Count register In some power sensitive appli R W 0 cations the Count register is not used and is the source of meaningful power dissipation This bit allows the Count register to be stopped in such situations Encoding Meaning 0 Enable counting of Count register 1 Disable counting of Count register PCI 26 Performance Counter Interrupt In an implementation of R 0 Release 2 of the Architecture this bit denotes whether a performance counter interrupt is pending analogous to the IP bits for other interrupt types Encoding Meaning 0 No timer interrupt is pending 1 Timer interrupt is pending The state of the PCI bit is available on the external MIAK interface as the S _PCint signal IC 25 Indicates if Interrupt Chaining occurred on the last IRET R Undefined instruction Encoding Meaning 0 Interrupt Chaining did not happen on last IRET 1 Interrupt Chaining occurred during last IRET 114 MIPS32 M14K Pro
113. two tables into one that contains all possible vector addresses as a function of the state that can affect the MIPS32 M14K Processor Core Software User s Manual Revision 02 03 77 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M14KT Core vector selection To avoid complexity in the table the vector address value assumes that the EBase register as imple mented in Release 2 devices is not changed from its reset state and that IntCtjyg is 0 Table 4 5 Exception Vector Base Addresses Statuspey Exception 0 1 Reset Soft Reset NMI 16 BFCO 0000 EJTAG Debug with ProbEn 0 in 16 BFCO 0480 the EJTAG Control Register EJTAG Debug with ProbEn 1 in 16 FF20 0200 the EJTAG Control Register SRAM Parity Error EBase3 30 16 BFCO 0300 EBaseyg 15 16 000 Note that EBase3 39 have the fixed value 2 10 Other For Release 1 of the architecture 16 BFCO 0200 16 8000 0000 For Release 2 of the architecture EBase3 12 ll 164000 Note that EBase3 _ 39 have the fixed value 2410 Table 4 6 Exception Vector Offsets Exception Vector Offset General Exception 164180 Interrupt Cause yy 1 16 200 In Release 2 implementa tions this is the base of the vectored interrupt table when StatuSpry 0 Reset Soft Reset NMI None Uses Reset Base Address Table 4 7 Exception Vectors Vector For Release 2 Implementations assumes EJ
114. valid entries However the interrupt will not be asserted when there is only one valid entry if it is an S Clkln entry e The RxFIFO has similar characteristics but these are even less visible to software since S ClkIn must be run ning to access the FDC registers 8 10 4 Sleep mode FDC data transfers do not prevent the core from entering sleep mode and will proceed normally in sleep mode The FDC block monitors the TAP interface signals with a free running clock When new receive data is available or trans mit data can be sent the gated clock will be enabled for a few cycles to transfer the data and then allowed to stop again If FDC interrupts are enabled transferring data may cause an interrupt to be generated which can wake the core up 8 10 5 FDC TAP Register The FDC TAP instruction performs a 38 bit bidirectional transfer of the FDC TAP register The register format is shown in Figure 8 37 and the fields are described in Figure 8 42 Figure 8 37 FDC TAP Register Format 37 36 35 32 31 0 In Out ProbeData Data In Accept Valid ChannelID Data Receive Data Out Buffer Full Valid Table 8 42 FDC TAP Register Field Descriptions Fields Read Name Bits Description Write Probe Data 37 Indicates to core that the probe is accepting the data that WwW Undefined Accept was scanned out Data In 36 Indicates to core that the probe is sending new data to the W Undefined Valid receiv
115. with a different value when Statusppy is 0 Combining bits 31 20 with the Exception Base field allows the base address of the exception vectors to be placed at any 4KByte page boundary If vectored interrupts are used a vector offset greater than 4KBytes can be generated In this case bit 12 of the Exception Base field must be zero The operation of the processor is UNDEFINED if software writes bit 12 of the Exception Base field with a 1 and enables the use of a vectored interrupt whose offset is greater than 4KBytes from the exception base address 122 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Figure 5 18 shows the format of the EBase Register Table 5 22 describes the EBase register fields Figure 5 18 EBase Register Format 31 30 29 12 11 10 9 0 1 0 Exception Base 00 CPUNum Table 5 22 EBase Register Field Descriptions Fields Name Bits Description Read Write Reset State 1 31 This bit is ignored on writes and returns one on reads R 1 0 30 This bit is ignored on writes and returns zero on reads R 0 Exception 29 12 In conjunction with bits 31 30 this field specifies the base R W 0 Base address of the exception vectors when StatuSpry is zero 0 11 10 Must be written as zero returns zero on reads 0 0 CPUNum 9 0 This field specifies the number of the CPU in a multi pro R Ex
116. written with zero returns zero on read ULR Mask 29 3 0 User Local Register This register provides read access to the coprocessor 0 UserLocal register In some operating environments the UserLocal regis ter is a pointer to a thread specific storage block instruction to a particular hardware register which may not be an actual register If bit n in this field is a 1 access is enabled to hardware register n If bit n of this field is a 0 access is disabled See the RDHWR instruction for a list of valid hard ware registers Each bit in this field enables access by the RDHWR Privileged software may determine which of the hardware registers are accessible by the RDHWR instruction In doing so a register may be virtualized at the cost of handling a Reserved Instruction Exception interpreting the 98 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions instruction and returning the virtualized value For example if it is not desirable to provide direct access to the Count register access to that register may be individually disabled and the return value can be virtualized by the operating system 5 2 3 BadVAddr Register CPO Register 8 Select 0 The BadVAdar register is a read only register that captures the most recent virtual address that caused the following e
117. 0 CU2 30 Controls access to coprocessor 2 This bit can only be writ ten if coprocessor is attached to the COP2 interface C2 bit in Configl is set This bit will read as 0 if no coproces Sor is present R W CUI CUO 29 28 27 Controls access to Coprocessor 1 COPI is not supported This bit cannot be written and will read as 0 Controls access to coprocessor 0 Encoding Meaning 0 Access not allowed 1 Access allowed Coprocessor 0 is always usable when the processor is run ning in kernel mode independent of the state of the CUO bit Enables reduced power mode The state of the AP bit is available on the external core interface as the S _RAP sig nal Undefined 0 for Cold Reset only FR 26 25 This bit is related to floating point registers Because the M14K core does not contain a floating point unit this bit is ignored on writes and reads as zero Used to enable reverse endian memory references while the processor is running in user mode Encoding Meaning 0 User mode uses configured endianness 1 User mode uses reversed endianness Neither Debug Mode nor Kernel Mode nor Supervisor Mode references are affected by the state of this bit MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Undefined 101 CPO Regi
118. 0 MIPS Technologies Inc All rights reserved 4 9 Exception Handling and Servicing Flowcharts Additional State Saved None Entry Vector Used Debug exception vector 4 8 22 Complex Break Exception A complex data break exception occurs when the complex hardware breakpoint detects an enabled breakpoint Com plex breaks are taken imprecisely the instruction that actually caused the exception is allowed to complete and the DEPC register and DBD bit in the Debug register point to a following instruction Debug Register Debug Status Bit Set DIBImpr DDBLImpr and or DDBSImpr Additional State Saved Debug fields indicate which type s of complex breakpoints were detected Entry Vector Used Debug exception vector 4 9 Exception Handling and Servicing Flowcharts The remainder of this chapter contains flowcharts for the following exceptions and guidelines for their handlers e General exceptions and their exception handler e Reset soft reset and NMI exceptions and a guideline to their handler e Debug exceptions MIPS32 M14K Processor Core Software User s Manual Revision 02 03 91 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M14KT Core Figure 4 3 General Exception Handler HW Exceptions other than Reset Soft Reset NMI EJ Tag Debug and cache error or first level TLB miss Note Interrupts can be masked by IE or IMs and Watch is masked if EXL 21 Comments
119. 09 2010 MIPS Technologies Inc All rights reserved Appendix A References This appendix lists other publications available from MIPS Technologies Inc that are referenced in this document These documents may be included in the SMIPS_PROJECT doc area of a typical M14K soft or hard core release or in some cases may be available on the MIPS web site http www mips com 1 MIPS32 M14K Processor Core Data Sheet MIPS document MD00666 2 MIPS32 M14K Processor Core Integrators Guide MIPS document MD00667 3 MIPS32 M14K CPU Implementor s Guide MIPS Document MD00669 4 MIPS32 M14K System Package amp Simulation Flow User s Manual MIPS document MD00717 5 MIPS Architecture For Programmers Volume I Introduction to the MIPS32 Architecture MIPS document MD0082 6 MIPS Architecture For Programmers Volume I Introduction to the microMIPS32 Architecture MIPS document MD0741 7 MIPS Architecture For Programmers Volume II The MIPS32 Instruction Set MIPS document MD0086 8 MIPSO Architecture For Programmers Volume II The microMIPS32 Instruction Set MIPS document MD0582 9 MIPS Architecture For Programmers Volume III The MIPS32 and microMIPS32 Privileged Resource Architecture MIPS Document MD00090 10 MIPSO Architecture for Programmers Volume IV h The MCU Application Specific Extension to the MIPS32 and microMIPS32 Architectures MIPS document MD00641 11 MIPS EJTAG Specification
120. 1 Virtual Memory Segments The Virtual memory segments are different depending on the mode of operation Figure 3 2 shows the segmentation for the 4 GByte 23 bytes virtual memory space addressed by a 32 bit virtual address for the three modes of opera tion The core enters Kernel mode both at reset and when an exception is recognized While in Kernel mode software has access to the entire address space as well as all CPO registers User mode accesses are limited to a subset of the vir tual address space 0x0000_0000 to 0x7FFF_FFFF and can be inhibited from accessing CPO functions In User mode virtual addresses 0x8000_0000 to OXFFFF_FFFF are invalid and cause an exception if accessed Debug mode is entered on a debug exception While in Debug mode the debug software has access to the same address space and CPO registers as for Kernel mode In addition while in Debug mode the core has access to the debug segment dseg This area overlays part of the kernel segment kseg3 dseg access in Debug mode can be turned on or off allowing full access to the entire kseg3 in Debug mode if so desired MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 3 2 Modes of Operation Figure 3 2 M14K processor core Virtual Memory Map Virtual Address User Mode Kernel Mode Debug Mode OXPFFFLPRRR TTT CCTs ees OxFF3F_FFFF it kseg3 OxFF20_0000 ae nd O
121. 10 9 7 6 4 3 1 0 Major Opcode rs2 d rs1 Imm M 15 10 9 7 6 4 3 0 Major Opcode rs2 d rs1 Minor Opc Imm 15 10 9 7 6 4 3 1 0 Major Opcode rd rs2 rs1 M 15 10 9 5 4 0 Major Opcode Minor opc rs1 d 15 10 9 5 4 0 Major Opcode rd Minor Opc Imm 15 10 9 5 4 0 Major Opcode rd rs1 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 279 microMIPS Instruction Set Architecture RO R1 R2 R3 R4 R0126 R0116 R1116 R2116 R1112 R2112 280 Figure 11 2 32 Bit Instruction Formats 31 26 25 0 Major Opcode Immediate Minor Opcode Other 31 26 25 21 20 16 15 0 Major Opcode Imm Other rs fs base Immediate Minor Opcode Other 31 26 25 21 20 16 15 0 Major Opcode rt ft index rs fs base Immediate Minor Opcode Other 31 26 25 21 20 16 15 11 10 0 Major Opcode rt ft index rs fs base rd fd Immediate Minor Opcode Other 31 26 25 21 20 16 15 11 10 0 Major Opcode rt ft rs fs rd fd rr fr Minor Opcode Other Figure 11 3 Immediate Fields within 32 Bit Instructions 32 bit instruction formats with 26 bit immediate fields Copyright 2009 2010 MIPS Technologies Inc All rights reserved 31 26 25 0 Major Opcode Immediate 31 26 25 16 15 0 Major Opcode Minor Opcode Other Immediate 32 bit instruction formats with 16 bit immedia
122. 14K Core on page 63 After updating a CPO register there is a hazard period of zero or more instructions from the update instruction MTCO and until the effect of the update has taken place in the core Refer to Chapter 10 M14K Processor Core Instructions on page 239 for further details on CPO hazards The current chapter contains the following sections e Section 5 1 CPO Register Summary e Section 5 2 CPO Register Descriptions 5 1 CPO Register Summary Table 5 1 lists the CPO registers in numerical order The individual registers are described throughout this chapter Where more than one registers shares the same register number at different values of the sel field of the instruction their names are listed using a slash as separator Table 5 1 CPO Registers Register Number Register Name Function 0 3 Reserved Reserved in the M14K core UserLocal User information that can be written by privileged software and read via RDHWR register 29 Reserved Reserved in the M14K core HWREna Enables access via the RDHWR instruction to selected hardware registers in non privileged mode BadVAdar Reports the address for the most recent address related exception Count Processor cycle count 11 Compare Timer interrupt control MIPS32 M14K Processor Core Software User s Manual Revision 02 03 95 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K
123. 16 200 512 All other values are reserved The operation of the pro cessor is UNDEFINED if a reserved value is written to this field Must be written as zero returns zero on read 0 5 2 8 SRSCtl Register CPO Register 12 Select 2 The SRSCt register controls the operation of GPR shadow sets in the processor This register does not exist in imple mentations of the architecture prior to Release 2 108 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Figure 5 8 shows the format of the SRSCtl register Table 5 10 describes the SRSCt register fields Figure 5 8 SRSCtl Register Format 31 30 29 26 25 22 21 18 17 16 15 12 11 10 9 6 5 4 3 0 0 0 0 0 0 a HSS 508 EICSS d0 ESS 06 PSS on CSS Table 5 10 SRSCtl Register Field Descriptions Fields Reset Name Bits Description Read Write State E 31 30 Must be written as zeros returns zero on read NENE NE UM Highest Shadow Set This field contains the highest shadow set number that is implemented by this proces sor A value of zero in this field indicates that only the normal GPRs are implemented Possible values of this field for the M14K processor are Encoding Meaning 0 One shadow set normal GPR set is present Two shadow sets are present Four shadow sets are present Eight shadow sets are p
124. 172 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints Table 8 7 IBCn Register Field Descriptions Fields Name Bits Description Read Write Reset State ASIDuse 23 Use ASID value in compare for instruction breakpoint n Encoding Meaning 0 Don t use ASID value in compare 1 Use ASID value in compare Must be written as zero returns zero on read R hwarts A preset value of 1 indicates that the address range trig gered instruction breakpoint feature is supported for this particular instruction breakpoint channel excl A value of 0 indicates that the breakpoint will match for addresses within inclusive of the range defined by IBMn and IBAn A value of 1 indicates that the break point will match for addresses outside exclusive to the range defined by IBMn and IBAn A value of 0 indicates that the breakpoint will match using the Equality and Mask equation as found section under 8 2 3 1 Conditions for Matching Instruction Breakpoints A value of 1 indicates that the breakpoint will match using the Address Range equation in section 8 2 3 1 Conditions for Matching Instruction Breakpoints Must be written as zero returns zero on read Use instruction breakpoint n as triggerpoint Encoding Meaning 0 Don t use it as triggerpoint 1 Use it as triggerpoi
125. 2 4 3 Divide Area Efficient MDU Divide operations also implement a simple non restoring algorithm This algorithm works only for positive operands hence the first cycle of the Mypy stage is used to negate the rs operand RS Adjust if needed Note that this cycle is executed even if negation is not needed The next 32 cycle 3 34 executes an interactive add subtract shift function Two sign adjust Sign Adjust 1 2 cycles are used to change the sign of one or both the quotient and the remainder Note that one or both of these cycles are skipped if they are not needed The rule is if both operands were positive or if this is an unsigned division both of the sign adjust cycles are skipped If the rs operand was negative one of the sign adjust cycles is skipped If only the rs operand was negative none of the sign adjust cycles are skipped Register writeback to HI and LO are done in the A stage Figure 2 12 shows the pipeline flow for a divide operation The repeat rate is either 34 35 or 36 cycles depending on how many sign adjust cycles are skipped as a second divide can be in the E stage when the first divide is in the last Mypyu Stage Figure 2 12 M14K Area Efficient MDU Pipeline Flow During a Divide DIV Operation Clock 1 2 3 34 35 36 37 38 E Stage P Mypy Stage P My py Stage P My py Stage P Mypy Stage 4 Aupy Stage P Wypy Stage gt RS Adjust Add Subtract Shift Sign Adjust 1 Sign Adjust 2 HI LO Write 2
126. 3 Copyright 2009 2010 MIPS Technologies Inc All rights reserved
127. 4K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 9 PC Data Address Sampling e Bits 14 0 IBrk DBrk Used to explicitly specify which instruction data or tuple breaks enable or disable iFlowTrace A value of 0 implies that trace is turned off unconditional trace stop and a value of 1 specifies that the trigger enables trace unconditional trace start 8 9 PC Data Address Sampling It is often useful for program profiling and analysis to periodically sample the value of the PC This information can be used for statistical profiling akin to gprof and is also very useful for detecting hot spots in the code In a multi threaded environment this information can be used to understand thread behavior and to verify thread schedul ing mechanisms in the absence of a full fledged tracing facility like PDtrace The PC sampling feature is optional within EJTAG but EJTAG and the TAP controller must be implemented if PC Sampling is required When implemented PC sampling can be turned on or off using an enable bit when the feature is enabled the PC value is continually sampled The presence or absence of the PC Sampling feature is indicated by the PCS PC Sample bit in the Debug Control Register If PC sampling is implemented and the PCSe PC Sample Enable bit in the Debug Control Register is also set to one then the PC values are constantly sampled at the defined rate
128. 5 8 DBVnpgy 15 8j BYTELANE 1 DBCngzyyj1 DBCngaiji amp amp DATA 23 16 DBVnpgy 23 16 BYTELANE 2 DBCngry o DBCngai gj amp amp DATA 31 24 DBVnpgy 31 24j BYTELANE 3 DBCngry 3 DBCngarj3 The match for a data breakpoint is always precise since the match expression is fully evaluated at the time the load store instruction is executed A true DB match can thereby be indicated on the very same instruction causing the DB match to be true Address Range Cores may optionally support the address range triggered data breakpoints When this feature is configured the fol lowing changes are made to the data breakpoint registers e DBAn represents the upper limit of a address range boundary e DBMn represents the lower limit of the address range boundary In addition the following bits must be supported DBOCn 10 hwarts a preset value of 1 indicates that the address range triggered data breakpoint feature is supported for this particular data breakpoint channel This bit is read only DBCn 9 exc a value of 0 indicates that the breakpoint will match for addresses inclusive within the range defined by DBMn and DBAn A value of 1 indicates that the breakpoint will match for addresses exclusive outside to the range defined by DBMn and DBAn This bit is writeable MIPS32 M14K Processor Core Software User s Manual Revision 02 03 167 Copyright 2009 2010 MIPS Tech
129. 50 5 2 36 CacheErr Register CPO Register 27 Select 0 sssssssssseseeeeeeeennnne 150 5 2 97 ETtorEPO GPO Register 30 Select 0 ota iienaa ed gt niae to ect tetuduiui R 151 5 2 38 DeSave Register CPO Register 31 Select 0 eessssssssssssseseeeeeeene enne 152 Chapter 6 Hardware and Software Initialization of the M14K Core 153 6 1 Hardware Initialized Processor State criar ei vascr inge acerbe ibo c Unit md eee 153 pl Coprocessor OS ale nea Ad eee tans E atin eee retin eee teed P haec ma Dodo rte iit cre e 153 5 1 2 Bus State Machine Sininen A E 154 6 1 3 Stati Configuration INPUTS isiin eani adaa a aaa 154 Gl FetehuAOddIess taninan R He BOI E Redo 154 6 27 SoftWare Initalized Processor SIale acucdeo tee iena b erecto a a t uu doe 154 p 2 1 Register Pile seras N NAE A EE a bevieetsaiuieide 154 6 2 2 GOprOGeSSOT O Stale iiec aia a a Aaaa aa 154 Chapter 7 Power Management of the M14K Core ccssecccseeeeeeeeeseeeeeeesenneeeeeeeeeeeeeneeeneeeeneeeeeeeess 157 7 14 Register Controlled Power Mahagetrierib s iie iecoris e hee ERG bec eoo dee bed exti ARTN E es Ur exta teda 157 7 2 Instruction Controlled Power Management ssssssssssssssseeee eene tne 158 Chapter 8 EJTAG Debug Support in the M14K Core eee 159 9d Debug Gontol REISTE oet ertet a a oe Dou oce Hia A E Sn E 159 9 2 HardwafteBIeakpOIs aicci a
130. 8 28 The endian mode for debug kernel mode is determined by the state of the S Endian input at power up 206 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 5 EJTAG TAP Registers Figure 8 28 Endian Formats for the PAD Register bit 31 dis 24 23 16 15 87 ib 0 BERN A n 0 4 5 6 7 Aln 2 1 Aino 0_ 2 3 anzi Most significant byte is at lowest address Word is addressed by byte address of most significant byte MSB LSB bit 31 24 23 16 15 87 0 Vien A n 0 27 6 5 4 Aln 2 1 Aln 0 3 2 1 0 Aln 2 0 Least significant byte is at lowest address Word is addressed by byte address of least significant byte The size of the transaction and thus the number of bytes available required for the PAD register is determined by the Psz field in the ECR 8 5 4 Fastdata Register TAP Instruction FASTDATA The width of the Fastdata Register is 1 bit During a Fastdata access the Fastdata register is written and read i e a bit is shifted in and a bit is shifted out During a Fastdata access the Fastdata register value shifted in specifies whether the Fastdata access should be completed or not The value shifted out is a flag that indicates whether the Fastdata access was successful or not if completion was requested Figure 8 29 Fastdata Register Format 0 Table 8 32 Fastdata Register Field Descriptio
131. Breakpoint Trap to SW Debug Handler SEB Sign Extend Byte Rd SignExtend Rt7_ o SEH Sign Extend Half RdzSignExtend Rt 9 SH Store Halfword half Mem Rs offset Rt SLL Shift Left Logical Rd Rt lt lt sa SLLV Shift Left Logical Variable Rd Rt lt lt Rs 4 0 SLT Set on Less Than if int Rs lt int Rt Rd 1 else Rd 0 SLTI Set on Less Than Immediate if int Rs lt int Immed Rt 1 else Rt 0 SLTIU Set on Less Than Immediate Unsigned if uns Rs uns Immed Rt 1 else Rt 0 246 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 10 3 MIPS32 Instruction Set for the M14K core Table 10 10 Instruction Set Continued MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Instruction Description Function SLTU Set on Less Than Unsigned if uns Rs lt uns Immed Rd 1 else Rd 0 SRA Shift Right Arithmetic Rd int Rt gt gt sa SRAV Shift Right Arithmetic Variable Rd int Rt gt gt Rs 4 0 SRL Shift Right Logical Rd uns Rt gt gt sa SRLV Shift Right Logical Variable Rd uns Rt gt gt Rs 4 0 SSNOP Superscalar Inhibit No Operation Nop SUB Integer Subtract Rt int Rs int Rd SUBU Unsigned Subtract Rt uns Rs uns Rd SW Store Word Mem Rs offset Rt SWC2 Store Word From Coprocessor 2 Mem Rs offset CPR 2 n 0 SWL Store Word Left See SWL instruction description
132. Bs of the PC value 00 Special Mode Delta Cycle Rollover message lt 10 gt lt 32 gt 010 Special Mode User add in Trace Message 32 bit user data as well as 10 bit delta cycle if enabled lt 10 gt lt NCC gt lt 31 gt lt 1 gt lt 4 gt 01 Special Mode Breakpoint Match Message 4 bit breakpoint ID 1 bit indicate breakpoint type 31 MSBs of the PC value NCC bit included as well as 10 bit delta cycle if enable lt 10 gt lt 32 gt lt 6 gt lt 1 gt lt 1 gt lt 4 gt 011 Special Mode Filtered Data Message 4 bit breakpoint ID 1 bit load or store indi cation bit full word indication 6 bit of addr 7 2 32 bit of the data information included as well as 10 bit delta cycle if enabled lt 10 gt lt NCC gt lt 31 gt lt R gt lt Ex gt lt FC gt 011 Special Mode Function Call Return Exception Tracing 1 bit function call indica tion 1 bit exception indication 1 bit function or exception return indication 31 MSBs of the PC value NCC bit included as well as 10 bit delta cycle if enabled 1 1111 Internal overflow 8 8 5 TCB Storage Representation Records from iFlowtrace are inserted into a memory stream exactly as they appear in the iFlowtrace data output Records are concatenated into a continuous stream starting at the LSB When a trace word is filled it is written to memory along with some tag bits Each record consists of a 64 bit word which comprises 58 message bits and 6 tag bits or header bits that clarify info
133. C 8 3 6 Usage of Data Qualified Breakpoints Each of the instruction breakpoints can be set to be data qualified In qualified mode a breakpoint will recognize its conditions only after the specified data breakpoint matches both address and data If the data breakpoint matches address but has a mismatch on the data value the instruction breakpoint will be unqualified and will not match until a subsequent qualifying match This feature can be used similarly to the ASID qualification that is available on cores with TLBs If an RTOS loads a process ID for the current process that load can be used as the qualifying breakpoint When a matching process ID is loaded entering the desired RTOS process qualified instruction breakpoints will be enabled When a different pro cess ID is loaded leaving the desired RTOS process the qualified instruction breakpoints are disabled Alterna tively with the Invert ValueMatch feature of the data breakpoint the instruction breakpoints could be enabled on any process ID other than the specified one e The qualifying data break must have DBCnre or DBCCnggg set e The qualifying data break should have data comparison enabled via settings of DBCng m and DBCngaj e The qualifying data break should not have pass counters priming conditions or tuples enabled e The qualifying data access can be either a load or store depending on the settings of DBCny5sg and DBCnyo p e The Qualified Unqualified state is
134. C Option 1 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 263 VectorNum CauSemgrpr elseif Config3ygrc 1 and EIC_Option 2 VectorNum EIC VectorNum elseif Config3yprc 0 VectorNum VIntPriorityEncoder endif if Config3yprce 1 and EIC Option 3 vectorOffset EIC VectorOffset else vectorOffset 0x200 VectorNum x IntCtlyg 0 endif endif endif CalcIntrptAddress vectorBase vectorOffset endfunction CalcIntrptAddress Exceptions Coprocessor Unusable Exception TLB Refill TLB Invalid Address Error Watch Cache Error Bus Error Exceptions 264 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 31 26 25 21 20 16 15 0 LL 110000 base rt offset 6 5 5 16 Format LL rt offset base MIPS32 Purpose Load Linked Word To load a word from memory for an atomic read modify write Description GPR rt lt memory GPR base offset The LL and SC instructions provide the primitives to implement atomic read modify write RMW operations for synchronizable memory locations The contents of the 32 bit word at the memory location specified by the aligned effective address are fetched and written into GPR rt The 16 bit signed offset is added to the contents of GPR base to form an effective address
135. C instructions completed Yes SC instructions failed Yes 20 Prefetch instructions completed Yes Reserved NA 146 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Event Num Counter 0 Mode Counter 1 Mode 21 Reserved NA Reserved NA 22 Reserved NA Reserved NA 23 Exceptions taken Yes Reserved NA 24 Reserved NA Reserved NA 25 Reserved NA ALU stall cycles No 26 Reserved NA Reserved NA 27 Reserved NA Reserved NA 28 Reserved NA Implementation specific CP2 event Yes 29 Reserved NA Reserved NA 30 Implementation specific CorExtend event Yes Reserved NA 31 Reserved NA Reserved NA 32 Reserved NA Reserved NA 33 Reserved NA Reserved NA 34 Reserved NA Reserved NA 35 Reserved NA CP2 To From Instructions completed Yes 36 Reserved 37 Reserved NA Reserved NA 38 Reserved NA Reserved NA 39 Reserved NA Reserved NA 40 Uncached stall cycles Yes Reserved NA 41 MDU stall cycles Yes Reserved NA 42 CP2 stall cycles Yes CorExtend stall cycles Yes 43 Reserved NA Reserved NA 44 Reserved NA Reserved NA 45 Load to Use stall cycles Yes Reserved NA 46 Other interlock stall cycles Yes Reserved NA 47 Reserved NA Reserved NA 48 Reserved NA Reserved NA 49 EJTAG Instruction Triggerpoints Yes EJTAG Data Triggerpoints Yes 50 Reserved NA Reserved NA 51 Rese
136. Debug exception vector 4 8 12 Execution Exception System Call The system call exception is one of the nine execution exceptions All of these exceptions have the same priority A system call exception occurs when a SYSCALL instruction is executed Cause Register ExcCode Value Sys Additional State Saved None MIPS32 M14K Processor Core Software User s Manual Revision 02 03 87 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M14K Core Entry Vector Used General exception vector offset 0x180 4 8 13 Execution Exception Breakpoint The breakpoint exception is one of the nine execution exceptions All of these exceptions have the same priority A breakpoint exception occurs when a BREAK instruction is executed Cause Register ExcCode Value Bp Additional State Saved None Entry Vector Used General exception vector offset 0x 180 4 8 14 Execution Exception Reserved Instruction The reserved instruction exception is one of the nine execution exceptions All of these exceptions have the same pri ority A reserved instruction exception occurs when a reserved or undefined major opcode or function field is exe cuted This includes Coprocessor 2 instructions which are decoded reserved in the Coprocessor 2 Cause Register ExcCode Value RI Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 8 15 Executio
137. E dataword GPR rt if LLbit then StoreMemory CCA WORD dataword pAddr vAddr DATA endif GPR rt 0 LLbit Exceptions TLB Refill TLB Invalid TLB Modified Address Error Watch Programming Notes LL and SC are used to atomically update memory locations as shown below ll LL T1 TO load counter ADDI T2 T1 1 increment SC T2 TO try to store checking for atomicity BEQ T2 0 L1 if not atomic 0 try again NOP branch delay slot Exceptions between the LL and SC cause SC to fail so persistent exceptions must be avoided Some examples of these are arithmetic operations that trap system calls and floating point operations that trap or require software emu lation assistance LL and SC function on a single processor for cached noncoherent memory so that parallel programs can be run on uniprocessor systems that do not support cached coherent memory access types 270 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 271 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 0 A SYNC 000000 00 0000 0000 0000 0 yp 001111 6 15 5 6 Format SYNC stype 0 implied MIPS32 Purpose Synchronize Shared Memory To order loads and stores Descri
138. ELANE where BYTELANB 0 is 1 only if the byte at bits 7 0 on the bus is accessed and BYTELANE 1 is 1 only if the byte at bits 15 8 is accessed etc The DB addr match is shown below DB addr match all 1 s DBMnppy ADDR DBAnpga amp amp all O s gt BAI amp BYTELANE The size of DBCnga and BYTELANE is 4 bits Data value compare is included in the match condition for the data breakpoint depending on the bytes BYTELANE as described above accessed by the transaction and the contents of breakpoint registers The DB no value compare is shown below DB no value compare all 1 s gt DBCngg DBCnga BYTELANE The size of DBCng y DBCngA and BYTELANE is 4 bits In case a data value compare is required DB no value compare is false then the data value from the data bus DATA is compared and masked with the registers for the data breakpoint The DBCIVM bit inverts the sense of the match if set the value match term will be high if the data value is not the same as the data in the DBVn register The endianess is not considered in these match equations for value as the compare uses the data bus value directly thus debug software is responsible for setup of the breakpoint corresponding with endianess DB value match DBCnIVM DATA 7 0 DBVnpgy 7 0 BYTELANE 0 DBCngpy o DBCngai o amp amp DATA 1
139. ERRERA areae eei ENORA Tu casu INE BARRERA ESERE RA 176 Figure 8 TE DBM Register fPOFITIGl 20 educ usod eet omsero tedio Feist FoU EE pte Disk bises petu dete Desi CLR D Ribas 177 Figure o 12 2D BASID Register FORMAL usas seite ono RE sated cote os Pedes br ede ep aaaea vasis aa Ero a Ca ETN 177 Figure 8 19 DBOR Register FORMAL coord oes arsit E dass deut budretesnes iur scnaesinn udtas CO esses E rNaase EIN UI RR dESG 178 Figure 8 142 DBVn Register Fortmal eter etate etes ease AREAREN RERA FL RAE UEBER E Rada tid 179 Figure B 15 DBC Om Registe FOLTBL ede ke REESE DDR URN emU Iu hse A Ur natade a Dra t od pte talsm ce IEEE eia 180 Figure 8 16 DBPOn Register FORM AWS uie oer e Pcia moch than rae aa ao iaaii 181 Figure 8 1 4 DVM Register FOMAI scscsessanatsdsxennrtasitecrmnataaduhun addqubor accas uten ru daa iq adt acc ut n died Dd Rd SER diae P OUR IE 181 Figure 8 187 CB TG Register meu 182 Figure 8 19 PrOndA Register FORffial mcntio sono Deresauk etus Fert ces AT ERR Seda sU ieunieieesa beaver elon naan ode 183 Figure 9 20 STOI eSGISter FONTE szccccxdeodeetui pere daret adini aE E E CECE usas kz AEE 185 Figure 8 21 S TOnE Register FOTTIal odo oen pipe cbe enazy ss A ber aleada tes tunditur i ertsare trap IRL E dede 186 Figure 822 TAP Controller State Diag tality 2252 2 acaso casti rri aoe etc ota ie tor e e esa rust etes ati Seat rro gto DIE 192 Figure 8 23 Concatenation of the EJTAG Address Data and Control Registers
140. Encoding of T EIOIO oec et tatcm OE esas etti oet Lasse cw ea es rere cerr rereer e secL E PAM d rer 241 COP2 Encoding of rs Field 2 2 2 3 0 0 6 naina ELA COEUR De TEC accu ke dU EEXK oedema 241 Table 10 7 COP2 Ericoding or rt Field When Tes BS itt tre cans t cone neue sad Paru psa aX rase gps 241 Table 10 9 COPO Encoding oL tS FIeld uiii ocio iiir uto trece ctu A pu tasMi Ai RPdSIM UEM LUNO 242 Table 10 9 COPO Encoding of Function Field When ISS CO d tri tH EL E ERR HEAR 242 Table 10 10 Instructibhi Seba idet epo ed rts eu hedera a 242 Format Values of hint Field for PREF Instruction enne nnne nentes 267 Table 11 1 Table 11 2 16 Bit Re encoding of Frequent MIPS32 Instructions sesssssssseseeeenenee nnns 283 16 Bit Re encoding of Frequent MIPS32 Instruction Sequences sssssssssssssses 284 Table 11 3 Instruction Specific Register Specifiers and Immediate Field Values essssssssss 286 Table 11 4 16 Bit Instruction General Purpose Registers 2 7 16 17 ssssssssssssssseee 287 Table 11 5 SB16 SH16 SW16 Source Registers 0 2 7 17 sse 288 Table 11 6 16 Bit Instruction Implicit General Purpose Registers cccccceeeeeeeeeeeeeaeeeeeeeeeeeaeseeeeeeesaeeneeeeeees 288 Table 11 7 16 Bit Instruction Special Purpose Registers ssssssssssssseseeeee eret nnne 289 Table 11 8 32 bit Instructions
141. FDC in order to get the attention of the target by causing a debug exception It also allows a host based debugger to query the target via Debug Executive commands to determine the cause of the hang 8 7 2 EJTAG Features Unmodified by SecureDebug SecureDebug will not modify the following EJTAG features e FDC Fast Debug Channel over EJTAG This is required to provide a path for an EJTAG probe to send and receive messages via the Debug Executive when one is included in the target code The physical EJTAG serial connection pins and protocol must function correctly as well as a cJTAG 2 wire connection for FDC e RST signal This is the hardware signal on the EJTAG connector that connects to the target system reset circuit It can be asserted by an EJTAG probe 8 8 iFlowtrace Mechanism There is only one optional trace mechanism that is available to extract additional information about program execu tion iFlowtrace is a light weight instruction only tracing scheme that is sufficient to reconstruct the execution flow in the core and it can only be controlled by debug software This tracing scheme has been kept very simple to minimize the impact on die size MIPS32 M14K Processor Core Software User s Manual Revision 02 03 211 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core 212 The iFlowtrace tracing scheme is not a strict subset of the PDtrace tracing methodology a
142. Gontrol Register Field Descriptions ot tete ett eh Nro ioa ek tat EXER ES ends peu tap ex SER EE ERR RRDG 137 Table 5 33 TraceControl2 Register Field Descriptions sisii inasistencia 139 Table 5 34 UserTraceData1 UserTraceData2 Register Field Descriptions sssees 141 Table 5 35 TraceBPG Register Field Descriptions aoo cocco poet ette eee tute tere ep e Pe teen eiae reas sedute rid 142 Table 5 36 Debug Register Field DescripHoTiS isisisi nnna eee en PO UIDES DRE MSS Seu ie 143 Table 5 97 DEP GC Register FOMA ioo Porra ra epe aha et borea poorer Pac eae iaeia Pase n tere ee NT 144 Table 5 38 Performance Counter Register Selects sissies aiai 145 Table 5 39 Performance Counter Control Register Field Descriptions eeseeeeeeennnne 145 Table 5 40 Event Desc HOS 9 9 n 17 odo DRE Ug ede sut o oS eu aoe DORT eee em IUS EE iu 148 Table 5 41 Performance Counter Count Register Field Descriptions ssssseeen 149 Table 5 42 Erratl Register Field DescripiQliS iuc coo acne pp tuta utn eae e nx beoe eu ur ee ur sadi c dese pras dde trux aiBes cards 150 Table 5 43 CacheErr Register Field Descriptions Primary Caches ssssseeeeene 150 Table 5 44 ErrorEPC Register Field Description etat tnter etum Deren ako nate Rx ru B e oA SKRRR US e DPA SEE a 152 Table 5 45 DeSave Register Field Description sseeseseeessesssseeseseeee eee tn nennen EI
143. I LJ LI LI LI LI LJ RS Adjust Add Subtract Add Subtract Rem Adjust Sign Adjust Early In MDU Res Rdy 2 4 MDU Pipeline Area Efficient MDU The area efficient multiply divide unit MDU is a separate autonomous block for multiply and divide operations The MDU is not pipelined but rather performs the computations iteratively in parallel with the integer unit IU pipe line and does not stall when the IU pipeline stalls This allows the long running MDU operations to be partially masked by system stalls and or other integer unit instructions The MDU consists of one 32 bit adder result accumulate registers HI and LO a combined multiply divide state machine and all multiplexers and control logic A simple 1 bit per clock recursive algorithm is used for both multi ply and divide operations Using Booth s algorithm all multiply operations complete in 32 clocks Two extra clocks are needed for multiply accumulate The non restoring algorithm used for divide operations will not work with nega tive numbers Adjustment before and after are thus required depending on the sign of the operands All divide opera tions complete in 33 to 35 clocks Table 2 3 lists the latencies number of cycles until a result is available for multiply and divide instructions The latencies are listed in terms of pipeline clocks In this table latency refers to the number of cycles necessary for the second instruction to use the
144. If this tracing mode is not imple 2 0 mented the field is read only and read as zero EST Enable Special Tracing Modes If set normal tracing is Optional for inhibited allowing the user to choose one of several spe iFlowTrace rev cial tracing modes Setting this bit inhibits normal trace 2 0 mode If no special tracing modes are implemented this field is read only and read as zero SyP Synchronization Period The synchronization period is set Required for to 2YP 9 instructions Thus a value of 0x0 implies 256 iFlowTrace rev instructions and a value of OxF implies 8M instructions 2 0 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 219 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Table 8 37 Control Status Register Field Descriptions Continued Fields Name Description Compliance OfCIk Controls the Off chip clock ratio When the bit is set this Required implies 1 2 that is the trace clock is running at 1 2 the core clock and when the bit is clear implies 1 4 ratio that is the trace clock is at 1 4 the core clock Ignored unless OfC is also set OfC Off chip 1 enables the PIB if present to unload the trace Preset Required memory 0 disables the PIB and would be used when on chip storage is desired or if a PIB is not present This bit is settable only if the design supports both on chip and off chip modes Otherwise is a read only bi
145. K Core Pipeline Stages with high performance MDU L we ET La qux l l l pog gno Ww x iul i A gt E Bypass i M gt E Bypass TEE RN I A gt E Bypass I SS e e Ae mu MDU Res Rdy RegW Mult Macc 16x16 32x16 CPA MDU Res Rd Nuit Mace 32a CPA MDU Res Rdy l Divide J Sign Adjust MDU Res Rd l l l l l IU Pipeline MDU Pipeline SRAM read Instruction Decode Register file read Instruction Address Calculation stage 1 and 2 Arithmetic Logic and S hift operations Data Address Calculation DSRAM read Load data aligner Register file write MUL instruction Carry Propagate Adder Multiply and Multiply Accumulate instructions Divide instructions Last stage of Divide is a sign adjust Result can be read from MDU One or more cycles Figure 2 2 shows the operations performed in each pipeline stage of the M14K processor core when the area efficient multiplier is present Figure 2 2 M14K Core Pipeline Stages with area efficient MDU LOT LOI LCI LT 1 l E M A W SRAM l l A gt E Bypass l l l r pj A E Bypass puc 7 To nes l l i Muliply Divide MbUResRd 1 i 2 1 1 I Stage Instruction Fetch During the Instruction fetch stage WDU Pipeli IU Pipelin e An instruction is fetched from the instructionSRAM Dec
146. LAT 152 Table 8 1 DCR Register Field Descriptions rinasa a E EA 160 Table 8 2 Addresses for Instruction Breakpoint Registers ene 170 Table 8 8 IBS Register Field DGescriptiORs s succo ope ett Ee net DRE Rex eee qup ECHO aU ter Ere acadaeipradedevessh acioedipte 170 Table 8 4 IBAn Register Field DeSCHDLIOFS asco notet eter t prn n er abre rr ka ta aaia And spen 171 Table 8 6 IBASIDn Register Field Descriptions idt a a a R aaa 172 Table 8 7 BCM Register Field Descriptions nassi moreso soot roue tanien ER sae eR LO eR e AATE A 172 Table 8 5 BM Register Field Descriptors ecupeotaooexxo s en eek teta eR oed ede a es 172 Table 8 8 IBGOn Register Field DescripliOTis sscda ortae perrita ti th mere pu tre rera pers vla nra eee ee lore e pan 174 Table 8 9 IBPGn Register Field Descriplloris ssicui reine iren uice pa ecu pulse deed Dur Ri dede bc duisi p Econ E ReiR E EEFH RR DAS 175 Table 8 10 Addresses for Data Breakpoint Registers cccceeeseeceeeeeeeeneeeeeeeaeeeeeeeeaaeeeeeeeaaaeeesecesaeeeeseeseenenees 175 Table 8 11 DBS Register Field Descriptions ceo scone Et E tese drei een ie Rea tenus EP ES SERRRDE 176 Table 8 12 DBAn Register Field Descriptions irri pini eei tionc cttam ie tuin eec peret dus 176 Table 8 19 DBMn Register Field DescripllOlis visccse aciei per iac uper decis uer bene aai 177 Table 8 14 DBASIDn Register Field Descriptions oi iet tiere reton cd rhe sea eet E heec betont tinens at aAa 177
147. M14K Processor Core Software User s Manual Revision 02 03 63 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M14KT Core When an exception condition is detected on an instruction fetch the core aborts that instruction and all instructions that follow When this instruction reaches the W stage various CPO registers are written with the exception state change the current program counter PC to the appropriate exception vector address and clearing the exception bits of earlier pipeline stages This implementation allows all preceding instructions to complete execution and prevents all subsequent instructions from completing Thus the value in the EPC ErrorEPC for errors or DEPC for debug exceptions is sufficient to restart execution It also ensures that exceptions are taken in the order of execution an instruction taking an exception may itself be killed by an instruction further down the pipeline that takes an exception in a later cycle 4 2 Exception Priority Table 4 1 contains a list and a brief description of all exception conditions The exceptions are listed in the order of their relative priority from highest priority Reset to lowest priority When several exceptions occur simultaneously the exception with the highest priority is taken Table 4 1 Priority of Exceptions Exception Description Reset Assertion of S _ColdReset signal Soft Reset Assertion of S _Reset si
148. MIIS MIPS32 M14K Processor Core Software User s Manual Document Number MD00668 Revision 02 03 April 30 2012 MIPS Technologies Inc 955 East Arques Avenue Sunnyvale CA 94085 4521 Copyright 2009 2010 MIPS Technologies Inc All rights reserved MIPS x7 Verified Copyright 2009 2010 MIPS Technologies Inc All rights reserved Unpublished rights if any reserved under the copyright laws of the United States of America and other countries This document contains information that is proprietary to MIPS Technologies Inc MIPS Technologies Any copying reproducing modifying or use of this information in whole or in part that is not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly prohibited At a minimum this information is protected under unfair competition and copyright laws Violations thereof may result in criminal penalties and fines Any document provided in source format i e in a modifiable form such as in FrameMaker or Microsoft Word format is subject to use and distribution restrictions that are independent of and supplemental to any and all confidentiality restrictions UNDER NO CIRCUMSTANCES MAY A DOCUMENT PROVIDED IN SOURCE FORMAT BE DISTRIBUTED TO A THIRD PARTY IN SOURCE FORMAT WITHOUT THE EXPRESS WRITTEN PERMISSION OF MIPS TECHNOLOGIES INC MIPS Technologies reserves the right to change the information contained in this document to improve function d
149. MIPS Technologies Inc All rights reserved 10 3 MIPS32 Instruction Set for the M14K core Table 10 10 Instruction Set Continued MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Instruction Description Function EXT Extract Bit Field Rt ExtractField Rs msbd lsb INS Insert Bit Field Rt InsertField Rt Rs msb sb IRET Return from Exception See MCU ASE Instructions J Unconditional Jump PC PC 31 28 Il offset lt lt 2 JAL Jump and Link GPR 31 PC 8 PC PC 31 28 Il offset lt lt 2 JALR Jump and Link Register Rd PC 8 PC Rs JALR HB Jump and Link Register with Hazard Barrier Rd PC 8 PC Rs Stall until all execution and instruc tion hazards are cleared JR Jump Register PC Rs JR HB Jump Register with Hazard Barrier PC Rs Stall until all execution and instruc tion hazards are cleared LB Load Byte Rt byte Mem Rs offset LBU Unsigned Load Byte Rt ubyte Mem Rs offset LH Load Halfword Rt half Mem Rs offset LHU Unsigned Load Halfword Rt uhalf Mem Rs offset LL Load Linked Word Rt Mem Rs offset LL 1 LLAdr Rs offset LUI Load Upper Immediate Rt immediate lt lt 16 LW Load Word Rt Mem Rs offset LWC2 Load Word To Coprocessor 2 CPR 2 n 0 Mem Rs offset LWL Load Word Left See LWL instruction LWR Load Word Right See LWR instruction MADD Multiply Add HI LO int Rs int Rt MFCO Move From Coprocessor 0 Rt CPR O n sel MFC2 Move From
150. MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core Table 5 39 Performance Counter Control Register Field Descriptions Continued EXL 0 Count when EXL When this bit is set count the event when EXL Undefined 1 and ERL 0 0 30 12 2 Must be written as zeroes returns zeroes when read 0 0 Table 6 60 describes the events countable with the two performance counters The mode column indicates whether the event counting is influenced by the mode bits U K EXL The operation of a counter is UNPREDICTABLE for events which are specified as Reserved Performance counters never count in debug mode or when ERL 1 Event Num Counter 0 Mode Counter 1 Mode 0 Cycles No Cycles No 1 Instructions completed Yes Instructions completed Yes 2 branch instructions Yes Reserved NA 3 JR r31 return instructions Yes Reserved NA 4 JR not r31 instructions Yes Reserved NA 5 Reserved NA Reserved NA 6 Reserved NA Reserved NA 7 Reserved NA Reserved NA 8 Reserved NA Reserved NA 9 Reserved NA Reserved NA 10 Reserved NA Reserved NA 11 Reserved NA Reserved NA 12 Reserved NA Reserved NA 13 Reserved NA Reserved NA 14 integer instructions completed Yes Reserved NA 15 loads completed Yes Stores completed Yes 16 J JAL completed Yes microMIPS instructions completed Yes 17 no ops completed Yes Integer multiply divide completed Yes 18 Stall cycles No Reserved NA 19 S
151. MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Figure 5 14 shows the format of the NestedEPC register Table 5 18 describes the NestedEPC register fields Figure 5 16 NestedEPC Register Format 31 0 NestedEPC Table 5 20 NestedEPC Register Field Descriptions Fields Read Reset Name Bits Description Write State Compliance NestedEPC 31 0 Nested Exception Program Counter R W Undefined Required Updated by exceptions which would update EPC if StatuSey is not set MCheck Interrupt Address Error all TLB exceptions Bus Error CopUnusable Reserved Instruction Overflow Trap Syscall FPU etc For these exception types this register field is updated regardless of the value of Status Ex Not updated by exception types which update ErrorEPC Reset Soft Reset NMI Cache Error Not updated by Debug exceptions 5 2 17 Processor Identification CPO Register 15 Select 0 The Processor Identification PRid register is a 32 bit read only register that contains information identifying the manufacturer manufacturer options processor identification and revision level of the processor Figure 5 17 PRid Register Format 31 24 23 16 15 8 7 5 4 2 1 0 Company Opt Company ID Processor ID Revision Table 5 21 PRid Register Field Descriptions Field
152. MS causes the controller to transition to the Select DR Scan state 8 4 3 Test Access Port TAP Instructions The TAP Instruction register allows instructions to be serially input into the device when TAP controller is in the Shift IR state Instructions are decoded and define the serial test data register path that is used to shift data between TDI and TDO during data register scanning MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 4 Test Access Port TAP The Instruction register is a 5 bit register In the current EJTAG implementation only some instructions have been decoded the unused instructions default to the BYPASS instruction Table 8 28 Implemented EJTAG Instructions 8 4 3 1 BYPASS Instruction Value Instruction Function 0x01 Select Chip Identification data register 0x03 IMPCODE Select Implementation register 0x08 ADDRESS Select Address register 0x09 DATA Select Data register 0x0A CONTROL Select EJTAG Control register 0x0B ALL Select the Address Data and EJTAG Control registers 0x0C EJTAGBOOT Set EjtagBrk ProbEn and ProbTrap to 1 as reset value 0x0D NORMALBOOT Set EjtagBrk ProbEn and ProbTrap to 0 as reset value OxOE FASTDATA Selects the Data and Fastdata registers 0x10 TCBCONTROLA Selects the TCBTCONTROLA register in the Trace Control Block 0x11 TCBCONTROLB Selects the TCBTCONT
153. O SLND nN AJo The value of this field is UNPREDICTABLE if Exter nal Interrupt Controller Mode is both implemented and enabled The external interrupt controller is expected to provide this information for that interrupt mode If EJTAG FDC is not implemented this field returns zero on read 106 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 9 IntCtl Register Field Descriptions Continued Fields Reset Read Write State Name Bits Description Enables Vector Prefetching Feature Encoding Meaning 0 Vector Prefetching disabled 1 Vector Prefetching enabled For IRET instruction Enables Interrupt Chaining Encoding Meaning 0 Interrupt Chaining disabled 1 Interrupt Chaining enabled For Auto Prologue feature This is the number of 4 byte words that is decremented from the value of GPR29 Encoding Decrement Amount in Words Decrement Amount in Bytes 0 3 3 12 Others As encoded e g 0x5 means 5 words 4 encoded value e g 0x5 means 20 bytes CIrEXL For Auto Prologue feature and IRET instruction If set during Auto Prologue and IRET interrupt chain ing the KSU ERL EXL fields are cleared Encoding Meaning 0 Fields are not cleared by thes
154. O cJTAG TMSC Controller L TCK Converion TCK TMS Block SecureDebug SecureDebug improves security by disabling untrusted EJTAG debug access An input signal is used to disable debug features such as Probe Trap Debug Interrupt Exception EjtagBrk and DINT signal the EJTAGBOOT instruction and PC Sampling MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 1 2 M14K Core Block Diagram 1 2 2 5 Coprocessor 2 Interface CP2 The optional coprocessor 2 CP2 interface provides a full featured interface for a coprocessor It provides full sup port for all the MIPS32 COP2 instructions with the exception of the 64 bit Load Store instructions LDC2 SDC2 The CP2 interface can provide access to a graphics accelerator coprocessor or a simple register file There is no sup port for the floating point coprocessor COP1 which requires 64 bit data transfers Refer to Chapter 10 M14K Processor Core Instructions on page 239 for more information on the Coprocessor 2 supported instructions 1 2 2 6 CorExtend User Defined Instructions UDI This optional module contains support for CorExtend user defined instructions These instructions must be defined at build time for the M14K core Access to UDI requires a separate license from MIPS and the core is then referred to as the M14K Pro core When licensed 16 instructions in
155. O register Debug Probe Software can determine which ISA is used when handling a debug exception by checking the state of the ISAOnDebug field in the EJTAG TAP Control register 11 1 4 Compliance and Subsetting This document does not change the instruction subsets as defined by the other MIPS32 architecture reference manu als including the subsets defined by the various ASEs 11 1 5 Mode Switch The MIPS32 architecture defines an ISA mode for each processor An ISA mode value of 0 indicates MIPS32 instruc tion decoding In processors implementing microMIPS an ISA mode value of 1 selects microMIPS instruction decoding In processors implementing the MIPS16e ASE an ISA mode value of 1 selects the decoding of instructions as MIPS16e In microMIPS implementations the ISA mode is not directly visible to normal software When EJTAG is imple mented the ISAMode is reflected in the EJTAG TAP Control register MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 11 11 11 2 11 2 Instruction Formats Mode switching between MIPS32 and microMIPS uses the same mechanism used by MIPS 16e namely the JALX JR JR HB JALR and JALR HB instructions as described below The JALX instruction executes a JAL and switches to the other mode e The JR and JALR instructions interpret bit 0 of the source registers as the target ISA mode O MIPS32 1 micro MI
156. O registers pair in the the Wypy stage while the Sub instruction writes to the register file in the W stage 2 3 1 32x16 Multiply High Performance MDU The 32x16 multiply operation begins in the last phase of the E stage which is shared between the integer and MDU pipelines In the latter phase of the E stage the rs and rt operands arrive and the Booth recoding function occurs at this time The multiply calculation requires one clock and occurs in the Mypy stage In the Aypy stage the carry propagate add CPA function occurs and the operation is completed The result is ready to be read from the HI LO registers in the Wy stage Figure 2 4 shows a diagram of a 32x16 multiply operation Figure 2 4 MDU Pipeline Flow During a 32x16 Multiply Operation Clock 1 2 3 4 Booth Array CPA 2 3 2 32x32 Multiply High Performance MDU The 32x32 multiply operation begins in the last phase of the E stage which is shared between the integer and MDU pipelines In the latter phase of the E stage the rs and rt operands arrive and the Booth recoding function occurs at this time The multiply calculation requires two clocks and occurs in the Mypy stage In the Aypy stage the CPA function occurs and the operation is completed MIPS32 M14K Processor Core Software User s Manual Revision 02 03 37 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Pipeline of the M14K Core Figure 2 5 shows a diagram of a 32x32
157. PO Register 13 Select 5 Compliance Level Optional The Nested Exception NestedExc register is a read only register containing the values of Statusgy and Statusgg prior to acceptance of the current exception 118 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions This register is part of the Nested Fault feature The existence of the register can be determined by reading the Config5NFExists bit Figure 5 14 shows the format of the NestedExc register Table 5 18 describes the NestedExc register fields Figure 5 14 NestedExc Register Format 31 3 2 1 0 0 ERL EXL 0 Table 5 18 NestedExc Register Field Descriptions Fields Read Reset Name Bits Description Write State Compliance 0 31 3 Reserved read as 0 RO 0 Required ERL 2 Value of StatuSgg prior to acceptance of current R Undefined Required exception Updated by all exceptions that would set either Statusgyx or Slatusgg Not updated by Debug exceptions EXL 1 Value of StatuSey prior to acceptance of current R Undefined Required exception Updated by exceptions which would update EPC if StatuSey is not set MCheck Interrupt Address Error all TLB exceptions Bus Error CopUnusable Reserved Instruction Overflow Trap Syscall FPU etc For these exception types this register field is updated regardless
158. PS and therefore set the ISA Mode bit according to the contents of bit 0 of the source register For the actual jump operation the PC is loaded with the value of the source register with bit 0 set to 0 The same applies to JR HB and JALR HB The instructions JALR and JALR HB save the ISA mode into bit 0 of the destination reg ister When exceptions or interrupts occur and the processor writes to EPC DEPC or ErrorEPC the ISA Mode bit is saved into bit 0 of these registers Then the ISA Mode bit is set according to the Config3 sA register field On return from an exception the processor loads the ISA Mode bit based on the value from either EPC DEPC or ErrorEPC If only one ISA mode exists either MIPS32 or microMIPS then this mode switch mechanism does not exist and the ISA mode has a fixed value O MIPS32 1 microMIPS Executing the JALX instruction will cause a Reserved Instruction exception JR and JALR instructions cause an Address exception on the target instruction fetch when bit 0 of the source register is different from the ISA mode The same applies to JR HB and JALR HB Exception handlers must be encoded in the instruction format supported by the processor 1 6 Branch and Jump Offsets In the MIPS32 architecture because instructions are always 32 bits in size the jump and branch target addresses are word 32 bit aligned Jump branch offset fields are shifted left by two bits to create a word aligned effective address In the
159. Pipeline IMMCSTIOCKS sexcssiccccncdacseauesseacyantwarssuadateodaas cade adnate qewasesececueasdaaysxanannggddan ed RARE UE E a EA 45 Table 2 5 Instruction InterloeKS caosa reri ds nate tet etu i tue PIRE teh ere 2 M duacecees RERESR REESE ERN AME 47 Table 2 6 Execution Pazaltds inp cioe do ien er poti Aq EDU t faa ncc Seb ODE E De beth eda Eie cece 48 Table 2 7 Instruction Plazalds uei ocior sperent tia brote t Extras ene gr pore ih be ea arr Re SERM npe SEEN npa XR pects 48 Table 2 8 Hazard Instruction LISUFIQ s sator Rasen eO adio cct ct Do sede ior ud rto edd EQ Nude Oa addi ODER R MON de 49 icio xm User Mode Segments nic iatene NE E N RRN 54 Table 3 2 Kernel Mode Segments sissies E E nausea pede 56 Table 3 3 Physical Address and Cache Attributes for dseg dmseg and drseg Address Spaces 58 Table 3 4 CPU Access to drseg Address Hallge cipere pen ceret pee mmn aiiai Aa 58 Table 3 5 CPU Access to dimseg Address Rangersiin iato eaae tes eei iier ease vues NR 59 Table 3 6 Cacheability of Segments with Block Address Translation 59 Table asi Prony Of EXC puns C 64 Ta ble4 2 Intermpt MOCBS ossibus tob fate oues p tasa tend ibo ton adno pt p Ka od etm adiu pdr sd b c iai d io prafbn EOS 66 Table 4 3 Relative Interrupt Priority for Vectored Interrupt MOdG cccccceeceecceceeeeeeeceeeeeeeecaeeeseeeeaeeeeseeeaeeenteees 69 Table 4 4 Exception Vector Offsets fo
160. Processor Core Software User s Manual Revision 02 03 233 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Instruction Set Overview Figure 9 1 Instruction Formats I Type Immediate 31 26 25 2120 16 15 0 Co os eO mmo Type J ump 31 2625 0 op target R Type PERREN 2625 2120 1615 1110 A a E ad op 6 bit operation code TS 5 bit source register specifier rt 5 bit target source destination register or branch condition immediate 16 bit immediate value branch displacement or address displacement target 26 bit jump target address rd 5 bit destination register specifier sa 5 bit shift amount funct 6 bit function field 9 2 Load and Store Instructions 9 2 1 Scheduling a Load Delay Slot A load instruction that does not allow its result to be used by the instruction immediately following is called a delayed load instruction The instruction slot immediately following this delayed load instruction is referred to as the load delay slot In an M14K core the instruction immediately following a load instruction can use the contents of the loaded register however in such cases hardware interlocks insert additional real cycles Although not required the scheduling of load delay slots can be desirable both for performance and R Series processor compatibility 9 2 2 Defining Access Types Access type indicates the size of a core data item to be loaded or stored set by the load or store instruction
161. ROLB register in the Trace Control Block 0x12 TCBDATA Selects the TCBDATA register in the Trace Control Block 0x14 PCSAMPLE Selects the PCsample register 0x17 FDC Selects Fast Debug Channel Ox1F BYPASS Bypass mode The required BYPASS instruction allows the processor to remain in a functional mode and selects the Bypass register to be connected between TD and TDO The BYPASS instruction allows serial data to be transferred through the pro cessor from TD to TDO without affecting its operation The bit code of this instruction is defined to be all ones by the IEEE 1149 1 standard Any unused instruction is defaulted to the BYPASS instruction 8 4 3 2 IDCODE Instruction The IDCODE instruction allows the processor to remain in its functional mode and selects the Device Identification ID register to be connected between TD and TDO The Device ID register is a 32 bit shift register containing infor mation regarding the IC manufacturer device type and version code Accessing the Identification Register does not interfere with the operation of the processor Also access to the Identification Register is immediately available via a TAP data scan operation after power up when the TAP has been reset with on chip power on or through the optional TRST Npin 8 4 3 3 IMPCODE Instruction This instruction selects the Implementation register for output which is always 32 bits 8 4 3 4 ADDRESS Instruction This instruction is used to select
162. Register Format 31 0 UserLocal MIPS32 M14K Processor Core Software User s Manual Revision 02 03 97 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core Table 5 3 UserLocal Register Field Descriptions Fields Description Write Reset State UserLocal 31 0 This field contains software information that is not interpreted by Undefined hardware Programming Notes Privileged software may write this register with arbitrary information and make it accessible to unprivileged software via register 29 ULR of the RDHWR instruction To do so bit 29 of the HWREna register must be set to a 1 to enable unprivileged access to the register In some operating environments the UserLocal register contains a pointer to a thread specific storage block that is obtained via the RDHWR register 5 2 2 HWREna Register CPO Register 7 Select 0 The HWRHEna register contains a bit mask that determines which hardware registers are accessible via the RDHWR instruction Figure 5 2 shows the format of the HWREna Register Table 5 4 describes the HWREna register fields Figure 5 2 HWREna Register Format 31 30 29 28 4 3 0 0 ULR 0 Mask Table 5 4 HWREna Register Field Descriptions Fields Name Bits Description Read Write Reset State 0 0 31 30 28 4 Must be written with zero returns zero on read Must be
163. Register State Value CauselP indicates the interrupts that are pending Entry Vector Used See 4 3 2 Generation of Exception Vector Offsets for Vectored Interrupts on page 74 for the entry vector used depending on the interrupt mode the processor is operating in 4 8 6 Debug Instruction Break Exception A debug instruction break exception occurs when an instruction hardware breakpoint matches an executed instruc tion The DEPC register and DBD bit in the Debug register indicate the instruction that caused the instruction hard ware breakpoint to match This exception can only occur if instruction hardware breakpoints are implemented Debug Register Debug Status Bit Set DIB Additional State Saved None Entry Vector Used Debug exception vector 4 8 7 Address Error Exception Instruction Fetch Data Access An address error exception occurs on an instruction or data access when an attempt is made to execute one of the fol lowing e Fetch an instruction load a word or store a word that is not aligned on a word boundary e Load or store a halfword that is not aligned on a halfword boundary e Reference the kernel address space from user mode MIPS32 M14K Processor Core Software User s Manual Revision 02 03 85 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M14KT Core 86 Note that in the case of an instruction fetch that is not aligned on a word bo
164. Return and Exception Tracing mode to trace the PC value of function calls and returns and or exceptions and returns e Breakpoint Match mode traces the breakpoint ID of a matching breakpoint and for data breakpoints the PC value of the instruction that caused it e Filtered Data Tracing mode traces the ID of a matching data breakpoint the load or store data value access type and memory access size and the low order address bits of the memory access which is useful when the data breakpoint is set to match a binary range of addresses e User Trace Messages The user can instrument their code to add their own 32 bit value messages into the trace by writing to the CPO User Trace Data register e Delta Cycle mode works in combination with the above trace modes to provide a timestamp between stored events It reports the number of cycles that have elapsed since the last message was generated and put into the trace Refer to Chapter 8 EJTAG Debug Support in the M14K Core on page 159 for more information on the EJTAG features cJTAG Support The M14K core provides an external conversion block that converts the existing EJTAG IEEE 1149 1 4 wire inter face at the M14K core to a cJTAG IEEE 1149 7 2 wire interface cJTAG reduces the number of wires from 4 to 2 and enables the support of Star 2 scan topology in the system debug environment Figure 1 4 cJTAG Support MIA4K EJTAG cJTAG 4 wire 2 wire interface interface TDI Tap TD
165. Sob iiio tier aane bc Rid Hiep eh RU aereo E OE bn E 234 92 2 Defining ACCESS TV OCS i tior dca aa RUE Cpu SOLEM Rb IOS UR us DOR DUE a cR URL tc ess 234 9 3 Compultational nsir eHOEiSs accio ctiee roti up esEs aee E R CU neers dade 235 9 3 1 Cycle Timing for Multiply and Divide Irstruetlons iriure onere tette sanae truc 236 9 4 Jump and Branch InsttcHOrS 2 2o irae etn Rote Rss rites ee bese lass seed N ie ix eed eR R 236 9 4 1 Overview of Jump Instructions enne nennen nens snnm en nnne nnne nenas 236 9412 Overview of Branch Instructors eiae cocta de esae EE EE se ARE 236 2 5 GoniellnstblctiofiS is etos ice vest tt ono tite sut xcci duse sane tics doa don etna mae DNE 236 9 6 Goprocessor INSU CHOFiS secet ioa aet heed S Ris Rc lucu E RE PHP ATARE 236 6 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 9 7 Enhancements to the MIPS Architecture ccc ce ccccc cece ceeccesuueeeecseescueeeeseeeeuueaseseseueeaaesseseuaeaaeseees 236 9 Zac CEO Count Leading OMNES is soon retenu desta tue E dd dm steadiastenctnagtericadeasexateanuanes 237 9 AnesObz s Count Leading Zeros etae te td tete Lee eto sec rt et see UR ES 237 9 73 MABD Muluply and Add Woldissuiistce eos reris tet txt eni Sut E Sepa E Ede tes uS P Eros uESEEGS 237 9 7 4 MABDU Multiply and Add Unsigned Word 1 tt ett pt tr nenas 237 9 7 5 MSUB Multiply and Subtract VOI rero
166. Statusgg to 1 Reset Soft Reset NMI or cache error does not save SHSClless in SRSCtlpss If software sets Statusgpz to 1 it must be aware of the operation of an IRET that may be subsequently executed The stack transactions behave as individual LW operations with respect to exception reporting BadVAddr would report the faulting address for an unaligned access and the faulting word address for unprivileged access TLB Refill and TLB Invalid exceptions For TLB exceptions the faulting word address would be reflected in the Context and EntryHi registers The CacheError register would reflect the faulting word address for Cache Errors Operation if IntCtlagg 0 Statusgg 1 Statusggy 1 Act as ERET read Operation section of ERET description else if ISAMode EPC PC4 4 1 in case of memory exception else EPC PC in case of memory exception endif temp lt 0x4 GPR 29 tempStatus LoadStackWord temp ClearHazards if IntCtlyp 0 IntCtlygp 1 amp tempStatusyp gt EICRIPL temp 0x8 GPR 29 tempSRSCtl lt LoadStackWord temp temp lt 0x0 GPR 29 tempEPC LoadStackWord temp endif Status tempStatus if IntCtlyog 0 IntCtlyog 1 amp tempStatusyp gt EICprpy GPR 29 GPR 29 DecodedValue IntCtlstkpec SRSCtl lt tempSRSCtl EPC lt tempEPC temp lt EPC StatuSpy amp 0 if Arc
167. TAG that EBase retains its reset Exception StatUSggy Status Cause ProbEn state and that IntCtl 0 Reset Soft Reset NMI X x 16 BFCO 0000 EJTAG Debug X x 16 BFCO 0480 EJTAG Debug x x 164FF20 0200 SRAM Parity Error 0 x EBase 31 30 241 EBase 28 12 163100 SRAM Parity Error 1 x X X 16 BFCO 0300 Interrupt 0 0 0 x 16 8000 0180 78 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 6 General Exception Processing Table 4 7 Exception Vectors Continued Vector For Release 2 Implementations assumes EJTAG that EBase retains its reset Exception Statusppy Status Cause ProbEn state and that IntCtly 0 Interrupt 0 0 16 8000 0200 Interrupt 1 0 16 BFCO 0380 Interrupt 1 0 16 BFCO 0400 All others 0 X 16 8000 0180 All others 1 X X X 16 BFCO 0380 x denotes don t care 4 6 General Exception Processing With the exception of Reset Soft Reset NMI cache error and EJTAG Debug exceptions which have their own spe cial processing as described below exceptions have the same basic processing flow e Ifthe EXL bit in the Status register is zero the EPC register is loaded with the PC at which execution will be restarted and the BD bit is set appropriately in the Cause register see Table 5 15 The value loaded into the EPC register is dependent on wh
168. TCB Encoding Meaning 0 Only one trace buffer is imple mented and the Debug sin gle step exception bit of this register indicates which trace buffer is implemented 1 Both on chip and off chip trace buffers are implemented by the TCB and the TBU bit of this register indicates to which trace buffer the trace is currently writ ten TBU 3 This bit denotes to which trace buffer the trace is cur R Undefined rently being written and is used to select the appropri ate interpretation of the TraceControlZs p field Encoding Meaning 0 Trace data is being sent to an on chip trace buffer 1 Trace Data is being sent to an off chip trace buffer Copyright 2009 2010 MIPS Technologies Inc All rights reserved MIPS32 M14K Processor Core Software User s Manual Revision 02 03 5 2 CPO Register Descriptions Table 5 33 TraceControl2 Register Field Descriptions Continued Fields Name Bits Description Read Write Reset State SyP 2 0 Used to indicate the synchronization period R Undefined The period in cycles between which the periodic syn chronization information is to be sent is defined as shown below for both when the trace buffer is on chip and off chip SyP On chip Off chip 000 2 27 001 33 28 010 24 29 011 25 210 100 26 211 101 y 212 110 28 213 111 2 m The On chip column value is used when the trace data is being written t
169. The TAP consists of a small controller driven by the TCK input which responds to the TMS input as shown in the state diagram in Figure 8 22 The TAP uses both clock edges of TCK TMS and TDI are sampled on the rising edge of TCK while TDO changes on the falling edge of TCK At power up the TAP is forced into the Test Logic Reset by low value on TRST_N The TAP instruction register is thereby reset to IDCODE No other parts of the EJTAG hardware are reset through the Test Logic Reset state When test access is required a protocol is applied via the TMS and TCK inputs causing the TAP to exit the Test Logic Reset state and move through the appropriate states From the Run Test Idle state an Instruction register scan or a data register scan can be issued to transition the TAP through the appropriate states shown in Figure 8 22 The states of the data and instruction register scan blocks are mirror images of each other adding symmetry to the pro tocol sequences The first action that occurs when either block is entered is a capture operation For the data registers the Capture DR state is used to capture or parallel load the data into the selected serial data path In the Instruction register the Capture IR state is used to capture status information into the Instruction register From the Capture states the TAP transitions to either the Shift or Exit states Normally the Shift state follows the Capture state so that test data or status informati
170. WP fields all fields in the Cause register are read only Release 2 of the Architecture added optional support for an External Interrupt Controller EIC interrupt mode in which P7 2 are interpreted as the Requested Interrupt Priority Level RIPL Figure 5 12 shows the format of the Cause register Table 5 15 describes the Cause register fields Figure 5 12 Cause Register Format 31 30 29 28 27 26 25 24 23 22 21 20 18 17 10 9 8 7 6 2 1 0 BDITI CE DC PCI IC AP IV WP cm 0 IPO IP2 IP1 IPO 0 Exc Code 0 RIPL Table 5 15 Cause Register Field Descriptions Fields Name Bits Description Read Write Reset State BD 31 Indicates whether the last exception taken occurred in a R Undefined branch delay slot Encoding Meaning 0 Not in delay slot 1 In delay slot The processor updates BD only if StatuSgx was zero when the exception occurred MIPS32 M14K Processor Core Software User s Manual Revision 02 03 113 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core Table 5 15 Cause Register Field Descriptions Continued Fields Name Bits Description Read Write Reset State TI 30 Timer Interrupt This bit denotes whether a timer inter R Undefined rupt is pending analogous to the P bits for other inter rupt types Encoding Meaning 0 No
171. a 1110 that sends a full PC value A discontinuity might happen due to various reasons for example an internal buffer over flow and at trace on trace off trigger action 8 8 2 Special Trace Modes iFlowtrace 2 0 adds special trace modes which can only be active when the normal tracing mode is disabled Software can determine which modes are supported by attempting to write the enable bits in the FCTL register Software can check the Illegal bit in the FCTL register if an unsupported combination of modes is requested the bit will be set and the trace contents will be unpredictable The special trace modes are described below 8 8 2 1 Mode Descriptions Delta Cycle Mode This mode is specified in combination with the other special trace modes It is enabled via the CYC bit in the Con trol Status Register When delta cycle reporting is enabled each trace message will include a 10b delta cycle value which reports the number of cycles that have elapsed since the last message was generated A value of 0 indicates that the two messages were generated in the same cycle A value of 1 indicates that they were generated in consecutive cycles If 1023 cycles elapse without an event being traced a counter rollover message is generated Note If the processor clocks stop due to execution of the WAIT instruction the delta cycle counter will also stop and will report active cycles between events rather than total cycles Breakpoint Match Mod
172. a a Rua P ITE EA LAUD PRS Md lap UL G 163 em bai cieli EET 164 9 22 COMPEX Break DOU tior sott eant cies etie edema ruere dh A epa eat meee 164 92 9 Conditions tor Matching BEeaRDOIUIS s usi orate oL eaa A EEN oder RD DEM EUE 165 8 2 4 Debug Exceptions from Breakpoints esses nennen nnne nennen nenas 168 9 2 5 Breakpoint Used as TOGO 3 cire icio an ca Phe Rec Heat rI nigel acta ade 169 9 2 6 Instr ction Breakpoint PIegISTOES secreta dear facet tiet deviant rap ete accidet tUe nea brad er pug Leeds 170 9 2 7 Data Breakpoint BBOISIBES usce etri Soter irgend bescb eate a xU bd Mx be N 175 8 2 8 Complex Breakpoint Registers ssssssssssssseeseee een nennen ennt nnne nennen estrena 182 8 3 Complex Breakpoint Usage odisea ie peo a else a eben ue oda dores 186 8 3 1 Checking for Presence of Complex Break Support 186 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 5 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 9 2 General Complex Break Behavior rostmi ana g n i araara n 187 8 3 39 Usage ol Pass COUMICIS pinoa E E dwn dfdn ut 188 8 3 4 Usage or Tuple Breakpolris 5 ret t et tp e ENAERE NARRANTE EAA E RREAK ERREARI 188 9 3 5 Usage Ol Priming Condo MS sssr sh soudeatebsadniaiin bocaioeepeacececgua pAsiesiese 188 8 9 6 Usage of Data Qualified Breakpolnis eeciie orent t ied iadaaa ernaia 189 8 3 7 Usage Of StopWatch TIMES issin tos peruise
173. a very frequent instruction It therefore supports full 5 bit unrestricted register fields for maximum effi ciency In fact MOVE used to be a simplified macro of an existing MIPS32 instruction There are 2 variants of the LW and SW instructions One variant implicitly uses the SP register to allow for a larger offset field The value in the offset field is shifted left by 2 before it is added to the base address There are four variants of the ADDIU instruction 1 A variant with one 5 bit register specifier that allows any GPR to be the source and destination register 2 A variant that uses the stack pointer as the implicit source and destination register 3 A variant that has separate 3 bit source and destination register specifiers 4 A variant that has the stack pointer as the implicit source register and one 3 bit destination register specifier A 16 bit NOP instruction is needed because of the new 16 bit instruction alignment and the need in specific cases to align instructions on a 32 bit boundary It can save code size as well NOP is not shown in the table because it is real ized as a macro as is NEGU NOP16 MOVE16 r0 r0 NEGU16 rt rs SUBU16 rt r0 rs Because microMIPS instructions are 16 bit aligned the 16 bit branch instructions support 16 bit aligned branch tar get addresses The offset field is left shifted by 1 before it is added to the PC MIPS32 M14K Processor Core Software User s Manual Revision 02 03
174. able 5 5 BaaVAdar Register Field DescrpliOn acsi p Ince nce e ene praedec eaux iu e acd e eoa aec eder anand 99 Table 5 6 Count Register Field DSc rip teins uoc satis cats sa tatit toss ute hacked drca eti tee tease EREA 99 Table 5 7 Compare Register Field DescrlptiOni uccoo iacob euet As 100 Table 5 9 Status Register Field IDesScfIplOris uocare rixae breiter rio ba pera tt n Fe rat pese rx n neces Taea 101 Table 5 9 IntCil Register Field IDescriptlOlis s2 oic fiori dnce cetera dese a een alannerecs 105 Table 5 10 SRSCil Register Field Descriptions seie iniaa aiea tende scc t tae at agate 109 Table 5 11 Sources for new SRSCtlcss on an Exeephon or Interfupl usuasseo acc pecie kia last esie ilia 111 Table 5 12 SRSMap Register Field DescriplHOfiS iano cet eter rre porn erae rata pere paese RE pe nde ekhad 111 Table 5 13 View IPL Register Field Descriptions icon uino qup ccs ertet epe od eU I ness cn ads cross dera din uper 112 Table 5 14 SRSMap Register Field Descriptions sssssssssssssssseeeeeenee eene nnn nnns 113 Table 5 15 Cause Register Fjeld Descriptions s cci o ettari ara ette tex tton sansa E ke be Ras kxp co ep Pu SER Desa SR a EROS 113 Table 5 16 Cause Register ExcCode Field nennen nnne nnne nnns nennen 117 Table 5 17 View RIPL Register Field Descriptions 5 sinat acea oett dac tn dad bereit semet disse uds 118 Table 5 18 NestedExc Register Field Descriptions ionic ioca E tei E irai eos or AKANE
175. access Bus error exceptions that occur on an instruction fetch have a higher priority than bus error exceptions that occur on a data access Bus errors taken on any external access on the M14K core are always precise Cause Register ExcCode Value IBE Error on an instruction reference MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 8 Exception Descriptions DBE Error on a data reference Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 8 10 Protection Exception The protection exception occurs when an access to memory that has been protected by the Memory Protection Unit has been attempted Or under certain circumstances attempted write to the EBase register See the Security Features of the M14K Processor Family MD00896 for more information Register ExcCode Value Prot Cause Code 29 Additional State Saved MPU Config Register Triggered Field MPU StatusN Register Cause Fields Entry Vector Used General exception vector offset 0x180 4 8 11 Debug Software Breakpoint Exception A debug software breakpoint exception occurs when an SDBBP instruction is executed The DEPC register and DBD bit in the Debug register will indicate the SDBBP instruction that caused the debug exception Debug Register Debug Status Bit Set DBp Additional State Saved None Entry Vector Used
176. ace The EJTAG Control register is not updated in the Update DR state unless the Reset occurred Rocc bit 31 is either 0 or written to 0 This is in order to ensure prober handling of processor accesses The value used for reset indicated in the table below takes effect on both hard and soft CPU resets but not on TAP controller resets by e g TRST_N TCK clock is not required when the hard or soft CPU reset occurs but the bits are still updated to the reset value when the TCK applies The first 5 TCK clocks after hard or soft CPU resets may result in reset of the bits due to synchronization between clock domains Figure 8 27 EJTAG Control Register Format 31 30 29 28 23 22 21 20 19 18 17 16 15 14 13 12 11 4 3 20 Prob Ejtag Rocc Psz Res Doze Halt PerRst PRnW PrAcc Res PrRst ProbEn Trap Res Brk Res DM Rs 200 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Table 8 31 EJTAG Control Register Descriptions 8 5 EJTAG TAP Registers Fields Name Bit s Description Read Write Reset State Rocc Psz 1 0 The bit indicates if a CPU reset has occurred Encoding Meaning 0 No reset occurred since bit last cleared 1 Reset occurred since bit last cleared The Hocc bit will keep the 1 value as long as reset is applied This bit must be cleared by the probe to acknowledge that the i
177. akpoint registers 0x1128 0x100 n IBPCn Instruction Breakpoint Pass Counter n described above with instruction breakpoint registers 0x2128 0x100 n DBCCn Data Breakpoint Complex Control n described above with data breakpoint registers 0x2130 0x100 n DBPCn Data Breakpoint Pass Counter n described above with data breakpoint registers 0x8000 CBTControl Complex Break and Triggerpoint Control indicates which of the complex breakpoint features are implemented 0x8300 0x20 n PrCndAln Prime Condition Register A for Instruction breakpoint n 0x84e0 0x20 n PrCndADn Prime Condition Register A for Data breakpoint n 0x8900 STCtl Stopwatch Timer Control 0x8908 STCnt Stopwatch Timer Count n is breakpoint number from 0 to 7 range dependent on implemented hardware 8 2 8 1 Complex Break and Trigger Control CBTC Register 0x8000 Compliance Level Implemented only if complex breakpoints are implemented The CBTC register contains configuration bits that indicate which features of complex break are implemented as well as a control bit for the stopwatch timer On an M14K core if complex break is implemented all of the separate fea tures will be present Figure 8 18 CBTC Register Format 9 8 7 5 4 3 2 1 0 I Ema ver eroe pe ee Table 8 21 CBTC Register Field Descriptions 31 Description Read Write Reset eect eter ELM X 9 7 5 Reserved 182 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copy
178. al description is shown in Table 8 22 The actual priming conditions for each of the breakpoints are shown in Table 8 23 31 Figure 8 19 PrCndA Register Format 24 23 16 15 Cond3 Cond2 Cond1 CondO MIPS32 M14K Processor Core Software User s Manual Revision 02 03 183 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Table 8 22 PrCndA Register Field Descriptions Fields Read Wr Name Bit s Description ite Reset State CondN 31 24 Specifies which triggerpoint is connected to priming R Preset 23 16 condition 3 2 1 or 0 for the current breakpoint 15 8 7 0 31 30 Reserved R 0 23 22 15 14 7 6 29 28 Trigger type R Preset 21 20 00 Special Bypass 13 12 01 Instruction 5 4 10 Data 11 Reserved 27 24 Break Number 0 14 R Preset 19 16 11 8 3 0 a Condition 0 is always Bypass and will read as 8 bO Table 8 23 Priming Conditions and Register Values for 61 2D Configuration Break Condo Cond1 Cond2 Cond3 PrCndA Value sia InstO Bypass Data Insti Inst2 Ox1211 2000 0x8300 Insti Bypass Data0 InstO Inst2 0x1210 2000 0x8320 Inst2 Bypass Data InstO 0x8340 Inst3 Bypass Datal Inst4 Inst5 0x1514 2100 0x8360 Inst4 Bypass Datal Inst3 Inst5 0x1513 2100 0x8380 Inst5 Bypass Datal Inst3 0x83a0 Data0 Bypass InstO Insti Inst2 Ox1211 1000 0x84e0 Datal Bypass Inst3 Inst4 Inst5 0x1514 1300 0x8500
179. al interrupt controller Instruction hazards are those created by the execution of one instruction and seen by the instruction fetch of another instruction Table 2 7 lists instruction hazards Table 2 7 Instruction Hazards Spacing Producer gt Consumer Hazard On Instructions gt Instruction fetch seeing the new value including a change to ERL fol Status lowed by an instruction fetch from the useg segment Instruction stream gt Instruction fetch seeing the new instruction stream Cache entries write via redi rected store 48 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 2 11 Hazards 2 11 2 Instruction Listing Table 2 8 lists the instructions designed to eliminate hazards See the document titled MIPS32 Architecture for Pro grammers Volume II The MIPS32 Instruction Set MD00086 for a more detailed description of these instructions Table 2 8 Hazard Instruction Listing Mnemonic Function EHB Clear execution hazard JALR HB Clear both execution and instruction hazards JR HB Clear both execution and instruction hazards SYNCI Synchronize caches after instruction stream write 2 11 2 1 Instruction Encoding The EHB instruction is encoded using a variant of the NOP SSNOP encoding This encoding was chosen for compat ibility with the Release 1 SSNOP instruction such that existing s
180. an instruction or data breakpoint is used as a so called triggerpoint The triggerpoints are like breakpoints only compared for instructions executed in non debug mode The BS n bit in the BS or DBS register is set when the respective B match or DB match bit is true The triggerpoint feature can be used to start and stop tracing MIPS32 M14K Processor Core Software User s Manual Revision 02 03 169 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core 8 2 6 Instruction Breakpoint Registers The registers for instruction breakpoints are described below These registers have implementation information and are used to set up the instruction breakpoints All registers are in drseg and the addresses are shown in Table 8 2 Table 8 2 Addresses for Instruction Breakpoint Registers Register Offset in drseg Mnemonic Register Name and Description 0x1000 IBS Instruction Breakpoint Status 0x1100 n 0x100 IBAn Instruction Breakpoint Address n 0x1108 n 0x100 IBMn Instruction Breakpoint Address Mask n Ox1110 n 0x100 IBASIDn Instruction Breakpoint ASID n Ox1118 n 0x100 IBCn Instruction Breakpoint Control n 0x1120 n 0x100 IBCCn Instruction Breakpoint Complex Control n 0x1128 n 0x100 IBPCn Instruction Breakpoint Pass Counter n n is breakpoint number in range 0 to 5 or 3 or 1 depending on the implemented hardware An example of some o
181. and E pipeline stages At the end of the E stage in cycle 2 the MDU pipeline starts processing the multiply operation Mult 3 In cycle 3 a 32x32 multiply operation Mult enters the I stage and is fetched from the instruction cache Since the Add operation has not yet reached the M stage by cycle 3 there is no activity in the M stage of the integer pipeline at this time 4 Incycle4 the Subtract instruction enters I stage The second multiply operation Mult enters the E stage And the Add operation enters M stage of the integer pipe Since the Mult multiply is a 32x16 operation only one clock is required for the Mypy stage hence the Mult operation passes to the Ay stage of the MDU pipeline 5 In cycle 5 the Subtract instruction enters E stage The Mult multiply enters the Mypy stage The Add operation enters the A stage of the integer pipeline The Mult operation completes and is written back in to the HI LO reg ister pair in the Wyqpy stage 6 Since a 32x32 multiply requires two passes through the multiplier with each pass requiring one clock the 32x32 Mult remains in the Myqpy stage in cycle 6 The Sub instruction enters M stage in the integer pipeline The Add operation completes and is written to the register file in the W stage of the integer pipeline 7 The Mult multiply operation progresses to the Ampu stage and the Sub instruction progress to the A stage 8 The Mult operation completes and is written to the HI L
182. as been fully initialize Statusggy 1 Privileged software may switch the current shadow set by writing a new value into SHSCtlpss loading EPC with a target address and doing an ERET 4 5 Exception Vector Locations The Reset Soft Reset and NMI exceptions are always vectored to location 16 BFC0 0000 EJTAG Debug excep tions are vectored to location 16 BFCO0 0480 or to location 16 FF20 0200 if the ProbTrap bit is zero or one respec tively in the EJTAG_Control_register Addresses for all other exceptions are a combination of a vector offset and a vector base address In Release 1 of the architecture the vector base address was fixed In Release 2 of the architec ture software is allowed to specify the vector base address via the EBase register for exceptions that occur when Statusggy equals 0 Table 4 5 gives the vector base address as a function of the exception and whether the BEV bit is set in the Status register Table 4 6 gives the offsets from the vector base address as a function of the exception Note that the V bit in the Cause register causes Interrupts to use a dedicated exception vector offset rather than the general exception vector For implementations of Release 2 of the Architecture Table 4 4 shows the offset from the base address in the case where StatuSggy 0 and Causey 1 For implementa tions of Release 1 of the architecture in which Cause y 1 the vector offset is as if ntCtiys were 0 Table 4 7 com bines these
183. ase offset lt temp Enable Interrupts The contents of the byte at the memory location specified by the effective address are fetched The specified bit within the byte is cleared to zero The modified byte is stored in memory at the location specified by the effective address The 12 bit signed offset is added to the contents of GPR base to form the effective address The read modify write sequence cannot be interrupted Transactions with locking semantics occur in some memory interconnects busses It is implementation specific whether this instruction uses such locking transactions Restrictions The operation of the processor is UNDEFINED if an ACLR instruction is executed in the delay slot of a branch or jump instruction Operation vAddr lt sign extend offset GPR base pAddr CCA AddressTranslation vAddr DATA STORE pAddr pAddrpgrzn 1 2 pAddr 9 xor ReverseEndian TempIE lt Statusir Statusr g amp 0 memword lt LoadMemory CCA BYTE pAddr vAddr DATA byte lt vAddr xor BigEndianC PU temp memwordz s pyte 8 byte temp lt temp and 1 0P xor OxFF dataword temp o8 byte StoreMemory CCA BYTE dataword pAddr vAddr DATA Statusyp lt TempIE Exceptions TLB Refill TLB Invalid TLB Modified Address Error Watch Programming Notes Upon a TLB miss a TLBS exception is signalled in the ExcCode field of the Cause register For address erro
184. at a Config5 register is Required present With the current architectural definition this bit should always read as a 0 Must be written as zeros returns zeros on read Reserved Indicates that the Nested Fault feature is present Required The Nested Fault feature allows recognition of faulting behavior within an exception handler 5 2 26 Config7 Register CPO Register 16 Select 7 The Config7 register contains implementation specific configuration information A number of these bits are write able to disable certain performance enhancing features within the M14K core Figure 5 27 Config Register Format 31 30 19 18 17 0 WII 0 HCI 0 132 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 30 Config7 Register Field Descriptions Fields Description Reset State Wait IE Ignore Indicates that this processor will allow an interrupt 1 to unblock a WAIT instruction even if E is preventing the interrupt from being taken This avoids problems using the WAIT instruction for bottom half interrupt servicing In WII mode when E 0 waking up from Sleep mode will not enter an Interrupt Service Routine 30 19 17 0 These bits are unused and should be written as 0 18 Hardware Cache Initialization Indicates that a cache does not require initialization by so
185. at may occur in debug mode Value is undefined after a debug exception Undefined MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 135 CPO Registers of the M14K Core Table 5 31 Debug Register Field Descriptions Continued Fields Name Bit s Description Read Write Reset State NoSST 9 Indicates whether the single step feature controllable by R 0 the SSt bit is available in this implementation Encoding Meaning 0 Single step feature available 1 No single step feature available SSt 8 Controls if debug single step exception is enabled R W 0 Encoding Meaning 0 No debug single step exception enabled 1 Debug single step exception enabled R 7 Reserved Must be written as zeros returns zeros on R 0 reads DIBImpr 6 Indicates that an Imprecise debug instruction break R Undefined exception occurred due to a complex breakpoint Cleared on exception in debug mode DINT 5 Indicates that a debug interrupt exception occurred R Undefined Cleared on exception in debug mode Encoding Meaning 0 No debug interrupt exception 1 Debug interrupt exception DIB 4 Indicates that a debug instruction break exception R Undefined occurred Cleared on exception in debug mode Encodi
186. ata Bypassing e Section 2 8 Interlock Handling e Section 2 9 Slip Conditions Section 2 10 Instruction Interlocks e Section 2 11 Hazards 2 1 Pipeline Stages The pipeline consists of five stages e Instruction I stage Execution E stage e Memory M stage Align A stage Writeback W stage The M14K core implements a Bypass mechanism that allows the result of an operation to be sent directly to the instruction that needs it without having to write the result to the register and then read it back The M14K soft core includes a build time option that determines the type of multiply divide unit MDU imple mented The MDU can be either a high performance array or an iterative area efficient array The MDU choice has a MIPS32 M14K Processor Core Software User s Manual Revision 02 03 31 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Pipeline of the M14K Core significant effect on the MDU pipeline and the latency of multiply divide instructions executed on the core Software can query the type of MDU present on a specific implementation of the core by querying the MDU bit in the Config register CPO register 16 select 0 see Chapter 5 CPO Registers of the M14K Core on page 95 for more details Figure 2 1 shows the operations performed in each pipeline stage of the M14K processor core when the high perfor mance multiplier is present Figure 2 1 M14
187. bilities All fields in the Config3 register are read only Figure 5 24 shows the format of the Config3 register Table 5 27 describes the Config3 register fields Figure 5 24 Config3 Register Format 31 30 23 22 21 20 18 17 16 15 14 13 12 11 9 8 7 6 5 4 3 2 1 0 ISA M M CD M 000000000 IPLW MMAR MCU On ISA ULRI RXT 0 ITL LPA Inm SP M 0 ISMI TL Exc Ct M Table 5 27 Config3 Register Field Descriptions Fields Name Bits Description Read Write Reset State M 31 This bit is reserved to indicate that a Config4 register is present R 1 0 30 23 11 9 2 Must be written as zeros returns zeros on read 0 0 IPLW 22 21 Width of the Status p and Causegjp fields R Preset Encoding Meaning 0 IPL and RIPL fields are 6 bits in width 1 IPL and RIPL fields are 8 bits in width Others Reserved If the PL field is 8 bits in width bits 18 and 16 of Status are used as the most significant bit and second most significant bit respectively of that field If the R PL field is 8 bits in width bits 17 and 16 of Cause are used as the most significant bit and second most significant bit respectively of that field MMAR 20 18 microMIPS Architecture revision level R Preset Encoding Meaning 0 Release 1 1 7 Reserved MCU 17 MIPS MCU ASE implemented R Preset Encoding Meaning 0 MCU ASE is not implemente
188. bits of the current program counter to form an absolute address Returns dispatches and large cross page jumps are usually implemented with the Jump Register or Jump and Link Register instructions Both are R type instructions that take the 32 bit byte address contained in one of the general purpose registers For more information about jump instructions refer to the individual instructions in Chapter 10 M14K Processor Core Instructions on page 239 9 4 2 Overview of Branch Instructions All branch instruction target addresses are computed by adding the address of the instruction in the delay slot to the 16 bit offset shifted left 2 bits and sign extended to 32 bits All branches occur with a delay of one instruction If a conditional branch likely is not taken the instruction in the delay slot is nullified Branches jumps ERET and DERET instructions should not be placed in the delay slot of a branch or jump 9 5 Control Instructions Control instructions allow the software to initiate traps they are always R type 9 6 Coprocessor Instructions CPO instructions perform operations on the System Control Coprocessor registers to manipulate the memory manage ment and exception handling facilities of the processor Refer to Chapter 10 M14K Processor Core Instructions on page 239 for a listing of CPO instructions 9 7 Enhancements to the MIPS Architecture The core execution unit implements the MIPS32 architecture which
189. ble 4 4 shows the exception vector offset for a representative subset of the vector numbers and values of the ntCtlVS field Table 4 4 Exception Vector Offsets for Vectored Interrupts Value of IntCtl Field Vector Number 2400001 2400010 2400100 2401000 2110000 0 1650200 1650200 1650200 1650200 1650200 1 16 0220 16 0240 16 0280 16 0300 16 0400 2 16 0240 16 0280 16 0300 16 0400 16 0600 3 16 0260 16 02CO 16 0380 16 0500 16 0800 4 16 0280 16 0300 16 0400 16 0600 16 0A00 5 16 02A0 16 0340 16 0480 16 0700 16 0C00 6 16 02C0 16 0380 16 0500 16 0800 16 0E00 7 16 02E0 16 03CO 16 0580 16 0900 16 1000 e 61 16 09A0 16 1140 16 2080 16 3F00 16 7C00 62 16 09CO 16 1180 16 2100 16 4000 16 7E00 63 16 09E0 16 11C0 16 2180 16 4100 16 8000 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 3 Interrupts The general equation for the exception vector offset for a vectored interrupt is vectorOffset lt 164200 vectorNumber x IntCtlyg 2 00000 When using large vector spacing and EIC mode the offset value can overlap with bits that are specified in the EBase register Software must ensure that any overlapping bits are specified as 0 in EBase This implementation ORs together the offset and base registers but it is architecturally undefined and software should not rely on this behavior
190. block Mnemonic Register Name and Description 0x0 FDACSR FDC Access Control and Status Register 0x8 FDCFG FDC Configuration Register 0x10 FDSTAT FDC Status Register 0x18 FDRX FDC Receive Register 0x20 0x8 n FDTXn FDC Transmit Register n 0 lt n lt 15 8 10 6 1 FDC Access Control and Status FDACSR Register Offset 0x0 This is the general CDMM Access Control and Status register which defines the device type and size and controls user and supervisor access to the remaining FDC registers The Access Control and Status register itself is only acces sible in kernel mode Figure 8 38 has the format of an Access Control and Status register shown as a 64 bit register and Table 8 44 describes the register fields Figure 8 38 FDC Access Control and Status Register 63 32 31 24 23 22 21 16 15 12 11 4 3 2 1 0 0 DevID 0 DevSize DevRev 0 Uw Ur Sw Sr Table 8 44 FDC Access Control and Status Register Field Descriptions Fields Name Bits Description DevType 31 24 This field specifies the type of device DevSize 21 16 This field specifies the number of extra 64 byte blocks allocated to this device The value 0x2 indicates that this device uses 2 extra or 3 total blocks DevRev 15 12 This field specifies the revision number of the device The R 0x0 value 0x0 indicates that this is the initial version of FDC 228 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copy
191. c IP4 BM4 gt I Ea HWI IP3 W IM3 L 3 HWO IP2 391NM2 M S IP1 JMIMI IPO IMO Causey SRSMap Shadow Set Number A typical software handler for vectored interrupt mode bypasses the entire sequence of code following the IV excep tion label shown for the compatibility mode handler above Instead the hardware performs the prioritization dis patching directly to the interrupt processing routine Unlike the compatibility mode examples a vectored interrupt handler may take advantage of a dedicated GPR shadow set to avoid saving any registers As such the Simple Inter rupt code shown above need not save the GPRs A nested interrupt is similar to that shown for compatibility mode but may also take advantage of running the nested exception routine in the GPR shadow set dedicated to the interrupt or in another shadow set Such a routine might look as follows Nes F F o tedException Nested exceptions typically require saving the EPC Status and SRSCtl registers setting up the appropriate GPR shadow set for the routine disabling the appropriate IM bits in Status to prevent an interrupt loop putting the processor in kernel mode and re enabling interrupts The sample code below can not cover all nuances of this processing and is intended only to demonstrate the concepts Use the current GPR shadow set and setup software context mfcO k0 CO EPC
192. c All rights reserved Table of Contents Chapter 1 Introduction to the MIPS32 amp M14K Processor Core ss ssccceccsssssesseeneeeeseseeeeseeeees 15 VR IU EE 15 k2 MIAK M Gore Block Dia Ghali serieen e O stances 19 Let hequiredbogie BIOGKS 5 5 nda Eon abet edu A a 20 1 2 2 Optonaldogic BIOGKS cites docent pesce erii Ebr kx t rei Ex peor aae 24 Ghapter 2 Pipeline or the M14K Cie iecore na tutta pince tuo pru Ru Ru Dun saa ruere rara cha te onines sehn 31 PX e iln selzie weee E a O E E A E E TE 31 Ze ltd Stage Instr ctiot Felge toiles eee eec pem E EA R pend sanc up bx tide 32 2 2 E Staget EXOCUBOTTs nino dpoxsutiseo tastes Li ix uupi tots aa AE Aa aia aiiai 33 v ouv bsiersuiea 2omet m E 33 VEU Ie RE cere 6 9 c9 NER E E RET LISTS 33 zx ous Stage Wille DAK RR T EU 34 2 2 MU llply DiVide ODSEallOriB das os dicta de etd tete atr uen a Ese UT ETE EA di Hepat d uM AR tatiana On urea lRG 34 2 9 MDU Pipeline High Performance MIU iiiter rn dann eaten aden eR ID HN CAR ee E Reda 34 2 940 32x 16 Multiply High Penormance MDU soit dedu ua te tuner et densities Sgt ederet cea 37 2 3 2 92x32 Multiply High Pertormance MEDI uicta io pae E Dered ed tnc testa tede 37 2 3 3 Divide High Performance MDU ssssssssssssssesesee eene nnne nennen rentrer nennen nennen nnn ens 38 2 4 MDU Pipeline Area Efficient MDU 3 eeepc i ese itai eic edenda aieo ete ala iie o Sidus 39 2 41 Multiply Area Enictont MIU i
193. cJTAG 4 wire 2 wire interface interface TDI Tap TDO cJTAG TMSC Controller TCK AdapterIP TCK TMS Block 232 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 9 Instruction Set Overview This chapter provides a general overview on the three CPU instruction set formats of the MIPS architecture Immedi ate Jump and Register Refer to Chapter 10 M14K Processor Core Instructions on page 239 for a complete list ing and description of instructions This chapter discusses the following topics e Section 9 1 CPU Instruction Formats e Section 9 2 Load and Store Instructions e Section 9 3 Computational Instructions e Section 9 4 Jump and Branch Instructions e Section 9 5 Control Instructions e Section 9 6 Coprocessor Instructions e Section 9 7 Enhancements to the MIPS Architecture Section 9 8 MCU ASE Instructions 9 1 CPU Instruction Formats Each CPU instruction consists of a single 32 bit word aligned on a word boundary There are three instruction for mats immediate I type jump J type and register R type as shown in Figure 9 1 The use of a small number of instruction formats simplifies instruction decoding allowing the compiler to synthesize more complicated and less frequently used operations and addressing modes from these three formats as needed MIPS32 M14K
194. cally set that is the read modify byte write sequence performed by this instruction cannot be interrupted 9 8 3 IRET This instruction can be used as a replacement for the ERET instruction when returning from an interrupt This instruction implements the Automated Interrupt Epilogue feature which automates restoring some of the COPO reg isters from the stack and updating the CO_Status register in preparation for returning to non exception mode This instruction also implements the optional Interrupt Chaining feature which allows a subsequent interrupt to be han dled without returning to non exception mode 238 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 10 M14K Processor Core Instructions This chapter supplements the MIPS32 Architecture Reference Manual by describing instruction behavior that is spe cific to a MIPS32 M14K processor core The chapter is divided into the following sections e Section 10 1 Understanding the Instruction Descriptions e Section 10 2 M14K Opcode Map e Section 10 3 MIPS32 Instruction Set for the M14K core The M14K processor core also supports the microMIPS extension to the MIPS32 architecture The microMIPS instruction set is described in Chapter 11 microMIPS Instruction Set Architecture on page 275 10 1 Understanding the Instruction Descriptions Refer to Volume II of
195. ccr Ri cu USE 221 PGSAMPLE TAP Register Format MIPS32 1 2 2 acetate retta ser estan i Seu eR RES ES QURE 223 Fast Debug Chamel Buiter Organizatloll nre exeo ENN 226 EDO TAP REISE ROMano taber tutu sace kia a uva iba n aeaa aa 227 FDG Access Gontrol and Status Register a ipe racines diae sam a e E dasp e dig N EM MONEO 228 FDG Contiguration Registe niesieni e eerste A ae aah N NE 229 FDC Status REOSE ika RE 230 FDC Receive dj Ern 231 FDC hransmlit Register cc bores terae aa a ER 231 eye teers a E O S 232 a pra sc E E E E E E E TT 234 16 Bit IMStHUCH OM FONTANE ects s esecevsperccecensenaceetsnpaneceetsbstadecees saucuactinpessccedshsndcutdannanctectaneneeccestaemcectcieas 279 oe lt MSUUCHOM Felfialsssosuss postes Gta tQut ums tndec et strat idt amd ieu abc i ento lt bx da M ee a RR IQ 280 Immediate Fields within 32 BIt Instr ctloris a siat iei p niae Erreichen roseis 280 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved List of Tables Table 2 1 MDU Instruction Latencies High Performance MDU cccccceseseeeeeeeeeeeeaeeeeeeeeeeeaeseeeeeeesaeeteeaeeeeaas 35 Table 2 2 MDU Instruction Repeat Rates High Performance MDU cccccceeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeeaeeeeeeeeeeas 36 Table 2 3 M14K Core Instruction Latencies Area Efficient MDU ccsceeeceeeeeeeeeeeeeeeeeeaeeeeeeeeesaeeseeeeeeeas 39 Table 2 4
196. ccurs while the core is in a low power state Setting the RP bit of the CPO Status register causes the core to assert the S FP signal The external agent can then decide whether to reduce the clock frequency and place the core into power down mode If an interrupt is taken while the device is in power down mode that interrupt may need to be serviced depending on the needs of the application The interrupt causes an exception which in turn causes the EXL bit to be set The setting of the EXL bit causes the assertion of the S EXL signal on the external bus indicating to the external agent that an interrupt has occurred At this time the external agent can choose to either speed up the clocks and service the inter rupt or let it be serviced at the lower clock speed The setting of the ERL bit causes the assertion of the S _EAL signal on the external bus indicating to the external agent that an error has occurred At this time the external agent can choose to either speed up the clocks and service the error or let it be serviced at the lower clock speed Similarly the EJ DebugM signal indicates that the processor is in debug mode Debug mode is entered when the processor takes a debug exception If fast handling of this is desired the external agent can speed up the clocks The core provides four power down signals that are part of the system interface Three of the pins change state as the corresponding bits in the CPO Status register are set
197. cessor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Table 5 15 Cause Register Field Descriptions Continued 5 2 CPO Register Descriptions Fields Name Bits Description Read Write Reset State AP 24 Indicates whether an exception occurred during Inter rupt Auto Prologue Encoding Meaning 0 Exception did not occur during Auto Prologue operation 1 Exception occurred during Auto Pro logue operation R Undefined IV WP 23 22 Indicates whether an interrupt exception uses the gen eral exception vector or a special interrupt vector Encoding Meaning 0 Use the general exception vector 16 180 1 Use the special interrupt vector 16 200 In implementations of Release 2 of the architecture if the Causeyy is 1 and Statusppy is 0 the special inter rupt vector represents the base of the vectored interrupt table Indicates that a watch exception was deferred because StatuSgx or StatuSgpy were a one at the time the watch exception was detected This bit both indicates that the watch exception was deferred and causes the exception to be initiated once Sfatusgy and Statusgg are both zero As such software must clear this bit as part of the watch exception handler to prevent a watch exception loop Software should not write a 1 to this bit when its value is a
198. cessor will start fetching instructions from address 0xFF20 0200 A pending processor access can only finish if the probe writes 0 to PrAcc or by a soft or hard reset 8 6 1 Fetch Load and Store from to EJTAG Probe Through dmseg 1 The internal hardware latches the requested address into the PA Address register in case of the Debug excep tion OXFF20 0200 2 The internal hardware sets the following bits in the EJTAG Control register PrAcc 1 selects Processor Access operation PHnW 0 selects processor read operation Psz 1 0 value depending on the transfer size 3 The EJTAG Probe selects the EJTAG Control register shifts out this control register s data and tests the PrAcc status bit Processor Access when the PrAcc bit is found 1 it means that the requested address is available and can be shifted out 4 The EJTAG Probe checks the PRnW bit to determine the required access 5 The EJTAG Probe selects the PA Address register and shifts out the requested address 6 The EJTAG Probe selects the PA Data register and shifts in the instruction corresponding to this address 7 The EJTAG Probe selects the EJTAG Control register and shifts a PrAcc 0 bit into this register to indicate to the processor that the instruction is available 8 The instruction becomes available in the instruction register and the processor starts executing 9 The processor increments the program counter and outputs an instruction read request for the n
199. cessors support two types of hardware interlocks e Stalls which are resolved by halting the pipeline e Slips which allow one part of the pipeline to advance while another part of the pipeline is held static In the M14K processor core all interlocks are handled as slips 2 9 Slip Conditions On every clock internal logic determines whether each pipe stage is allowed to advance These slip conditions prop agate backwards down the pipe For example if the M stage does not advance neither does the E or I stage Slipped instructions are retried on subsequent cycles until they issue The back end of the pipeline advances normally during slips This resolves the conflict when the slip was caused by a missing result NOPs are inserted into the bub ble in the pipeline Figure 2 19 shows an instruction cache miss that causes a two cycle slip Figure 2 19 Instruction Cache Miss Slip Clock 1 2 3 4 5 6 Stage lu 4 e iso E I hil ly l4 I M ILI mul A i35 a ae lofo qd Cache miss detected Q Critical word received Q Execute E stage In the first clock cycle in Figure 2 19 the pipeline is full and the cache miss is detected Instruction Ip is in the A stage instruction I is in the M stage instruction I is in the E stage and instruction I is in the I stage The cache miss occurs in clock 2 when the I4 instruction fetch is attempted L advances to the E stage and waits for the instruc tion to be fetched from main memory
200. ctions to be issued every cycle while a 32 bit x 32 bit MAC instruction can be issued every other cycle The area efficient MDU option handles multiplies with a one bit per clock iterative algorithm The basic Enhanced JTAG EJTAG features provide CPU run control with stop single stepping and re start and with software breakpoints using the SDBBP instruction Additional EJTAG features such as instruction and data vir tual address hardware breakpoints complex hardware breakpoints connection to an external EJTAG probe through the Test Access Port TAP and PC Data tracing may be included as an option 1 1 Features e S stage pipeline e 32 bit Address and Data Paths MIPS32 M14K Processor Core Software User s Manual Revision 02 03 15 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Introduction to the MIPS32 amp M14K Processor Core MIPS32 Compatible Instruction Set Multiply Accumulate and Multiply Subtract Instructions MADD MADDU MSUB MSUBU Targeted Multiply Instruction MUL Zero One Detect Instructions CLZ CLO Wait Instruction WAIT Conditional Move Instructions MOVZ MOVN MIPS32 Enhanced Architecture Release 2 Features Vectored interrupts and support for external interrupt controller Programmable exception vector base Atomic interrupt enable disable GPR shadow registers one three seven or fifteen additional shadows can be optionally added to minimize latency for interr
201. d LW16 Load Immediate Load Word LWGP16 Load Word GP LWSP16 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Load Word SP 283 microMIPS Instruction Set Architecture Table 11 1 16 Bit Re encoding of Frequent MIPS32 Instructions Continued Number of Register Fields Immediate Field Size bit Register Field Width bit Total Size of Other Fields Empty 0 Field Size bit Minor Opcode Size bit Comment MFHI16 POOL16C MFLO16 POOL16C Move from HI Register Move from LO Register MOVEI6 MOVEI6 Move NOTI16 ORI6 POOL16C POOL16C NOT OR SB16 SB16 Store Byte SDBBP16 POOL16C SH16 Cause Debug Breakpoint Exception Store Halfword SH16 SLL16 POOL16B POOL16B Shift Word Left Logical Shift Word Right Logical SRL16 SUBU16 POOLI16A SW16 SW16 5bit 1 0 0 Sub Unsigned Store Word SWSP SWSP16 XORI6 POOL16C 11 3 1 2 Frequent MIPS32 Instruction Sequences 0 Store Word SP 0 These 16 bit instructions are equivalent to frequently used short sequences of MIPS32 instructions The instruc tion specific register and immediate value selection are shown in Table 11 3 Table 11 2 16 Bit Re encoding of Frequent MIPS32 Instruction Sequences Number of Register Fields Immediate Field Size R
202. d 1 MCU ASE is implemented 128 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 27 Config3 Register Field Descriptions Continued Fields Name Bits Description Read Write Reset State ISAOnExc 16 Reflects the Instruction Set Architecture used when vectoring to RW Preset driven an exception Affects exceptions whose vectors are offsets from by signal EBASE external to z CPU core Encoding Meaning 0 MIPS32 ISA is used on entrance to an exception vector 1 microMIPS is used on entrance to an exception vector ISA 15 14 Indicates Instruction Set Availability R Preset driven by signal i F to Encodin Meanin enema g g CPU core 0 Only MIPS32 is implemented 1 Only microMIPS is implemented 2 Both MIPS32 and MicroMIPS are implemented MIPS32 ISA used when coming out of reset 3 Both MIPS32 and MicroMIPS are implemented MicroMIPS is used when coming out of reset ULRI 13 UserLocal register implemented This bit indicates whether the R Preset UserLocal coprocessor 0 register is implemented Encoding Meaning 0 UserLocal register is not imple mented 1 UserLocal register is implemented RXI 12 Indicates whether the RIE and XIE bits exist within the R 0 PageGrain reg
203. d modify write instructions ASET and ACLR eases commonly used semaphore manipulation in microcontroller applications Interrupts are automatically disabled during the operation to maintain coherency e Memory Management Unit e Simple Fixed Mapping Translation FMT mechanism e Memory Protection Unit MPU e Optional feature that improves system security by restricting access execution and trace capabilities from untrusted code in predefined memory regions e Simple SRAM Style Interface e Cacheless operation enables deterministic response and reduces die size e 32 bit address and data input byte enables enable simple connection to narrower devices e Single or multi cycle latencies e Configuration option for dual or unified instruction data interfaces e Redirection mechanism on dual I D interfaces permits D side references to be handled by I side e Transactions can be aborted e Reference Design e A typical SRAM reference design is provided e An AHB Lite BIU reference design is provided between the SRAM interface and AHB Lite Bus e An optimized interface for slow memory Flash access using prefetch buffer scheme is provided e Parity Support e The I SRAM and D SRAM support optional parity detection e CorExtend User Defined Instruction Set Extensions e Allows user to define and add instructions to the core at build time e Maintains full MIPS32 compatibility e Supported by industry standard development tools e Single or multi cycle i
204. d or store instruction matches the instruction breakpoint and the data breakpoint of the result ing load or store address and optional data value matches e Priming This allows a breakpoint to be enabled only after other break conditions have been met Also called sequential or armed triggering e Qualified This feature uses a data breakpoint to qualify when an instruction breakpoint can be taken Once a load matches the data address and the data value the instruction break will be enabled If a load matches the address but has mis matching data the instruction break will be disabled Performance Counters Performance counters are used to accumulate occurrences of internal predefined events cycles conditions for pro gram analysis debug or profiling A few examples of event types are clock cycles instructions executed specific instruction types executed loads stores exceptions and cycles while the CPU is stalled There are two 32 bit counters Each can count one of the 64 internal predefined events selected by a corresponding control register A counter overflow can be programmed to generate an interrupt where the interrupt handler software can maintain larger total counts PC Address Sampling This sampling function is used for program profiling and hot spots analysis Instruction PC and or Load Store addresses can be sampled periodically The result is scanned out through the EJTAG port The Debug Control Regis ter DCR is use
205. d to specify the sample period and the sample trigger Fast Debug Channel FDC The M14K core includes optional FDC as a mechanism for high bandwidth data transfer between a debug host probe and a target FDC provides a FIFO buffering scheme to transfer data serially with low CPU overhead and minimized waiting time The data transfer occurs in the background and the target CPU can either choose to check the status of the transfer periodically or it can choose to be interrupted at the end of the transfer Figure 1 3 FDC Overview MIAK Probe EJTAG TAP FDC Receive from 32 FIFO TDI lt a _ _ _ fg jj Probe to Core FIP Transmit from 32 I TDO Core to Probe 7 F TMS Tap Controller 41 4 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 27 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Introduction to the MIPS32 6 M14K Processor Core 28 iFlowtrace The M14K core has an option for a simple trace mechanism called iFlowtrace This mechanism traces only the instruction PC not data addresses or values This simplification allows the trace block to be small and the trace com pression to be very efficient iFlowtrace memory can be configured as off chip on chip or both iFlowtrace also offers special event trace modes when normal tracing is disabled namely e Function Call
206. dicates the ratio between the trace clock and the core clock The Trace clock is always 1 2 of the trace port data rate hence the full speed ITCB out puts data at the CPU core clock rate but the trace clock is half that hence the 1 2 OfCIk value is the full speed and the 1 4 OfCIk ratio is half speed When a 64 bit trace word is ready to transmit the PIB reads it from the FIFO and begins sending it out on TR DATA It is sent in 4 bit increments starting at the LSBs In a valid trace word the 4 LSBs are never all zero so a probe lis tening on the TR DATA port can easily determine when the transmission begins and then count 15 additional cycles to collect the whole 64 bit word Between valid transmissions TR_DATA Is held at zero and TR CLK continues to run TR CLK runs continuously whenever a probe is connected An optional signal TR PROBE N may be pulled high when a probe is not connected and could be used to disable the off chip trace port If not present this signal must be tied low at the Probe Interface Block PIB input The following encoding is used for the 6 tag bits to tell the PIB receiver that a valid transmission is starting if srcount 0 EncodedSrCount 111010 58 else if srcount 16 EncodedSrCount 111011 59 else if srcount 32 EncodedSrCount 111100 60 else if srcount 48 EncodedSrCount 111101 61 else EncodedSrCount srcount 8 8 8 Breakpoint Based Enabling o
207. ds and downloads the processor will stall on accesses to the Fastdata area The PrAcc proces sor access pending bit will be 1 indicating the probe is required to complete the access Both upload and download accesses are attempted by shifting in a zero SPrAcc value to request access completion and shifting out SPrAcc to see if the attempt will be successful i e there was an access pending and a legal Fastdata area address was used Downloads will also shift in the data to be used to satisfy the load from dmseg s Fastdata area while uploads will shift out the data being stored to dmseg s Fastdata area As noted above two conditions must be true for the Fastdata access to succeed These are e PrAcc must be 1 i e there must be a pending processor access e The Fastdata operation must use a valid Fastdata area address in dmseg 0xFF20 0000 to OxFF20 000F Table 8 33 shows the values of the PrAcc and SPrAcc bits and the results of a Fastdata access Table 8 33 Operation of the FASTDATA access PrAccin Address the LSB PrAcc LSB Probe Match Conirol SPrAcc Action in the Changes Shifted Data Shifted Operation Check Register Shifted In Data Register To Out Out Download using Fails x X none unchanged 0 invalid FASTDATA Passes 1 1 none unchanged 1 invalid 1 0 write data 0 SPrAcc 1 valid previ ous data 0 X none unchanged 0 invalid Upload using Fails X X none unchanged 0 invalid FASTDATA Passes 1 1 none unchanged 1 inva
208. e This modes uses EJTAG data and instruction breakpoint hardware to enable a trace of PC values Instead of starting or stopping trace a triggerpoint will cause a single breakpoint match trace record This record indicates that there was a triggerpoint match the breakpoint ID of the matching breakpoint and the PC value of an instruction that matched the instruction of data breakpoint This mode can only be used when normal tracing mode is turned off This mode can MIPS32 M14K Processor Core Software User s Manual Revision 02 03 213 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core 214 not be used in conjunction with other special trace modes This mode is enabled or disabled via the BM field in the Control Status register see Section 8 8 6 ITCB Register Interface for Software Configurability The breakpoints used in this mode must have the TE bet set to enable the match condition Software should avoid setting up overlapping breakpoints The behavior when multiple matches occur on the same instruction is to report a BreakpointID of 7 Filtered Data Tracing Mode This mode uses EJTAG data breakpoint hardware to enable a trace of data values Rather than starting or stopping trace as in normal trace mode a data triggerpoint will cause a filtered data trace record This record indicates that there was a data triggerpoint match the breakpoint ID of the matching breakpoint
209. e In this case steps 2 and 3 are skipped e The exception is one that sets Sfatusgg Reset Soft Reset or NMI e The exception causes entry into EJTAG Debug Mode e Slatusggy 1 e S atusgy 1 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 5 Exception Vector Locations 2 SRSCtl ss is copied to SHSCtlpss 3 SRSCtlcss is updated from one of the following sources e The appropriate field of the SRSMap register based on IPL if the exception is an interrupt Causey 1 Config3ygyc 0 and Config3yy 1 These are the conditions for a vectored interrupt e The E CSS field of the SRSCtl register if the exception is an interrupt Causejy 1 and Config3yg c 1 These are the conditions for a vectored EIC interrupt e The ESS field of the SRSCt register in any other case This is the condition for a non interrupt exception or a non vectored interrupt Similarly the rules for updating the fields in the SRSCt register at the end of an exception or interrupt are as follows 1 No field in the SRSCtl register is updated if any of the following conditions is true In this case step 2 is skipped e A DERET is executed e An ERET is executed with Statusgg 1 2 SHSCllpss is copied to SRHSCtlcss These rules have the effect of preserving the SRSCt register in any case of a nested exception or one which occurs before the processor h
210. e FIFO Receive 37 Indicates to probe that the receive buffer is full and the R Buffer Full core will not accept the data being scanned in Analogous to ProbeDataAccept but opposite polarity Data Out 36 Indicates to probe that the core is sending new data from R Valid the transmit FIFO ChannelID 35 32 Channel number associated with the data being scanned in R W Undefined or out This field can be used to indicate the type of data that is being sent and allow independent communication channels Scanning in a value with ChannelID Oxd and Data In Valid 0 will generate a receive interrupt This can be used when the probe has completed sending data to the core MIPS32 M14K Processor Core Software User s Manual Revision 02 03 227 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Table 8 42 FDC TAP Register Field Descriptions Read Reset Description Write State R W Data value being scanned in or out Undefined 8 10 6 Fast Debug Channel Registers This section describes the Fast Debug Channel registers CPU access to FDC is via loads and stores to the FDC device in the Common Device Memory Map CDMM region These registers provide access control configuration and status information as well as access to the transmit and receive FIFOs The registers and their respective offsets are shown in Table 8 43 Table 8 43 FDC Register Mapping Offset in CDMM Register device
211. e M14K core and coprocessor 2 for all coprocessor 2 instruc tions MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 2 8 Interlock Handling Figure 2 18 Coprocessor 2 Interface Transactions One Cycle One Cycle One Cycle One Cycle One Cycle COP2 inst Capture Control amp FromData Core internal operations Fetch instrucion Get ToData from memory Decode and setup valid Core to CP 2 info Validate inst Instrucion ToData Complete CP 2 to Core info Control amp FromData CP2 internal Operations Capture ToData Complete instruction As can be seen in the Figure all control and data from the coprocessor must occur in the M stage If this is not the case the A stage will start slipping in the following cycle and thus stall the I E M and A stages but if all expected control and data is available in the M stage coprocessor 2 instructions can execute with no pipeline stalls The only exception to this is the Branch on Coprocessor conditions BC2 instruction All branch instructions including the regular BEQ BNE etc must be resolved in the E stage The M14K core does not have branch prediction logic and thus the target address must be available before the end of the E stage The BC2 instruction has to follow the same protocol as all other coprocessor 2
212. e Microcontroller Application Specific Extension MCUASE that provides enhanced interrupt delivery and interrupt latency reduction 4 3 1 Interrupt Modes The M14K core includes support for three interrupt modes as defined by Release 2 of the Architecture e Interrupt Compatibility mode in which the behavior of the M14K is identical to the behavior of a Release 1 implementations Vectored Interrupt VI mode which adds the ability to prioritize and vector interrupts to a handler dedicated to that interrupt and to assign a GPR shadow set for use during interrupt processing The presence of this mode is denoted by the Vint bit in the Config3 register Although this mode is architecturally optional it is always present on the M14K CoreType lc so the Vint bit will always read as a 1 e External Interrupt Controller EIC mode which redefines the way interrupts are handled to provide full support for an external interrupt controller that handles prioritization and vectoring of interrupts As with VI mode this mode is architecturally optional The presence of this mode is denoted by the VEIC bit in the Config3 register On the M14K CoreType lc the VEIC bit is set externally by the static input S _E CPresent to allow system logic to indicate the presence of an external interrupt controller Following reset the M14K processor defaults to Compatibility mode which is fully compatible with all implementa tions of Release 1 of the Architecture
213. e actual source of the interrupt if multiple interrupt requests are ORed together on a single IP line Once that task is performed the interrupt may be processed in one of two ways Completely at interrupt level e g a simply UART interrupt The SimpleInterrupt routine below is an example of this type By saving sufficient state and re enabling other interrupts In this case the software model determines which interrupts are disabled during the processing of this interrupt Typically this is either the single StatusIM bit that corresponds to the interrupt being processed or some collection of other Statusyy bits so that lower priority interrupts are also disabled The NestedInterrupt routine below is an example of this type SimpleInterrupt a Nes MIPS32 M14KT Process the device interrupt here and clear the interupt request at the device In order to do this some registers may need to be saved and restored The coprocessor 0 state is such that an ERET will simple return to the interrupted code eret Return to interrupted code tedException Nested exceptions typically require saving the EPC and Status registers any GPRs that may be modified by the nested exception routine disabling the appropriate IM bits in Status to prevent an interrupt loop putting the processor in kernel mode and re enabling interrupts The sample code below can not cover all nuances of this processin
214. e carry propagate add The actual register writeback is performed in the W stage high performance MDU option e A MUL operation makes the result available for writeback The actual register writeback is performed in the W stage e EJTAG complex break conditions are evaluated 2 1 5 W Stage Writeback During the Writeback stage e Forregister to register or load instructions the result is written back to the register file 2 2 Multiply Divide Operations The M14K core implement the standard MIPS II multiply and divide instructions Additionally several new instructions were standardized in the MIPS32 architecture for enhanced performance The targeted multiply instruction MUL specifies that multiply results be placed in the general purpose register file instead of the HI LO register pair By avoiding the explicit MFLO instruction required when using the LO register and by supporting multiple destination registers the throughput of multiply intensive operations is increased Four instructions multiply add MADD multiply add unsigned MADDU multiply subtract MSUB and multi ply subtract unsigned MSUBU are used to perform the multiply accumulate and multiply subtract operations The MADD MADDU instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers Similarly the MSUB MSUBU instruction multiplies two operands and then subtracts the product from the HI and LO register
215. e halfwords of 32 bit instructions This means that a 32 bit instruction is not treated as a Word data type instead the halfwords are treated in the same way as individual 16 bit instructions The halfword containing the major opcode is always the first in the sequence Example SRL r1 r1 7 binary opcode fields 000000 00001 00001 00111 00001 000000 hex representation 0021 3840 Address 3 4 272 tli v0 Little Endian Data 38 40 00 21 Address OM db 2 3 Big Endian Data 00 21 38 40 Instructions are placed in memory such that they are in order with respect to the address 11 3 microMIPS Re encoded Instructions This section lists all microMIPS re encoded instructions sorted into 16 bit and 32 bit categories In the 16 bit category e Frequent MIPS32 instructions and macros re encoded as 16 bit Register and immediate fields are reduced in size by using encodings of frequently occurring values In the 32 bit category e All MIPS32 instructions including all application specific extensions except MIPS16e re encoded MIPS32 MIPS 3D ASE MIPS DSP ASE MIPS MT ASE and SmartMIPS ASE e Opcode space for user defined instructions UDIs e New instructions designed primarily to reduce code size MIPS32 M14K Processor Core Software User s Manual Revision 02 03 281 Copyright 2009 2010 MIPS Technologies Inc All rights reserved microMIPS Instruction Set Architecture 282 To differentiate between 16 bit and
216. e in the Wypyg stage Figure 2 10 shows the latency for a multiply operation The repeat rate is 33 cycles as a second multiply can be in the first Mypu stage when the first multiply is in Aypyu stage Figure 2 10 M14K Area Efficient MDU Pipeline Flow During a Multiply Operation Clock 1 2 33 34 35 EStage Pl Mypu Stage P Auou Stage P Wupu Stage JE ee Ry T Add sub shift HI LO Write neo wa 2 4 2 Multiply Accumulate Area Efficient MDU Multiply accumulate operations use the same multiply machine as used for multiply only Two extra stages are needed to perform the addition subtraction The operations uses 34 cycles in Mypy stage to complete the multi ply accumulate The register writeback to HI and LO are done in the A stage Figure 2 11 shows the latency for a multiply accumulate operation The repeat rate is 35 cycles as a second multi ply accumulate can be in the E stage when the first multiply is in the last Mypy stage Figure 2 11 M14K Area Efficient MDU Pipeline Flow During a Multiply Accumulate Operation Clock 1 2 33 34 35 36 37 e EStage M Munu Stage lt Munu Stage lt Mupu Stage Ampu Stage Waipu Stage P gt LILI LI LI LI Ly Add Subtract Shift Accumulate LO Accumulate HI HI LO Write 40 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 2 5 Branch Delay
217. e is in power down mode In instruction controlled power down mode execution of the WAIT instruction is used to invoke low power mode Refer to Chapter 7 Power Management of the M14K Core on page 157 for more information on power manage ment 1 2 2 Optional Logic Blocks The core consists of the following optional logic blocks as shown in the block diagram in Figure 1 1 2 2 1 Reference Design The M14K core contains a reference design that shows a typical usage of the core with 24 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 1 2 M14K Core Block Diagram Dual I SRAM and D SRAM interface with fast memories i e SRAM for instruction and data storage e Optimized interface for slow memory i e Flash memory access by having a prefetch buffer and a wider Data Read bus i e IS RData 127 0 to speed up I Fetch performance e AHB lite bus interface to the system bus if the memory accesses are outside the memory map for the SRAM and Flash regions AHB Lite is a subset of the AHB bus protocol that supports a single bus master The interface shares the same 32 bit Read and Write address bus and has two unidirectional 32 bit buses for Read and Write data The reference design is optional and can be modified by the user to better fit the SOC design requirement Figure 1 2 Reference Design Block Diagram Prefetch 128 bit Int
218. e of some of the registers DBMO is at offset 0x2108 and DBV is at offset 0x2220 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 175 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core 8 2 7 1 Data Breakpoint Status DBS Register 0x2000 Compliance Level Implemented if data breakpoints are implemented The Data Breakpoint Status DBS register holds implementation and status information about the data breakpoints Figure 8 9 DBS Register Format 29 28 27 24 23 2 10 OCONEE g Table 8 11 DBS Register Field Descriptions Fields ea Read Wr Name Bit s Description ite Reset State Res 31 Must be written as zero returns zero on read R 0 ASID 30 Indicates that ASID compares are supported in data R 0 breakpoints 0 Not supported 1 Supported Res 29 28 Must be written as zero returns zero on read R 0 BCN 27 24 Number of data breakpoints implemented R 4 2 1 or 08 Res 23 4 Must be written as zero returns zero on read R 0 BS 3 0 Break status for breakpoint n is at BS n with n from 0 R WO Undefined to 1 The bit is set to 1 when the condition for the corre sponding breakpoint has matched a Based on actual hardware implemented b In case of only 1 data breakpoint bit 1 become reserved 8 2 7 2 Data Breakpoint Address n DBAn Register 0x2100 0x100 n Compliance Level Implemented only for implemented data br
219. e opera tions Fields are cleared by these operations Enables Auto Prologue feature Encoding Meaning 0 Auto Prologue disabled 1 Auto Prologue enabled MIPS32 M14K Processor Core Software User s Manual Revision 02 03 107 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core Table 5 9 IntCtl Register Field Descriptions Continued Fields Name Bits Description Read Write State UseKStk Chooses which Stack to use during Interrupt Automated Prologue Encoding Meaning 0 Copy 29 of the Previous SRS to the Current SRS at the beginning of IAP This is used for Bare Iron environ ments with only one stack Use 29 of the Current SRS at the beginning of IAP This is used for environments where there are separate User mode and Ker nel mode stacks In this case 29 of the SRS used during IAP must be pre initialized by software to hold the Kernel mode stack pointer 12 10 Must be written as zero returns zero on read po o Vector Spacing If vectored interrupts are implemented R W as denoted by Config3yyn or Config3ygyc this field specifies the spacing between vectored interrupts Spacing Spacing Between Between Vectors Encoding Vectors hex decimal 16 00 16 000 0 16 01 16 020 32 16 02 16 040 64 16 04 16 080 128 16 08 16 100 256 16 10
220. e read as 0 before it is guaranteed that the indication is cleared in the CPU clock domain also This bit controls the EJ PrHst signal If the signal is used in the system then it must be ensured that both the processor and all devices required for a reset are properly reset Otherwise the system may fail or hang The bit resets itself since the EJTAG Control register is reset by hard or soft reset MIPS32 M14K Processor Core Software User s Manual Revision 02 03 203 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Table 8 31 EJTAG Control Register Descriptions Continued Fields Read Name Bit s Description Write Reset State ProbEn Probe Enable R W Oor 1 This bit indicates to the CPU if the EJTAG memory is from handled by the probe so processor accesses are answered EJTAGBOOT Encoding Meaning 0 The probe does not handle EJTAG memory transactions The probe does handle EJTAG mem ory transactions It is an error by the software controlling the probe if it sets the ProbTrap bit to 1 but resets the ProbEn to 0 The operation of the processor is UNDEFINED in this case The ProbEn bit is reflected as a read only bit in the ProbEn bit bit 0 in the Debug Control Register DCR The read value indicates the effective value in the DCR due to synchronization issues between TCK and CPU clock domains however it is ensur
221. eakpoints The Data Breakpoint Address n DBAn register has the address used in the condition for data breakpoint n Figure 8 10 DBAn Register Format 31 0 DBA Table 8 12 DBAn Register Field Descriptions Fields Read W Dee sa Bit s Description rite Reset State 30 0 Data Data breakpoint address for condition Data breakpoint address for condition for condition Undefined 176 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints 8 2 7 3 Data Breakpoint Address Mask n DBMn Register 0x2108 0x100 n Compliance Level Implemented only for implemented data breakpoints The Data Breakpoint Address Mask n DBMn register has the mask for the address compare used in the condition for data breakpoint n A 1 indicates that the corresponding address bit will not be considered in the match A mask value of all 0 s would require an exact address match while a mask value of all 1 s would match on any address Figure 8 11 DBMn Register Format DBM Table 8 13 DBMn Register Field Descriptions Fields Read W Name Bit s Description rite DBM Data breakpoint address mask for condition Undefined 0 Corresponding address bit not masked Reset State 1 Corresponding address bit masked 8 2 7 4 Data Breakpoint ASID n DBASIDn Register 0x2110 0x100 n Com
222. ed The ERET instruction will use the return address held in ErrorEPC instead of EPC The lower 2 bytes of kuseg are treated as an unmapped and uncached region See Chapter 3 Memory Management of the M14K Core on page 51 This allows main memory to be accessed in the presence of cache errors The operation of the processor is UNDE FINED if the ERL bit is set while the processor is exe cuting instructions from kuseg Exception Level Set by the processor when any exception other than Reset Soft Reset or NMI exceptions is taken Encoding Meaning 0 Normal level 1 Exception level When EXL is set The processor is running in Kernel Mode Interrupts are disabled EPC Causepgy and SRSCtI implementations of Release 2 of the Architecture only will not be updated if another exception is taken Interrupt Enable Acts as the master enable for software and hardware interrupts Encoding Meaning 0 Interrupts are disabled 1 Interrupts are enabled In Release 2 of the Architecture this bit may be modified separately via the DI and EI instructions 5 2 7 IntCtl Register CPO Register 12 Select 1 R W 1 Undefined Undefined The ntCt register controls the expanded interrupt capability added in Release 2 of the Architecture including vec tored interrupts and support for an external interrupt controller This register does not exist in impleme
223. ed by the EPC register at the completion of interrupt processing If Statusypy field has a lower priority than that of the External Interrupt Controller value The value of GPR 29 is first saved to a temporary register then GPR 29 is incremented for the stack frame size The EIC is signalled that the next pending interrupt has been accepted This signalling will update the Causepypy and SRSCtlgycss fields from the EIC output values The SHSCtlgjcss field is copied to the SRSCtlcss field while the Causeg p field is copied to the Statusjp field The saved temporary register is copied to the GPR 29 of the current SRS The KSU ERL and EXL fields of the Status register are optionally set to zero No barrier for execution hazards nor instruction hazards is created IRET finishes by jumping to the interrupt vector driven by the EIC IRET does not execute the next instruction i e it has no delay slot MIPS32 M14K Processor Core Software User s Manual Revision 02 03 257 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 258 Restrictions The operation of the processor is UNDEFINED if an IRET is executed in the delay slot of a branch or jump instruc tion The operation of the processor is UNDEFINED if an IRET is executed when either Shadow Register Sets are not enabled or when EIC interrupt mode is not enabled An IRET placed between an LL and SC instruction will always cause the SC to fail The effective addre
224. ed that change of the ProbEn prior to setting the EjfagBrk bit will have effect for the debug handler executed due to the debug excep tion The reset value of the bit depends on whether the EJTAG BOOT indication is given or not Encoding Meaning 0 Processor is in non debug mode No EJTAGBOOT indication given Processor is in debug mode EJTAG BOOT indication given 204 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 5 EJTAG TAP Registers Table 8 31 EJTAG Control Register Descriptions Continued Fields Name Bit s Description Read Write Reset State ProbTrap Probe Trap This bit controls the location of the debug exception vec tor Encoding 0 In normal memory OxBFCO 0480 1 In EJTAG memory at OxFF20 0200 in dmseg Meaning Valid setting of the ProbTrap bit depends on the setting of the ProbEn bit as described for the ProbEn bit The ProbTrap should not be set to 1 for debug exception vector in EJTAG memory unless the ProbEn bit is also set to 1 to indicate that the EJTAG memory may be accessed The read value indicates the effective value to the CPU due to synchronization issues between TCK and CPU clock domains however it is ensured that change of the ProbTrap bit prior to setting the EjfagBrk bit will have effect for the EjtagBrk T
225. ed with the lower bit of the SAMode field and written to the GPR Similarly a write to the EPC register via MTCO takes the value from the GPR and distributes that value to the exception PC and the SAMode field as follows ExceptionPC GPR rt 3 0 ISAMode lt 2 0 GPRIrt g That is the upper 31 bits of the GPR are written to the upper 31 bits of the exception PC and the lower bit of the exception PC is cleared The upper bit of the SAMode field is cleared and the lower bit is loaded from the lower bit of the GPR Figure 5 15 EPC Register Format 31 0 EPC Table 5 19 EPC Register Field Description Fields Name Bit s Description Read Write Reset State EPC 31 0 Exception Program Counter R W Undefined 5 2 16 NestedEPC CPO Register 14 Select 2 Compliance Level Optional The Nested Exception Program Counter NestedEPC is a read write register with the same behavior as the EPC register except that e The NestedEPC register ignores the value of Statusgy and is therefore updated on the occurrence of any exception including nested exceptions e The NestedEPC register is not used by the ERET DERET IRET instructions To return to the address stored in NestedEPC software must copy the value of the NestedEPC register to the EPC register This register is part of the Nested Fault feature The existence of the register can be determined by reading the Config5NFExists bit
226. efill TLB Invalid Address Error Reserved Instruction Watch Programming Notes There is no Load Linked Word Unsigned operation corresponding to Load Word Unsigned MIPS32 M14K Processor Core Software User s Manual Revision 02 03 265 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 266 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 31 26 25 21 20 16 15 0 PREF 110011 base hint offset 6 5 5 16 Format PREF hint offset base MIPS32 Purpose Prefetch To move data between memory and cache Description prefetch_memory GPR base offset PREF adds the 16 bit signed offset to the contents of GPR base to form an effective byte address The hint field sup plies information about the way that the data is expected to be used PREF does not cause addressing related exceptions including TLB exceptions If the address specified would cause an addressing exception the exception condition is ignored and no data movement occurs However even if no data is moved some action that is not architecturally visible such as writeback of a dirty cache line can take place It is implementation dependent whether a Bus Error or Cache Error exception is reported if such an error is detected as a byproduct of the action taken by the PREF instruction PREF neither generates a memory operation nor modifies the s
227. egister Field Width bit Total Size of Other Fields Empty 0 Field Size bit Minor Opcode Size bit Comment BEQZI6 Branch on Equal Zero BEQZI6 BNEZI6 BNEZI6 POOL16C Branch on Not Equal Zero Jump Register ADDIU SP POOLI16C DDIUSP 284 Jump Register Com pact MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 11 3 microMIPS Re encoded Instructions Table 11 2 16 Bit Re encoding of Frequent MIPS32 Instruction Sequences Continued Register Total Major Number of Immediate Field Size of Empty 0 Minor Opcode Register Field Size Width Other FieldSize Opcode Name Fields bit bit Fields bit Size bit Comment LWM16 POOL16C 4 Load Word Multiple SWM16 POOL16C 4 Store Word Multiple MIPS32 M14K Processor Core Software User s Manual Revision 02 03 285 Copyright 2009 2010 MIPS Technologies Inc All rights reserved microMIPS Instruction Set Architecture 11 3 1 3 Instruction Specific Register Specifiers and Immediate Field Encodings Table 11 3 Instruction Specific Register Specifiers and Immediate Field Values 286 Number of Immediate Register 1 Register 2 Register 3 Register Field Size Decoded Decoded Decoded Immediate Field Decoded Instruction Fields bit Value Value Value Val
228. egister Descriptions Continued Fields Read Name Bit s Description Write Reset State Doze Doze state R 0 The Doze bit indicates any kind of low power mode The value is sampled in the Capture DR state of the TAP con troller Encoding Meaning 0 CPU not in low power mode 1 CPU is in low power mode Doze includes the Reduced Power RP and WAIT power reduction modes Halt Halt state R 0 The Halt bit indicates if the internal system bus clock is running or stopped The value is sampled in the Cap ture DR state of the TAP controller Encoding Meaning 0 Internal system clock is running 1 Internal system clock is stopped PerRst Peripheral Reset R W 0 When the bit is set to 1 it is only guaranteed that the peripheral reset has occurred in the system when the read value of this bit is also 1 This is to ensure that the setting from the TCK clock domain gets effect in the CPU clock domain and in peripherals When the bit is written to 0 then the bit must also be read as 0 before it is guaranteed that the indication is cleared in the CPU clock domain also This bit controls the EJ_PerRst signal on the core PRnW Processor Access Read and Write R Undefined This bit indicates if the pending processor access is for a read or write transaction and the bit is only valid while PrAcc is set Encoding Meaning 0 Read transaction 1 Write transaction
229. ement a timer and timer interrupt function The timer interrupt is an output of the cores The Compare register maintains a stable value and does not change on its own When the value of the Count register equals the value of the Compare register the S Timerlnt pin is asserted This pin will remain asserted until the Compare register is written The S Timerlnt pin can be fed back into the core on one of the interrupt pins to generate an interrupt Traditionally this has been done by multiplexing it with hardware interrupt 5 to set interrupt bit P 7 in the Cause register For diagnostic purposes the Compare register is a read write register In normal use however the Compare register is write only Writing a value to the Compare register as a side effect clears the timer interrupt Figure 5 5 Compare Register Format 31 0 Compare Table 5 7 Compare Register Field Description Fields Description Read Write Reset State Interval count compare value Undefined 5 2 6 Status Register CPO Register 12 Select 0 The Status register is a read write register that contains the operating mode interrupt enabling and the diagnostic states of the processor Fields of this register combine to create operating modes for the processor Refer to 3 2 Modes of Operation on page 51 for a discussion of operating modes and 4 3 Interrupts on page 65 for a dis cussion of interrupt modes Interrupt Enable I
230. en the pipeline is restarted 8 8 1 2 Normal Trace Mode Outputs 1 Stall cycles in the pipe are ignored by the tracing logic and are not traced This is indicated by the signal Out_Valid that is turned off when no valid instruction is being traced When Out_Valid is asserted instructions are traced out as described in the rest of this section The traced instruction PC is a virtual address In the output format every sequentially executed instruction is traced as 1 b0 Every instruction that is not sequential to the previous one is traced as either a 10 or an 11 read this as a serial bitstream from left to right This implies that the target instruction of a branch or jump is traced this way not the actual branch or jump instruction this is similar to PDtrace A 10 instruction implies a taken branch for a conditional branch instruction whose condition is unpredictable statically but whose branch target can be computed statically and hence the new PC does not need to be traced out Note that if this branch was not taken it would have been indicated by a 0 bit that is sequential flow A 11 instruction implies a taken branch for an indirect jump like instruction whose branch target could not be computed statically and hence the taken branch address is now given in the trace This includes for example instructions like jr jalr and interrupts e 1100 followed by 8 bits of 1 bit shifted offset from the last PC The bit assignments of
231. eneral exception vector before getting GPRs k0 and k1 are available no shadow register switches invoked in compatibility mode HW7 HWO SW1 SWO Read Cause register for IP bits and Status register for IM bits Keep only IP bits from Cause and mask with IM bits no bits set spurious interrupt Assumptions Causej 1 if it were zero here The software priority is IP9 IPO Location Offset 0x200 from exception base ef IVexception mfcO k0 CO Cause mfcO k1 CO Status andi k0 k0 M_CauseIM and k0 kO k1 beq k0 zero Dismiss JR clz k0 kO ip 66 Find first bit set IP9 IPO kO 14 23 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved OX F F F FF F F X F HF F F F KF X s 4 3 Interrupts xori k0 k0 0x17 PVA 23 HS 9 5 ER sll k0 k0 VS Shift to emulate software IntCtlyg la k1 VectorBase Get base of 10 interrupt vectors addu k0 kO k1 Compute target from base and offset jr ko Jump to specific exception routine nop Each interrupt processing routine processes a specific interrupt analogous to those reached in VI or EIC interrupt mode Since each processing routine is dedicated to a particular interrupt line it has the context to know which line was asserted Each processing routine may need to look further to determine th
232. ent Unit MMU e SRAM Interface e Power Management Optional blocks include e Reference Design e microMIPS Instruction Recode e EJTAG Debug Support e Coprocessor 2 Interface CP2 CorExtendQ User Defined Instructions UDI MIPS32 M14K Processor Core Software User s Manual Revision 02 03 19 Copyright 2009 2010 MIPS Technologies Inc All rights reserved In troduction to the MIPS32 M14K Processor Core Figure 1 M14K Processor Core Block Diagram M14K Core Reference Design ow me me P d microMIPS GPR User defined SRAM Cop blk s IF Execution Unit Controller Flash ALU Shift MDU VF User defined UDI Atomic LdSt Perf or Area Opt CorExtend blk I F hz UDI 1 AHB Lite VF System System Debug P rofiing Interface 1 Coprocessor m US 20 Fast Debug Channel Interrupt Performance Counters Power Mgt f Interface Sampling IDSRAM SecureDebug VF 1 oa a e a Ser a ee EE AEC RAE SL Mee Peat eee ESAE pee pap A a EEEE SEE Optional Fixed R equired 1 2 1 Required Logic Blocks The following subsections describe the required logic blocks of the M14K processor core 1 2 1 1 Execution Unit The core execution unit implements a load store architecture with single cycle Arithmetic Logic Unit ALU opera tions logical shift add subtract and an autonomous multiply divide unit The
233. er fields K23 and KU see 5 2 20 Config Register CPO Register 16 Select 0 Write protection of segments is not possible during FM translation 3 2 2 User Mode In user mode a single 2 GByte 23 bytes uniform virtual address space called the user segment useg is available Figure 3 3 shows the location of user mode virtual address space Figure 3 3 User Mode Virtual Address Space 32 bit OxFFFF_FFFF Address Error 0x8000_0000 Ox7FFF FFFF 2GB Mapped useg 0x0000 0000 The user segment starts at address 0x0000 0000 and ends at address 0x7FFF_FFFF Accesses to all other addresses cause an address error exception The processor operates in User mode when the Status register contains the following bit values e UM 1 e EXL 0 e ERL 0 In addition to the above values the DM bit in the Debug register must be 0 Table 3 1 lists the characteristics of the useg User mode segments Table 3 1 User Mode Segments Status Register Bit Value Address Bit Segment Value EXL ERL UM Name Address Range Segment Size 32 bit 0 0 1 useg 0x0000_0000 gt 2 GByte A 31 20 Ox7FFF FFFF 23 bytes 54 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 3 2 Modes of Operation All valid user mode virtual addresses have their most significant bit cleared to 0 indicating that user mode can only access the lower
234. erated and an internal bit in the data breakpoint registers is set to indicate that the match occurred The match is precise in that the debug exception or trigger occurs on the instruction that caused the break point to match 8 2 2 Complex Breakpoints The complex breakpoint unit utilizes the instruction and data breakpoint hardware and looks for more specific match ing conditions There are several different types of enabling that allow more exact breakpoint specification Tuples add an additional condition to data breakpoints of requiring an instruction breakpoint on the same instructions Pass counters are counters that decrement each time a matching breakpoint condition is taken Once the counter reaches 0 the break or trigger effect of the breakpoint is enabled Priming allows a breakpoint to only be enabled once another trigger condition has been detected Data qualification allows instruction breakpoints to only be enabled once a corre sponding load data triggerpoint has matched both address and data Data qualified breakpoints are also disabled if a load is executed that matches on the address portion of the triggerpoint but has a mismatching data value The com plex breakpoint features can be combined to create very complex sequences to match on MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints In addition to the breakpo
235. ernal Buffer AHB Lite Bus Internal ISRAM amp External Memory I F 2 2 2 microMIPS Instruction Recode Decode The M14K core supports the microMIPS instruction set which contains all MIPS32 ISA instructions except for branch likely instructions in a new 32 bit encoding scheme with some of the commonly used instructions also available in 16 bit encoded format This ISA improves code density through the additional 16 bit instructions while maintaining a performance similar to MIPS32 mode In microMIPS mode 16 bit or 32 bit instructions are fetched and recoded to legacy MIPS32 instruction opcodes in the pipeline s I stage so that the M14K core can have the same MAK microarchitecture Because the microMIPS instruction stream can be intermixed with 16 bit halfword or 32 bit word size instructions on halfword or word boundaries additional logic is in place to address the word misalignment issues thus minimizing performance loss 1 2 2 3 Memory Protection Unit MPU The MPU can be configured to have from 1 to 16 memory protection regions Each region is enabled by a set of Watch registers that define the address size and protection of each memory region The MPU control and Watch registers are implemented by CDMM Common Device Memory Map registers After they have been programmed these control registers can be locked to prohibit later modifications Once programmed a Protection Exception will be triggered when an Instruct
236. es government Government the use duplication reproduction release modification disclosure or transfer of this information or any related documentation of any kind is restricted in accordance with Federal Acquisition Regulation 12 212 for civilian agencies and Defense Federal Acquisition Regulation Supplement 227 7202 for military agencies The use of this information by the Government is further restricted in accordance with the terms of the license agreement s and or applicable contract terms and conditions covering this information from MIPS Technologies or an authorized third party MIPS MIPS I MIPS II MIPS III MIPS IV MIPS V MIPS 3D MIPS16e MIPS32 MIPS64 microMIPS MIPS Based MIPSsim MIPS Logo MIPS Technologies Logo MIPS VERIFIED MIPS VERIFIED Logo SmartMIPS 4K 4Kc 4Kp 4KE 4KEc 4KEm 4KEp 4KEPro 4KS 4KSd M4K M14K MIA4KC 24K 24Kc 24Kf 24KE 24KEc 24KEf 34K 34Kc 34Kf 74K 74Kc 74Kf 1004K 1004Kc 1004Kf R3000 R4000 R5000 R10000 At the core of the user experience BusBridge Clam CorExtend CoreFPGA CoreLV EC FPGA View MIPS Navigator MIPS System Navigator Malta MDMX OCI PDtrace Pro Series SEAD 3 SOC it and YAMON are trademarks or registered trademarks of MIPS Technologies Inc in the United States and other countries Template nB1 01 Built with tags 2B MIPS32 PROC MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies In
237. escription 0 16 s0 General purpose register 1 17 sl General purpose register 2 2 vO General purpose register 3 3 vl General purpose register 4 4 a0 General purpose register 5 5 al General purpose register 6 6 a2 General purpose register 7 7 a3 General purpose register MIPS32 M14K Processor Core Software User s Manual Revision 02 03 287 Copyright 2009 2010 MIPS Technologies Inc All rights reserved microMIPS Instruction Set Architecture 288 1 0 7 correspond to the register s 16 bit binary encoding and show how that encoding relates to the MIPS registers 0 7 never refer to the registers except within the binary microMIPS instructions From the assembler only the MIPS names 16 17 2 etc or the symbolic names s0 s1 vO etc refer to the registers For example to access register number 17 in the register file the programmer references 17 or s1 even though the micro MIPS binary encoding for this register is 001 2 General registers not shown in the above table are not accessible through the 16 bit instruc tion using 3 bit register specifiers The Move instruction can access all 32 general purpose registers Table 11 5 SB16 SH16 SW16 Source Registers 0 2 7 17 16 Bit 32 Bit MIPS Symbolic Name Register Register From Encoding Encoding ArchDefs h Description 0 0 zero Hard wired Zero 1 17 sl General purpose register 2 2 vO General purpose registe
238. esign or otherwise MIPS Technologies does not assume any liability arising out of the application or use of this information or of any error or omission in such information Any warranties whether express statutory implied or otherwise including but not limited to the implied warranties of merchantability or fitness for a particular purpose are excluded Except as expressly provided in any written license agreement from MIPS Technologies or an authorized third party the furnishing of this document does not give recipient any license to any intellectual property rights including any patent rights that cover the information in this document The information contained in this document shall not be exported reexported transferred or released directly or indirectly in violation of the law of any country or international law regulation treaty Executive Order statute amendments or supplements thereto Should a conflict arise regarding the export reexport transfer or release of the information contained in this document the laws of the United States of America shall be the governing law The information contained in this document constitutes one or more of the following commercial computer software commercial computer software documentation or other commercial items If the user of this information or any related documentation of any kind including related technical data or manuals is an agency department or other entity of the United Stat
239. esired When set to one the core tracing logic does not allow a FIFO overflow or discard trace data This is achieved by stalling the pipeline when the FIFO is nearly full so that no trace records are ever lost When set to one this enables tracing in Debug Mode For trace to be enabled in Debug mode the On bit must be one When set to zero trace is disabled in Debug Mode irrespective of other bits Undefined Undefined On bit must be one When set to zero trace is disabled in Exception Mode irrespective of other bits When set to one this enables tracing in Kernel Mode Undefined For trace to be enabled in Kernel mode the On bit must be one When set to zero trace is disabled in Kernel Mode irrespective of other bits ne uw bit is reserved Must be written as zero returns Zero on ne uw R W R W When set to one this enables tracing in Exception R W Undefined Mode For trace to be enabled in Exception mode the R W When set to one this enables tracing in User Mode Undefined For trace to be enabled in User mode the On bit must be one When set to zero trace is disabled in User Mode irre spective of other bits ASID M 20 13 In an FM based MMU core in which ASID is not sup ported this field is ignored on writes and returns zero on reads ASID In an FM based MMU core in which ASID is not sup ported this field is ignored on writes and returns zero on reads In an FM based MMU core in whic
240. essor compares RIPL with Status yp to determine if the requested interrupt has higher priority than the current PL If RIPL is strictly greater than Status p and interrupts are enabled StatUS 1 Statusgy 0 and Statuspgg 0 an interrupt request is signaled to the pipeline When the processor starts the interrupt exception it loads RIPL into Causeg p which overlays Causejpo jp and signals the external interrupt controller to notify it that the request is being serviced Because CausSegyp is only loaded by the processor when an interrupt exception is signaled it is available to software during interrupt processing The vector number that the EIC passes to the core is combined with the ntCtlys to determine where the interrupt service routine is located The vector number is not stored in any software visible registers In EIC interrupt mode the external interrupt controller is also responsible for supplying the GPR shadow set number to use when servicing the interrupt As such the SRSMap register is not used in this mode and the mapping of the vectored interrupt to a GPR shadow set is done by programming or designing the interrupt controller to provide the correct GPR shadow set number when an interrupt is requested When the processor loads an interrupt request into Causeg p it also loads the GPR shadow set number into SHSCtlgjcss which is copied to SRSCtlcss when the inter rupt is serviced The operation of EIC interrupt mode
241. est code size 11 1 Overview 11 1 1 MIPSr3 Architecture MIPSr3 is a family of architectures which includes Release 3 0 of the MIPS32 Architecture and the first release of the microMIPS32 architecture Enhancements included in the MIPSr3 Architecture are e MIPSr3 Architecture includes MIPS32 Release 3 ISA and microMIPS ISA e The MIPS16 ASE is phased out microMIPS is a replacement for MIPS16e Therefore these two ASEs never co exist within the same processor core e Branch likely instructions are phased out in microMIPS and are emulated by the assembler They remain avail able in the MIPS32 encoding Unless otherwise described in this document all other aspects of the MIPS32r3 architecture are identical to MIPS32 Release 2 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 275 Copyright 2009 2010 MIPS Technologies Inc All rights reserved microMIPS Instruction Set Architecture 276 11 1 2 Default ISA Mode The instruction sets that are available win an implementation are reported in the Config3 c register field bits 15 14 Config A bit 2 is not used for microMIPS For implementations that support both microMIPS and MIPS32 the selected ISA mode following reset is determined by the setting of the Config3 register field which is a read only field set by a hardware signal external to the pro cessor core For implementations that support both microMIPS and MIPS32 the selected ISA
242. et the receive FIFO is full If RxF is not set the R FIFO is not full TxE 1 If TxE is set the transmit FIFO is empty If TxE is not set R the FIFO is not empty TxF 0 If TxF is set the transmit FIFO is full If TxF is not set the R FIFO is not full 8 10 6 4 FDC Receive FDRX Register Offset 0x18 This register exposes the top entry in the receive FIFO A read from this register returns the top item in the FIFO and removes it from the FIFO itself The result of a write to this register is UNDEFINED The result of a read when the FIFO is empty is also UNDEFINED so software must check the RxE flag in FDSTAT prior to reading Figure 8 41 shows the format of the FDC Receive register and Table 8 47 describes the register fields Figure 8 41 FDC Receive Register 31 0 RxData Table 8 47 FDC Receive Register Field Descriptions Read Reset Description Write State RxData 31 0 This register holds the top entry in the receive FIFO R Undefined 8 10 6 5 FDC Transmit n FDTXn Registers Offset 0x20 0x8 n These sixteen registers access the bottom entry in the transmit FIFO The different addresses are used to generate a 4b channel identifier that is attached to the data value This allows software to track different event types without need ing to reserve a portion of the 32b data as a tag A write to one of these registers results in a write to the transmit FIFO of the data value and channel ID corres
243. ether the processor implements microMIPS and whether the instruction is in the delay slot of a branch or jump which has delay slots Table 4 8 shows the value stored in each of the CPO PC reg isters including EPC For implementations of Release 2 of the Architecture if Statusgey 0 the CSS field in the SRSCIl register is copied to the PSS field and the CSS value is loaded from the appropriate source If the EXL bit in the Status register is set the EPC register is not loaded and the BD bit is not changed in the Cause register For implementations of Release 2 of the Architecture the SHSCII register is not changed Table 4 8 Value Stored in EPC ErrorEPC or DEPC on an Exception microMIPS In Branch Jump Implemented Delay Slot Value stored in EPC ErrorEPC DEPC No No Address of the instruction No Yes Address of the branch or jump instruction PC 4 Yes No Upper 31 bits of the address of the instruction combined with the SA Mode bit Yes Yes Upper 31 bits of the branch or jump instruction PC 2 or PC 4 depending on size of the instruction in the micro MIPS ISA Mode and PC 4 in the 32 bit ISA Mode com bined with the SA Mode bit The CE and ExcCode fields of the Cause registers are loaded with the values appropriate to the exception The CE field is loaded but not defined for any exception type other than a coprocessor unusable exception The EXL bit is set in the Status register The processor is started at t
244. evision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 2 6 Data Bypassing Figure 2 15 shows the data bypass for an Add instruction followed by a Sub and another Add instruction The Sub instruction uses the output from the Add instruction as one of the operands and thus the M to E bypass is used The following Add uses the result from both the first Add instruction and the Sub instruction Since the Add data is now in A stage the A to E bypass is used and the M to E bypass is used to bypass the Sub data to the Add instruc tion Figure 2 15 IU Pipeline M to E bypass One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle ADD E M A w R3 R24R1 A to E bypass SUB p R4 R3 R7 M to E bypas ADD 4 p R5 R3 R4 2 6 1 Load Delay Load delay refers to the fact that data fetched by a load instruction is not available in the integer pipeline until after the load aligner in A stage All instructions need the source operands available in the E stage An instruction immedi ately following a load instruction will if it has the same source register as was the target of the load cause an instruc tion interlock pipeline slip in the E stage see 2 10 Instruction Interlocks on page 46 If an instruction following the load by 1 or 2 cycles uses the data from the load the A to E bypass see Figure 2 30 serves to reduce or avoid stall cycles
245. ewShadowSet lt SRSCt lprcss else VecNum lt VIntPriorityEncoder NewShadowSet lt SRSMapypy X4 5 Ip X4 endif vectorOffset lt 164200 VecNum x IntCtlyg 2 00000 endif if Statusppgy 1 or IntCtlyg 0 then endif if Causey 0 then endif elseif ExceptionType Interrupt then Update the shadow set information for an implementation of Release 2 of the architecture if ArchitectureRevision 2 2 and SRSCtlyss gt 0 and Statuspry 0 and Statuspggy 0 then SRSCtlpgg SRSCtI egg SRSCtlcegg NewShadowSet endif endif if Statusgyg 1 then Causecp FaultingCoprocessorNumber CauSeg ccoge ExceptionType Statuspy amp 1 80 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 7 Debug Exception Processing Calculate the vector base address if Statusppy 1 then vectorBase 16 BFC0 0200 else if ArchitectureRevision 2 2 then The fixed value of EBase3 39 forces the base to be in kseg0 or ksegl vectorBase EBase3 12 164000 else vectorBase 16 8000 0000 endif endif Exception PC is the sum of vectorBase and vectorOffset PC vectorBase 49 vectorBase o 9 vectorOffsety 0 No carry between bits 29 and 30 4 7 Debug Exception Processing All debug exceptions have the same basic processing flow e The DEPC re
246. exception Uninitialized bits should be masked off after reading these registers MIPS32 M14K Processor Core Software User s Manual Revision 02 03 155 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Hardware and Software Initialization of the M14K Core 156 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 7 Power Management of the M14K Core An M14K processor core offers a number of power management features including low power design active power management and power down modes of operation The core is a static design that supports a WAIT instruction designed to signal the rest of the device that execution and clocking should be halted reducing system power con sumption during idle periods The core provides two mechanisms for system level low power support discussed in the following sections e Section 7 1 Register Controlled Power Management e Section 7 2 Instruction Controlled Power Management 7 1 Register Controlled Power Management The AP bit in the CPO Status register enables a standard software mechanism for placing the system into a low power state The state of the RP bit is available externally via the S HP output signal Three additional pins SI EXL SI EHL and EJ DebugM support the power management function by allowing the user to change the power state if an exception or error o
247. execution unit includes 32 bit adder used for calculating the data address Address unit for calculating the next instruction address Logic for branch determination and branch target address calculation e Loadaligner e Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results e Leading Zero One detect unit for implementing the CLZ and CLO instructions e Arithmetic Logic Unit ALU for performing bitwise logical operations e Shifter and Store aligner MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 1 2 M14K Core Block Diagram 1 2 1 2 General Purposed Register GPR Shadow Registers The M14K core contains thirty two 32 bit general purpose registers used for integer operations and address calcula tion Optionally one three seven or fifteen additional register file shadow sets each containing thirty two registers can be added to minimize context switching overhead during interrupt exception processing The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline _ 2 1 3 Multiply Divide Unit MDU The Multiply Divide unit performs multiply and divide operations Two configuration options exist for the MDU selectable at build time an area efficient iterative
248. ext instruction This starts the whole sequence again Using the same protocol the processor can also execute a load instruction to access the EJTAG Probe s memory For this to happen the processor must execute a load instruction e g a LW LH LB with the target address in the appro priate range Almost the same protocol is used to execute a store instruction to the EJTAG Probe s memory through dmseg The store address must be in the range 0xFF20 0000 to OxFF2F FFFF the ProbEn bit must be set and the processor has to be in debug mode DM 1 The sequence of actions is found below The internal hardware latches the requested address into the PA Address register 2 The internal hardware latches the data to be written into the PA Data register MIPS32 M14K Processor Core Software User s Manual Revision 02 03 209 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core 9 The internal hardware sets the following bits in the EJTAG Control register PrAcc selects Processor Access operation PRnW 1 selects processor write operation Psz 1 0 value depending on the transfer size The EJTAG Probe selects the EJTAG Control register shifts out this control register s data and tests the PrAcc status bit Processor Access when the PrAcc bit is found 1 it means that the requested address is available and can be shifted out The EJTAG Probe checks the PRnW bit to deter
249. f D UIS 100 Status Register RON abet siue aniran noc eo teras sero utn E epe eR e EN DEDE S D ae E MD Ee e UR UN EPL S ed eERA DeE edes 101 at Register TOMA ats occcuda teo dicke nae Er a xb sonducdsaveandextinn descents EE REECE EET 105 ShReGt Register Offfial adobe Drei tier desee but Exdueia eia tddu S 109 Figute 5 9 SHSMap Register T Offmales ou reset vetta tei xU sect Lotte t ccu iu oL oes ES 111 Figure 5 10 View IFL Register FOME sais usi an uei pr ated E ERRA hormiga CREDERE etes RIS God R RD 112 Figure 511 9m sMap RegIster FORMAL oor orte a iore dee tug Faces aada bee ev ER ua aaa onata 113 8 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Figure 5 12 Figure 5 13 Figure 5 14 Figure 5 15 Figure 5 16 Figure 5 17 Figure 5 18 Figure 5 19 Cause Register FOL Tila send cube cxacedigenceduteagdeadsvevecnpAisdeigus Go e RI xse cape RORE 113 View RIPL Register FOlIIOTuss odierna cidasuey deas uere oc dese tn ue On Wired Sasso sedis au acer 118 NestedExc Registef FOnmal sectio uiti ees toit aN a a 119 LEPC Register FOL acte omit oet sU esaet dieto usen teu ded uetus A 120 NestedEPG Register Fonna ss cao rer tne ctp eese Ea Naina ku ooN Iso tein 121 PRO ROJS r FO sc EE ODE 121 wEBase Register aE a E E onm A oH EE T T E E E T 123 GDMMB se Register f OLI uoo otim ote AOE NEA A 123 Figure 5 20 Config Register Format Select O 12
250. f Tracing Each hardware breakpoint in the EJTAG block see the MIPS EJTAG Specification MD00047 revision 4 14 has a control bit associated with it that enables a trigger signal to be generated on a break match condition In special trace mode this trigger can be used to insert an event record into the trace stream In normal trace mode this trigger signal can be used to turn trace on or off thus allowing a user to control the trace on off functionality using breakpoints Similar to the TraceIBPC and TraceDBPC registers in PDtrace registers are defined to control the start and stop of iFlowtrace The details on the actual register names and drseg addresses are shown in Table 8 41 Table 8 41 drseg Registers that Enable Disable Trace from Breakpoint Based Triggers Register Name drseg Address Reset Value 222 ITrigiFlowTrcEn Ox3FDO Register that controls whether or not hard ware instruction breakpoints can trigger iFlowtrace tracing functionality DTrigiFlowTrcEn Ox3FD8 Register that controls whether or not hard ware data and tuple breakpoints can trig ger iFlowtrace tracing functionality The bits in each register are defined as follows e Bit 28 IE DB Used to specify whether the trigger signal from EJTAG simple or complex instruction data or tuple break should trigger iFlowTrace tracing functions or not A value of 0 disables trigger signals from EJTAG instruction breaks and 1 enables triggers for the same MIPS32 M1
251. f the registers BAO is at offset 0x1100 and BC2 is at offset 0x1318 8 2 6 1 Instruction Breakpoint Status IBS Register 0x1000 Compliance Level Implemented only if instruction breakpoints are implemented The nstruction Breakpoint Status IBS register holds implementation and status information about the instruction breakpoints Figure 8 2 IBS Register Format 31 30 29 28 27 24 23 6 5 0 Res ASIDsup Res BCN Res BS Table 8 3 IBS Register Field Descriptions Fields Read Wr Name Bit s Description ite Reset State Res 31 Must be written as zero returns zero on read R 0 ASIDsup 30 Indicates that ASID compare is supported in instruction R 0 breakpoints 0 No ASID compare 1 ASID compare IBASIDn register implemented Res 29 28 Must be written as zero returns zero on read R 0 BCN 27 24 Number of instruction breakpoints implemented R 0 2 4 6 or 8 Res 23 8 Must be written as zero returns zero on read R 0 170 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints Table 8 3 IBS Register Field Descriptions Fields Read Wr Name Bit s Description ite Reset State BS 7 0 Break status for breakpoint n is at BS n with n from 0 R W Undefined to 7 The bit is set to 1 when the condition for the corre sponding breakpoint has matched and BCnTE or IBCnBE are set
252. ftware This bit will most likely only be set on simulation only cache mod els and not on real hardware 5 2 27 Debug Register CPO Register 23 Select 0 The Debug register is used to control the debug exception and provide information about the cause of the debug exception and also when re entering at the debug exception vector due to a normal exception in debug mode The read only information bits are updated every time the debug exception is taken or when a normal exception is taken when already in debug mode Only the DM bit and the EJTAGver field are valid when read from non debug mode the values of all other bits and fields are UNPREDICTABLE Operation of the processor is UNDEFINED if the Debug register is written from non debug mode Some of the bits and fields are only updated on debug exceptions and or exceptions in debug mode as shown below e DSS DBp DDBL DDBS DIB DINT DIBImpr DDBLImpr DDBSImpr are updated on both debug exceptions and on exceptions in debug modes e DExcCode is updated on exceptions in debug mode and is undefined after a debug exception e Halt and Doze are updated on a debug exception and are undefined after an exception in debug mode e DBDis updated on both debug and on exceptions in debug modes All bits and fields are undefined when read from normal mode except those explicitly described to be defined e g EJTAGver and DM Figure 5 28 Debug Register Format
253. g and is intended only to demonstrate the concepts Save GPRs here and setup software context mfcO k0 CO EPC Get restart address Sw k0 EPCSave Save in memory mfcO k0 CO Status Get Status value Sw k0 StatusSave Save in memory T3 k1 IMbitsToClear Get Im bits to clear for this interrupt p this must include at least the IM bit for the current interrupt and may include y others and k0 kO k1 Clear bits in copy of Status ins k0 zero S_StatusEXL W_StatusKSU W_StatusERL W_StatusEXL Clear KSU ERL EXL bits in k0 mtcO k0 CO Status Modify mask switch to kernel mode M Processor Core Software User s Manual Revision 02 03 67 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M14KT Core re enable interrupts Process interrupt here including clearing device interrupt In some environments this may be done with a thread running in kernel or user mode Such an environment is well beyond the scope of this example f To complete interrupt processing the saved values must be restored and the original interrupted code restarted uA di Disable interrupts may not be required lw k0 StatusSave Get saved Status including EXL set lw k1 EPCSave JE and EPC mtcO k0 CO Status Restore the original value mtcO k1 CO EPC and EPC Res
254. g it 8 8 6 1 IFlowTrace Control Status IFCTL Register offset Ox3fcO The Control Status register provides the mechanism for turning on the different trace modes Figure 8 31 has the for mat of the register and Table 8 37 describes the register fields Figure 8 31 Control Status Register 31 30 16 15 14 13 12 11 10 9 8 5 4 3 2 1 0 ies z i G n f 218 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Table 8 37 Control Status Register Field Descriptions 8 8 iFlowtrace Mechanism Fields Name Description Compliance 0 Reserved for future use Read as zeros must be written as Required Zeros Illegal This bit is set by hardware and indicates if the currently Required enabled trace output modes are an illegal combination A value of 1 indicates an unsupported setting A value of 0 indicates that the currently selected settings are legal FDT CAUSE Extended Filtered Data Trace mode FDT Adds causing Optional for load store virtual address to Filtered Data Trace iFlowTrace rev FDT CAUSE only has effect if FDT is set 2 0 The extended trace sequence is a FDT trace message fol lowed by the Breakpoint Match BM trace message If CYC is set the FDT trace message will have a DeltaCycle Message value of 0 directly followed by the Breakpoint match BM message This message sequence FDT delta cycle of 0 and BM
255. gister is loaded with the program counter PC value at which execution will be restarted and the DBD bit is set appropriately in the Debug register The value loaded into the DEPC register is the current PC if the instruction is not in the delay slot of a branch or the PC 4 of the branch if the instruction is in the delay slot of a branch e The DSS DBp DDBL DDBS DIB DINT DIBImpr DDBLImpr and DDBSImpr bits in the Debug register are updated appropriately depending on the debug exception type e The Debug register is updated with additional information for complex breakpoints e Halt and Doze bits in the Debug register are updated appropriately e DMbitin the Debug register is set to 1 e The processor is started at the debug exception vector The value loaded into DEPC represents the restart address for the debug exception and need not be modified by the debug exception handler software in the usual case Debug software need not look at the DBD bit in the Debug regis ter unless it wishes to identify the address of the instruction that actually caused the debug exception A unique debug exception is indicated through the DSS DBp DDBL DDBS DIB DINT DIBImpr DDBLImpr and DDBSImpr bits in the Debug register No other CPO registers or fields are changed due to the debug exception thus no additional state is saved Operation if InstructionInBranchDelaySlot then DEPC PC 4 Debugpgp 1 else DEPC lt PC Debugpgp
256. gisters are present 1 One or more Watch registers are present This bit is always read as 0 because the M14K core does not contain Watch registers Code compression MIPS16e implemented R 0 0 No MIPS16e present 1 MIPS16e is implemented EJTAG present This bit is always set to indicate that the R 1 core implements EJTAG FPU implemented This bit is always zero because the core R 0 does not contain a floating point unit 5 2 22 Config2 Register CPO Register 16 Select 2 The Config2 register is an adjunct to the Config register and is reserved to encode additional capabilities information Config2 is allocated for showing the configuration of level 2 3 caches These fields are reset to 0 because L2 L3 caches are not supported by the M14K core All fields in the Config2 register are read only Figure 5 23 Config2 Register Format Select 2 31 30 0 IS Table 5 26 Config2 Register Field Descriptions Select 1 Fields Name Bit s Description Read Write Reset State M 31 This bit is hardwired to 1 to indicate the presence of the R 1 Config3 register 0 30 0 These bits are reserved R 0 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 127 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core 5 2 23 Config3 Register CPO Register 16 Select 3 The Config3 register encodes additional capa
257. gisters that Enable Disable Trace from Breakpoint Based Triggers sse 222 Table 8 42 FDC TAP Register Field Descriptions nora erret a sete kd rera R a div enaanngnecs 227 Table 8 43 FOC Register Mappli sca ote etate et rutas Reese acceptance Presa cue Tuta E 228 Table 8 44 FDC Access Control and Status Register Field Descriptions sssseeees 228 Table 8 45 FDC Configuration Register Field Descriptions eese 229 Table 8 46 FDC Status Register Field Descriptions esses esses senem nnne nn 230 Table 8 47 FDC Receive Register Field Descriptions essssisesesssesssseseeenee nnne nnne nennen 231 Table 8 49 FDTXnAdd ess Decoder eee E etu e petentem actio Sas ER 232 Table 8 48 FDC Transmit Register Field Descriptions esses enne 232 Table 9 1 Byte Access Within d MOI ssoscosvuse ous etx rue ipe QE USO UNIN ae E aestu EEGA 235 Table 10 1 Table 10 2 Table 10 3 Table 10 4 Table 10 5 Table 10 6 Encoding or tig ODCOgeT eld tont poetice i e Hao E Loc stans ta titus taste teen dut Peste tte tonectids 240 Special Opcode encoding of Function Field ciae ences ente then eek tke nna XXE kann eR RE RE nana ennn 240 Special2 Opcode Encoding of Function Field sss eene 240 Special3 Opcode Encoding of Function Field sse eene 241 Heglimim
258. gnal EJTAG Debug Single Step EJTAG Debug Interrupt Caused by the assertion of the external EJ DINT input or by setting the EjtagBrk bit in the ECR register Asserting edge of S _NMI signal Interrupt Assertion of unmasked hardware or software interrupt signal Protection Instruction fetch Instruction fetch access to a protected memory region was attempted EJTAG debug hardware instruction break matched AdEL Fetch address alignment error User mode fetch reference to kernel address ISRAM Parity Error Parity error on I SRAM access IBE Instruction fetch bus error Instruction Validity Exceptions An instruction could not be completed because it was not allowed access to the required resources Coprocessor Unusable or was illegal Reserved Instruc tion If both exceptions occur on the same instruction the Coprocessor Unus able Exception takes priority over the Reserved Instruction Exception Protection Instr Execution Attempted to write EBase when not allowed by MPU Execution Exception An instruction based exception occurred Integer overflow trap system call breakpoint floating point or Coprocessor 2 exception Tr Execution of a trap when trap condition is true Protection Data access Data access to a protected memory region was attempted DDBL DDBS EJTAG Data Address Break address only or EJTAG Data Value Break on Store address and value Load address alignment error
259. h ASID is not sup R ported this field is ignored on writes and returns 1 on reads This causes all match equations to work cor rectly in the absence of an ASID 138 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 32 TraceControl Register Field Descriptions Continued Fields Description Read Write Reset State These three bits control the trace mode function Undefined Mode Trace Mode 000 Trace PC 001 Trace PC and load address 010 Trace PC and store address 011 Trace PC and both load store addresses 100 Trace PC and load data 101 Trace PC and load address and data 110 Trace PC and store address and data 111 Trace PC and both load store address and data The TraceControl2yajiaModes field determines which of these encodings are supported by the processor The operation of the processor is UNPREDICTABLE if this field is set to a value which is not supported by the processor This is the master trace enable switch in software con R W 0 trol When zero tracing is always disabled When set to one tracing is enabled whenever the other enabling functions are also true 5 2 29 Trace Control2 Register CPO Register 23 Select 2 The TraceControl2 register provides additional control and status information Note that some
260. half of the virtual memory map Any attempt to reference an address with the most significant bit set while in user mode causes an address error exception The system maps all references to useg through the FMT 3 2 3 Kernel Mode The processor operates in Kernel mode when the DM bit in the Debug register is 0 and the Status register contains one or more of the following values e UM 0 ERL 1 e EXL 1 When a non debug exception is detected EXL or ERL will be set and the processor will enter Kernel mode At the end of the exception handler routine an Exception Return ERET instruction is generally executed The ERET instruc tion jumps to the Exception PC clears ERL and clears EXL if ERL 0 This may return the processor to User mode Kernel mode virtual address space is divided into regions differentiated by the high order bits of the virtual address as shown in Figure 3 4 Also Table 3 2 lists the characteristics of the Kernel mode segments MIPS32 M14K Processor Core Software User s Manual Revision 02 03 55 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Memory Management of the M14K Core Figure 3 4 Kernel Mode Virtual Address Space OxFFFF_FFFF Kernel virtual address space kseg3 OxEO00 0000 Fixed Mapped 512MB OxDFFF FFFF Kernel virtual address space Fixed Mapped 512MB kseg2 0xC000 0000 OxBFFF FFFF Kernel virtual address space ksegl 0xA000 0000 Unmapped Uncached 512MB Ox9FFF FFFF
261. hat the breakpoint will match for addresses exclusive outside to the range defined by BMn and BAn This bit is writeable IBCn 4 hwart a value of 0 indicates that the breakpoint will match using the Equality and Mask equation as found in Section 8 2 3 1 Conditions for Matching Instruction Breakpoints A value of 1 indicates that the breakpoint will match using address ranges using the equation below IB match IBCnTCuse TC IBCnTC amp amp IBCnASIDuse ASID IBASIDnASID amp amp IBCnhwarts IBCnhwart amp amp IBMnIBM PC IBAnIBA 0 IBCnhwarts amp amp IBCnhwart amp amp IBCnexcl amp amp IBM lt PC lt IBA IBCnexcl amp amp IBM gt PC PC gt IBA Or if microMIPS is supported IB range match IBCnTCuse TC IBCnTC amp amp IBCnASIDuse ASID IBASIDnASID amp amp IBCnhwarts IBCnhwart amp amp IBMnIBM PC MSB 1 lt lt 1 ISAmode IBAnIBA 0 IBCnhwarts amp amp IBCnhwart amp amp IBMnIBM 0 ISAmode IBAnIBA 0 0 amp amp IBCnexcl amp amp IBM MSB 1 lt PC MSB 1 lt IBA MSB 1 IBCnexcl amp amp IBM MSB 1 gt PC MSB 1 PC MSB 1 gt IBA MSB 1 Also note that addresses that overlap a boundary is considered for both exclusive and inclusive breakpoint matches 8 2 3 2 Conditions for Matching Data B
262. he exception vector MIPS32 M14K Processor Core Software User s Manual Revision 02 03 79 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M14KT Core The value loaded into EPC represents the restart address for the exception and need not be modified by exception handler software in the normal case Software need not look at the BD bit in the Cause register unless it wishes to identify the address of the instruction that actually caused the exception Note that individual exception types may load additional information into other registers This is noted in the descrip tion of each exception type below Operation If Statuspgxp is 1 all exceptions go through the general exception vector and neither EPC nor Causepgp nor SRSCtl are modified if Statuspy 1 then vectorOffset c 1614180 else if InstructionInBranchDelaySlot then EPC restartPC PC of branch jump Causegp amp 1 else EPC lt restartPC PC of instruction Causegp 0 endif Compute vector offsets as a function of the type of exception NewShadowSet SRSCtlpss Assume exception Release 2 only if ExceptionType TLBRefill then vectorOffset 163000 elseif ExceptionType Interrupt then if Causey 0 then vectorOffset lt 16 180 else if Statuspggy 1 or IntCtlyg 0 then vectorOffset lt 1634200 else if Config3ygc 1 then VecNum Causegrpr N
263. he reset value of the bit depends on whether the EJTAG BOOT indication is given or not Encoding Meaning 0 Processor is in non debug mode No EJTAGBOOT indication given Processor is in debug mode EJTAG BOOT indication given Oor 1 from EJTAGBOOT EjtagBrk reserved EJTAG Break Setting this bit to 1 causes a debug exception to the pro cessor unless the CPU was in debug mode or another debug exception occurred When the debug exception occurs the processor CoreType lc clock is restarted if the CPU was in low power mode This bit is cleared by hardware when the debug exception is taken The reset value of the bit depends on whether the EJTAG BOOT indication is given or not Encoding Meaning 0 Processor is in non debug mode No EJTAGBOOT indication given Processor is in debug mode EJTAG BOOT indication given Oor 1 from EJTAGBOOT Res reserved MIPS32 M14K Processor Core Software User s Manual Revision 02 03 205 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Table 8 31 EJTAG Control Register Descriptions Continued Fields Read Name Bit s Description Write Reset State DM 3 Debug Mode R 0 This bit indicates the debug or non debug mode Encoding Meaning 0 Processor is in non debug mode 1 Processor is in debug mode The b
264. heir previous state If TMS is sampled LOW at the ris ing edge of TCK the controller transitions to the Pause IR state A HIGH on TMS causes the controller to transition to the Update IR state which terminates the scanning process The instruction cannot change while the TAP control ler is in this state and the instruction register retains its previous state 8 4 2 14 Pause IR State The Pause IR state allows the controller to temporarily halt the shifting of data through the instruction register in the serial path between TD and TDO If TMS is sampled LOW at the rising edge of TCK the controller remains in the Pause IR state A HIGH on TMS causes the controller to transition to the Exit2 IR state The instruction cannot change while the TAP controller is in this state 8 4 2 15 Exit2 IR State This is a temporary controller state in which the instruction register retains its previous state If TMS is sampled LOW at the rising edge of TCK then the controller transitions to the Shift IR state to allow another serial shift of data A HIGH on TMS causes the controller to transition to the Update IR state which terminates the scanning process The instruction cannot change while the TAP controller is in this state 8 4 2 16 Update IR State The instruction shifted into the instruction register takes effect on the rising edge of TCK If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Run Test Idle state A HIGH on T
265. hine Check exceptions are precise on the M14K processor so this bit will always read as 0 R W1 CacheEP 22 Indicates that an imprecise Cache Error is pending Cache Errors cannot be taken by the M14K core so this bit will always read as 0 DBusEP IEXI DDBSImpr 21 20 19 Data access Bus Error exception Pending Covers imprecise bus errors on data access similar to the behavior of BusEP for imprecise bus errors on an instruction fetch Imprecise Error eXception Inhibit controls exceptions taken due to imprecise error indications Set when the processor takes a debug exception or exception in debug mode Cleared by execution of the DERET instruction otherwise modifiable by debug mode software When IEXI is set the imprecise error exception from a bus error on an instruction fetch or data access cache error or machine check is inhibited and deferred until the bit is cleared Indicates that an imprecise Debug Data Break Store exception was taken Imprecise data breaks only occur on complex breakpoints R WI Undefined DDBLImpr Ver 18 17 15 Indicates that an imprecise Debug Data Break Load exception was taken Imprecise data breaks only occur on complex breakpoints EJTAG version Undefined 101 DExcCode 14 10 Indicates the cause of the latest exception in debug mode The field is encoded as the ExcCode field in the Cause register for those normal exceptions th
266. hing Normally on MIPS architecture processors when an interrupt or exception is signalled execution pipelines must be flushed before the interrupt exception handler is fetched This is necessary to avoid mixing the contexts of the inter rupted faulting program and the exception handler The MCU ASE introduces a hardware mechanism in which the interrupt exception vector is prefetched whenever the interrupt input signals change The prefetch memory transac tion occurs in parallel with the pipeline flush and exception prioritization This decreases the overall latency of the execution of the interrupt handler s first instruction Automated Interrupt Prologue The use of Shadow Register Sets avoids the software steps of having to save general purpose registers before han dling an interrupt The MCU ASE adds additional hardware logic that automatically saves some of the COPO state in the stack and auto matically updates some of the COPO registers in preparation for interrupt handling MIPS32 M14K Processor Core Software User s Manual Revision 02 03 75 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M14KT Core Automated Interrupt Epilogue A mirror to the Automated Prologue this features automates the restoration of some of the COPO registers from the stack and the preparation of some of the COPO registers for returning to non exception mode This feature is imple mented within the
267. hitectureRevision 2 2 and SRSCtlygg gt 0 and Statusggy 0 then SRSCtlosg SRSCtlypgg endif if IsMicroMIPSImplemented then MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved PC temp3 1 0 ISAMode lt tempo else PC amp temp endif LLbit lt 0 Cause c amp 0 ClearHazards else Signal EIC for Next Interrupt wait for EIC outputs to update CauSeprpr EICRIPL SRSCtlpregg lt ElCgg temp29 GPR 29 GPR 29 lt GPR 29 DecodedValue IntCtlstkpec Statusyp Causepypy SRSCtlogg SRSCtlaregs NewShadowSet lt SRSCtlgrcss GPR 29 lt temp29 if IntCtloizgg T Statusgy amp 0 Statusgsy amp 0 endif Causey amp 1 ClearHazards PC CalcIntrptAddress endif endif function LoadStackWord vaddr if vAddr o 0 then SignalException AddressError endif pAddr CCA AddressTranslation vAddr DATA LOAD memword lt LoadMemory CCA WORD pAddr vAddr LoadStackWord lt memword endfunction LoadStackWord function CalcIntrptAddress if StatusBEV 1 vectorBase OxBFC0 0200 else if ArchitectureRevision 2 2 vectorBase EBase3 _ 45 077 else vectorBase 0x8000 0000 endif endif if Causey 0 vectorOffset 0x180 else if Statusggy 1 or IntCtlyg 0 vectorOffset 0x200 else if Config3yg c 1 and EI
268. ibed in more detail in Section 8 9 PC Data Address Sampling 8 4 3 12 FDC Instruction This selects the Fast Debug Channel The use of the FDC is described in more detail in Section 8 10 Fast Debug Channel 8 4 3 13 TCBCONTROLA Instruction This instruction is used to select the TCBCONTROLA register to be connected between TD and TDO This register is only implemented if the Trace Control Block is present If no TCB is present then this instruction will select the Bypass register 8 4 3 14 TCBCONTROLB Instruction This instruction is used to select the TCBCONTROLB register to be connected between TD and TDO This register is only implemented if the Trace Control Block is present If no TCB is present then this instruction will select the Bypass register 8 4 3 15 TCBDATA Instruction This instruction is used to select the TCBDATA register to be connected between TD and TDO This register is only implemented if the Trace Control Block is present If no TCB is present then this instruction will select the Bypass register It should be noted that the TCBDATA register is only an access register to other TCB registers The width of the TCBDATA register is dependent on the specific TCB register 8 5 EJTAG TAP Registers The EJTAG TAP Module has one Instruction register and a number of data registers all accessible through the TAP 8 5 1 Instruction Register The Instruction register is accessed when the TAP receives an Instruct
269. id tos atin tote den nier tcd daa eter naire mien toes 40 24 2 Multiply Accumulate Area Efficient MDU J iier oi Eterna citato bak ha eene tne ea btc neret 40 2 4 3 Divide Area Efficient MDU sssssissssssssessseseeeee nennen tenn nnn ns inn tent neni inn rren enne stress 41 25 Branch Delay I EEUU 41 PS BITE BYPASS iena aa R TET EN 42 ZO MINNIE 43 2 6 2 Move from HI LO and CPO Delay sss ener nennen senten nnne ens 43 27 GoOprocessor2 InstDCl9l s sso tede iets eode boe proide U ie dicet seno tH aed RG oido Cep ade 44 exsilio sui ne eese Eun EE NT 45 219 Slip COMCIMOMS eee RE A a E 46 2 10 Instiucton Interot KS osineen a a a a aa a OREL aaia 46 PX Hoza dSn E 47 2 11 1 VpS O Haza Sa a EO get aan se eosin E 48 2 Al hes Instr ctomn Lisin Gerk E EEN 49 211 3 Elinmimatimng Hazard Sissing aaa ai a iaaii aaia 49 Chapter 3 Memory Management of the M14K Core cessere nnne nnn 51 em alae e acc aealans 51 3 2 Nodes OF CDOLallOETs iuc oto pea oes Docet ta a e epa Eu ues ea EIL AR TAL IDEM ORG b DP RDUM DADA DM L OR GEL ORN COND REND TERIS 51 3 2 1 Virtual Memory Segrmielils xc cern nci reine iue RI pu i CEP B tud ERN OE ER BER HU Ee PR TRE dae acids 52 ee TT EONO cp S 54 32S Kemell MOU rerai E E E 55 3 2 4 DEBUG MOUS irinin a aa aa aA aiae aiaa iai 57 3 3 Fixed Mapping ue US 59 SAO System Contool COPrOCES S Olne utet tiat usd t
270. ificant three bits of the virtual address are 1005 32 bit ksegO virtual address space is selected it is the 27 byte 512 MByte kernel virtual space located at addresses 0x8000_0000 Ox9FFF_FFFF References to ksegO are unmapped the physical address selected is defined by subtracting 0x8000 0000 from the virtual address The KO field of the Config register controls cacheability 3 2 3 3 Kernel Mode Kernel Space 1 kseg1 In Kernel mode when the most significant three bits of the 32 bit virtual address are 1015 32 bit ksegl virtual address space is selected ksegl is the 22 byte 512 MByte kernel virtual space located at addresses 0xA000 0000 OxBFFF FFFF References to kseg1 are unmapped the physical address selected is defined by subtracting 0xA000 0000 from the virtual address 3 2 3 4 Kernel Mode Kernel Space 2 kseg2 In Kernel mode when UM 0 ERL 1 or EXL 1 in the Status register and DM 0 in the Debug register and the most significant three bits of the 32 bit virtual address are 1105 32 bit kseg2 virtual address space is selected In the MIAK core this 22 byte 512 MByte kernel virtual space is located at physical addresses OxCO000 0000 OxDFFF FFFF 3 2 3 5 Kernel Mode Kernel Space 3 kseg3 In Kernel mode when the most significant three bits of the 32 bit virtual address are 111 the kseg3 virtual address space is selected In the M14K core this 22 byte 512 MByte kernel virtual space is located a
271. iggered Message 1 UTM1 is generated When UserTraceData2 register is written a trace message of type User Triggered Message 2 UTM2 is generated Please refer toS 2 30 User Trace Datal Register CPO Register 23 Select 3 User Trace Data2 Register CPO Register 24 Select 3 on page 141 Overflow messages can also be generated when tracing off chip if the IO control bit is 0 and trace data is generated faster than it is consumed No overflow will be generated when using on chip trace 8 8 2 2 Special Trace Mode Outputs The normal and special trace modes cannot be enabled at the same time because the trace message encoding is not unique between the two modes The software reading the trace stream must be aware of which mode is selected to know how to interpret the bits in the trace stream The message types for each type of special trace message are unique 00 as above read a bitstream from left to right Delta Cycle Rollover message The output format is 1 0 2 b00 e 010 User Trace Message The format of this type of message is 2 0 3 b010 34 3 Data 31 0 35 UTM2 UTM1 1 UTM2 0 UTM1 44 36 DeltaCycle if enabled e 011 Reserved e 10 Breakpoint Match Message The output format during this trace mode is 1 0 2 2 b01 5 2 BreakpointID 6 Instruction Breakpoint 37 7 MatchingPC 31 1 38 NCC 48 39 DeltaCycle if enabled Note that for a MIPS32 or MIPS64 ins
272. ilizes two First In First Out FIFO structures to buffer data between theM14K and probe The probe uses the FDC TAP instruction to access these FIFOs while the M14K itself accesses them using memory accesses To transfer data out of the M14K the M14K writes one or more pieces of data to the transmit FIFO At this time the M14K can resume doing other work An external probe would examine the sta tus of the transmit FIFO periodically If there is data to be read the probe starts to receive data from the FIFO one entry at a time When all data from the FIFO has been drained the probe goes back to waiting for more data The M14K can either choose to be informed of the empty transmit FIFO via an interrupt or it can choose to periodically check the status Receiving data works in a similar manner the probe writes to the receive FIFO At that time the M14K is either interrupted or finds out via polling a status bit The M14K can then do load accesses to the receive FIFO and receive data being sent to it by the probe The TAP transfer is bidirectional a single shift can be pulling transmit data and putting receive data at the same time The primary advantage of FDC over normal processor accesses or fastdata accesses is that it does not require the M14K to be blocked when the probe is reading or writing to the data transfer FIFOs This significantly reduces the M14K overhead and makes the data transfer far less intrusive to the code executing on the M14K
273. imal amount of hardware initialization and relies on software to fully initialize the device This chapter contains the following sections e Section 6 1 Hardware Initialized Processor State e Section 6 2 Software Initialized Processor State 6 1 Hardware Initialized Processor State An M14K processor core like most other MIPS processors is not fully initialized by hardware reset Only a minimal subset of the processor state is cleared This is enough to bring the core up while running in unmapped and uncached code space All other processor state can then be initialized by software S ColdHeset is asserted after power up to bring the device into a known state Soft reset can be forced by asserting the S _Reset pin This distinction is made for compatibility with other MIPS processors In practice both resets are handled identically with the exception of the setting of Statussg 6 1 1 Coprocessor 0 State Much of the hardware initialization occurs in Coprocessor 0 e Statusggy cleared to 1 on Reset SoftReset e StatuStg cleared to 0 on Reset SoftReset e Statussg cleared to 0 on Reset set to 1 on SoftReset e StatUSym cleared to 0 on Reset SoftReset e Statusep set to 1 on Reset SoftReset e StatuSpp cleared to 0 on Reset SoftReset e Config fields related to static inputs set to input value by Reset SoftReset Configyg set to 010 uncached on Reset SoftReset e DebugDM cleared to 0 on Reset SoftReset unless
274. iming condi tions e The instruction breakpoint involved in the tuple should be configured as follows IBCCncpgrE s IBCCnprong IBCCnpg IBCnrg IBCnge IBPCn 0 8 3 5 Usage of Priming Conditions Priming conditions provide a way to have one breakpoint enabled by another one Prior to the priming condition being satisfied any breakpoint matches are ignored e Priming condition resets to bypass which specifies that no priming is required e 3 other priming conditions are available for each breakpoint These condition vary from breakpoint to breakpoint since it makes no sense for a breakpoint to prime itself The conditions for each of the breakpoints are listed in Table 8 23 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 3 Complex Breakpoint Usage e The priming breakpoint must have xBCnrg or xBCCncge set e Once the priming condition has been seen the primed breakpoint will remain primed until its xBCCn register is written e The primed state is stored with the breakpoint being primed and not with the breakpoint that is doing the priming e Each Prime condition is the comparator output after it has been qualified by its own Prime condition data quali fication and pass counter Using this several stages of priming are possible e g data cycle D followed by instruction A followed by instruction B N times followed by instruction
275. ing edge of the TCK clock depending on the TAP controller state The core signal for this is called EJ TDI TDO Test Data Output Serial output data is shifted from the Instruction or data register to the TDO pin on the falling edge of the TCK clock When no data is shifted out the TDO is 3 stated The core signal for this is called EJ TDO with output enable controlled by EJ TDOzstate MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 4 Test Access Port TAP Table 8 27 EJTAG Interface Pins Continued Pin Type Description TRST_N I Test Reset Input Optional pin The TRST_N pin is an active low signal for asynchronous reset of the TAP controller and instruction in the TAP module independent of the processor logic The processor is not reset by the assertion of TRST_N The core signal for this is called EJ TRST N This signal is optional but power on reset must apply a low pulse on this signal at power on and then leave it high in case the signal is not available as a pin on the chip If available on the chip then it must be low on the board when the EJTAG debug features are unused by the probe 8 4 2 Test Access Port Operation The TAP controller is controlled by the Test Clock TCK and Test Mode Select TMS inputs These two inputs determine whether an the Instruction register scan or data register scan is performed
276. instructions on the CP2 Interface All core interface operations belonging to the E M and A stages will have to occur in the E stage for BC2 instructions This means that a BC2 instruction always slips for a minimum of 2 cycles int the E stage and any delay in the return of branch information from coprocessor 2 will add to the number of slip cycles All other Coprocessor 2 instructions can operate without slips provided that all con trol and data information from coprocessor 2 is transferred in the M stage 2 8 Interlock Handling Smooth pipeline flow is interrupted when cache misses occur or when data dependencies are detected Interruptions handled entirely in hardware such as cache misses are referred to as interlocks At each cycle interlock conditions are checked for all active instructions Table 2 4 lists the types of pipeline interlocks for the M14K processor core Table 2 4 Pipeline Interlocks Interlock Type Sources Slip Stage I side SRAM Stall SRAM Access not complete Instruction Producer consumer hazards E M Stage Hardware Dependencies MDU E Stage BC2 waiting for COP2 Condition Check D side SRAM Stall SRAM Access not complete Coprocessor 2 completion slip Coprocessor 2 control and or data delay from coprocessor MIPS32 M14K Processor Core Software User s Manual Revision 02 03 45 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Pipeline of the M14K Core In general MIPS pro
277. int logic the complex break unit also includes a Stopwatch Timer block This counter can be used to measure time spent in various sections It can either be free running or it can be set up to start and stop counting based on a trigger from instruction breakpoints 8 2 3 Conditions for Matching Breakpoints A number of conditions must be fulfilled in order for a breakpoint to match on an executed instruction or a data trans action and the conditions for matching instruction and data breakpoints are described below The breakpoints only match for instructions executed in non debug mode thus never on instructions executed in debug mode The match of an enabled breakpoint can either generate a debug exception or a trigger indication The BE and or TE bits in the BCn or DBCn registers are used to enable the breakpoints Debug software should not configure breakpoints to compare on an ASID value unless a TLB is present in the imple mentation 8 2 3 1 Conditions for Matching Instruction Breakpoints There are two methods for matching conditions Equality and Mask or Address Range Equality and Mask When an instruction breakpoint is enabled that breakpoint is evaluated for the address of every executed instruction in non debug mode including execution of instructions at an address causing an address error on an instruction fetch The breakpoint is not evaluated on instructions from a speculative fetch or execution nor for addresses which are una
278. intain its register file write slot As a result the MUL 16x16 or 32x16 operation will always force a one cycle stall of the IU pipeline and the MUL 32x32 will force a two cycle stall If the integer instruction immediately following the MUL operation uses its result an additional stall is forced on the IU pipeline MIPS32 M14K Processor Core Software User s Manual Revision 02 03 35 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Pipeline of the M14K Core Table 2 2 lists the repeat rates peak issue rate of cycles until the operation can be reissued for multiply accumu late subtract instructions The repeat rates are listed in terms of pipeline clocks In this table repeat rate refers to the case where the first MDU instruction in the table below if back to back with the second instruction Table 2 2 MDU Instruction Repeat Rates High Performance MDU i Instruction Sequence Operand Size of 1st Repeat Instruction 1st Instruction 2nd Instruction Rate 16 bit MULT MULTU MADD MADDU 1 MADD MADDU MSUB MSUBU MSUB MSUBU 32 bit MULT MULTU MADD MADDU MSUB MSUBU 2 MADD MADDU MSUB MSUBU Figure 2 3 below shows the pipeline flow for the following sequence 1 32x16 multiply Mult 2 Add 3 32x32 multiply Mult 4 Subtract Sub The 32x16 multiply operation requires one clock of each pipeline stage to complete The 32x32 multiply operation requires two clocks in the Mypy pipe
279. introduced within microMIPS sessi 289 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 13 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 14 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 1 Introduction to the MIPS32 M14K Processor Core The MIPS32 M14K core from MIPS Technologies is a high performance low power 32 bit MIPS RISC proces sor core intended for custom system on silicon applications The core is designed for semiconductor manufacturing companies ASIC developers and system OEMs who want to rapidly integrate their own custom logic and peripher als with a high performance RISC processor An M14K core is fully synthesizable to allow maximum flexibility it is highly portable across processes and can easily be integrated into full system on silicon designs This allows develop ers to focus their attention on end user specific characteristics of their product The M14K core is especially well suited for microcontrollers and applications that have real time requirements with a high level of performance efficiency and security requirements The M14K implements the MIPSr3 Architecture in a 5 stage pipeline It includes support for the MIPS32 Release 3 Architecture and microMIPS an Instruction Set Architecture with optimized MIPS32 16 bit and 32 bit instr
280. ion Fetch or Data Access matches the address of the protected memory region or any modification of the EBase base address of exception vectors register was attempted Each protected region can also disable the iFlowtrace capability Typically the MPU improves system security by disabling access to bootcode and preventing execution of non trusted code executing in kernel mode MIPS32 M14K Processor Core Software User s Manual Revision 02 03 25 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Introduction to the MIPS32 6 M14K Processor Core 26 1 2 2 4 EJTAG Debug Support The M14K core provides for an optional Enhanced JTAG EJTAG interface for use in the software debug of applica tion and kernel code In addition to standard user mode and kernel modes of operation the M14K core provides a Debug mode that is entered after a debug exception derived from a hardware breakpoint single step exception etc is taken and continues until a debug exception return DERET instruction is executed During this time the proces sor executes the debug exception handler routine The EJTAG interface operates through the Test Access Port TAP a serial communication port used for transferring test data in and out of the M14K core In addition to the standard JTAG instructions special instructions defined in the EJTAG specification specify which registers are selected and how they are used Debug Registers Four debug regi
281. ion instructions available in Release 2 the preferred method to eliminate hazards is to place one of the instructions listed in Table 2 8 between the producer and consumer of the hazard Execution hazards can be removed by using the EHB JALR HB or JR HB instructions Instruction hazards can be removed by using the JALR HB or JR HB instructions in conjunction with the SYNCI instruction Since the M14K core does not contain caches the SYNCI instruction is not strictly necessary but is still recommended to create portable code that can be run on other MIPS processors that may contain caches MIPS32 M14K Processor Core Software User s Manual Revision 02 03 49 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Pipeline of the M14K Core 50 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management of the M14K Core The M14K processor core includes a Memory Management Unit MMU that interfaces between the execution unit and the cache controller The core implements a simple Fixed Mapping FM style MMU This chapter contains the following sections e Section 3 1 Introduction e Section 3 2 Modes of Operation e Section 3 3 Fixed Mapping MMU e Section 3 4 System Control Coprocessor 3 1 Introduction The MMU will translate any virtual address to a physical address before a request is
282. ion multiplies two unsigned words and subtracts the result from the HI LO register pair The 32 bit word value in the GPR rs is multiplied by the 32 bit value in the GPR rt treating both operands as unsigned values to produce a 64 bit result The product is subtracted from the 64 bit concatenated values in the HI and LO reg ister pair The resulting value is then written back to the HI and LO registers No arithmetic exception occurs under any circumstances 9 7 7 MUL Multiply Word The MUL instruction multiplies two words and writes the result to a GPR The 32 bit word value in the GPR rs is multiplied by the 32 bit value in the GPR rt treating both operands as signed values to produce a 64 bit result The least significant 32 bits of the product are written to the GPR rd The contents of the HI and LO register pair are not defined after the operation No arithmetic exception occurs under any circumstances 9 7 8 SSNOP Superscalar Inhibit NOP The MIPS32 M14K processor cores treat this instruction as a regular NOP 9 8 MCU ASE Instructions The MCU ASE includes some new instructions which are particularly useful in microcontroller applications 9 8 1 ACLR This instruction allows a bit within an uncached I O control register to be atomically cleared that is the read modify byte write sequence performed by this instruction cannot be interrupted 9 8 2 ASET This instruction allows a bit within an uncached I O control register to be atomi
283. ion register scan protocol During an Instruc tion register scan operation the TAP controller selects the output of the Instruction register to drive the TDO pin The shift register consists of a series of bits arranged to form a single scan path between TD and TDO During an Instruc tion register scan operations the TAP controls the register to capture status information and shift data from TDI to TDO Both the capture and shift operations occur on the rising edge of TCK However the data shifted out from the MIPS32 M14K Processor Core Software User s Manual Revision 02 03 197 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core TDO occurs on the falling edge of TCK In the Test Logic Reset and Capture IR state the instruction shift register is set to 00001 as for the IDCODE instruction This forces the device into the functional mode and selects the Device ID register The Instruction register is 5 bits wide The instruction shifted in takes effect for the following data regis ter scan operation A list of the implemented instructions are listed in Table 8 28 8 5 2 Data Registers Overview The EJTAG uses several data registers which are arranged in parallel from the primary TDl input to the primary TDO output The Instruction register supplies the address that allows one of the data registers to be accessed during a data register scan operation During a data register scan
284. ion with the LL SC atomic read modify write semaphore instructions Sync Mechanism The interface includes a protocol that externalizes the execution of the SYNC instruction External logic might choose to use this information to enforce memory ordering between various elements in the system External Call Indication The instruction fetch interface contains signals that indicate that the core is fetching the target of a subroutine call type instruction such as JAL or BAL At some point after a call there will typically be a return to the original code sequence If a system prefetches instructions it can make use of this information to save instructions that were prefetched and are likely to be executed after the return 1 2 1 7 Power Management The core offers a number of power management features including low power design active power management and power down modes of operation The core is a static design that supports a WAIT instruction designed to signal the rest of the device that execution and clocking should be halted hence reducing system power consumption during idle periods The core provides two mechanisms for system level low power support Register controlled power management e nstruction controlled power management In register controlled power management mode the core provides three bits in the CPO Status register for software control of the power management function and allows interrupts to be serviced even when the cor
285. ions in alphabetical order Instructions that have implementation dependent behavior are described afterwards The descriptions for other instructions exist in the architecture reference manual and are not duplicated here Table 10 10 Instruction Set Instruction Description Function ADD Integer Add Rd Rs Rt ADDI Integer Add Immediate Rt Rs Immed ADDIU Unsigned Integer Add Immediate Rt Rs y Immed ADDU Unsigned Integer Add Rd Rs y Rt AND Logical AND Rd Rs amp Rt ANDI Logical AND Immediate Rt Rs amp 046 ll Immed ACLR Atomic Bit Clear See MCU ASE Instructions ASET Atomic Bit Set See MCU ASE Instructions B Unconditional Branch PC int offset Assembler idiom for BEQ r0 r0 offset BAL Branch and Link GPR 31 PC 8 Assembler idiom for BGEZAL r0 offset PC int offset 242 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 10 3 MIPS32 Instruction Set for the M14K core Table 10 10 Instruction Set Continued Instruction Description Function BC2F BC2FL BC2T Branch On COP2 Condition False Branch On COP2 Condition False Likely Branch On COP2 Condition True if COP2Condition cc PC int offset if COP2Condition cc PC int offset else Ignore Next Instruction if COP2Condition cc PC int offset BC2TL Branch On COP2 Condition True Like
286. is not enabled and when the bit value is 1 then PC sampling is enabled and the counters are operational 162 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints Table 8 1 DCR Register Field Descriptions Continued Fields Read Reset Name Bits Description Write State IntE 4 Hardware and software interrupt enable for Non Debug R W 1 Mode in conjunction with other disable mechanisms Encoding Meaning 0 Interrupt disabled 1 Interrupt enabled depending on other enabling mechanisms NMIE 3 Non Maskable Interrupt NMI enable for Non Debug R W 1 Mode Encoding Meaning 0 NMI disabled 1 NMI enabled NMIpend 2 Indication for pending NMI R 0 Encoding Meaning 0 No NMI pending 1 NMI pending SRstE 1 Soft Reset Enable R W This bit allows the system to mask soft resets The core does not internally mask soft resets Rather the state of this bit appears on the EJ_SAstE external output signal allowing the system to mask soft resets if desired ProbEn 0 Probe Enable This bit reflects the ProbEn bit in the R Same value EJTAG Control register as ProbEn in ECR Encoding Meaning see Table 0 No accesses to dmseg allowed 9 4 1 EJTAG probe services accesses to dmseg 0 31 30 Must be written as zeros return zeros on
287. is some general complex break behavior that is common to all complex breakpoints This behavior is described below e Resets to a disabled state when the core is reset the complex break functionality will be disabled and debug software that is not aware of complex break should continue to function normally e Complex break state is not updated on exceptional instructions e Complex breakpoints are evaluated at the end of the pipeline and complex breakpoint exceptions are taken imprecisely on the following instruction e There is no hazard between enabling and enabled events When an instruction causes an enabling event the fol lowing instruction sees the enabled state and reacts accordingly MIPS32 M14K Processor Core Software User s Manual Revision 02 03 187 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core 188 8 3 3 Usage of Pass Counters Pass counters specify that the breakpoint conditions must match N times before the breakpoint action will be enabled e Controlled by writing to the per breakpoint pass counter register e Resets to 0 e Writing to a non zero value enables the pass counter When enabled each time the breakpoint conditions match the counter will be decremented by 1 After the counter value reaches 0 the breakpoint action breakpoint excep tion trigger or complex break enable will occur on any subsequent matches and the counter will not decreme
288. ister Encoding Meaning 0 The RIE and XIE bits are not imple mented within the PageGrain register 1 The RIE and XIE bits are implemented within the PageGrain register ITL 8 Indicates that iFlowTrace hardware is present R Preset MIPS32 M14K Processor Core Software User s Manual Revision 02 03 129 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core Table 5 27 Config3 Register Field Descriptions Continued Fields Name Bits Description Read Write Reset State LPA i Denotes the presence of support for large physical addresses on R Preset MIPS64 processors Not used by MIPS32 processors and returns Zero on read Encoding Meaning 0 Large physical address support is not implemented 1 Large physical address support is implemented For implementations of Release 1 of the Architecture this bit returns zero on read VEIC 6 Indicates support for an external interrupt controller R Externally Set Encoding Meaning 0 Support for EIC interrupt mode is not implemented 1 Support for EIC interrupt mode is implemented The value of this bit is set by the static input S _E CPresent This allows external logic to communicate whether an external interrupt controller is attached to the processor or not VInt 5 Indicates implementation of Vectored interrupts R 1 Encoding Meaning 0 Vector interrupts are not i
289. ister was last written to a non zero value It will remain imprecise until this register is written to 0 by soft ware 8 2 7 9 Data Value Match DVM Register 0x2ffo Compliance Level Implemented only if data breakpoints are implemented The Data Value Match DVM register captures the data value of a load that takes a precise data value breakpoint This allows debug software to synthesize the load instruction without re executing it in case it is to a system register that has destructive reads Figure 8 17 DVM Register Format 31 0 LDV Table 8 19 DVM Register Field Descriptions Fields Bit s Description Read W Name rite Reset State LDV Load data value for the last precise load data value R Undefined breakpoint taken MIPS32 M14K Processor Core Software User s Manual Revision 02 03 181 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core 8 2 8 Complex Breakpoint Registers The registers for complex breakpoints are described Table 8 20 These registers have implementation information and are used to setup the data breakpoints All registers are in drseg Table 8 20 Addresses for Complex Breakpoint Registers Register Offset in drseg Mnemonic Register Name and Description 0x1120 0x100 n IBCCn Instruction Breakpoint Complex Control n described above with instruction bre
290. it is sampled in the Capture DR state of the TAP controller Res 2 0 reserved R 0 8 5 3 Processor Access Address Register The Processor Access Address PAA register is used to provide the address of the processor access in the dmseg and the register is only valid when a processor access is pending The length of the Address register is 32 bits and this register is selected by shifting in the ADDRESS instruction 8 5 3 1 Processor Access Data Register The Processor Access Data PAD register is used to provide data value to and from a processor access The length of the Data register is 32 bits and this register is selected by shifting in the DATA instruction The register has the written value for a processor access write due to a CPU store to the dmseg and the output from this register is only valid when a processor access write is pending The register is used to provide the data value fora processor access read due to a CPU load or fetch from the dmseg and the register should only be updated with a new value when a processor access write is pending The PAD register is 32 bits wide Data alignment is not used for this register so the value in the PAD register matches data on the internal bus The undefined bytes for a PA write are undefined and for a PAD read then 0 zero must be shifted in for the unused bytes The organization of bytes in the PAD register depends on the endianess of the core as shown in Figure
291. l input indicates which interrupt pin is has been combined with and this information is reflected in the ntCtllPFDCI field Note that this interrupt is a regular interrupt and not a debug interrupt The FDC Configuration Register see Section 8 10 6 2 FDC Configuration FDCFG Register Offset Ox8 includes fields for enabling and setting the threshold for generating each interrupt Receive and transmit interrupt thresholds are specified independently but they are ORed together to form a single interrupt The following interrupt thresholds are supported e Interrupts Disabled No interrupt will be generated and software must poll the status registers to determine if incoming data is available or if there is space for outgoing data e Minimum M14K Overhead This setting minimizes the M14K overhead by not generating an interrupt until the receive FIFO RxFIFO is completely full or the transmit FIFO TxFIFO is completely empty Minimum latency To have the MIAK take data as soon as it is available the receive interrupt can be fired when ever the RxFIFO is not empty There is a complimentary TxFIFO not full setting although that may not be quite as useful e Maximum bandwidth When configured for minimum M14K overhead bandwidth between the probe and M14K can be wasted if the M14K does not service the interrupt before the next transfer occurs To reduce the chances of this happening the interrupt threshold can be set to almost full or al
292. le hardware breakpoints on virtual addresses SI AD 6I 2D 41 2D 21 1D breakpoints or no breakpoints e Optional complex hardware breakpoints with 81 4D 6I 2D simple breakpoints e TAP controller is chainable for multi CPU debug 18 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 1 2 M14K Core Block Diagram e Support EJTAG IEEE 1149 1 and compatible with cJTAG 2 wire IEEE 1149 7 extension protocol e Cross CPU breakpoint support e iFlowtrace support for real time instruction PC and special events e PC and or load store address sampling for profiling e Performance Counters e Support for Fast Debug Channel FDC e SecureDebug e An optional feature that disables access via EJTAG in an untrusted environment e Testability e Full scan design achieves test coverage in excess of 99 dependent on library and configuration options 1 2 M14K Core Block Diagram The M14K core contains both required and optional blocks as shown in the block diagram in Figure 1 Required blocks are the lightly shaded areas of the block diagram and are always present in any core implementation Optional blocks may be added to the base core depending on the needs of a specific implementation The required blocks are as follows e Execution Unit e General Proposed Registers GPR e Multiply Divide Unit MDU e System Control Coprocessor CPO e Memory Managem
293. lid 1 0 read data 0 SPrAcc 1 valid data 0 X none unchanged 0 invalid There is no restriction on the contents of the Data register It is expected that the transfer size is negotiated between the download upload transfer code and the probe software Note that the most efficient transfer size is a 32 bit word The Rocc bit of the Control register is not used for the FASTDATA operation 8 6 TAP Processor Accesses 208 The TAP modules support handling of fetches loads and stores from the CPU through the dmseg segment whereby the TAP module can operate like a slave unit connected to the on chip bus The core can then execute code taken from the EJTAG Probe and it can access data via a load or store which is located on the EJTAG Probe This occurs MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 6 TAP Processor Accesses in a serial way through the EJTAG interface the core can thus execute instructions e g debug monitor code without occupying the memory Accessing the dmseg segment EJTAG memory can only occur when the processor accesses an address in the range from OxFF20 0000 to OxFF2F FFFF the ProbEn bit is set and the processor is in debug mode DM 1 In addition the LSNM bit in the CPO Debug register controls transactions to from the dmseg When a debug exception is taken while the ProbTrap bit is set the pro
294. ligned with an executed instruction A breakpoint match depends on the virtual address of the executed instruction PC which can be masked at bit level The registers for each instruction breakpoint have the values and mask used in the compare and the equation that determines the match is shown below in C like notation IB_match all 1 s gt IBMnypy PC lBAngga The match indication for instruction breakpoints is always precise i e indicated on the instruction causing the IB_ match to be true Address Range Cores may optionally support the address range triggered instruction breakpoints When this feature is configured the following changes are made to the instruction breakpoint registers e BAn represents the upper limit of a address range boundary e BMn represents the lower limit of the address range boundary In addition the following bits must be supported IBCn 6 hwarts a preset value of 1 indicates that the address range triggered instruction breakpoint feature is sup ported for this particular instruction breakpoint channel This bit is read only MIPS32 M14K Processor Core Software User s Manual Revision 02 03 165 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core 166 IBCn 5 excl a value of 0 indicates that the breakpoint will match for addresses inclusive within the range defined by IBMn and IBAn A value of 1 indicates t
295. lue is a waste of power Hence when in a WAIT state the processor must simply switch the New bit to 1 each time it is set to 0 by the probe hardware Hence the external agent or probe reading the PC value will detect a WAIT instruction for as long as the processor remains in the WAIT state When the processor leaves the WAIT state then counting is resumed as before 8 9 2 Data Address Sampling EJTAG revision 5 0 extends the PC sampling mechanism to allow sampling of data load and store addresses This feature is enabled with DASe bit 23 in the Debug Control Register When enabled the PCSAMPLE scan register includes a data address sample All load and store addresses can be captured or they can be qualified using a data breakpoint trigger DASQ 1 configures data sampling to record a data address only when it triggers data breakpoint 0 To be used for Data Address Sampling qualification data breakpoint 0 must be enabled using its TE trigger enable bit PCSR controls how often data addresses are sampled When the PCSR counter triggers the most recent load store address generated is accepted and made available to shift out through PCSAMPLE 8 10 Fast Debug Channel 224 The Fast Debug Channel FDC mechanism provides an efficient means to transfer data between the M14K and an external device using the EJTAG TAP pins The external device would typically be an EJTAG probe and that is the term used here but it could be something else FDC ut
296. ly if COP2Condition cc 1 PC int offset else Ignore Next Instruction BEQ BEQL Branch On Equal Branch On Equal Likely if Rs Rt PC int offset if Rs Rt PC int offset else Ignore Next Instruction BGEZ BGEZAL BGEZALL BGEZL Branch on Greater Than or Equal To Zero Branch on Greater Than or Equal To Zero And Link Branch on Greater Than or Equal To Zero And Link Likely Branch on Greater Than or Equal To Zero Likely if Rs 31 PC int offset GPR 31 PC 8 if Rs 31 PC int offset GPR 31 PC 8 if Rs 31 PC int offset else Ignore Next Instruction if Rs 31 PC int offset else Ignore Next Instruction BGTZ BGTZL BLEZ Branch on Greater Than Zero Branch on Greater Than Zero Likely Branch on Less Than or Equal to Zero if Rs 31 amp amp Rs 0 PC int offset if Rs 31 amp amp Rs 0 PC int offset else Ignore Next Instruction if Rs 31 ll Rs 0 PC int offset BLEZL Branch on Less Than or Equal to Zero Likely if Rs 31 ll Rs PC int offset else Ignore Next Instruction BLITZ Branch on Less Than Zero MIPS32 M14K Processor Core Software User s Manual Revision 02 03 if Rs 31 PC int offset Copyright 2009 2010 MIPS Technologies Inc All rights reserved 243 M14K Processor Core Instructions Table 10 10 Instruction Set Continued
297. mes Bits Data 63 0 Trace Word o Undefined 220 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 8 6 3 ITCBRDP Register Offset 0x3f88 8 8 iFlowtrace Mechanism The TCBRDP register is the address pointer to on chip trace memory It points to the TW read when reading the TCBTW register This value will be automatically incremented after a read of the TCBTW register The format of the TCBADP register is shown below and the field is described in Table 8 39 The value of n depends on the size of the on chip trace memory As the address points to a 64 bit TW lower three bits are always zero Figure 8 33 ITCBRDP Register Format 31 n l n 0 Address Table 8 39 ITCBRDP Register Field Descriptions Fields Description Read Reset Compliance Write State Names Data 31 n 1 Reserved Must be written zero reads back zero 0 0 Required Address n 0 Byte address of on chip trace memory word R W Undefined Required 8 8 6 4 ITCBWRP Register Offset 0x3f90 The TCBWRP register is the address pointer to on chip trace memory It points to the location where the next new TW for on chip trace will be written The top bit in the register indicates whether the pointer has wrapped If it has then the write pointer will also point to the oldest trace word and the read pointer can be set to that to read
298. microMIPS architecture because instructions can be either 16 or 32 bits in size the jump and branch target addresses are halfword 16 bit aligned Branch jump offset fields are shifted left by only one bit to create half word aligned effective addresses To maintain the existing MIPS32 ABIs link unit object file entry points are restricted to 32 bit word alignments In the future a microMIPS only ABI can be created to remove this restriction 1 7 Coprocessor Unusable Behavior If an instruction associated with a non implemented coprocessor is executed it is implementation specific whether a processor executing in microMIPS mode raises an RI exception or a coprocessor unusable exception While in micro MIPS mode the M14K has the same behavior as in MIPS32 mode coprocessor unusable exceptions will be raised Instruction Formats This section defines the formats of microMIPS instructions The microMIPS variable length encoding comprises 16 bit and 32 bit wide instructions The 6 bit major opcode is left aligned within the instruction encoding Instructions can have 0 to 4 register fields For 32 bit instructions the register field width is 5 bits while for most 16 bit instructions the register field width is 3 bits utilizing instruction specific register encoding All 5 bit register fields are located at a constant position within the instruction encoding MIPS32 M14K Processor Core Software User s Manual Revision 02 03 277 Co
299. mine the required access The EJTAG Probe selects the PA Address register and shifts out the requested address The EJTAG Probe selects the PA Data register and shifts out the data to be written The EJTAG Probe selects the EJTAG Control register and shifts a PrAcc 0 bit into this register to indicate to the processor that the write access is finished The EJTAG Probe writes the data to the requested address in its memory 10 The processor detects that PrAcc bit 0 which means that it is ready to handle a new access The above examples imply that no reset occurs during the operations and that Hocc is cleared Note Probe accesses and external bus accesses are serialized by the core A probe access will not begin until all external bus requests have completed Similarly a new probe or external bus access will not begin until a pending probe access has completed 8 7 SecureDebug For security reasons users can optionally disable certain EJTAG capabilities via the SecureDebug feature in order to prevent untrusted access to the core through debug mode 8 7 1 Disabling EJTAG debugging 8 7 1 1 EJ DisableProbeDebug Signal An input signal to the core is defined EJ DisableProbeDebug which when asserted forces ProbEn 0 and Prob Trap 0 EJ DisableProbeDebug overrides any other ProbEn or ProbTrap settings 210 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All
300. mode upon handling an exception is determined by the setting of the Config3 saoneExc register field bit 16 The Config3 sAonExc register field is write able by software and has a reset value that is set by a hardware signal external to the processor core This register field allows privileged software to change the ISA mode to be used for subsequent exceptions This capability is for all exception types whose vectors are offsets of the EBASE register For implementations that support both microMIPS and MIPS32 the selected ISA mode when handling a debug exception is determined by the setting of the ISAonDebug register field in the EJTAG TAP Control register This reg ister field is writeable by EJTAG probe software and has a reset value that is set by a hardware signal external to the processor core For CPU cores supporting the MT ASE and multiple VPEs the ISA mode for exceptions can be selected on a per VPE basis 11 1 3 Software Detection Software can determine if microMIPS is implemented by checking the state of the ISA Instruction Set Architecture field in the Config3 CPO register Configic bit 2 is not used for microMIPS Software can determine if the MIPS32 ISA is implemented by checking the state of the ISA Instruction Set Architec ture register field in the Config3 CPO register Software can determine which ISA is used when handling an exception by checking the state of the ISAOnExc ISA on Exception field in the Config3 CP
301. most empty to generate an interrupt earlier This setting causes receive interrupts to be generated when there are 0 or 1 unused RxFIFO entries Transmit interrupts are generated when there are 0 or 1 used TxFIFO entries see note in following section about this con dition 8 10 3 M14K M14K FDC Buffers Figure 8 36 shows the general organization of the transmit and receive buffers on the M14K M14K MIPS32 M14K Processor Core Software User s Manual Revision 02 03 225 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Figure 8 36 Fast Debug Channel Buffer Organization Store Address Store Data to FDTXn Load from FDSTAT Load from FDRX Addr Decode A r RXFIFO C Chan Data OOO Chan Data S Clkin 226 EJ TCK Chan Data a p Capture DR fpdate DR EJ TDI EJ TDO Status Control Logic One particular thing to note is the asynchronous crossings between the EJ TCK and SI Clkln clock domains This crossing is handled with a handshake interface that safely transfers data between the domains Two data registers are included in this interface one in the source domain and one in the destination domain The control logic actively manages these registers so that they can be used as FIFO entries The fact that one FIFO entry is i
302. mplemented 1 Vectored interrupts are implemented On the M14K core this bit is always a 1 because vectored inter rupts are implemented SP 4 When set indicates that Small 1KByte page support is imple R 0 mented Encoding Meaning 0 Small page support is not implemented 1 Small page support is implemented CDMM 3 Common Device Memory Map implemented This bit indicates R Preset whether the CDMM is implemented Encoding Meaning 0 CDMM is not implemented 1 CDMM is implemented 130 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 27 Config3 Register Field Descriptions Continued Fields Name Bits Description Read Write Reset State SM SmartMIPS ASE implemented This bit indicates whether the SmartMIPS ASE is implemented Because SmartMIPS isnot present on the M14K core this bit will always be 0 Encoding Meaning 0 SmartMIPS ASE is not implemented 1 SmartMIPS ASE is implemented TL Trace Logic implemented This bit indicates whether PC or data trace is implemented Encoding Meaning 0 Trace logic is not implemented 1 Trace logic is implemented 5 2 24 Configuration Register 4 CPO Register 16 Select 4
303. n Fields Power up SPrAcc Shifting in a zero value requests completion of the Fast R W Undefined data access The PrAcc bit in the EJTAG Control register is Overwritten with zero when the access succeeds The access succeeds if PrAcc is one and the operation address is in the legal dmseg Fastdata area When successful a one is shifted out Shifting out a zero indicates a Fastdata access failure Shifting in a one does not complete the Fastdata access and the PrAcc bit is unchanged Shifting out a one indi cates that the access would have been successful if allowed to complete and a zero indicates the access would not have successfully completed MIPS32 M14K Processor Core Software User s Manual Revision 02 03 207 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core The FASTDATA access is used for efficient block transfers between dmseg on the probe and target memory on the processor An upload is defined as a sequence of processor loads from target memory and stores to dmseg A download is a sequence of processor loads from dmseg and stores to target memory The Fastdata area specifies the legal range of dmseg addresses OxFF20 0000 OxFF20 000F that can be used for uploads and downloads The Data Fastdata registers selected with the FASTDATA instruction allow efficient completion of pending Fastdata area accesses During Fastdata uploa
304. n Coprocessor 2 Exception enne 89 4 8 18 Execution Exception Implementation Specific 1 Exception sssseeees 89 4 8 19 Execution Exception Integer Ove TOW sa cerner tese d aeta in Rye netu epe ne MESS IR e Eod DARE 90 48 20 y etceenteme ace ceeetescsan eE E e EAEN 90 4821 Debug Data Break Exo piosse AR 90 19 22 Complex Break EXCODIGEE eaaet preset E EEEE ERO EENAA EA NECN rsen edu aud 91 4 9 Exception Handling and Servicing FIOWCIAFIS iouis seedageseidsteagss ne adtacadas tee Ep brasdn eir tta dad C ad DS Ire ndeS 91 Chapter 5 CPO Registers of the M14K Core eeeeeseeeeeeeeeeeeee esee eene nennen nnne nnne nnn 95 Bile CPO Register SUMUMANY esci ec aote iu ees cux oer IUe A sx Els tpe sva tust pas Fa dba px a Sina cei ERI Seb R cub dU 95 5 2 CPO Register Descriptions sisinio dania Rub Ea EHE e d dA uoa dI aiaa ed RE Vk EUER ha dG 97 52 1 Userbocal Register CPO Register 4 Select 2 tieniti uberi id POR neha 97 5 2 2 HW REna Register GPO Register 7 Select U io irme oec oret sedere aita Sapete ctae area 98 5 2 9 BadVAddr Register CPO Register 8 Select 0 cei iiiter tonat ced bak Dered ed tnc tex ewe ddec 99 5 2 4 Count Register CPO Register 9 Select 0 ssssssssssssssseeeeee enne 99 5 2 5 Compare Register CPO Register 11 Select 0 sessssssssssseseeeee enne tnnt 100 5 2 6 Stat s Register CPO Register 12 Select 0
305. n Exception Coprocessor Unusable The coprocessor unusable exception is one of the nine execution exceptions All of these exceptions have the same priority A coprocessor unusable exception occurs when an attempt is made to execute a coprocessor instruction for one of the following e acorresponding coprocessor unit that has not been marked usable by setting its CU bit in the Status register e CPO instructions when the unit has not been marked usable and the processor is executing in user mode Cause Register ExcCode Value CpU 88 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 8 Exception Descriptions Additional State Saved Table 4 13 Register States on a Coprocessor Unusable Exception Causecg Unit number of the coprocessor being referenced Entry Vector Used General exception vector offset 0x180 4 8 16 Execution Exception CorExtend Unusable The CorExtend unusable exception is one of the nine execution exceptions All of these exceptions have the same pri ority A CorExtend Unusable exception occurs when an attempt is made to execute a CorExtend instruction when Statuscgg is cleared It is implementation dependent whether this functionality is supported Generally the function ality will only be supported if a CorExtend block contains local destination registers Cause Register ExcCode Value CEU Additional State
306. n Read Write Reset State Res 3 Must be written as zero returns zero on reads R 0 TE 2 Use data breakpoint n as triggerpoint R W 0 Encoding Meaning 0 Don t use it as triggerpoint 1 Use it as triggerpoint IVM 1 Invert Value Match When set the data value compare R W 0 will be inverted i e a break or trigger will be taken if the value does not match the specified value BE 0 Use data breakpoint n as breakpoint R W 0 Encoding Meaning 0 Don t use it as breakpoint 1 Use it as breakpoint 8 2 7 6 Data Breakpoint Value n DBVn Register 0x2120 0x100 n Compliance Level Implemented only for implemented data breakpoints The Data Breakpoint Value n DBVn register has the value used in the condition for data breakpoint n Figure 8 14 DBVn Register Format 31 0 DBV Table 8 16 DBVn Register Field Descriptions Fields Read Wr Name Bit s Description ite Reset State DBV 31 0 Data breakpoint value for condition R W Undefined 8 2 7 7 Data Breakpoint Complex Conirol n DBCCn Register 0x2128 n 0x100 Compliance Level Implemented only if complex breakpoints are implemented and only for implemented data breakpoints The Data Breakpoint Complex Control n DBCCn register controls the complex break conditions for data breakpoint n MIPS32 M14K Processor Core Software User s Manual Revision 02 03 179 Copyright
307. n the EJ TCK clock domain is normally transparent but it can create some unexpected behavior Shift Register e TxFIFO availability Data is first written into the S _C k FIFO entries then into the EJ TCK FIFO entry requir ing several EJ TCK cycles to complete the handshake and move the data EJ TCK is generally much slower than SI ClkIn and may even be stopped although that would be uncommon when this feature is in use This can result in not enough space for new data even though there are only N 1 data values queued up To prevent the loss of data the TxF flag in FDSTAT is set when all of the S ClkIn FIFO entries are full Software writes to the FIFO should always check the TxF bit before attempting the write and should not make any assumptions about being able to use all entries arbitrarily i e software seeing the FxE bit set should not assume that it can write TxCnt data words without checking for full TxFIFO Almost Empty Interrupt As transmit data moves from S ClkInto EJ TCK both of the flops will tem porarily look full This makes it difficult to determine when just 1 FIFO entry is in use To enable a simpler con dition the almost empty TxInterrupt condition is set when all of the S ClkIn FIFO entries are empty When this MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 10 Fast Debug Channel condition is met there will be O or 1
308. ncident was detected The EJTAG Control register is not updated in the Update DR state unless Rocc is 0 or written to 0 This is in order to ensure proper handling of processor access These bits are used in combination with the lower two address bits of the Address register to determine the size of a processor access transaction The bits are only valid when processor access is pending PAA 1 0 Psz 1 0 00 00 Transfer Size Byte LE byte 0 BE byte 3 Byte LE byte 1 BE byte 2 Byte LE byte 2 BE byte 1 Byte LE byte 3 BE byte 0 Halfword LE bytes 1 0 BE bytes 3 2 Halfword LE bytes 3 2 BE bytes 1 0 Word LE BE bytes 3 2 1 0 Triple LE bytes 2 1 0 BE bytes 3 2 1 Triple LE bytes 3 2 1 BE bytes 2 1 0 Reserved 01 00 10 00 11 00 00 01 10 01 00 10 00 11 01 11 All others Note LE little endian BE big endian the byte refers to the byte number in a 32 bit register where byte 3 bits 31 24 byte 2 bits 23 16 byte 1 bits 15 8 byte O bits 7 0 independently of the endianess Reset Occurred R W Processor Access Transfer Size R Undefined Res MIPS32 M14K Processor Core Software User s Manual Revision 02 03 reserved R 201 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Table 8 31 EJTAG Control R
309. nd its trace format outputs differ from those of PDtrace Trace formats using simplified instruction state descriptors were designed for the iFlowtrace trace to simplify the trace mechanism and to obtain better compression Tracing is disabled if the processor enters Debug Mode refer to the EJTAG specification for description of Debug Mode This is true for both Normal Trace Mode as well as Special Trace Mode The presence of the iFlowtrace mechanism is indicated by the CPO Config3 7 register bit 8 8 1 A Simple Instruction Only Tracing Scheme A trace methodology can often be mostly defined by its inputs and outputs Hence this basic scheme is described by the inputs to the core tracing logic and by the trace output format from the core We assume here that the execution flow of the program is traced at the end of the execution path in the core similar to PDtrace 8 8 1 1 Trace Inputs 1 In_TraceOn when on legal trace words are coming from the core and at the point when it is turned on that is for the first traced instruction a full PC value is output When off it cannot be assumed that legal trace words are available at the core interface In Stall This says stall the processor to avoid buffer overflow that can lose trace information When off a buffer overflow will simply throw away trace data and start over again When on the processor is signalled from the tracing logic to stall until the buffer is sufficiently drained and th
310. ndicates that the processor was in any kind of low R Undefined power mode when a debug exception occurred Encoding Meaning 0 Processor not in low power mode when debug exception occurred 1 Processor in low power mode when debug exception occurred Halt 26 Indicates that the internal system bus clock was stopped R Undefined when the debug exception occurred Encoding Meaning 0 Internal system bus clock stopped 1 Internal system bus clock running 134 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 31 Debug Register Field Descriptions Continued Fields Name Bit s Description Read Write Reset State CountDM 25 Indicates the Count register behavior in debug mode Encoding Meaning 0 Count register stopped in debug mode 1 Count register is running in debug mode R W 1 IBusEP MCheckP 24 23 Instruction fetch Bus Error exception Pending Set when an instruction fetch bus error event occurs or if a 1 is written to the bit by software Cleared when a Bus Error exception on an instruction fetch is taken by the proces sor and by reset If BusEP is set when EXI is cleared a Bus Error exception on an instruction fetch is taken by the processor and BusEP is cleared Indicates that an imprecise Machine Check exception is pending All Mac
311. ng Meaning 0 No debug instruction exception 1 Debug instruction exception DDBS 3 Indicates that a debug data break exception occurred on R Undefined a store Cleared on exception in debug mode Encoding Meaning 0 No debug data exception on a store 1 Debug instruction exception on a store DDBL 2 Indicates that a debug data break exception occurred on R Undefined a load Cleared on exception in debug mode Encoding Meaning 0 No debug data exception on a load 1 Debug instruction exception on a load 136 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 31 Debug Register Field Descriptions Continued Fields Name Bit s Description Read Write Reset State DBp 1 Indicates that a debug software breakpoint exception R Undefined occurred Cleared on exception in debug mode Encoding Meaning 0 No debug software breakpoint excep tion 1 Debug software breakpoint exception DSS 0 Indicates that a debug single step exception occurred R Undefined Cleared on exception in debug mode Encoding Meaning 0 No debug single step exception 1 Debug single step exception 5 2 28 Trace Control Register CPO Register 23 Select 1 The TraceControl register configuration is shown below This register is only implemented if the EJTAG PDTrace capability is prese
312. nologies Inc All rights reserved EJTAG Debug Support in the M14K Core 168 DBCn 8 hwart a value of 0 indicates that the breakpoint will match using the Equality and Mask equation as found in Section 8 2 3 2 Conditions for Matching Data Breakpoints A value of 1 indicates that the breakpoint will match using address ranges using the equation below DB match DBCnTCuse TC DBCnTC amp amp TYPE load amp amp DBCnNoLB TYPE store amp amp DBCnNoSB amp amp DB addr range match amp amp DB no value compare DB value match DB addr range match DBCnASIDuse ASID DBASIDnASID amp amp DBCnhwarts DBCnhwart amp amp DBMnDBM ADDR DBAnDBA 0 DBCnhwarts amp amp DBCnhwart amp amp DBCnexcl amp amp DBMn lt ADDR lt DBAn DBCnexcl amp amp DBMn ADDR ADDR DBAn When address range triggered data breakpoints is enabled DBCn BLM 3 0 must be set to 4 b1111 because value matching is not supported with this feature Addresses that overlap a boundary is considered for both exclusive and inclusive breakpoint matches 8 2 4 Debug Exceptions from Breakpoints Instruction and data breakpoints may be set up to generate a debug exception when the match condition is true as described below 8 2 4 1 Debug Exception by Instruction Breakpoint If the breakpoint is enabled
313. nstructions MIPS32 M14K Processor Core Software User s Manual Revision 02 03 17 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Introduction to the MIPS32 amp M14K Processor Core e Multi Core Support e External lock indication enables multi processor semaphores based on LL SC instructions e External sync indication allows memory ordering e Debug support includes cross core triggers e Multiply Divide Unit high performance configuration e Maximum issue rate of one 32x16 multiply per clock via on chip 32x16 hardware multiplier array e Maximum issue rate of one 32x32 multiply every other clock e Early in iterative divide Minimum 11 and maximum 34 clock latency dividend rs sign extension depen dent e Multiply Divide Unit area efficient configuration e 32 clock latency on multiply e 34 clock latency on multiply accumulate e 33 35 clock latency on divide sign dependent e Full featured Coprocessor 2 Interface e 32 bit interface to an external coprocessor e Power Control e Minimum frequency 0 MHz e Power down mode triggered by WAIT instruction e Support for software controlled clock divider e Support for extensive use of local gated clocks e EJTAG Debug Profiling and iFlowtraceTM Mechanism e CPU control with start stop and single stepping e Virtual instruction and data address value breakpoints e Hardware breakpoint supports both address match and address range triggering e Optional simp
314. nt Must be written as zero returns zero on read Use instruction breakpoint n as breakpoint Encoding Meaning 0 Don t use it as breakpoint 1 Use it as breakpoint 8 2 6 6 Instruction Breakpoint Complex Control n IBCCn Register 0x1120 n 0x100 Compliance Level Implemented only if complex breakpoints are implemented and only for implemented instruction breakpoints The Instruction Breakpoint Complex Control n IBCCn register controls the complex break conditions for instruction breakpoint n MIPS32 M14K Processor Core Software User s Manual Revision 02 03 173 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Figure 8 7 IBCCn Register Format 174 31 14 13 10 9 8 5 4 3 2 1 0 E mes Tempo e aes Table 8 8 IBCCn Register Field Descriptions Fields Name Bits Description Read Write Reset State Res Must be written as zero returns zero on read R 0 PrCnd Upper bits of priming condition for instruction breakpoint R 0 n The M14K core only supports 4 priming conditions so the upper 2 bits are read as 0 PrCnd Priming condition for instruction breakpoint n R W 0 00 Bypass no priming needed Other vary depending on the break number refer to Table 8 10 for mapping CBE Complex Break Enable enables this breakpoint for use R W 0 in a complex sequence as a priming condition for another breakpoint to s
315. nt Figure 5 29 TraceControl Register Format 31 30 29 28 27 26 25 24 23 22 21 20 19 12 5 4 3 1 0 Ts ur 0 TB 1o D E k S u ASID_M ASID c Mode On Table 5 32 TraceControl Register Field Descriptions TS 31 The trace select bit is used to select between the hard R W 0 ware and the software trace control bits A value of zero selects the external hardware trace block signals and a value of one selects the trace control bits in this software control register UT 30 This bit is used to indicate the type of user triggered R W Undefined trace record A value of zero implies a user type 1 and a value of one implies a user type 2 The actual triggering of a user trace record occurs on a write to the UserTraceData register 29 28 Reserved for future use Must be written as zero returns zero on read MIPS32 M14K Processor Core Software User s Manual Revision 02 03 137 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core Table 5 32 TraceControl Register Field Descriptions Continued Fields Description Read Write Reset State Trace All Branch When set to one this tells the pro R W Undefined cessor to trace the PC value for all taken branches not just the ones whose branch target address is statically unpredictable Inhibit Overflow This signal is used to indicate to the core trace logic that slow but complete tracing is d
316. nt further The action does not occur on the match that causes the 1 gt 0 counter decrement e Ifthe breakpoint also has priming conditions and or data qualified specified the pass counter will only decre ment when the priming and or qualified conditions have been met e fa data breakpoint is configured to be a tuple breakpoint the data pass counter will only decrement on instruc tions where both the instruction and data break conditions match The pass counter for the instruction break involved in a tuple should not be enabled if the tuple is enabled e Once a pass counter has been enabled it will be treated as enabled until the pass counter is explicitly written to 0 Namely breakpoint exceptions will continue to be taken imprecisely until the pass counter is disabled by writing to 0 e The counter register will be updated as matches are detected The current count value can be read from the regis ter while operating in debug mode Note that this behavior is architecturally recommended but not required 8 3 4 Usage of Tuple Breakpoints A tuple breakpoint is the logical AND of a data breakpoint and an instruction breakpoint Tuple breakpoints are spec ified as a condition on a data breakpoint If the DBCCnTUP bit is set the data breakpoint will not match unless there the corresponding instruction breakpoint conditions are also met e Uses the data breakpoint resources to specify the break action break status pass counters and pr
317. ntations of Release 1 of the Architecture 104 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 31 5 2 CPO Register Descriptions Figure 5 7 shows the format of the ntCt register Table 5 9 describes the ntCtl register fields 29 28 26 25 23 22 Figure 5 7 IntCtl Register Format 21 20 16 15 14 13 12 10 9 5 4 0 IPTI IPPCI IPFDC PF Clr Use ICE StkDec EXL APE KStk 000 VS 0 Table 5 9 IntCtl Register Field Descriptions Fields Reset Name Bits Description Read Write State IPTI 31 29 For Interrupt Compatibility and Vectored Interrupt Externally modes this field specifies the IP number to which the Set Timer Interrupt request is merged and allows software to determine whether to consider Causey for a poten tial interrupt Hardware Interrupt Encoding Source 2 HWO HWI HW2 HW4 HW5 3 4 5 HW3 6 7 The value of this bit is set by the static input SI IPTI 2 0 This allows external logic to communi cate the specific S Int hardware interrupt pin to which the S Timerlnt signal is attached The value of this field is not meaningful if External Interrupt Controller Mode is enabled The external inter rupt controller is expected to provide this information for that interrupt mode MIPS32 M14K Proces
318. nterrupts are enabled when all of the following conditions are true E 1 e EXL 0 e ERL 0 e DM 0 If these conditions are met then the settings of the M and IE bits enable the interrupts Operating Modes If the DM bit in the Debug register is 1 then the processor is in debug mode otherwise the pro cessor is in either kernel or user mode The following CPU Status register bit settings determine user or kernel mode MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved User mode UM 1 EXL 0 and ERL 0 Kernel mode UM 0 or EXL 1 or ERL 1 5 2 CPO Register Descriptions Coprocessor Accessibility The Status register CU bits control coprocessor accessibility If any coprocessor is unus able then an instruction that accesses it generates an exception Figure 5 6 shows the format of the Status register Table 5 8 describes the Status register fields 31 28 27 26 25 24 23 Figure 5 6 Status Register Format 22 21 20 19 18 17 16 10 9 8 7 6 CU3 CUO RPIFR RE BEV TS SR NMIIM9 CEE IMS8 IM2 IMI IMO UM ERL EXL Fields Name Bits IPL IPL Table 5 8 Status Register Field Descriptions Description Read Write Reset State CU3 31 Controls access to coprocessor 3 COP3 is not supported This bit cannot be written and will read as 0 R
319. nts in the sys tem Restrictions The effect of SYNC on the global order of loads and stores for memory access types other than uncached and cached coherent is UNPREDICTABLE Operation SyncOperation stype Exceptions None 272 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 31 26 25 24 6 5 0 COPO CO WAIT 010000 1 Implementation Dependent Code 100000 6 1 19 6 Format WAIT MIPS32 Purpose Enter Standby Mode Wait for Event Description The WAIT instruction forces the core into low power mode The pipeline is stalled and when all external requests are completed the processor s main clock is stopped The processor will restart when reset S _Reset or S _ColdReset is signaled or a non masked interrupt is taken S NMI SI Int or EJ DINT Note that theM14K core does not use the code field in this instruction If the pipeline restarts as the result of an enabled interrupt that interrupt is taken between the WAIT instruction and the following instruction EPC for the interrupt points at the instruction following the WAIT instruction Restrictions The operation of the processor is UNDEFINED if a WAIT instruction is placed in the delay slot of a branch or a jump If access to Coprocessor 0 is not enabled a Coprocessor Unusable Exception is signaled Operation I Enter lower power mode I 1 Po
320. o an on chip trace buffer e g TraceControl2Zygy 0 Conversely the Off chip column is used when the trace data is being written to an off chip trace buffer e g TraceControl2ygu 1 5 2 30 User Trace Data1 Register CPO Register 23 Select 3 User Trace Data2 Regis ter CPO Register 24 Select 3 A software write to any bits in the UserTraceData1 or UserTraceData2 registers will trigger a trace record to be writ ten indicating a type 1 or type 2 user format respectively The trace output data is UNPREDICTABLE if these regis ters are written in consecutive cycles This register is only implemented if the MIPS iFlowtrace capability is present Figure 5 31 User Trace Data1 User Trace Data2 Register Format 31 0 Data Table 5 34 UserTraceData1 UserTraceData2 Register Field Descriptions Fields Name Bits Description Write Reset State Data Software readable writable data When written this triggers a user format trace record out of the PDtrace interface that transmits the Data field to trace memory MIPS32 M14K Processor Core Software User s Manual Revision 02 03 141 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core 5 2 31 TraceBPC Register CPO Register 23 Select 4 This register is used to start and stop tracing using an EJTAG Hardware breakpoint The Hardware breakpoint can then be set as a trigger source
321. oci tu rcr rrr ride recs tha nace tk pu occae uiua reb N ERR werd bad 83 4 9 39 Debug Interru pt E XxeoepliOD uscite tarte od i exu cnc xU teda a qun a RU RU Qo cR Urt dude ra Ce MER RH a UR REUAIE dE 84 4 8 4 Non Maskable Interrupt NMI EXCODLIOTI ics rior rore Erie ERE E EE ERA 84 4 9 5 Intertmupt EXOSDUODqs da deeds db to cuexor N cea t peak tin ie dom DUM ROPA DE XLI UNE 85 4 8 6 Debug Instruction Break EXCepllOni u dcr bet e rient re became gi peni 85 4 8 7 Address Error Exception Instruction Fetch Data Access ssssssseseeee 85 4 9 9 SRAM Panty Eror EXCODLIlOEs x etu tico aa depu a E AA EER 86 4 8 9 Bus Error Exception Instruction Fetch or Data Access ssessssssssssseeeeeenenn 86 4 9 10 Protection EXCODLODL sisse crainte ena bera pron aa pex KENEEN aaa ANANKE AE 87 4 8 11 Debug Software Breakpoint EXCODLOT cuite necat tati ses enda es eee rna t ku aia 87 48 12 Execution Exception System Galla eter e ot a a a 87 4 8 19 Execution Exception Breampoiit acest ccncessshecededhs Fee adeves stchiulocas bete eSu etui xs boue bidkxE DO AIR ARI teu Dus 88 4 8 14 Execution Exception Reserved Instruction eese nnns 88 4 8 15 Execution Exception Coprocessor Unusable essssssssessssseseenneeee nnne 88 4 8 16 Execution Exception CorExtend Unusable eesesssssssessseses sentent nnne 89 4 8 17 Execution Exceptio
322. of TCK the controller transitions to the Pause DR state A HIGH on TMS causes the controller to transition to the Update DR state which terminates the scanning process The instruction cannot change while the TAP controller is in this state 8 4 2 8 Pause DR State The Pause DR state allows the controller to temporarily halt the shifting of data through the test data register in the serial path between TDI and TDO All test data registers selected by the current instruction retain their previous state If TMS is sampled LOW on the rising edge of TCK the controller remains in the Pause DR state A HIGH on TMS causes the controller to transition to the Exit2 DR state The instruction cannot change while the TAP controller is in this state 8 4 2 9 Exit2 DR State This is a temporary controller state in which all test data registers selected by the current instruction retain their previ ous state If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Shift DR state to allow another serial shift of data A HIGH on 7MS causes the controller to transition to the Update DR state which termi nates the scanning process The instruction cannot change while the TAP controller is in this state 8 4 2 10 Update DR State When the TAP controller is in this state the value shifted in during the Shift DR state takes effect on the rising edge of the TCK for the register indicated by the Instruction register If TMS is sampled LOW a
323. of the ErrorEPC register are significant and must be writable It is also used to store the program counter on Reset Soft Reset and nonmaskable interrupt NMJ exceptions The ErrorEPC register contains the virtual address at which instruction processing can resume after servicing an error This address can be e The virtual address of the instruction that caused the exception e The virtual address of the immediately preceding branch or jump instruction when the error causing instruction is in a branch delay slot Unlike the EPC register there is no corresponding branch delay slot indication for the ErrorEPC register In processors that implement microMIPS a read of the ErrorEPC register via MFCO returns the following value in the destination GPR GPR rt lt ErrorExceptionPC3 ISAModeg That is the upper 31 bits of the error exception PC are combined with the lower bit of the SAMode field and written to the GPR Similarly a write to the ErrorEPC register via MTCO takes the value from the GPR and distributes that value to the error exception PC and the SAMode field as follows ErrprExceptionPC GPR rt 3 4 0 ISAMode lt 2 0 GPR rtlo That is the upper 31 bits of the GPR are written to the upper 31 bits of the error exception PC and the lower bit of the error exception PC is cleared The upper bit of the SAMode field is cleared and the lower bit is loaded from the lower bit of the GPR
324. of the value of Status x Not updated by exception types which update ErrorEPC Reset Soft Reset NMI Cache Error Not updated by Debug exceptions 0 0 Reserved read as 0 RO 0 Required 5 2 15 Exception Program Counter CPO Register 14 Select 0 The Exception Program Counter EPC is a read write register that contains the address at which processing resumes after an exception has been serviced AII bits of the EPC register are significant and must be writable For synchronous precise exceptions the EPC contains one of the following e The virtual address of the instruction that was the direct cause of the exception MIPS32 M14K Processor Core Software User s Manual Revision 02 03 119 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core 120 e The virtual address of the immediately preceding branch or jump instruction when the exception causing instruction is in a branch delay slot and the Branch Delay bit in the Cause register is set On new exceptions the processor does not write to the EPC register when the EXL bit in the Status register is set however the register can still be written via the MTCO instruction In processors that implement microMIPS a read of the EPC register via MFCO returns the following value in the destination GPR GPR rt ExceptionPC3 ISAMode That is the upper 31 bits of the exception PC are combin
325. oftware may be modified to be compatible with both Release 1 and Release 2 implementations See the EHB instruction description for additional information The JALR HB and JR HB instructions are encoding using bit 10 of the hint field of the JALR and JR instructions These encodings were chosen for compatibility with existing MIPS implementations including many which pre date the MIPS32 architecture Because a pipeline flush clears hazards on most early implementations the JALR HB or JR HB instructions can be included in existing software for backward and forward compatibility See the JALR HB and JR HB instructions for additional information The SYNCI instruction is encoded using a new encoding of the REGIMM opcode This encoding was chosen because it causes a Reserved Instruction exception on all Release 1 implementations As such kernel software run ning on processors that don t implement Release 2 can emulate the function using the CACHE instruction 2 11 3 Eliminating Hazards The Spacing column shown in Table 2 6 and Table 2 7 indicates the number of unrelated instructions such as NOPs or SSNOPs that prior to the capabilities of Release 2 would need to be placed between the producer and consumer of the hazard in order to ensure that the effects of the first instruction are seen by the second instruction Entries in the table that are listed as 0 are traditional MIPS hazards which are not hazards on the M14K core With the hazard eliminat
326. on can be shifted out for inspection and new data shifted in Follow ing the Shift state the TAP either returns to the Run Test Idle state via the Exit and Update states or enters the Pause state via Exit The reason for entering the Pause state is to temporarily suspend the shifting of data through either the Data or Instruction Register while a required operation such as refilling a host memory buffer is performed From the Pause state shifting can resume by re entering the Shift state via the Exit2 state or terminate by entering the Run Test Idle state via the Exit2 and Update states Upon entering the data or Instruction register scan blocks shadow latches in the selected scan path are forced to hold their present state during the Capture and Shift operations The data being shifted into the selected scan path is not output through the shadow latch until the TAP enters the Update DR or Update IR state The Update state causes the shadow latches to update or parallel load with the new data that has been shifted into the selected scan path MIPS32 M14K Processor Core Software User s Manual Revision 02 03 191 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Figure 8 22 TAP Controller State Diagram PLZ 0 0 GA RunTestide 1 Select DR Scan H l 0 0 ap 1 Exitl IR 1 Exit DR 0 1 o Exi DR Exit2 IR Update DR Update IR 1 0 m
327. on has been serviced Most exceptions are precise which mean that EPC can be used to identify the instruction that caused the exception For precise exceptions the restart location in the EPC regis ter is the address of the instruction that caused the exception or if the instruction was executing in a branch delay slot the address of the branch instruction immediately preceding the delay slot To distinguish between the two software must read the BD bit in the CPO Cause register Bus error exceptions and CP2 exceptions may be imprecise For imprecise exceptions the instruction that caused the exception cannot be identified This chapter contains the following sections e Section 4 1 Exception Conditions e Section 4 2 Exception Priority e Section 4 3 Interrupts e Section 4 4 GPR Shadow Registers e Section 4 5 Exception Vector Locations e Section 4 6 General Exception Processing e Section 4 7 Debug Exception Processing e Section 4 8 Exception Descriptions e Section 4 9 Exception Handling and Servicing Flowcharts 4 1 Exception Conditions When an exception condition occurs the instruction causing the exception and all those that follow it in the pipeline are cancelled flushed Accordingly any stall conditions and any later exception conditions that might have refer enced this instruction are inhibited obviously there is no benefit in servicing stalls for a cancelled instruction MIPS32
328. operation the addressed scan register receives TAP control sig nals to capture the register and shift data from TDI to TDO During a data register scan operation the TAP selects the output of the data register to drive the TDO pin The register is updated in the Update DR state with respect to the write bits This description applies in general to the following data registers e Bypass Register e Device Identification Register e Implementation Register e EJTAG Control Register ECR e Processor Access Address Register e Processor Access Data Register e FastData Register 8 5 2 1 Bypass Register The Bypass register consists of a single scan register bit When selected the Bypass register provides a single bit scan path between TDI and TDO The Bypass register allows abbreviating the scan path through devices that are not involved in the test The Bypass register is selected when the Instruction register is loaded with a pattern of all ones to satisfy the IEEE 1149 1 Bypass instruction requirement 8 5 2 2 Device Identification ID Register The Device Identification register is defined by IEEE 1149 1 to identify the device s manufacturer part number revi sion and other device specific information Table 8 29 shows the bit assignments defined for the read only Device Identification Register and inputs to the core determine the value of these bits These bits can be scanned out of the ID register after being selected The registe
329. or cleared The fourth pin indicates that the processor is in debug mode The S HP signal represents the state of the RP bit 27 in the CPO Status register e The S EXL signal represents the state of the EXL bit 1 in the CPO Status register e The S EHL signal represents the state of the ERL bit 2 in the CPO Status register MIPS32 M14K Processor Core Software User s Manual Revision 02 03 157 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Power Management of the M14K Core The EJ DebugM signal indicates that the processor has entered debug mode 7 2 Instruction Controlled Power Management 158 The second mechanism for invoking power down mode is through execution of the WAIT instruction If the bus is idle at the time the WAIT instruction reaches the M stage of the pipeline the internal clocks are suspended and the pipeline is frozen However the internal timer and some of the input pins S ni 5 0 S NMI SI Reset SI ColdHeset and EJ DINT continue to run If the bus is not idle at the time the WAIT instruction reaches the M stage the pipeline stalls until the bus becomes idle at which time the clocks are stopped Once the CPU is in instruc tion controlled power management mode any enabled interrupt NMI debug interrupt or reset condition causes the CPU to exit this mode and resume normal operation While the part is in this low power mode the S SLEEP signal is asserted to indicate to ex
330. or execution hazards or instruction hazards is created IRET finishes by jumping to the interrupt vector driven by the EIC IRET does not execute the next instruction i e it has no delay slot MIPS32 M14K Processor Core Software User s Manual Revision 02 03 261 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 262 Restrictions The operation of the processor is UNDEFINED if IRET is executed in the delay slot of a branch or jump instruction The operation of the processor is UNDEFINED if IRET is executed when either Shadow Register Sets are not enabled or the EIC interrupt mode is not enabled An IRET placed between an LL and SC instruction will always cause the SC to fail The effective addresses used for stack transactions must be naturally aligned If either of the two least significant bits of the address is non zero an Address Error exception occurs IRET implements a software barrier that resolves all execution and instruction hazards created by Coprocessor 0 state changes for Release 2 implementations refer to the SYNCI instruction for additional information on resolving instruction hazards created by writing the instruction stream The effects of this barrier begin with the instruction fetch and decode of the instruction at the PC to which the IRET returns In a Release 2 implementation IRET does not restore SHSCtlcss from SRHSCtlpss if Statusggy 1 or Statusgpy 1 because any exception that sets
331. orted a core may only support a subset of the possible priming condition values This can be checked by 4 hf to the xBCCnPrCnd field If only 1 or 2 bits can be written the available priming conditions will be described in the PrCndA registers If 3 bits are writable PrCndA and PrCnaB will describe the conditions and if all 4 bits are writable the PrCndA PrCndB PrCndC and PrCnaD registers will all exist Some cores may also support changing the priming conditions and this can be checked by attempting to write to the PrCnd registers If an M14K core supports priming conditions it will support 4 statically mapped priming condi tions per breakpoint which will be described in the PrCndA registers 8 If support for qualified breakpoints is indicated it may only be supported for some of the breakpoints Addition ally the data breakpoint used for the qualification may be configurable Software can check this by writing to the xBCCnDQ and xBCCnDQBrkNum fields If an M14K core support qualified breakpoints it will only support it on instruction breakpoints and the data break used for qualification will be fixed for each instruction breakpoint 9 If the stopwatch timer is implemented either one or two pairs of instruction breakpoints may be available for controlling it and it may be possible to dynamically select which instruction breakpoints are used This can be tested by writing to the STCtl register 8 3 2 General Complex Break Behavior There
332. ory CCA BYTE dataword pAddr vAddr DATA Statusyp lt TempIE Exceptions TLB Refill TLB Invalid TLB Modified Address Error Watch Programming Notes Upon a TLB miss a TLBS exception is signalled in the ExcCode field of the Cause register For address error a ADES exception is signalled in the ExcCode field of the Cause register For other data stream related exceptions such as Debug Data Break exceptions and Watch exceptions it is implementation specific whether this instruction is treated as a load or as a store MIPS32 M14K Processor Core Software User s Manual Revision 02 03 255 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 256 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 31 26 25 6 5 0 COPO CO 0 IRET 010000 1 00 0000 0000 0000 0000 111000 6 1 20 6 Format IRET MIPS32 and MCU ASE Purpose Interrupt Return with automated interrupt epilogue handling Optionally jump directly to another interrupt vector without returning to original return address Description IRET is used to automate some of the operations that are required when returning from an interrupt handler It can be used in place of the ERET instruction at the end of interrupt handlers The IRET instruction is only appropriate when using Shadow Register Sets and EIC Interrupt mode The automated opera
333. ory requests to this region access the CDMM logic Encoding Meaning 0 CDMM Region is disabled 1 CDMM Region is enabled If set to 1 this indicates that the first 64 byte Device Preset Register Block of the CDMM is reserved for addi tional registers that manage CDMM region behavior and are not IO device registers CDMMSize This field represents the number of 64 byte Device Preset Register Blocks instantiated in the core Encoding Meaning DRB 2 DRBs 3 DRBs 512 DRBs 5 2 20 Config Register CPO Register 16 Select 0 The Config register specifies various configuration and capabilities information Most of the fields in the Config reg ister are initialized by hardware during the Reset exception process or are constant Figure 5 20 Config Register Format Select 0 31 30 2827 25 24 23 22 21 20 19 17 16 15 14 13 12 10 9 7 6 3 2 0 M K23 KU 0 UDISB MDU 0 DS BE AT AR MT 0 KO Figure 5 21 Config Register Field Descriptions Fields Name Bit s Description Read Write Reset State M 31 This bit is hardwired to 1 to indicate the presence of the R 1 Config register 124 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Figure 5 21 Config Register Field Descriptions Continued Description Read Wri
334. ot be written DQ 4 Qualify this breakpoint based on the data breakpoint indi R 0 cated in DBrkNum Data qualification of data breakpoints is not supported on an M14K core and this field will read as 0 and cannot be written 180 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints 8 2 7 8 Data Breakpoint Pass Counter n DBPCn Register 0x2130 n 0x100 Compliance Level Implemented only if complex breakpoints are implemented and only for implemented data breakpoints The Data Breakpoint Pass Counter n DBPCn register controls the pass counter associated with data breakpoint n If complex breakpoints are implemented there will be an 16b pass counter for each of the data breakpoints on the MIAK core Figure 8 16 DBPCn Register Format 31 16 15 0 HI n Description Read Write Reset State 0 Table 8 18 DBPCn Register Field Descriptions 31 16 Ignored on write returns zero on read R 0 PassCnt 15 0 Prevents a break trigger action until the matching condi R W 0 tions on data breakpoint n have been seen this number of times Each time the matching condition is seen this value will be decremented by 1 Once the value reaches 0 subse quent matches will cause a break or trigger as requested and the counter will stay at 0 The break or trigger action is imprecise if the PassCnt reg
335. pa cene E em mese idi usas Vids 217 8 8 6 ITCB Register Interface for Software Configurability essen 218 9 8 7 WTCBElowtrace Om C hip MSM ACS i caine dei cs cea i reino Cet aae Seq OONA 222 8 8 8 Breakpoint Based Enabling of TraGInag usnn th reet nata vh idet epe Ep pta RR a ENNEA 222 8 9 PO Data Address Samplihigiss uds sonaia anctavedswsaduad shaq au Rida tp ax a priuatis CERA A dDES 223 S951 PO Samping im Welt Stale deter dass tuse S eiue x Tt EPI IE ES 224 8 9 2 Data Address Salt OM ing ssas ionia ans enesnc aur So SUR Cedo AN tasca A cte use E p tuong uds 224 8 10 Fast Debug Channels xp diria dessus a EE tede RA pu ine O as x Er D EEEN 224 8 10 1 Gommon Device Memory Mapis ire deis ter e doit cena pad rse E e meidpddinrdtsd eS 225 8 10 2 Fast Debug Channel ater ulpa cause secca de setti Lon i Cie to cet e eat ru oet erase etr ae ee ep etoboSs 225 8 109 MIAKNMTAK FDG BUMTCUS E 225 Bl OAs Sleep ModE aE era araa oier daan aoaia 227 8 105 DIE i o E E E N 227 9 10 5 Fast Debug Ghannel BegISIGES cuiu roit es esent E annaa OERS 228 Semester E 232 Chapter 9 Instruction Set Overvlgw esaerea cenae eost rac uie nna tn menn na Raana Ea SEE rSn 233 9 1 CPU Instruction Formats scisco to tice ice ani ria de es be tuden ei er Edad it derit eae eec ti cian Fedele ictu E edd 233 9 2 Loadiand Store nS MUCO NS e iode etre eens icc ihe satt s Cesena bove etc eui a diver Mab ed bt 234 9 2 1 Schedubng a Load Delay
336. peration seeeeeeesss 40 Figure 2 11 M14K Area Efficient MDU Pipeline Flow During a Multiply Accumulate Operation 40 Figure 2 12 M14K Area Efficient MDU Pipeline Flow During a Divide DIV Operation 41 Figure 2 19 10 Pipeline Branch Delay 353 3 tia cEro ttr chao Ure a pE NU s REP eti UNIS Up mcus byl cen d xupP uU DUREE RESO esp DUE 42 Figure 2 14 1U Pipeline Data Bypass tiir tr obe s terrere br etr e e ERE reri a dt RAAEN a 42 Figure 2 15 IU Pipeline Mito E DY PASS scd opea xeledsuoreldarupred d padrrtestes a ane 43 Figute 2 16 1U Pipeline A to E Data bypass 1 neri at tuere este ees totiens iris ea ERRARE LR ENS 43 Figure 217 1U Pipeline Slip atter a MEHM societe ie m Se XXe ENE 44 Figure 2 18 Coprocessor 2 Interface Tramsactioris aeoeoi coire trt rient he ores ert ek n bre x npa e EX ap xir eaa Rd 45 Figure 2 19 Instruction Gache MISS S Ipi sooner atta ua secu Sac ine re add tq sen Rire xa dude Ekans E dcEK DEN SVO RS CE 46 Figure 3 1 Address Translation During SRAM ACCESS aat tort oos t eee Pane eU Esas Eu rra a dRE Redde 51 Figure 3 2 M14K processor core Virtual Memory Map sec ciesedsatiietadadurncenisuunss eene aS pee Une eoo oe UR OP ne E eias RuS 53 Figure 3 3 User Mode Virtual Address SP ACC i rrt iib tas Pee E detenti aate npe cia ba deba Eur coc ANNAE E 54 Figure 3 4 Kernel Mode Virtual Address Space
337. pically required for caches The SRAM inter face includes separate uni directional 32 bit buses for address read data and write data Dual or Unified Interfaces The SRAM interface includes a build time option to select either dual or unified instruction and data interfaces The dual interface enables independent connection to instruction and data devices It generally yields the highest per formance because the pipeline can generate simultaneous I and D requests which are then serviced in parallel For simpler or cost sensitive systems it is also possible to combine the I and D interfaces into a common interface that services both types of requests If I and D requests occur simultaneously priority is given to the D side Back stalling Typically read and write transactions will complete in a single cycle However if multi cycle latency is desired the interface can be stalled to allow connection to slower devices Redirection When the dual I D interface is present a mechanism exists to divert D side references to the I side if desired The mechanism can be explicitly invoked for any other D side references as well When the DS Redir signal is asserted a D side request is diverted to the I side interface in the following cycle and the D side will be stalled until the trans action is completed Transaction Abort The core may request a transaction fetch load store sync to be aborted This is particularly useful in case of inte
338. pliance Level Implemented only for implemented data breakpoints For processors with a TLB based MMU this register is used to define an ASID value to be used in the match expres sion On the M14K processor this register is reserved and reads as 0 Figure 8 12 DBASIDn Register Format 31 8 7 0 Res ASID Table 8 14 DBASIDn Register Field Descriptions Fields Read Wr Bit s Description ite Reset State Must be written as zero returns zero on read Data breakpoint ASID value for compares 8 2 7 5 Data Breakpoint Control n DBCn Register 0x2118 0x100 n Compliance Level Implemented only for implemented data breakpoints The Data Breakpoint Control n DBCn register controls the setup of data breakpoint n MIPS32 M14K Processor Core Software User s Manual Revision 02 03 177 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Name 31 24 23 14 13 12 11 8 7 4 3 2 1 0 Fields Figure 8 13 DBCn Register Format 22 18 17 Table 8 15 DBCn Register Field Descriptions Bits Description Read Write Reset State Res 31 24 Must be written as zero returns zero on reads R 0 ASIDuse Res BAI NoSB 23 Use ASID value in compare for data breakpoint n R 0 Encoding Meaning 0 Don t use ASID value in compare 1 Use ASID value in compare 22 18 Must be written as zero returns zero on reads R 0 17 14
339. ponding to the register being written Reads from these registers are UNDE FINED Attempting to write to the transmit FIFO if it is full has UNDEFINED results Hence the software running on the core must check the TxF flag in FDSTAT to ensure that there is space for the write Figure 8 42 shows the for mat of the FDC Transmit register and Table 8 48 describes the register fields Figure 8 42 FDC Transmit Register 31 0 TxData MIPS32 M14K Processor Core Software User s Manual Revision 02 03 231 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Table 8 48 FDC Transmit Register Field Descriptions Read Reset Description Write State TxData 31 0 This register holds the bottom entry in the transmit FIFO W Unde Undefined fined value on read Table 8 49 FDTXn Address Decode 0x20 0x0 0x40 0x4 0x60 0x8 0x80 Oxc 0x28 0x1 0x5 0x68 0x9 0x88 Oxf 0x30 0x2 0x6 0x70 Oxa 0x38 0x3 0x58 0x7 0x78 Oxb 0x98 8 11 cJTAG Interface The cJTAG external IP block provided as part of the M14K processor core converts a 4 wire EJTAG IEEE 1149 1 interface to a 2 wire cJTAG IEEE1149 7 interface A high level view of cJTAG is shown in Figure 8 43 Operation of the conversion adapter is transparent to software Refer to the cJTAG Adapter User s Manual 12 for more details Figure 8 43 cJTAG Interface MIAK EJTAG
340. popj cC 276 11 1 4 Compliance and SUDSETMING iii recae seeders a toria e cesta be eui n ict Do Hi se eI REID MUE 276 LUN es Mode SWIG Mis e E meas 276 11 1 6 Branch and Jurap OffSelssisi ctis ce ination Rina i dI PR Hed Ede lato 277 11 1 7 Coprocessor Unusanle BenaViOn 25 nicest eaiski depot ENEE eid ANDA 277 11 2 IMSTHUCTION ONIN AUS 3 eeescel io a N E fi ndeasend avanti E 277 11 2 1 Instruction Stream Organization and EndianneSs ccc ccccceeceeeeeeeeceeeeeeeeseaeeeeeeeseceeeesaeeseaas 281 11 9 microMIPS Re encoded IInstrulClOns sui Feste etit Ran sian Cose Pepe Usb e seo npud ink niae AY ch Hago Hc ced ae 281 14 51 ea Galego Greener eee ear eter mea rrr E et Serene Dai ere tuse ed E terre Ide aer E 282 113 2 16 bit Instruction Register SOL d te retener ea editore bes ee eai sun di sestiuwe dere ees 287 11 3 9532 Bit Galego tiu ccu dote teere A R tracer yet er rerrrrrereer dU DR LL ster errr erent kerr er 289 Appendix A References iuieeiie certet itti cencessunantedanieuwesccecanentodaacecteveniacunnssncseiectesaxeseernesceces 291 Appendix B Revision HISIOtV nno tm tetas so ets anna at nu n RAM intu a Ra AM ERR MR SA e DER TERRENS 293 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 7 Copyright 2009 2010 MIPS Technologies Inc All rights reserved List of Figures Figure 1 MTAK Processor Gore Block Diagrami certo oi rores ieiuno c o e RP ERTA 20 Figure 1 1 Figure 1 2
341. pt control ler for prioritization in EIC interrupt mode with other interrupt sources The state of these bits is available on the external core interface as the S _SWint 1 0 bus ExcCode 6 2 Exception code see Table 5 16 R Undefined 0 20 18 7 Must be written as zero returns zero on read 0 0 1 0 Table 5 16 Cause Register ExcCode Field Exception Code Value Decimal Hexadecimal Mnemonic Description 0 16 00 Int Interrupt 1 3 16 01 16 03 Reserved 4 16 04 AdEL Address error exception load or instruction fetch 5 16 05 AdES Address error exception store 6 16 06 IBE Bus error exception instruction fetch 7 16 07 DBE Bus error exception data reference load or store 8 16 08 Sys Syscall exception 9 16 09 Bp Breakpoint exception 10 16 0a RI Reserved instruction exception 11 16 0b CpU Coprocessor Unusable exception 12 16 0c Ov Arithmetic Overflow exception 13 16 0d Tr Trap exception 14 15 16 0e 16 0f Reserved 16 16 10 IS1 Implementation Specific Exception 1 COP2 17 16 11 CEU CorExtend Unusable 18 16 12 C2E Coprocessor 2 exceptions 19 28 16 13 16 1c Reserved 29 16 1d MPU MPU Exception 30 16 le Parity Error Parity error In normal mode a parity error exception has a dedicated vector and the Cause register is not updated If a parity error occurs while in Debug Mode this code is written to the Debug DExcCode field to indicate that re entry to Debug Mode was cau
342. ption Simple Description e SYNC affects only uncached and cached coherent loads and stores The loads and stores that occur before the SYNC must be completed before the loads and stores after the SYNC are allowed to start e Loads are completed when the destination register is written Stores are completed when the stored value is visi ble to every other processor in the system e SYNC is required potentially in conjunction with SSNOP in Release 1 of the Architecture or EHB in Release 2 of the Architecture to guarantee that memory reference results are visible across operating mode changes For example a SYNC is required on entry to and exit from Debug Mode to guarantee that memory affects are han dled correctly Detailed Description e SYNC does not guarantee the order in which instruction fetches are performed The stype values 1 31 are reserved for future extensions to the architecture A value of zero will always be defined such that it performs all defined synchronization operations Non zero values may be defined to remove some synchronization opera tions As such software should never use a non zero value of the stype field as this may inadvertently cause future failures if non zero values remove synchronization operations e The SYNC instruction is externalized on the SRAM interface of the M14K core External logic can use this infor mation in a system dependent manner to enforce memory ordering between various memory eleme
343. pyright 2009 2010 MIPS Technologies Inc All rights reserved microMIPS Instruction Set Architecture 278 The immediate field is right aligned in the following instructions e some 16 bit instructions with 3 bit register fields e 32 bit instructions with 16 bit or 26 bit immediate field The name immediate field as used here includes the address offset field for branches and load store instructions as well as the jump target field Other instruction specific fields are typically located between the immediate and minor opcode fields Instructions that have multiple other fields are listed in alphabetical order according to the name of the field with the first name of the order located at the lower bit position An empty bit field that is not explicitly shown in the instruction format is located next to the minor opcode field Figure 11 1 and Figure 11 2 show the 16 bit and 32 bit instruction formats MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved S3R0 S3R117 S3R210 S3R213 S3R214 S3R3I0 S5R110 S5R115 S5R210 11 2 Instruction Formats Figure 11 1 16 Bit Instruction Formats 15 10 9 0 Major Opcode Minor Opc Imm 15 10 9 7 6 0 Major Opcode rs1 d Minor Opc Imm 15 10 9 6 5 3v 2 0 Major Opcode Minor Opc rs2 d rs1 15
344. r rupts Because the core does not know whether transactions are re startable it cannot arbitrarily interrupt a request which has been initiated on the SRAM interface However cycles spent waiting for a multi cycle transaction to com plete can directly impact interrupt latency In order to minimize this effect the interface supports an abort mecha nism The core requests an abort whenever an interrupt is detected and a transaction is pending abort of an instruction fetch may also be requested in other cases The external system logic can choose to acknowledge or to ignore the abort request MIPS32 M14K Processor Core Software User s Manual Revision 02 03 23 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Introduction to the MIPS32 6 M14K Processor Core Connecting to Narrower Devices The instruction and data read buses are always 32 bits in width To facilitate connection to narrower memories the SRAM interface protocol includes input byte enables that can be used by system logic to signal validity as partial read data becomes available The input byte enables conditionally register the incoming read data bytes within the core and thus eliminate the need for external registers to gather the entire 32 bits of data External muxes are required to redirect the narrower data to the appropriate byte lanes Lock Mechanism The SRAM interface includes a protocol to identify a locked sequence and is used in conjunct
345. r 3 3 vl General purpose register 4 4 a0 General purpose register 5 5 al General purpose register 6 6 a2 General purpose register 7 4 a3 General purpose register p 0 7 correspond to the register s 16 bit binary encoding and show how that encoding relates to the MIPS registers 0 7 never refer to the registers except within the binary microMIPS instructions From the assembler only the MIPS names 16 17 2 etc or the symbolic names s0 s1 vO etc refer to the registers For example to access register number 17 in the register file the programmer references 17 or s1 even though the micro MIPS binary encoding for this register is 001 2 General registers not shown in the above table are not accessible through the 16 bit instruc tions using 3 bit register specifier The Move instruction can access all 32 general purpose registers Table 11 6 16 Bit Instruction Implicit General Purpose Registers 16 Bit 32 Bit MIPS Symbolic Name Register Register From Encoding Encoding ArchDefs h Description Implicit 28 gp Global pointer register Implicit 29 sp Stack pointer register Implicit 31 ra Return address register MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 11 3 microMIPS Re encoded Instructions Table 11 7 16 Bit Instruction Special Purpose Registers Symbolic Name Pu
346. r a ADES exception is signalled in the ExcCode field of the Cause register For other data stream related exceptions such as Debug Data Break exceptions and Watch exceptions it is implementation specific whether this instruction is treated as a load or as a store MIPS32 M14K Processor Core Software User s Manual Revision 02 03 251 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 252 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 31 26 25 21 20 16 15 14 12 11 4 3 0 REGIMM ATOMIC 000001 base 00111 1 Bit offset 6 5 5 1 3 12 Format ASET bit offset base MIPS32 and MCU ASE Purpose Atomically Set Bit within Byte Description Disable interrupts temp memory GPR base offset temp lt temp or 1 lt lt bit memory GPR base offset lt temp Enable Interrupts The contents of the 8 bit byte at the memory location specified by the effective address are fetched The specified bit within the byte is set to one The modified byte is stored in memory at the location specified by the effective address The 12 bit signed offset is added to the contents of GPR base to form the effective address The read modify write sequence cannot be interrupted Transactions with locking semantics occur in some memory interconnects busses It is implementation specific whether this instruction uses such
347. r Vectored Interrupts ssessssssssssseeeee eene nnne nnns 74 Table 4 5 Exception Vector Base Addresses rd n Pr te ak RR ede XR Na NOS ONERE FERAKN RAN RA 44 RES RU KCERRKR PANE ABE aE 78 Table 4 6 Exception Vector OIfSels inscia kroceste eae teca kx a dd Sy a a RQYk Y A ENE 78 Table 4 7 Exception Veolols seccion t ot dama at au Nette id M T ERIT NUI nares M LH US 78 Table 4 8 Value Stored in EPC ErrorEPC or DEPC on an Exception sse 79 Table 4 9 Debug Exception Vector Addresses or nth argent Rates canh raa rk ka Rx n d RS RR ERAN Ra aH X aia 82 Table 4 10 Register States an Interrupt EXCOpLIOn iride ee sedat nexa kr Eee aa AA 85 Table 4 11 CPO Register States on an Address Exception Error esssssssssssseseeeeeen nnns 86 Table 4 12 CPO Register States on a SRAM Parity Error Exception sssssseseseeeeeeen entres 86 Table 4 13 Register States on a Coprocessor Unusable Exception ssssssssssseeseeeeeneenenn 89 Table 5 1 GPO Registers set sscc tesis t od uices better scduu E A ten d n EU EPL ced duiA id bxrH ed LAS 95 Table 5 2 CPO Register Feld Types irt ott ee eset ea canc YR cua aet i cem etos ctu RE ee eEE Le seqeh o dns 97 Table 5 4 HWhEna Register Field DescrlpliaIs so oit iet ep nah bo fet De Eo Eee bu bero edP eee 98 Table 5 3 UserLocal Register Field DescriptiOns oooci inr mn rere Pont ti itte hay rper her pam cese 98 T
348. r is selected when the Instruction register is loaded with the IDCODE instruction Figure 8 25 Device Identification Register Format 31 28 27 12 11 1 0 Version PartNumber ManufID R 198 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 5 EJTAG TAP Registers Table 8 29 Device Identification Register Fields Read Name Bit s Description Write Reset State Version Version 4 bits R EJ_Version 3 0 This field identifies the version number of the proces sor derivative PartNumber Part Number 16 bits R EJ_PartNumber 15 0 This field identifies the part number of the processor derivative ManufID Manufacturer Identity 11 bits R EJ ManufID 10 0 Accordingly to IEEE 1149 1 1990 the manufacturer identity code shall be a compressed form of the JEDEC Publications 106 A R R 1 8 5 2 3 Implementation Register This 32 bit read only register is used to identify the features of the EJTAG implementation Some of the reset values are set by inputs to the core The register is selected when the Instruction register is loaded with the IMPCODE instruction Figure 8 26 Implementation Register Format 31 29 28 25 24 23 21 20 17 16 15 14 13 0 EJTAGver reserved pei ASIDsize reserved MIPS16 0 NNDMA reserved Table 8 30 Implementation Register Descriptions Fields Read Wr Name Bit s Descrip
349. reads 0 0 28 27 21 19 13 12 8 2 Hardware Breakpoints Hardware breakpoints provide for the comparison by hardware of executed instructions and data load store transac tions It is possible to set instruction breakpoints on addresses even in ROM area Data breakpoints can be set to cause a debug exception on a specific data transaction Instruction and data hardware breakpoints are alike for many aspects and are thus described in parallel in the following The term hardware is not generally added to breakpoint unless required to distinguish it from a software breakpoint MIPS32 M14K Processor Core Software User s Manual Revision 02 03 163 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core 164 There are two types of simple hardware breakpoints implemented in the M14K core Instruction breakpoints and Data breakpoints The M14K core may also contain a complex breakpoint unit A core may be configured with the following breakpoint options No data or instruction breakpoints without complex break support e Two instruction and one data breakpoint without complex break support e Four instruction and two data breakpoints without complex break support e Six instruction and two data breakpoints without support for complex breaks e Six instruction and two data breakpoints with support for complex breaks e Eight instruction and four data breakpoints without suppor
350. reakpoints There are two methods for matching conditions namely 1 by Equality and Mask or 2 by Address Range Equality and Mask When a data breakpoint is enabled that breakpoint is evaluated for every data transaction due to a load store instruc tion executed in non debug mode including load store for coprocessor and transactions causing an address error on data access The breakpoint is not evaluated due to a PREF instruction or other transactions which are not part of explicit load store transactions in the execution flow nor for addresses which are not the explicit load store source or destination address A breakpoint match depends on the transaction type TYPE as load or store the address and optionally the data value of a transaction The registers for each data breakpoint have the values and mask used in the compare and the equation that determines the match is shown below in C like notation The overall match equation is the DB_match DB_match TYPE load amp amp DBCnyorp TYPE store amp amp DBCnggogg amp amp DB addr match amp amp DB no value compare DB value match MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints The match on the address part DB_addr_match depends on the virtual address of the transaction ADDR and the accessed bytes BYT
351. reakpoints e Two data and six instruction breakpoints with or without complex breakpoints e Four data and eight instruction breakpoints with or without complex breakpoints Instruction breakpoints occur on instruction execution operations and the breakpoint is set on the virtual address A mask can be applied to the virtual address to set breakpoints on a binary range of instructions Data breakpoints occur on load store transactions The breakpoint is set on a virtual address value with the same sin gle address or binary address range as the Instruction breakpoint Data breakpoints can be set on a load a store or both Data breakpoints can also be set to match on the operand value of the load store operation with byte granularity masking Finally masks can be applied to both the virtual address and the load store value Complex breakpoints utilize the simple instruction and data breakpoints and break when a combination of events is seen Complex break features include MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 1 2 M14K Core Block Diagram e Pass Counters Each time a matching condition is seen a counter is decremented The break or trigger will only be enabled when the counter has counted down to 0 e Tuples A tuple is the pairing of an instruction and a data breakpoint The tuple will match if both the virtual address of the loa
352. reakpoints is implemented Encoding Meaning 0 No inverted data value match on data hardware breakpoints implemented 1 Inverted data value match on data hardware breakpoints implemented DVM 14 Indicates if a data value store on a data value breakpoint R Preset match is implemented Encoding Meaning 0 No data value store on a data value breakpoint match implemented 1 Data value store on a data value break point match implemented RDVec 11 Enables relocation of the debug exception vector The R W value in the Debug VectorAddr register is used for EJTAG exceptions when ProbTrap 0 and RDVec 1 CBT 10 Indicates if complex breakpoint block is implemented R Preset Encoding Meaning 0 No complex breakpoint block imple mented 1 Complex breakpoint block imple mented PCS 9 ndicates if the PC Sampling feature is implemented R Encoding Meaning 0 No PC Sampling implemented 1 PC Sampling implemented PCR 8 6 PC Sampling rate Values 0 to 7 map to values 25 to 2 R W cycles respectively That is a PC sample is written out every 32 64 128 256 512 1024 2048 or 4096 cycles respectively The external probe or software is allowed to set this value to the desired sample rate ER PCSe 5 If the PC sampling feature is implemented then indi R W cates whether PC sampling is initiated or not That is a value of 0 indicates that PC sampling
353. regardless of whether they succeeded Note that this only counts PREFs that are actually attempted PREFs to uncached addresses or ones with translation errors are not counted Cp2 To From instns Includes move to from control to from and cop2 loads and stores Instruction execution events SC instructions failed SC instruction that did not update memory Note While this event and the SC instruction count event can be con figured to count in specific operating modes the timing of the events is much different and the observed operating mode could change between them causing some inaccuracy in the measured ratio Exceptions Taken Any type of exception taken EJTAG instruction triggers 0 49 Number of times an EJTAG Instruction Trigger Point condition matched EJTAG data triggers 1 49 Number of times an EJTAG Data Trigger Point condition matched 148 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 40 Event Descriptions Continued eventname Counter number Deseripton General Stalls ALU stall cycles Counts the number of cycles in which the ALU pipeline cannot advance Stall cycles Counts the total number of cycles in which no instructions are issued by SRAM to ALU the RF stage does not advance This includes both of the previous two events However this is different
354. registers are connected to a clock that is stopped when the processor is in sleep mode f the top level clock gater is present Most events would not be active during that time but others would be notably the cycle count This behavior should be considered when analyzing measurements taken on a system Further note that FPGA implementations of the core would generally not have the clock gater present and thus would have differ ent behavior than a typical ASIC implementation Figure 5 35 Performance Counter Control Register 31 30 12 11 5 4 3 2 1 0 M 0 Event IE U 0 K EXL Table 5 39 Performance Counter Control Register Field Descriptions Fields Name Bits Description Read Write Reset State If this bit is one another pair of Performance Controland Counter Preset registers is implemented at a MTCO or MFCO select field value of n 2 and n 3 Counter event enabled for this counter Possible events are listed in Undefined Table 6 60 Counter Interrupt Enable This bit masks bit 31 of the associated 0 count register from the interrupt exception request output Count in User Mode When this bit is set the specified event is Undefined counted in User Mode Count in Kernel Mode When this bit is set count the event in Ker Undefined nel Mode when EXL and ERL both are 0 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 145 Copyright 2009 2010
355. resent Sixteen shadow sets are present 2 4 6 8 14 Reserved The value in this field also represents the highest value that can be written to the ESS EICSS PSS and CSS fields of this register or to any of the fields of the SRSMap register The operation of the processor is UNDEFINED if a value larger than the one in this field is written to any of these other fields Must be written as zeros returns zero on read 0 EIC interrupt mode shadow set If Config3ypyc is 1 EIC interrupt mode is enabled this field is loaded from the external interrupt controller for each interrupt request and is used in place of the SRSMap register to select the current shadow set for the interrupt See Section 4 3 1 Interrupt Modes for a discussion of EIC interrupt mode If Config3yzyc is 0 this field must be written as zero and returns zero on read Undefined Must be written as zeros returns zero on read Exception Shadow Set This field specifies the shadow set to use on entry to Kernel Mode caused by any excep tion other than a vectored interrupt The operation of the processor is UNDEFINED if soft ware writes a value into this field that is greater than the value in the HSS field Must be written as zeros returns zero on read MIPS32 M14K Processor Core Software User s Manual Revision 02 03 109 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registe
356. rflow message by recognizing that it is the last trace word These trace formats are written to a trace memory that is either on chip or off chip No particular size of SRAM is specified the size is user selectable based on the application needs and area trade offs Each trace word can typically store about 20 to 30 instructions in normal trace mode so a 1 KWord trace memory could store the history of 20K to 30K executed instructions The on chip SRAM or trace memory is written continuously as a circular buffer It is accessible via drseg address mapped registers There are registers for the read pointer write pointer and trace word The write pointer register includes a wrap bit that indicates that the pointer has wrapped since the last time the register was written Before start ing trace the write pointer would typically be set to 0 To read the trace memory the read pointer should be set to 0 if there has not been a wrap or to the value of the write pointer if there has been Reading the trace word register will read the entry pointed to by the read pointer and will automatically increment the read pointer Software can continue reading until all valid entries have been read out 8 8 6 ITCB Register Interface for Software Configurability The ITCB includes a drseg memory interface to allow software to set up tracing and read the current status If an on chip trace buffer is also implemented there are additional registers included for accessin
357. rformance Counter Count Register Field Descriptions Description Read Write Reset State Counter Undefined MIPS32 M14K Processor Core Software User s Manual Revision 02 03 149 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core 5 2 35 ErrCtl Register CPO Register 26 Select 0 The ErrCtl register controls parity protection of data and instruction SRAM Parity protection can be enabled or dis abled using the PE bit Figure 5 37 ErrCtl Register Format 31 30 PE R Table 5 42 Errctl Register Field Descriptions Fields Name Bit s Description Read Write Reset State PE 31 Parity Enable This bit enables or disables the parity protec tion for both the instruction SRAM and the data SRAM Encoding Meaning 0 Parity disabled 1 Parity enabled This field is only write able if the parity option was imple mented when the M14K was built If parity is not sup ported this field is always read as 0 Software can test for parity support by attempting to write a 1 to this field then read back the value R or R W 0 30 0 Must be written as zero returns zero on reads 5 2 36 CacheErr Register CPO Register 27 Select 0 The CacheErr register provides an interface with the cache error detection logic When a SRAM Parity Error excep tion is signaled the fields of this register are se
358. rigger signals from instruc tion breakpoints 0 14 6 Reserved 0 0 142 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 35 TraceBPC Register Field Descriptions Continued Fields Name Bits Description Read Write Reset State IBPOn 5 0 Each of the 6 bits corresponds to the 6 possible R W 0 EJTAG hardware instruction breakpoints that may be implemented Bit 0 corresponds to the first instruction breakpoint and so on If only 2 instruction breakpoints are present in the EJTAG implementation then only bits 0 and 1 are used The rest are always ignored by the tracing logic because they will never be triggered A value of one for each bit implies that a trigger from the corresponding instruction breakpoint should start tracing And a value of zero implies that tracing should be turned off with the trigger signal 5 2 32 Debug2 Register CPO Register 23 Select 6 This register holds additional information about Complex Breakpoint exceptions This register is only implemented if complex hardware breakpoints are present Figure 5 33 Debug2 Register Format 31 4 3 2 1 0 0 Prm DQ Tup PaCo Table 5 36 Debug2 Register Field Descriptions Fields Name Bits Description Read Write Reset State
359. right 2009 2010 MIPS Technologies Inc All rights reserved 8 10 Fast Debug Channel Table 8 44 FDC Access Control and Status Register Field Descriptions Continued Fields Read Reset Name Bits Description Write State Uw 3 This bit indicates if user mode write access to this device R W is enabled A value of 1 indicates that access is enabled A value of 0 indicates that access is disabled An attempt to write to the device while in user mode with access dis abled is ignored Ur 2 This bit indicates if user mode read access to this device is enabled A value of 1 indicates that access is enabled A value of 0 indicates that access is disabled An attempt to read from the device while in user mode with access dis abled will return 0 and not change any state 2 2 Sw 1 This bit indicates if supervisor mode write access to this device is enabled A value of 1 indicates that access is enabled A value of 0 indicates that access is disabled An attempt to write to the device while in supervisor mode with access disabled is ignored 2 Sr 0 This bit indicates if supervisor mode read access to this device is enabled A value of 1 indicates that access is enabled A value of 0 indicates that access is disabled An attempt to read from the device while in supervisor mode with access disabled will return 0 and not change any state 0 11 4 Reserved for future use Ignored on write returns zero on R read 8
360. right 2009 2010 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints Table 8 21 CBTC Register Field Descriptions Continued Fields Name Bits Description Read Write Reset State STMode Stopwatch Timer Mode controls whether the stopwatch timer is free running or controlled by triggerpoints 0 free running started and stopped by instruction triggers Stopwatch Timer Present indicates whether stopwatch timer is implemented Priming Present indicates whether primed breakpoints are supported Data Qualify Present indicates whether data qualified breakpoints are supported Tuple Present indicates whether any tuple breakpoints are implemented Pass Counters Present indicates whether any break points have pass counters associated with them 8 2 8 2 Priming Condition A PrCndAl Dn Registers Compliance Level Implemented if complex breakpoints are implemented The Prime Condition registers hold implementation specific information about which triggerpoints are used for the priming conditions for each breakpoint register On an M14K core these connections are predetermined and these registers are read only The architecture allows for up to 16 priming conditions to be specified and there can be up to 4 priming condition registers per breakpoint A B C D An M14K core only allows for 4 priming conditions and thus only implements the PrCndA registers The gener
361. rmation about the message in that word The ITCB includes a 58 bit shift register to accumulate trace messages Once 58 or more bits are accumulated the 58 bits and 6 tag bits are sent to the memory write interface Messages may span a trace word boundary In this case the 6 tag bits indicate the bit number of the first full trace message in the 58 bit data field The tag bits are slightly encoded so they can serve a secondary purpose of indicating to off chip trace hardware when a valid trace word transmission begins The encoding ensures that at least one of the 4 LSBs of the tag is always a 1 for a valid trace message The tag values are shown in Table 8 36 The longest trace message is 57 bits filtered data MIPS32 M14K Processor Core Software User s Manual Revision 02 03 217 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core trace in special trace mode with delta cycle so the starting position indicated by the tag bits is always between 0 and 56 Table 8 36 Tag Bit Encoding Starting Bit of First Full Encoding Trace Message decimal 0 58 16 59 32 60 48 61 Unused 0 16 32 48 Reserved 62 63 Others StartingBit When trace stops ON set to zero any partially filled trace words are written to memory Any unused space above the final message is filled with 1 s The decoder distinguishes 1111 patterns used for fill in this position from an 1111 ove
362. robTrap ProbEn and EjtagBrk bits in the EJTAG Control register are set to 1 after a hard or soft reset This EJTAGBOOT indication is effective until a NORMALBOOT instruction is given TRST_N is asserted or a ris ing edge of TCK occurs when the TAP controller is in Test Logic Reset state It is possible to make the CPU go into debug mode just after a hard or soft reset without fetching or executing any instructions from the normal memory area This can be used for download of code to a system which have no code in ROM The Bypass register is selected when the EJTAGBOOT instruction is given 8 4 3 9 NORMALBOOT Instruction When the NORMALBOOT instruction is given and the Update IR state is left then the reset value of the ProbTrap ProbEn and EjtagBrk bits in the EJTAG Control register are set to 0 after hard or soft reset The Bypass register is selected when the NORMALBOOT instruction is given 196 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 5 EJTAG TAP Registers 8 4 3 10 FASTDATA Instruction This selects the Data and the Fastdata registers at once as shown in Figure 8 24 Figure 8 24 TDI to TDO Path When in Shift DR State and FASTDATA Instruction is Selected TDI data d Fastdata TDO 8 4 3 11 PCsample Register PCSAMPLE Instruction This selects the PCsample Register The use of the PCsample Register is descr
363. roduct is added to the 64 bit concatenated values in the HI and LO register pair The resulting value is then written back to the HI and LO registers No arithmetic exception occurs under any circumstances 9 7 4 MADDU Multiply and Add Unsigned Word The MADDU instruction multiplies two unsigned words and adds the result to the HI LO register pair The 32 bit word value in the GPR rs is multiplied by the 32 bit value in the GPR rt treating both operands as unsigned values to produce a 64 bit result The product is added to the 64 bit concatenated values in the HI and LO register pair The resulting value is then written back to the HI and LO registers No arithmetic exception occurs under any conditions 9 7 5 MSUB Multiply and Subtract Word The MSUB instruction multiplies two words and subtracts the result from the HI LO register pair The 32 bit word value in the GPR rs is multiplied by the 32 bit value in the GPR rt treating both operands as signed values to pro duce a 64 bit result The product is subtracted from the 64 bit concatenated values in the HI and LO register pair The resulting value is then written back to the HI and LO registers No arithmetic exception occurs under any circum stances MIPS32 M14K Processor Core Software User s Manual Revision 02 03 237 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Instruction Set Overview 9 7 6 MSUBU Multiply and Subtract Unsigned Word The MSUBU instruct
364. rom SRSCtlgss If SRSCthysg is zero the results of a software read or write of this register are UNPREDICTABLE The operation of the processor is UNDEFINED if a value is written to any field in this register that is greater than the value of SRSCthyss The SRSMap2 register contains the shadow register set numbers for vector numbers 9 8 The same shadow set num ber can be established for multiple interrupt vectors creating a many to one mapping from a vector to a single shadow register set number MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Figure 5 11 shows the format of the SRSMap2 register Table 5 14 describes the SRSMap2 register fields Figure 5 11 SRSMap Register Format 31 8 7 4 3 0 0 SSV9 SSV8 Table 5 14 SRSMap Register Field Descriptions Name Bits Description Compliance SSV8 Shadow register set number for Vector Number 8 Required 0 31 8 Must be written as zero returns zero on read R 0 RESERVED SSV9 T 4 Shadow register set number for Vector Number 9 R W 0 Required 5 2 12 Cause Register CPO Register 13 Select 0 The Cause register primarily describes the cause of the most recent exception In addition fields also control soft ware interrupt requests and the vector through which interrupts are dispatched With the exception of the P1 0 DC IV and
365. rpose PC Program counter The PC relative ADDIU can access this register as an operand HI Contains high order word of multiply or divide result LO Contains low order word of multiply or divide result 11 3 3 32 Bit Category 11 3 3 1 New 32 bit instructions The following table lists the 32 bit instructions introduced in the microMIPS ISA Table 11 8 32 bit Instructions introduced within microMIPS Register Total Major Number of Immediate Field Size of Empty 0 Minor Opcode Register Field Size Width Other FieldSize Opcode Name Fields bit Fields Size bit Comment ADDIUPC ADDIUPC ADDIU PC Relative BEQZC POOL22I Branch on Equal to Zero No Delay Slot POOL32I Branch on Not Equal to Zero No Delay Slot JALRS POOL32A Jump and Link Regis ter Short Delay Slot JALRS HB POOL32A Jump and Link Regis ter with Hazard Bar rier Short Delay Slot JALS JALS32 Jump and Link Short Delay Slot JALX JALX Jump and Link Exchange LWP POOL32B Load Word Pair LWXS POOL32A Load Word Indexed Scale POOL32B 1 5bit Load Word Multiple POOL32B 2 5 bit Load Word Pair POOL32B 1 5bits Store Word Multiple MIPS32 M14K Processor Core Software User s Manual Revision 02 03 289 Copyright 2009 2010 MIPS Technologies Inc All rights reserved microMIPS Instruction Set Architecture 290 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 20
366. rs of the M14K Core Table 5 10 SRSCtI Register Field Descriptions Continued Fields Reset Name Bits Description Read Write State Previous Shadow Set If GPR shadow registers are implemented and with the exclusions noted in the next paragraph this field is copied from the CSS field when an exception or interrupt occurs An ERET instruction copies this value back into the CSS field if Statuspry 0 This field is not updated on any exception which sets StatuSgg to 1 i e Reset Soft Reset NMI cache error an entry into EJTAG Debug mode or any excep tion or interrupt that occurs with Sfatusgy 1 or StatuSpry 1 This field is not updated on an exception that occurs while StatuSgg 1 The operation of the processor is UNDEFINED if soft ware writes a value into this field that is greater than the value in the HSS field Must be written as zeros returns zero on read Current Shadow Set If GPR shadow registers are imple mented this field is the number of the current GPR set With the exclusions noted in the next paragraph this field is updated with a new value on any interrupt or exception and restored from the PSS field on an ERET Table 5 11 describes the various sources from which the CSS field is updated on an exception or interrupt This field is not updated on any exception which sets StatuSppy to 1 i e Reset Soft Reset NMI cache error an entry into EJTAG Debug mode or any excep tion
367. ructions space will cause a reserved instruction exception If assembler support exists the mnemonics for CorExtend instructions are most likely UDIO UDII UDI15 240 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 10 2 M14K Opcode Map Table 10 4 Special3 Opcode Encoding of Function Field function bits 2 0 RIRIRIRIRjRIj Ry Ryel r BLITZ BGEZ TGEI TGEIU BLTZAL BGEZAL Q Q 1 The core will treat the entire row as a BC2 instruction However compiler and assembler support only exists for the first one Some compiler and assembler products may allow the user to add new instructions Table 10 7 COP2 Encoding of rt Field When rs BC2 BC2T BC2TL MIPS32 M14K Processor Core Software User s Manual Revision 02 03 241 Copyright 2009 2010 MIPS Technologies Inc All rights reserved M14K Processor Core Instructions Table 10 8 COPO Encoding of rs Field bits 23 21 Table 10 9 COPO Encoding of Function Field When rs CO function bits 2 0 bits 5 3 000 0 1 2 3 4 5 6 7 10 3 MIPS32 Instruction Set for the M14K core This section describes the MIPS32 instructions for the M14K cores Table 10 10 lists the instruct
368. rved NA Reserved NA 52 Reserved NA Reserved NA MIPS32 M14K Processor Core Software User s Manual Revision 02 03 147 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core Event Num Counter 0 Mode Counter 1 Mode 53 Reserved NA Reserved NA 54 Reserved NA Reserved NA 55 Reserved NA Reserved NA 56 63 Reserved NA Reserved NA Table 5 40 Event Descriptions Event Event Name Counter Number Description Total number of cycles The performance counters are clocked by the top level gated clock If the M14K is built with that clock gater present none of the counters will increment while the clock is stopped e g due to a WAIT instruc tion Instruction ad ai The following events indicate P of various types of instructions Branch instns Counts all branch instructions that completed JR R31 return instns Counts all JR R31 instructions that completed JR not R31 Counts all JR xx not 31 and JALR instructions indirect jumps Integer instns Non floating point non Coprocessor 2 instructions J JJAL Direct Jump And Link instruction microMIPS All microMIPS instructions no ops This includes all instructions that normally write to a GPR but where the destination register was set to r0 Integer Multiply Divide Counts all Integer Multiply Divide instructions MULxx DIVx MADDx MSUBx SC Counts conditional stores
369. rview MIPS drseg bus rd wr port Out_Valid iFlowtrace MIPS Optional Off chip Core PIB _ gt In_TraceOn trace Ef port In Stall FIFO Control trace on trace off From trigger block 216 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 8 iFlowtrace Mechanism 8 8 4 ITCB IFlowTrace Interface The iFlowtrace interface consists of 57 data signals plus a valid signal The 57 data signals encode information about what the CPU is doing in each clock cycle Valid indicates that the CPU is executing an instruction in this cycle and therefore the 57 data signals carry valid execution information The iFlowtrace data bus is encoded as shown in Table 8 35 Note that all the non defined upper bits of the bus are zeroes Table 8 35 Data Bus Encoding Valid Data LSBs Description 0 X No instructions executed in this cycle 1 0 Normal Mode Sequential instruction executed 1 Ol Normal Mode Branch executed destination predictable from code 1 850011 Normal Mode Discontinuous instruction executed PC offset is 8 bit signed offset 1 1621011 Normal Mode Discontinuous instruction executed PC offset is 16 bit signed off set 1 lt NCC gt lt 31 gt 0111 Normal Mode Discontinuous instruction or synchronization record No Code Compression NCC bit included as well as 31 MS
370. s Name Bit s Description Read Write Reset State Company Opt 31 24 Company Option Whatever is specified by the SoC R Preset builder who synthesizes the M14K refer to your SoC manual It should be preset at config GUI with a number between 0x00 and 0x7F higher values 0x80 OxFF are reserved by MIPS Technologies MIPS32 M14K Processor Core Software User s Manual Revision 02 03 121 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core Table 5 21 PRid Register Field Descriptions Continued Fields Name Bit s Description Read Write Reset State Company ID Identifies the company that designed or manufactured the processor In the M14K this field contains a value of 1 to indicate MIPS Technologies Inc Processor ID Identifies the type of processor This field allows software to distinguish between the various types of MIPS Technol ogies processors Revision Specifies the revision number of the processor This field allows software to distinguish between one revision and another of the same processor type This field is broken up into the following three subfields Major Revi This number is increased on major revisions of the proces Preset sion sor core Minor Revi This number is increased on each incremental revision of Preset sion the processor and reset on each new major revision Patch Level 1 0 If a patch is made to
371. s on page 65 for a complete discussion of enabled interrupts Encoding Meaning 0 Interrupt request disabled 1 Interrupt request enabled In implementations of Release 2 of the Architecture in which EIC interrupt mode is enabled Config3ypic 1 these bits take on a different meaning and are interpreted as the PL field described below MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 1 for NMI 0 otherwise Undefined Undefined for IM7 IM2 0 for IM9 IM8 5 2 CPO Register Descriptions Table 5 8 Status Register Field Descriptions Continued Fields Name Bits Description Read Write Reset State IPL 18 16 10 Interrupt Priority Level In implementations of Release 2 of the Architecture in which EIC interrupt mode is enabled Config3ypic 1 this field is the encoded 0 63 value of the current IPL An interrupt will be signaled only if the requested IPL is higher than this value If EIC interrupt mode is not enabled Config3ygqc 0 these bits take on a different meaning and are interpreted as the M7 IM2 bits described above R W Undefined for IPL15 IPL10 0 for IPL18 IPL17 IMI IMO UM 9 8 7 5 Interrupt Mask Controls the enabling of each of the soft ware interrupts Refer to Section 4 3 Interrupts for a complete discussion of enabled
372. s The MADD MADDU and MSUB MSUBU operations are commonly used in DSP algo rithms All multiply operations except the MUL instruction write to the HI LO register pair All integer operations write to the general purpose registers GPR Because MDU operations write to different registers than integer operations fol lowing integer instructions can execute before the MDU operation has completed The MFLO and MFHI instructions are used to move data from the HI LO register pair to the GPR file If a MFLO or MFHI instruction is issued before the MDU operation completes it will stall to wait for the data 2 3 MDU Pipeline High Performance MDU 34 The M14K processor core contains an autonomous multiply divide unit MDU with a separate pipeline for multiply and divide operations This pipeline operates in parallel with the integer unit IU pipeline and does not stall when the IU pipeline stalls This allows multi cycle MDU operations such as a divide to be partially masked by system stalls and or other integer unit instructions The MDU consists of a 32x16 Booth encoded multiplier array a carry propagate adder result accumulation registers HI and LO multiply and divide state machines and all necessary multiplexers and control logic The first number shown 32 of 32x16 represents the rs operand The second number 16 of 32x16 represents the rt operand The core only checks the latter rt operand value to determine how many times the
373. s UNDEFINED if a value is written to any field in this register that is greater than the value of SRSCthyss The SRSMap register contains the shadow register set numbers for vector numbers 7 0 The same shadow set number can be established for multiple interrupt vectors creating a many to one mapping from a vector to a single shadow register set number Figure 5 9 shows the format of the SRSMap register Table 5 12 describes the SRSMap register fields Figure 5 9 SRSMap Register Format 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 SSV7 SSV6 SSV5 SSV4 SSV3 SSV2 SSV1 SSVO Table 5 12 SRSMap Register Field Descriptions Fields Name Bits Description Read Write Reset State SSV7 31 28 Shadow register set number for Vector Number 7 R W 0 SSV6 27 24 Shadow register set number for Vector Number 6 R W 0 SSV5 23 20 Shadow register set number for Vector Number 5 R W 0 SSV4 19 16 Shadow register set number for Vector Number 4 R W 0 SSV3 15 12 Shadow register set number for Vector Number 3 R W 0 SSV2 11 8 Shadow register set number for Vector Number 2 R W 0 SSVI T 4 Shadow register set number for Vector Number 1 R W 0 SSVO 3 0 Shadow register set number for Vector Number 0 R W 0 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 111 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core 5 2 10 View_IPL Regis
374. saved SRSCtl mtcO k1 CO EPC and EPC mtcO k0 CO SRSCt1 Restore shadow sets ehb Clear hazard eret Dismiss the interrupt 4 3 1 3 External Interrupt Controller Mode External Internal Interrupt Controller Mode redefines the way that the processor interrupt logic is configured to pro vide support for an external interrupt controller The interrupt controller is responsible for prioritizing all interrupts including hardware software timer and performance counter interrupts and directly supplying to the processor the priority level and vector number of the highest priority interrupt EIC interrupt mode is in effect if all of the following conditions are true e Config9ygjic 1 e IniCtlys 0 e Causey 1 e StatuSpry 0 In EIC interrupt mode the processor sends the state of the software interrupt requests Causerjp po the timer inter rupt request Causey the performance counter interrupt request Caus pc and Fast Debug Channel Interrupt Causegpcy to the external interrupt controller where it prioritizes these interrupts in a system dependent way with other hardware interrupts The interrupt controller can be a hard wired logic block or it can be configurable based on control and status registers This allows the interrupt controller to be more specific or more general as a function of the system environment and needs MIPS32 M14K Processor Core Software User s Manual Revision 02 03 71 Copyright
375. sed by a parity error MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 117 CPO Registers of the M14K Core Table 5 16 Cause Register ExcCode Field Continued Exception Code Value Decimal Hexadecimal Mnemonic Description 31 16 1f Reserved 5 2 13 View_RIPL Register CPO Register 13 Select 4 Figure 5 13 View_RIPL Register Format 31 10 9 2 1 0 0 IPL IP9 IP2 IPO RIPL Table 5 17 View_RIPL Register Field Descriptions Fields Name Bits Description Read Write Reset State Compliance IP1 IPO 1 0 SW Interrupt Pending R W Undefined Required If EIC interrupt mode is not enabled controls which SW interrupts are pending IPO IP2 HW Interrupt Pending Undefined for Required If EIC interrupt mode is not enabled indicates which HW IP7 IP2 interrupts are pending 0 for IP9 IP8 Interrupt Priority Level Undefined Required If EIC interrupt mode is enabled this field indicates the Requested Priority Level of the pending interrupt 31 10 1 0 Must be written as zero returns zero on read Reserved This register gives read access to the P or RIPL field that is also available in the Cause Register The use of this reg ister allows the Interrupt Pending or the Requested Priority Level to be read without extracting that bit field from the Cause Register 5 2 14 NestedExc C
376. ses This mapping is shown in Figure 3 6 When ERL 1 useg and kuseg become unmapped and uncached The ERL behavior is the same as if there was a TLB The ERL mapping is shown in Figure 3 7 The ERL bit is usually never asserted by software It is asserted by hardware after a Reset SoftReset or NMI See 4 8 Exception Descriptions on page 82 for further information on exceptions Figure 3 6 FM Memory Map ERL 0 in the M14K Processor Core Virtual Address kseg3 OxEOO00 0000 kseg2 OxC000_0000 ksegl 0xAO000 0000 kseg0 0x8000 0000 useg kuseg 0x0000 0000 60 Physical Address kseg3 OxEOO00 0000 kseg2 0xCO00 0000 useg kuseg 0x4000 0000 reserved 0x2000 0000 ksegQ ksegl 0x0000_0000 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 3 4 System Control Coprocessor Figure 3 7 FM Memory Map ERL 1 in the M14K Processor Core Virtual Address kseg3 OxE000_0000 kseg2 OxC000_0000 ksegl 0xAO000 0000 kseg0 0x8000 0000 useg kuseg 0x 0000 0000 Physical Address kseg3 OxEO000 0000 kseg2 OxC000_0000 reserved 0x8000_0000 useg kuseg 0x2000_0000 ksegQ ksegl 0x0000 0000 3 4 System Control Coprocessor The System Control Coprocessor CPO is implemented as an integral part of M14K processor core and supports memory management addre
377. set in order to start or stop the timer 8 4 Test Access Port TAP 190 The following main features are supported by the TAP module 5 pin industry standard JTAG Test Access Port TCK TMS TDI TDO TRST_N interface which is compatible with IEEE Std 1149 1 Target chip and EJTAG feature identification available through the Test Access Port TAP controller The processor can access external memory on the EJTAG Probe serially through the EJTAG pins This is achieved through Processor Access PA and is used to eliminate the use of the system memory for debug rou tines Support for both ROM based debugger and debugging both through TAP 8 4 1 EJTAG Internal and External Interfaces The external interface of the EJTAG module consists of the 5 signals defined by the IEEE standard Table 8 27 EJTAG Interface Pins Pin Type Description TCK Test Clock Input Input clock used to shift data into or out of the Instruction or data regis ters The TCK clock is independent of the processor clock so the EJTAG probe can drive TCK independently of the processor clock frequency The core signal for this is called EJ_TCK TMS Test Mode Select Input The TMS input signal is decoded by the TAP controller to control test operation TMS is sampled on the rising edge of TCK The core signal for this is called EJ_TMS TDI Test Data Input Serial input data TDI is shifted into the Instruction register or data regis ters on the ris
378. single step the debug single step exception has priority over all other exceptions except reset and soft reset Debug Register Debug Status Bit Set DSS Additional State Saved None Entry Vector Used Debug exception vector MIPS32 M14K Processor Core Software User s Manual Revision 02 03 83 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M14KT Core 84 4 8 3 Debug Interrupt Exception A debug interrupt exception is either caused by the EjtagBrk bit in the EJTAG Control register controlled through the TAP or caused by the debug interrupt request signal to the CPU The debug interrupt exception is an asynchronous debug exception which is taken as soon as possible but with no specific relation to the executed instructions The DEPC register is set to the instruction where execution should con tinue after the debug handler is through The DBD bit is set based on whether the interrupted instruction was execut ing in the delay slot of a branch Debug Register Debug Status Bit Set DINT Additional State Saved None Entry Vector Used Debug exception vector 4 8 4 Non Maskable Interrupt NMI Exception A non maskable interrupt exception occurs when the S NMI signal is asserted to the processor S NMl is an edge sensitive signal only one NMI exception will be taken each time it is asserted An NMI exception occurs only at instruction boundaries so it does no
379. sor Core Software User s Manual Revision 02 03 105 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core Table 5 9 IntCtl Register Field Descriptions Continued Fields Reset Name Bits Description Read Write State IPPCI 28 26 For Interrupt Compatibility and Vectored Interrupt modes this field specifies the IP number to which the Performance Counter Interrupt request is merged and allows software to determine whether to consider CauSepcy for a potential interrupt Hardware Interrupt Encoding IP bit Source 2 HWO 3 HW1 4 HW2 5 HW3 6 7 HW4 HW5 The value of this bit is set by the static input SI IPPCI 2 0 This allows external logic to communi cate the specific S Int hardware interrupt pin to which the S PClnt signal is attached The value of this field is not meaningful if External Interrupt Controller Mode is enabled The external inter rupt controller is expected to provide this information for that interrupt mode IPFDC 25 23 For Interrupt Compatibility and Vectored Interrupt R Preset or modes this field specifies the IP number to which the Externally Fast Debug Channel Interrupt request is merged and Set allows software to determine whether to consider CauS rgpc for a potential interrupt Hardware Encoding IP bit Interrupt Source 2 2 HWO HW1 HW2 HW3 HW4 HW5 SLD Nm RI
380. ss translation exception handling and other privileged operations Certain CPO registers are used to support memory management Refer to Chapter 5 CPO Registers of the MI4KTM Core on page 95 for more information on the CPO register set MIPS32 M14K Processor Core Software User s Manual Revision 02 03 61 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Memory Management of the M14K Core 62 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts in the M14K Core The M14K processor core receives exceptions from a number of sources including arithmetic overflows I O inter rupts and system calls When the CPU detects one of these exceptions the normal sequence of instruction execution is suspended and the processor enters kernel mode In kernel mode the core disables interrupts and forces execution of a software exception processor called a handler located at a specific address The handler saves the context of the processor including the contents of the program counter the current operating mode and the status of the interrupts enabled or disabled This context is saved so it can be restored when the exception has been serviced When an exception occurs the core loads the Exception Program Counter EPC register with a location where exe cution can restart after the excepti
381. sses used for the stack memory transactions must be naturally aligned If either of the two least significant bits of the address is non zero an Address Error exception occurs IRET implements a software barrier that resolves all execution and instruction hazards created by Coprocessor 0 state changes for Release 2 implementations refer to the SYNCI instruction for additional information on resolving instruction hazards created by writing the instruction stream The effects of this barrier are seen starting with the instruction fetch and decode of the instruction at the PC to which the IRET returns In a Release 2 implementation IRET does not restore SESCtlcss from SRSCtlpss if Statusggy 1 or if Statusgpy 1 because any exception that sets Statusgp to 1 Reset Soft Reset NMI or cache error does not save SRSCticgg in SRSCtlpss If software sets Statusgpz to 1 it must be aware of the operation of an IRET that may be subsequently executed The stack memory transactions behave as individual LW operations with respect to exception reporting BadVAddr would report the faulting address for unaligned access and the faulting word address for unprivileged access TLB Refill and TLB Invalid exceptions For TLB exceptions the faulting word address would be reflected in the Context and EntryHi registers The CacheError register would reflect the faulting word address for Cache Errors Operation if IntCtlapg 0 Statusgp
382. st stage when the first divide is in the Reg WR stage Figure 2 6 High Performance MDU Pipeline Flow During a 8 bit Divide DIV Operation Clock 1 2 3 4 10 11 12 13 E Stage Mypy Stage Mypy Stage Mmpu Stage gt Mmpu Stage Ampu Stage Wmpu Stage gt RS Adjust Add Subtract Add Subtract Rem Adjust Sign Adjust MDU Res Rdy Early In Figure 2 7 High Performance MDU Pipeline Flow During a 16 bit Divide DIV Operation Clock 1 2 3 4 18 19 20 21 Estage P4 Munu Stage P Mupu Stage P Mupu Stage 4 Mupu Stage 4 Ampu Stage P Wunu Stage gt RS Adjust Add Subtract Add Subtract Rem Adjust Sign Adjust MDU Res Rdy Early In 38 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 2 4 MDU Pipeline Area Efficient MDU Figure 2 8 High Performance MDU Pipeline Flow During a 24 bit Divide DIV Operation Clock 1 2 3 4 26 27 28 29 Estage PE Mupu Stage A Mupu Stage P Mapu Stage Muu Stage P Ampu Stage P Wunu Stage P LI LJ LI LI LI LI LJ RS Adjust Add Subtract Add Subtract Rem Adjust Sign Adjust MDU Res Rdy Early In Figure 2 9 High Performance MDU Pipeline Flow During a 32 bit Divide DIV Operation Clock 1 2 3 4 34 35 36 37 Estage P E Munu Stage P Mupu Stage P Mapu Stage P Mupu Stage Je Ampu Stage P Wunu Stage P L
383. stage high performance MDU MTHI MTLO DIV 32bx32b yl E stage DIV MUL MULTx MADDx Until DIV completes E stage MSUBx MTHI MTLO MFHI MFLO DIV MULT MUL MADD MSUB MTHI MTLO MF MULT MUL MADD MSUB Until 1st MDU op E stage HI MFLO DIV MTHI MTLO MFHI MFLO completes area efficient MDU DIV MUL Any Instruction Until MUL completes E stage area efficient MDU MFCO MFC2 CFC2 Consumer of target data 1 E stage 2 11 Hazards In general the M14K core ensures that instructions are executed following a fully sequential program model in which each instruction in the program sees the results of the previous instruction There are some deviations to this model referred to as hazards Prior to Release 2 of the MIPS32 Architecture hazards primarily CPO hazards were relegated to implementa tion dependent cycle based solutions primarily based on the SSNOP instruction This has been an insufficient and error prone practice that must be addressed with a firm compact between hardware and software As such new instructions have been added to Release 2 of the architecture which act as explicit barriers that eliminate hazards To the extent that it was possible to do so the new instructions have been added in such a way that they are back ward compatible with existing MIPS processors MIPS32 M14K Processor Core Software User s Manual Revision 02 03 47 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Pipeline of the
384. stage The MDU pipeline is shown as the shaded areas of Figure 2 3 and always starts a computation in the final phase of the E stage As shown in the figure the Mypy pipe stage of the MDU pipeline occurs in parallel with the M stage of the IU pipeline the Ay stage occurs in parallel with the A stage and the Wypy stage occurs in parallel with the W stage In general this need not be the case Following the 1st cycle of the M stages the two pipelines need not be synchronized This does not present a problem because results in the MDU pipeline are written to the HI and LO registers while the integer pipeline results are written to the register file Figure 2 3 MDU Pipeline Behavior During Multiply Operations cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 E E qu x pr Tm ee l l i f l l l Mult I E Mwpu Em WMDU l l Add j I E M A Ww l Mult I E Nem EE NES Waipu Sub l l I E M A WwW l i The following is a cycle by cycle analysis of Figure 2 3 1 The first 32x16 multiply operation Mult is fetched from the instruction cache and enters the I stage 36 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 2 3 MDU Pipeline High Performance MDU 2 An Add operation enters the I stage The Mult operation enters the E stage The integer and MDU pipelines share the I
385. sters DEBUG DEBUG2 DEPC and DESAVE have been added to the MIPS Coprocessor 0 CPO register set The DEBUG and DEBUG 2 registers show the cause of the debug exception and are used for setting up single step operations The DEPC Debug Exception Program Counter register holds the address on which the debug exception was taken which is used to resume program execution after the debug operation finishes Finally the DESAVE Debug Exception Save register enables the saving of general purpose registers used during execution of the debug exception handler To exit debug mode a Debug Exception Return DERET instruction is executed When this instruction is executed the system exits debug mode allowing normal execution of application and system code to resume EJTAG Hardware Breakpoints There are several types of simple hardware breakpoints defined in the EJTAG specification These stop the normal operation of the CPU and force the system into debug mode There are two types of simple hardware breakpoints implemented in the M14K core Instruction breakpoints and Data breakpoints Additionally complex hardware breakpoints can be included which allow detection of more intricate sequences of events The M14K core can be configured with the following breakpoint options e No data instruction or complex breakpoints e One data and two instruction breakpoints without complex breakpoints e Two data and four instruction breakpoints without complex b
386. sters of the M14K Core 102 Table 5 8 Status Register Field Descriptions Continued Fields Name Bits Description Read Write Reset State R 24 23 BEV 22 Reserved This field is ignored on writes and reads as 0 Controls the location of exception vectors Encoding 0 Normal 1 Bootstrap Meaning TS 21 SR 20 TLB shutdown Because the M14K core does not contain a TLB this bit is ignored on writes and reads as 0 Indicates that the entry through the reset exception vector was due to a Soft Reset Encoding 0 Not Soft Reset NMI or Reset 1 Soft Reset Meaning Software can only write a 0 to this bit to clear it and cannot force a 0 1 transition 1 for Soft Reset 0 other wise NMI 19 CEE 17 IM9 IM2 18 16 10 Indicates that the entry through the reset exception vector was due to an NMI Encoding 0 Not NMI Soft Reset or Reset 1 NMI Meaning Software can only write a 0 to this bit to clear it and cannot force a 0 1 transition CorExtend Enable Implementation dependent If CorEx tend block indicates that this bit should be used any attempt to execute a CorExtend instruction with this bit cleared will result in a CorExtend Unusable exception This bit is reserved if CorExtend is not present Interrupt Mask Controls the enabling of each of the hard ware interrupts Refer to 4 3 Interrupt
387. stored with the instruction breakpoint that is being qualified Writing its IBCCn register will disqualify that breakpoint e Qualified instruction breakpoint can also have priming conditions and or pass counters enabled The pass counter will only decrement when the priming and qualifying conditions have been met The instruction breakpoint action break trigger or complex enable will only occur when all priming qualifying and pass counter condi tions have been met e Qualified instruction breakpoint can be used to prime another breakpoint 8 3 7 Usage of Stopwatch Timers The stopwatch timer is a drseg memory mapped count register It can be configured to be free running or controlled by instruction breakpoints This could be used to measure the amount of time that is spent in a particular function by starting the counter upon function entry and stopping it upon exit e Count value is reset to 0 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 189 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Reset state has counter stopped and under breakpoint control so that the counter is not running when the core is not being debugged Bit in CBTControl register controls whether the counter is free running or breakpoint controlled Counter does not count in debug mode When breakpoint controlled the involved instruction breakpoints must have BCnrg or IBCCngogg
388. stqer cea lexpencdecadhaxad nddtQ and EA Sec URNA AS 189 E NEVER 190 8 4 1 EJTAG Internal and External Interfaces 2 eterni eren aAA ENR 190 8 4 2 Test ACCESS POM ODBFADIOTI editoria or dee ib bes ferais ka peat O kx bros Vea xeu e rsen a Rua 191 8413 Test Access Port TAP Instf ctlOns scossi sin a a A 194 8 5 EJTAG TAP REGISCKS iage E a ES ires EE E du E N TO 197 Sa k MSEMICHOM Foge Olsi 197 8 5 2 Data Registers OVBIVIGW rarianang raora eai na 198 8 5 3 Processor Access Address Register unco oisi oce str a ia 206 8 5 4 Fastdata Register TAP Instruction EASTDATA ieieto n nte tren retten 207 6 05 TAF PIOCESSON ACCESSES e aAA 208 8 6 1 Fetch Load and Store from to EJTAG Probe Through dmseg sss 209 SAvEESI IMUI IBI eoe EE 210 eg s Disabling Ed FAQ debttggilig s t occae chat aieo ec tette n Date i iE IE 210 8 7 2 EJTAG Features Unmodified by SecureDebug sssesssesseesenene nennen 211 8 8 iElowtrace M MOCRaHISITI sco cete kar SR ER Rc aao aridan anae 211 8 8 1 A Simple Instruction Only Tracing Scheme ces cope erro aaa a pas gOS 212 8 9 2 Special Trace MOGOGS etti ond testes tete ptus assent iuter au etos ut aute tec Pra Mes teP erui T Rue eR NUES RUE S 213 8 33 GB OVBIVIBW c codo oit iececa dept usu tre stem ead AN ibt c ei sbepe sue esee neues acs 216 8 9 dT GB IEIOWTrace IBIGE Tae oer erroe EEE ERO a r ua Sponsa TN 217 8 8 5 T OB Storage HepreseltallOl s ceo preces beress e
389. switching shadow sets write new value to S ins k0 zero S StatusEXL mtcO k0 CO Status If switching shadow sets and do execute an eret to clear EXL shadow sets and jump to routine address to EPC us Process interrupt here W StatusKSU W Status Clear KSU ERL Modify IPL Save in memory 6 Set IPL to RIPL in copy of Status Save SRSCtl if changing shadow sets EXL bit switch to kernel mode RSCtlpss here ERL W_StatusEXL s in k0 re enable interrupts clear only KSU above write target switch including clearing device interrupt The interrupt completion code is identical to that shown for VI mode above 4 4 3 2 Generation of Exception Vector Offsets for Vectored Interrupts For vectored interrupts in either VI or EIC interrupt mode a vector number is produced by the interrupt control logic This number is combined with ntCtlVS to create the interrupt offset which is added to 16 200 to create the exception vector offset For VI interrupt mode the vector number is in the range 0 9 inclusive For EIC interrupt mode the vector number is in the range 0 63 inclusive The ntCtlVS field specifies the spacing between vector loca tions If this value is zero the default reset state the vector spacing is zero and the processor reverts to Interrupt Compatibility Mode A non zero value enables vectored interrupts and Ta
390. t accordingly Fields Name Bits 31 Figure 5 38 CacheErr Register Primary Caches 30 29 ER EB Addr Table 5 43 CacheErr Register Field Descriptions Primary Caches Description Read Write Reset State ER 31 Error Reference Indicates the type of reference that encountered an error Encoding Meaning 0 Instruction 1 Data Undefined 150 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 43 CacheErr Register Field Descriptions Primary Caches Continued Fields Name Bits Description Read Write Reset State EB 30 Error Both Indicates that a data SRAM parity error occurred in R Undefined addition to an instruction SRAM parity error Encoding Meaning 0 No additional data SRAM parity error 1 Additional data SRam parity error In the case of an additional data SRAM parity error the remainder of the bits in this register are set according to the instruction SRAM parity error Addr 29 0 Error address Specifies on which address the error was detected R Undefined 5 2 37 ErrorEPC CPO Register 30 Select 0 The ErrorEPC register is a read write register similar to the EPC register except that ErrorEPC is used on error exceptions All bits
391. t cause any reset or other hardware initialization The state of the cache memory and other processor states are consistent and all registers are preserved with the following exceptions The BEV TS SR NMI and ERL fields of the Status register are initialized to a specified state e The ErrorEPC register is loaded with PC 4 if the state of the processor indicates that it was executing an instruc tion in the delay slot of a branch Otherwise the ErrorEPC register is loaded with PC e PC is loaded with OXBFCO 0000 Cause Register ExcCode Value None Additional State Saved None Entry Vector Used Reset OXBFCO 0000 Operation Statusggy amp 1 Statusgg amp 0 Statusgg amp 0 Statusyyr 1 StatuSga amp 1 if InstructionInBranchDelaySlot then ErrorEPC amp PC 4 else MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 8 Exception Descriptions ErrorEPC PC endif PC lt OxBFCO 0000 4 8 5 Interrupt Exception The interrupt exception occurs when one or more of the six hardware two software or timer interrupt requests is enabled by the Status register and the interrupt input is asserted See 4 3 Interrupts on page 65 for more details about the processing of interrupts Register ExcCode Value Int Additional State Saved Table 4 10 Register States an Interrupt Exception
392. t for complex breaks Eight instruction and four data breakpoints with support for complex breaks Instruction breaks occur on instruction fetch operations and the break is set on the virtual address on the bus between the CPU and the instruction cache Finally a mask can be applied to the virtual address to set breakpoints on a range of instructions Instruction breakpoints compare the virtual address of the executed instructions the value of PC with the registers for each instruction breakpoint including masking of address When an instruction breakpoint matches a debug exception and or a trigger is generated An internal bit in the instruction breakpoint registers is set to indicate that the match occurred 8 2 1 Data Breakpoints Data breakpoints occur on load store transactions Breakpoints are set on virtual address values similar to the Instruc tion breakpoint Data breakpoints can be set on a load a store or both Data breakpoints can also be set based on the value of the load store operation Finally masks can be applied to both the virtual address and the load store value Data breakpoints compare the transaction type TYPE which may be load or store the virtual address of the transac tion ADDR accessed bytes BYTELANE and data value DATA with the registers for each data breakpoint including masking or qualification on the transaction properties When a data breakpoint matches a debug exception and or a trigger is gen
393. t indicating which mode is supported IO Inhibit overflow If set the CPU is stalled whenever the Required trace memory is full Ignored unless OfC is also set En Trace enable This bit may be set by software or by Required Trace on Trace off action bits from the Complex Trigger block Software writes EN with the desired initial state of tracing when the ITCB is first turned on and EN is con trolled by hardware thereafter EN turning on and off does not flush partly filled trace words On Software control of trace collection 0 disables all collec Required tion and flushes out any partially filled trace words 8 8 6 2 ITCBTW Register offset OX3F80 The TCBTW register is used to read Trace Words from the on chip trace memory The TW read is the TW pointed to by the TCBRDP register A side effect of reading the ITCBTW register is that the TCBRDP register increments to the next TW in the on chip trace memory If TCBRDP is at the max size of the on chip trace memory the increment wraps back to address zero Note that this is a 64b register On a 32b processor software must read the upper word offset Ox3F84 first as the address increment takes place on a read of the lower word 0x3F80 The format of the TCBTW register is shown below and the field is described in Table 8 38 Figure 8 32 ITCBTW Register Format 63 0 Data Table 8 38 ITCBTW Register Field Descriptions Fields Description Compliance Na
394. t physical addresses OxE000 0000 OxFFFF_FFFF 3 2 4 Debug Mode Debug mode address space is identical to Kernel mode address space with respect to mapped and unmapped areas except for kseg3 In kseg3 a debug segment dseg co exists in the virtual address range OXFF20 0000 to OxFF3F FFFF The layout is shown in Figure 3 5 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 57 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Memory Management of the M14K Core Figure 3 5 Debug Mode Virtual Address Space OxFFFF FFFF OxFFA40 0000 ksegl kseg0 Unmapped Mapped if mapped in Kernel Mode 0x0000 0000 The dseg is sub divided into the dmseg segment at OXFF20 0000 to OXFF2F FFFF which is used when the probe ser vices the memory segment and the drseg segment at OxXFF30 0000 to OxFF3F_FFFF which is used when mem ory mapped debug registers are accessed The subdivision and attributes for the segments are shown in Table 3 3 Accesses to memory that would normally cause an exception if tried from kernel mode cause the core to re enter debug mode via a debug mode exception The unmapped kseg0 and kseg1 segments from kernel mode address space are available from debug mode which allows the debug handler to be executed from uncached and unmapped memory Table 3 3 Physical Address and Cache Attributes for dseg dmseg and drseg Address Spaces Segment Sub Segment Cache Name Name Virt
395. t the rising edge of TCK the controller transitions to the Run Test Idle state A HIGH on TMS causes the controller to transition to the Select DR Scan state The instruction cannot change while the TAP controller is in this state and all shift register stages in the test data registers selected by the current instruction retain their previous state MIPS32 M14K Processor Core Software User s Manual Revision 02 03 193 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core 194 8 4 2 11 Capture_IR State In this state the shift register contained in the Instruction register loads a fixed pattern 00001 on the rising edge of TCK The data registers selected by the current instruction retain their previous state If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Shift_IR state A HIGH on TMS causes the controller to transition to the Exit _JR state The instruction cannot change while the TAP controller is in this state 8 4 2 12 Shift_IR State In this state the instruction register is connected between TD and TDO and shifts data one stage toward its serial out put on the rising edge of TCK If TMS is sampled LOW at the rising edge of TCK the controller remains in the Shift IR state A HIGH on TMS causes the controller to transition to the Exit IR state 8 4 2 13 Exit1 IR State This is a temporary controller state in which all registers retain t
396. t way with hardware interrupt 5 In implementations of Release 2 of the Architecture in which EIC interrupt mode is not enabled Config3ypc 0 timer and performance counter interrupts are com bined in an implementation dependent way with any hardware interrupt If EIC interrupt mode is enabled Config3ygic 1 these bits take on a different mean ing and are interpreted as the RIPL field described below RIPL 17 10 Requested Interrupt Priority Level R Undefined for In implementations of Release 2 of the Architecture in bits 15 10 which EIC interrupt mode is enabled Config3yg c 1 this field is the encoded 0 255 value of the 0 for bits 17 16 requested interrupt A value of zero indicates that no interrupt is requested If EIC interrupt mode is not enabled Config3ypc 0 these bits take on a different meaning and are interpreted as the P7 P2 bits described above 116 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 15 Cause Register Field Descriptions Continued Fields Name Bits Description Read Write Reset State IP1 IPO 9 8 Controls the request for software interrupts R W Undefined Bit Name Meaning 9 IP1 Request software interrupt 1 8 IPO Request software interrupt 0 These bits are exported to an external interru
397. tart or stop the stopwatch timer or as part of a tuple breakpoint DBrkNum Indicates which data breakpoint channel is used to qualify R 6I 2D Complex Breakpoint this instruction breakpoint Configuration IBCCO 2 0 IBCC3 6 1 8I AD Complex Breakpoint Configuration IBCCO 1 0 IBCC2 3 1 IBCC4 5 2 IBCC6 7 3 Q Qualify this breakpoint based on the data breakpoint indi R W 0 cated in DBrkNum 0 Not dependent on qualification 1 Breakpoint must be qualified to be taken 8 2 6 7 Instruction Breakpoint Pass Counter n IBPCn Register 0x1128 n 0x100 Compliance Level Implemented only if complex breakpoints are implemented and only for implemented instruction breakpoints The Instruction Breakpoint Pass Counter n IBPCn register controls the pass counter associated with instruction breakpoint n If complex breakpoints are implemented there will be an 8b pass counter for each of the instruction breakpoints on the M14K core MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints Figure 8 8 IBPCn Register Format 31 8 7 0 ee Table 8 9 IBPCn Register Field Descriptions Description Read Write Reset State 0 Ignored on write returns zero on read PassCnt Prevents a break trigger action until the matching condi tions on breakpoint n have been seen this number of times Each time the
398. tart the counter if the timer is under pairO breakpoint control EnO 0 Enables the first pair pairO of breakpoint registers to R 1 control the timer when under breakpoint control If the stopwatch timer is configured to be under breakpoint control by setting CBTControlSTM and this bit is set the breakpoints indicated in the StartChanO and StopChan0 fields will control the timer The M14K core only supports 1 pair of stopwatch con trol breakpoints so this field is not writable and will read as 1 8 2 8 4 Stopwatch Timer Count STCnt Register 0x8908 Compliance Level Implemented if stopwatch timer is implemented The Stopwatch Timer Count STCnt register is the count value for the stopwatch timer Figure 8 21 STCnt Register Format 31 0 Count Table 8 26 STCtl Register Field Descriptions Fields Read Wr Name Bit s Description ite Reset State Count 31 0 Current counter value R W 0 8 3 Complex Breakpoint Usage 8 3 1 Checking for Presence of Complex Break Support Software should verify that the complex breakpoint hardware is implemented prior to attempting to use it The full sequence of steps is shown below for general use Spots where the M14K core has restricted behavior are noted 1 Read the Config1EP bit to check for the presence of EJTAG logic EJTAG logic is always present on an MI4K core 186 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright
399. tate of a cache line for a location with an uncached memory access type whether this type is specified by the address segment e g kseg1 the programmed coherency attribute of a segment e g the use of the KO KU or K23 fields in the Config register or the per page coherency attribute provided by the TLB If PREF results in a memory operation the memory access type and coherency attribute used for the operation are determined by the memory access type and coherency attribute of the effective address just as it would be if the memory operation had been caused by a load or store to the effective address Values of hint Field for PREF Instruction Value Name Data Use and Desired Prefetch Action 0 load Use Prefetched data is expected to be read not modified Action Fetch data as if for a load Use Prefetched data is expected to be stored or modified Action Fetch data as if for a store Reserved load_streamed Use Prefetched data is expected to be read not modified but not reused extensively it streams through cache store_streamed Use Prefetched data is expected to be stored or modified but not reused exten sively it streams through cache 6 load_retained Use Prefetched data is expected to be read not modified and reused exten sively it should be retained in the cache 7 store_retained Use Prefetched data is expected to be stored or modified and reused exten sively it should
400. te Reset State This field controls the cacheability of the kseg2 and kseg3 address segments in FM implementations Refer to Table 5 24 for the field encoding This field controls the cacheability of the kuseg and useg address segments in FM implementations Refer to Table 5 24 for the field encoding 24 23 Must be written as 0 Returns zero on reads 0 2 This bit indicates that CorExtend User Defined Instructions Preset have been implemented 0 No User Defined Instructions are implemented 1 User Defined Instructions are implemented 2 Indicates whether SimpleBE bus mode is enabled Set via Externally Set SI SimpleBE 0 input pin 0 No reserved byte enables on SRAM interface 1 Only simple byte enables allowed on SRAM interface 2 This bit indicates the type of Multiply Divide Unit present 0 Fast high performance MDU 2 1 0 1 Iterative area efficient MDU 16 5 19 17 Must be written as 0 Returns zero on reads Dual SRAM interface 0 Unified instruction data SRAM interface 1 Dual instruction data SRAM interfaces 1 Indicates the endian mode in which the processor is run Externally Set ning Set via S _Endian input pin 0 Little endian 1 Big endian Architecture type implemented by the processor This field is always 00 to indicate the MIPS32 architecture Architecture revision level This field is always 001 to indi cate MIPS32 Release 2 0 Release 1 1 Release 2 2 7 Reserved
401. te fields 31 26 25 21 20 16 15 0 Major Opcode Minor Opcode Other rs fs Immediate 31 26 25 21 20 16 15 0 Major Opcode rt ft rs fs Immediate 32 bit instruction formats with 12 bit immediate fields 31 26 25 21 20 16 15 12 11 0 Major Opcode Other rs fs Minor Opcode Immediate 31 26 25 21 20 16 15 12 11 0 Major Opcode rt ft rs fs Minor Opcode Immediate MIPS32 M14K Processor Core Software User s Manual Revision 02 03 11 3 microMIPS Re encoded Instructions The instruction size can be completely derived from the major opcode For 32 bit instructions the major opcode also defines the position of the minor opcode field and whether or not the immediate field is right aligned Instructions formats are named according to the number of the register fields and the size of the immediate field The names have the structure R lt x gt I lt y gt For example an instruction based on the format R2116 has 2 register fields and a 16 bit immediate field 11 2 1 Instruction Stream Organization and Endianness 16 bit instructions are placed within the 32 bit or 64 bit memory element according to system endianness e Ona 32 bit processor in big endian mode the first instruction is read from bits 31 16 and the second instruction is read from bits 15 0 e Ona32 bit processor in little endian mode the first instruction is read from bits 15 0 and the second instruction is read from bits 31 16 The above rule also applies to th
402. tential interrupt taken here Exceptions Coprocessor Unusable Exception MIPS32 M14K Processor Core Software User s Manual Revision 02 03 273 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 274 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 11 microMIPS Instruction Set Architecture The microMIPS architecture minimizes the code footprint of applications thus reducing the cost of memory which is particularly high for embedded memory At the same time the high performance of MIPS cores is main tained Using this technology the customer can generate best results without spending time to profile its application The smaller code footprint typically leads to reduced power consumption per executed task because of the smaller number of memory accesses microMIPS is a replacement for the existing MIPS16e ASE It is also an alternative to the MIPS32 instruction encod ing and can be implemented in parallel or stand alone Overview of changes from the existing MIPS32ISA e 16 bit and 32 bit opcodes for MIPS64 also 48 bit opcodes e Optimized opcode operand field definitions based on statistics e Branch and jump delay slots will be kept for maximum compatibility and lowest risk e Removal of branch likely instructions emulation by assembler e Fine tuned register allocation algorithm in the compiler for low
403. ter CPO Register 12 Select 4 Figure 5 10 View_IPL Register Format 31 10 9 0 0 IM IPL Table 5 13 View_IPL Register Field Descriptions Fields Read Name Bits Description Write Reset State Compliance IM 9 0 Interrupt Mask R W Undefined for Required If EIC interrupt mode is not enabled controls which inter IM7 IM2 rupts are enabled 0 for IM9 IM8 IPL 9 2 Interrupt Priority Level R W Undefined Required If EIC interrupt mode is enabled this field is the encoded value of the current PL 31 10 1 0 Must be written as zero returns zero on read 0 0 Reserved 112 This register gives read and write access to the M or PL field that is also available in the Status Register The use of this register allows the Interrupt Mask or the Priority Level to be read written without extracting inserting that bit field from to the Status Register The PL field might be located in non contiguous bits within the Status Register All of the PL bits are presented as a contiguous field within this register 5 2 11 SRSMap2 Register CPO Register 12 Select 5 The SRSMap2 register contains 2 4 bit fields that provide the mapping from an vector number to the shadow set number to use when servicing such an interrupt The values from this register are not used for a non interrupt excep tion or a non vectored interrupt Causejy 0 or ntCth s 0 In such cases the shadow set number comes f
404. tered Data Tracing mode is enabled IFCTLpprz cAusp l Function Call Return and Exception Tracing Mode In this mode the PC value of function calls and returns and or exceptions and returns are traced out This mode can only be used when normal tracing mode is turned off This mode cannot be used in conjunction with other special trace modes The function call return and exception return are independently enabled or disabled via the FCR and ER bits in the Control Status register see Section 8 8 6 ITCB Register Interface for Software Configurability These events are reported for the following instructions e MIPS22 function calls JAL JALR JALR HB JALX e microMIPS function calls JAL JALR JALR HB JALX JALR16 JALRS16 JALRS JALRS HB JALS e MIPS32 function returns JR JR HB e microMIPS function returns JR JR HB JRC JRADDIUSP JR16 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 8 8 iFlowtrace Mechanism e Exceptions Reported on the first instruction of the exception handler Exception returns ERET e MCU ASE Interrupt returns IRET Other Trace Messages In any of the special trace modes it is possible to embed messages into the trace stream directly from a program This is done by writing to the UserTraceData1 or UseTraceData2 Cop0 registers When UserTraceData register is writ ten a trace message of type User Tr
405. ternal agents what the state of the chip is MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 6 EJTAG Debug Support in the M14K Core The EJTAG debug logic in the M14K processor core provides three optional modules 1 Hardware breakpoints 2 Test Access Port TAP for a dedicated connection to a debug host 3 Tracing of program counter data address data value trace to On chip memory or to a Trace probe These features are covered in the following sections e Section 8 1 Debug Control Register e Section 8 2 Hardware Breakpoints e Section 8 3 Complex Breakpoint Usage e Section 8 4 Test Access Port TAP e Section 8 5 EJTAG TAP Registers e Section 8 6 TAP Processor Accesses e Section 8 7 SecureDebug e Section 8 8 iFlowtrace Mechanism e Section 8 9 PC Data Address Sampling e Section 8 10 Fast Debug Channel e Section 8 11 cJTAG Interface 8 1 Debug Control Register The Debug Control Register DCR register controls and provides information about debug issues and is always pro vided with the CPU core The register is memory mapped in drseg at offset 0x0 The DataBrk and InstBrk bits indicate if hardware breakpoints are included in the implementation and debug software is expected to read hardware breakpoint registers for additional information Hardware and software
406. ternally Set cessor system and can be used by software to distinguish a particular processor from the others The value in this field is set by the SJ CPUNum 9 0 static input pins to the core In a single processor system this value should be set to zero 5 2 19 CDMMBase Register CPO Register 15 Select 2 The 36 bit physical base address for the Common Device Memory Map facility is defined by this register This regis ter only exists if Config3c py is set to one Figure 5 19 shows the format of the CDMMBase register and Table 5 23 describes the register fields Figure 5 19 CDMMBase Register Format 31 11 10 9 8 0 CDMM UPPER ADDR EN CI CDMMSize Table 5 23 CDMMBase Register Field Descriptions CDMM UP Bits 35 15 of the base physical address of the mem R W Undefined PER ADDR ory mapped registers The number of implemented physical address bits is implementation specific For the unimplemented address bits writes are ignored and reads return zero MIPS32 M14K Processor Core Software User s Manual Revision 02 03 123 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core Table 5 23 CDMMBase Register Field Descriptions Fields Name Bits Description Read Write Reset State Enables the CDMM region If this bit is cleared memory requests to this address region access regular system memory If this bit is set mem
407. ters Coprocessor 0 also contains the logic for identifying and managing exceptions Exceptions can be caused by a variety of sources including boundary cases in data external events or program errors Interrupt Handling The M14K core includes support for eight hardware interrupt pins two software interrupts and a timer interrupt These interrupts can be used in any of three interrupt modes as defined by Release 2 of the MIPS32 Architecture MIPS32 M14K Processor Core Software User s Manual Revision 02 03 21 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Introduction to the MIPS32 6 M14K Processor Core e Interrupt compatibility mode which acts identically to that in an implementation of Release 1 of the Architec ture e Vectored Interrupt VI mode which adds the ability to prioritize and vector interrupts to a handler dedicated to that interrupt and to assign a GPR shadow set for use during interrupt processing The presence of this mode is denoted by the VInt bit in the Config3 register This mode is architecturally optional but it is always present on the MIAK core so the VInt bit will always read as a 1 for the MIAK core e External Interrupt Controller EIC mode which redefines the way in which interrupts are handled to provide full support for an external interrupt controller handling prioritization and vectoring of interrupts The presence of this mode denoted by the VEIC bit in the Config3
408. the Address register to be connected between TDI and TDO The EJTAG Probe shifts 32 bits through the TD pin into the Address register and shifts out the captured address via the TDO pin MIPS32 M14K Processor Core Software User s Manual Revision 02 03 195 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core 8 4 3 5 DATA Instruction This instruction is used to select the Data register to be connected between TD and TDO The EJTAG Probe shifts 32 bits of TDI data into the Data register and shifts out the captured data via the TDO pin 8 4 3 6 CONTROL Instruction This instruction is used to select the EJTAG Control register to be connected between TD and TDO The EJTAG Probe shifts 32 bits of TD data into the EJTAG Control register and shifts out the EJTAG Control register bits via TDO 8 4 3 7 ALL Instruction This instruction is used to select the concatenation of the Address and Data register and the EJTAG Control register between TD and TDO It can be used in particular if switching instructions in the instruction register takes too many TCK cycles The first bit shifted out is bit O Figure 8 23 Concatenation of the EJTAG Address Data and Control Registers TDI Address 0 Data 0 7 p EJTAG Control 0L TDO 8 4 3 8 EJTAGBOOT Instruction When the EJTAGBOOT instruction is given and the Update IR state is left then the reset values of the P
409. the opcode map are available for UDI and each instruc tion can have single or multi cycle latency A UDI instruction can operate on any one or two general purpose registers or immediate data contained within the instruction and can write the result of each instruction back to a general pur pose register or local register Implementation details for UDI can be found in other documents available from MIPS Refer to Table 10 3 Special2 Opcode Encoding of Function Field for a specification of the opcode map available for user defined instructions MIPS32 M14K Processor Core Software User s Manual Revision 02 03 29 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Introduction to the MIPS32 amp M14K Processor Core 30 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline of the M14K Core The M14K processor core implements a 5 stage pipeline similar to the original R3000 pipeline The pipeline allows the processor to achieve high frequency while minimizing device complexity reducing both cost and power con sumption This chapter contains the following sections e Section 2 1 Pipeline Stages e Section 22 Multiply Divide Operations e Section 2 3 MDU Pipeline High Performance MDU e Section 2 4 MDU Pipeline Area Efficient MDU e Section 2 5 Branch Delay e Section 2 6 D
410. tion ite Reset State EJTAGver EJTAG Version 2 Version 2 6 reserved reserved DINTsup DINT Signal Supported from Probe EJ_DINTsup This bit indicates if the DINT signal from the probe is supported Encoding Meaning 0 DINT signal from the probe is not sup ported Probe can use DINT signal to make debug interrupt MIPS32 M14K Processor Core Software User s Manual Revision 02 03 199 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core Table 8 30 Implementation Register Descriptions Fields Read Wr Name Bit s Description ite Reset State ASIDsize 23 21 Size of ASID field in implementation R 0 Encoding Meaning 0 No ASID in implementation 1 6 bit ASID 2 8 bit ASID 3 Reserved reserved reserved MIPS 16 Indicates whether MIPS 16 is implemented Encoding Meaning 0 No MIPS16 support 1 MIPS 16 implemented reserved reserved NoDMA No EJTAG DMA Support reserved 13 0 reserved R 0 8 5 2 4 EJTAG Control Register This 32 bit register controls the various operations of the TAP modules This register is selected by shifting in the CONTROL instruction Bits in the EJTAG Control register can be set cleared by shifting in data status is read by shifting out the contents of this register This EJTAG Control register can only be accessed by the TAP interf
411. tions of this instruction can be used to reverse the effects of the automated operations of the Auto Prologue feature If the EIC mode of interrupts and the Interrupt Chaining feature are used the IRET instruction can be used to shorten the time between returning from the current interrupt handler and handling the next requested interrupt If Automated Prologue feature is disabled then IRET behaves exactly as ERET If either Statusppy or StatuSggy bits are set then IRET behaves exactly as ERET If Interrupt Chaining is disabled Interrupts are disabled COPO Status SRSCtl and EPC registers are restored from the stack GPR 29 is incre mented for the stack frame size IRET then clears execution and instruction hazards conditionally restores SRSCtlcss from SRSCtlpss and returns to the interrupted instruction pointed by the EPC register at the comple tion of interrupt processing If Interrupt Chaining is enabled Interrupts are disabled COPO Status register is restored from the stack The priority output of the External Inter rupt Controller is compared with the PL field of the Status register If Statusyp has a higher priority than that of the External Interrupt Controller value COPO SRSCt and EPC registers are restored from the stack GPR 29 is incremented for the stack frame size IRET then clears execution and instruction hazards conditionally restores SRSCtlcss from SHSCtlpss and returns to the interrupted instruction point
412. to zero behavior Software reads of this field return the or to the appropriate state respectively on pow last value updated by hardware erup If the Reset State of this field is Undefined If the Reset State of this field is Undefined software reads of this field result in an UNPRE hardware updates this field only under those DICTABLE value except after a hardware conditions specified in the description of the update done under the conditions specified in field the description of the field W A field that can be written by software but which can not be read by software Software reads of this field will return an UNDEFINED value 0 A field that hardware does not update and for A field to which the value written by software which hardware can assume a zero value must be zero Software writes of non zero val ues to this field may result in UNDEFINED behavior of the hardware Software reads of this field return zero as long as all previous software writes are zero If the Reset State of this field is Undefined software must write this field with zero before it is guaranteed to read as zero 5 2 1 UserLocal Register CPO Register 4 Select 2 The UserLocal register is a read write register that is not interpreted by the hardware and conditionally readable via the RDHWR instruction Figure 5 1 shows the format of the UserLocal register Table 5 3 describes the UserLocal register fields Figure 5 1 UserLocal
413. tore GPRs and software state eret Dismiss the interrupt 4 3 1 2 Vectored Interrupt VI Mode In Vectored Interrupt VI mode a priority encoder prioritizes pending interrupts and generates a vector which can be used to direct each interrupt to a dedicated handler routine This mode also allows each interrupt to be mapped to a GPR shadow register set for use by the interrupt handler VI mode is in effect when all the following conditions are true s Config3 vint 1 s Contig3 veic 0 IntCtlys 0 e Causey z l s Statusggy 0 In VI interrupt mode the eight hardware interrupts are interpreted as individual hardware interrupt requests The timer interrupt is combined in a system dependent way external to the core with the hardware interrupts the inter rupt with which they are combined is indicated by the PTI field in ntCtI to provide the appropriate relative priority of the timer interrupt with that of the hardware interrupts The processor interrupt logic ANDs each of the Cause p bits with the corresponding S atus bits If any of these values is 1 and if interrupts are enabled Status 1 68 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 3 Interrupts Statusgy 0 and Statusgg 0 an interrupt is signaled and a priority encoder scans the values in the order shown in Table 4 3 Table 4 3 Relative Interrupt Priority for
414. truction MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 31 26 25 21 20 16 15 0 SC 111000 base rt offset 6 5 5 16 Format SC rt offset base MIPS32 Purpose Store Conditional Word To store a word to memory to complete an atomic read modify write Description if atomic update then memory GPR base offset GPR rt GPR rt lt 1 else GPR rt lt 0 The LL and SC instructions provide primitives to implement atomic read modify write RMW operations for syn chronizable memory locations The 32 bit word in GPR rt is conditionally stored in memory at the location specified by the aligned effective address The 16 bit signed offset is added to the contents of GPR base to form an effective address The SC completes the RMW sequence begun by the preceding LL instruction executed on the processor To complete the RMW sequence atomically the following occur e The 32 bit word of GPR rt is stored into memory at the location specified by the aligned effective address e Al indicating success is written into GPR rt Otherwise memory is not modified and a 0 indicating failure is written into GPR rt On the M14K core the SRAM interface supports a lock protocol and the success or failure can be indicated by external hardware If the following event occurs between the execution of LL and SC the SC fails e An ERET
415. truction 1st Instruction 2nd Instruction Clocks 16 bit MULT MULTU MADD MADDU 1 MADD MADDU MSUB MSUBU or MSUB MSUBU MFHI MFLO 32 bit MULT MULTU MADD MADDU 2 MADD MADDU or MSUB MSUBU or MSUB MSUBU MFHI MFLO 16 bit MUL Integer operation 2B 32 bit MUL Integer operation 283 8 bit DIVU MFHI MFLO 9 16 bit DIVU MFHI MFLO 17 24 bit DIVU MFHI MFLO 25 32 bit DIVU MFHI MFLO 33 8 bit DIV MFHI MFLO 10 41 16 bit DIV MFHI MFLO 18 4 24 bit DIV MFHI MFLO 26 41 32 bit DIV MFHI MFLO 34 4 any MFHI MFLO Integer operation 2 any MTHI MTLO MADD MADDU or 1 MSUB MSUBU 1 For multiply operations this is the rt operand For divide operations this is the rs operand 2 Integer Operation refers to any integer instruction that uses the result of a previous MDU operation 3 This does not include the 1 or 2 IU pipeline stalls 16 bit or 32 bit that the MUL operation causes irre spective of the following instruction These stalls do not add to the latency of 2 4 If both operands are positive then the Sign Adjust stage is bypassed Latency is then the same as for DIVU In Table 2 1 a latency of one means that the first and second instructions can be issued back to back in the code without the MDU causing any stalls in the IU pipeline A latency of two means that if issued back to back the IU pipeline will be stalled for one cycle MUL operations are special because the MDU needs to stall the IU pipeline in order to ma
416. truction NCC 1 and for microMIPS instruction NCC 0 e 110 Filtered Data Message The output format during this trace mode is 0 3 b011 3 BreakpointID Load Store 1 Load 0 Store FullWord 1 32b data 0 lt 32b 4 5 Addr 7 2 6 15 32b data value OR 46 15 BE 3 0 4 b0 24b data value OR 46 15 BE 3 0 12 b0 16b data value OR 2 6 7 8 1 4 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 215 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core 46 15 BE 3 0 20 b0 8b data value 56 47 DeltaCycle if enabled e 1110 Function Call Return Exception Tracing The output format during this trace mode is 3 0 4 b0111 48 39 Delta Cycle if enabled Note that for a MIPS32 or MIPS64 instruction NCC 1 and for microMIPS instruction NCC 0 FC 1 implies a function call Ex 1 implies the start of an exception handler and R 1 implies a function or exception return e 1111 Overflow message The format of this type of message is 3 0 2 4 b1111 8 8 3 ITCB Overview The IFlowTrace Control Block ITCB is responsible for accepting trace signals from the CPU core formatting them and storing them into an on chip FIFO The figure also shows the Probe Interface Block PIB which reads the FIFO and outputs the memory contents through a narrow off chip trace port Figure 8 30 Trace Logic Ove
417. ual Address Generates Physical Address Attribute OxFF20 0000 dmseg maps to addresses Uncached through 0x0 0000 OxF_FFFF in EJTAG OxFF2F FFFF probe memory space OxFF30 0000 through OxFF3F FFFF drseg maps to the breakpoint reg isters OxO 0000 OxF_FFFF 3 2 4 1 Conditions and Behavior for Access to drseg EJTAG Registers The behavior of CPU access to the drseg address range at OxXFF30 0000 to OXFF3F FFFF is determined as shown in Table 3 4 Table 3 4 CPU Access to drseg Address Range LSNM Bit in Debug Transaction Register Access Load Store 1 Kernel mode address space kseg3 Fetch Don t care drseg see comments below Load Store 0 Debug software is expected to read the Debug Control Register DCR to determine which other memory mapped registers exist in drseg The value returned in response to a read of any unimplemented memory mapped register is 58 MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 3 3 Fixed Mapping MMU unpredictable and writes are ignored to any unimplemented register in the drseg Refer to Chapter 8 EJTAG Debug Support in the M14K Core on page 159 for more information on the DCR The allowed access size is limited for the drseg Only word size transactions are allowed Operation of the processor is undefined for other transaction sizes 3 2 4 2 Conditions and
418. uating instruction The processor contin ues to sample the PC value even when it is in Debug mode Note that some of the smaller sample periods can be shorter than the time needed to read out the sampled value That is it might take 41 TCK clock ticks to read a MIPS32 sample while the smallest sample period is 32 processor clocks While the sample is being read out multiple samples may be taken and discarded needlessly wasting power To reduce unnecessary overhead the TAP register includes only those fields that are enabled If both PC Sampling and Data Sampling are enabled then both samples are included in the PCSample scan register PC Sample is in the least significant bits followed by a Data Address Sample If either PC Sampling or Data Address Sampling is dis abled then the TAP register does not include that sample The total scan length is 49 2 82 bits if all fields are present and enabled MIPS32 M14K Processor Core Software User s Manual Revision 02 03 223 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M14K Core 8 9 1 PC Sampling in Wait State Note that the processor samples PC even when it is asleep that is in a WAIT state This permits an analysis of the amount of time spent by a processor in WAIT state which may be used for example to revert to a low power mode during the non execution phase of a real time application But counting cycles to update the PC sample va
419. uc tions that provides a significant reduction in code size while maintaining performance equivalent to MIPS32 The M14K is a successor to the M4K designed from the same microarchitecture including the Microcontroller Appli cation Specific Extension MCU ASE enhanced interrupt handling lower interrupt latency a memory protection unit a reference design of an optimized interface for flash memory and native AMBA 3 AHB Lite Bus Interface Unit BIU and additional power saving security debug and profiling features The M14K core is cacheless in lieu of caches it includes a simple interface to SRAM style devices This interface may be configured for independent instruction and data devices or combined into a unified interface The SRAM interface allows deterministic latency to memory while still maintaining high performance The MMU consists of a simple Fixed Mapping Translation FMT mechanism for applications that do not require the full capabilities of a Translation Lookaside Buffer TLB based MMU available on other MIPS cores The core includes one of two different Multiply Divide Unit MDU implementations selectable at build time allow ing the user to trade off performance and area for integer multiply and divide operations The high performance MDU option implements single cycle multiply and multiply accumulate MAC instructions which enable DSP algorithms to be performed efficiently It allows 32 bit x 16 bit MAC instru
420. ue ADDIUSP 9 258 3 2 257 lt lt 2 ADDIUR2 2 3 rs1 2 7 16 17 rd 2 7 16 17 1 1 4 8 12 16 20 24 ADDIURISP 1 6 rd 2 7 16 17 0 63 lt lt 2 ADDUI6 3 0 rs1 2 7 16 17 rs2 2 7 16 17 rd 2 7 16 17 ANDI6 2 0 rs1 2 7 16 17 rd 2 7 16 17 ANDII6 2 4 rs1 2 7 16 17 rd 2 7 16 17 1 2 3 4 7 8 15 16 31 32 63 64 128 255 32768 65535 B16 0 10 512 511 lt lt 1 BREAKI6 4 0 15 JALRS16 Soil 1 e p seii JRADDIUSP 0 31 2 LBUI16 rb 2 7 16 17 al 2 7 16 17 1 0 14 LW16 2 4 rb 2 7 16 17 rd 2 7 16 17 0 15 lt lt 2 LWM16 2bit list 1 ee 0 15 lt lt 2 LWGP 7 rd 2 7 16 17 64 63 lt lt 2 LWSP rd 5 bit field 0 31 lt lt 2 MFLO16 5bit 1 rd 5 bit field ORI6 2 rs1 2 7 16 17 rd 2 7 16 17 SB16 HE rb 2 7 16 17 0 15 SH16 2 rb 2 7 16 17 rs1 0 2 7 17 0 15 lt lt 1 SLL16 2 rs1 2 7 16 17 rd 2 7 16 17 1 8 see encoding tables MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 11 3 microMIPS Re encoded Instructions Table 11 3 Instruction Specific Register Specifiers and Immediate Field Values Continued Number of Immediate Register 1 Register 2 Register 3 Register Field Size Decoded Decoded Decoded Immediate Field Decoded Instruction Fields Value Value Value Value SRLI6 rs1 2 7 16 17 rd 2 7 16 17 1 8 see encoding tables SUBUI6 0 rs1 2 7 16 17 rs2 2 7 16 17 rd 2 7 16
421. un Ex ku Ro kA EXEE eH RSEN S 145 Figure 5 36 Performance Counter Count Register cccscceceeceeeeneeeeeeeeeeesaeeeseeeeecaaeeseeaeeeceaeesesaaeeseeeesesaeessnees 149 Figure 5 37 EHI Register FOAL scere tbrsuiec ctus dass ades budrete E 150 Figute 5 38 CachieErr Register Primary Caches messis testet e ie dicen te neta Ee t eben d Maec Ea 150 Igureb 39 Errore PG Register FO MMAL s rase a pest E EET ate xU A telo ine Cedo petas cete TES ea 152 Figure 5 40 DeSave Register FORTI sore Feria tinum a rnit x trei aka pner ua revise ka te per uta dei awe Sek 152 Figure a1 DOR Register Formal occa oisi ten Eras in e Det aita uade a Eua du E 160 Figure 8 2 IBS teli Medi M EE 170 Figure e 3 BAM Beglister FONTIm d suse o becpesox vendesi beo euktu tee c ask Pt O eo eeR eso eR LESE bu teque cu an Riedel ns 171 Figure 8 4 BMn Register FFOLTTal uua india ries daret tiat tti edes da restent ip e ure t pede ta c ed eR rares 171 Figure 8 5 IBASIDN Register Format roii oe paran rode desi xim tede Etudes iuc a nde atn aue Ete uec i rtsazs ERN I RES drETE 172 Figure 8 6 IBG Register FORTI 2 2 3 2 2 2 ut tci seta d rhet Lon istoc De usati oet tese E rra dN I 172 Figure 8 7 IBC Gi Register EET 0 00 0L S05 L 5m 174 Figure 8 8 IBPOn REJSE FON AL o cec dece th o Feria tup mocethca naai Diae aaa 175 Figure 8 9 DBS Register Format uico ost erit besito ize qe em dcin te Mida api D Ent E 176 Figure 8 10 DBAn Register Format 2er iecit ENEA
422. undary PC is updated before the condition is detected Therefore both EPC and BadVAddr point to the unaligned instruction address In the case of a data access the exception is taken if either an unaligned address or an address that was inaccessible in the current proces sor mode was referenced by a load or store instruction Cause Register ExcCode Value ADEL Reference was a load or an instruction fetch ADES Reference was a store Additional State Saved Table 4 11 CPO Register States on an Address Exception Error Register State BadVAddr failing address Entry Vector Used General exception vector offset 0x180 4 8 8 SRAM Parity Error Exception A SRAM error exception occurs when an instruction or data reference detects a data error This exception is not maskable To avoid disturbing the error in the cache array the exception vector is to an unmapped uncached address This exception is precise Cause Register ExcCode Value N A Additional State Saved Table 4 12 CPO Register States on a SRAM Parity Error Exception Register State Value CacheErr Error state ErrorEPC Restart PC Entry Vector Used Cache error vector offset 1652100 4 8 9 Bus Error Exception Instruction Fetch or Data Access A bus error exception occurs when an instruction or data access makes a bus request and that request terminates in an error The bus error exception can occur on either an instruction fetch or a data
423. upt handlers Bit field manipulation instructions microMIPS Compatible Instruction Set microMIPS ISA is a build time configurable and run time convertible ISA to improve code size density over MIPS32 while maintaining MIPS32 performance Combining both 16 bit and 32 bit opcodes microMIPS supports all MIPS32 instructions except branch likely instructions with new optimized encoding Frequently used MIPS32 instructions are available as 16 bit instructions Added fifteen new 32 bit instructions and thirty nine 16 bit instructions corresponding to commonly used MIPS32 instructions Stack pointer implicit in instruction MIPS32 assembly and ABI compatible Supports ASEs and User defined Instructions UDIs MCU ASE Increases the number of interrupt hardware inputs from 6 to 8 for Vectored Interrupt VI mode and from 63 to 255 for External Interrupt Controller EIC mode Separate priority and vector generation 16 bit vector address is provided Hardware assist combined with the use of Shadow Register Sets to reduce interrupt latency during the pro logue and epilogue of an interrupt MIPS32 M14K Processor Core Software User s Manual Revision 02 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 1 1 Features e An interrupt return with automated interrupt epilogue handling instruction IRET improves interrupt latency e Supports optional interrupt chaining e Two memory to memory atomic rea
424. whether it was a load or store the size of the request low order address bits and the data value This mode can only be used when normal tracing mode is turned off This mode can not be used in conjunction with other special trace modes This mode can be enabled or disabled via the FDT bit in the Control Status register see Section 8 8 6 ITCB Register Interface for Software Configurability The corresponding data breakpoint must have the TE bit set to enable the match condition Software should avoid setting up overlapping data breakpoints The behavior when multiple matches on one load or store are detected is to report a BreakpointID of 7 Extended Filtered Data Tracing Mode Extends Filtered Data Tracing Mode by adding the virtual address of the load store instruction to the generated trace information see Section Filtered Data Tracing Mode above This behavior is enabled disabled by the FDT CAUSE field in the FCTL Control Status register see Section 8 8 6 ITCB Register Interface for Software Configurability FDT CAUSE only has effect if the FDT field is also set The extended trace sequence is a FDT trace message followed by the Breakpoint Match BM trace message If the IFCTLcyc field is set the FDTtrace message will have a DeltaCycle Message value of 0 directly followed by the Breakpoint Match message This message sequence FDT delta cycle of 0 and BM indicates to the trace disassem bler that Extended Fil
425. wo instructions are allowed to execute since the jump branch and the instruction in the delay slot are executed as one step Debug single step exceptions are enabled by the SSt bit in the Debug regis ter and are always disabled for the first one two instructions after a DERET The DEPC register points to the instruction on which the debug single step exception occurred which is also the next instruction to single step or execute when returning from debug mode So the DEPC will not point to the instruction which has just been single stepped but rather the following instruction The DBD bit in the Debug register is never set for a debug single step exception since the jump branch and the instruction in the delay slot is executed in one step Exceptions occurring on the instruction s executed with debug single step exception enabled are taken even though debug single step was enabled For a normal exception other than reset a debug single step exception is then taken on the first instruction in the normal exception handler Debug exceptions are unaffected by single step mode e g returning to a SDBBP instruction with debug single step exceptions enabled causes a debug software breakpoint exception and DEPC points to the SDBBP instruction However returning to an instruction not jump branch just before the SDBBP instruction causes a debug single step exception with the DEPC pointing to the SDBBP instruc tion To ensure proper functionality of
426. xFF1F FFFF OxEOO00 0000 OxDFFF FFFF kseg2 0xC000 0000 ong ksegl Ox9FFF FFFF kseg0 0x8000 0000 Ox7FFF FFFF useg kuseg 0x0000 0000 Each of the segments shown in Figure 3 2 are either mapped or unmapped The following two sub sections explain the distinction Then sections 3 2 2 User Mode 3 2 3 Kernel Mode and 3 2 4 Debug Mode specify which segments are actually mapped and unmapped 3 2 1 1 Unmapped Segments An unmapped segment does not use the FM to translate from virtual to physical addresses Unmapped segments have a fixed simple translation from virtual to physical address This is much like the transla tions the FM provides for the M14K core but we will still make the distinction All segments are treated as uncached within the M14K core Cache coherency attributes of cached or uncached can be specified and this information will be sent with the request to allow the system to make a distinction between the two MIPS32 M14K Processor Core Software User s Manual Revision 02 03 53 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Memory Management of the M14K Core 3 2 1 2 Mapped Segments A mapped segment does use the FM to translate from virtual to physical addresses For the M14K core the mapped segments have a fixed translation from virtual to physical address The cacheability of the segment is defined in the CPO Config regist
427. xception Address error AdEL or AdES The BadVAdar register does not capture address information for bus errors because they are not addressing errors Figure 5 3 BadVAddr Register Format 31 0 BadVAddr Table 5 5 BadVAddr Register Field Description Description Read Write Reset State Bad virtual address Undefined 5 2 4 Count Register CPO Register 9 Select 0 The Count register acts as a timer incrementing at a constant rate whether or not an instruction is executed retired or any forward progress is made through the pipeline The counter increments every other clock if the DC bit in the Cause register is 0 The Count register can be written for functional or diagnostic purposes including at reset or to synchronize proces sors By writing the CountDM bit in the Debug register it is possible to control whether the Count register continues incre menting while the processor is in debug mode Figure 5 4 Count Register Format 31 0 Count Table 5 6 Count Register Field Description Fields Name Bits Description Read Write Reset State Count 31 0 Interval counter R W Undefined MIPS32 M14K Processor Core Software User s Manual Revision 02 03 99 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPO Registers of the M14K Core 100 5 2 5 Compare Register CPO Register 11 Select 0 The Compare register acts in conjunction with the Count register to impl
428. ycle One Cycle One Cycle One Cycle One Cycle J ump or Branch Lr om Delay Slot Instruction Jump Target Instruction l E M A One Clock Branch Delay 2 6 Data Bypassing Most MIPS32 instructions use one or two register values as source operands These operands are fetched from the register file in the first part of E stage The ALU straddles the E to M boundary and can present the result early in the M stage However the result is not written to the register file before the W stage If no precautions were taken it would take 3 cycles before the result was available for the following instructions To avoid this data bypassing is implemented Between the register file and the ALU a data bypass multiplexer is placed on both operands see figure below This enables the M14K core to forward data from a preceding instruction whose target is a source register of a following instruction An M to E bypass and an A to E bypass feed the bypass multiplexers A W to E bypass is not needed as the register file is capable of making an internal bypass of Rd write data directly to the Rs and Rt read ports Figure 2 14 IU Pipeline Data Bypass stage E stage M stage A stage W stage AtoE bypass 4 i M to E bypass Rs Addr Instruction Rs Read RtAddr Reg File Rd Write RtRead Bypass Load data HI LO Data or multiplexers CPO data 42 MIPS32 M14K Processor Core Software User s Manual R

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MIPS32® M14K™ Processor Core Software User`s Manual