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PC-TIO-10 User Manual - National Instruments

1. x Mode N shown Figure 15n provides software triggered strobe with level gating that is also hardware retriggerabie The counter must be issued an ARM command before counting can occur Once armed the counter will count ali source edges which occur while the gate is active and disregard those source edges which occur while the Gate is inactive This permits the Gate to tum the count process on and off After the issuance of the ARM command and the application of an active Gate the counter will count to TC Upon reaching TC the counter will reload from the Load ing Count ng will resume upon the issuance of a new ARM command All active going Gate edges issued to an armed counter will cause a retrigger operation Upon application of the Gate edge the counter contents will be saved in the Hold register On the first qualified source edge after application of the retriggering gate edge the contents of the Load register will be transferred into the counter Counting will resume on the second qualified source edge after the retriggering Gate edge Qualified source edges are active going edges which occur while the Gate is active AMD Am9513A Data Sheet Am9513A 2 135 National Instruments Corporation C 21 PC TIO 10 User Manual Appendix C AMD Am9513A Data Sheet aare VA XXX AAA WF004700 Figure 151 Mode L Waveforms NININININININININININININININA 7 NEW
2. Board DMA Channel Interrupt Level Base I O Address AT AO 6 10 Channel 5 Lines 11 12 1C0 hex AT DIO 32F Channels 5 6 Lines 11 12 240 hex AT GPIB Channel 5 Line 11 2C0 hex AT MIO 16 Channels 6 7 Line 10 220 hex AT MIO 16D Channels 6 7 Lines 5 10 220 hex AT MIO 16F 5 Channels 6 7 Line 10 220 hex AT MIO 16X None None 220 hex GPIB PCII Channel 1 Line 7 2B8 hex GPIB PCIIA Channel 1 Line 7 2 1 hex GPIB PCIII Channel 1 Line 7 280 hex National Instruments Corporation 2 3 PC TIO 10 User Manual Chapter 2 Configuration and Installation Table 2 2 Default Settings of National Instruments Products for the PC Continued Board DMA Channel Interrupt Level Base I O Address Lab PC 1200 Channel 3 Line 5 260 hex PC DIO 24 None Line 5 210 hex PC DIO 96 None Line 5 180 hex PC LPM 16 None Line 5 260 hex PC TIO 10 None Line 5 1A0 hex These settings are software configurable and are disabled at startup time Interrupt Level Selection PC TIO 10 User Manual There are two sets of jumpers for interrupt selection on the PC TIO 10 board W1 is used for selecting the interrupt level while W2 is used for local selection of two of the counter outputs as interrupt sources The locations of these jumpers are shown in Figure 2 1 The PC TIO 10 board can connect to any one of six interrupt lines of the PC I O Channel IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 or IRQ9 You select the interrupt li
3. D 29 1e INTERRUPT OUTPUTS iRQA A NM CO sO V LDLTTICTOLTT MM E 2 uu el E DATA BUS 00 07 ir ee volgen ssf vss 08 amea aaar a i MERE CN RN Output Low Voltage 1 1 6 mA NEUEN GS LC ESL MUR Capacitance Win 0 TA 289C 210 MHz in 12095 Ee rN EMEN EENENI MOTOROLA MICROPROCESSOR DATA 3 1693 PC TIO 10 User Manual D 3 National Instruments Corporation National Instruments Corporation MC6821 DC ELECTRICAL CHARACTERISTICS Continued Appendix D Motorola MC6821Data Sheet PERIPHERAL BUS 7 7 CA1 CA2 1 2 Input Leakage Current R W RESET RSO RS1 CSO CS1 CS2 1 25 m Vin 010 5 25 V CBi Enabe i Hi Z Input Leakage Current Vin 0 4 to 2 4 V PBo PB7 c82 nz 20 10 pA Input High Current Vip 2 4 PAO PA7 CA2 20 40 pA Darlington Drive Current Vo 1 5 V PBO PB7 CB2 oH 10 10 mA input Low Current 0 4 V PAO PA7 2 24 mA Output High Voltage Load 200 PAO PA7 PBO PB7 CA2 CB2 Vss 24 v ULoad 10 PAO PA7 CA2 Vcc 10 Output Low Voltage l 3 2 VoL Vss 0 V Capacitance Vin 20 TA 25 C f 1 0 MHz Cin 10 pF POWER REQUIREMENT
4. COMMAND WF004710 Figure 15n Mode N Waveforms MODE O modulate counting The counter must be armed before appli cation of the triggering Gate edge Gate edges applied to a Software Triggered Strobe with Edge Gating disarmed counter are disregarded Irrespective of the Gate and Hardware Retriggering level the counter will count all source edges after the triggering Gate edge until the first TC On the first TC the 15 14 CM13 CM12 11 cm10 cms counter will be reloaded from the Load register and disarmed mee oe x x 7 A ia order maw courting in that order to initiate a new counting Unlike Modes F and L which disregard the Gate input once counting starts owe ows cma owe in Mode the count process wil be retriggered on active Lipeg e x ee eee Oo Gai odes the Coulter the counter On each retriggering Gate edge the counter contents will be transferred into the Hold register On the first Mode shown in Figure 150 is similar Mode except that source edge after the retriggering Gate edge the Load counting will not begin until an active going Gate edge is register contents will be transferred into the counter Counting applied to an armed counter and the Gate level is not used to will resume on the second source edge after a retrigger 2 136 Am9
5. 2 140 PC TIO 10 User Manual Figure 15x Mode X Waveforms After power on reset or a Master Reset command the Counter Mode registers are initialized to a preset condition The value entered OBOO hex and results in the following control configuration Output low impedance to ground Count down Count binary Count once Load register selected No retriggering F1 input source selected Positive true input polarity No gating Output Control Counter mode bits CMO through CM2 specify the output control configuration Figure 17 shows a schematic represen tation of the output control logic The OUT pin may be off a high impedance state or it may be inactive with a low impedance to ground The three remaining valid combinations represent the active high active low or TC Toggle output waveforms One output form available is called Terminal Count TC and represents the period in time that the counter reaches an equivalent value of zero TC will occur on the next count when the counter is at 0001 for down counting at 9999 BCD for BCD up counting or at FFFF hex for binary up counting Figure 18 shows a Terminal Count pulse and an exampie context that generated it The TC width is determined by the period of the counting source Regardless of any gating input or whether the counter is Armed or Disarmed the terminal count will go active for only one clock cycle Figure 18 assumes active high source polarity counter armed
6. National Instruments Corporation Motorola MC6821Data Sheet This appendix contains the manufacturer data sheet for the Motorola MC6821 integrated circuit Motorola Inc This circuit is used on the PC TIO 10 board Copyright Motorola Inc 1988 Reprinted with permission of copyright owner All rights reserved Motorola Inc Q3 1988 Data Book Microprocessor Microcontroller and Peripheral Data Volume II National Instruments Corporation D 1 PC TIO 10 User Manual Appendix D Motorola MC6821Data Sheet MOTOROLA SEMICONDUCTOR E MC6821 Peripheral Interface Adapter PIA The MC6821 Peripheral Interface Adapter provides the universal means of interfacing peripheral equipment to the M6800 Family of microprocessors This device is capable of interfacing the MPU to peripherals through two 8 bit bidirectional peripheral data buses and four control lines No exter nal logic is required for interfacing to most peripheral devices The functional configuration of the PIA is programmed by the MPU during system initialization Each of the peripheral data lines can be programmed to act as an input or output and each of the four control interrupt lines may be programmed for one of several control modes This allows a high degree of flexibility in the overall operation of the interface 8 Bit Bidirectional Data Bus for Communication with the MPU Two Bidirectional 8 Bit Buses for interface to Peripherals Two Programmabl
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8. 001 lt N lt 101 Description The initial output level for TC Toggle mode is Cleared LOW for counter N selected by N4 N2 N1 001 Counter 1 thru 101 Counter 5 respectively This command conditions the TC Toggle flip flop see Figure 17 but does not appear at the counter output unless TC Toggle mode CM2 CM1 CMO 010 is selected Step Counter Coding C7 C8 CS C4 C3 C2 Ci 001 amp N lt 101 Description Counter N is incremented or decremented by one depending on its operating configuration if the Counter Mode register associated with the selected counter has its CM3 bit cleared to zero this command will cause the counter to decrement by one if CM3 is set to a logic high this command will increment the counter by one The STEP command wiit take effect even on a disarmed counter Load Data Pointer Register Coding C7 C8 C5 C4 C2 C1 G4 G2 G1 000 110 Description Bits in the E and G fields will be transferred into the corresponding Element and Group fields of the Data Pointer register as shown in Figure 7 The Byte Pointer bit in the Data Pointer register is set Transfers into the Data Pointer only occur for G field values of 001 010 011 100 101 and 111 Values of 000 and 110 for G should not be used See the Setting the Data Pointer Register section of this document for additional details Disable Data Pointer Sequencing Coding C7 C6 C5 C4 C3 C2 C1 CO 1 17 1 0 0 0
9. Write Low to Write High Write Pulse Duration Note 12 21 150 ms Gate Valid to Count Source High Special Gate Notes 10 13 17 22 TEHGV2 Count Source High to Gate Valid Special Gate Notes 10 13 18 2 eo vs Notes E Enabled counter source input SRC1 SRC5 1 Abbreviations used for the switching parameter symbols are F AUI GATES F1 F amp TCN 1 given as the letter T followed by four or five characters The i 2 first third ch t t the si n on 5 Dem T GATES TCN 1 which the measurements start and end Signal abbrevia R Read AD eed are S Chip Select CS A Address C D W Write WA C Clock X2 Y Output OUT1 OUTS D Data In 080 0815 Am9513A 2 149 National Instruments Corporation 35 PC TIO 10 User Manual Appendix C AMD Am9513A Data Sheet SWITCHING CHARACTERISTICS over MILITARY operating range for SMD DESC and APL Products Group A Subgroups 9 10 11 are tested unless otherwise noted Am9513A Parameter Symbol Description Min Max Unit TAVAL Valid to Read Low 25 TAVWH C D valid to Write High TCHCH X2 High to X2 High X2 Period Note 13 145 TCHCL X2 High to X2 Low X2 High Pulse Width Note 13 70 ns TCLCH X2 Low to X2 High X2 Low Pulse Width Note 13 70 ns TOVWH Data In Valid to Write High 80 ns Count Source High to Count
10. Set interrupt vector save the current vector before writing out new one mov cmp ja add jmp slave add mov setvec push mov int pop mov mov cmp jne cmp je ii 0 mov mov mov push mov mov handler mov int pop National Instruments Corporation ax bp 6 get interrupt level al 7 check to see if it belongs to master short slave or slave interrupt chip al 008h offset for master vector list short setvec go set the vector al 068h offset for slave vector list Slave ack 1 flag for slave channel ax Save vector number for later ah 35h get current vector 21h get previous int addr in es bx ax restore vector number cx cs prep to compare current new vectors dx es dx cx See if vector is already there short ii 0 bx offset handler short ii exit vector already installed exit vect num al save vector number for remove isr word ptr int addr 0 bx Save the address word ptr int addr 2 es ds Save the data segment ds cx copy cx cs into ds dx offset isr handler ds dx points to new ah 25h 21h install the handler in the system ds 4 17 PC TIO 10 User Manual Chapter 4 Programming mask interrupt level in the interrupt controller register and store the original setting of the mask bit for the selected interrupt level level level mov mov shl mov not in jmp and and out jmp in jmp and and out mov cx bp 6 bx 1
11. N4 Na Clear Toggle out LOW for counter N 001 lt N lt 101 N2 Step counter N 001 lt N lt 101 s 3 9 9 9 sabie Data Pointer Segurara Sd e 3 3 3 9 Pr Se nter 188 bus model 1 3 3 9 0 0 Ges Enable Pointer Sequencngi 1 3 2 fe oft on FOUN T 3 3 9 9 fs 1 Gear MM Enter 88 bus model 1 1 o o i o alo e 3 3 2 Too To Ense for Wie operations ABSIT om TTT Toa J Ssane Preteteh for Wie ogeraens amostra eae ES Not to be used for asynchronous operations Figure 19 Am9513A Command Summary determines which reload source to use on the upcoming TC Following each ARM or LOAD AND ARM command a counter in one of these modes will reload from the Hold register on the first TC and alternate reload sources thereafter reload from the Load register on the second TC the Hold register on the third etc Load Counters Coding Description Any combination of counters as specified in the S field wili be loaded with previously entered values The source of information for each counter will be either the associated Load register or the associated Hold register as determined by the operating configuration in the Mode register The Load Unused except when XXX 111 001 or 000 Figure 20 Am9513A Unused Command Codes Arm Counters
12. Po xi xt x Mode H shown in Figure 15h is identical to Mode G except that the Gate input is used to qualify which source edges are to be counted The counter must be armed for counting to occur Once armed the counter will count ail source edges that occur while the Gate is active This permits the Gate to tum the count process on and off As with Mode G the counter will be reloaded from the Hold register on the first TC and reloaded from the Load register and disarmed on the second TC This mode allows the Gate to contro the extension of both the initial output delay time and the pulse width OUTPUT TC TOGGLED OUTPUT e e NAASIS UVUA emer WF004650 Figure 15g Mode G Waveforms MODE Hardware Triggered Delayed Pulse Strobe eg x Px x x x Dots txt xt xi xt x Mode shown in Figure 15i is identical to Mode G except that counting will not begin until a Gate edge is applied to an armed counter The counter must be armed before application of the triggering Gate edge Gate edges applied to a disarmed counter are disregarded An armed counter will start counting on the first source edge after the triggering Gate edge Counting will then proceed in the same manner as in Mode G After the second TC the counter will disarm itself An ARM command and Gate edge must be issued in this order to restart counting Note that after application of a triggering Gate edge
13. ns Gate Valid to Write High Notes 3 10 tt 199 ns _TRHAX Read High to C D Dont Care 2 9 s Read High to Count Source High Notes 4 7 gt 9 s Read High to Data Out Invalid tt 1 ws TRMOZ Read High to Data Out at High impedance Data Bus Release Time 7 21 TRHRL Read High to Read Low Read Recovery Time a 100 ns Read High to CS High 28 9 TRHWL Read High to Write Low Read Recovery Time o 21 T3300 TRLOV Read Low to Data Out Vaid a ns TRLOX Read Low to Data Bus Orien Data Bus Drive Time 20 ns TRLRH Read Low to Read High Read Duration Note 12 o amp o Ta T CS tow to Read Low Note 12 Tan 29 21 170 TWHAX Write High to C O Don t Care 2 TWHOX Write High to Data In Dort Care 29 e ee ee Eh Nee ELT M TWHGV Write High to Gate Vaid Notes 5 10 14 475 _TWHAL write High to Read Low Write Recovery Time Note 1 Tat poj TWHSH Write High to CS High Note ig 29 U U 8 2 s TWHWL Write High to Write Low Write Recovery Time Note 16 2t m TWHvv Write High to Out Valid Notes amp 14 o eso m _TWLWH
14. each of which has programmable edge polarity and individual enable clear and disable commands A second set of jumpers W2 locally connects two of the counter outputs to the interrupt circuitry With these connections external wrap backs are unnecessary if you want to use a counter to generate timed interrupts Refer to Chapter 4 Programming or to Appendix D Motorola MC6821Data Sheet for more detailed information on controlling interrupts Refer to Chapter 2 Configuration and Installation for more information on configuring the jumper settings Timing and Digital 1 0 Connector All timing and digital I O is transmitted through a standard 50 pin male connector Pin 34 is connected to 5 V through a protection fuse F1 This 5 V supply is often required to operate I O module mounting racks Pin 33 is connected to ground See Chapter 2 Configuration and Installation for additional information National Instruments Corporation 3 3 PC TIO 10 User Manual Programming This chapter describes in detail the address and function of each of the PC TIO 10 control and status registers This chapter also includes important information about programming the PC TIO 10 The PC TIO 10 is a timing and digital I O board designed around two Am9513A integrated circuits and one MC6821 integrated circuit The Am9513A is a general purpose counter timer with five 16 bit individually controlled counters and a 4 bit frequency scaler outp
15. 1 MHz Ta 25 C Pins not under test at 0 V Temperature Supply Voltage Vcc Operating ranges define those limits between which the functionality of the device is guaranteed Test Conditions Min Al inputs Except X2 V i En an a pusswem o pe Dema we 0 2 Input Load Current Except X2 VSS lt VIN lt VCC Guaranteed by design SWITCHING TEST INPUT OUTPUT WAVEFORMS Appendix C AMD Am9513A Data Sheet ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Commercial C Devices Storage Temperature 65 C to 150 Temperature Ta 0 to 70 C 5 V 5 24 210 100 xt s 7 0 8 7 POINTS 08 0 45V x2 WFO04B10 q TC002000 Crystal is fundamental mode parallel resonant 32 pF load capacitance less than 100 2 ESR Co less than 100 pF Am9513A 2 147 National Instruments Corporation C 33 PC TIO 10 User Manual Appendix C AMD 9513 Data Sheet The second and fourth letters designate the reference states of the signais named in the first and third letters respectively using 3 following abbreviations H HIGH L LOW V VAUD X Unknown or Don t care Z High Impedance 2 Any input transition that occurs before this minimum setup requirement will be reflected in the contents read from the status register 3 Any input transition that occurs before this minimum setup requirement will act on the counter before the execu
16. Resolution can be expressed in bits in proportions or in percent of full scale For example a system has 12 bit resolution one part in 4 096 resolution and 0 0244 of full scale G 12 National Instruments Corporation resource locking RTD RTI RTSI bus S S sample counter SCADA scan scan clock scan rate sec National Instruments Corporation G 13 Glossary a technique whereby a device is signaled not to use its local memory while the memory is in use from the bus root mean square the square root of the average value of the square of the instantaneous signal amplitude a measure of signal amplitude resistance temperature detector a metallic probe that measures temperature based upon its coefficient of resistivity referred to input real time system integration bus the National Instruments timing bus that connects DAQ boards directly by means of connectors on top of the boards for precise synchronization of functions samples the clock that counts the output of the channel clock in other words the number of samples taken On boards with simultaneous sampling this counter counts the output of the scan clock and hence the number of scans supervisory control and data acquisition a common PC function in process control applications where programmable logic controllers PLCs perform control functions but are monitored and supervised by a PC one or more analog or digital input samp
17. counter decrementing and an external reload value of K The counter will always be loaded from an external location when TC occurs the user can choose the source location and the value if a non zero value is picked the counter will never reaily attain a zero state and TC will indicate the counter state that would have been zero had no paraite transfer occurred Am9513A C 26 National Instruments Corporation Appendix C AMD Am9513A Data Sheet COMPARATOR MC MN TC CONNECTION TO N 1 COUNTER Figure 17 Output Control Logic Am9513A National Instruments Corporation C 27 Count Control 0 Disable Special Gate 1 Enable Special Gate 0 Reload from Load 1 Reload from Load or Hold Except in Mode X Which Reloads Only from Load 0 Count Once 1 Count Repetitively 0 Binary Count 1 BCD Count 0 Count Down 1 Count Up Source Edge 0 Count on Rising Edge 1 Count on Falling Edge Gating Control Output 000 No Gating 000 Inactive Output Low 001 Active High TCN 1 001 Active High Terminal Count Pulse 010 Active High Level GATE Net 010 TC Toggied 011 Active High Level GATE N 1 011 100 Active High Level GATE N 100 Inactive Output High Impedance 101 Active Low Level GATE N 101 Active Low Terminal Count Pulse 110 Active High Edge GATE N 110 Megai 111 Active Low Edge GATE N 111 DF003784 Note See Figure 15 for restric
18. tion as specified by bit 1 CRB b7 must first be cleared by a read of data b3 1 Write Strobe with E Restore CB2 goes low on first low to high E transition following an MPU write into Output Register B returned b5 b4 b3 high by the next low to high E tran Tr T sition following an E pulse which Occurred while the part was de selected 11 Set Reset CA2 2 2 CB2 goes low as MPU writes b3 0 into Control Register CA2 CB2 goes high as MPU writes b3 1 into Control Register MOTOROLA MICROPROCESSOR DATA 3 1701 PC TIO 10 User Manual D 11 National Instruments Corporation ORDERING INFORMATION MC6821 Package Type Frequency MHz Temperature Order Number Cerdip 1 0 0 to 70 C S Suffix 1 0 40 C to 85 C 1 5 O C to 70 1 5 40 to 85 C 2 0 0 to 70 C Plastic 1 0 0 to 70 C P Suffix 1 0 40 C to 85 C 1 5 0 to 70 C 1 5 40 C to 85 C 2 0 0 to 70 PIN ASSIGNMENT Appendix D Motorola MC6821Data Sheet MC6821S MC6821CS MC68A21S MC68A21CS MC68B21S MC6821P MC6821CP MC68A21P MC68A21CP MC68B21P National Instruments Corporation MOTOROLA MICROPROCESSOR DATA 3 1702 PC TIO 10 User Manual Switch Settings Table E 1 lists the possible switch settings the corresponding base T O address and the base I O address space used for that setting Note I O address space hex 000 through hex OFF is not listed in T
19. transfer Hold register into counter on each TC that gate is HIGH On active gate edge transfer counter into Hold register and then reload counter from Load register On active gate edge transfer counter into Hold register but counting continues 2 Mode X is available tor Am9513A COUNTER MODE DESCRIPTIONS i 2 c Counter Mode register bits CM15 CM13 and CM7 CMS select the operating mode for each counter see Figure 14 To simplify references to a particular mode each mode is assigned a letter from A through X Representative waveforms for the counter modes are illustrated in Figures 15a through 15v Because the letter suffix in the figure number is keyed to the mode Figures 15m 15p 15t 15u and 15w do not exist The figures assume down counting on rising source edges Those modes which automatically disarm the counter oja o o o o 8 Ble gl Bl 8 8 a eveL EDGE Ree MERE GS EE EDD REN SEX Te ERE IRI pee ux po TS x x X Notes 1 Counter modes M T U and W are reserved and shouid not be used Figure 14 Counter Mode Operating Summary the ARM command is omitted The retriggering modes N O Q and R are shown with one retrigger operation Both a TC output waveform and a TC Toggled output waveform are shown for each mode The symbolis L and are used to represent count values equal to the
20. 0 1 1 1 0 1 1 108 108 IDF 0 1 1 1 1 0 0 1E0 1E0 1E7 0 1 1 1 1 0 1 1E8 1E8 1EF 0 1 1 1 1 1 0 1F0 1FO 1F7 0 1 1 1 1 1 1 1F8 1F8 1FF 1 0 0 0 0 0 0 200 200 207 1 0 0 0 0 0 1 208 208 20F 1 0 0 0 0 1 0 210 210 217 1 0 0 0 0 1 1 218 218 21F 1 0 0 0 1 0 0 220 220 227 1 0 0 0 1 0 1 228 228 22F 1 0 0 0 1 1 0 230 230 237 PC TIO 10 User Manual E 2 National Instruments Corporation Appendix E Switch Settings Table E 1 Switch Settings with Corresponding Base 1 0 Address and Base 1 0 Address Space Continued Switch Setting Base I O Base I O Address Space A9 A8 A7 A6 5 4 Address hex Used hex 1 0 0 0 1 1 1 238 238 23F 1 0 0 1 0 0 0 240 240 247 1 0 0 1 0 0 1 248 248 24F 1 0 0 1 0 1 0 250 250 257 1 0 0 1 0 1 1 258 258 25F 1 0 0 1 1 0 0 260 260 267 1 0 0 1 1 0 1 268 268 26F 1 0 0 1 1 1 0 270 270 277 1 0 0 1 1 1 1 278 278 27F 1 0 1 0 0 0 0 280 280 287 1 0 1 0 0 0 1 288 288 28F 1 0 1 0 0 1 0 290 290 297 1 0 1 0 0 1 1 298 298 29F 1 0 1 0 1 0 0 2A0 2A0 2A7 1 0 1 0 1 0 1 2A8 2A8 2AF 1 0 1 0 1 1 0 2B0 2B0 2B7 1 0 1 0 1 1 1 2B8 2B8 2BF 1 0 1 1 0 0 0 2 0 2C0 2C7 1 0 1 1 0 0 1 2C8 2C8 2CF 1 0 1 1 0 1 0 2D0 2D0 2D7 1 0 1 1 0 1 1 2D8 2D8 2DF 1 0 1 1 1 0 0 2E0 2E0 2E7 1 0 1 1 1 0 1 2E8 2E8 2EF 1 0 1 1 1 1 0 2F0 2F0 2F7 N
21. 1 3B8 3B8 3BF 1 1 1 1 0 0 0 3C7 1 1 1 1 0 0 1 3C8 3C8 3CF 1 1 1 1 0 1 0 3D0 3D0 3D7 1 1 1 1 0 1 1 3D8 3D8 3DF 1 1 1 1 1 0 0 3E0 3E0 3E7 1 1 1 1 1 0 1 3E8 3E8 3EF 1 1 1 1 1 1 0 3F0 3F0 3F7 1 1 1 1 1 1 1 3F8 3F8 3FF National Instruments Corporation E 5 PC TIO 10 User Manual Technical Support Resources This appendix describes the comprehensive resources available to you in the Technical Support section of the National Instruments Web site and provides technical support telephone numbers for you to use if you have trouble connecting to our Web site or if you do not have internet access NI Web Support To provide you with immediate answers and solutions 24 hours a day 365 days a year National Instruments maintains extensive online technical support resources They are available to you at no cost are updated daily and can be found in the Technical Support section of our Web site at www natinst com support Online Problem Solving and Diagnostic Resources e KnowledgeBase A searchable database containing thousands of frequently asked questions FAQs and their corresponding answers or solutions including special sections devoted to our newest products The database is updated daily in response to new customer experiences and feedback e Troubleshooting Wizards Step by step guides lead you through common problems and answer questions about our entire product line Wizards include screen shots tha
22. 13 081 DB1 14 D82 082 15 DB3 0B3 16 084 084 17 DB5 085 18 DB6 DB6 19 087 DB7 20 D88 GATE 1A 22 D89 GATE 2A 23 0810 GATE 3A 24 0811 GATE 4 25 0812 GATE 5A 26 DB13 27 0814 28 Figure 2 Data Bus Assignments Interface Considerations All of the input and output signals for the Am9513A are specified with logic levels compatible with those of standard TTL circuits In addition to providing TTL compatible voitage levels other output conditions are specified to heip configure non standard interface circuitry The logic level specifications take into account all worst case combinations of the three variables that affect the logic level thresholds ambient tem perature supply voitage and processing parameters A change in any of these toward nominal values will improve the actual operating margins and will increase noise immunity Unprotected open gate inputs of high quality MOS transistors exhibit very high resistances on the order of perhaps 10 4 ohms It is easy therefore in some circumstances for charge to enter the gate node of such an input faster than it can be discharged and consequently for the gate voitage to rise high enough to break down the oxides and destroy the transistor Appendix C Ail inputs to the Am9513A include protection networks to help prevent damaging accumulations of static charge The protec tion circuitry is designed to slow the transitions of incoming curr
23. 2 5 uA max Pulse width Am9513A source inputs 70 nsec min Pulse width Am9513A gate inputs 145 nsec min Pulse width MC6821 EXTIRQ I and 2 100 nsec min National Instruments Corporation A 1 PC TIO 10 User Manual Appendix A Specifications Output Signal Specifications atts V 1 0 hy Note The total current output from pin 34 may be limited by the available current from your computer s power supply To determine the available current subtract the maximum power consumption of the board from the maximum current per slot The difference if less than 1 A is the maximum current available to pin 34 If the difference is equal to or greater than 1 A the maximum current available is restricted by the limitations of the connector as shown previously Output logic high voltage all outputs at Iput 200 2 4 V min 5 0 V max Output logic low voltage all outputs at Iput 3 2 mA 0 0 V min 0 4 V max Darlington drive current MC6821 Port B at 1 5 1 0 mA min 10 0 mA max Operating Environment Temrperatute irre itte ren 0 to 70 C Relative humidity oes 596 to 9096 noncondensing Storage Environment Temperature netten 55 to 150 C Relative humidity se 596 to 9096 noncondensing Physical Dimensions ertet 9 9 cm by 12 0 cm 3 9
24. 4 8 interrupt control circuitry 3 3 interrupt level See also local interrupt default settings for National Instruments products table 2 3 to 2 4 factory settings table 2 2 selecting 2 4 to 2 5 T O channel control circuitry 3 2 T O connector electrical specifications A 1 to A 2 input signal specifications A 1 T O signal ratings A 1 output signal specifications A 2 pin assignments figure 2 7 B 1 timing and digital I O connector 3 3 IRQ bit 4 7 J jumper settings See also switch settings factory settings table 2 2 interrupt level selection 2 4 to 2 5 disabling interrupts figure 2 5 IRQS figure 2 4 to 2 5 local interrupt selection 2 5 L LabVIEW application software 1 2 LabWindows CVI application software 1 2 to 1 3 local interrupt See also interrupt level factory settings table 2 2 selecting 2 5 National Instruments Corporation manual See documentation MC6821 Control Registers 4 7 to 4 8 MC6821 Data Registers 4 6 Motorola MC6821 Peripheral Interface Adapter data sheet D 1 to D 12 interrupt programming example 4 9 to 4 21 register map 4 2 theory of operation 3 2 National Instruments application software 1 2 to 1 3 National Instruments Web support F 1 to F 2 NI DAQ driver software 1 3 0 online problem solving and diagnostic resources F 1 operating environment specifications A 2 operation of PC TIO 10 See theory of operation optional equipment 1 3 OUT
25. 5 10 14 475 n wee High to Read Low Write Recovery Tine Note ijj TWHSH Write High to CS High Note 12 20 ns TWHWL Write High Write Low Write Recovery Time Note 1 E TWHYV Write High to Out Valid Notes 6 14 90 ns TWLWH Write Low to Write High Write Pulse Duration Note 12 1 0 TGVEH2 Gate Valid to Count Source High Special Gate Notes 10 13 17 200 ns LTENGV2 Count Source High to Gate Vaid Special Gate Notes 10 13 18 ons Notes E Enabled counter source input SRC1 SRC5 1 Abbreviations used for the switching parameter symbois are F SU GATES F1 F5 TCN 1 given as the letter T followed by four or five characters The i first and thi cters r t the signal nai oi G Counter gate input GATE1 GATES TCN 1 4 h Q Data D80 0815 which the measurements start and end Signal abbrevia Read AD tions used are S Chip Select CS A Address W Write WR C Clock X2 Y Output OUT1 OUTS D Data in DBO DB15 2 150 Am9513A PC TIO 10 User Manual C 36 National Instruments Corporation The second and fourth letters designate the reference states of the signals named in the first and third letters respectively using the following abbreviations H HIGH L LOW V VALID X Unknown or Don t care Z High impedance 2 Any input transition that occurs before this minimum setup requirement will be ref
26. Defense applications are available in several packages and operating ranges Standard Military Drawing SMD DESC products are fully compliant with MIL STD 883C requirements The order number Valid Combination for SMD DESC products is formed by a combination of Military Drawing Part Number b Device Type c Case Outline d Lead Finish 5962 95523 9t a LEAD FINISH X Any Lead Finish Acceptable CASE OUTLINE 40 Pin Ceramic DIP CD 040 X 44 Pin Ceramic LCC CL 044 b MILITARY DEVICE TYPE 01 7 MHz 9513A amp MILITARY DRAWING NO DESCRIPTION 5962 85523 System Timing Controlier Valid Combinations Valid Combinations list configurations planned to be Valid Combinations supported in volume for this device Consult the local AMD sales office to confirm availability of specific valid combinations or to check for newly released valid combinations Group A Tests Group A tests consist of Subgroups 1 2 3 7 8 9 10 11 2 118 Am9513A PC TIO 10 User Manual C 4 National Instruments Corporation Appendix C AMD Am9513A Data Sheet products is formed by a combination of a Device Number c Device Class d Package Type Lead Finish 28 a ig DEVICE NUMBER DESCRIPTION Am9513A System Timing Controller Valid Combinations ORDERING INFORMATION continued APL Products AMD products
27. Jumper Setting Factory Setting OUT2 and OUT7 be jumpered simultaneously The interrupt for OUT2 is enabled and disabled through access to the port A interrupt control circuitry of the MC6821 PIA OUT7 is enabled and disabled through access to the port B interrupt control circuitry of the MC6821 PIA One or both of these interrupts can be asserted at any time if they are enabled If both interrupts are enabled simultaneously your interrupt handler must check both channels for interrupts before returning control to the foreground task For more information see Chapter 4 Programming National Instruments Corporation 2 5 PC TIO 10 User Manual Chapter 2 Configuration and Installation Installation The PC TIO 10 can be installed in any unused ISA 8 bit 16 bit or 32 bit expansion slot in your computer You are now ready to install the PC TIO 10 The following are general installation instructions but consult the user manual or technical reference manual of your personal computer for specific instructions and warnings If you want to install this board in an EISA class computer you can obtain a configuration file for the board by contacting National Instruments 1 Turn off your computer 2 Remove the top cover or access port to the I O channel 3 Remove the expansion slot cover on the back panel of the computer 4 Insert the PC TIO 10 in an unused ISA 8 bit 16 bit or 32 bit slot It may be a tight fit but do not
28. Load and Hold register contents respectively The symbols and N represent arbitrary count values For each mode the required bit pattern in the Counter Mode register is shown don t care bits are marked X These figures are designed to clarify the mode descriptions the Am9513A Electrical Specification should be used as the authoritative reference for timing relationships CMS 0 are shown with the WH pius entering the required between signals ARM command for modes which count repetitively CMS 1 2 128 Am9513A C 14 PC TIO 10 User Manual National Instruments Corporation To keep the following mode descriptions concise and to the point the phrase source edges used to refer to active going source edges only not to inactive going edges Simi larly the phrase gate edges refers only to active going gate edges Also again to avoid verbosity and euphuism the descriptions of some modes state that a counter is stopped or disarmed a TC inhibiting further counting As is fully explained in the TC section of this document for these modes the counter is actually stopped or disarmed following the active going source edge which drives the counter out of TC In other words since a counter in the TC state always counts irrespective of its gating or arming status the stopping or disarming of the count sequence is delayed until TC is terminated MODE A Software Triggered Strobe with
29. Minimum tgsu 100 nsec Minimum tgn 10 nsec Minimum tgw 145 nsec Minimum tour 300 nsec Maximum Figure 2 9 Timing Signal Relationships The GATE and OUT signal transitions in Figure 2 9 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges The same timing diagram with the source signal inverted and referenced to the falling edge of the source signal applies to the case in which the counter is programmed to count falling edges The signal applied at a SOURCE input can be used as a clock source by any of the Am9513A counter timers and by the Am9513A frequency division output FOUT The signal applied to a SOURCE input must not exceed a frequency of 7 MHz for proper operation of the Am9513A The Am9513A counters can be individually programmed to count rising or falling edges of signals applied at any of the Am9513A SOURCE or GATE input pins 2 12 National Instruments Corporation Chapter 2 Configuration and Installation In addition to the signals applied to the SOURCE and GATE inputs the Am9513A generates five internal timebase clocks from the clock signal supplied by the PC TIO 10 The five internal timebase clocks can be used as counting sources and these clocks have a maximum skew of 75 nsec between them The SOURCE signal shown in Figure 2 9 represents any of the signals applied at the SOURCE inputs GATE inputs or internal timebase cloc
30. Sheet For detailed applications information consult the Am9513A Am9513A System Timing Controller technical manual published by Advanced Micro Devices Inc Pulses and square waves can be produced by programming a counter to generate a pulse signal at its OUT pin or to toggle the OUT signal each time the counter reaches the terminal count For event counting one of the counters is programmed to count rising or falling edges applied to any of the Am9513A SOURCE inputs The counter value can then be read to determine the number of edges that have occurred Counter operation can be gated on and off during event counting National Instruments Corporation 2 9 PC TIO 10 User Manual Chapter 2 Configuration and Installation PC TIO 10 User Manual Figure 2 7 shows connections for a typical event counting operation where a switch is used to gate the counter on and off Counter SOURCE 5 OUT so bo GATE Switch Switch Source 9 33 GND Connector PC TIO 10 Board Figure 2 7 Event Counting Application with External Switch Gating To perform pulse width measurement a counter is programmed to be level gated The pulse to be measured is applied to the counter GATE input The counter is programmed to count while the signal at the GATE input is either high or low If the counter is programmed to count an internal time
31. Source High Source Cycle Time Note 7 145 ny TEL Count Source Duration Note 7 70 ns Count Source High to FOUT Valid Note 7 Count Source High to Gate Valid Level Gating Hold Time Notes 7 9 10 Count Source High to Read Low Set up Time Notes 2 7 Count Source High to Write High Set up Time Notes 3 7 100 te Out l Immediate or Delayed Toggle Output onn TEHGV TEHYV Count Source High to Out Valid Note 7 300 ns FN High to FN 1 Valid Note 11 75 ns TGVEH pes ud rs Source High Level Gating Set up Time 100 ni TGVGV Gate Valid to Gate Valid Gate Pulse Duration Notes 8 10 145 ns Gate Valid to Write High Notes 3 10 100 ns TRHAX Read High to C D Don t Care 0 ns TRHEH Read High to Count Source High Notes 4 7 ns TRHOX Read High to Data Out Invalid ons TRHOZ High Data on a High Impedance 85 ns TRHRL Read High to Read Low Read Recovery Time 1000 ns TRHSH Read High to CS High Note 12 0 TRHWL Read High to Write Low Read Recovery Time 1000 ns TRLOV Read Low to Data Out Valid 110 ns ns TRLRH Read Low to Read High Head Pulse Duration Note 12 Tsun CS tow to Read tow Nue ij ns 170 ns Write High to Don t Care 20 ns TWHOX Write High to Data in Don t Care 20 TWHEH Write High to Count Source High Notes 5 7 14 15 sso n TWHGV Write High to Gate Valid Notes
32. TC once then disarm xx Count to TC disarm Lg a T count to TC repeatedly wo saig X X x x LE Gate input does not gate counter input x x x x Count onty during active gate level x x x x Start count on active gate edge and stop count on x x next TC Start count on active gate edge and stop count on x x second TC No hardware reriggerng X X X XT Reload counter from Load register on TC Retoad counter on each TC alternating reload source between Load and registers Transter Load register into counter on each TC that gate is LOW transfer Hold register into counter on each TC that gate is HIGH On active gate edge transfer counter into Hold register and then reload counter from Load register Counter Mode Special Gate CM7 Reload Source CM6 Repetition CM5 Gate Control CM15 CM13 Count to TC once then disarm Count to TC twice then disarm Count to TC repeatedty without disarming Gate input does not gate counter input Count onty during active gate level Start count on active gate edge and stop count on next TC Start count on active gate edge and stop count on second TC No hardware retriggering Reload counter from Load register on TC Reload counter on sach TC aitemating reload source between Load and Hold registers Transfer Load register into counter on each TC that gate is LOW
33. TIO 10 User Manual a method of triggering in which you simulate an analog trigger using software Also called software triggering device that transforms a signal from one form to another For example analog to digital converters ADCs for analog input digital to analog converters DACs for analog output digital input or output ports and counter timers are conversion devices the time required in an analog input or output system from the moment a channel is interrogated such as with a read instruction to the moment that accurate data is available digital to analog digital to analog converter an electronic device often an integrated circuit that converts a digital number into a corresponding analog voltage or current a method of propagating signals along a bus in which the devices are prioritized on the basis of their position on the bus decibel the unit for expressing a logarithmic measure of the ratio of two signal levels dB 20log10 V1 V2 for signals in volts direct digital synthesis a high accuracy circuit that samples at a higher rate and lower resolution than is needed and by means of feedback loops pushes the quantization noise above the frequency range of interest This out of band noise is typically removed by digital filters a control action with an output that is proportional to the rate of change of the error signal Derivative control anticipates the magnitude difference between the process variabl
34. These eight bits should be accessed before the eight bits of the most significant byte are accessed National Instruments Corporation 4 3 PC TIO 10 User Manual Chapter 4 Programming Am9513A Command Registers The Am9513A Command Registers control the overall operation of the Am9513A Counter Timer and selection of the internal registers that are accessed through the Am9513A Data Registers Address Base address 01 hex for Am9513A STC A Base address 03 hex for Am9513A STC B Type Write only Word Size 8 bit register 8 bit port Bit Map yi 6 5 4 3 2 1 0 C7 C6 C5 C4 C3 C2 Cl CO Bit Name Description 7 0 C lt 7 0 gt These eight bits are loaded into the Am9513A Command Register See Appendix C AMD Am9513A Data Sheet for detailed bit descriptions of the Am9513A Command Registers PC TIO 10 User Manual 4 4 National Instruments Corporation Am9513A Status Registers Chapter 4 Programming The Am9513A Status Registers give information about the output pin status of each counter in Am9513A In addition these registers indicate the current setting of the byte pointer which indicates whether the next byte to be accessed is the most significant byte or the least significant byte Address Base address 01 hex for Am9513A STC A Base address 03 hex for Am9513A STC B Type Read only Word Size 8 bit register 8 bit port Bit Map 6 5 4 3
35. added in a 1 1 amplitude ratio inches standardized digital communications networks used in industrial automation applications they often replace vendor proprietary networks so that devices from different vendors can communicate in control systems integral nonlinearity a measure in LSB of the worst case deviation from the ideal A D or D A transfer characteristic of the analog I O circuitry PC TIO 10 User Manual Glossary input bias current input impedance input offset current instrument driver instrumentation amplifier integral control integrating ADC interval scanning I out ISA isolation isolation voltage isothermal kS PC TIO 10 User Manual the current that flows into the inputs of a circuit the measured resistance and capacitance between the input terminals of a circuit the difference in the input bias currents of the two inputs of an instrumentation amplifier a set of high level software functions that controls a specific GPIB VXI or RS 232 programmable instrument or a specific plug in DAQ board Instrument drivers are available in several forms ranging from a function callable language to a virtual instrument VI in LabVIEW a circuit whose output voltage with respect to ground is proportional to the difference between the voltages at its two inputs a control action that eliminates the offset inherent in proportional control an ADC whose output code represents the averag
36. and as flexible as using the low level programming described in Chapter 4 Programming There are several options to choose from when programming your National Instruments DAQ hardware You can use LabVIEW LabWindows CVI or NI DAQ National Instruments Application Software PC TIO 10 User Manual LabVIEW features interactive graphics a state of the art user interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of virtual instruments VIs for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW The LabVIEW Data Acquisition VI Library is functionally equivalent to the NI DAQ software LabWindows CVI features interactive graphics and a state of the art user interface and uses the ANSI standard C programming language The LabWindows CVI Data Acquisition Library a series of functions for using 1 2 National Instruments Corporation Chapter 1 Introduction National Instruments DAQ hardware is included with LabVIEW CVI The LabWindows CVI Data Acquisition VI Library is functionally equivalent to the NI DAQ software Using LabVIEW or LabWindows CVI software will greatly reduce the development time for your data acquisition and control application NI DAQ Driver Software The NI DAQ driver software is included at no charge with all National Instruments DAQ hardware NI DAQ has an extensive library of functions that you can call from your application pro
37. bx cl cx bx bx al maskm 2 cl al al bl maskm al 42 al masks 42 ch al al bh masks al int mask cx restore saved registers ii exit pop pop pop pop pop pop pop sti ret install isr PC TIO 10 User Manual es ds dx cx bx ax bp endp 4 18 get interrupt level generate some masks cx has 1 in bit pos of int level bx has 0 in bit pos of int level get mask data from master chip delay wait for data transfer determine setting of mask bit enable interrupts for selected delay wait for data transfer get mask data from slave chip delay wait for data transfer determine setting of mask bit enable interrupts for selected save the previous value of the mask National Instruments Corporation remove isr bp reg ret addr ofs ret addr seg remove isr proc cli push push push push push push mov mov See if our vector cmp jz mov mov int mov mov cmp jne cmp jne National Instruments Corporation at bp 0 at bp 2 at bp 4 far ax bx cx dx ds es ax seg _DATA ds ax Chapter 4 Programming is installed if not do not remove the vector vect_num 0 short ri_exit al vect_num ah 35h 21h 2 dx es dx cx see our get get if vect num was ever set vector never installed exit vector number current vector from DOS get previous int addr in es bx prep to compare old current vectors See i
38. eight byte block transfers in which both the Address bus and the Data bus are used to transfer data million floating point operations per second the unit for expressing the computational power of a processor multifunction I O million instructions per second the unit for expressing the speed of processor machine code instructions MXI Interface to Everything a custom ASIC designed by National Instruments that implements the PCI bus interface The MITE supports bus mastering for high speed data transfers over the PCI bus most significant bit mean time between failure mean time to repair predicts downtime and how long it takes to fix a product PC TIO 10 User Manual Glossary multiplexed mode mux NIST NI TIO 0 onboard RAM optical coupler optocoupler optical isolation output settling time output slew rate PC TIO 10 User Manual an SCXI operating mode in which analog input channels are multiplexed into one module output so that your cabled DAQ device has access to the module s multiplexed output as well as the outputs on all other multiplexed modules in the chassis through the SCXI bus Also called serial mode multiplexer a switching device with multiple inputs that sequentially connects each of its inputs to its output typically at high speeds in order to measure several signals with a single analog input channel NuBus a slot dependent 32 bit bus type used in Macintosh computers t
39. for Aerospace and Defense applications are available in several packages and operating ranges APL Approved Products List products ara fully compliant with MIL STD 883C requirements The order number Valid Combination for APL b Speed Option if applicable A EN LEAD FINISH A Hot Solder DIP d PACKAGE TYPE Q 40 Pin Ceramic DIP CD 040 44 Pin Ceramic Leadless Chip Carrier CL 044 DEVICE CLASS B Class B b SPEED OPTION Not Applicable Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device Consult the local AMD sales office to confirm availability of specific valid combinations or to check for newly released valid combinations Group A Tests Group A tests consist of Subgroups 1 2 3 7 8 9 10 11 9513 National Instruments Corporation 2 119 C 5 PC TIO 10 User Manual Appendix C AMD Am9513A Data Sheet PIN DESCRIPTION Crystal X1 and X2 are the connections for an externat crystal used to determine the frequency of the internal oscillator The crystal should be a paraile resonant fundamental mode type An RC or LC or other reactive network may be used instead of a crystal For driving from an external frequency source X1 should be left open and X2 should be connected to a TTL source and a pull up resistor 7 FOUT Frequency The FOUT output is denved from 4 bit counter that may programmed to d
40. for serial communication update interval a signal range that is always positive for example 0 to 10 V PC TIO 10 User Manual Glossary update update rate visual basic custom control VBXs VPICD W working voltage PC TIO 10 User Manual the output equivalent of a scan One or more analog or digital output samples Typically the number of output samples in an update is equal to the number of channels in the output group For example one pulse from the update clock produces one update which sends one new sample to every analog output channel in the group the number of output updates per second volts volts direct current virtual DMA driver external volt volts input high volts input low volts in virtual instrument software architecture a new driver software architecture developed by National Instruments to unify instrumentation software GPIB DAQ and VXI It has been accepted as a standard for VXI by the VXIplug amp play Systems Alliance a specific form of binary packaged object that can be created by different companies and integrated into applications written using Visual Basic virtual programmable interrupt controller device the highest voltage that should be applied to a product in normal use normally well under the breakdown voltage for safety margin See also breakdown voltage G 16 National Instruments Corporation Glossary Z zero overhead looping the ability of a high perform
41. force the board into place 5 Screw the mounting bracket of the PC TIO 10 to the back panel rail of the computer Check the installation Replace the cover to the computer Note If you have an ISA class computer and you are using a configurable software package such as NI DAQ you may need to reconfigure your software to reflect any changes in jumper or switch settings If you have an EISA class computer you need to update the computer s resource allocation or configuration table by reconfiguring your computer See your computer s user manual for information about updating the configuration table The PC TIO 10 board is now installed and ready for operation Signal Connections A This section includes specifications and connection instructions for the signals given on the PC TIO 10 I O connector Caution Connections that exceed any of the maximun ratings of input or output signals on the PC TIO 10 may result in damage to the PC TIO 10 board and to the PC Maximum input ratings for each signal are given in this chapter under the discussion of that signal National Instruments is not liable for any damages resulting from any such signal connections PC TIO 10 User Manual 2 6 National Instruments Corporation 1 0 Connector Pin Description Figure 2 6 show the pin assignments for the PC TIO 10 I O connector Chapter 2 SOURCE1 OUT1 GATE2 SOURCE3 OUT3 GATE4 GATE5 SOURCE6 OUT6 GATE7 SOURCE8 OUT8 GATE9 GAT
42. hardware sampling of the counter contents without interrupting the count A LOAD AND ARM command or a LOAD command followed by an ARM command is required to initialize the counter Once armed a Gate edge starts the counting operation Gate edges applied to a disarmed counter are disregarded After application of the Triggering Gate edge the counter will count ail qualified source edges until the first TC irrespective of the gate level All gate edges applied during the counting sequence will store the current count in the Hold register but they will not interrupt the counting sequence On each TC the counter will be reloaded from the Load register and stopped Subsequent counting requires a new triggering Gate edge counting resumes on the first source edge following the triggering Gate edge Note Mode X is only available in the Am9513A devices COUNTER MODE CONTROL OPTIONS Each Counter Logic Group includes a 16 bit Counter Mode CM register used to contro of the individual options available with its associated general counter These options gating control Figure 18 shows the bit assignments for the options in detail Note that generally each counter is indepen dently configured and does not depend on information outside its Counter Logic Group The Counter Mode register should be loaded only when the counter is Disarmed Attempts to load the Counter Mode register when the counter is armed may resuit in erratic counter operation
43. in a high impedance state After power up or reset the data bus will be configured for 8 bit width and will use only OBO through OB7 DBO is the least significant and 087 is the most significant bit position The data bus may be reconfigured for 16 bit width by changing a control bit in tne Master Mode register This is accomplished by writing an 8 bit command into the low order OB lines while holding the 0813 DB15 lines at a logic high level Thereafter 16 lines can be used with DBO as the least significant and DB15 as the most significant bit position When operating in the 8 bit data bus environment DB8 0815 will never be driven active by the 9513 through DB12 may optionally be used as additional Gate inputs see Figure 2 If unused they should be heid HIGH When pulled LOW a GATENA signal will disable the action of the corresponding counter N gating 0813 0815 should be held HIGH in 6 0 bus mode whenever CS and WR are simultaneously active Chip Select The active low Chip Select input enables Read and Write operations on the data bus When Chip Select is HIGH the Read and Write inputs are ignored The first Chip Select signal after power up is used to clear the power on reset circuitry if Chip Select is tied to ground permanently the power on reset circuitry may not function In such a configuration the software reset command must be issued following power up to reset tha Am9513A 1 RD 1 Read The active
44. is actually disarmed stopped immediately following TC 2 142 PC TIO 10 User Manual This may cause count sequences different from what a user might expect Since the counter is always reloaded at the start of TC and since it always counts at the end of TC the counter contents following TC will differ by one from the reloaced value irrespective of the operating mode used If the reloaded value was 0001 for down counting 9999 BCD for BCD up counting or FFFF hex for binary up counting the count at the end of TC will drive the counter into TC again regardless of whether the counter is gated off or disarmed As long as these values are reloaded the TC output will stay active If a TC Toggled output is selected it will toggle on each count Execution of a LOAD LOAD AND ARM or STEP command with these counter contents will act the same as application of a source pulse causing to remain active and a TC Toggled output to toggie Count Control Counter Mode bits CM3 through CM7 specify the various options available for direct control of the counting process CM3 and CM4 operate independently of the others and control up down and BCD binary counting They may be combined freely with other control bits to form many types of counting configurations The other three bits and the Gating Control field interact in complex ways Bit CM5 controls the repetition of the count process When CMS 1 counting will proceed in the specified mo
45. its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be lia
46. may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation LabVIEW nat inst com and NI DAQ are trademarks of National Instruments Corporation Product and company names mentioned herein are trademarks or trade names of their respective companies WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing for a level of reliability suitable for use in or in connection with surgical implants or as critical components in any life support systems whose failure to perform can reasonably be expected to cause significant injury to a human Applications of National Instruments products involving medical or clinical treatment can create a potential for death or bodily injury caused by product failure or by errors on the part of the user or application designer Because each end user system is customized and differs from National Instruments testing platforms and because a user or application designer may use National Instruments products in combination with other products in a manner not evaluated or contemplated by National Instruments the user or application designer is ultimately responsible for verifying and validating the suitability of Nation
47. measure of deviation of the gain of an amplifier from the ideal gain an undesired change in a signal that typically lasts a short period of time level of random vibration G 6 National Instruments Corporation H half flash ADC half power bandwidth handshaked digital I O hex Hz IDE IEEE 488 IMD in Industrial Device Networks INL National Instruments Corporation G 7 Glossary an ADC that determines its output code by digitally combining the results of two sequentially performed lower resolution flash conversions the frequency range over which a circuit maintains a level of at least 3 dB with respect to the maximum level a type of digital acquisition generation where a device or module accepts or transfers data after a digital pulse has been received Also called latched digital I O hexadecimal hertz integrated development environment the shortened notation for ANSI IEEE Standards 488 1978 488 1 1987 and 488 2 1987 See also GPIB intermodulation distortion the ratio in dB of the total rms signal level of harmonic sum and difference distortion products to the overall rms signal level The test signal is two sine waves added together according to the following standards SMPTE A 60 Hz sine wave and a 7 kHz sine wave added in a 4 1 amplitude ratio DIN A 250 Hz sine wave and an 8 kHz sine wave added in a 4 1 amplitude ratio CCIF A 14 kHz sine wave and a 15 kHz sine wave
48. one the specified operation is performed on the counter so designated when an S bit is a Zero no operation occurs for the corresponding counter This type oi command format has three basic advantages It saves host software by allowing any combination of counters to be acted on by a single command It allows simultaneous action on multiple counters where synchronization of commands is important It allows counter specific service routines to control individual counters without needing to be aware of the operating context of other counters Three of the commands use a 3 bit binary code N4 N2 N1 to identify the affected counter a 001 programs counter 1 etc Unlike the previously mentioned commands these commands allow you to program only one counter at a time Am9513A 2 143 National Instruments Corporation C 29 PC TIO 10 User Manual Appendix C AMD Am9513A Data Sheet Command Code c2 c1 co Command Description Et Load Data Pointer register with contents of E and G fields G 000 G 110 sa S3 S2 51 Arm counting tor selected counters Ss sa so 52 SY Load contents of speciei source al selected commis s2 S Load and Arm al selected counters S2 St and Save an selected S3 S2 S Save selected counters in Hold register 55 53 52 S Disarm selected counters 1 Na N2 N Set Toggle out HIGH for counter N 001 lt N lt 101
49. patterns at a constant rate because the handshaked signal is produced at a constant rate a credit card sized expansion card that fits in a PCMCIA slot often referred to as a PCMCIA card Peripheral Component Interconnect a high performance expansion bus architecture originally developed by Intel to replace ISA and EISA It is achieving widespread acceptance as a standard for PCs and workstations it offers a theoretical maximum transfer rate of 132 Mbytes s an expansion bus architecture that has found widespread acceptance as a de facto standard in notebook size computers It originated as a specification for add on memory cards written by the Personal Computer Memory Card International Association programmable function input programmable gain instrumentation amplifier an electrical device that responds to a change in the intensity of the light falling upon it Peripheral Interface Adapter a three term control mechanism combining proportional integral and derivative control actions Also see proportional control integral control and derivative control the technique used on a DAQ board to acquire a programmed number of samples after trigger conditions are met PC TIO 10 User Manual Glossary potentiometer pretriggering proportional control protocol proximity sensor PXI Q quantization error quantizer R reglitch relative accuracy resolution PC TIO 10 User Manual an electrical device th
50. reload will reload the counter from the Load register If the Gate is HIGH LOADs and reloads will occur from the Hoid register The polarity of the Gate only selects the reload source it does not start or modulate counting Once armed the counter will count repetitively to TC On each TC the counter will reload itself from the register determined by the polarity of the Gate Counting will continue in this manner until a DISARM command is issued to the counter Frequency shift keying may be obtained by specifying a TC Toggied output mode in the Counter Mode register The switching of frequencies is achieved by modulating the Gate C 24 National Instruments Corporation Appendix C AMD Am9513A Data Sheet NINININININININ ET NENNEN WHORE ARES x MEE Cae ae aay GED WFO004751 Figure 15s Mode S Waveforms aa AVAVAVAUAUAUAUAVAUAUAUAC a SOY UNE D ED ED C ED ED CD E D D E9 CD E EN S EP NES LEE merce oe WFO04 Figure 15v Mode V Waveforms 760 Am9513A 2 139 National Instruments Corporation C 25 PC TIO 10 User Manual Appendix C AMD 9513 Data Sheet MODE X Hardware Save available in Am9513A only cms oma cwiz own cto edge x Px x x x cms cma 2 Pate ts txt xt xix x Mode X as shown in Figure 15x provides a
51. the FOUT interface pin The STC is addressed by the external system as two locations a Control port and a Data port The Control port Figure 4 Counter Logic Groups 1 and 2 2 122 PC TIO 10 User Manual 15001221 provides direct access to the Status and Command registers as weil as allowing the user to update the Data Pointer register The Data port is used to communicate with all other addressable internal locations The Data Pointer register controls the Data port addressing Among the registers accessible through the Data port are the Master Mode register and five Counter Mode registers one for each counter The Master Mode register controls the program options that are not controlled by the Counter Mode registers Each of the five general purpose counters 16 bits long and is independently controlled by its Counter Mode register Through this register a user can software select one of 16 sources as the counter input a variety of gating and repetition modes up or down counting in binary or BCD and active high or active low input and output polarities Associated with each counter are a Load register and a Hold register both accessible through the Data port The Load register is used to automatically reload the counter to any predefined vaiue thus controlling the effective count period The Hold register is used to save count values without disturbing the count process permitting the host processo
52. the Gate input will be disregarded until the second TC This differs from Mode H where the Gate can be modulated throughout the count cycle to stop and start the Cu eee x Xe o 20 CD CC CA et D one Figure 15h Mode H Waveforms AMD Am9513A Data Sheet Am9513A 2 133 National Instruments Corporation C 19 PC TIO 10 User Manual Appendix C AMD Am9513A Data Sheet care QUU WFO04670 Figure 15i Mode Waveforms MODE J Variable Duty Cycle Rate Generator with No Hardware Gating cm7 cms 2 cmo x Mode J shown Figure 15 will find the greatest usage frequency generation applications with variable duty cycle requirements Once armed the counter will count continuously until it is issued a DISARM command On the first TC the counter will be reloaded from the Hold register Counting will then proceed until the second TC at which time the counter will be reloaded from the Load register Counting will continue with the reload source alternating on each TC until a DISARM command is issued to the counter The third TC reloads from the Hold register the fourth TC reloads from the Load register etc A variable duty cycle output can be generated by specif
53. the Terminal Count TC occurs Terminal Count is defined as that period of time when the counter contents would have been zero if an external value had not been transferred into the counter Thus the terminal count frequency can be the input frequency Am9513A National Instruments Corporation Appendix C divided by the value in the Load register In all operating modes either the Load or Hold register will be transferred into the counter when TC occurs In cases where values are being accumulated in the counter the Load register action can become transparent by filling the Load register with all zeros Hold Register The 16 bit read write Hold register is dual purpose It can be used in the same way as the Load register thus offering an alternate source for module definition for the counter The Hold register may also be used to store accumulated counter values for later transfer to the host processor This allows the count to be sampled while the counting process proceeds without interruption Transfer of the counter contents into the Hold register is accomplished by the hardware interface in Some operating modes or by software commands at any time Counter Mode Register The 16 bit read write Counter Mode register controis the gating counting output and source select functions within each Counter Logic Group The Counter Mode Control Options section of this document describes the detailed control options available
54. there is a 75 ns skew between F1 F2 F3 F4 and F5 9 The TC output will remain inactive if programmed to be in the TC TOGGLE mode and the step command is used to increment or decrement the counter The output will go into TC if programmed to be in the active High or active Low terminal count modes The only two ways out of TC in this case are Arming the counter and having an active source con nected to it lssuing another step command Troubleshooting Symptom Solution Appendix APPENDIX 10 Timing parameters TEHWH TGVWH specified as negative The diagrams in Figure A3 show the relationship between these signais 11 in mode X the counter will count all qualified source edges until the second not the first TC and then stop 12 A TC can occur when the counters are loaded if the counter was stopped at FFFF 999949 in the count up mode or at count 0001 when counting down This is because an internal TC is generated which forces TC to be generated on the next count pulse 13 In modes that alternate the reload source between the load and the hold registers e g mode J if the counter is disarmed at 00014 for down counting or 999919 for BCD up counting or FFFFy for binary up counting and rearmed the reload source after the first TC will be the load register instead of the hold register To avoid this issue a software dummy load to the counter immediately after the disar
55. were generated by a source edge rather than by the LOAO Execution of a LOAD or LOAD AND ARM command while the counter is in TC will cause the TC to end For Armed counters in all modes except S or V the LOAD source used will be that to be used for the upcoming TC The LOADing operation will not alter the selection of reload source for the upcoming TC For Disarmed counters in modes except S or V the reload sources used will be the LOAD register For modes S or V the In modes which alternate reload sources Modes G L the reload source will be selected by the GATE input regardless ARMing operation is used as a reset for the logic which of whether the counter is Armed or Disarmed 2 144 PC TIO 10 User Manual Am9513A C 30 National Instruments Corporation Special considerations apply when modes with alternating reload sources are used Modes G L If a LOAD command drives the counter to TC in these modes the reload source for the next TC will be from the opposite reload location In other words the LOAD generated TC will cause the reload sources to alternate just as a TC generated by a source edge would Note that if a second LOAD command is issued during the LOAD generated TC or during any other TC for that matter the second LOAD command will terminate the TC and cause a reload from the source designated for use with the next TC The second LOAD will not alter the reload source for the next TC since the se
56. ws Towra cma cm2 cmo cmo oms cw cvs 2 cmt x MODE G In Mode G the Gate does not affect the counter s operation Once armed the counter will count to TC twice and then automatically disarm itself For most applications the counter will initially be loaded from the Load register either by a LOAD command or by the last TC of an earlier timing cycle Upon counting to the first TC the counter wiil reload itself from the Hold register Counting will proceed until the second TC when the counter will reload itself from the Load register and automatically disarm itself inhibiting further counting Counting can be resumed by issuing a new ARM command A software triggered delayed puise one shot may be generated by speci fying the TC Toggled output mode in the Counter Mode register The initial counter contents control the delay from the ARM command until the output pulse starts The Hold register contents control the pulse duration Mode G is shown in Fig ure 15g PC TIO 10 User Manual DD DDD aare NA OX AAA Figure 15f Mode F Waveforms 2 132 Am9513A C 18 National Instruments Corporation Appendix C E MODE H Sottware Triggered Delayed Puise One Shot with Hardware Gating cms cma cma cm2 cm cmo EEEREN _om7 cms cma 2
57. 0 Description This command sets Master Mode bit 14 without affecting other bits in the Master Mode register MM14 controls the automatic sequencing of the Data Pointer regis ter Disabling the sequencing allows repetitive host processor access to a given internal location without repetitive updating of the Data Pointer MM14 may also be controlled by loading a full word into the Master Mode regi C 31 AMD Am9513A Data Sheet 2 145 PC TIO 10 User Manual Appendix C AMD Am9513A Data Sheet Enable Data Pointer Sequencing cleared FOUT will become active and will drive out the selected and divided FOUT signal 12 be Coding controlled by loading the fuil Master Mode register in parallel 1 1 1 0 O0 0 0 90 Description This command clears Master Mode bit 14 without aftecting other bits in the Master Mode register MM14 controls the automatic sequencing of the Data Pointer regis ter Enabling the sequencing allows sequential host processor access to several internal locations without repetitive updating of the Data Pointer MM14 may also be controlled by loading a full word into the Master Mode register See the Data Pointer Register section of this document for additional information on Data Pointer sequencing Enable 16 Bit Data Bus Coding C7 C8 C5 C4 C2 CI 1 1 1 0 1 1 1 1 Description This command sets Master Mode bit 13 without affecting other bits in the Master Mode register MM
58. 03 M mega 106 Numbers Symbols degrees percent A A amperes A D analog to digital ADC analog to digital converter an electronic device often an integrated ADC resolution ALU AMD amplification circuit that converts an analog voltage to a digital number the resolution of the ADC which is measured in bits An ADC with 16 bits has a higher resolution and thus a higher degree of accuracy than a 12 bit ADC arithmetic logic unit the element s in a processing system that perform s the mathematical functions such as addition subtraction multiplication division inversion AND OR NAND and NOR Advanced Micro Devices a type of signal conditioning that improves accuracy in the resulting digitized signal and reduces noise National Instruments Corporation G 1 PC TIO 10 User Manual Glossary amplitude flatness antialiasing filter anti imaging filter attenuate attenuation ratio autozero AWG B BCD bipolar break before make breakdown voltage brickwall filter burden voltage burst mode PC TIO 10 User Manual a measure of how close to constant the gain of a circuit remains over a range of frequencies a low pass filter preceding an ADC usually a brickwall filter that rejects signal energy above the Nyquist frequency 1 2 the sample rate of the ADC so that the ADC does not mistake out of band signals for in band signals a low pass filter after an DAC usually a bri
59. 1 and 2 MOTOROLA MICROPROCESSOR DATA 3 1700 National Instruments Corporation D 10 PC TIO 10 User Manual Appendix D Motorola MC6821Data Sheet MC6821 Determine Active CA1 CB1 Transition for Setting Interrupt Flag IROA B 1 bit 7 b1 0 IRQA B 1 set by high to iow transition on CAT CB1 bi 1 IRQAIBI set by low to high transition on CA1 CB FIGURE 18 CONTROL WORD FORMAT CA1 CB1 Interrupt Request Enable Disable bO 0 Disables IRQA B MPU Interrupt by CA1 CB1 active transition bO 1 Enable IRQA B MPU Interrupt by CA1 1 active transition 1 IRQA B will occur on next MPU generated positive transition of bO if CAT CBT active transition oc curred while interrupt was disabled IRQA B 1 Interrupt Flag bit 7 Goes high on active transition of CA1 1 Automa tically cleared by MPU Read of Output Register A B May also be cleared by hardware Reset sw s w Is o IRQA B 1 IRQA B 2 CA2 CB2 DDR CA1 1 Flag Flag Control Access Controi IROA B 2 Interrupt Flag bit 6 When CA2 C82 is an input IRQA B goes high on ac tive transition CA2 CB2 Automatically cleared by MPU Read of Output Register A B May also be Cleared by hardware Reset CA2 CB2 Established as Output b5 1 IROAIB 220 not affected by CA2 CB2 transitions Control Register Determines Whether Data Direction Regis
60. 13 controls the multiplexer in the data bus buffer When MM13 is set multiplexing takes place and ail 16 exte nal data bus lines are used to transfer information into and out of the STC 13 may be controlled by loading the full Master Mode register in parallel Enable 8 Bit Data Bus Coding C7 C6 CS C4 C3 C2 Ci Description This command clears Master Mode bit 13 without affecting other bits in the Master Mode register MM13 controis the multiplexer in the data bus buffer When MM13 is cleared the muitiplexer is enabled and 16 bit internal informa tion is transferred eight bits at a time to the eight low order externa data bus lines MM13 may also be controlled by loading the full Master Mode register in parallel Gate Off FOUT Coding C7 C8 C5 C3 C2 C1 CO Description This command sets Master Mode bit 12 without affecting other bits in the Master Mode register MM12 controis the output state of the FOUT signal When gated off the FOUT line will exhibit a low impedance to ground MM12 may aiso be controlled by loading the full Master Mode register in parallel Gate On FOUT Description This command clears Master Mode bit 12 without affecting other bits in the Master Mode register MM12 controls the output status of the FOUT signal When MM12 is 2 146 PC TIO 10 User Manual When FOUT is gated on or off a transient pulse may be generated on the FOUT signal Disable Prefetch for Wr
61. 2 1 0 X OUT5 OUT4 OUT3 OUT2 OUTI BYTE POINTER Bit Name Description 7 6 X Unused bits They may be returned as 0 or 1 5 1 OUT lt 5 1 gt Each of these five bits returns the logic state of the associated counter output pin For example if the bit OUTA is set then the output pin of Counter 4 or Counter 9 is at a logic high state 0 BYTE This bit represents the state of the Am9513A Byte Pointer POINTER Flip Flop If this bit is set the next byte to be written to or National Instruments Corporation read from the Data Port is the least significant byte if this bit is clear the next byte to be written to or read from the Data Port is the most significant byte 4 5 PC TIO 10 User Manual Chapter 4 Programming Register Descriptions for the MC6821 The MC6821 PIA has four registers Port A and Port B both have a Data Register and a Control Register The bit maps and signal definitions for each of these registers are as follows For more information on the various registers refer to Appendix D Motorola MC6821Data Sheet MC6821 Data Registers The MC6821 Data Registers are used to read from or write to the Output Registers the I O registers for Ports A and B and the Data Direction Registers Address Base address 04 hex for Port A Base address 06 hex for Port B Type Read and write Word Size 8 bit register 8 bit port Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 DI DO Bit Name D
62. 513A PC TIO 10 User Manual C 22 National Instruments Corporation NINININININININININININININININ _ 7 OUTPUT Figure 150 Mode O Waveforms MODE Q Rate Generator with Synchronization Event Counter with Auto Read Reset E ouem Ex Lx X2 rue puts aes pac pe e n Mode Q shown in Figure 15q provides a rate generator with synchronization or an event counter with auto read reset The counter must first be issued an ARM command before Counting can occur Once armed the counter will count all source edges which occur while the Gate is active and disregard those edges which cccur while the Gate is inactive This permits the Gate to turn the count process on and off After the issuance of an ARM command and the application of an active Gate the counter will count to TC repetitively On each TC the counter will reload itself from the Load register The counter may be retriggered at any time by presenting an active going Gate edge to the Gate input The retriggering Gate edge will transfer the contents of the counter into the Hold register The first qualified source edge after the retrig gering Gate edge will transfer the contents of the Load register into the Counter Counting will resume on the second qualified source edge after the retriggering Gate edge Quali fied source edges are active going edges which occur while the Gate is acti
63. A and Port B National Instruments Corporation 4 1 PC TIO 10 User Manual Chapter 4 Programming Register Map The following table lists the address map for the PC TIO 10 Table 4 1 PC TIO 10 Address Map Offset Address Register Hex Size Type Am9513A Register Group STCA Data Register 00 8 bit Read and write Read and write 01 8 bit Write only Command Register 01 8 bit Read only STC B Data Register 02 8 bit Read and write Command Register 03 8 bit Write only Status Register 03 8 bit Read only MC6821 Register Group PIA Port A Data Register 04 8 bit Read and write Port A Control Register 05 8 bit Read and write Port B Data Register 06 8 bit Read and write Port B Control Register 07 8 bit Read and write Register Descriptions The register descriptions for the devices on the PC TIO 10 including the Am9513A STCs and the MC6821 PIA are given on the pages that follow Register Descriptions for the Am9513A STCs Each of the two Am9513A STC devices has three registers a data register a command register and a status register The bit maps and signal definitions for each of these registers are as follows Counters 1 2 3 4 and 5 map to Counters 1 2 3 4 and 5 of STC A respectively Counters 6 7 8 9 and 10 map to Counters 1 2 3 4 and 5 of STC B respectively PC TIO 10 User Manual 4 2 National Instruments Corporation Chapter 4 Programming Am9513A Data Registers The A
64. CM5 and CM6 Hardware Retriggering Whenever hardware retriggering is enabled Modes N O Q and A all active going Gate edges initiate retrigger opera tions On application of the Gate edge the counter contents will be transferred to the Hold register On the first qualified source edge after application of the retriggering Gate edge the Load register contents will be transferred into the counter Qualified source edges are edges which occur while the counter is gated on and Armed This means that if level gating is used the edge occurring on active going gate transitions will initiate a retrigger Similarly when edge gating is enabled an edge used to start the counter will aiso initiate a retrigger The first count source edge applied after the Gate edge will not increment decre ment the counter but retrigger it If a LOAD LOAD AND ARM or a STEP Command occurs between the retriggering Gate edge and the first qualified source edge it will be interpreted as a source edge and transfer the Load register contents into the counter There after the counter will count all qualified source edges When some form of Gating is specified CM7 controls hard ware retriggering In this case when CM7 0 hardware retriggering does not occur when CM7 1 the counter is retriggered any time an active going Gate edge occurs Retriggering causes the counter value to be saved in the Hold register and the Load register contents to be trans
65. Chip PBS Setect RS0 36 PB6 RS 35 Rw e87 RW 21 Control Enabie 25 RESET 34 Data Direction Control Register B Register 8 CRB T 18 CB interrupt Status 37 Control B 39 683 SSS ae a ae eee a MOTOROLA MICROPROCESSOR DATA 3 1697 PC TIO 10 User Manual D 7 National Instruments Corporation Appendix D MC6821 PIA INTERFACE SIGNALS FOR MPU The PIA interfaces to the M6800 bus with an 8 bit bidirec tional data bus three chip select lines two register select fines two interrupt request lines a read write line an enable line and a reset line To ensure proper operation with the MC6800 MC6802 or MC6808 microprocessors shouid be used as an active part of the address decoding Bidirectional Data 00 07 The bidirectional data lines 00 07 allow the transfer of data between the MPU and the PIA The data bus output drivers are three state devices that remain in the high impedance off state except when the MPU performs a PIA read operation The read write line is in the read high state when the PIA is selected for a read operation Enable E The enable pulse E is the only timing Signal that is supplied to the PIA Timing of all other signals is referenced to the leading and trailing edges of the E pulse Read Write R W This Signal is generated by the MPU to control the direction of data transfers on the data bus A low state on the PIA read write line
66. Coding Description Any combination of counters as specified by the S field will be enabled for counting A counter must be armed before counting can commerce Once armed the counting process may be further enabled or disabled using the hard ware gating facilities This command can only arm or do nothing for a given counter a zero in the S field does not disarm the counter ARM and DISARM commands can be used to gate counter operation on and off under software control DISARM com mands entered while a counter is in the TC state will not take effect until the counter leaves TC This ensures that the counter never latches up in a TC state The counter may leave the TC state because of application of a count source edge execution of a LOAD or LOAD AND ARM command or execution of a STEP command Hold contents are not changed This command will cause a transfer independent of any current operating configuration for the counter it will often be used as a software retrigger or as counter initialization prior to active hardware gating If a LOAD or LOAD AND ARM command is executed during the cycle preceding TC the counter will go immediately to TC This occurs because the LOAD operation is performed by generating a pseudo count pulse internal to the Am9513A and the 9513 is expecting to go into TC on the next count pulse The reload source used to reload the counter will be the same as that which would have been used if the TC
67. Cs The code below lists a sample function that can be used to reset the Am9513A STCs on the PC TIO 10 In addition the code lists a sample function that can be used to generate a variable duty cycle square wave miscellaneous definitions define cmd port 0x0001 define data_port 0x0000 define no err 0 define range err 1 define stc a 0x0000 define stc_b 0x0002 define tio ba 0x01a0 function prototypes void main void void reset9513 unsigned int unsigned int int Square wave unsigned int unsigned int unsigned int unsigned long unsigned long support functions void reset9513 base address chip offset unsigned int base address chip offset unsigned int cmd data int ctr set up the register addresses cmd base address chip offset cmd port data base address chip offset data port National Instruments Corporation 4 9 PC TIO 10 User Manual Chapter 4 Programming reset the 9513 outp cmd Oxff reset the chip for ctr 1 ctr lt 5 ctr outp cmd ctr select Counter Mode Register outp data 0x00 store mode low byte outp data 0x00 store mode high byte outp emd ctr 8 select Counter Load Register outp data 0x03 store load low byte outp data 0x00 store load high byte outp cmd 0 5 load all counters int square wave base address counter timebase high time low time unsign
68. DAQ PC TIO 10 User Manual b f NATIONAL April 1999 Edition y INSTRUMENTS Part Number 371349 01 Worldwide Technical Support and Product Information www natinst com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 794 0100 Worldwide Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 011 284 5011 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 China 0755 3904939 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 India 91805275406 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico D F 5 280 7625 Mexico Monterrey 8 357 7695 Netherlands 0348 433466 Norway 32 27 73 00 Singapore 2265886 Spain Madrid 91 640 0085 Spain Barcelona 93 582 0251 Sweden 08 587 895 00 Switzerland 056 200 51 51 Taiwan 02 2377 1200 United Kingdom 01635 523545 For further support information see the Technical Support Resources appendix To comment on the documentation send e mail to techpubsenatinst com Copyright 1990 1999 National Instruments Corporation All rights reserved Important Information Warranty Copyright Trademarks The PC TIO 10 is warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at
69. E10 FOUT1 EXTIRQ1 GND AO A2 A4 AG BO B2 B4 B6 GATE1 SOURCE2 O AJN OUT2 8 GATE3 Oo wo 10 SOURCE4 12 OUT4 13 14 OUT5 15 16 GATE6 17 18 SOURCE7 19 20 OUT7 21 22 GATE8 23 24 SOURCE9 25 26 OUT9 27 28 OUT10 29 30 FOUT2 31 32 EXTRIQ2 33 34 45V 35 36 A1 37 38 39 40 5 41 42 43 44 B1 45 46 B3 47 48 B5 49 50 7 National Instruments Corporation Figure 2 6 PC TIO 10 1 0 Connector Pin Assignments 2 7 Configuration and Installation PC TIO 10 User Manual Configuration and Installation Signal Connection Descriptions Pins Signal Names Description 1 4 7 1 10 15 18 21 24 SOURCE 1 4 SOURCE lt 6 9 gt These are the source inputs for Counters through 4 and Counters 6 through 9 The source inputs for Counters 5 and 10 do not appear on the I O connector because they are internally connected to a 5 MHz clock 2 5 8 11 13 16 19 22 25 27 GATE lt 1 10 gt These are the gate inputs for Counters 1 through 10 3 6 9 12 14 17 20 23 26 28 OUT 1 10 These are the outputs for Counters 1 through 10 29 30 FOUT 1 2 These are the frequency outputs of the t
70. EST LOADS FIGURE E LOAD 00 07 50V PAO PA7 PBO PB7 CA2 CB2 RL 2 4 ko 5 0V Test Point 06150 iR 1 25 OF Ea MMD6150 c R Test Point oe Equi 190 pF 11 7 T MMD7000 or Equiv FIGURE 4 CMOS EQUIVALENT TEST LOAD PAO PA7 CA2 Test Point e 30 pF MMD7000 or Equiv 30 pF R2 12 FIGURE 5 NMOS EQUIVALENT TEST LOAD RG Only 5 0 V 1 5 KQ Test Point MOTOROLA MICROPROCESSOR DATA 3 1695 PC TIO 10 User Manual National Instruments Corporation FIGURE 6 PERIPHERAL DATA SETUP AND HOLD TIMES Reed Mode PAO PA7 P80 PB7 tpos PDM Enable FIGURE 8 CA2 DELAY TIME Read Mode CRA 5 1 CRA 3 CRA 4 0 Enable 1 N RS2 m CA2 FIGURE 10 PERIPHERAL DATA AND CB2 DELAY TIMES Write Mode CRB 5 3 1 CRB 4 0 Enable POW PBO PB t toc 2 CB2 goes low as a resuit of the positive transition of Enabie FIGURE 12 CB2 DELAY TIME Write Mode 5 1 CRB 3 CRB 4 0 Enable f te TE cB1 i ICB2 RS2 2 Assumes part was deselected during any previous E pulse Appendix D Motorola MC6821Data Sheet FIGURE 7 CA2 DELAY TIME Read Mode CRA 6 1 CRA 4 0 1 2 51 PWer CA2 Assumes part was deselected during the previous pulse FIGURE 9 PERIPHERAL CMOS DATA DELAY TIMES Write Mode CRA 5 CRA 3 1 CRA 4 0 I vec 30 FIGU
71. Figure 16 shows the bit assignments for the Counter Mode registers Alarm Registers and Comparators Added functions are available in the Counter Logic Groups for Counters 1 and 2 see Figure 4 Each contains a 16 bit Alarm register and a 16 bit Comparator When the value in the counter reaches the value in the Alarm register the Compara tor output will go true The Master Mode register contains control bits to individually enable disable the comparators When enabled the comparator output appears on the OUT pin of the associated counter in place of the normal counter output The output will remain true as long as the comparison is true that is until the next input causes the count to change The polarity of the Comparator output will be active high if the Output Control field of the Counter Mode register is 001 or 010 and active low if the Output Controi field is 101 MASTER MODE CONTROL OPTIONS The 16 bit Master Mode MM register is used to control those internal activities that are not controlled by the individual Counter Mode registers This includes frequency control Time of Day operation comparator controls data bus width and data pointer sequencing Figure 11 shows the bit assign ments for the Master Mode register This section describes the use of each control field Master Mode register bits MM12 MM13 and MM14 can be individually set and reset using commands issued to the Command register In addition they can ail be ch
72. Input DF001913 FOUT Source Master Mode bits MM4 through MM7 specify the source input for the FOUT divider Fifteen inputs are available for selection and they include the five Source pins the five Gate pins and the five internal frequencies derived from the oscillator The 16th combination of the four control bits all zeros is used to assure that an active frequency is available at the input to the FOUT divider following reset FOUT Divider Bits MMB through MM11 specify the dividing ratio for the FOUT Divider The FOUT source selected by bits MM4 through MM7 is divided by an integer value between 1 and 16 inctusive and is then passed to the FOUT output buffer After power on or reset the FOUT divider is set to divide by 16 FOUT Gate Master Mode bit MM12 provides a software gating capability for the FOUT signal When MM12 1 FOUT is off and in a low impedance state to ground MM12 may be set or cleared in conjunction with the loading of the other bits in the Master Mode register alternatively there are commands that allow MM12 to be individually set or cleared directly without chang ing any other Master Mode bits After power up or reset FOUT is gated on When changing the FOUT divider ratio or FOUT source transient pulses as short as haif the period of the FOUT source may appear on the FOUT pin Tuming the FOUT gate on or off can aiso generate a transient This should be Alarm 1 and Counter 1 considered when u
73. LED A AT xA h 5 37 o He 35 Do 50 49 TTL Signal 9 48 Port B o B lt 7 4 gt 47 5 lt WW M Switch 33 GND 7S 10 Figure 2 10 Digital 1 0 Connections In Figure 2 10 port A is configured for digital output and port B is configured for digital input Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch in Figure 2 10 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 2 10 Power Connections Pin 34 of the I O connector is connected to the 5 V supply from the PC power supply This pin is referenced to GND and can be used to power external digital circuitry For more information on this output pin see Output Signal Specifications in Appendix A Specifications Power Rating 1 0 A at 5 V 10 UN Caution Under no circumstances should this 5 V power pin be connected directly to ground or to any other voltage source on the PC TIO 10 or any other device Doing so may damage the PC TIO 10 and the PC National Instruments is not liable for damage resulting from such a connection National Instruments Corporation 2 15 PC TIO 10 User Manual Chapter 2 Configuration and Installation Cabling The PC TIO 10 digital I O con
74. No Hardware Gating Ds 9 Tx LX 150 9 9 x Ex LX L Wa ARM TC TOGGLED OUTPUT Am9513A National Instruments Corporation CE ANINI NIN SINASI Nd Ni Ns COMMAND COUNT VALUE s Xe i OUTPUT DROITE a Ee Figure 15a Mode A Waveforms AMD Am9513A Data Sheet Appendix C Mode A shown in Figure 15a is one of the simplest operating modes The counter will be available for counting source edges when it is issued an ARM command On each TC the counter will reload from the Load register and automaticaily disarm itself inhibiting further counting Counting will resume when a new ARM command is issued MODE B Software Triggered Strobe with Levei Gating xe Px x x x Loe ojojx x xy xy x J Mode B shown in Figure 15b is identical to Mode A except that source edges are counted only when the assigned Gate is active The counter must be armed before counting can occur Once armed the counter will count all source edges which occur while the Gate is active and disregard those edges which occur while the Gate is inactive This permits the Gate to turn the count process on and off On each TC the counter will reioad from the Load register and automatically disarm itself inhibiting further counting uniti a new ARM command is issued GIVEN 2 129 C 15 PC TIO 10 User Manual Appendix C AMD Am9513A Data Sheet WF004600 Figure 15b Mode B Wa
75. OTOROLA MICROPROCESSOR DATA PC TIO 10 User Manual 3 1699 D 9 National Instruments Corporation Appendix D Motorola MC6821Data Sheet MC6821 Control of CA1 and CB1 Interrupt Input Lines CRA 0 enable the MPU interrupt signals IRGA and respec CRB 0 CRA 1 and CRB 1 The two lowest order bits of tively Bits CRA 1 and CRB 1 determine the active transition the control registers are used to control the interrupt input of the interrupt input signals CA1 and CB1 lines CA1 and C81 Bits CRA O and CRB O are used to FIGURE 17 PORT A AND PORT B EQUIVALENT CIRCUITS Port A Port B Port Pin DATA Data Direction 1 Output Pin Data Direction 0 einput Pin 0 Input Pin 1 Output Pin Read A Data ead ae 8 in Input or iiim Output Mode in Input Mode Internal PIA Bus ORDERING INFORMATION MC68A21CP Motorola Integrated Circuit M6800 Family Blanks 1 0 MHz A 1 5 MHz B 2 0 MHz Device Designation In M6800 Family Temperature Range Blank 0 70 C C 40 86 C Package Plastic S Cerdip L Ceramic BETTER PROGRAM Better program processing is available on ail types listed Add suffix letters to part number Level 1 S 2 add D Level 3 add DS Level 1 S 10 Temp Cycles i 25 to 150 C Hi Temp testing at TA max Level 2 D 168 Hour Burn in at 125 C Level 3 DS Combination of Level
76. RE 11 CB2 DELAY TIME Write Mode CRB 5 CRB 3 1 CRB 4 0 Enable ca2 RS3 PWer c8 Assumes part was deselected during the previous E pulse FIGURE 13 INTERRUPT PULSE WIDTH AND RESPONSE cime CA1 2 c81 2 8 M trsa 4 Assumes Interrupt Enable Bits are set Note Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 0 volts unless otherwise noted MOTOROLA MICROPROCESSOR DATA National Instruments Corporation PC TIO 10 User Manual Appendix D Motorola MC6821Data Sheet MC6821 FIGURE 14 TRO RELEASE TIME FIGURE 15 RESET LOW TIME TRL Enable RESET UR mS The RESET line must be a for a minimum of 1 0 us before addressing the PIA Note Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 0 voits unless otherwise noted FIGURE 16 EXPANDED BLOCK DIAGRAM 40 Roa Interrupt Status Contro A 39 CA2 Control Register A DO 33 CRA 32 Data Direction on 31 Register A DDRA 30 QA 29 Output Bus 05 28 06 27 2 PAO LC 1 ORA SPA Peripheral 5 interface 6 PAG A e 7 PAS Bus Input D Register bo e 8 PAS BIR amp m 9 PA7 vec Pin 20 PBO vss Pint ees nae eal P82 cso 22 Peripherat 13 P83 Interface 1 24 PBa ESZ 23
77. S Power Ossipaton CT TP 59 BUS TIMING CHARACTERISTICS See Notes and 2 30 DERE Pewne 29 129 Giock fice and L5 L Adaress Hod Tei tw Address Setup Time Below E 1a Chip Select Soup TmeBeoet o o 5 ptweSeexrodTme 39 18 Read Data Hod Time 1 1 toga 20 0 20 90 20 5 s m Hod Tine ww 9 fe Output Data Delay Time 290 580 90 ms input Bata Sup me 5 9 9 The data bus output buffers no longer sourcing or sinking current by topHAMax High Impedance FIGURE 1 BUS TIMING R W Address Non Muxed Read Data MPU Read Data Non Muxed Non Muxed Write Data MPU Write Data Non Muxed Non Muxed Notes 1 Voltage levels shown are V 50 4 V VQ z 2 4 V unless otherwise specified 2 Measurement points shown are 0 8 V and 2 0 V unless otherwise specified MOTOROLA MICROPROCESSOR DATA 3 1694 D 4 PC TIO 10 User Manual Appendix D Motorola MC6821Data Sheet MC6821 PERIPHERAL TIMING CHARACTERISTICS Vcc 5 0 V 5 Vgg 0 V TA TL to TH Characteristic unless otherwise specified Data Setup Time Da
78. _ _ _ _ NAAA AAAA AAAA AAAA cae TASU ez etd S NEG SERE WF004740 Figure 15r Mode R Waveforms MODE S MODE V RELOAD SOURCE Frequency Shift Keying wr owe ous ows ows om owe ows T owe wo owe owi owo L bslslxixlilxixixj Mode V shown in Figure 15v provides frequency shift keying Gate COUNT VALUE oureut OureuT In this mode the reload source for LOAD commands irre spective of whether the counter is armed or disarmed and for TC initiated reloads is determined by the Gate input The Gate input in Mode S is used only to select the reload source not to start or modulate counting When the Gate is Low the Load register is used when the Gate is High the Hold register is used Note the Low Load High Hold mnemonic convention Once armed the counter will count to TC twice and then disarm itself On each TC the counter will be reloaded from the reload source selected by the Gate Following the second TC an ARM command is required to start a new counting cycle Mode S is shown in Figure 15s oi Am9513A 2 138 PC TIO 10 User Manual modulation capability Gate operation in this mode is identical to that in Mode S If the Gate is Low a LOAD command or a TC induced
79. able E 1 since it is reserved for system use Table E 1 Switch Settings with Corresponding Base 1 0 Address and Base 1 0 Address Space Switch Setting Base I O Base I O Address Space A9 A8 A7 A6 5 4 Address hex Used hex 0 1 0 0 0 0 0 100 100 107 0 1 0 0 0 0 1 108 108 10F 0 1 0 0 0 1 0 110 110 117 0 1 0 0 0 1 1 118 118 11F 0 1 0 0 1 0 0 120 120 127 0 1 0 0 1 0 1 128 128 12F 0 1 0 0 1 1 0 130 130 137 0 1 0 0 1 1 1 138 138 13F 0 1 0 1 0 0 0 140 140 147 0 1 0 1 0 0 1 148 148 14F 0 1 0 1 0 1 0 150 150 157 0 1 0 1 0 1 1 158 158 15F 0 1 0 1 1 0 0 160 160 167 0 1 0 1 1 0 1 168 168 16F 0 1 0 1 1 1 0 170 170 177 National Instruments Corporation E 1 PC TIO 10 User Manual Appendix E Switch Settings Table E 1 Switch Settings with Corresponding Base 1 0 Address and Base 1 0 Address Space Continued Switch Setting Base I O Base I O Address Space A9 A8 A7 A6 5 4 Address hex Used hex 0 1 0 1 1 1 1 178 178 17F 0 1 1 0 0 0 0 180 180 187 0 1 1 0 0 0 1 188 188 18F 0 1 1 0 0 1 0 190 190 197 0 1 1 0 0 1 1 198 198 19F 0 1 1 0 1 0 0 1A0 1A0 1A7 0 1 1 0 1 0 1 1A8 1A8 0 1 1 0 1 1 0 1B0 1 0 1B7 0 1 1 0 1 1 1 1B8 1B8 1BF 0 1 1 1 0 0 0 100 1C7 0 1 1 1 0 0 1 1C8 1C8 ICF 0 1 1 1 0 1 0 1D0 1 0 107
80. acturer data sheet for the AMD Am9513A integrated circuit Advanced Micro Devices Inc This circuit is used on the PC TIO 10 board Copyright O Advanced Micro Devices Inc 1989 Reprinted with permission of copyright owner All rights reserved Advanced Micro Devices Inc 1990 Data Book Personal Computer Products Processors Coprocessors Video and Mass Storage National Instruments Corporation C 1 PC TIO 10 User Manual Appendix C 2 116 AMD 9513 Data Sheet Am9513A System Timing Controller FINAL Five independent 16 bit counters High speed counting rates Up down and binary BCD counting Internal oscillator frequency source Tapped frequency scaler Programmabie frequency output 8 bit or 16 bit bus interface Time of day option Alarm comparators on counters 1 and 2 The Am9513A System Timing Controller is an LSI circuit designed to service many types of counting sequencing and timing applications It provides the capability for pro grammabie frequency synthesis high resolution program mabie duty cycle waveforms retriggerable digital one shots time of day clocking coincidence alarms complex pulse generation high resolution baud rate generation frequency shift keying stop watching timing event count accumulation waveform analysis etc A variety of program operating modes and control features allows the 9513 to be personalized for particular applicat
81. al Instruments products whenever National Instruments products are incorporated in a system or application including without limitation the appropriate design process and safety level of such system or application Contents About This Manual Introduction to the PC TIO 10 ix Conventions ote ie I Ra I a HE ix Related Docuimentatiotn tee eaae due Chapter 1 Introduction What Your Kit Should Contain sss nennen enne 1 2 Optional Software adea at sti P RETE Ha a re RR Eu niet 1 2 National Instruments Application Software sese 1 2 NEDAGO Drivet SoftWate 1 3 Optional Equipment gott ettet 1 3 p M 1 4 Chapter 2 Configuration and Installation Board Configuration acie tg e epp tap n cheer tpi eiie 2 1 Interrupt Level Selection 2 eee eR 2 4 Local Interrupt Selection eee the net ertt 2 5 Installation Dem t ene eet m tet e e 2 6 Signal ConnectioDs oS Ubera et 2 6 Connector Pin Description eesseeeeseeeeeeneeneee enne 2 7 Signal Connection Descriptions seseseseeeeeeeeenee en eene enne 2 8 Timing Signal Connections eet PREIS 2 9 Digital I O Signal Connections 2 13 Power Connections i oe apod eme Ee HE ae 2 15 Cabin
82. al data buses and four interrupt control lines for interfacing to peripheral devices Section A Peripheral Data PAO PA7 Each of the peripheral data lines can be programmed to act as an input or output This is accomplished by setting a 1 in the cor responding Data Direction Register bit for those lines which are to be outputs A 0 in a bit of the Data Direction Register causes the corresponding peripheral data line to act as an input During an MPU Read Peripheral Data Operation the data on peripheral lines programmed to act as inputs ap pears directly on the corresponding MPU Data Bus lines In the input mode the internal pullup resistor on these lines represents a maximum of 1 5 standard TTL loads The cata in Output Register A will appear on the data lines that are programmed to be outputs A logicai 1 written in to the register will cause a high on the corresponding data line while a 0 results in a low Data in Output Register may be read by an MPU Read Peripheral Data operation when the corresponding lines are programmed as outputs This data will be read properly if the voltage on the peripheral data lines is greater than 2 0 volts for a logic 1 output and less than 0 8 volt for a logic 0 output Loading the output lines such that the voltage on these lines does not reach full voltage causes the data transferred into the MPU on a Read operation to differ from that contained in
83. al timing requirements 2 12 to 2 13 specifications and ratings for Am9513A T O signals 2 11 to 2 12 time lapse measurement 2 10 timing I O connector 3 3 timing signals 2 9 to 2 12 U unpacking PC TIO 10 1 4 W Web support from National Instruments F 1 to F 2 online problem solving and diagnostic resources F 1 software related resources F 2 Worldwide technical support F 2 National Instruments Corporation
84. ance processor to repeat instructions without requiring time to branch to the beginning of the instructions zero wait state memory memory fast enough that the processor does not have to wait during any reads and writes to the memory National Instruments Corporation G 17 PC TIO 10 User Manual Index Numbers 5 V signal connection to pin 34 through protection fuse F1 3 3 description table 2 8 A lt 0 7 gt signals description table 2 8 digital I O connections 2 13 address lines A9 through AO 2 2 Am9513A Command Registers 4 4 Am9513A Data Registers 4 3 Am9513A Status Registers 4 5 Am9513A System Timing Controller data sheet C 1 to C 40 programming considerations 4 8 register map 4 2 specifications and ratings for I O signals 2 11 to 2 12 theory of operation 3 2 lt 0 7 gt signals description table 2 8 digital I O connections 2 13 base I O address default settings 2 2 default settings for National Instruments products table 2 3 to 2 4 example settings table 2 3 factory settings table 2 2 switch settings with corresponding base I O address and base I O address space table E 1 to E 5 National Instruments Corporation bits BYTE POINTER 4 5 lt 7 0 gt 4 4 D lt 7 0 gt 4 3 4 6 D lt 15 8 gt 4 3 DRS 4 7 EDGE 4 7 INTEN 4 8 IRQ 4 7 OUT lt 5 1 gt 4 5 board configuration See configuration BYTE POINTER bit 4 5 C C lt 7 0 gt bi
85. andard Architecture propagating a signal by means of a varying electric field equivalent time sampling the current used to excite a device to produce a voltage to be measured an onboard EEPROM that may contain device specific initialization and system boot functionality National Instruments Corporation G 5 PC TIO 10 User Manual Glossary F false triggering fetch and deposit filtering flash ADC floating signal sources flyby FPGA FSK gain gain accuracy glitch amp rms PC TIO 10 User Manual triggering that occurs at an unintended time a data transfer in which the data bytes are transferred from the source to the controller and then from the controller to the target a type of signal conditioning that allows you to filter unwanted signals from the signal you are trying to measure an ADC whose output code is determined in a single step by a bank of comparators and encoding logic signal sources with voltage signals that are not connected to an absolute reference or system ground Also called nonreferenced signal sources Some common example of floating signal sources are batteries transformers or thermocouples a type of high performance data transfer in which the data bytes pass directly from the source to the target without being transferred to the controller field programmable gate array frequency shift keying the factor by which a signal is amplified sometimes expressed in decibels a
86. anged by writing directly to the Master Mode register After power on reset or a Master Reset command the Master Mode register is cleared to an all zero condition This results in the following configuration Time of Day disabled Both Comparators disabled FOUT Source is frequency F1 FOUT Divider set for divide by 16 FOUT gated on Data Bus 8 bits wide Data Pointer Sequencing enabled Frequency Scaler divides in binary 2 125 C 11 AMD Am9513A Data Sheet PC TIO 10 User Manual Appendix C AMD Am9513A Data Sheet POUT Divider 0000 Olvide by 16 0001 by 1 0010 Olvide by 2 0011 Olvide by 3 0100 by 4 0101 Olvide by 5 0110 Oide by 6 0111 Olvide dy 7 1000 Divide by 8 1001 Divide by 9 1010 Divide by 10 1011 Olvide by 11 1100 Olvide by 12 1101 eue 1110 Olvide by 14 1111 Divide by 15 Es T FOUT On 1 FOUT OR Low Z to GNO Bus Width 0 8 Bit Bus 1 16 8 Bus Date Pointer Control 0 Enable increment 1 Disable increment Senter Controt 0 Binary Division 1 BCD Division Time of Day Bits and MM1 of the Master Mode register specify the Time ot Day TOD options When 0 and MM1 0 the special logic used to implement TOD is disabled and Count ers 1 and 2 will operate in exactly the same way as Counters 3 4 and 5 When MMO 1 or MM1 1 additional counter decoding and controi logic is enabled on Counters 1 and 2 which c
87. anual C 34 Am9513A National Instruments Corporation Appendix C AMD Am9513A Data Sheet SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Note 1 ummm tren mee Ds ir e wm GBvadis Redi G7 Vat to Wwe Hgn 39 X en 3 EA S High to X2 Low R2 High Pulse Wm Note 1j 22 79 7 x2 Low X2 High X2 Lom Pulse With Note a 2 1 m in Vaid fo We High Count Source High to Count Sowce High Source Time Note 22 345 jns soe oe 7 Count Source High to FOUT Valid Note 7 22 500 ns _TEHGV Count Source High to Gate Valid Level Gating Hold Time Notes 7 9 10 2 TEHRL Count Source High to Read Low Set up Time Notes 2 7 2t 1 __TEHWH Count Source High to Write High Set up Time Notes 3 7 a 100 TC STC utp 3 tC Out Count Source High to Out Valid Note 7 immediate or Delayed Toggle Outpt 2 FN High to FN 1 Valid Note 11 D ns L jJ Gate Valid to Count Source High Level Gating Setup Time Notes 7 9 10 22 o ns Gate Vaid to Gate Valid Gate Pulse Duration Notes 8 10 O O 22 14s
88. ardware products and utility routines Worldwide Support National Instruments has offices located around the globe Many branch offices maintain a Web site to provide information on local services You can access these Web sites from www natinst com worldwide If you have trouble connecting to our Web site please contact your local National Instruments office or the source from which you purchased your National Instruments product s to obtain support For telephone support in the United States dial 512 795 8248 For telephone support outside the United States contact your local branch office Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 011 284 5011 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 China 0755 3904939 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 India 91805275406 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico D F 5 280 7625 Mexico Monterrey 8 357 7695 Netherlands 0348 433466 Norway 32 27 73 00 Singapore 2265886 Spain Madrid 91 640 0085 Spain Barcelona 93 582 0251 Sweden 08 587 895 00 Switzerland 056 200 51 51 Taiwan 02 2377 1200 United Kingdom 01635 523545 PC TIO 10 User Manual F 2 National Instruments Corporation Glossary Prefix Meaning Value n nano 10 9 u micro 10 6 m milli 10 3 k kilo 1
89. ational Instruments Corporation E 3 PC TIO 10 User Manual Appendix E Switch Settings Table E 1 Switch Settings with Corresponding Base 1 0 Address and Base 1 0 Address Space Continued Switch Setting Base I O Base I O Address Space A9 8 7 A6 5 4 Address hex Used hex 1 0 1 1 1 1 1 2F8 2F8 2FF 1 1 0 0 0 0 0 300 300 307 1 1 0 0 0 0 1 308 308 30F 1 1 0 0 0 1 0 310 310 317 1 1 0 0 0 1 1 318 318 31F 1 1 0 0 1 0 0 320 320 327 1 1 0 0 1 0 1 328 328 32F 1 1 0 0 1 1 0 330 330 337 1 1 0 0 1 1 1 338 338 33F 1 1 0 1 0 0 0 340 340 347 1 1 0 1 0 0 1 348 348 34F 1 1 0 1 0 1 0 350 350 357 1 1 0 1 0 1 1 358 358 35F 1 1 0 1 1 0 0 360 360 367 1 1 0 1 1 0 1 368 368 36F 1 1 0 1 1 1 0 370 370 377 1 1 0 1 1 1 1 378 378 37 1 1 1 0 0 0 0 380 380 387 1 1 1 0 0 0 1 388 388 38F 1 1 1 0 0 1 0 390 390 397 1 1 1 0 0 1 1 398 398 39F 1 1 1 0 1 0 0 3A0 3A7 1 1 1 0 1 0 1 3A8 3AF 1 1 1 0 1 1 0 3B0 3B7 PC TIO 10 User Manual E 4 National Instruments Corporation Appendix E Switch Settings Table E 1 Switch Settings with Corresponding Base 1 0 Address and Base 1 0 Address Space Continued Switch Setting Base I O Base I O Address Space A9 A8 A7 A6 5 4 Address hex Used hex 1 1 1 0 1 1
90. auses their decades to tum over at the counts that generate appropriate 24 hour TOD accumulations For addi tional information see the Time of Day chapter in the 9513A System timing controller technical manual Comparator Enabie Bits MM2 and MM3 control the Comparators associated with Counters 1 and 2 When a Comparator is enabled its output is substituted for the normal counter output on the associated OUT1 or OUT pin The comparator output will be active high if the output control fieid of the Counter Mode register is 001 or 010 and active low for a code of 101 Once the compare output is true it will remain so until the count changes and the comparison therefore goes false The two Comparators can always be used individually in any operating mode One special case occurs when the Time of Day option is revoked and both Comparators are enabled The operation of 2 will then be conditioned by Comparator 1 so that a fuil 32 bit compare must be true in order to generate a true signal on OUT2 will continue as usual to reflect the state of the 16 bit comparison between Figure 11 Master Mode Register Bit Assignments FOUT Source 0000 E1 0001 SRC 1 0010 SRC 2 0011 SAC 0100 SAC 4 0101 SAC 5 0110 GATE 1 0111 GATE 2 1000 GATE 3 1001 GATE 4 1010 GATE 5 1011 F1 1100 F2 1101 F3 1110 F4 1111 F5 01 TOO Enabied 5 input 10 Enabled 6 input 11 TOD Enabled 10
91. base then the pulse width is equal to the counter value multiplied by the timebase period For time lapse measurement a counter is programmed to be edge gated An edge is applied to the counter GATE input to start the counter The counter can be programmed to start counting after receiving either a high to low edge or a low to high edge If the counter is programmed to count an internal timebase then the time lapse since receiving the edge is equal to the counter value multiplied by the timebase period To measure frequency a counter is programmed to be level gated and the rising or falling edges are counted in a signal applied to a SOURCE input The gate signal applied to the counter GATE input is of some known duration In this case the counter is programmed to count either rising or falling edges atthe SOURCE input while the gate is applied The frequency of the input signal is then the count value divided by the known gate period Figure 2 8 shows the connections for a frequency measurement application A second counter can also be used to generate the gate signal in this application 2 10 National Instruments Corporation Chapter 2 Configuration and Installation Counter SOURCE OUT ro GATE Signal Gate Source Source e a A GND Connector PC TIO 10 Board Figure 2 8 Frequency Measurement Applica
92. ble for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Under the copyright laws this publication
93. byte at a 2AmN Y time to and from the eight low order external data bus lines caren The Byte Pointer bit toggles with each byte transter in this er mode GaTewa Appendix C 1 DF001920 Figure 12 Gating Control Thus the host processor by controlling MM14 may repetitive ly read write a single intemal location or may sequentially read write groups of locations Bit MM14 can be loaded by writing to the Master Mode register or can be set or cleared by software command Seater Ratios Master Mode bit MM15 controis the counting configuration of the Frequency Scaler counter When 15 0 the Scaler divides the oscillator frequency in binary steps so that each subfrequency is 1 16 of the preceding frequency When MM15 1 the Scaler divides in BCD steps so that adjacent frequencies are related by ratios of 10 instead of 16 see Figure 13 22323 AF002541 AMD Am9513A Data Sheet BCD Binary Scaling Scaling Frequency MM15 1 MM15 0 F1 OSC osc F2 F1 10 F1 16 F3 F1 100 F1 256 F4 F1 1 000 Fi 4096 F5 F1 10 000 F1 65 536 Figure 13 Frequency Scaler Ratios Am9513A 2 127 National Instruments Corporation C 13 PC TIO 10 User Manual Appendix C AMD Am9513A Data Sheet Counter Mode A Special Gate CH7 olof olol L9 5 tr j s Repetition 5 o o 0 1 1 1 0 0 0 D 1 1 EDGE 000 LEVEL EDGE 000 LEvEL 000 LEVEL EDGE Count to
94. chip counter mode count of 65 536 goes to 0 count of 65 536 goes to 0 low time disarm the ctr select Mode Reg send mode low byte send mode high byte Select Load Reg send load low byte high time 8 send load high byte select Hold Reg send hold low byte low time 8 send hold high byte 1 load the ctr Set output high 1 arm the ctr PC TIO 10 User Manual Chapter 4 Programming xf start a 100 khz 70 duty cycle square wave on Counter 8 tio ba selects the board s base address 8 selects the counter 0x000b selects timebase F1 or 1 MHz 7L selects a high time of 7 psec 3L selects a low time of 3 usec a total of 10 psec cycle gives a 100 kHz wave 7 clocks high out of 10 clocks gives a 70 duty cycle Square wave tio ba 8 0x000b 7L 3L Interrupt Programming Example for the MC6821 PC TIO 10 User Manual The PC TIO 10 is configured so that EXTIRQ1 on the I O connector is connected to CA1 on the MC6821 EXTIRQ 2 on the I O connector is connected to CB1 on the MC6821 and CA2 and CB2 of the MC6821 are disabled The signal names CA1 CA2 CB1 and CB2 refer to the names of pins located on the MC6821 The names are given to clarify how the interrupt circuitry is connected on the MC6821 For more information on these signals see Appendix D Motorola MC6821Data Shee
95. ckwall filter that rejects signal energy above the Nyquist frequency 1 2 the sample rate of the DAC in order to suppress out of band images of the in band signal created by the D A conversion process to decrease the amplitude of a signal the factor by which a signal s amplitude is decreased the technique of internally shorting the internal circuit while disconnecting the measurement to compensate for temperature effects American Wire Gauge binary coded decimal a signal range that includes both positive and negative values for example 5 V to 5 V atype of switching contact that is completely disengaged from one terminal before it connects with another terminal the voltage high enough to cause breakdown of optical isolation semiconductors or dielectric materials See also working voltage a low pass filter having very flat passband a very sudden sharp transition region and high rejection in the stopband the voltage drop across the input section of the current mode a high speed data transfer in which the address of the data is sent followed by back to back data words while a physical signal is asserted G 2 National Instruments Corporation C C CalDAC capacitively coupled channel clock chromatograph CI circuit trigger clip CMRR code width cold junction compensation common mode range common mode signal common mode voltage Compact PCI compensation range National Instrumen
96. cond LOAD does not generate a TC reload sources alternate on TCs only not on LOAD commands Load and Arm Counters Description Any combination of counters as specified in the S field will be first loaded and then armed This command is equivalent to issuing a LOAD command and then an ARM command A LOAD AND ARM command which drives a counter to TC generates the same sequence of operations as execution of a LOAD command and then an ARM command In modes which disarm on TC Modes A C and N O and Modes G and S if the current TC is the second in the cycle the ARM part of the LOAD AND ARM command will re enable counting for another cycle In modes which alternate reload sources Modes L the ARMing operation will cause the next TC to retoad from the HOLD register irrespective of which reload source the current TC used This command should not be used during asynchronous operations Disarm Counters Description Any combination of counters as specified by the S field will be disabled from counting A disarmed counter will cease all counting independent of other conditions The only exception to this is that a counter in the TC state will always count once in order to leave TC before DISARMing This count may be generated by a source edge by a LOAD or LOAD AND ARM command the LOAD AND ARM command will negate the DISARM command or by a STEP command A disarmed counter may be updated using the LOAD command an
97. ction of this signal line is programmed with Control Register A Peripheral Control CB2 Peripheral Control line CB2 may also be programmed to act as an interrupt input or peripheral control output As an input this line has high in put impedance and is compatible with standard TTL As an output it is compatible with standard TTL and may also be used as a source of up to 1 milliampere at 1 5 volts to directly drive the base of a transistor switch This line is programmed by Control Register B INTERNAL CONTROLS INITIALIZATION A RESET has the effect of zeroing all PIA registers This wiil set PAO PA7 PBO PB7 CA2 and CB2 as inputs and all interrupts disabled The PIA must be configured during the restart program which follows the reset There are six locations within the PIA accessible to the MPU data bus two Peripheral Registers two Data Direction Registers and two Control Registers Selection of these locations is controlled by the RSO and RS1 inputs together with bit 2 in the Control Register as shown in Table 1 Details of possible configurations of the Data Direction and Contro Register are as follows TABLE 1 INTERNAL ADDRESSING Control Register Location Selected o o ox rernm Penes o 9 9 x See pressen Rewer DS o 9 x reenen tense 3 9 e o bee Ovecron Rene CE lxlewe e 9 E X Don t Care PORT A B HARDWARE CHARACTERISTICS As shown in Figu
98. d may be read using the SAVE command A count process may be resumed using an ARM command See the ARM command description for further details Save Counters Coding 1 0 1 S5 54 S3 S2 51 Description Any combination of counters as specified by S field will have their contents transferred into their associated Hold register The transfer takes place without interfering with any counting that may be underway This command will overwrite any previous Hold register contents The SAVE command is designed to allow an accumulated count to be preserved so that it can be read by the host CPU at some later time Disarm and Save Counters Am9513A National Instruments Corporation Appendix C Description Any combination of counters as specified by the S field will be disarmed and the contents of the counter will be transferred into the associated Hold registers This com mand is identical to issuing a DISARM command followed by a SAVE command Set TC Toggle Output Coding e C7 C8 C5 C4 C3 C2 Ci 1 1 1 0 1 N NI 00 lt N lt 101 Description The initial output level for TC Toggle mode is set HIGH for counter N selected by N4 N2 N1 001 Counter 1 thru 101 Counter 5 respectively This command conditions the TC Toggle flip flop see Figure 17 but does not appear at the counter output unless TC Toggle mode CM2 CM1 CMO 010 is selected Clear TC Toggle Output Coding C7 C5 C4 C2 C1
99. d remove isr is presented as follows Be sure to pass a 32 bit structure pointer to the PC TIO 10 User Manual 4 14 National Instruments Corporation Chapter 4 Programming install_isr function because the main program s data will probably be stored in a different memory segment than the one where the interrupt functions are located In addition if you call the installation function from a language besides C make sure the parameters are passed in the proper order C pushes parameters on the stack from right to left but most other languages most notably Pascal push parameters from left to right Finally be sure to make the calls to the functions using 32 bit addresses because all of the code assumes data is offset with respect to a 32 bit return address The code can be modified to use 16 bit addresses by changing far to near and decrementing all references to the base page register bp by two in install isr and remove isr only Do not modify isr handler Also isr handler should check service and clear both Port A and Port B interrupts before issuing the end of interrupt command If interrupts are still active when the end of interrupt command is issued program operation usually becomes unstable and is likely to lock up the computer assemble this file with the following command masm MX filename MX preserves case sensitivity function prototypes void install_isr int level isr_block_type far isr_b
100. de until the counter is disarmed When CMS 0 the count process will proceed only until one full cycie of operation occurs This may occur after one or two TC events The counter is then disarmed automatically The single or double TC requirement will depend on the state of other control bits Note that even if the counter is automatical ly disarmed upon a TC it always counts the count source edge which generates the trailing TC edge When TC occurs the counter is always reloaded with a value from either the Load register of the Hold register Bit CM6 specifies the source options for reloading the counter When CM6 0 the contents of the Load register will be transferred into the counter at every occurrence of TC When CM6 1 the counter reload location will be either the Load or Hold Register The reload location in this case may be controlled externally by using a Gate pin Modes S and V or may alternate on each TC Modes G through L With alternating sources and with the TC Toggled output selected the duty cycle of the output waveform is controlled by the relative Load and Hold values and very fine resolution of duty cycles ratios may be achieved Bit CM7 controis the special gating functions that allow retriggering and the selection of Load or Hold sources for counter reloading The use and definition of CM7 will depend Am9513A C 28 National Instruments Corporation on the status of the Gating Control field and bits
101. duct Name 4 W2 6 012 Figure 2 1 PC TIO 10 Parts Locator Diagram National Instruments Corporation 2 1 PC TIO 10 User Manual Chapter 2 Configuration and Installation PC TIO 10 User Manual Address lines A9 through AO are used to communicate with your PC TIO 10 Address lines A9 through A3 determine the address of the board within your computer system This address is called the base I O address whereas address lines A2 through AO are used by the PC TIO 10 to decode accesses to the onboard registers The positions of the switches at U12 as shown in Figure 2 1 determine the base I O address for your PC TIO 10 Each switch at U12 corresponds to one of the address lines A9 through A3 The switches at U12 are set at the factory to provide a base I O address of hex 1A0 With this default setting the PC TIO 10 uses the I O address space hex 1A0 through 1A7 Similarly the PC TIO 10 has a factory default setting of interrupt level 5 while its local interrupt setting is set to no connect and no connect The settings shown in Table 2 1 are suitable for most systems However if your system has other hardware at this base I O address or interrupt level you need to change these settings on the PC TIO 10 as described in the following pages or on the other hardware Table 2 1 PC TIO 10 Factory Set Switch and Jumper Settings Need Head Need Head Need Head Base I O Address Hex 1A0 factory setting U12 Int
102. e 188 YX AME qp NEP es ee I ee Ca E GINE WF004691 Figure 15k Mode K Waveforms MODE L Hardware Triggered Deiayed Puise One Shot eis oma cma wiz cm1 euro cmo cme emcee x Px xx x cms 2 cut ps cpu xix Mode L shown in Figure 151 is similar to Mode J except that counting will not begin until a Gate edge is applied to an armed counter The counter must be armed before application of the triggering Gate edge Gate edges applied to a disarmed counter are disregarded The counter will start counting source edges after the triggering Gate edge and counting will proceed until the second TC Note that after application of a triggering Gate edge the Gate input will be disregarded for the remainder of the count cycle This differs from Mode K where the gate can be modulated the count cycle to stop and start the counter On the first TC after application of the triggering Gate edge the counter will be reloaded from the Hold register On the second TC the counter wiil be reloaded from the Load register and counting will stop until a new gate edge is issued to the counter Note that unlike Mode K new Gate edges are required after every second TC to continue counting Software Triggered Strobe with Level Gating and Hardware Retriggering x cus
103. e Control Registers Two Programmable Data Direction Registers Four Individually Controlled Interrupt input Lines Two Usable as Peripheral Control Outputs Handshake Contro Logic for Input and Output Peripheral Operation High Impedance Three State and Direct Transistor Drive Peripheral Lines Program Controlled Interrupt and Interrupt Disable Capability CMOS Orive Capability on Side A Peripheral Lines Two TTL Drive Capability on All A and Side Buffers TTL Compatible Static Operation This document contains information on a new product Specifications and information herein are subject to change without notice MOTOROLA MICROPROCESSOR DATA 3 1692 National Instruments Corporation D 2 PC TIO 10 User Manual Appendix D Motorola MC6821Data Sheet MC6821 MAXIMUM RATINGS _ Characteristics T Symbol Value Unit This device contains circuitry to protect the cu Voltage tu RR RR o3to 70 v inputs against damage due to high static input Voltage ig 03to 70 voltages or electric fields however it is ad Temperature Range TL to TH vised that normal precautions be taken to MC6821 MC68A21 MC68B21 TA 0 to70 C avoid applications of any voltage higher than MC6821C MC68A21C 40 to 85 maximum rated voltages to this high impedance circuit For proper operation it is recommended that Vin and Voy be con strained to the range VsssiVi or Vout VCC Unused inputs must always be tied
104. e and the setpoint differential mode an analog input consisting of two terminals both of which are isolated from computer ground whose difference is measured G 4 National Instruments Corporation differential measurement system digital trigger DIN dithering DMA DNL DRAM DSP dual access memory dual ported memory dynamic range E ECL EGA EISA electrostatically coupled ETS excitation current expansion ROM Glossary a way you can configure your device to read signals in which you do not need to connect either input to a fixed reference such as the earth or a building ground a TTL level signal having two discrete levels a high and a low level Deutsche Industrie Norme the addition of Gaussian noise to an analog input signal direct memory access differential nonlinearity a measure in least significant bit of the worst case deviation of code widths from their ideal value of 1 LSB dynamic RAM digital signal processing memory that can be sequentially accessed by more than one controller or processor but not simultaneously accessed Also known as shared memory memory that can be simultaneously accessed by more than one controller or processor the ratio of the largest signal level a circuit can handle to the smallest signal level it can handle usually taken to be the noise level normally expressed in decibels emitter coupled logic enhanced graphics adapter Extended Industry St
105. e lines are open drain no load device on the chip This permits all interrupt request lines to be tied together in a wire OR configuration Each Interrupt Request line has two internal interrupt flag bits that can cause the Interrupt Request line to go low Each flag bit is associated with a particular peripheral interrupt line Also four interrupt enable bits are provided in the PIA which may be used to inhibit a particular interrupt from a peripheral device Servicing an interrupt by the MPU may be accomplished by a software routine that on a prioritized basis sequentially reads and tests the two control registers in each PIA for in terrupt flag bits that are set The interrupt flags are cleared zeroed as a result of an MPU Read Peripheral Data Operation of the corresponding data register After being cleared the interrupt flag bit can not be enabled to be set until the PIA is deselected during an E pulse The E pulse is used to condition the interrupt control lines CA1 CA2 CB1 CB2 When these lines are used as interrupt inputs at least one E pulse must occur from the in active edge to the active edge of the interrupt input signal to condition the edge sense network If the interrupt flag has been enabled and the edge sense circuit has been properly conditioned the interrupt flag will be set on the next active transition of the interrupt input pin PIA PERIPHERAL INTERFACE LINES The PIA provides two 8 bit bidirection
106. e resistance of which can be manually adjusted used for manual adjustment of electrical circuits and as a transducer for linear or rotary position the technique used on a DAQ board to keep a continuous buffer filled with data so that when the trigger conditions are met the sample includes the data leading up to the trigger condition a control action with an output that is to be proportional to the deviation of the controlled variable from a desired setpoint the exact sequence of bits characters and control codes used to transfer data between computers and peripherals through a communications channel such as the GPIB bus a device that detects the presence of an object without physical contact Most proximity sensors provide a digital on off relay or digital output signal PCI eXtensions for Instrumentation an open specification that builds on the CompactPCI specification by adding instrumentation specific features the inherent uncertainty in digitizing an analog value due to the finite resolution of the conversion process a device that maps a variable from a continuous distribution to a discrete distribution to modify the glitches in a signal in order to make them less disruptive a measure in LSB of the accuracy of an ADC It includes all nonlinearity and quantization errors It does not include offset and gain errors of the circuitry feeding the ADC the smallest signal increment that can be detected by a measurement system
107. e uidisse enne deuote ets te a A ete t dep edere tn 2 16 Chapter 3 Theory of Operation Data Transcelvers 2 5 a eb t e pete het ed te meret 3 2 PC I O Channel Control Circuitry eese eene nne rennen rennen 3 2 Am9513A System Timing Controller essere 3 2 MC6821 Peripheral Interface Adapter eee eeceeseeseeneceseeseeesecaeeesesseeeseseeeeaeeeaes 3 2 Interr pt Control csc rt er t etd ERES 3 3 Timing and Digital I O Connector essere renes 3 3 National Instruments Corporation V PC TIO 10 User Manual Contents Chapter 4 Programming Introduction eeu mte eed eto egi 4 1 Resister Map us Ero ER e DERE et HORE re S NUES 4 2 Register Descriptions eret tret tret Eee gei et rene ceri ped ete Ehe ehe 4 2 Register Descriptions for the Am9513A 4 2 Am9513A Data R gisterS eostn oiar T 4 3 Am9513A Command Registers esse 4 4 Am9513A Status Registers esses 4 5 Register Descriptions for the MC6821 sss 4 6 MC6821 Data Registers esee emen eene 4 6 MC6821 Control REgist rS sesir a ee 4 7 Programming Considerations for the Am9513A STUCs sse 4 8 Programming Example for the Am9513A STCs sss 4 9 Interrupt Programming Example for the MC6821 sess 4 12 Appendix A Specifications Appendix B 1 0 Connector Appendix C AMD Am9513A Data Sheet Appendi
108. e value of the input voltage over a given time interval scanning method where there is a longer interval between scans than there is between individual channels comprising a scan output current Industry Standard Architecture a type of signal conditioning in which you isolate the transducer signals from the computer for safety purposes This protects you and your computer from large voltage spikes and makes sure the measurements from the DAQ device are not affected by differences in ground potentials the voltage that an isolated circuit can normally withstand usually specified from input to input and or from any input to the amplifier output or to the computer bus constructed to maintain constant temperature across area Isothermal construction of terminal blocks increases thermocouple measurement accuracy 1 000 samples G 8 National Instruments Corporation L linearity linearization low frequency corner LSB MBLT MFLOPS MIO MIPS MITE MSB MTBF MTTR National Instruments Corporation G 9 Glossary the adherence of device response to the equation R KS where R response S stimulus and K a constant a type of signal conditioning in which software linearizes the voltage levels from transducers so the voltages can be scaled to measure physical phenomena in an AC coupled circuit the frequency below which signals are attenuated by at least 3 dB least significant bit meters
109. ected a cycle will be repeated as soon as another Gate edge occurs With repetition selected any Gate edge applied after TC goes active will start a new count cycle Edge gating is useful when implementing a digital single shot since the gate can serve as a convenient firing trigger A 001 code in this field selects the TC not TOGGLE output from the adjacent lower numbered counter as the gate This is useful for synchronous counting when adjacent counters are concatenated COMMAND DESCRIPTIONS The command set for the Am9513A allows the host processor to customize and manage the operating modes and features for particular applications to initialize and update both the internal data and control information and to manipulate operating bits during operation Commands are entered direct ly into the 8 bit Command register by writing into the Control port see Figure 6 All available commands are described in the following text Figure 19 summarizes the command codes and includes a brief description of each function Figure 20 shows all the unused code combinations unused codes should not be entered into the Command register since undefined activities may occur Six of the command types are used for direct software control of the counting process and they each contain a 5 bit S field In a linear select fashion each bit in the S field corresponds to one of five general counters S1 Counter 1 52 Counter 2 etc When an S bit is a
110. ed int base address counter timebase unsigned long high time low time unsigned int cmd data mode check ranges if counter lt 1 counter gt 10 timebase gt 15 high time 1L high time gt 65536L low time lt 11 1ow time gt 655361 return range err set up the register addresses cmd base address counter gt 5 stc b stc a cmd port data base address counter gt 5 stc b stc a data port PC TIO 10 User Manual 4 10 National Instruments Corporation Chapter 4 Programming adjust some parameters and program the counter if counter gt 5 counter 5 mode 0x0062 timebase lt lt 8 if high_time 65536L high time OL if low_time 65536L hes low time OL ys outp cmd 0xcO 0x01 lt lt counter 1 outp cmd counter outp data mode outp data mode gt gt 8 outp cmd counter 0x08 outp data unsigned int high time outp data unsigned int outp cmd counter 0x10 outp data unsigned int outp data unsigned int outp cmd 0x40 0x01 lt lt outp cmd 0xe8 counter outp cmd 0x20 0x01 lt lt return no err the main function void main reset both 9513s reset9513 tio ba stc a reset9513 tio ba stc b National Instruments Corporation 4 11 counter counter 5 ctrs per
111. enables the input buffers and data is transferred from the MPU to the PIA on the E signal if the device has been selected A high on the read write line sets up the PIA for a transfer of data to the bus The PIA output buffers are enabled when the proper ad dress and the enable puise E are present RESET The active low RESET line is used to reset all register bits in the PIA to a logical zero low This line can be used as a power on reset and as a master reset during system operation Chip Selects CS0 CS1 CS2 These three input Signals are used to select the PIA CSO and CS1 must be high and CSZ must be low for selection of the device Data transfers are then performed under the control of the enable and read write signals The chip select lines must be stable for the duration of the E pulse The device is deselected when any of the chip selects are in the inactive state Register Selects RSO and RS1 The two register select lines are used to select the various registers inside the PIA These two lines are used in conjunction with internal Control Registers to select a particular register that is to be written or read The register and chip select lines should be stable for the duration of the E pulse while in the read or write cycle Interrupt Request IRQA and IRQB The active low In terrupt Request lines IRQA and iRQB act to interrupt the MPU either directly or through interrupt priority circuitry Thes
112. ent surges and to provide low impedance discharge paths for voitages beyond the normal operating levels Note howev er that input energy levels can nonetheless be too high to be Successfully absorbed Conventional design storage and handling precautions should be observed so that the protec tion networks themselves are not overstressed Within the limits of normal operation the input protection circuitry is inactive and may be modeled as a lumped series RC as shown in Figure 3 a The functionally active input connection during normai operation is the gate of a MOS transistor No active sources or drains are connected to the inputs so that neither transient nor steady state currents are impressed on the driving signals other than the charging or discharging of the input capacitance and the accumulated leakage associated with the protection network and the input circuit AF002521 Figure 3 Input Circuitry The only exception to the purely capacitive input case is the X2 crystal input As shown in Figure 3 b an internal resistor connects X1 and X2 in addition to th protection network The resistor is a modestly high value of more than 100kohms Fanout from the driving circuitry into the Am9513A inputs will generally be limited by transition time considerations rather than DC current limitations when the loading is dominated by conventional MOS circuits In an operating environment ail inputs should be terminated so they do not fl
113. errupt Level Interrupt level W1 Row 5 5 selected factory setting Local Interrupt No Connect and W2 No Connect No Connect No Connect factory setting The different permutations of A9 through A3 yield 128 different possible base I O addresses in the range from hex 000 though 3F8 Appendix E Switch Settings lists the switch settings corresponding to these base addressees 2 2 National Instruments Corporation Chapter 2 Configuration and Installation On the U12 DIP switches press the side marked OFF to select a binary value of 1 for the corresponding address bit Press the other side of the switch to select a binary value of 0 for the corresponding address bit Suppose you wish to use Hex 228 as your base I O address The corresponding binary pattern is 1000101000 for A9 through AO A9 through A3 should be set to 1000101 via the switch at U12 as shown in Figure 2 2B Figure 2 2A shows the default factory setting for the switches at U12 that yields a base I O address of hex 1 U12 U12 ACA a A6 MAs A6 MAM A5 A5 Na A amp Ce A3 M s A3 4 Switches Set to Base I O Address Hex 228 A Switches Set to Default Setting Base I O Address Hex 1A0 Figure 2 2 Example Base 1 0 Address Switch Settings Table 2 2 Default Settings of National Instruments Products for the PC
114. es only 8 bit transfers Am9513A System Timing Controller The Am9513A STCs are the heart of the PC TIO 10 These chips have five individually controlled 16 bit counters each of which can be configured to operate in a number of different modes Therefore the PC TIO 10 can be used for applications such as rate generation FSK and pulse parameter measurement Each of the counters has its own source SOURCE gate GATE and output OUT connections Each STC has an independently controlled frequency scaler output The STCs are clocked by an onboard 1 MHz crystal oscillator to give 1 timing resolution In addition SOURCES and SOURCE10 are clocked at 5 MHz to give 200 nsec resolution on all timing channels Refer to Chapter 4 Programming or to Appendix C AMD Am9513A Data Sheet for more detailed information MC6821 Peripheral Interface Adapter PC TIO 10 User Manual The MC6821 PIA features sixteen bits of bit configurable digital I O In addition this device has two edge programmable interrupt inputs with which the PC TIO 10 can receive external interrupts Refer to Chapter 4 Programming or to Appendix D Motorola MC6821Data Sheet for more detailed information 3 2 National Instruments Corporation Chapter 3 Theory of Operation Interrupt Control Circuitry The interrupt level used by the PC TIO 10 is selected by the onboard jumper W1 Interrupts can be generated from two different sources EXTIRQI and EXTIRQ2
115. escription 7 0 D lt 7 0 gt If the Output Register is being accessed see the PC TIO 10 User Manual description of the Control Registers on the page that follows writing a value to the Data Register updates all output bits and has no effect on input bits Reading the Data Register returns the current signal value of all bits including those configured for output If the Data Direction Register is being accessed writing a zero to a bit makes the corresponding I O line an input while writing a one to a bit makes the corresponding I O line an output Reading the Data Direction Register returns the current configuration 4 6 National Instruments Corporation MC6821 Control Registers Chapter 4 Programming The MC6821 Control Registers control the overall operation of the MC6821 and the selection of the two internal registers that are accessed through each of the MC6821 Data Registers Some of the bits in the Control Registers are not used because of the design of the PC TIO 10 These bits should be set as follows Base address 05 hex for Port A Base address 07 hex for Port B Read and write Address Type Word Size Bit Map 6 8 bit register 8 bit port IRQ 0 0 0 DRS EDGE INTEN Bit 6 3 Name IRQ Reserved DRS EDGE National Instruments Corporation Description This is a read only bit that reflects the current status of the interrupt input f
116. f CM2 1 When the high impedance option is selected and the comparator is enabled the status register bit will reflect an active high comparator output When the low impedance to Ground option is selected and the comparator is enabled the status register bit will reflect an active low comparator output The Status register is normally accessed by reading the Control port see Figure 6 but may also be read via the Data port as part of the Control Group BYTE POINTER Ours OUT 3 OUT 1 DF001900 Figure 10 Status Register Bit Assignments DATA PORT REGISTERS Counter Logic Groups As shown in Figures 4 and 5 each of the five Counter Logic Groups consists of a 16 bit general counter with associated controt and output logic a 16 bit Load register a 16 bit Hold register and a 16 bit Mode register in addition Counter Groups 1 and 2 aiso include 16 bit Comparators and 16 bit Alarm registers The comparator alarm functions are con trolled by the Master Mode register The operation of the Counter Mode registers is the same for ail five counters The host CPU has both read and write access to all registers in the Counter Logic Groups through the Data port The counter itself is never directly accessed Load Register The 16 bit read write Load register is used to control the effective length of the general counter Any 16 bit value may be written into the Load register That value can then be transferred into the counter each time
117. f our vector is already there short ri exit different vector segment exit bx offset handler short ri exit different vector offset exit PC TIO 10 User Manual Chapter 4 Programming restore old mask and vector values mov in jmp or out jmp in jmp or out jmp mov mov lds int cx int mask al maskm 42 al cl maskm al 42 al masks 42 al ch masks al 42 al vect num ah 25h dx int addr 21h restore saved registers ri exit pop pop pop pop pop pop sti ret remove isr endp isr handler F _isr_handler PC TIO 10 User Manual CI push push es ds dx far 4 20 get the old mask value get current master mask delay wait for data transfer OR in old mask value send out new setting delay wait for data transfer get current slave mask delay wait for data transfer OR in old mask value send out new setting delay wait for data transfer al holds interrupt level ds dx points to new handler install the old vector National Instruments Corporation Service interrupt your code here Chapter 4 Programming i if this was not your interrupt jump to ih 0 3 if this was your interrupt service it as appropriate the pointer for the data structure isr block is stored at DATA isrb addr to access the structure use the following steps mov ax seg DATA mov ds ax lds s
118. ferred into the counter When No Gating is specified the definition of CM7 changes In this case when CM7 0 the Gate input has no effect on the counting when CM7 1 the Gate input specifies the source selecting either the Load or Hold register used to reload the counter when TC occurs Figure 14 shows the various available contro combinations for these interrelated bits Count Source Selection Counter Mode bits 8 through CM12 specify the source used as input to the counter and the active edge that is counted Bit CM12 controis the polarity for all the sources logic zero counts rising edges and logic one counts falling edges Bits CM8 through CM11 select 1 of 16 counting sources to route to the counter input Five of the available inputs are internal frequencies derived from the internal oscillator see Figure 13 for frequency assignments Ten of the available inputs are interface pins five are labeled SRC and five are labeled GATE The 16th availabie input is the TC output from the adjacent lower numbered counter The Counter 5 TC wraps around to the Counter 1 input This option allows internal concatenating that permits very long counts to be accumulated Since all five counters may be concatenated it is possible to configure a counter that is 80 bits long on one Am9513A chip When TCN 1 is the source the count ripples between the connected counters External connections can also be made and can use the toggle bit fo
119. gramming environment These functions include routines for digital I O counter timer operations RTSI and acquiring data to extended memory NI DAQ has both high level DAQ I O functions for maximum ease of use and low level DAQ I O functions for maximum flexibility and performance Examples for high level functions are streaming data to disk or acquiring a certain number of data points An example of a low level function is writing directly to registers on the DAQ device NI DAQ does not sacrifice performance of National Instruments DAQ devices because it lets multiple devices operate at their peak performance even simultaneously NI DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers NI DAQ maintains a consistent software interface so that you can change platforms with minimal modifications to your code Whether you are using conventional programming languages or NI DAQ software your application uses the NI DAQ driver software Optional Equipment The following is a list of optional equipment available for the PC TIO 10 e CB 50 I O connector block 0 5 m cable e Standard ribbon cable 0 5 m e Standard ribbon cable 1 0 m e Shielded ribbon cable 1 0 m e Shielded ribbon cable 2 0 m Refer to the Cabling section in Chapter 2 Configuration and Installation for additional information on cabling and connectors National In
120. hat has 32 interrupts and does not use DMA numerically controlled oscillator National Institute of Standards and Technology See TIO optional RAM usually installed into SIMM slots a device designed to transfer electrical signals by utilizing light waves to provide coupling with electrical isolation between input and output Sometimes called optoisolator or photocoupler the technique of using an optoelectric transmitter and receiver to transfer data without electrical continuity to eliminate high potential differences and transients the amount of time required for the analog output voltage to reach its final value within specified limits the maximum rate of change of analog output voltage from one level to another G 10 National Instruments Corporation P parallel mode passband pattern generation PC Card PCI PCMCIA PFI PGIA photoelectric sensor PIA PID control posttriggering National Instruments Corporation G 11 Glossary atype of SCXI operating mode in which the module sends each of its input channels directly to a separate analog input channel of the device to the module the range of frequencies which a device can properly propagate or measure a type of handshaked latched digital I O in which internal counters generate the handshaked signal which in turn initiates a digital transfer Because counters output digital pulses at a constant rate this means you can generate and retrieve
121. hat the gating puise initiates a hardware retrigger save operation 18 This parameter applies to hardware load source select modes S and V CM7 1 and CM15 CM13 000 This parameter represents the minimum hold time to ensure that the GATE input selects the correct load source on the active source edge TC003853 2 151 C 37 PC TIO 10 User Manual Appendix C AMD Am9513A Data Sheet SWITCHING WAVEFORMS 1 TGvww Twwav wore 3 T wore WF004792 TPN NOTE 11 v c004801 Figure 22 Counter Switching Waveforms 2 152 Am9513A PC TIO 10 User Manual C 38 National Instruments Corporation Design Hints 1 When a crystal is not being used X1 and X2 should be connected as shown for TTL input Figure A1 and no input Figure A2 2 Recommended oscillator capacitor values are 18 pF on X1 and X2 3 Unused inputs should be tied to VCC 4 The TC output can glitch when the counter is loaded For this reason this output should not be connected to edge sensitive interrupts The counter output should be set or cleared after the LOAD command 5 The two most significant bits of the status register are not specified They may be zero or one 6 The mode register should not be modified when the counter is armed 7 The LOAD and HOLD registe s should not be changed during TC 8 When using the different clocks for different counters be aware that
122. i isrb_addr you need not use ds si but be sure to save any registers you use acknowledge the interrupt ih 0 mov mov mov cmp slave je out jmp Ths out ax seg DATA ds ax al eoi Slave ack 0 short ih 1 acks al 42 ackm al restore saved registers pop pop sti iret isr handler _ TEXT ends end National Instruments Corporation ds ax endp 4 21 signify end of interrupt See if we need to acknowledge jump if not send slave acknowledge delay wait for data transfer send master acknowledge PC TIO 10 User Manual Specifications This appendix lists the specifications of the PC TIO 10 These specifications are typical at 25 C unless otherwise stated The operating temperature range is 0 to 70 C 1 0 Connector Electrical Specifications 1 0 Signal Ratings Absolute maximum voltage rating 0 3 to 47 0 V with respect to GND Input Signal Specifications Input logic high voltage all inputs 2 0 V min 5 25 V max Input logic low voltage all inputs 0 0 V min 0 8 V max Input current Am9513A 0 Vere 5 25 M stas ter 10 uA min 10 uA max Input current MC6821 Port A 0 8 M ester 2 4 mA max Input current MC6821 Port A 2 0 lt 5 25 V assesses 400 pA max Input current MC6821 Port B 0 4 lt Vin ZAN Jinin 10 uA max Input current MC6821 EXTIRQI and EXTIRQ2 0 lt Vi lt 5 25 V
123. in by 4 75 in connector eene 50 pin male ribbon cable connector PC TIO 10 User Manual A 2 National Instruments Corporation Appendix A Specifications Power Requirement from PC 1 0 Channel Typical power eeeeeeeeeneee 0 6 A at 5 VDC 5 Maximum power eee 1 4 Aat 5 VDC 45 5 Note These power usage figures do not include power used by external devices that are connected to the fused supply present on the I O connector National Instruments Corporation A 3 PC TIO 10 User Manual 1 0 Connector This appendix describes the pinout and signal names for the I O connector on the PC TIO 10 Figure B 1 shows the PC TIO 10 I O connector SOURCE1 OUT1 GATE2 SOURCES OUT3 GATE4 GATE5 SOURCE6 OUT6 GATE7 SOURCES8 OUT8 GATE9 GATE10 FOUT1 EXTIRQ1 GND AO A2 A4 A6 BO B2 B4 B6 GATE1 SOURCE2 OUT2 GATE3 SOURCE4 OUT4 OUT5 GATE6 SOURCE7 OUT7 GATE8 SOURCE9 OUT9 OUT10 FOUT2 EXTRIQ2 5 1 5 7 B1 B3 B5 B7 Figure B 1 PC TIO 10 1 0 Connector Detailed signal specifications are included in Chapter 2 Configuration and Installation and in Appendix A Specifications National Instruments Corporation B 1 PC TIO 10 User Manual AMD Am9513A Data Sheet This appendix contains the manuf
124. inal Count On each Terminal Count TC the counter will reload itself from the Load or Hoid register TC is defined as that period of time when the counter contents would have been zero had no reload occurred Some special conditions apply to counter operation immediately before and during TC 1 In the clock cycle before TC an internal signal is generated that commits the counter to go to TC on the next count and retriggering by a hardware Gate edge Modes N O Q and R or a software LOAD or LOAD AND ARM command will not extend the time to TC Note that the next count driving the counter to TC can be caused by the application of a count source edge in level gating modes the edge must occur while the gate is active or it will be disregarded by the application of a LOAD or LOAD AND ARM command see 2 below or by the application of a STEP command 2 Ifa LOAD or LOAD AND ARM command is executed during the cycle preceding TC the counter will immediately go to TC If these commands are issued during TC the TC state will immediately terminate 3 When TC is active the counter will always count the next source edge issued to it even if it is disarmed or gated off during TC This means that TC will never be active for longer than one count period and it may in fact be shorter if a STEP command or a LOAD or LOAD AND ARM command is applied during TC see item 2 above This aiso means that a counter that is disarmed or stopped on TC
125. ines CA1 CA2 CB1 or CB2 The for mat of the control words is shown in Figure 18 DATA DIRECTION ACCESS CONTROL BIT CRA 2 and CRB 2 Bit 2 in each Control Register CRA and deter mines selection of either a Peripheral Output Register or the corresponding Data Direction E Register when the proper register select signals are applied to 50 and RS1 A 1 in bit 2 allows access of the Peripheral Interface Register while a0 causes the Data Direction Register to be addressed Interrupt Flags CRA 6 CRA 7 CRB 6 and CRB 7 The four interrupt flag bits are set by active transitions of signals on the four Interrupt and Peripheral Control tines when those lines are programmed to be inputs These bits cannot be set directly from the MPU Data Bus and are reset indirectly by a Read Peripheral Data Operation on the ap propriate section Control of CA2 and CB2 Peripheral Control Lines CRA 3 CRA 4 CRA 5 CRB 3 CRB 4 and CRB 5 Bits 3 4 and 5 of the two control registers are used to control the CA2 and CB2 Peripheral Control lines These bits determine if the con trol lines will be an interrupt input or an output control signal If bit CRA 5 CRB 5 is low CA2 CB2 is an interrupt input line similar to CA1 CB1 When CRA 5 CRB 5 is high CA2 CB2 becomes an output signal that may be used to control peripheral data transfers When in the output mode CA2 and CB2 have slightly different loading characteristics M
126. ions as well as dynamically reconfigured under program control BLOCK SOURCE 1 6 1 5 PC TIO 10 User Manual GENERAL DESCRIPTION Am9513A DISTINCTIVE CHARACTERISTICS Complex duty cycle outputs One shot or continuous outputs Programmable count gate source selection Programmable input and output polarities Programmabie gating functions Retriggering capability 5 voit power supply Standard 40 pin package SMO DESC qualified 000000 The STC includes five general purpose 16 bit counters variety of internal frequency sources and extemai pins may be selected as inputs for individual counters with software selectable active high or active low input polarity Both hardware and software gating of each counter is available Three state outputs for each counter provide pulses or levels and can be active high or active low The counters can be programmed to count up or down in either binary or BCD The host processor may read an accumulated count at any time without disturbing the counting process Any of the counters may be internaily concatenated to form any effective counter length up to 80 bits DIAGRAM 80003381 National Instruments Corporation Appendix C AMD Am9513A Data Sheet CONNECTION DIAGRAMS Top View DIP 0813 OS12 GATE OB1TUGATE 4A OB1O GATE 3A DGNWGATE 2A 88 GNO HTT TPE Eee GATE 1 CD005212 CD009912 Note Pin 1 is marked for orientati
127. ite Operations Coding C7 C8 C5 C4 C3 C2 CO Description This command disables the prefetch circuitry during Write operations if does not affect Read operations This reduces the write recovery time and allows the user to use block move instructions for initialization of the Am9513A registers Once prefetch is disabled for writing an Enable Prefetch for Write or a Reset command is necessary to re enable the prefetch circuitry for writing Note This command is only available in Am9513A de vices it is an illegal command in the non A Am9513 device Enabie Prefetch for Write Operations Coding C7 C6 CS C4 C3 C2 C CO Description This command re enables the prefetch circuitry for Write operations It is used only to terminate the Disable Prefetch Command Note This command is only available in Am9513A de vices it is an illegal command in the non A Am9513 device Master Reset Coding C7 C8 C5 C4 C3 C2 Ci CO Description The Master Reset command duplicates the action of the power on reset circuitry It disarms all counters enters 0000 in the Master Mode Load and Hoid registers and enters 0800 hex in the Counter Mode registers Following either a power up or software reset the LOAD command should be applied to ail the counters to clear any that may be in a TC state The Data Pointer register should also be set to a legal value since reset does not initialize it A complete reset operation follows 1 Usi
128. ivide its input by any integer value from 1 through 16 inclusive The input to the counter is selected from any of 15 sources including the internal scaled oscillator frequencies FOUT may be gated on and off under software control and when off wil exhibit a low impedance to ground Control over the various FOUT options resides in the Master Mode register After power up FOUT provides a frequency that is 1 16 that of the oscillator The input source on power up is F1 4 39 GATE1 GATES i Gate The Gate inputs may be used to control the operations of individual counters by determining when 36 34 counting may proceed The same Gate input may control up to three counters Gate pins may also be selected as count sources for any of the counters and for the FOUT divider The active polarity for a selected Gate input is programmed at each counter Gating function options allow level sensitive gating or edge initiated gating Other gating modes are available including one that allows the Gate input to select between two counter output frequencies All gating functions may also be disabled The active Gate input is conditioned by an auxiliary input when the unit is operating with an external B bit data bus See Data Gus description Schmitt trigger circuitry on the GATE inputs allows slow transition times to be used a ej 4 33 29 SRC1 SRCS Source The Source inputs provide exter signa
129. ks See Appendix C AMD Am9513A Data Sheet for further details Specifications for signals at the GATE input are referenced to the signal at the SOURCE input or one of the Am9513A internally generated signals Figure 2 9 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or low at least 100 nsec before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by tosu and tg in Figure 2 9 Similarly the gate signal must be held for at least 10 nsec after the rising or falling edge of a source signal for the gate to take effect at that source edge The gate high or low period must be at least 145 nsec in duration If an internal timebase clock is used the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement creates an uncertainty of one source clock period with respect to unsynchronized gating sources Signals generated at the OUT pin are referenced to the signal at the SOURCE input or to one of the Am9513A internally generated clock signals Figure 2 9 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 300 nsec after the source signal s rising or falling edge Digital 1 0 Signal Connections Pins 31 32 and 35 through 50 of the I O connector are digital I O signa
130. l pins Pins 35 through 42 are connected to the digital lines A lt 0 7 gt for digital I O Port A Pins 43 through 50 are connected to the digital lines B lt 0 7 gt for digital I O Port B Pins 31 and 32 are connected to the external interrupt lines EXTIRQ1 and EXTIRQ 2 Ports A and B can be programmed a bitwise basis to be inputs or outputs The following specifications and ratings apply to the digital I O lines Absolute maximum voltage rating 0 3 to 7 0 V with respect to GND National Instruments Corporation 2 13 PC TIO 10 User Manual Chapter 2 Configuration and Installation Digital Input Specifications referenced to GND Minimum Maximum Input logic high voltage 2 0 V 5 25 V Input logic low voltage 0 0 V 0 8 V Input current Port A 0 lt Vi lt 0 8 V 2 4 mA Input current Port A 2 0 lt Vi lt 5 25 V 400 uA Input current Port B 0 4 Vi 2 4 V 10 pA Input current EXTIRQI and EXTIRQ 2 0 lt Vi lt 5 25 V 2 5 pA Digital Output Specifications referenced to GND Minimum Maximum Output logic high voltage at Ij 200 uA 2 4 V 5 0 V Output logic low voltage at Iut 3 2 mA 0 0 V 0 4 V Darlington drive current Port B at Vgxrt 1 5 V 1 0 mA 10 0 mA PC TIO 10 User Manual 2 14 National Instruments Corporation Chapter 2 Configuration and Installation Figure 2 10 depicts signal connections for three typical digital I O applications 5
131. lected in the contents read from the status register 3 Any input transition that occurs before this minimum setup requirement act on the counter before the execution of the operation initiated by the write and the counter may be off by one count 4 Any input transition that occurs after this minimum hold time is guaranteed to not influence the contents read from the status register on the current read operation 5 Any input transition that occurs after this minimum hold time is guaranteed to be seen by the counter as occurring after the action initiated by the write operation and the counter may be off by one count 6 This parameter applies to cases where the write operation causes a change in the output bit 7 The enabled count source is one of F1 F5 TCN 1 SRC1 SRC5 GATE1 GATE 5 as selected in the applicable Counter Mode register The timing diagram assumes the counter counts on rising source edges The timing specifications are the same for falling edge counting 8 This parameter applies to edge gating CM15 13 110 111 and gating when both 7 1 and CM15 CM13 000 This parameter represents the minimum GATE puise width needed to ensure that the pulse initiates counting or counter reloading 9 This parameter applies to both edge and level gatinq CM15 CM13 001 through 111 and CM7 0 This pa This test circuit is the dynamic load of a Teradyne J941 Am9513A National Instr
132. les Typically the number of input samples in a scan is equal to the number of channels in the input group For example one pulse from the scan clock produces one scan which acquires one new sample from every analog input channel in the group the clock controlling the time interval between scans On boards with interval scanning support for example the AT MIO 16F 5 this clock gates the channel clock on and off On boards with simultaneous sampling for example the EISA A2000 this clock clocks the track and hold circuitry the number of scans per second For example a scan rate of 10 Hz means sampling each channel 10 times per second seconds PC TIO 10 User Manual Glossary self calibrating settling time Shannon Sampling Theorem S H shared memory SIMM SMB SNR software trigger SPDT SS STC strain gauge statically configured device successive approximation ADC PC TIO 10 User Manual a property of a DAQ board that has an extremely stable onboard reference and calibrates its own A D and D A circuits without manual adjustments by the user the amount of time required for a voltage to reach its final value within specified limits a law of sampling theory stating that if a continuous bandwidth limited signal contains no frequency components higher than half the frequency at which it is sampled then the original signal can be recovered without distortion sample and hold a circuit that ac
133. lipsis represent a range of values associated with a bit or signal name for example DBIO lt 3 0 gt The symbol leads you through nested menu items and dialog box options to a final action The sequence File Page Setup Options directs you to pull down the File menu select the Page Setup item and select Options from the last dialog box This icon denotes a note which alerts you to important information This icon denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash National Instruments Corporation ix PC TIO 10 User Manual About This Manual A This icon denotes a warning which advises you of precautions to take to avoid being electrically shocked italic Italic text denotes variables emphasis a cross reference or an introduction to a key concept This font also denotes text that is a placeholder for a word or value that you must supply monospace Text in this font denotes text or characters that you should enter from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions and code excerpts NI DAQ NI DAQ is used throughout this manual to refer to the NI DAQ software for DOS Windows LabWindows unless otherwise noted Related Documentation The following d
134. lock input level indicates the interrupt level that is to be modified on input isr block points to the data structure that will be used by the isr_handler function void isr_handler void the isr handler function will never be called from C void remove_isr void public _install_isr _isr_handler _remove_isr _DATA segment word public DATA National Instruments Corporation 4 15 PC TIO 10 User Manual Chapter 4 Programming declarations ackm equ acks equ eoi equ maskm equ masks equ int addr dd int mask dw isrb addr dd slave ack db vect num db DATA ends TEXT assume cs TEXT install isr bp reg ret addr ofs ret addr seg level isr block ofs isr block seg install isr PC TIO 10 User Manual cli pus mov pus pus pus pus pus pus mov mov Segment word public D DJ oO Do Pp 00020h 000a0h 00020h 00021h 000a1h CODE ss TEXT ds DATA at bp 0 at bp 2 at bp 4 at bp 6 at bp 8 at bp 10 proc far bp bp sp ax bx cx dx ds es ax seg _DATA ds ax 4 16 National Instruments Corporation mov mov mov mov Chapter 4 Programming Save the pointer for the isr block structure used in isr handler ax bp 8 get ofs into ax word ptr isrb addr 0 ax save address in variable ax bp 10 get seg into ax word ptr isrb addr 2 ax save address in variable
135. low Read signal is conditioned by Chip Select and indicates that internal information is to be transferred to the data bus The source will be determined by the being addressed and for Data Port reads by the contents of the Data Pointer register WA and should be mutually exclusive Write The active low Write signal is conditioned by Chip Select and indicates that data bus information is to be transterred to an internal location The destination will be determined by the being addressed and for Data Port writes by the contents of the Data Pointer register WA and should be mutually exciusive 8 Control Data The Control Data signal selects source and destination locations for Read and Write operations on the data bus Control Write operations load the Command register and the Data Pointer Control Read operations output the Status register Data Read and Data Write transfers communicate with alt other internal registers indirect addressing at the data port is controlled internally by the Data Pointer register nl 2 120 Am9513A PC TIO 10 User Manual C 6 National Instruments Corporation Chip Select Controi Data Source N Gate N Data Bus Frequency Out Out N Figure 1 interface Signal Summary Figure 1 summarizes the interface signais and their abbreviations for the STC Data Bus Width MM14 Package Pin 16 Bits 8 Bits 12
136. ls that may be counted by any of the counters Any Sourca lina may be routed to any or all of the counters and the FOUT divider The active polarity for a selected SRC input is programmed at each counter Any duty cycle waveform will be accepted as long as the minimum pu se width is at least half the period of the maximum specified counting frequency for the part Schmitt tngger circuitry on the SRC inputs allows slow transition times to be used Counter Each 3 state OUT signal is directly associated with a corresponding individual counter Depending on the counter configuration the OUT signal may be a pulse a square wave or a complex duty cycle waveform OUT puise polanties are individually programmable The output circuitry detects the counter state that would have been ail bits zero in the absence of a reinitialization That information is used to generate the selected waveform type An optional output mode for Counters and 2 ovemdes the normal output mode and provides a true OUT signal when the counter contents match the contents of an 3 2 40 OUT OUTS Alarm register 12 19 20 087 vo Data Bus The 16 bidirectional Data Bus lines are used for information exchanges with the host processor 22 28 088 OB15 HIGH on a Data Bus line corresponds to one and LOW corresponds to zero These lines act as inputs when WA and CS are active and as outputs when RD and CS are active When CS is inactive these pins are placed
137. lt 1 10 gt signals description table 2 8 timing connections 2 11 to 2 13 OUT lt 5 1 gt bits 4 5 P parts locator diagram 2 1 PC I O channel control circuitry 3 2 PC TIO 10 features 1 1 kit contents 1 2 optional equipment 1 3 overview ix National Instruments Corporation l 3 Index software options 1 2 to 1 3 unpacking 1 4 physical specifications A 2 pin assignments for I O connector figure 2 7 B 1 power connections 2 15 power requirements from PC I O channel A 2 to A 3 problem solving and diagnostic resources online F 1 programming 4 1 to 4 21 See also registers Am9513A STC device considerations 4 8 examples Am9513A STCs 4 9 to 4 12 interrupt programming for MC6821 4 9 to 4 21 overview of registers 4 1 protection fuse A 3 pulse and square wave production 2 9 pulse width measurement 2 10 R registers Am9513A Command Registers 4 4 Am9513A Data Registers 4 3 Am9513A Status Registers 4 5 MC6821 Control Registers 4 7 to 4 8 MC6821 Data Registers 4 6 overview 4 1 register map 4 2 S signal connections 2 6 to 2 15 digital I O signals 2 13 to 2 15 exceeding maximum ratings caution 2 6 I O connector pin assignments figure 2 7 PC TIO 10 User Manual Index power connections 2 15 signal description table 2 8 timing signals 2 9 to 2 12 signal timing requirements 2 12 to 2 13 software options 1 2 to 1 3 National Instruments application software 1 2 t
138. ludes five general purpose 16 bit counters A variety of internal frequency sources and external pins may be selected as inputs for individual counters with software select able active high active low input polarity Both hardware and software gating of each counter is available Three state outputs for each counter provide either pulses or levels The counters can be programmed to count up or down in either binary or BCD The accumulated count may be read without disturbing the counting process Any of the counters may be internally concatenated to form an effective counter length of up to 80 bits The Am9513A block diagrams indicate the interface signals and the basic flow of information Internal control lines and the internal data bus have been omitted The control and data registers are ail connected to a common internal 16 bit bus The externa bus may be 8 or 16 bits wide in the 8 bit mode the internal 16 bit information is muitiplexed to the low order data bus pins DBO through OB7 An internal oscillator provides a convenient source of frequen cies for use as counter inputs The oscillator s frequency is controlled at the X1 and X2 interface pins by an external reactiva network such as a crystal The oscillator output is divided by the Frequency Scaler to provide several sub frequencies One of the scaled frequencies or one of ten input signals may be selected an input to the FOUT divider and then comes out of the chip at
139. m command 14 In the down counting mode of the Am9513A if a 0001 is loaded into the counter and another LOAD COUNTER command is issued the TC of that counter will go active if the load register contents are subsequently changed and the counter armed the first clock edge will cause the new load register contents to transfer into the counter and the next clock edge will decrement the counter and make it go out of TC 15 Glitches on CS just before the FID or WA pulse may cause the part to behave incorrectly 16 Timing parameters TGVEH amp TEHGV must not be vio lated Figure A4 shows a method H A 1 Registers not being programmed correctly Check READ or WRITE recovery time 2 Setup and hold problems observed in synchronous systems Try switching from positive edge to negative edge triggering R1 6 8 10 R2 is function of Driver Circuitry to meet AMD Am9513A Data Sheet X2 VIH 3 8 V X2 ViL 08 V Figure A1 Crystal Input Configuration 2 153 Am9513A National Instruments Corporation 6 39 PC TIO 10 User Manual Appendix C AMD Am9513A Data Sheet 2 154 PC TIO 10 User Manual xi 5 og x2 Figure A2 Crystal Input Configuration TCo02000 Count Source GATE Figure A3 TEHWH TGVWH Timing Diagram GATE GATE Am9513A TC004100 Figure A4 GATE SRC Configuration Suggestion Am9513A WFO023981
140. m9513A Data Registers are used to read from or write to any of the 18 internal registers of the Am9513A The Am9513A Command Registers must be written to in order to select the register to be accessed by the Am9513A Data Registers The internal registers accessed by the Am9513A Data Registers are as follows e Counter Mode Registers for Counters 1 2 3 4 and 5 e Counter Load Registers for Counters 1 2 3 4 and 5 e Counter Hold Registers for Counters 1 2 3 4 and 5 e Compare Registers for Counters 1 and 2 e Master Mode Register All these registers are 16 bit registers that must be accessed through an 8 bit port least significant byte first Bit descriptions for each of these registers are included in Appendix C AMD Am9513A Data Sheet Address Base address 00 hex for Am9513A STC A Base address 02 hex for Am9513A STC B Type Read and write Word Size 16 bit register 8 bit port Bit Map 7 6 5 4 3 2 1 0 D15 D14 D13 D12 Dil D10 D9 D8 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 DO Bit Name Description 7 0 D lt 15 8 gt These eight bits are the most significant byte to be loaded into or read from the Am9513A Internal Register currently selected These eight bits should be accessed after the eight bits of the least significant byte are accessed 7 0 D lt 7 0 gt These eight bits are the least significant byte to be loaded into or read from the Am9513A Internal Register currently selected
141. n cases where the GATENA input is used this timing specification must be met by both the GATE and GATENA inputs 11 Signals F1 F5 cannot be directly monitored by the user The phase difference between these signals will manifest itself by causing counters using two different F signals to count at different times on nominally simultaneous transi tions in the F signals F1 X2 12 This timing specification assumes that CS is active when ever RD or are active CS may be held active indefinitely 13 This parameter assumes X2 is driven from an external gate with a square wave 14 This parameter assumes that the write operation is to the command register 15 This timing specification applies to single action com mands only g LOAD ARM SAVE etc For double action commands such as LOAD AND ARM and DISARM AND SAVE TWHEH minimum 700 ns 16 n short data write mode TWHRL and TWHWL mini mum 1000 ns 17 This parameter applies to the hardware retrigger save modes N O Q A and X CM7 1 and CM15 13 lt gt 000 This parameter ensures that the gating pulse initiates a hardware retrigger save operation 18 This parameter applies to hardware load source select modes S and V CM7 1 and CM15 CM13 000 This parameter represents the minimum hold time to ensure that the GATE input selects the correct load source on the active source edge l 2 148 PC TIO 10 User M
142. ne by setting a jumper W1 The default interrupt line is IRQ5 To change to another line remove the jumper from IRQ5 and place it on the pins for another request line Figure 2 3 shows the default factory setting for IRQS oot DD uU 55558 wo A N j IRQ3 IRQ9 Figure 2 3 Interrupt Jumper Setting for IRQ5 Factory Setting 2 4 National Instruments Corporation Chapter 2 Configuration and Installation To disable the PC TIO 10 interrupt request line change the jumper setting as shown in Figure 2 4 IRQ3 Figure 2 4 Interrupt Jumper Setting for Disabling Interrupts Local Interrupt Selection In addition to the jumpers for selecting the interrupt level used by the PC TIO 10 a set of jumpers W2 is used to locally connect two of the counter outputs to the interrupt generation circuitry There are four positions on this set of jumpers two No Connect positions labelled N C a position for OUT2 and a position for OUT7 The position for OUT2 connects the output of counter 2 to the EXTIRQI input while the position for OUT connects the output of counter 7 to the EXTIRQ2 input The No Connect positions are intended as storage positions for one or both of the jumpers if you do not want to use one or both of the counter outputs for interrupt purposes The default positions for the jumpers on W2 are shown in Figure 2 5 OUT2 OUT7 N C W2 N C Figure 2 5 Local Interrupt
143. nector is a standard 50 pin header connector which can be interfaced using 50 pin ribbon cable with appropriate connectors Signal input and output wires can be attached to screw terminals on the connector block and are therefore connected to the PC TIO 10 I O connector The CB 50 is useful for initial prototyping of an application or in situations where PC TIO 10 interconnections are frequently changed Once a final field wiring scheme has been developed however you may want to develop your own cable This section contains information for the design of custom cables The PC TIO 10 I O connector is a 50 pin male ribbon cable header connector The manufacturer and the appropriate part number for this connector is as follows e part number 2550 5002UB The mating connector for the PC TIO 10 is a 50 position polarized ribbon socket connector with strain relief National Instruments uses a polarized keyed connector to prevent inadvertent upside down connection to the PC TIO 10 The manufacturer and the appropriate part number for this mating connector is as follows e part number 3425 7650 The manufacturer part number for the standard ribbon cable 50 conductor 28 AWG stranded that can be used with these connectors is as follows e part number 3365 50 PC TIO 10 User Manual 2 16 National Instruments Corporation Theory of Operation This chapter explains the basic operation of the PC TIO 10 circuitr
144. ng the procedure given in the Command Initiation section of this document enter the FF hex command to perform a software reset 2 Using the Command Initiation procedure enter the LOAD command for all counters opcode 5F hex 3 Using the procedure given in the Setting the Data Pointer Register section of this document set the Data Pointer to a valid code The legal Data Pointer codes are given in Figure 8 The Master Mode Counter Mode Load and Hold registers can now be initialized to the desired values Am9513A C 32 National Instruments Corporation VCC with Respect to VSS 0 5 V to 70 V All Signal Voltages with Respect to 55 0 5 V to 70 V Power Dissipitation Package Limitation 15 W Supply Voltage Vcc Industrial Devices Temperature TA Supply Voltage Vcc Military M Devices Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure Functionality at or above these limits is not implied Exposure to absolute maximum ratings for extended periods may affect device reliability OC CHARACTERISTICS over operating ranges unless otherwise specified Description Input Hysteresis SRC and GATE Inputs Only Foe ee ee at Output High Voltage VSS lt VIN lt VCC Input Load Current X2 VSS 0 4 lt VOUT lt VCC Output Leakage Current Except X1 High impedance State Supply Curent Stau Sate Ge ees t
145. o 1 3 NI DAQ driver software 1 3 software related resources F 2 SOURCE signals SOURCE lt 1 4 gt signals table 2 8 SOURCE lt 6 9 gt signals table 2 8 timing connections 2 11 to 2 13 specifications connector electrical specifications A to A 2 input signal specifications 1 I O signal ratings A 1 output signal specifications A 2 operating environment A 2 physical A 2 power requirements from PC I O channel A 2A 3 storage environment A 2 specifications and ratings Am9513A System Timing Controller 2 11 to 2 12 digital I O signal connections 2 13 to 2 14 square wave production 2 9 storage environment specifications A 2 switch settings See also jumper settings default settings 2 2 factory settings table 2 2 settings with corresponding base I O address and base I O address space table E 1 to E 5 PC TIO 10 User Manual l 4 T technical support resources F 1 to F 2 theory of operation 3 1 to 3 3 Am9513A System Timing Controller 3 2 block diagram 3 1 data transceivers 3 2 interrupt control circuitry 3 3 MC6821 Peripheral Interface Adapter 3 2 PC I O channel control circuitry 3 2 timing and digital I O connector 3 3 time lapse measurement 2 10 timing connections See also Am9513A System Timing Controller event counting 2 9 to 2 10 frequency measurement 2 10 to 2 11 GATE SOURCE OUT and FOUT signals 2 11 pulse and square wave production 2 9 pulse width measurement 2 10 sign
146. oat and therefore will not accumulate stray static charges Unused inputs should be tied directly to Ground or VCC as appropriate An input in use wil have some type of logic output driving it and termination during operation will not be a problem Where inputs are driven from logic external to the card conta ning this chip however on board termination should be provided to protect the chip when the board is unplugged the input would otherwise float A pull up resistor or a simple inverter or gate will suffice Am9513A National Instruments Corporation 2 121 C 7 PC TIO 10 User Manual AMD Am9513A Data Sheet Appendix C AMD 9513 Data Sheet DETAILED DESCRIPTION The Am9513A System Timing Controller STC is a support device for processor oriented systems that is designed to enhance the available capability with respect to counting and timing operations it provides the capability for programmable frequency synthesis high resolution programmable duty cycle wavetorms retriggerable digital timing functions time of day clocking coincidence alarms complex puise generation high resolution baud rate generation frequency shift keying stop watching timing event count accumulation waveform analysis and many more A variety of programmable operating modes and control features allow the Am9513A to be personalized for particular applications as well as dynamically reconfigured under program control The STC inc
147. ocuments contain information that you may find helpful as you read this manual e Am9513A Am9513 System Timing Controller technical manual e Your computer s technical manual PC TIO 10 User Manual X National Instruments Corporation Introduction This chapter describes the PC TIO 10 lists the contents of your PC TIO 10 kit lists the optional software and equipment for use with the PC TIO 10 and explains how to unpack PC TIO 10 kit The PC TIO 10 is a timing and digital I O interface for the PC Two AMD Am9513A STCs are used for the timing interface With these chips which feature many different timing and counting modes the PC TIO 10 can perform a wide range of pulse measurement and wave generation functions A Motorola MC6821 PIA is used for the digital I O interface each of the two 8 bit I O ports is bit configurable In addition the PC TIO 10 has two edge sensitive interrupt inputs with programmable edge selection Any external TTL signal including any of the counter outputs can be connected to these interrupt inputs The timing circuits on the board make the PC TIO 10 useful for the following operations e Wave and pulse generation e Frequency shift keying FSK e Pulse width measurement e Time of day counting and alarm generation e Event counting The digital I O lines on the PC TIO 10 interface the PC to the following e BCD compatible panel meters and test equipment e Opto isolated solid state rela
148. on ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges The order number Valid Combination is formed by a combination of a Device Number b Speed Option if applicable c Package Type d Temperature Range Optional Processing AM9513A OPTIONAL PROCESSING Blank Standard processing B Bum in d TEMPERATURE RANGE C Commercial 0 to 70 C industrial 40 to 85 PACKAGE TYPE 40 Pin Plastic DIP PO 040 D 40 Pin Ceramic DIP CD 040 J 44 Pin Plastic Leaded Chip Carrier PL 044 b SPEED OPTION Not a DEVICE NUMBER DESCRIPTION Am9513A System Timing Controller Valid Combinations Valid Combinations list configurations planned to be supported in Valid Combinations volume for this device Consult the local AMD sales office to Casa 068 08 26 confirm availablity of specific valid combinations to check on aes PC DC 0 08 JC newly released combinations and to obtain additional data This device is also available in Military temperature AMD s standard military grade products range Ne Am9513A 2 117 National Instruments Corporation C 3 PC TIO 10 User Manual Appendix C AMD Am9513A Data Sheet ORDERING INFORMATION continued Standard Military Drawing SMD DESC Products AMD products for Aerospace and
149. or the selected Control Register If this bit is one in the Port A Control Register an interrupt request is pending on the external interrupt line EXTIROQI If this bit is one in the Port B Control Register an interrupt request is pending on the external interrupt line EXTIRQ2 Always write a zero to this bit These bits are not used on the PC TIO 10 Always write a Zero to each of these bits This is the Data Register Select bit Writing a one to this bit selects the Output Register while writing a zero to this bit selects the Data Direction Register Reading this bit shows the bit s current state Refer to the description of the Data Register for more information This is the control bit for selecting the edge that will cause an interrupt Writing a one to this bit selects rising edge interrupts while writing a zero to this bit selects falling edge interrupts The Port A Control Register controls external interrupt line EXTIROQI while the Port B Control Register controls external interrupt line EXTIRQ2 Reading this bit shows the bit s current state 4 7 PC TIO 10 User Manual Chapter 4 Programming 0 INTEN This bit enables and disables the interrupt generation capability of EXTIRQI or EXTIRQ2 Writing a one to this bit enables interrupts while writing a zero to this bit disables interrupts The Port A Control Register controls EXTIRQI while the Port B Control Register controls EXTIRQ2 Reading this bit shows the bit s current
150. ove isr void the main program void main unsigned int pa_ctrl pa_data pb ctrl pb data isr block type block calculate register addresses pa ctrl base address porta offset ctrl offset pa data base address porta offset data offset pb ctrl base address portb offset ctrl offset pb data base address portb offset data offset National Instruments Corporation 4 13 PC TIO 10 User Manual Chapter 4 Programming clear any active interrupts by reading Data Registers outp pa ctrl 0x04 select Output Register inp pa data clear Port A interrupts outp pb ctrl 0x04 select Output Register inp pb data clear Port B interrupts install the interrupt service routine isr block pa ctrl pa ctrl initialize isr block isr block pa data pa data isr block pb ctrl pb ctrl isr block pb data pb data isr block done 0 install isr irq channel amp isr block configure Ports A and B for interrupts outp pa ctrl 0x05 enable falling edge interrupts outp pb ctrl 0x07 enable rising edge interrupts wait for the process to be completed while isr block done call foreground code disable interrupts and remove the interrupt service routine 7 outp pa_ctrl 0x04 inp pa data outp pb ctrl 0x04 inp pb data remove isr Sample code for the functions install isr an
151. quires and stores an analog voltage on a capacitor for a short period of time See dual access memory single in line memory module a type of miniature coaxial signal connector signal to noise ratio the ratio of the overall rms signal level to the rms noise level expressed in decibels a programmed event that triggers an event such as data acquisition single pole double throw a property of a switch in which one terminal can be connected to one of two other terminals simultaneous sampling a property of a system in which each input or output channel is digitized or updated at the same instant System Timing Controller a thin conductor which is attached to a material that detects stress or vibrations in that material The conductor s resistance is a function of the applied force a device whose logical address cannot be set through software that is it is not dynamically configurable an ADC that sequentially compares a series of binary weighted values with an analog input to produce an output digital word in n steps where n is the bit resolution of the ADC G 14 National Instruments Corporation switchless device system noise T H THD THD N thermistor thermocouple TIO TTL UART UI unipolar National Instruments Corporation G 15 Glossary devices that do not require dip switches or jumpers to configure resources on the devices also called Plug and Play devices a measure of the amo
152. r prefetches are also performed after each write to the Data port and after execution of the Load Data Pointer com 2 124 PC TIO 10 User Manual mand The following rules should be kept in mind regarding Data port Transfers Counter 1 Mode Reg Counter 1 Load Reg Counter 1 Hold Reg Counter 2 Mode Reg Counter 2 Load Reg Counter 2 Hold Reg HOLD CYCLE Counter 5 Hold Reg Alarm Reg 1 ELEMENT CYCLE Alarm Reg 2 Master Mode Reg Status Reg CONTROL GROUP CYCLE STATUS CYCLE LS001240 Figure 9 Data Pointer Sequencing The Data Pointer register should always be reloaded before reading from the Data port if a command other than Load Data Pointer was issued to the Am9513A following the last Data port read or write The Data Pointer does not have to be loaded again if the first Data port transaction after a command entry is a write since the Data port write will automatically cause a new prefetch to occur 2 Operating modes N O Q R and X allow the user to save the counter contents in the Hold register by applying an active going gate edge if the Data Pointer register had been pointing to the Hold register in question the pre fetched value will not correspond to the new value saved in the Hold Register To avoid reading an incorrect value a new Load Data Pointer command should be issued before attempting to read the saved data A Da
153. r even longer counts This is easily accomplished by selecting a TC Toggled output mode and wiring OUTN to one of the SRC inputs Gating Control Counter Mode bits CM15 CM14 CM13 specify the hardware gating options When gating is selected 000 the Appendix C AMD Am9513A Data Sheet counter will proceed unconditionally as long as it is armed For any other gating mode the count process is conditioned by the specified gating configuration For a code of 100 in this field counting can proceed only when the pin labeled GATEN associated with Counter N is at a logic high level When it goes LOW counting is simply suspended until the Gate goes HIGH again A code of 101 performs the same function with an opposite active polarity Codes 010 and 011 offer the same function as 100 but specify alternate input pins as Gating Sources This allows any of three interface pins to be used as gates for a given counter On Counter 4 for example pin 34 pin 35 or pin 36 may be used to perform the gating function This also allows a single Gate pin to simulta neously control up to three counters Counters 1 and 5 are considered adjacent when using TCN 1 001 Gate N 1 010 and Gate N 1 011 controis For codes of 110 or 111 in this field counting proceeds after the specified active Gate edge until one or two TC events occur Within this interval the Gate input is ignored except for the retriggering option When repetition is sel
154. r to read intermediate counts In addition the Hold register may be used as a second Load register to generate a number of complex output waveforms All five counters have the same basic control logic and control registers Counters 1 and 2 have additional Alarm registers and comparators associated with them plus the extra logic necessary for operating in a 24 hour time of day mode For real time operation the time of day logic will accept 50Hz 60Hz or 100Hz input frequencies Each general counter has a single dedicated output pin It may be turned off when the output is not of interest or may be configured in a variety of ways to drive interrupt controllers Darlington buffers bus drivers etc The counter inputs on the other hand are specifically not dedicated to any given interface line Considerable versatility is available for configur ing both the input and the gating of individual counters This not only permits dynamic reassignment of inputs under soft ware control but also allows multiple counters to use a single input and a single gate pin to control more than one counter Indeed a single pin can be the gate for one counter and at the same time the count source for another 18001231 Figure 5 Counter Logic Groups 3 4 and 5 Am9513A C 8 National Instruments Corporation Element Pointer 00 Mode Register 01 Load Register 10 Register 00 Alarm Register 1 01 Alarm Register 2 10 Mas
155. re 17 the MC6821 has a pair of I O ports whose characteristics differ greatly The A side is designed to drive CMOS logic to normal 30 to 70 levels and incor porates an internal pullup device that remains connected even in the input mode Because of this the A side requires more drive current in the input mode than Port B In con trast the side uses a normal three state NMOS buffer which cannot pullup to CMOS levels without external resistors The B side can drive extra loads such as Dari ingtons without problem When the PIA comes out of reset the A port represents inputs with pullup resistors whereas the B side input mode also will float high or low depending upon the load connected to it Notice the differences between a Port A and Port B read operation when in the output mode When reading Port A the actual pin is read whereas the B side read comes from an output latch ahead of the actual pin CONTROL REGISTERS CRA and CRB The two Control Registers CRA and CRB allow the MPU to contro the operation of the four peripheral control lines CA1 CA2 1 and CB2 In addition they allow the MPU to enable the interrupt lines and monitor the status of the inter rupt flags Bits O through 5 of the two registers may be writ ten or read by the MPU when the proper chip select and register select signals are applied Bits 6 and 7 of the two registers are read only and are modified by external interrupts occurring on control l
156. ress Map tnt eR rte emer 4 2 Table E 1 Switch Settings with Corresponding Base I O Address and Base I O Address Space sese E 1 National Instruments Corporation vii PC TIO 10 User Manual About This Manual Introduction to the PC TIO 10 Conventions This manual describes the mechanical and electrical aspects of the PC TIO 10 and contains information concerning its operation and programming The PC TIO 10 is a timing and digital I O interface for the PC Two Advanced Micro Devices AMD Am9513A System Timing Controllers STCs are used for the timing interface With these chips which feature many different timing and counting modes the PC TIO 10 can perform a wide range of pulse measurement and wave generation functions A Motorola MC6821 Peripheral Interface Adapter PIA is used for the digital I O interface each of the two 8 bit I O ports is bit configurable In addition the PC TIO 10 has two edge sensitive interrupt inputs with programmable edge selection Any external transistor transistor logic TTL signal including any of the counter outputs can be connected to these interrupt inputs This manual describes installation theory of operation and basic programming considerations for the PC TIO 10 The example programs included are written in C and assembly language lt gt H AN The following conventions appear in this manual Angle brackets that contain numbers separated by an el
157. sing FOUT as a system clock source 2 126 Am9513A PC TIO 10 User Manual C 12 National Instruments Corporation Bus Width Bit MM13 controls the multiplexer at the data bus interface in order to configure the part for an 8 bit or 16 bit external bus The intemai bus is always 16 bits wide When MM13 1 16 bit data is transferred directly between the internal bus and all 18 of the external bus lines In this configuration the Byte Pointer bit in the Data Pointer register remains set at ail times When the Am9513A is set to operate with an 8 bit data bus width pins DB8 through DB15 are not used for the data bus and are available for other functions Pins 0813 through DB15 should be tied high Pins 088 through 0812 are used as auxiliary gating inputs and are labeled GATE1A through GATESA respectively The auxiliary gate pin GATENA is logically ANDed with the gate input to Counter N as shown in Figure 12 The output of the AND gate is then used as the gating signal for Counter N Data Pointer Sequencing Bit MM14 controls the Data Pointer logic to enable or disable the automatic sequencing functions When 14 1 the contents of the Data Pointer can be changed onty directly by entering a command When 14 0 several types of automatic sequencing of the Data Pointer are available These are described in the Data Pointer register section of this document When MM13 0 16 bit internal data is transferred a
158. ssed while bypassing the Mode and Load registers The third type of sequencing is the Control cycle If G4 G2 G1 111 and E2 E1 11 the Element Pointer will be incremented through the values 00 01 and 10 with no change to the Group Pointer When G4 G2 G1 111 and 2 E1 11 no incrementing takes place and only the Status register will be available through the Data port Note that the Status register can also always be read directly through the Control port For all these auto sequencing modes if an 8 bit data bus is used the Byte pointer will toggle after every data transfer to allow the least and most significant bytes to be transferred before the Element or Group fields are incremented Prefetch Circuit To minimize the read access time to internal Am9513A registers a prefetch circuit is used for all read operations through the Data port Following each read or write operation through the Data port the Data Pointer register is updated to point to the next register to be accessed Immediately following this update the new register data is transferred to a special prefetch latch at the interface pad logic When the user performs a subsequent read of the Data port the data bus drivers are enabled outputting the prefetched data on the bus Since the internal data register is accessed prior to the start of the read operation its access time is transparent to the user To keep the prefetched data consistent with the Data Pointe
159. state Programming Considerations for the Am9513A STCs Before using the Am9513A STC devices you must initialize them To do this perform the following steps on each of the Am9513A STC devices All writes are 8 bit write operations All values are given in hexadecimal 1 Issue a master reset by writing FF to the Am9513A Command Register 2 Initialize all five counters For ctr 1 to 5 follow these steps Write ctr to the Am9513A Command Register select the Counter Mode Register Write 00 to the Am9513A Data Register store the least significant byte of the counter mode value Write 00 to the Am9513A Data Register store the most significant byte of the counter mode value Write ctr 8 to the Am9513A Command Register select the Counter Load Register Write 03 to the Am9513A Data Register store the least significant byte of the counter load value Write 00 to the Am9513A Data Register store the most significant byte of the counter load value 3 Load all counters with their Counter Load Register values by writing 5F to the Am9513A Command Register Note When you initialize Am9513A STC which contains Counters 6 through 10 ctr must range from 1 to 5 not from 6 to 10 Also each Am9513A STC must always be configured to use the 8 bit bus mode in order to function properly PC TIO 10 User Manual 4 8 National Instruments Corporation Chapter 4 Programming Programming Example for the Am9513A ST
160. struments Corporation 1 8 PC TIO 10 User Manual Chapter 1 Introduction Unpacking Your PC TIO 10 board is shipped in an antistatic package to prevent electrostatic damage to the board Several components on the board can be damaged by electrostatic discharge To avoid such damage in handling the board touch the antistatic package to a metal part of your computer chassis before removing the board from the package Remove the board from the package and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any way Do not install a damaged board into your computer PC TIO 10 User Manual 1 4 National Instruments Corporation Configuration and Installation This chapter describes the PC TIO 10 jumper configurations installation of the PC TIO 10 board in your computer signal connections to the PC TIO 10 board and cabling instructions Board Configuration The PC TIO 10 contains one DIP switch and two jumpers to configure the base I O address and interrupts respectively The DIP switch and jumpers are shown in the parts locator diagram in Figure 2 1
161. t Interrupts are enabled and disabled through the MC6821 Control Register In addition the edge that generates the interrupt is programmable through the MC6821 Control Register When an interrupt is generated as indicated when the Control Register is read the only way the interrupt can be cleared is by reading the Output Register through the Data Register of the I O port that indicated the interrupt For instance if IRQ in the Port B Control Register is set you must set DRS of the Port B Control Register to one and then you must read the Port B Data Register The data returned may not be important depending on how you are using interrupts 4 12 National Instruments Corporation Chapter 4 Programming The code that follows demonstrates how to set up the MC6821 for interrupt generation defines for the program define base address 0x01A0 board located at address 1A0 define porta offset 0x04 offset for Port A define portb offset 0x06 offset for Port B define data_offset 0x00 offset of Data Register define ctrl offset 0x01 offset of Control Register define irq channel 5 the interrupt channel set on W1 a sample structure for the interrupt service routine typedef struct unsigned int pa_ctrl pa_data pb ctrl pb data int done isr block type prototypes for the assembly language functions void far install isr int isr block type far void far rem
162. t illustrate the steps being described and provide detailed information ranging from simple getting started instructions to advanced topics e Product Manuals A comprehensive searchable library of the latest editions of National Instruments hardware and software product manuals e Hardware Reference Database A searchable database containing brief hardware descriptions mechanical drawings and helpful images of jumper settings and connector pinouts Application Notes A library with more than 100 short papers addressing specific topics such as creating and calling DLLs developing your own instrument driver software and porting applications between platforms and operating systems National Instruments Corporation F 1 PC TIO 10 User Manual Software Related Resources Instrument Driver Network A library with hundreds of instrument drivers for control of standalone instruments via GPIB V XI or serial interfaces You also can submit a request for a particular instrument driver if it does not already appear in the library e Example Programs Database A database with numerous non shipping example programs for National Instruments programming environments You can use them to complement the example programs that are already included with National Instruments products Software Library A library with updates and patches to application software links to the latest versions of driver software for National Instruments h
163. ta Hold Time Delay Time Enable Negative Transition to CA2 Negative Transition Delay Time Enable Negative Transition t CA2 Positive Transition Rise and Fall Times for CA1 and CA2 Input Signals Delay Time from CA1 Active Transition to CA2 Positive Transition Delay Time Enable Negative Transition to Data Valid Delay Time Enable Negative Transition to CMOS Data Valid 7 CA2 Delay Time Enable Positive Transition to CB2 Negative Transition Delay Time Data Valid to CB2 Negative Transition Delay Time Enable Positive Transition to CB2 Positive Transition Control Output Pulse Width CA2 CB2 En 1 tp te 1 0 1 0 0 us pa 8 4 1852 20 135 10 us 3 8 10 0 670 0 5 us 3 11 12 top 20 20 20 ns 310 tms o67 05 ws 31 500 375 250 ns 3 7 11 i Rise and Fail Time for CB1 and CB2 Input Signals te 10 10 1 0 j tus 12 Detay Time 1 Active Transition to CB2 Positive Transition tas2 10 us 3 12 Interrupt Release Time IRQA and IRQB R oj 1450 41 10 eos 0 85 us 5 14 Interrupt Response Time t3 10 1 10 us 5 13 a 1 interrupt Input Pulse Time pw 500 500 500 ns 13 RESET Low Time tar 10 lose jos us 15 IVALENT FIGURE 2 BUS TIMING T
164. ta port write to another register will also initiate a prefetch subsequent reads will access the recently saved Hold register data Many systems will use the saving gate edge to interrupt the host CPU In systems such as this the interrupt service routine should issue Load Data Pointer command prior to reading the saved data Status Register The 8 bit read only Status register indicates the state of the Byte Pointer bit in the Data Pointer register and the state of the Am9513A C 10 National Instruments Corporation OUT signal for each of the general counters See Figures 10 and 17 The OUT signals reported are those internal to the chip after the polarity select logic and just before the three state interface buffer circuitry Bits SR6 and SR7 may be 0 or 1 The Status register OUT bit reflects an active high or active low TC output or a TC Toggled output as programmed in the Output Control Field of the Counter Mode register That is it reflects the exact state of the OUT pin When the low impedance to Ground Output option CM2 CMO 000 is selected the Status register will reflect an active high TC Output When a high impedance Output option CM2 CMO 100 is selected the Status register will reflect an active low TC output For Counters 1 and 2 the OUT pin will reflect the comparator Output if the comparators are enabled The Status register bit and OUT pin are active high if CM2 0 and active low i
165. ter Mode Reg National Instruments Corporation Element Cycie increment 11 Hold Register Hold Cycie increment 101 Counter Group 5 Control Cycie increment 110 Illegal 111 Control Group 11 Status Register No increment Figure 7 Data Pointer Register Am9513A C 9 Appendix C DF001890 AMD Am9513A Data Sheet AF002531 2 123 PC TIO 10 User Manual Appendix C AMD 9513 Data Sheet Master Mode Register FF17 Alarm 1 Register FFO7 Alarm 2 Register FFOF Status Register FFIF Figure 8 Load Data Pointer Commands Sequencing is enabled by clearing Master Mode bit 14 MM14 to zero As shown in Figure 9 several types of sequencing are available depending on the data bus width being used and the initial Data Pointer value entered by command When E1 0 or E2 0 and G4 G2 G1 points to a Counter Group the Data Pointer will proceed through the Element cycle The Element field will automatically sequence through the three values 00 01 and 10 starting with the value entered When the transition from 10 to 00 occurs the Group field will also be incremented by one Note that the Element field in this case does not sequence to a value of 11 The Group field circulates only within the five Counter Group codes If E2 E1 11 and a Counter Group are selected then only the Group field is sequenced This is the Hold cycle It allows the Hold registers to be sequentially acce
166. ter Or Output Register is Addressed b2 0 Data Direction Register selected b2 1 Output Register selected CA2 CB2 Established as Output by bS 1 CA2 CB2 Established as Input by b5 0 Note that operation of CA2 and CB2 output b5 b4 53 functions are not identical b5 b4 b3 T gt 2 03 0 Read Strobe with CA1 Restore GA EZ interrupt Monast Enable 03 0 Disables IRQA B MPU Interrupt by CA2 C82 active transition b3 1 Enables IRQAIB MPU Interrupt by CA2 C82 active transition iRQA B will occur on next MPU generat ted positive transition of b3 if CA2 CB2 active transition occurred while interrupt was disabled Determines Active CA2 CB2 Transition for Setting interrupt Flag IRQA BI2 Bit b6 b4z0 IRQA B 2 set by high to low transi tion on CA2 CB2 04 1 IRQA B 2 set by low to high transi tion on CA2 CB2 CA2 goes low on first high to low E transition following an MPU read of Output Register A returned high by next active CA transition as specified by bit 1 b3 1 Read Strobe with E Restore CA2 goes low on first high to iow E transition following an MPU read of Output Register A returned high by next high to low E transition dur ing a deselect b3 0 Write Strobe with CB1 Restore CB2 goes low on first low to high E transition following an MPU write into Output Register B returned high by the next active CB1 transi
167. the respective bit of Output Register A Section B Peripheral Data PBO PB7 The peripheral data lines in the B Section of the PIA can be programmed to act as either inputs or outputs in a similar manner to PAO 7 They have three state capabiity allowing them to enter a high impedance state when the peripheral data line is used as an input In addition data on the peripheral data lines MOTOROLA MICROPROCESSOR DATA National Instruments Corporation 3 1698 D 8 PC TIO 10 User Manual Motorola MC6821Data Sheet Appendix D Motorola MC6821Data Sheet MC6821 PBO PB7 will be read properly from those lines programmed as outputs even if the voltages are below 2 0 volts for a high or above 0 8 V for a low As outputs these lines are compatible with standard TTL and may also be used as a source of at least 1 milliampere at 1 5 volts to directly drive the base of a transistor switch Interrupt Input CA1 and C81 Peripheral input lines CA1 and CB1 are input only lines that set the interrupt flags of the control registers The active transition for these signals is also programmed by the two control registers Peripheral Control CA2 The peripheral control line CA2 can be programmed to act as an interrupt input or as a peripheral control output As an output this line is compati ble with standard TTL as an input the internal pullup resistor on this line represents 1 5 standard TTL loads The fun
168. ting cms cma cmr cm wo omo ome we x x x Mode E shown in Figure 15e is identical to Mode except the counter will only count those source edges which occur while the Gate input is active This feature allows the counting process to be enabled and disabled under hardware control A square wave rate generator may be obtained by specifying the AMD Am9513A Data Sheet TC Toggied output mode COUNT wu Xo XX XX ED ED 0D CE TC OUTPUT Eug CPC gt TC TOGGL D OUTPUT WF004620 Figure 15d Mode D Waveforms COUNT vate 2 OUTPUT TC TOGGLEO OufPuT Figure 15e Mode E Waveforms ene EREMO Am9513A 2 131 National Instruments Corporation C 17 PC TIO 10 User Manual Appendix C AMD Am9513A Data Sheet MODE F Non Retriggerable One Shot Mode F shown in Figure 15f provides a non retriggerable one shot timing function The counter must be armed before it will function Application of a Gate edge to the armed counter will enable counting When the counter reaches TC it will retoad itseif from the Load register The counter will then stop counting awaiting a new Gate edge Note that unlike Mode C a new ARM command is not needed after TC only a new Gate edge After application of a triggering Gate edge the Gate input is disregarded until TC Software Triggered Deiayed Puise One Shot
169. tion Two or more counters can be concatenated by connecting the OUT signal from one counter to the SOURCE signal of another counter The counters can then be treated as one 32 bit or larger counter for most counting applications It is possible to create up to a 160 bit counter in this manner The GATE SOURCE OUT and FOUT signals on the I O connector are connected directly to the Am9513A input and output pins The input and output ratings and timing specifications for the Am9513A signals are given as follows The following specifications and ratings apply to the Am9513A I O signals Absolute maximum voltage rating 0 5 to 7 0 V with respect to GND Am9513A Digital Input Specifications referenced to GND Minimum Maximum Input logic high voltage 2 0 V 5 25 V Input logic low voltage 0 0 V 0 8 V Input current 0 lt Vin lt 5 25 V 10 pA 10 pA National Instruments Corporation 2 11 PC TIO 10 User Manual Chapter 2 Configuration and Installation PC TIO 10 User Manual Am9513A Digital Output Specifications referenced to GND Minimum Maximum Output logic high voltage all outputs at Ij 200 uA 2 44 V 5 0 V Output logic low voltage all outputs at 3 2 mA 0 0 V 0 4 V Figure 2 9 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT signals of the Am9513A STCs SOURCE IH Mi V GATE ML OUT ML tse 145 nsec Minimum tsp 70 nsec
170. tion of the operation initiated by the write and the counter may be off by one count 4 Any input transition that occurs after this minimum hold time is guaranteed to not influence the contents read from the status register on the current read operation 5 Any input transition that occurs after this minimum hold time is guaranteed to be seen by the counter as occurring after the action initiated by the write operation and the counter may be off by one count 6 This parameter applies to cases where the write operation causes a change in the output bit 7 The enabled count source is one of F1 F5 TCN 1 SRC1 SRCS GATE1 GATE 5 as selected in the applicable Counter Mode register The timing diagram assumes the counter counts on rising source edges The timing specifications are the same for failing edge counting 8 This parameter applies to edge gating CM15 CM13 110 or 111 and gating when both CM7 1 and CM15 CM13 000 This parameter represents the minimum GATE puise width needed to ensure that the pulse initiates counting or counter reloading 9 This parameter applies to both edge and level gating CM15 CM13 001 through 111 and CM7 0 This pa rameter represents the minimum setup or hold times to ensure that the Gate input is seen at the intended level on the active source edge and the counter may be off by one count 10 This parameter assumes that the GATENA input is unused 16 bit bus mode or is tied high I
171. tions on Count Control and Gating Control bit combinations Figure 16 Counter Mode Register Bit Assignments TO STATUS REGISTER OUTPUT TC OUTPUT BD003393 2 141 PC TIO 10 User Manual Appendix C AMD 9513 Data Sheet Figure 18 Counter Output Waveforms The other output form TC Toggled uses the trailing edge of TC to toggle a flip flop to generate an output level instead of a pulse The toggle output is half the frequency of TC The TC Toggled output will frequently be used to generate variable duty cycle square waves in Operating Modes G through K In Mode L the TC Toggled output can be used to generate a one shot function with the delay to the start of the output pulse and the width of the output pulse separately programma ble With selection of the minimum delay to the start of the pulse the output will toggie the second source pulse following application of the triggering Gate edge Note that the TC Toggled output form contains no implication about whether the output is active high or active low Unlike the TC output which generates a transient pulse which can clearly be active high or active low the TC Toggled output waveform only flips the state of the output on each TC The sole criterion of whether the TC Toggled output is active high or active low is the level of the output at the start of the count cycie This can be controlled by the Set and Clear Output commands See Figure 19 TC Term
172. to an appropriate logic voltage levei e g either Storage Temperature Range THERMAL CHARACTERISTICS Thermal Resistance Vss or Vcc Plastic Cerdip POWER CONSIDERATIONS The average chip junction temperature Ty in C can be obtained from Ty Tat 1 where Ta Ambient Temperature C Package Thermal Resistance Junction to Ambient C W Pp PINT Icc x Vcc Watts Chip Internal Power Pport Port Power Dissipation Watts User Determined For most applications lt and can be neglected PPORT may become significant if the device is configured to drive Darlington bases or sink LED loads An approximate relationship between Pp and Ty if is neglected is Pp K Ty 273 C 2 Solving equations 1 and 2 for K gives K Pp T q 273 C 2 3 where K is a constant pertaining to the particular part K can be determined from equation 3 by measuring Pp at equilibrium for a known TA Using this value of K the values of Pp and Ty can be obtained by solving equations 1 and 2 iteratively for any value of TA DC ELECTRICAL CHARACTERISTICS 5 0 Vdc 5 55 0 TA Tp to TH unless otherwise noted BUS CONTROL INPUTS R W Enable RESET ASO 51 CS0 CS1 CS2 T input Low Votage SSS 733 03 155298 v Input Leakage Current Vin 0 to 5 25 V tin 10 25 EEOAE
173. ts 4 4 cables optional 1 3 standard connectors 2 16 configuration 2 1 to 2 5 address lines A9 through AO 2 2 default settings for National Instruments products table 2 3 to 2 4 example base I O address switch settings table 2 3 factory set switch and jumper settings table 2 2 interrupt level selection 2 4 to 2 5 local interrupt selection 2 5 to 2 6 parts locator diagram 2 1 connector See I O connector conventions used in manual ix x D D lt 7 0 gt bits Am9513A Data Registers 4 3 MC6821 Data Registers 4 6 PC TIO 10 User Manual Index D lt 15 8 gt bits 4 3 data transceivers 3 2 diagnostic resources online F 1 digital I O connector 3 3 digital I O signal connections 2 13 to 2 15 specifications and ratings 2 13 to 2 14 typical signal connections figure 2 14 DMA channel default settings table 2 3 to 2 4 documentation conventions used in manual ix x related documentation x DRS bit 4 7 E EDGE bit 4 7 equipment optional 1 3 event counting application 2 9 to 2 10 EXTIRQ lt 1 2 gt signals description table 2 8 digital I O connections 2 13 F FOUT lt 1 2 gt signals description table 2 8 timing connections 2 11 frequency measurement 2 10 to 2 11 G GATE lt 1 10 gt signals description table 2 8 timing connections 2 11 to 2 13 GND signal table 2 8 PC TIO 10 User Manual l 2 installation procedure 2 6 unpacking PC TIO 10 1 4 INTEN bit
174. ts Corporation G 3 Glossary Celsius calibration DAC connecting a capacitor in a signal path to remove the DC content of the signal the clock controlling the time interval between individual channel sampling within a scan Boards with simultaneous sampling do not have this clock an instrument used in chemical analysis of gases and liquids computing index a condition for starting or stopping clocks clipping occurs when an input signal exceeds the input range of the amplifier common mode rejection ratio a measure of an instrument s ability to reject interference from a common mode signal usually expressed in decibels dB the smallest detectable change in an input voltage of a DAQ device a method of compensating for inaccuracies in thermocouple circuits the input range over which a circuit can handle a common mode signal the mathematical average voltage relative to the computer s ground of the signals from a differential input any voltage present at the instrumentation amplifier inputs with respect to amplifier ground refers to the core specification defined by the PCI Industrial Computer Manufacturer s Group PICMG the range of a parameter for which compensating adjustment can be made PC TIO 10 User Manual Glossary conditional retrieval conversion device conversion time D A DAC daisy chain dB DDS delta sigma modulating ADC derivative control DIFF differential input PC
175. uments Corporation SWITCHING TEST CIRCUIT AMD Am9513A Data Sheet Appendix C rameter represents the minimum setup or hold times to ansure that the Gate input is seen at the intended level on the active source edge and the counter may be off by one count 10 This parameter assumes that the GATENA input is unused 16 bit bus mode or is tied high In cases where the GATENA input is used this timing specification rust be met by both the GATE and GATENA inputs 11 Signals F1 F5 cannot be directly monitored by the user The phase difference between these signals will manifest itself by causing counters using two different F signals to count at different times on nominally simultaneous transi tions in the F signals F1 X2 12 This timing specification assumes that CS is active when ever RD or WA are active CS may be held active indefinitely 13 This parameter assumes X2 is driven from an external gate with a square wave 14 This parameter assumes that the write operation is to the command register 15 This timing specification applies to single action com mands only e g LOAD ARM SAVE etc For double action commands such as LOAD AND ARM and DISARM AND SAVE TWHEH minimum 700 ns 16 In short data write mode TWHRL TWHWL mini mum 1000 ns 17 This parameter applies to the hardware retrigger save modes N O Q R and X CM7 1 and CM15 CM13 lt gt 000 This parameter ensures t
176. unt of noise seen by an analog circuit or an ADC when the analog inputs are grounded track and hold a circuit that tracks an analog voltage and holds the value on command total harmonic distortion the ratio of the total rms signal due to harmonic distortion to the overall rms signal in decibel or a percentage signal to THD plus noise the ratio in decibels of the overall rms signal to the rms signal of harmonic distortion plus noise introduced a semiconductor sensor that exhibits a repeatable change in electrical resistance as a function of temperature Most thermistors exhibit a negative temperature coefficient a temperature sensor created by joining two dissimilar metals The junction produces a small voltage as a function of the temperature a National Instruments timing and triggering controller ASIC The TIO includes four general purpose counter timers used for applications such as event counting period and frequency measurement and pulse train generation It also includes a trigger routing and condition mechanism for connecting RTSI bus and board specific trigger and timing signals The TIO also provides advanced digital I O capabilities for time stamping multiple I O lines and controlling digital output lines transistor transistor logic universal asynchronous receiver transmitter an integrated circuit that converts parallel data to serial data and vice versa commonly used as a computer bus to serial device interface
177. ut The MC6821 is a 16 bit bit configurable digital I O device with two interrupt inputs that are edge programmable This chapter includes programming information for the PC TIO 10 along with program examples written in C and assembly language 5 Note If you plan to use a programming software package such as LabWindows NI DAQ with your PC TIO 10 board you need not read this chapter Introduction Each of the two Am9513A STC devices is controlled by three different registers a data register a command register and a status register These registers are defined later in this chapter Because there are two Am9513A STC devices on the board they are referenced as STC A and STC B when differentiation is required The MC6821 PIA has four different registers that control its operation The 16 I O lines are grouped into two 8 bit ports Port A and Port B each of which has a control register and a data register associated with it These registers are defined later in this chapter For clarification both registers and ports are referenced in the sections that follow A register refers to a given 8 bit or 16 bit register on the actual Am9513A STC or MC6821 PIA whereas a port refers to the I O channel register through which the device must be accessed Therefore the size shown for a register indicates both the register size and the I O channel port size The digital I O ports associated with the MC6821 PIA are always referenced as Port
178. ve Am9513A National Instruments Corporation Appendix C RC MODE R Retriggerable One Shot Execprspacpo tele e Mode R shown in Figure 15r is similar to Mode Q except that edge gating rather than level gating is used In other words rather than use the Gate level to qualify which source edges to count Gate edges are used to start the counting operation The counter must be armed before application of the triggering Gate edge Gate edges applied to a disarmed counter are disregarded After application of a Gate edge an armed counter will count ail source edges until TC irrespective of the Gate level On the first TC the counter will be reloaded from the Load register and stopped Subsequent counting will not occur until a new Gate edge is applied All Gate edges applied to the counter including the first used to trigger counting initiate a retrigger operation Upon application of a Gate edge the counter contents are saved in the Hold register On the first source edge after the retriggering Gate edge the Load register contents will be transferred into the counter Counting will resume on the second source edge after the retriggering Gate edge 2 137 C 23 AMD Am9513A Data Sheet PC TIO 10 User Manual Appendix C AMD Am9513A Data Sheet PIVIPL PLS OuTPuT Um X OuTPuT Figure 15q Mode Q Waveforms I _ _
179. veforms MODE C armed counter The counter must be armed before application of the triggered Gate edge Gate edges applied to a disarmed Hardware Triggered Strobe counter are disregarded The counter will start counting on the emo cme source unti TC At counter vil elca epee x X X X x the Load register and automatically disarm Counting wil then remain inhibited until a new ARM command and a new Gi lied it Ni fti icati oms owe cma ome cm Gato edge Gato input wil bo disregarded for Co o o X X x X x _ te remainder of the count This differs trom Mode where the Gate can be modulated throughout the count cycie Mode C shown in Fi 15c is identicai to Mode A except to stop and start the ter that counting Wi rot begin nu Gate edge is applied to the T A ER ERR OO VALUE wem Lc oc eg of Ve USSNEIM WFO004610 Figure 15c Mode C Waveforms 2 130 Am9513A PC TIO 10 User Manual C 16 National Instruments Corporation MODE D Rate Generator with No Hardware Gating cre cura cara Ge oe 5 9 9 x Lx x LX XJ cms cme cw MODE Appendix Rate Generator with Level Ga
180. wo Am9513A devices 31 32 EXTIRQ lt 1 2 gt These are the interrupt inputs for the PC TIO 10 33 GND This pin is connected to the computer s ground signal 34 5 This pin is connected to the computer s 5 VDC power supply 35 42 lt 0 7 gt These the eight digital I O lines on Port A of the MC6821 The MSB is A7 43 50 lt 0 7 gt These the eight digital T O lines on Port B of the MC6821 The MSB is B7 PC TIO 10 User Manual 2 8 National Instruments Corporation Chapter 2 Configuration and Installation Timing Signal Connections Pins through 30 of the I O connector are connections for timing I O signals on the two onboard Am9513A Counter Timers The timing signals include the GATE SOURCE and OUT signals for the Am9513A Counters 1 through 10 and the FOUTI and FOUT2 signals generated by the Am9513A STCs Counters 1 through 10 of the Am9513A Counter Timers can be used for general purpose applications such as pulse and square wave generation event counting and pulse width time lapse and frequency measurements For these applications SOURCE and GATE signals can be directly applied to the counters from the I O connector and the counters are programmed for various operations The Am9513A Counter Timer is described briefly in Chapter 3 Theory of Operation For detailed programming information consult Appendix C AMD Am9513A Data
181. x D Motorola MC6821Data Sheet Appendix E Switch Settings Appendix F Technical Support Resources PC TIO 10 User Manual vi National Instruments Corporation Contents Glossary Index Figures Figure 2 1 10 Parts Locator Diagram esee 2 1 Figure 2 2 Example Base I O Address Switch sess 2 3 Figure 2 3 Interrupt Jumper Setting for IRQ5 Factory Setting 2 4 Figure 2 4 Interrupt Jumper Setting for Disabling Interrupts 2 5 Figure 2 5 Local Interrupt Jumper Setting Factory 2 5 Figure 2 6 10 I O Connector Pin Assignments eee 2 7 Figure 2 7 Event Counting Application with External Switch Gating 2 10 Figure 2 8 Frequency Measurement Application sss 2 11 Figure 2 9 Timing Signal Relationships eeeeeeneenee 2 12 Figure 2 10 Digital I O 2 15 Figure 3 1 10 Block Diagram esee eene 3 1 Figure B 1 10 W O Connector eeeeeeeeeeeneereeeneen e emen B 1 Tables Table 2 1 PC TIO 10 Factory Set Switch and Jumper Settings 2 2 Table 2 2 Default Settings of National Instruments Products for the PC 2 3 Table 4 1 PC TIO 10 Add
182. y The block diagram in Figure 3 1 illustrates the key functional components of the PC TIO 10 board 1 MHz and 5 MHz Clocks 5 AMD p sounce 4 Data Am9513A SOURCE 4 Transceiver STC A OUT 6 AMD eSouncE 4 Channel Am9513A SOURCE Control OUT 6 Port A 8 Interrupt Motorola Pot B 8 Control MC6821 Circuitry PIA EXTIRQ_ 2 Connector c c s o 9 o n 1A Fuse Figure 3 1 PC TIO 10 Block Diagram The PC I O channel consists of an address bus a data bus a DMA arbitration bus interrupt lines and several control and support signals National Instruments Corporation 3 1 PC TIO 10 User Manual Chapter 3 Theory of Operation Data Transceivers The data transceivers control the sending and receiving of data to and from the PC I O channel PC 1 0 Channel Control Circuitry The base address used by the board is determined by an onboard switch setting The address on the PC I O channel bus is monitored by the address decoder which is part of the I O channel control circuitry If the address on the bus matches the selected I O base address of the board the board is enabled and the corresponding register on the PC TIO 10 is accessed In addition the I O channel control circuitry monitors and transmits the PC I O channel control and support signals The control signals identify transfers as read or write memory or I O and 8 bit 16 bit or 32 bit transfers The PC TIO 10 us
183. ying the TC Toggled output in the Counter Mode register The Load and Hold values then directly control the output duty cycle with high resolution available when relatively high count values are used PC TIO 10 User Manual MODE K Variable Duty Cycle Rate Generator with Level Gating x x x Lx x eur ewe cma ovs Mode shown in Figure 15k is identical to Mode J except that source edges are only counted when the Gate is active The counter must be armed for counting to occur Once armed the counter will count all source edges which occur while Gate is active and disregard those source edges which occur while the Gate is inactive This permits the Gate to turn the count process on and off As with Mode J the reload source used will aiternate on each TC starting with the Hold register on the first TC after any ARM command When the TC Toggled output is used this mode allows the Gate to modulate the duty cycle of the output waveform It can affect both the HIGH and LOW portions of the output waveform Am9513A C 20 National Instruments Corporation 2 VALUE PANNINIINIININININININDN 202000000200002 Appendix C cR ea m d aA ei MEUM Figure 15j Mode J Waveforms No wy Cx eC OX COGO ee S Dec COGO om
184. ys and I O module mounting racks The PC TIO 10 turns the PC into a timing and digital I O system controller for applications in laboratory testing production testing and industrial process monitoring and control National Instruments Corporation 1 1 PC TIO 10 User Manual Chapter 1 Introduction What Your Kit Should Contain The contents of the PC TIO 10 kit are listed as follows e PC TIO 10 board e PC TIO 10 User Manual e NI DAQ software for DOS Windows LabWindows with manuals If your kit is missing any of the components contact National Instruments Your PC TIO 10 is shipped with the NI DAQ software NI DAQ has a library of functions that can be called from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation digital I O counter timer SCXI RTSI and self calibration NI DAQ maintains a consistent software interface among its different versions so you can switch between platforms with minimal modifications to your code Optional Software This manual contains complete instructions for directly programming the PC TIO 10 Normally however you should not need to read the low level programming details in the user manual because the NI DAQ software package for controlling the PC TIO 10 is included with the board Using NI DAQ is quicker and easier than

PC-TIO-10 User Manual - National Instruments

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