FMC150 User Manual
Contents
1. 33 0 1 64 53 37 90 FMC150 User Manual mg JE r1 5 Appendix A LPC pin out ep 9 EE 1 6 1 1 ee 1 0 1 6 1 8 Ja er me emo mw a o ev dd 3 ev mw me av 3 ea 33 aw av en DE zi av NDC R am BE av Ta en me ME en av a PGND PGND a sam oo ME EN HEN we em so av ox o BE eo Gv LPC LPC LPC LPC Colors indicate _CC signal and associated I O signal groups as recommended by AV57 1 in Table 14 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 902. Guidelines for controlling the clock tree Apart from enabling the onboard reference and VCXO the whole clock tree is controlled by programming the CDCE72010 device through a serial communication bus The following guidelines should be taken into account 1 The internal reference is enabled by driving REF_EN high The internal reference should only be enabled in case internal clock is used and there is no external reference applied 2 The onboard VCXO is enabled by default but can be disabled through the GPIO pins on the AMC7823 see section 5 4 This may be useful when using external clock 3 It is recommended to disable the unused clock outputs 4 It is recommended to disable PLL functions and VXCO input on the CDCE72010 when an external sampling clock is applied 5 In case internal clock is used the PLL functions needs to be enabled The recommended phase detector frequency is 160kHz In case the internal reference is used the reference divider should be set to 625 The VCO divider is set to 4608 6 Other phase detector frequencies may be used but stability of the PLL is not guaranteed in all cases 5 2 Guidelines for controlling the ADC Controlling the ADC enables advanced control of the digitizing process The ADS62P49 can be programmed through a serial communication interface to change the output format or using advanced settings among which gain control offset correction and several power down modes 1 Low speed mod
3. asserted MON N INT Only the first four channels can be monitored with thresholds These are the main supplies derived from the other voltages on channel 4 to 7 lt is recommended to power down the unused features DAC operation precision current source and reference buffer amplifier Internal reference must be selected Since the AMC7823 is powered from 3 3V only internal reference of 1 25V is allowed Only internal trigger mode is supported Auto mode is recommended to continuously monitor channel 0 to channel 3 and verify against the programmed thresholds Temperature h8 1 Table 6 Temperature and voltage parameters 5 5 Controlling onboard FANS The FMC150 holds two power headers which may optionally be used to power low profile FANS glued on the devices On the FMC150 each FAN can be switched off individually by pulling its control signal high The control signals are connected to the GPIO on the AMC7823 6 Environment 6 1 Temperature Operating temperature FMC150 User Manual January 2011 www 4dsp com 15 ADSP est distribu par TECHWAY www techway fr info techway fr 33 011 64 53 37 90 FMC150 User Manual ter r1 5 e 40C to 85 C Industrial Storage temperature e 40Cto 120C 6 2 Monitoring The AMC7823 device may be used to monitor the voltage on the different power rails as well as the temperature It is recommended that the carrier card and or host software uses the power down features
4. in the devices in the case the temperature is too high Normal operations can resume once the temperature Is within the operating conditions boundaries 6 3 Cooling Two different types of cooling will be available for the FMC150 6 3 1 Convection cooling The air flow provided by the chassis fans the FMC150 is enclosed in will dissipate the heat generated by the on board components minimum airflow of 300 LFM is recommended Optionally low profile FANS can be glued on top of the devices Refer to section 5 5 on how to control these FANS For standalone operations such as on a Xilinx development kit it is highly recommended to blow air across the FMC and ensure that the temperature of the devices is within the allowed range 4DSP s warranty does not cover boards on which the maximum allowed temperature has been exceeded 6 3 2 Conduction cooling In demanding environments the ambient temperature inside a chassis could be close to the operating temperature defined in this document It is very likely that in these conditions the junction temperature of power consuming devices will exceed the operating conditions recommended by the devices manufacturers mostly 85 C While a low profile heat sink coupled with sufficient air flow might be sufficient to maintain the temperature within operating boundaries some active cooling would yield better results and would certainly help with resuming operations much faster in the case the devices wer
5. set to 1 65V 4 7 Clock tree 4 7 1 External clock input There is one clock input on the front panel that can serve as a sampling clock input or as a reference clock input in case the internal clock is desired Note when internal clock is enabled and there is no need for an external reference it is highly recommended to leave the external clock input unconnected to prevent interference with the internal clock 4 7 2 Architecture The FMC150 card offers a clock architecture that combines flexibility and high performance Components have been chosen in order to minimize jitter and phase noise to reduce degradation of the data conversion performance The user may choose to use an external sampling clock or an internal sampling clock TS CDCE72010 PLL and clock distribution device is the base of the clock tree The external clock input is routed to two RF transformers one for driving the reference input of the PLL SEC_IN and one for driving the auxiliary clock input AUXIN The auxiliary input can be connected directly to the distribution section of the CDCE72010 The VCO can be powered down to avoid interference with the external clock FMC150 User Manual January 2011 www 4dsp com 11 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC150 User Manual Rh JEg r1 5 The VCXO is connected to the VCXO clock input This clock input connects both to the clock distribution section and the PLL secti
6. 2 FMC150 daughter card main characteristics 4 4 Analog input channels The AC coupled input uses wideband RF transformers TC1 1T Two transformers are used to compensate for imbalance and therefore improving harmonic distortion performance FMC150 User Manual January 2011 www 4dsp com 10 ADSP est distribu par TECHWAY www techway fr info techway fr 33 011 64 53 37 90 FMC150 User Manual mg JEg r1 5 capacitor in front of the transformer blocks the DC path to ground which will protect the signal source in case a DC coupled signal with offset is accidentally connected to the FMC150 The input impedance is matched to 500Q behind the transformers by terminating each node to the common mode voltage of the ADC The R C R filter near the input of the A D converter can be used to improve performance when lower input bandwidth is required By default this filter is assembled 4 5 Analog output channels The AC coupled output uses wideband RF transformers TC4 1W An optional re construction filter is available on each DAC output Refer to Table 2 for the filter characteristics The filter can be bypassed on the board with 00 resistors L1 270n L3 270n mw nn C2 12p C1 2p C312p L2 270n L4 270n vy ULF Figure 4 Optional DAC re construction filter 4 6 External trigger input The external trigger input is configured as a single ended input The allowed input range is ground and 3 3V The trigger threshold is
7. FMC150 User Manual mg JE r1 5 FMC150 User Manual Contact www iechway fr TECHWAY S A S 19 Avenue de Norv ge B t Oslo Villebon sur Yvette 91953 Courtaboeuf Cedex France T 33 0 1 64 53 37 90 F 33 0 1 64 53 17 74 Email support 4dsp com This document is the property of 4DSP LLC and may not be copied nor communicated to a third party without the written permission of 4DSP Inc 4DSP LLC 2010 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC150 User Manual ter r1 5 Revision History 2010 08 13 Initial Draft 0 1 2010 08 13 Release after review 1 0 2010 10 20 Update oscillator details in the clock tree 1 1 description Removed DIP switch definition FMC150 User Manual January 2011 www 4dsp com 2 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC150 User Manual mg SE Table of Contents 1 Acronyms and related documents rannnnnnnnnnnennnnnnnnennnnnnnnnnnnnennnnnnnnennnnennnnnnnnen LE ACONI a ee Re et ints Tee Related DOCS ee ee ae 2 General description sssssss sn scene esse ee 3 lastalla lt 1 ass EE se 4 1 Phycisal specifications 4 4 1 1 Board Dimensions c AR PORDAN REE EE NE 42 Electrical specifications vr eek dal EEPROM ceee EEE EEES AN 1 6 1 6 E E E E O 422 NNN 4 3 Main characteristics ss 4 4 Analog input channels 4 5 Analog output Channels sss eee eee ee eee 4 6 Ex
8. User Manual January 2011 www 4dsp com 12 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC150 User Manual s g JEg r1 5 VTUNE VCP TED R47 TBD C52 TED C51 t 39 Figure 6 PLL1 loop filter design Table 3 Loop filter component values 4 8 Power supply Power is supplied to the FMC150 card through the FMC connector The pin current rating is 2 7A but the overall maximum is limited according to Table 4 Table 4 FMC standard power specification The power provided by the carrier card can be very noisy Special care Is taken with the power supply generation on the FMC150 card to minimize the effect of power supply noise on clock generation and data conversion Typical Maximum VADJ 554 mA 665 mA 3P3V 100 mA 12POV 368 mA 442 mA 3P3VAUX Paire 0 01 uA 1 uA Table 5 Typical Maximum current drawn from FMC carrier card FMC150 User Manual January 2011 www 4dsp com 13 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC150 User Manual mg JEg r1 5 5 Controlling the FMC150 Good knowledge of the internal structure and communication protocol of relevant onboard devices is required for controlling the FMC150 This document only provides guidelines for programming the devices For detailed information it is recommended to refer to the datasheets listed in the related documents section of this document 5 1
9. ated Documents FPGA Mezzanine Card FMC standard ANSI VITA 57 1 Datasheet ADS62P49 Rev 2009 06 Texas Instruments Datasheet DAC3283 Rev 2010 04 Texas Instruments Datasheet CDCE72010 Rev 2010 06 Texas Instruments Datasheet ADS4249 Rev 0 2 2010 03 Texas Instruments Datasheet AMC 7823 Texas Instruments FMC150 User Manual January 2011 www 4dsp com 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 r1 5 FMC150 User Manual mg JEg r1 5 2 General description The FMC150 is a four channel ADC DAC FMC daughter card The card provides two 14 bit A D channels and two 16 bit D A channels which can be clocked by an internal clock source optionally locked to an external reference or an externally supplied sample clock In addition there is one trigger input for customized sampling control The FMC150 daughter card is mechanically and electrically compliant to FMC standard ANSI VITA 57 1 The FMC150 has a low pin count connector front panel I O and can be used in a conduction cooled environment The design is based on TTS ADS62P49 ADS4249 dual channel 14 bit 250Msps ADC and TIS DAC3283 dual channel 16 bit 800Msps DAC The analog signal inputs are AC coupled connecting to MMCX SSMC coax connectors on the front panel The FMC150 allows flexible control on sampling frequency analog input gain and offset correction through serial communication busses Furthermore the card is equipped with power supply and
10. e disabled because of a temperature over range 7 Safety This module presents no hazard to the user 8 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system FMC150 User Manual January 2011 www 4dsp com 16 ADSP est distribu par TECHWAY www techway fr info techway fr 33 011 64 53 37 90 FMC150 User Manual mg JEg r1 5 9 Ordering information Part Number FMC150 2 1 1 1 Card Type FMC150 0 Temperature Range Industrial 40 C to 85 C 1 Commercial 0 C to 70 C 2 Connector Type Standard Feature MMCX snap coupling 1 SSMC screw coupling 2 Analog Signal Input Standard Feature VCXO option 491 52MHz 1 VCXO option 737 28MHz 2 Custom VCXO option contact factory 3 Mil 1 46058c Conformal Coating No Conformal Coating 1 Add Conformal Coating 2 10 Warranty Basic Warranty 1 Year from Date of Shipment 90 Days from Date of Shipment included oe Warranty 2 Years from Date of Shipment 1 Year from Date of Shipment optional FMC150 User Manual January 2011 www 4dsp com 17 4DSP est distribu par TECHWAY www techway fr info techway fr
11. e should be selected for sampling frequencies below 100Msps 2 External reference should never be enabled 3 Do not enable CMOS mode when there is LVDS termination on the carrier card 5 3 Guidelines for controlling the DAC Controlling the DAC enables advanced control of the conversion process The DAC3283 can be programmed through a serial communication interface to change the input format or using advanced settings among which gain control offset correction and several power down modes 1 The communication bus can only be used in unidirectional mode thus using SDIO as data input and ALARM SDO as data output FMC150 User Manual January 2011 www 4dsp com 14 ADSP est distribu par TECHWAY www techway fr info techway fr 33 011 64 53 37 90 FMC150 User Manual mg JEg r1 5 5 4 Guidelines for controlling onboard monitoring The FMC150 holds an AMC7823 for monitoring several power supply voltages on the board as well as temperature The device can be programmed and read out through a SPI bus 1 2 The measured values must be multiplied by one or two to get the actual level The measured value on channel 4 must be multiplied by 5 7 to get the actual level Continuously operating the SPI bus might interfere with the A D or D A conversion process resulting in signal distortion It is recommended to program the minimum and maximum thresholds in the monitoring devices and only read from the devices when the interrupt line is
12. gue input bandwidth 0 40 500MHz tbd 73 dBFS is the maximum provided by TI SFDR tbd 88 dBc is the maximum provided by TI Analog Outputs FMC150 User Manual January 2011 www 4dsp com 9 ADSP est distribu par TECHWAY www techway fr info techway fr 33 011 64 53 37 90 FMC150 User Manual ar D s r1 5 Output voltage range 1Vp p Output impedance 50Q AC coupled 82MHz 5th order Chebyshev low pass filter Slope Roll Off 124 9 dB decade Difference between the signal strengths at 65 MHz and 75 MHz 0 6 dB Output filter can be bypassed with OQ resistors Analogue output bandwidth Low cut off is 3MHz due to the output transformer stage External Clock Reference Input Input Level 0 1 1 3 Vp p Input impedance 500 AC coupled Input bandwidth External Trigger input LVTLL LVCMOS Format Logic 0 gt max 0 8V Logic 1 gt min 2 0V Frequency range Up to 125 MHz ADC Output Data width LVDS 7 pairs DDR per channel Data Format Offset binary or 2 s complement Sampling Frequency Range up to 250MHz DAC Input Data width LVDS 8 pairs DDR Data Format Offset binary or 2 s complement Sampling Frequency Range up to 800MHz Internal Sampling Clock LVPECL 491 52 MHz contact factory for different frequency options F R ADC 245 76 MHz contact factory for different frequency options Po SER DAC 491 52 MHz contact factory for different frequency options Table
13. ndby current is only 0 01uA when SCL and SDA are kept at 3V3VAUX level The EEPROM is write protected The protection can be removed by switching on SW1 of the DIP switch silk screen label is WR EN 4 2 1 JTAG The FMC150 card TDO pin is connected to the TDI pin to ensure continuity of the JTAG chain TCK TMS and TRST are left unconnected on the FMC150 4 2 2 FMC Connector The low pin count connector has only bank LA available and two dedicated LVDS clock pairs The recommendations from AV57 1 Table 14 have been taking into account resulting in the following arrangement e The clock and data pairs from the ADC are mapped to LAOO CC and LAO1 LA14 respectively e The remaining connections from this associated I O signals LA15 LA16 are used for non critical control signals e The reference clock for the DAC interface is mapped to CLKO M2C The clock frame and data pairs to the DAC are mapped to LA17 LA26 e The remaining connections from this associated I O signals LA27 LA33 are used for non critical control signals e The external trigger connects to CLK1 M2C Refer also to Appendix A LPC pin out 4 3 Main characteristics Analog Inputs Number of channels Channel resolution Input voltage range 2Vp p 10 dBm Programmable from OdB to 6dB in 0 5dB steps Input gain 6dB gain gives an input voltage range of 1 Vp p Inputimpedanee impedance Inputimpedanee 50Q AC coupled AC 500 AC coupled Analo
14. on In order to tune the VCXO to a certain frequency a reference clock is required An onboard 100MHz oscillator can be enabled in case there is no external reference connected The onboard oscillator is connected to the primary reference input PRI_IN CDCE72010 De C XTAL 100MHz LVPECL r UTP l s UIN PRI IN te UDP UM roe UJP UIN De LEP Ly gt LER LSIN LEP 1 i K a b i i kr wa DAC AUE HIL d 4 UTN s i i i To FMC gt UEP UEN Figure 5 Clock tree architecture The A D and D A clock outputs on the CDCE72010 should be configured as LVPECL outputs Another output is configured as LVDS output and connects to the FMC connector to be used as reference clock for the D A clock and data signals CLK TO FPGA P N 4 7 3 PLL design The PLL functionality of the CDCE72010 is used to operate from an internal sampling clock To enable flexibility in frequency selection while maintaining high performance a high frequency low phase noise VCXO is used A high frequency oscillator enables different output frequencies after division The design allows different VCXO types 1 VS 705 491 52 MHz default a enabling 245 76 MHz A D sampling divide by 2 b enabling 491 52 MHz D A sampling divide by 1 2 TCO 2111 737 28 MHz contact 4DSP a enabling 245 76 MHz A D sampling divide by 3 b enabling 737 28 MHz D A sampling divide by 1 FMC150
15. ront panel I O The front area holds 6 MMCX or 6 SSMC connectors The stacking height is 10mm FMC150 User Manual January 2011 www 4dsp com 7 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC150 User Manual lg JEg r1 5 lt 1 5 mm gt 16 66mm gt 61 7 Amm 2 6 mm 2 1Amm HMM UO 63 8mm SPC CPPCC CCCP I II IR I I RCC SRP CPC CCPC PCC CCC CCPC I RIRE Fed LI IR IR IR I IR IR I CCRC 27 18 mm men 56 846 mm Figure 2 FMC150 dimensions 4 1 2 Front panel There are 6 MMCX or SSMC connectors available from the front panel From top to bottom analog in analog in B clock in CLK trigger in TRG analog out C and analog out D Figure 3 Bezel design 4 2 Electrical specifications The FMC150 card is designed to operate in LVDS mode The FMC150 requires a VADJ voltage of 2 5V The data converters operate in LVDS mode clock and data pairs All other status and control signals like serial communication busses operate at LVCMOS 2 5V level FMC150 User Manual January 2011 www 4dsp com 8 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC150 User Manual mg JEg r1 5 4 2 1 EEPROM The FMC150 card carries a small serial EEPROM 24LC02B which is accessible from the carrier card through the FC bus The EEPROM is powered by 3V3VAUX The sta
16. temperature monitoring and offers several power down modes to switch off unused functions Sy 7 LVDS Clock 1 anne Coupling A D E Control Channel B C3 Monitoring E m AMC7823 Q External D lock F Clo Clock tree LVDS Clock 1 D 5 Reference lt Control T External gt CDCE72010 OS Trigger N LVDS Trigger 1 N E No lt 5 Channel C LVDS Clock 1 5 SA ups paa it D A LVDS Data 8 Channel D Figure 1 FMC150 block diagram FMC150 User Manual January 2011 www 4dsp com 6 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC150 User Manual mg JEg r1 5 3 Installation 3 1 Requirements and handling instructions e Prevent electrostatic discharges by observing ESD precautions when handling the card e Do not flex the card and do not exceed the maximum torque specification on the coax connectors e The FMC150 daughter card must be installed on a carrier card compliant to the FMC standard e The FMC carrier card must support the low pin count connector 160 pins The FMC carrier card may support the high pin count connector 400 pins e The FMC carrier card must support a VADJ VIO B voltage of 2 5V LVDS mode 4 Design 4 1 Phycisal specifications 4 1 1 Board Dimensions The FMC150 card complies with the FMC standard known as ANSI VITA 57 1 The card is a single width conduction cooled mezzanine module with region 1 and f
17. ternal trigger input K iy ame ec Ge gt ae ee ee eee A1 eee iNpUt EE EE Aee FEIT EE ne eo nets NE We so 9 REE A F RT TN re 5 Controlling the FMC ae sae ends 5 1 Guidelines for controlling the clock tree 5 2 Guidelines for controlling the ADC 5 3 Guidelines for controlling the DAC 5 4 Guidelines for controlling onboard monitoring 55 Controlling onboard FANS Se sese eee 60 EnvironmeNn ooo tie ces essences encens nan seen een cne see ce ue 61 T MOCTAUTS nn meme meme meme EE 6 2 ION TORING Suede de ne done din O OO a O 631 e e n lt e ien COC a ne ce ao st 6 32 Conduction COOIMING erre tene FMC150 User Manual January 2011 www 4dsp com 4DSP est distribu par TECHWAY www techway fr info techway fr 33 011 64 53 37 90 r1 5 FMC150 User Manual mg JE r1 5 10 Warranty Append APG DIMOU Lupen 18 January 2011 FMC150 User Manual www 4dsp com 4 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC150 User Manual mg JE 1 Acronyms and related documents 1 1 1 2 Acronyms DDR __ Double Data Rate O Oo Fineline Ball Grid Array FPGA Mezzanine Card Printed Circuit Board Peripheral Component Interconnect PCI Express Multi Gigabit Transceiver Phase Locked Loop i QDR __ Quadruple Data rate S Transistor Logic level PCle Mezzanine card Table 1 Glossary DEP LVDS Low Voltage Differential Signaling it s Rel
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