NPCIe-8560-8E1/T1/J1
Contents
1. Version 1 2 O N A T GmbH 3 NPCIe 8560 8E1 T1 J1 Technical Reference Manual Table of Contents TABLE OF CONTENTS ev gENeENENESN NN REN EEN NSEN ENN SEN ENKEN ENN EENS EN EE ENNEN ENNER ENKEN ge A LIST OF TABLES aa a a a a a a a a e a aaa a aaia aaa aiaa 5 LIST OF FIGURES ia aaa aaa aa a aaa B Ben a aar a ia ia a a aiiidh Esa 5 CONVENTIONS a uc SSES AER SE ENEEARE EN SEN REENEN ENEE E ERR E dEAEE ER de gees 6 1 INTRODUCTION WEE 7 23 e VI CAT Ad TEE 8 2 1 MAJOR FEATURES iii a 8 2 2 BLOCK DIAGRAM EE 9 2 3 LOCATION OVERVIEW ee pee zssse irerkr Ra ARES YN o EX REN SQEFRKYNERUN REV i 10 3 BOARD FEATURES i 11 lceiserrccsRrashcRiUURseusovanDOEEsCRR sums EREDUR aa aana 11 3 1 Le CIR 11 3 1 1 PrOCeSSOE CO db 11 3 1 2 Processor Integrated I O e 11 3 2 MEMO eet D toute See Ee E ee ee See 12 3 2 1 DDR SDRAM ir barba PEE ble ERA a re PLATES 12 3 2 2 2A IM 12 3 3 PCI EXPRESS INTERFACE 12 3 4 El T1 J1 EINE INTERFACES NES E di 12 3 5 ETHERNET rc ita ad Dalla rdg 12 3 6 PTMC INTERFACE cita Aia 13 3 7 NR EL OB 13 3 8 E ee 13 4 HARDWARE aa a a a a a a a a iia 14 4 1 FRONT PANEL AND LEDS a a Ls AAT 14 4 2 CONNECTORS AND SWITCHES ccccccconnncnncnnnnnnnnnnnnnnnnn nn eaae aane aa nna nnn 15 4 2 1 PICPCLExpre ss COnDeCctOF 2 sorore DEEN youn ued pees DEN Aa PERS eR s 16 4 2 2 S1 Ethernet COMME COS nana canaria 16 4 2 3 S35 JISDN ConnectOF EE 17 4 2 4 IPL Lattice Program Ming Porta A 18 4 2 5 JP2 BDM an2. P412 P411 s3 Or Hun Please refer to the following sub chapters to look up the connector pin assignment of the NPCIe 8560 8E1 T1 J1 Version 1 2 O N A T GmbH 15 NPCIe 8560 8E1 T1 J1 Technical Reference Manual 4 2 1 P1 PCI Express Connector P1 is a standard PCle x1 connector Table 2 P1 PCIe Connector Pin Assignment Pinf Signal Signal Pin Ae po TDI gt SAT D AY 33V TST O 4 2 2 SI Ethernet Connector The following table shows the pin assignment of RJ45 connector S1 This connector carries the 1000BaseT signals of the Ethernet interface Table 3 S1 Ethernet Connector Pin Assignment 3 1 3 m 1 8 Version 1 2 O N A T GmbH 16 NPCIe 8560 8bE1 T1 J1 Technical Reference Manual 4 2 3 S3 ISDN Connector The ISDN front panel connectors are 8 pin RJ45 connectors The 8 E1 T1 J1 line interfaces are available on the pins of the front panel connectors S3a S3d each connector carries two interfaces The following tables show the pin assignments Table 4 S3a ISDN Connector Pin Assignment Table 5 S3b ISDN Connector Pin Assignment Table 6 S3c ISDN Connector Pin Assignment Table 7 S3d ISDN Connector Pin Assignment Version 1 2 O N A T GmbH 17 NPCIe 8560 8bE1 T1 J1 Technical Reference Manual 4 2 4 JP1 Lattice Programming Port Connector JP
3. 10 9 USER GND 10 59 USER USER 60 59 op RxdDO 60 For configuration 2 the PTMC Specification does not define a fixed usage for the PINS marked with USER These pins are connected to the FPGA on the NPCIe 8560 8E1 T1 J1 Please contact NAT if a user defined usage of those pins is needed Version 1 2 N A T GmbH 21 NPCIe 8560 8E1 T1 J1 Technical Reference Manual 4 2 9 S2 RS232 Connector The following table shows the pin assignment of the RS232 interface Table 13 S2 RS232 Connector Pin Assignment 3 TxD_SCC1 5 GND LI Connector S2 is connected to SCC1 of the MPC8560 CPM RxD_SCC1 3 TxDSCCi NES CENE 4 2 10DIP SW1 Flash Half Select PCIe Bridge Direction The table below gives an overview of the operating parameters configurable via DIP SW1 Details are given in the following subchapters Table 14 DIP SW1 Pin Assignment Overview FLASH half select PCIe Bridge Direction 4 2 10 1 DIP SW1 Switch 1 Boot FLASH Select Switch By operating Switch 1 of DIP SW1 to ON the upper half of the Boot FLASH is selected for booting If Switch 1 of DIP SW1 is turned to OFF the lower half of the Boot FLASH is selected for booting Table 15 DIP SW 1 Switch 1 Boot Flash Select Pin Assignment Upper FLASH Half Lower FLASH Half Default Switch 1 of DIP SW1 is toggled to OFF lower half of the Boot FLASH is selected for booting Version 1 2 O N A T GmbH
4. 22 NPCIe 8560 8E1 T1 J1 Technical Reference Manual 4 2 10 2 DIP SW1 Switch 2 PCIe Bridge Direction Switch This switch is used to select the source of the PCIe reference clock If Switch 2 of DIP SW1 is turned to ON a local 100MHz reference is chosen Additionally the PCI reset from the PEX8112 has no longer impact on the rest of the board This mode is intended to be selected when the board is used in a standalone application If Switch 2 of DIP SW1 is turned to OFF the external reference clock from the PCIe connector is taken Table 16 DIP SW 1 Switch 2 PCIe Bridge Direction Pin Assignment Local 100MHz Clock External Clock from PCIe Connector Default Switch 2 of DIP SW1 is switched to OFF external clock from PCIe connector selected 4 2 11LF1 Write Protect Pin Solder Field If the solder field LF1 is closed the Write Protect Pin WP Pin of the FLASH is asserted Default Solder field LF1 is open FLASH write protection is disabled 4 2 12LF2 Voltage Source Solder Field Solder field LF2 selects the source of the PMC 3 3Vayux If the solder field is closed towards the mark on the PCB 3 3V AUX the 3 3Vayx of the PMC is directly connected to the 3 3Vayx of the PCIe connector If the solder field is closed to the other side the 3 3Vayx of the PMC is sourced by the local generated 3 3V Default Solder field LF2 is closed towards the mark 3 3V AUX the PMC 3 3Vaux is sourced by the local ge
5. 8560 8E1 T1 J1 Features cocococcocnncnnnnnnnnnnnnnnnnnncnnnnrrnnnnrnnnnrrnnnes 25 List of Figures Figure 1 NPCIe 8560 8E1 T1 J1 Block Diagram Overview enn 9 Figure 2 NPCIe 8560 8E1 T1 J1 Location diagram Overview eee 10 Figure 3 NPCIe 8560 8E1 T1 J1 Front Panel View 14 Figure 4 NPCIe 8560 8E1 T1 J1 Connector and Switch location Overview 15 Version 1 2 O N A T GmbH 5 NPCIe 8560 8bE1 T1 J1 Technical Reference Manual Conventions If not otherwise specified addresses and memory maps are written in hexadecimal notation identified by Ox The following table gives a list of the abbreviations used in this document Table 1 List of used abbreviations b o Bitbinry Oo B O Byte Complex Programmable Logic Device DR a Data Rate El 2 048 Mbit G 703 Interface Ji E OB 1 FLASH Reprogrammable ROM internal TDM 231 po 1 544 Mbit G 703 Interface Japan Line Interface Unit PCI Express Time Slot Assigner Version 1 2 O N A T GmbH 6 NPCIe 8560 8E1 T1 J1i Technical Reference Manual 1 Introduction The NPCIe 8560 8E1 T1 J1 is a high performance standard height full length PCI Express x1 add in card The NPCIe 8560 8E1 T1 J1 is providing access to E1 T1 J1 interfaces combined with the functionality of a PMC carrier board It is intended to be used with standard PMC or PTMC modules in a standard PC with PCI Expr
6. GmbH 29 NPCIe 8560 8E1 T1 J1 Technical Reference Manual 8 Known Bugs Restrictions none Version 1 2 O N A T GmbH 30 NPCIe 8560 8E1 T1 J1i Technical Reference Manual Appendix A Reference Documentation 1 3 7 8 10 11 12 13 Freescale MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual 7 2004 Rev 1 Samsung DDR SDRAM 512 MB C die Rev 1 1 6 2005 PLX Technology PEX8112AA PCI Express to PCI Bridge Data Book 11 2007 Rev 1 1 Zarlink ZL30100 T1 E1 System Synchronizer Data Sheet 11 2005 Maxim DS26518 8 Port T1 E1 J1 Transceiver Rev 103008 Spansion S29GL N MirrorBit Flash Family Data Sheet Rev B Am 3 10 2006 N A T FPGA TSI Technical Reference Manual March 2005 Ver 1 0 N A T TDM FPGA Technical Reference Manual October 2006 Ver 1 0 Version 1 2 O N A T GmbH 31 NPCIe 8560 8E1 T1 J1 Technical Reference Manual Appendix B Document s History Date Description Author 07 07 2010 12 08 2010 Changed Memory size added LED description ks updated connector location diagram 20 05 2013 Contact data updated typo correction 04 07 2013 Adapted to new layout reworked Se PEREAT IEEE 10 2013 GE renamed Version 1 2 O N A T GmbH 32
7. complete power that is needed by the PMC will be added to the 12V line of the PCIe connector Automatic Power Up In the following situations the NPCIe 8560 8E1 T1 J1 will automatically be reset and proceed with a normal power up e The voltage sensor generates a reset e when 12V voltage level drops below 8V e when 3 3V voltage level drops below 3 08V e The main board backplane signals a PCIe Reset Thermal Considerations The NPCIe 8560 8E1 T1 J1 can be operated in a temperature range of 0 C to 65 C if the air velocity does not fall below 1 m s This minimum velocity is required in the region of the CPU s heat sink the residual area should be passed by air with a minimum velocity of 0 5 m s Version 1 2 O N A T GmbH 27 NPCIe 8560 8bE1 T1 J1 Technical Reference Manual 7 3 7 3 1 7 3 2 Statement on Environmental Protection Compliance to RoHS Directive Directive 2002 95 EC of the European Commission on the Restriction of the use of certain Hazardous Substances in Electrical and Electronic Equipment RoHS predicts that all electrical and electronic equipment being put on the European market after June 30th 2006 must contain lead mercury hexavalent chromium polybrominated biphenyls PBB and polybrominated diphenyl ethers PBDE and cadmium in maximum concentration values of 0 1 respective 0 01 by weight in homogenous materials only As these hazardous substances are currently used with semiconductors plastic
8. households has to be handled by the supplier manufacturer however it allows a greater flexibility in business to business relationships This pays tribute to the fact with industrial use electrical and electronical products are commonly integrated into larger and more complex environments or systems that cannot easily be split up again when it comes to their disposal at the end of their life cycles As N A T products are solely sold to industrial customers by special arrangement at time of purchase the customer agreed to take the responsibility for a WEEE compliant disposal of the used N A T product Moreover all N A T products are marked according to the directive with a crossed out bin to indicate that these products within the European Community must not be disposed with regular waste Version 1 2 O N A T GmbH 28 NPCIe 8560 8bE1 T1 J1 Technical Reference Manual If you have any questions on the policy of N A T regarding the Directive 2002 95 EC of the European Commission on the Restriction of the use of certain Hazardous Substances in Electrical and Electronic Equipment RoHS or the Directive 2002 95 EC of the European Commission on Waste Electrical and Electronic Equipment WEEE please contact N A T by phone or e mail 7 3 3 Compliance to CE Directive Compliance to the CE directive is declared A CE sign can be found on the PCB 7 3 4 Product Safety The board complies with EN60950 and UL1950 Version 1 2 O N A T
9. 1 connects the JTAG or programming port of the Lattice FPGA devices Table 8 JP1 Lattice Programming Port Pin Assignment 4 2 5 JP2 BDM and JTAG Connector The BDM port also called COP header can be used for debugging It is supported by major debug tool manufacturers Table 9 JP2 BDM and JTAG Connector Pin Assignment Version 1 2 O N A T GmbH 18 NPCIe 8560 8bE1 T1 J1 Technical Reference Manual 4 2 6 P11 P12 PMC Connectors Table 10 P11 P12 PMC Connectors Pin Assignment Pin Signal Signal Pin Pin amp Signal Signal Pin d ERAN TRSTA 3 TMS mo 4 5 INB amp INC 6 5 TDI GND 6 7 nce v 8 7 nD PMC RSvD 8 9 INTD PMCRSVD 10 9 PMCRSVD PMCRSVD 10 59 AD 0O2 AD O 60 f 59 GND PMCRSVD 60 Version 1 2 O N A T GmbH 19 NPCIe 8560 8E1 T1 J1 Technical Reference Manual 4 2 7 P13 PMC Connector Table 11 P13 PMC Connector Pin Assignment sapo cp crm oo Version 1 2 O N A T GmbH 20 NPCIe 8560 8bE1 T1 J1 Technical Reference Manual 4 2 8 P14 PMC Connector Configuration 2 3 Table 12 P14 PMC Connector Configuration 2 3 Pin Assignment P14 Configuration 2 P14 Configuration 3 Signal Signal Pin Signal Pin amp Pin gl Signal Pin 5 USER USER 6 5 Txclav TXADR4 6 7 USER USER 8 7 RXADR3 GND 8 9 USER USER
10. 11 NPCIe 8560 8bE1 T1 J1 Technical Reference Manual 3 2 Memory 3 2 1 DDR SDRAM The onboard DDR SDRAM memory is 64 bit wide its size is 128MB The interface to the DDR SDRAM is implemented in the MPC8560 By programming several registers the DDR RAM controller can be adapted to different RAM architectures 3 2 2 FLASH The NPCIe 8560 S8E1 T1 J1 provides a 16 bit wide FLASH PROM with a capacity of 16 64MB assembly option default 32MB This memory is connected to the demultiplexed upper 16 data bits DO 15 and to the latched address lines Demultiplexing of the local address data bus of the CPU as well as address latching is performed by an FPGA The FLASH PROM can be programmed either by the CPU by appropriate software or through the BDM port or by a PCI bus master 3 3 PCI Express Interface The NPCIe 8560 8E1 T1 J1 includes a x1 PCI Express interface which is implemented in a PEX8111 PCI X to PCIe bridge PLX The PCI Express interface is connected directly to the PCI Express connector whereas the PCI interface is connected to the MPC8560 CPU and the PMC connector The PCIe bridge may receive its reference clock either from the PCIe connector or from a local 100 MHz oscillator circuitry the clock source is programmable 3 4 E1 T1 J1 Line Interfaces The NPCIe 8560 8E1 T1 J1 carries a Maxim DS26518 framer which implements eight E1 T1 J1 interfaces These interfaces connect the framer to the front panel RJ45 connect
11. Bus N ne AIN i FLASH N X CT Bus H 110 S Eumun 1 2 lt gt ho d y NE dE pu N p e i K TDM Bus a E1 T1 J1 3 4 esa ctal I E1 Framer PLL EU T1J 5 6 DS26518 Zarlink reee I zL30100 EUTUM 7 8 Le alls SPI SP FLASH Version 1 2 O N A T GmbH 9 NPCIe 8560 8E1 T1 J1 Technical Reference Manual 2 3 Location Overview The position of important components is shown in the following location overview Depending on the board type it might be that the board does not include all components named in the location diagram Figure 2 NPCIe 8560 8E1 T1 J1 Location diagram Overview JAS Caner cmo 7 FULL LENGTH CARD 101 85 CA A ETH VY VW as 4 PHY 82 3 Eimas Framer ramum PTMC l Na l l D E l 5 z l EE EE O O l a KZ dL a Power l Supply 1 rd e g E wei E aa Re m on S B g e S Uy SS Dn BIC PLL a fH Lr2 loc PCle ref CLK 0 E1 T1 J1 Line Protection Version 1 2 O N A T GmbH 10 NPCIe 8560 8bE1 T1 J1 Technical Reference Manual 3 Board Features The NPCIe 8560 8E1 T1 J1 can be divided into a number of functional blocks which are described in the following paragraphs 3 1 3 1 1 3 1 2 CPU Processor Core The MPC8560 PowerQUICC III is a versatile communic
12. Manual of the PC Server main board used or of the PCIe system the board will be plugged into e Before installing or uninstalling the NPCIe 8560 8E1 T1 J1 switch off the power e Before touching integrated circuits ensure to take all require precautions for handling electrostatic devices e Ensure that the NPCIe 8560 8E1 T1 J1 is connected to the main board or to the PCIe backplane with the connector completely inserted e When operating the board in areas of strong electromagnetic radiation ensure that the module e is bolted the front panel or rack e and shielded by closed housing Version 1 2 O N A T GmbH 26 NPCIe 8560 8bE1 T1 J1 Technical Reference Manual 7 2 Installation Prerequisites and Requirements IMPORTANT Before powering up check this section for installation prerequisites and requirements 7 2 1 7 2 2 7 2 3 7 2 4 Requirements The installation requires only e an PCIe main board or a PCIe backplane for connecting the NPCIe 8560 8b1 T1 J1 Power supply The power supply for the NPCIe 8560 8E1 T1 31 must meet the following specifications e Required for the NPCIe 8560 8E1 T1 J1 e 12V 1 1A typ e 3 3V 0 9A typ e Required for the PMC Module e 3 3Vaux can be connected to 3 3aux of the PMC via LF2 or it can be connected to the local generated 3 3V for the PMC e All other PMC Power supplies 12V 5V 3 3V 12V are locally generated out of the 12V from the PCle connector That means the
13. NPCIe 8560 8bE1 T1 J1 Technical Reference Manual NPCIe 8560 8E1 T1 J1 Telecom PCIe Module Technical Reference Manual V1 2 HW Revision 1 0 NPCIe 8560 8E1 T1 J1 Technical Reference Manual The NPCIe 8560 8E1 T1 J1 has been designed by N A T GmbH Konrad Zuse Platz 9 D 53227 Bonn Phone 49 228 965 864 0 Fax 49 228 965 864 10 Internet http www nateurope com Version 1 2 O N A T GmbH 2 NPCIe 8560 8bE1 T1 J1 Technical Reference Manual Disclaimer The following documentation compiled by N A T GmbH henceforth called N A T represents the current status of the product s development The documentation is updated on a regular basis Any changes which might ensue including those necessitated by updated specifications are considered in the latest version of this documentation N A T is under no obligation to notify any person organization or institution of such changes or to make these changes public in any other way We must caution you that this publication could include technical inaccuracies or typographical errors N A T offers no warranty either expressed or implied for the contents of this documentation or for the product described therein including but not limited to the warranties of merchantability or the fitness of the product for any specific purpose In no event will N A T be liable for any loss of data or for errors in data utilization or processing resulting from the use
14. ations processor that integrates on one chip a high performance PowerPC RISC microprocessor running at 833MHz a very flexible system integration unit and many communications peripheral controllers that can be used in a variety of applications particularly in communications and networking systems The core is an embedded variant of the PowerPC e500 core with 32 Kbytes of instruction cache and 32 Kbytes of data cache To this primary cache adds 256 Kbytes of Level 2 cache The system interface unit SIU consists of a flexible memory controller that interfaces to almost any user defined memory system and many other peripherals making this device a complete system on a chip Processor Integrated I O The MPC8560 PowerQUICC III integrates a switch fabric and 2 10 100 1000 MB MACs which support various standard protocols The communications processor module CPM includes four serial communications controllers SCCs with the addition of three high performance communication channels that support new emerging protocols for example 155 Mbps ATM and Fast Ethernet The CPM frequency may be set up to 333 MHz The MPC8560 features dedicated hardware that can handle up to 256 full duplex time division multiplexed logical channels as well as DMA functionality executing memory to memory and memory to I O transfers Furthermore the MPC8560 integrates a 64 bit PCI PCI X interface and a 4 channel DMA controller Version 1 2 O N A T GmbH
15. ck can transfer data through the same physical ports that connects to the front panel interface or the PTMC The iTDM interface conforms to the SFP 0 and SFP 1 specifications 3 8 FC Devices The NPCIe 8560 8E1 T1 J1 features an I C link which is connected to the MPC8560 DC interface and to a couple of local devices The following devices are connected e An EEPROM for storage of board specific information 24C08 e Atemperature sensor LM75 which is located near the MPC8560 CPU to sense the processor temperature e Areal time clock device DS1339C Version 1 2 O N A T GmbH 13 NPCIe 8560 8E1 T1 J1 Technical Reference Manual 4 Hardware 4 1 Front Panel and LEDs The following figures shows the LEDs placed on the front panel of the NPCIe 8560 8b1 T1 J1 Figure 3 NPCIe 8560 8E1 T1 J1 Front Panel View ETH E ES TT TT LED1 LED2 e TA sf The NPCIe 8560 8E1 T1 J1 module is equipped with 2 LEDs which are controlled by the Ethernet PHY They are integrated in the RJ45 Ethernet interface jack LED1 is showing the link status and LED2 shows the activity Please refer to Chapter 4 2 for detailed information about the front panel connectors Version 1 2 O N A T GmbH 14 NPCIe 8560 8E1 T1 J1 Technical Reference Manual 4 2 Connectors and Switches Figure 4 NPCIe 8560 8bE1 T1 J1 Connector and Switch location Overview 101 85 mt e P14 P13
16. d JTAG Connector nana ora nana ahhh nana 18 4 2 6 PIA PI2 ME Connectors ener ee A a eee e ean Eva Nea aen 19 4 2 7 PI3 PMC enee 20 4 2 8 P14 PMC Connector Configuration Z A 21 4 2 9 S52 RS232 lee Te e 22 4 2 10 DIP SW1 Flash Half Select PCIe Bridge Direction 22 4 2 10 1 DIP SW1 Switch 1 Boot FLASH Select Switch 22 4 2 10 2 DIP SW1 Switch 2 PCIe Bridge Direction Switch 23 4 2 11 LEI Write Protect Pin Solder Pied 23 4 2 12 LF2 Voltage Source Solder Field oooococcccccccconccconcccnnnncnnncnnnnconnncnnnnns 23 5 NPCIE 8560 8E1 T1 J1 PROGRAMMING NOTES nennen nnn 24 6 BOARD SPECIFICATION 522225 5 2 ERR EKEKE ENN REENEN NEEN KSE N REN 25 Version 1 2 O N A T GmbH 4 NPCIe 8560 8bE1 T1 J1 Technical Reference Manual 7 INSTALLATION en cnnnee NEE KEE EE usas eua sunu unn 26 7 1 SAFETY NOTE ervan mE 26 7 2 INSTALLATION PREREQUISITES AND REOUIREMENTS 27 7 2 1 Reqg iremoehlts sdei a A AAA Ts FREE A oases 27 7 2 2 POWER SUP A adda ee ees 27 7 2 3 Automatic PoWer EE 27 7 2 4 Thermal Considerations 27 7 3 STATEMENT ON ENVIRONMENTAL PROTECTION sccesceeceeeee tees tees tees tees eens tans tans eaaetas 28 7 3 1 Compliance to RoHS Directive 28 7 3 2 Compliance to WEEE Directive 28 7 3 3 Compliance to CE Directive 29 7 3 4 Product Safety aoc a e T eer ve Due erat vue A 29 8 KNOWN BUGS RESTRICTIONS sen
17. ess extension slots Version 1 2 O N A T GmbH NPCIe 8560 8bE1 T1 J1 Technical Reference Manual 2 Overview 2 1 Major Features e PowerQUICC III MPC8560 based Embedded PowerPC Architecture e 128 MB main Memory DDR SDRAM e 16 64 MB FLASH default 32MB e x1 PCI Express Interface Rev 1 1 e 8x E1 T1 J1 Primary Rate Line Interface e 1000BaseT Ethernet channel on Front Panel e iTDM Interface e PTMC Interface for configuration 2 3 e 32 bit PCI bus e CT bus e Ethernet e RS232 serial I O Version 1 2 O N A T GmbH 8 NPCIe 8560 8E1 T1 J1 Technical Reference Manual 2 2 Block Diagram The following figure shows a block diagram of the NPCIe 8560 8E1 T1 J1 Figure 1 NPCIe 8560 8bE1 T1 J1 Block Diagram Overview 8 o ES 2 c a 8 x PCle xi N PCle to A PCI 32 bit N en PCI bridge AJ O 8 S 1GbE Ethernet Ge 4 sm TE ee 120 N RTC S e o o D 38 PTMC site MPC8560 SA NI S83 128 256MB 838MHz meum Bel CFG 2 or 5 DDR zh i 888 F y i N 828 e SDRAM ML PowerQUICC3 258 Plate SUD FPGA EE 333MHz B N Ente y Lattice ECP3 RS232 i Console p 16 64MB Local
18. nerated 3 3V Version 1 2 O N A T GmbH 23 NPCIe 8560 8E1 T1 J1 Technical Reference Manual 5 NPCIe 8560 8E1 T1 J1 Programming Notes TBD Note This chapter will be completed in a later version of the User s Manual For the time being contact N A T for further assistance on programming Version 1 2 O N A T GmbH 24 NPCIe 8560 8bE1 T1 J1 Technical Reference Manual 6 Board Specification Table 17 NPCIe 8560 8bE1 T1 J1 Features PowerQUICC III MPC8560 833MHz based add in card 111 15mm x 312 00mm Firmware OKI LINUXBSP on request MPC8560 833MHz Storage Temperature 40 C 85 C Humidity 10 90 rh non condensing Standards compliance PCI Express Base Specification Rev 1 1 PCI Express CEM Specification Rev 1 1 PICMG 2 15 Rev 1 0 ITU T G 703 for E1 T1 Standard ITU T G 823 Jitter Attenuation Version 1 2 N A T GmbH 25 NPCIe 8560 8bE1 T1 J1 Technical Reference Manual 7 Installation 7 1 Safety Note To ensure proper functioning of the NPCIe 8560 8E1 T1 31 during its usual lifetime take the following precautions before handling the board CAUTION Electrostatic discharge and incorrect board installation and uninstallation can damage circuits or shorten their lifetime e Before installing or uninstalling the NPCIe 8560 8E1 T1 J1 read this installation section e Before installing or uninstalling the NPCIe 8560 8E1 T1 J1 read the Installation Guide and the User s
19. of this product or the documentation In particular N A T will not be responsible for any direct or indirect damages including lost profits lost savings delays or interruptions in the flow of business activities including but not limited to special incidental consequential or other similar damages arising out of the use of or inability to use this product or the associated documentation even if N A T or any authorized N A T representative has been advised of the possibility of such damages The use of registered names trademarks etc in this publication does not imply even in the absence of a specific statement that such names are exempt from the relevant protective laws and regulations patent laws trade mark laws etc and therefore free for general use In no case does N A T guarantee that the information given in this documentation is free of such third party rights Neither this documentation nor any part thereof may be copied translated or reduced to any electronic medium or machine form without the prior written consent from N A T GmbH This product and the associated documentation is governed by the N A T General Conditions and Terms of Delivery and Payment Note The release of the Hardware Manual is related to a certain HW board revision given in the document title For HW revisions earlier than the one given in the document title please contact N A T for the corresponding older Hardware Manual release
20. or S3 Timing and interface characteristics can be set up by software within the DS26518 The line interfaces conform to EN60950 and G 703 G 823 litter Attenuation The front panel RJ45 connector S3 consists of 4 RJ45 jacks with integrated LEDs In order to support 8 E1 T1 J1 interfaces each RJ45 jack carries 2 E1 T1 J1 interfaces The LEDs are bi colored and programmable through registers which reside within the FPGA 3 5 Ethernet The NPCIe 8560 8E1 T1 31 implements a Gigabit Ethernet interface 1000Base T at the front panel that is connected to the onboard FPGA All other onboard devices are connected to the same FPGA which implements a HUB functionality that allows all devices to access the front interface The connected devices are the TSEC Ethernet MAC of the MPC8560 CPU as well as the PMC PTMC connected to the FPGA via RMII and the iTDM block implemented in the FPGA The PMC is only connected via a 100MBit interface The Broadcom BCM5461 Ethernet PHY is connected to the FPGA via GMII interface It connects to the front panel connector S1 Version 1 2 O N A T GmbH 12 NPCIe 8560 8bE1 T1 J1 Technical Reference Manual 3 6 PTMC Interface The NPCIe 8560 8bE1 T1 J1 implements a CT Bus H 110 that connects to the PMC connector 3 7 ITDM The NPCIe 8560 8bE1 T1 J1 implements a serial iTDM interface based on Ethernet The iTDM Block implemented in the FPGA has also access to the Ethernet Hub block Therefore the iTDM Blo
21. s i e semiconductor packages connectors and soldering tin any hardware product is affected by the RoHS directive if it does not belong to one of the groups of products exempted from the RoHS directive Although many of hardware products of N A T are exempted from the RoHS directive it is a declared policy of N A T to provide all products fully compliant to the RoHS directive as soon as possible For this purpose since January 31st 2005 N A T is requesting RoHS compliant deliveries from its suppliers Special attention and care has been paid to the production cycle so that wherever and whenever possible RoHS components are used with N A T hardware products already Compliance to WEEE Directive Directive 2002 95 EC of the European Commission on Waste Electrical and Electronic Equipment WEEE predicts that every manufacturer of electrical and electronical equipment which is put on the European market has to contribute to the reuse recycling and other forms of recovery of such waste so as to reduce disposal Moreover this directive refers to the Directive 2002 95 EC of the European Commission on the Restriction of the use of certain Hazardous Substances in Electrical and Electronic Equipment RoHS Having its main focus on private persons and households using such electrical and electronic equipment the directive also affects business to business relationships The directive is quite restrictive on how such waste of private persons and
22. sere KEE KEE nennen neant anna 30 APPENDIX A REFERENCE DOCUMENTATION e eene nnn 31 APPENDIX B DOCUMENT S HISTORY KKK KEE EEN ENER annuntiat 32 List of Tables Table 1 List of used abbreviations 0ooococcccnccnnnccnnnconancnnnncnnnnrnnnnrnnnnrnrnnrnranrnrannnnnn 6 Table 2 P1 PCIe Connector Pin Aesionment mnn 16 Table 3 S1 Ethernet Connector Pin Aesionment sess 16 Table 4 S3a ISDN Connector Pin Aeslonment esses 17 Table 5 S3b ISDN Connector Pin Aesignment rra nana 17 Table 6 S3c ISDN Connector Pin Assignment ssssssssseem m 17 Table 7 S3d ISDN Connector Pin Aesignment cee eee eee eee e eee teats eens teens 17 Table 8 JP1 Lattice Programming Port Pin Assignment EE 18 Table 9 JP2 BDM and JTAG Connector Pin Assignment esses 18 Table 10 P11 P12 PMC Connectors Pin Aeslonment teens teste eee ee teens 19 Table 11 P13 PMC Connector Pin Assignment sssssssssssen me 20 Table 12 P14 PMC Connector Configuration 2 3 Pin Assignment 21 Table 13 S2 RS232 Connector Pin Assignment cece eect eee ee eee e eee e neta tees 22 Table 14 DIP SW1 Pin Assignment Overvlew eee e eee ee etna teeta ea eeeeaee es 22 Table 15 DIP SW1 Switch 1 Boot Flash Select Pin Assignment 22 Table 16 DIP SW1 Switch 2 PCIe Bridge Direction Pin Assignment 23 Table 17 NPCIe
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