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AC100 User Manual

1. SRCI SRC2 ADC_DIGITAL DACCLK o DAC_DIGITAL HPF amp AGC HPF amp DRC MN M U jSYSCLK DVOMISER x IF1_TX RX AIF psicLK 5 gt ep AIFI_BCLK LRCK_CTL U 5 4 DPLL mee TP xp Js M BCLK2A F2 M 1282CLK ACLK2 x 1 ERU gt U AIF2_BCLK LRCK_CTL x J m BCLK3A 5 AIF3 TX RX U gt AIF3_BCLK LRCK_CTL _____ 2 ADDA gt E 4 z REGISTER PART 2 REGISTER PART 1 HMICBIAS DETECT 2 RTC 22 TWI RSB osc 7 CK32K OUTPUT 9 Figure6 Clocking Management 11 3 PLL A Phase Locked Loop PLL is used to provide a flexible input clock range from 128KHz to 24MHz source of the PLL can be set to MCLK1 MCLK2 BCLKI BCLK2 by setting register The PLL output is always used to provide the system clock SYSCLK of AUDIO codec when 24 576MHz or 22 5792MHz can not be provided from MCLK The PLL transmit formula as below FOUT FIN N M QK 1 N N_i 0 2 N_f Table 1 clock setting for SYSCLK 24 576 MHz FIN M N K FOUT 128K 1 576 1 24 576 192K 1 384 1 24 576 256K 1 288 1 24 576 384 1 192 1 24 576 i m m 1 24 576M 6M 25 307 2 1 24 576M 13
2. z z gf z E g g a z g g E d g 8 8 dz a 2 2 8 System Clock Path 2 5 z xp 5 z B x x I25 PCM Interface Ta PCM Interface POL Interface LR L R ho e Lok ix Pilg lily gid RS gt L R Channel Source Exchange Channel Source Exchange acu Ly H x BCLK2 Ly Soo Siloti 501 iri ll ite tr DAP DAP j DAP SPKOUT2P icm puri m lt m G gt SPKOUT2N II II Z lt gt ya SPKOUTIP gt DMIC DATA CEPIT SPKOUTIN p MiciP MICIN m H 1 gt MaN iDH 1 T DACL EAROUTP m 192 ADCL Ere A I MIXL 5 oi m gt MIC3N 9 0 BR L7 EAROUTN LINEINL N m gt gt LINEINR P E T gt B gt m gt _ bis le 1 1 a _ 8 HPOUTL 1 gt L67 ADCR AT 1A DACL Tt 4 MIXL IPI Kk im AXIR i m i e EL m gt Al Bi HPOUTR H TELE ary a xx gt gt 1 2 gt gt gt 4 lt 5 1 LINEOUTP Mies gt d anu mH LINEOUTN gt MIXR Se gt gt Figure 2 Data Path Diagram 5 Pin Assignment 1 33 SDIN3 1 28
3. m S 5 8 sock B i z 9 S X gt 22255 8959 z z g 5 8 g 25254 E a E 2 5 adina 9 gt E O 0 0 ODO OOO O O Q O Hee 1002 gt O IRQ RTC RTC LO AVCC 4 DS PCM PCM Mono 7 Reference 1 gt VRAI Voltage lt No SRC AVCC MBIAS MBIAS AVCC Charge HBIAS gt HBIAS Pump HPOUTL MixerL Boost L4 ADC_L DAC_L F HPOUTR ADC 3 DAC c Volume AGC Volume Headphone 4 Input amp Mixer High High Filter ET Filter iR EAROUTP ADC_R DAC_R E EAROUTN Output Earpiece Mixer MixerL SPOLP Mi R gt A E SPOLN gt Left Speak d MixerL SPORP gt E MixerR EU gt d SPORN Right Speak gt MIC gt mic I LINEOUTP gt O LINEOUTN gt Lineout Figure 1 Functional Block Diagram 4 2 Data Path Diagram
4. Powers 100 User Manual Revision 1 0 2014 06 10 Copyright 2014 X Powers Technology All Rights Reserved Declaration This documentation is the original work and copyrighted property of X Powers Reproduction in whole or in part must obtain the written approval of X Powers and give clear acknowledgement to the copyright owner The information furnished by X Powers is believed to be accurate and reliable X Powers reserves the right to make changes in circuit design and or specifications at any time without notice X Powers does not assume any responsibility and liability for its use Nor for any infringements of patents or other rights of the third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Allwinner This documentation neither states nor implies warranty of any kind including fitness for any particular application Third party licences may be required to implement the solution product Customers shall be solely responsible to obtain all appropriately required third party licences X Powers shall not be liable for any licence fee or royalty due in respect of any required third party licence X Powers shall have no warranty indemnity or other obligations with respect to matters covered under any required third party licence About Documentation This documentation of AC100 is intended to be used by board level product designers a
5. 3 0 0 3 0 7 Vit Low Level Input Voltage VCCIO 1 8V 0 3 0 7 VCCIO 3 0v 2 7 High Level Input Voltage V VCCIO 1 8V 1 5 3 0 0 4 VoL Low Level Input Voltage V VCCIO 1 8V NA 0 4 Io Tri state Output Leakage Current TBD TBD TBD uA CN Input Capacitance NA NA 5 pF 5 9 Analog Performance Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UINT DAC Output Path DAC to Headphone on HPOUTL or HPOUTR R 10kQ Performance FScale Output Level 0dB 1KHz 0 9 Vrms SNR A weighted OdB 1KHz 100 dB THD N NO Aweight OdB 1KHz 84 Crosstalk L R OdB 1KHz 88 88 dB DAC to Headphone on HPOUTL or HPOUTR R 16Q FScale Output Level OdB 1KHz 0 5 Vrms SNR A weighted OdB 1KHz 99 dB THD N P0 15mW OdB 1KHz 81 dB THD N P0 5mW OdB 1KHz 82 dB Crosstalk L R OdB 1KHz 82 82 DAC to Headphone on HPOUTL 320 FScale Output Level OdB 1KHz 0 7 Vrms SNR A weighted OdB 1KHz 100 dB THD N P0 15mW OdB 1KHz 83 THD N P0 5mW OdB 1KHz 83 dB Crosstalk L R OdB 1KHz 86 86 dB DAC to Earpiece Driver on EAROUTP and EAROUTN R 16Q FScale Output Level OdB 1KHz 1 0 Vrms SNR A weighted OdB 1KHz 100 dB THD N P0 12mW OdB 1KHz 81 dB DC Offset at load OdB 1KHz 2 mV DAC to SPK signal on SPKOUTLP and SP
6. Default 0 0000 Register Name AC_DAC_DAPLGDEC Bit Read Write Default Description Gain smooth filter decay time coefficient setting the 15 0 R W 0x0000 coefficient reg a7 10 0 reg a8 is 3 24 format 2s complement Reg a9h DAC DAP High Gain Attack Time Coef Register Default 0x0100 Register Name AC DAC DAPHGATC Bit Read Write Default Description 15 11 Gain smooth filter attack time coefficient setting the 10 0 R W 0x0100 coefficient reg a9 10 0 reg aa is 3 24 format 2s complement Reg aah DAC DAP Low Gain Attack Time Coef Register Default 0x0000 Register Name AC DAC DAPLGATC Bit Read Write Default Description 0 0000 Gain smooth filter attack time coefficient setting the coefficient reg a9 10 0 reg aa is 3 24 format 2s complement Reg DAC DAP High Energy Threshold Register Default OXOAFB Register Name AC DAC DAPHETHD Bit Read Write 15 0 R W Default 0x04FB Description The DRC Energy compress threshold parameter T setting the reg ab reg ac is 8 24 format 2s complement Reg ach_DAC DAP Low Energy Threshold Register Default OXOEDO Register Name AC_DAC_DAPLETHD Bit Read Write Default Description The DRC Energy compress threshold parameter 15 0 R W Ox9EDO setting the T ab reg
7. LSPK EN 5 R W 0x0 Left Speaker Enable 0 Disable 1 Enable 5 VOL Right amp Left speaker VOLume control 4 0 R W 0 0 00000 amp 00001 Reg 59h Lineout Control Register Total 31 level from OdB to 43 5dB 1 5db step mute when Default 0x8060 Register Name LOUT CTRL Bit R W Default Description 15 8 R W 0x80 Reservd LINEOUTG 20 R W 0x3 Line out Gain Control From 4 5dB to 6dB 1 5dB step default is OdB R W 0x0 LINEOUTEN 4 Line out Enable 0 disable 1 enable LINEOUTSO 3 R W 0x0 Boost stage to Line out mute 0 Mute 1 On 2 R W 0x0 LINEOUTSI MIC2 Boost stage to Line out mute 0 Mute 1 On R W 0 0 R W 0x0 LINEOUTS2 Right Output mixer to Line out mute 0 Mute 1 On LINEOUTS3 Left Output mixer to Line out mute 0 Mute 1 On Reg 80h_ADC DAP Left Status Register Default 0 0000 Register Name AC_ADC_DAPLSTA Bit Read Write Default Description 15 10 R 0x0 Reserved 9 R 0x0 Left AGC saturation flag 8 R 0x0 Left AGC noise threshold flag Left Gain applied by AGC 7 1 format 2s complement 20dB 40dB 0 5B step 0x50 40dB 7 0 R 0x0 Ox4F 39 5dB 0x00 00dB OxFF 0 5dB Reg 81h ADC DAP Right Status Register Default 0x0000 Register Name AC ADC DAPRSTA Bit Read Write Default Description 11 10 R 0x0 Reserved 9 R 0x0 Right AGC saturation flag 8 R
8. 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01 119 25dB 15 8 R W OxA0 A Ox9F 0 75dB Ox AO OdB 1 0 75dB OxFF 71 25dB ADC VOL R ADC left channel volume 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01 119 25dB 7 0 R W 2 Ox9F 0 75dB Ox AO OdB 1 0 75dB OxFF 71 25dB Reg 44h HMIC Control 1 Register Default 0x0000 Register Name HMIC CTRL1 Bit Read Write Default Description 15 12 R W 0x0 HMIC_M debounce when Key down or key up 11 8 R W 0x0 HMIC_N debounce when earphone plug in or pull out R W 0x0 HMIC DATA IRQ MODE Hmic Data Irq Mode Select 0 Hmic data irq once after key down 1 Hmic data irq from key down util key up 6 5 R W 0 0 HMIC HYSTERESIS Hmic Hysteresis Threshold1 00 no Hysteresis 01 Pull Out when Data lt Hmic_th2 1 10 Pull Out when Data lt Hmic_th2 2 11 Pull Out when Data lt Hmic_th2 3 R W 0 0 PULLOUT IRQ EN Hmic Earphone Pull out Irq Enable 00 disable 11 enable R W 0 0 HMIC PLUGIN IRQ Hmic Earphone Plug in Irq Enable 00 disable 11 enable R W 0 0 KEYUP Hmic Key Up Irq Enable 00 disable 11 enable R W 0 0 KEYDOWN Hmic Key Down Irq Enable 00 disable 11 enable R W 0 0 DAT
9. Filter Filter DigiMic 1b gt 5b Figure 28 Digital Microphone Block Diagram Digital Microphone timing as below CLK DAT Z DataL XZ DataR ZX DataL KX ZX Datar X Z DataL DataR Figure 29 Digital Microphone timing Digital Microphone application as below Voo Select Gnd Select Figure 30 Digital Microphone Application 11 12 Audio Jack Detect The microphone bias output pin HBIAS provide a low noise reference voltage suitable for biasing electrets type microphones and the associated external resistor biasing network Hbias is designed to drive headset microphone and a bias current detect function is provided for external accessory detection by measuring the Hbias current In some application it s used to detect the insertion removal of a aduio jack and the button press These events will cause a significant change in bias current flow which can be detected and used to generate a signal to the processor When HBIAS current detect is enabled 5 bit ADC will send out sample data at 16 32 64 128Hz clock rate Digital logic trigger an interrupt event controlled by register setting when the data is changed The digital circuit generate five IRQ signals that can be disabled by register the data from ADC can be read from register HMIC STATUS Bit12 8 IRQ Timing Diagram P M Key2 iN EarPhones Plu
10. is 8 24 format 2s complement Reg DAC DAP High Gain K Parameter Register Default 0x0780 Register Name AC DAC DAPHGKPA Bit Read Write Default Description 15 11 10 0 0x0780 The DRC gain Uy slope k parameter setting the reg ad 10 0 reg ae is 3 24 format 2s complement Reg aeh DAC DAP Low Gain K Parameter Register Default 0x0000 Register Name AC DAC DAPLGKPA Bit Read Write Default Description 15 0 0x0000 The DRC gain slope parameter setting the reg ad 10 0 reg ae is 3 24 format 2s complement Reg afh DAC DAP High Gain Offset Parameter Register Default 0x0100 Register Name AC DAC DAPHGOPA Bit Read Write Default Description 15 13 The DRC gain curve offset parameter setting the reg 12 0 R W 0x0100 af 12 0 reg 60 is 5 24 format 2s complement Reg b h DAC DAP Low Gain Offset Parameter Register Default 0x0000 Register Name AC DAC DAPLGOPA Bit Read Write Default Description 0 0000 DRC gain curve offset parameter setting the reg af 12 0 regb0 is 5 24 format 2s complement Reg blh DAC DAP Optimum Register Default 0x0000 Register Name AC DAC DAPOPT Bit Read Write Default Description 15 6 DRC gain defaut value setting 5 R W 0 0 The default gain is 1
11. mess uet E 5 9 Mm LSBi IMSB LSBi 6050 517 6 0 SIZE y I2S Justified mode Figure 15 125 Justified mode LRCK DIV BCLK Left channel Right channel SPINE Fee IMSB LSBi I MSB LSBi 08 SIZE g ORD SIZE Left Justified mode Figure 16 Left Justified mode LRCK DIV BCLK Left channel Right channel LRCK UUL uH lt SDOUT IMSB LSBi LSBi SIZE Y Right Justified mode Figure 17 Right Justified mode Short I Short BCLK I LRCK bg SDIN Left channel Right channel DO 1 5 LSBiMSB LSBi pWORD_SIZE y 00 5125 mode A BCLK INV 0 Figure 18 mode A LRCK INV 0 lg KY Short I Short LRCK csse E Left channel Right channel du que n r2 ens DERE MSB LSB MSB LSBi 1050 5176 p ORD SIZE Pem mode B BCLK INV 1 Figure 19 Pcm mode B LRCK INV 1 LRCK DIV Left channel Right channel m d Se a 12 IMSB LSBIMSB LSBI WORD SIZE WORD SIZE Pem mode A BCLK INV 0 Figure 20 Pcm mode mono LRCK_INV 0 LRCK DIV Short I short BCLK so LRCK Hur zar o E Pr eee sees ERI Tue Left channel Right channel HOENERS
12. Default 0x0000 Register Name 125 SR Bit Read Write Default Description 15 12 R W 0 0 ADDA FS DSI ADDA Sample Rate synchronised with I2S1 clock zone 0000 8KHz 0001 11 025KHz 0010 12KHz 0011 16KHz 0100 22 05KHz 0101 24KHz 0110 32KHz 0111 44 1KHz 1000 48KHz 1001 96KHz 1010 192KHz Other Reserved 11 8 R W 0 0 ADDA FS 1052 ADDA Sample Rate synchronised with 1252 clock zone 0000 8KHz 0001 11 025KHz 0010 12KHz 0011 16KHz 0100 22 05KHz 0101 24KHz 0110 32KHz 0111 44 1 KHz 1000 48KHz 1001 96KHz 1010 192KHz Other Reserved R W 0x0 SRC1_ENA SRC1 Enable SRC1 Performs sample rate conversion of digital audio input to the AC100 0 Disable 1 Enable R W 0x0 SRC1_SRC From which the input data will come 0 I2S1 DAC Timeslot 0 1 I2S2 DAC R W 0x0 SRC2_ENA SRC2 Enable SRC2 Performs sample rate conversion of digital audio output from the 100 0 Disable 1 Enable R W 0 0 SRC2 SRC To which the converted data will be output 0 DS1 ADC Timeslot 0 1 I2S2 ADC Reg 10h_I2S1 BCLK LRCK Control Register Default 0x0000 Bit Read Write Default Register Name DSILCK Description 15 R W 0 0 1251 MSTR MOD 1251 Audio Interface mode select 0 Master mode 1 Slave mode 14 R W 0x0 I2S1_BCLK_INV I2S1 BCLK Polarity
13. MICI to L or R output mixer Gain Control From 4 5dB to 6dB 1 5dB step default is OdB MIC2G 2 to L or R output mixer Gain Control From 4 5dB to 6dB 1 5dB step default is OdB 2 0 0x3 LINEING LINEINL R to L R output mixer Gain Control From 4 5dB to 6dB 1 5dB step default is OdB Reg 56h Headphone Output Control Register Default 0x0001 Register Name HPOUT Bit R W Default Description 15 R W 0 0 5 Right Headphone Power Amplifier PA Input Source Select 0 DACR 1 Right Analog Mixer 14 0x0 LHPS Left Headphone Power Amplifier PA Input Source Select 0 DACL 1 Left Analog Mixer 13 12 0x0 0x0 RHPPA_MUTE All input source to Right Headphone PA mute including Right Output mixer and Internal DACR 0 Mute 1 On LHPPA_MUTE All input source to Left Headphone PA mute including Left Output mixer and Internal DACL 0 1 On 0 0 Right amp Left Headphone Power Amplifier Enable 0 Disable 1 Enable 10 9 4 0 0 HP VOL Headphone Volume Control HPVOL Total 64 level from OdB to 62dB 1dB step mute when 000000 3 2 0 0 HPPA DEL Headphone delay time when start up 00 4ms 01 8ms 10 16ms 11 32ms 1 0 0x1 HPPA IS Headphone output stage current select 00 is minimum 11 is maximum Reg 57h
14. VDD Digital power for Audio digital it can generate by inner LDO 0 3 1 3 IOI Digital power for digital I O buffer 125 181252 0 3 3 63 102 Digital power for digital I O buffer 125 181253 0 3 3 63 CPVDD Analog power for headphone charge pump 0 3 2 0 VCC_RTC LDO Input power for RTC 0 3 3 63 V VIO RTC Digital power for RTC digital core it can be generate by inner LDO 0 3 1 52 V Operating Ambient Temperature 20 85 6 Vesp ESD 4 E KV 8 2 Recommended Operating Conditions Parameter Description MIN TPY MAX Unit LDO IN LDO Input power for AudioCODEC 1 35 1 8 1 5 3 63 V VDD CORE Digital power for Audio digital core it can be generate by inner 1 08 12 1 32 LDO IOI Digital power for digital I O buffer 125 181252 1 8 3 3 3 63 V VCC IO2 Digital power for digital I O buffer 125 181253 1 8 3 3 3 63 CPVDD Analog power for headphone charge pump 12 1 8 1 98 VCC RIC LDO Input power for RTC 1 35 1 8 3 3 3 63 VIO Digital power for digital core it can be generate by inner 1 08 1 2 1 32 LDO GND AGND Ground reference 0 V 8 3 Static Characteristics Symbol Parameter Test condition Min Typical Max Units VCCIO1 0 3 Vin Input Voltage Range 0 3 2 0 3 VCCIO 3 0v 2 4 3 6 High Level Input Voltage V VCCIO 1 8V 14 1 98
15. 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01 119 25dB Ox9F 0 75dB 0 0dB OxA1 0 75dB OxFF 71 25dB Reg 15h 1251 Volume Control 2 Register Default 0xA0A0 Register 1251 VOL CTRL2 Bit Read Write Default Description 15 8 R W OxAO 251 ADCLI VOL 1251 Timeslot 1 left channel volume 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01 119 25dB Ox9F 0 75dB 0xA0 OdB 1 0 75dB OxFF 71 25dB 7 0 R W OxAO DS1 ADCRI VOL 1251 ADC Timeslot 1 right channel volume 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01 119 25dB Ox9F 0 75dB 0xA0 OdB 1 0 75dB OxFF 71 25dB Reg 16h I2S1 Volume Control 3 Register Default 0xA0A0 Register Name 1251 VOL CTRL3 Bit Read Write Default Description 15 8 R W OxAO DS1 DACLO VOL 1251 DAC Timeslot 0 left channel volume 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01 119 25dB Ox9F 0 75dB 0xA0 OdB 1 0 75dB OxFF 71 254 7 0 R W OxAO DS1 DACRO VOL 1251 DAC Timeslot 0 right channel volume 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01 119 25dB Ox9F 0 75dB 0xA0 0dB 1 0 75dB OxFF 71 25dB Reg 17h_I2S1 Volume Control 4 Register Default 0xA0A0 Register Name DD 1 VOL CTRLA Bit Read Write 15 8 R W Default
16. 15 R W 0 0 Vie enable bit 0 Disable minute alarm 1 Enable minute alarm 14 7 ALM MIN SET 6 0 R W 0x0 These bits represent the current minute value coded in BCD format The value should be from 0 to 59 Reg dah Alarm Hours Register Default 0x0001 Register Name ALM REG Bit Read Write Default Description ENA Hour alarm enable bit 15 R W 0 0 0 Disable hour alarm 1 Enable hour alarm 14 9 AM PM SEL AM PM select 8 R W 0 0 0 1 PM 7 6 ALM_HOU_SET 5 0 R W 0 1 These bits represent the current hour value coded in BCD format The value should be from to 23 Reg dbh Alarm Weekdays Register Default 0x0000 Register Name ALM WEEK REG Bit Read Write Default Description ALM WEE ENA Week alarm enable bit 15 R W 0x0 0 Disable hour alarm 1 Enable hour alarm 14 3 2 0 R W 0x0 ALM_WEE_SET These bits represent the current weekday value coded BCD format The value should be from 0 to 6 000 Sunday 001 Monday 010 Tuesday 011 Wednesday 100 Thursday 101 Friday 110 Saturday Reg Alarm Days Register Default 0x0001 Register Name ALM DAY REG Bit Read Write Default Description ALM DAY ENA Day alarm enable bit 15 R W 0 0 0 Disable day alarm 1 Enable day alarm 14 6 ALM DAY
17. 6 HBIAS O Second bias voltage output for headset microphone 26 HPOUTFB I Pseudo differential headphone ground reference 29 CPN Charge pump flying back capacitor 31 CPP Charge pump flying back capacitor 22 VRAI Internal reference voltage 21 VRA2 O Internal reference voltage 9 VRP O Internal reference voltage 12 VRN Internal reference voltage Power Ground 16 AVCC P Analog power 13 AGND G Analog ground 32 CPVDD Analog power for headphone charge pump 28 CPVEE P Charge pump negative decoupling Pin 23 VPP P Headphone positive voltage input 24 VEE P Headphone PA negative voltage input 62 VDD CORE P Digital power for digital core 44 VCC IOI P Digital power for digital I O buffer 125161252 35 VCC 1O2 Digital power for digital I O buffer 1253 63 LDOIN P Input power for Audio LDO 59 VIO RIC P Digital power for RTC 58 VCC P Input power for LDO 69 GND G Digital ground Others 1 30 39 52 Not connected 8 Electrical Characteristics 8 1 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only Permanent damage to the device may be caused by continuously operating at or beyond these limits Device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified Symbol Parameter MIN MAX Unit LDO IN LDO Input power for AudioCODEC 0 3 3 63
18. Manual setting ratio high 10 bit Reg b9h_SRC1 Control 2 Register Default 0x0000 Register Name SRC1 CTROL2 Bit Read Write 15 0 R W Default 0 0 Description 5 RATI StET 15 0 Manual setting ratio low 16 bi Reg 5 Control 3 Register Default 0x0040 Register Name SRC1 CTRL3 Bit Read Write Default Description 5 FIFO LEV 5 0 15 10 R 0x0 SRCI FIFO Level low 6 bit 5 VAL 25 16 9 0 R 0x40 E P Calculated ratio high 10 bit Reg bbh_SRC1 Control 4 Register Default 0 0000 Register Name SRC1_CTRL4 Bit Read Write Default Description SRC1_RATI_VAL_ 15 0 15 0 R 0 0 Calculated ratio low 16 bit Reg bch_SRC2 Control 1 Register Default 0x0000 Register Name SRC2 CTRL1 Bit Read Write Default Description SRC2 RATI ENA 15 R W 0 0 SRC2 Manual setting ratio enable O disable 1 enable SRC2 STS 14 R 0x0 SRC2 Ratio lock status O not locked 1 locked SRC2 13 R 0x0 SRC2 FIFO Overflow status O normal 1 overflowed SRC2 FIFO 8 6 12 10 R 0 0 SRC2 FIFO Level high 3 bit SRC2 RATI SET 25 16 9 0 R W 0 0 M Manual setting ratio high 10 bit Reg bdh SRC2 Control 2 Register Default 0x0000 Register Name SRC2 CTRL2 Bit Read Write Default Description SRC2 RATI SET 15 0 15 0 R W 0x0 Ma
19. OxAO Description 1251 DACLI VOL 1251 DAC Timeslot 1 left channel volume 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01 119 25dB Ox9F 0 75dB 0dB 0 75dB OxFF 71 254 7 0 OxAO DS1 DACRI VOL 1251 DAC Timeslot 1 right channel volume 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01 119 25dB Ox9F 0 75dB 0xA0 0dB 1 0 75dB OxFF 71 25dB Reg 18h 1251 Digital Mixer Gain Control Register Default 0x0000 Register Name 1251 GAIN Bit 15 12 11 8 Read Write Default 0x0 0x0 Description 1251 ADCLO GAIN 1251 ADC Timeslot 0 left channel mixer gain control 0 0dB 1 6dB Bit15 DS1 DAOL data Bit14 1052 DACL data Bit13 ADCL data Bit12 1252 DACR data 1251 ADCRO GAIN 1281 ADC Timeslot 0 right channel mixer gain control 0 0dB 1 6dB Bit11l DS1 DAOR data Bit10 I282 DACR data Bit9 ADCR data Bit8 I282 DACL data 7 6 R W 0 0 1251 ADCLI GAIN 1251 ADC Timeslot 1 left channel mixer gain control 0 0dB 1 6dB Bit7 I2S2_DACL data Bit6 ADCL data 5 4 R W 0x0 Reserved 3 2 R W 0 0 1251 ADCRI GAIN 1281 ADC Timeslot 1 right channel mixer gain control 0 0dB 1 6dB Bit3 1252 data Bit2 ADCR data 1 0 R W 0x0 Reserved Reg 20h I282 BCLK LRCK Control Register Defau
20. output is the input data 3 Right energy default value setting include the input and 2 R W 0 ee 0 min 1 max Right channel gain hystersis setting The different between target level and the signal level must larger than the hystersis when the gain change 1 0 R W 00 00 0 4375db 01 0 9375db 10 1 9375db 11 3db DAC DAP Control Register Default 0x0000 Register Name AC DAC DAPCTRL Bit Read Write Default Description 15 3 DRC enable control 2 R W 0 0 disable 1 enable Left channel HPF enable control 1 R W 0 0 disable 1 enable Right channel HPF enable control 0 R W 0 0 disable 1 enable Reg alh DAC DAP High HPF Coef Register Default OxOOFF Register Name AC DAC DAPHHPFC Bit Read Write Default Description 15 11 HPF coefficient setting the coefficient reg a1 10 0 reg a2 10 0 R W OxFF is 3 24 format 2s complement Reg a2h DAC DAP Low HPF Coef Register Default OXFACI Register Name AC DAC DAPLHPFC Bit Read Write Default Description 15 0 R W OxFACI HPF coefficient setting the coefficient reg a1 10 0 reg a2 is 3 24 format 2s complement Reg a3h DAC DAP Left High Energy Average Coef Register Default 0x0100 Register Name AC DAC DAPLHAVC Bit Read Write Default Description 15 11 Left channel energy ave
21. x32 fs T n 1 32 fs When the gain decreases the actual gain will decrease 0 5dB at every attack time 8ch DAP Right Decay Time Register Default OxOO1F Register Name AC ADC DAPRDT Bit Read Write Default Description 15 Right decay time coefficient setting 0000 1x32 fs 0001 2x32 fs OxO01F 14 0 R W is 32x32fs TFFF 27 x32 fs T n 1 32 fs When the gain increases the actual gain will increase 0 5dB at every decay time Reg 8dh_ADC DAP Right Attack Time Register Default 0 0000 Register Name AC_ADC_DAPRAT Bit Read Write Default Description 15 Right attack time coefficient setting 0000 1x32 fs 0001 2x32 fs 14 0 R W 0 0000 Lm s 2 x32 fs T n 1 32 fs When the gain decreases the actual gain will decrease 0 54 at every attack time Reg 8eh_ADC DAP Noise Threshold Register Default 1 1 Register Name AC_ADC_DAPNTH Bit Read Write Default Description 15 13 Left channel noise threshold setting 0x00 30dB 0x01 32dB Ox1E 0x02 34dB 12 8 R W 90dB Ox1D 88dB Ox1E 90dB Ox1F 90dB the same as Ox 1E 7 5 Right channel noise threshold setting 90 30dB 0x00 30dB 4 0 R W Ox1E 90dB 0x01 32dB 0x02 34dB Ox1D 88dB Ox1E 90dB
22. 0 Normal 1 Inverted 13 12 9 R W R W 0x0 0x0 I2S1_LRCK_INV I2S1 LRCK Polarity 0 Normal 1 Inverted I2S1_BCLK_DIV Select the I2S1CLK BCLK1 ratio 0000 DSICLK 1 0001 DSICLK 2 0010 I2S1CLK 4 0011 IDSICLK 6 0100 DSICLK 8 0101 I2S1CLK 12 0110 DSICLK 16 0111 DSICLK 24 1000 DSICLK 32 1001 I2SICLK 48 1010 I2SICLK 64 1011 DSICLK 96 1100 DSICLK 128 1101 DSICLK 192 1110 Reserved 1111 Reserved 8 6 R W 0 0 281 LRCK DIV Select the BCLK1 LRCK ratio 000 16 001 32 010 64 011 128 100 256 xx Reserved 5 4 R W 0 0 1251 WORD 517 1251 digital interface word size 00 8bit 01 16bit 10 20bit 11 24bit 3 2 R W R W 0 0 0 0 I2S1 DATA FMT 125 digital interface data format 00 125 mode 01 Left mode 10 Right mode 11 DSP mode DSP MONO PCM DSP Mono mode select 0 Stereo mode select 1 Mono mode select R W 0 0 2581 TDMM 1251 TDM Mode enable 0 Disable 1 Enable Reg 11h I281 SDOUT Control Register Default 0x0000 Bit Read Write Default Register Name 251 SDOUT Description 15 R W 0x0 DS1 ADCLO ENA 1281 ADC Timeslot 0 left channel enable 0 Disable Enable 14 R W 0 0 1251 ADCRO 1251 ADC Timeslot 0 right channel enable 0 Disable 1 Enable 13 12 R
23. 0 when being read 14 1 R W 0 0 Reserved C8H REG Read control 0 R W 0 0 0 Read the effective real time clock value 1 Read the value of REG C8H REG written by host Reg d0h Alarm Interrupt Enable Register Default 0x0000 Register Name INT Bit Read Write Default Description 15 1 INT Alarm interrupt enable 0 R W 0x0 0 Alarm interrupt disable 1 Alarm interrupt enable Reg d1h Alarm Interrupt Status Register Default 0x0000 Register Name ALM INT STA REG Bit Read Write Default Description 15 1 ALM INT STS Alarm interrupt status Set 1 to this bit will clear it 0 R W 0x0 0 Alarm interrupt is not pending 1 Alarm interrupt is pending Reg d8h_Alarm Seconds Register Default 0x0000 Register Name ALM_SEC_REG Bit Read Write Default Description ALM_SEC_ENA Second alarm enable bit 15 R W 0x0 0 Disable second alarm 1 Enable second alarm 14 7 6 0 R W 0 0 ALM SEC SET These bits represent the current second value coded in BCD format The value should be from 0 to 59 For example if the 6 0 is 1011001 this represents the value 59 Reg d9h Alarm Minutes Register Default 0x0000 Register Name ALM MIN REG Bit Read Write Default Description MIN
24. 010 4 011 8 100 16 101 32 110 64 111 122 32KHz R W 0 0 CK32KAP MUX SEL CK32KAP Output source select control 0 32KHz from RTC 1 4MHz from ADDA 3 1 0 0 CK32KAP POST DIV Post division after clock selection 000 1 001 2 010 4 011 8 R W 0x1 100 16 101 32 110 64 111 128 CK32KAP_ENA CK32KAP Output enable control 0 Disable output 1 Enable output Reg c2h_CK32K Output Control Register 2 Default 0x0000 Register Name CK32K_OUT_CTRL2 Bit Read Write Default Description 15 8 R W 0x0 Reserved 7 5 0x0 CK32KBB_PRE_DIV Pre division after 4MHz input from ADDA 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 122 32KHz R W 0 0 CK32KBB MUX SEL CK32KBB Output source select control 0 32KHz from RTC 1 4MHz from ADDA 3 1 0x0 2 POST DIV Post division after clock selection 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 R W 0 0 2 CK32KBB Output enable control 0 Disable output 1 Enable output Reg CK32K Output Control Register Default 0x0000 Register Name 32 OUT CTRL3 Bit 15 8 Read Write R W Default 0 0 Description Reserved 7 5 R W 0 0 0 0 CK32KMD DIV Pre division after
25. 0x0 Right AGC noise threshold flag Right Gain applied by AGC 7 1 format 2s complement 20dB 40dB 0 5dB step 0x50 40dB 7 0 R 4 39 5dB 0x00 00dB OxFF 0 5dB Reg 82h ADC DAP Left Channel Control Register Default 0x0000 Register Name AC ADC DAPLCTRL Bit Read Write Default Description 15 R W 0 0 Reserved Left AGC enable 14 R W 0x0 0 disable 1 enable 13 R W 0 0 Left HPF enable 12 R W 0x0 0 disable 1 enable Left Noise detect enable 0 disable 1 enable 11 10 9 8 R W R W 0x0 0x0 Reserved Left Hysteresis setting 00 1dB 01 2dB 10 4dB 11 disable 7 4 R W 0 0 Left Noise debounce time 0000 disable 0001 4 fs 0010 8 fs 1111 16 4096 fs T 2 U fs except N 0 3 0 R W 0 0 Left Signal debounce time 0000 disable 0001 4 fs 0010 8 fs 1111 16 4096 fs 20 7 65 except 0 Reg 83h ADC DAP Right Channel Control Register Default 0x0000 Register Name AC ADC DAPRCTRL Bit Read Write Defauit Description 15 R W 0x0 Reserved Right AGC enable 14 R W 0x0 0 disable 1 enable Right HPF enable 13 R W 0x0 3 0 disable 1 enable Right Noise detect enable 12 R W 0x0 0 disable 1 enable 11 10 R W 0x0 Reserved Right Hysteresis setting 00 1dB 9 8 R W 0x0 01 2dB 10 4dB 11 disable Right Noise debounce time 00
26. 1 The default gain is 0 The hysteresis of the gain smooth filter to use the decay time coefficient or the attack time coefficient When in the decay time state if g n 1 g n gt hysteresis then the state will change to attack time state and when in the attack time if g n g n 1 gt hysteresis then the state will change to decay time state Note the hysteresis of 0x00 and 0x04 is the same 4 0 R W 0x00 00000 24 00001 27 00010 277 00011 27 00100 27 10011 27 10100 11111 1 hysteresis aus except n 0x00 and n less 0x14 Reg 4 DAP Enable Register Default 0x0000 Register Name ADC DAP ENA Bit 15 Read Write Default 0 0 Description I281 ADCLO ENA 1251 ADC timeslot 0 left channel enable 0 Disable 1 Enable 14 0 0 1251 ADCRO 1251 ADC timeslot 0 right channel AGC enable 0 Disable 1 Enable 13 12 0 0 0 0 DS1 ADCLI 1251 ADC timeslot 1 left channel enable 0 Disable 1 Enable DS1 1281 ADC timeslot 1 right channel AGC enable 0 Disable 1 Enable R W 0 0 12582 1252 ADC left channel AGC enable 0 Disable 1 Enable 10 R W 0 0 1252 1252 ADC right channel AGC enable 0 Disable 1 Enable 0x0 I2S2_DACL_AGC_ENA 1252 DAC left channel AGC enable
27. 2 channel ADC with a high level of mixed signal integration Three audio interface are available in order to provide independent and fully asynchronous connections to multiple processors typically such as an application processor baseband and bluetooth transceiver An integrated digital PLL supports a large range of input output frequencies and It can generate required audio clocks for codec from standard audio crystal rate such as 22 5792MHz and 24 576MHz also can be from common reference clock frequencies such as 12MHz 13MHz and 19 2MHz an internal RC oscillator can be used in Free running Mode where the application processor can be inactive during voice call application The 2 ADC and 2 DAC in device use advanced multi bit delta sigma modulation technique to convert data between analog and digital The SNR performance can reach 100 dB A wight Five analog input paths allow diverse analog audio sources such as three sets of differential microphone one differential or single ended linein and one stereo FM input One ground reference headphone output is provided The output amplifier are powered from an integrated Charge Pump in order to achieve a higher quality less power consumption in headphone playback whist without any DC blocking capacitor and avoiding unwanted noise A mono differential BTL drive amplifier is available for driving the handset receiver Two stereo differential speaker output is available by using an exte
28. 4MHz input from ADDA 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 122 32 2 CK32KMD MUX SEL CK32KMD Output source select control 0 32KHz from RTC 1 4MHz from ADDA 3 1 0 0 CK32KMD POST DIV Post division after clock selection 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 R W 0 0 CK32KMD CK32KMD Output enable control 0 Disable output 1 Enable output Reg c h Reset Register Default 0x0000 Register Name RST REG Bit Read Write Default Description RTC KEY FIELD 15 8 WO 0x0 RTC key field should be written at value 0x53 Writing any other value in this field aborts the write operation 7 1 _ When this bit is set to 1 then all registers of time will be reset to 0 R W 0 0 default values 0 No effect 1 Reset relevant registers Reg c7h RTC Control Register Default 0x0000 Register Name RTC REG Bit 15 Read Write R W Default 0 0 Description SIM simulation bit When this bit is set 1 the relevant registers will rolling over faster such as second minute hour ext 0 Normal mode 1 Simulation mode 14 3 0 0 0 0 Error mode 0 Do not affect current Time Week Date Set the wrong segment to max value RTC STOP RTC stop bit Whe
29. 8 R W 0 0 DSICLK SRC I2S1CLK Source Select 00 01 MLCK2 1X PLL 0 0 I2S2CLK_ENA I2S2CLK Enable 0 Disable 1 Enable 0 0 Reserved 5 4 R W 0 0 I2S2CLK_SRC I2S2CLK Source Select 00 01 MLCK2 1X PLL 2 1 R W 0 0 0 0 SYSCLK SYSCLK Enable 0 Disable 1 Enable Reserved 0x0 SYSCLK_SRC System Clock Source Select 0 I2SICLK 1 DS2CLK Reg 04h Module Clock Enable Control Register Default 0x0000 Register Name MOD ENA Bit Read Write Default Description 15 0 R W 0 0 Module clock enable control 0 Clock disable 1 Clock enable BIT15 I2S1 BIT14 DS2 BIT13 I2S3 BIT12 Reserved BIT11 SRC1 BIT10 SRC2 BIT9 Reserved BIT8 Reserved BIT7 HPF amp AGC BIT6 HPF amp DRC BIT5 Reserved BIT4 Reserved BIT3 ADC Digital BIT2 DAC Digital BIT1 Reserved BITO Reserved Reg 05h Module Reset Control Register Default 0x0000 Bit Read Write Default Register Name MOD RST CTRL Description 15 0 R W 0x0 Module reset control O Reset asserted Reset de asserted BIT15 I2S1 BIT14 I2S2 BIT13 I2S3 BIT12 Reserved BIT11 SRC1 BIT10 SRC2 BIT9 Reserved BIT8 Reserved BIT7 HPF amp AGC BIT6 HPF amp DRC BIT5 Reserved BIT4 Reserved BIT3 ADC Digital BIT2 DAC Digital BIT 1 Reserved BITO Reserved Reg 06h ADDA Sample Rate Configuration Register
30. Bit 4 LINEINL LINEINR Bit 3 LINEINL Bit 2 AUXINL Bit 1 Left output mixer Bit 0 Right output mixer Reg 52h ADC Source Boost Control Register Default 0x4444 Register Name ADC SRCBST CTRL Bit R W Default Description 15 R W 0x0 MICIAMPEN MICI boost AMPlifier ENable 0 Disable 1 Enable 14 12 Ox4 MICIBOOST MICI boost amplifier Gain control OdB when 000 and from 30dB to 48dB when 001 to 111 11 0x0 MIC2AMPEN boost AMPlifier ENable 0 Disable 1 Enable 10 8 0x4 MIC2BOOST MIC2 boost amplifier Gain control OdB when 000 and from 30dB to 48dB when 001 to 111 0x0 MIC2SLT MIC2 Source select 0 MIC2 1 MIC3 6 4 Ox4 LINEIN DIFF PREG LINEINL LINEINR differential signal pre amplifier gain control 12dB to 9dB 3dB step default is OdB 2 0 Ox4 AXI PREG AXI pre amplifier gain control 12dB to 9dB 3dB step default is OdB Reg 53h_Output Mixer amp DAC Analog Control Register Default 0x0f80 Bit R W Default Register Name OMIXER_DACA_CTRL Description 15 0 0 DACAREN Internal DAC Analog Right channel Enable 0 Disable 1 Enable 14 13 0 0 0 0 DACALEN Internal DAC Analog Left channel Enable 0 Disable 1 Enable RMIXEN Right Analog Output Mixer Enable 0 Disable 1 Enable 12 0 0 LMIXEN Left Analog Output Mixer Enable 0 Disa
31. CPVEE 1 27 HPOUTR 1 25 HPOUTL 1 20 SPOLN 1 19 SPOLP r r SE 4 045 ew 961 DAV eros 761 N1nONVv3 oianv Ol diniOuv3 QN5V znias OF NYA z noas Tr u1n0O3NI oou zv 11003NH ens tv dua vv 1 INIGS St 11noas sr SVI8H Dow zv NZIW DOS 0 Lee TOW 6r NTOIIA 061 vas 151 521 la 531 262 541 551 60 Sai 611 63 Id 641 CKO2 56 VDD_CORE 621 SCK X32Kl IRQ_RTC vcc Rrc 581 X32KO LDOIN MBIAS MIC3N AXIR AXIL CKO1 RTC CKO3 RTC Figure3 Pin Assignment 6 Package Dimension Nd D D2 MILLIMETER SYMBOL MIN NOM MAX l 1 A 0 70 0 75 0 80 E Al 0 02 0 05 b 0 15 0 20 0 25 c 0 18 0 20 0 25 a D 7 90 8 00 8 10 D2 5 39 5 49 5 59 e 0 40BSC Nd 6 40BSC 4 7 90 8 00 8 10 5 39 5 49 5 59 6 A0BSC EXPOSED THERMAL L 35 4 45 PAD ZONE BOTTOM VIEW 048417 0550 K 0 20 lt h 0 30 0 35 0 40 z a ead 240240 Figure4 Package Dimension 7 Pin Signal Description This chapter describes the 68 pins of 100 from four aspects pin number signal name type and pin definition All the pins are classified into four groups including
32. DAC output 11 8 3 Digital Mixers The digital mixers are provided for digital audio data mixing on four 1251 output paths two 1252 output paths and two paths to the stereo DAC It s separately controlled by the register 1251 5 1252 MXR SRC and DAC SRC Control Left Rigth source select Mono Mix control Mpa TOUT 111045 CNOWTI TLNOAS amp TNIAS Lnods NOWT Figure 24 Digital Data Path 11 9 Analogue Audio Input Path The Codec supports five Analogue Audio Input paths LINEINL R AXIL R MICIP N MIC2P N MIC3P N 11 9 1 Microphone Input MICINIP N MICIN2P N MIC3INP N provide differential input that can be mixed into the ADC record mixer or DAC output mixer MICIN is high impedance low capacitance input suitable for connection to a wide range of differential microphones of different dynamics and sensitive There are only two microphone pre amplifiers for the 3 differential microphone inputs MICINIP N are input to the first pre amplifier MICIN2P N amp MICIN3P N are selected to input the 2nd pre amplifier by the register ADC SRCBST CTRL bit7 Each microphone preamplifier has a separate enable bit SRCBST Bit15 amp Bitll The gain for each pre amplifer can be set independently using MICIBOOST MIC2BOOST MBIAS pro
33. Input Path rrt rr gg e eei e ren nt ten nri ne 34 11 9 T Microphone Input eee MENOR 34 TLI 22 AXIER etae venerint 34 11 9 3 E INEINTZR Inp t tec cafe ee reete 35 11 10 Analogue Audio Output 36 11 10 1 Headphone 2222 2 2222222 4 4 1 36 11 10 2 Earpiece Outpfrt M ssen T 36 TT 10 3 Speaker utpote enm eee ete eei eet 37 TT LOA Time Output m code tee e ON e 37 11 11 Digital MicroPgone Interface re rt nee tern e nter e dre n nnda 38 11 12 Afidio 39 40 1 14 DigitallAudio Process Tor ADO e oer eere e E RR D EX IR Y eda 41 VI High Pass Filters ie deed Ret d AE 42 11 1472 Auto Control ree o n oc po n ED LEER DRE 42 11 13 Digital Audio Process Tor eniro ite e t tn noe rena hona 46 FLASA High Pass Filter ettet Re Rete t Resp 47 11 152 Dynamic Range Control tiere rte Rear MP E o E bI 16 REC Module ettet teta 12 1 Description The 100 is a highly integrated audio codec and subsystem designed for tablet and smart mobile application platforms It has three I2S PCM interface 2 channels DAC and
34. W R W 0 0 0 0 I2S1_ADCL1_ENA 1251 ADC Timeslot 1 left channel enable 0 Disable 1 Enable I2S1_ADCR1_ENA 1251 ADC Timeslot 1 right channel enable 0 Disable 1 Enable 11 10 0 0 I2S1_ADCLO_SRC 1251 ADC Timeslot 0 left channel data source select 00 I2S1_ADCLO 01 2S1 ADCRO 10 251 0 251 ADCRO 11 1251 0 251 ADCRO 2 9 8 R W 0 0 1251 ADCRO SRC 1251 ADC Timeslot 0 right channel data source select 00 2S1 ADCRO 01 2S1 ADCLO 10 1251 ADCLO DS1 ADCRO 11 1251 ADCLO DS1 ADCRO 2 7 6 R W 0 0 251 ADCLI SRC I2S1 ADC Timeslot 1 left channel data source select 00 1251 ADCLI 01 1251 ADCRI 10 251 ADCLI4DS1 ADCRI 11 d2S1_ADCL1 I2S1_ADCR1 2 5 4 R W 0 0 1251 ADCRI SRC 1251 ADC Timeslot 1 right channel data source select 00 2S1 ADCRI 01 1251 ADCIL 10 1251 ADCLI D2SI ADCRI 11 1251 ADCLI DSI ADCR1 2 R W 0 0 1251 ADCP 1281 ADC Companding enable 8 bit mode only 0 Disable 1 Enable R W 0 0 1281 ADCP SEL DSIADC Companding mode select 0 A law 1 u law 1 0 R W 0 0 1281 SLOT SIZ Select the slot size only mode 00 8 01 16 10 32 11 Reserved Reg 12h 1251 SDIN Control Register Default 0x0000 Register Name 1251 SDIN Bit Read Write Default Description 15 R W 0 0
35. as the system clock S YSCLK In order to save power the left and right analog ADC part can be enabled disabled separately by setting register Bitl5 amp Bitll The digital ADC part can be enabled disabled by ADC DIG CTRL Bit15 The volume control of the stereo ADC is set via register ADC CTRL Bit14 12 amp ADC Bit10 8 11 7 Stereo DAC The stereo DAC sample rate is the same as the stereo ADC The sample rate is configured by the register ADDA FS 1251 or ADDA FS 1252 depending on which I2SnCLK selected as the system clock SYSCLK In order to save power the left and right DAC can be enabled disabled separately by setting register DACA CTRL Bit15 14 The digital DAC part can be enabled disabled by DAC DIG Bit15 11 8 Mixer The Codec supports three series of mixers for all function requirements 2channels DAC Output mixers 2channels ADC Record mixers Digital mixers 11 8 1 DAC Output Mixers The output mixer is used to drive analogut output including headphone earpiece speaker lineout The following signals can be mixed into the output mixer LINEINL R AXIL R MIC1P N MIC2P N Stereo DAC output 11 8 2 ADC Record Mixers The ADC record mixer is used to mix analog signals as input to the Stereo ADC for recording The following signals can be mixed into the output mixer LINEINL R AXIL R MICIP N MIC2P N Stereo
36. average level coefficient 15 0 R W Ox1EBS8 setting the coefficient reg86 10 0 reg87 is 3 24 format 2s complement Reg 88 ADC DAP Right High Average Coef Register Default 0x0005 Register Name AC ADC DAPRHAC Bit Read Write Default Description 15 11 Right channel output signal average level coefficient 10 0 R W 0 0005 setting the coefficient reg88 10 0 reg89 is 3 24 format 2s complement Reg 89h ADC DAP Right Low Average Coef Register Default OX IEBS Register Name AC ADC DAPRLAC Bit Read Write 15 0 R W Default OxIEBS Description Right channel output signal average level coefficient setting the coefficient reg88 10 0 reg89 is 3 24 format 2s complement Reg 8ah_ADC DAP Left Decay Time Register Default OxOO1F Register Name AC ADC DAPLDT Bit Read Write Default Description 15 Left decay time coefficient setting 0000 1x32 fs 0001 2x32 fs Ox0O01F 14 0 R W is 32x32fs 27 x32 fs T n 1 32 fs When the gain increases the actual gain will increase 0 5dB at every decay time Reg 8bh_ADC DAP Left Attack Time Register Default 0 0000 Register Name AC_ADC_DAPLAT Bit Read Write Default Description 15 Left attack time coefficient setting 0000 1x32 fs 0001 2x32 fs 14 0 R W Ox0000 i a TFFF 2
37. digital IO pin analog IO pin filter reference and power ground There are five pin types here O for output I for input I O for input output P for power and G for ground Pin Number Signal Name Type Description Digital IO Pins 49 MCLKI I 125 interface master input clock 1 45 SDINI I First 125 interface serial data input 46 SDOUTI O First 125 interface serial data output 48 BCLKI First 125 interface serial bit clock 47 LRCKI First 125 interface synchronous clock 50 MCLK2 I 125 interface master iuput clock 2 40 SDIN2 I Second 125 interface serial data input 41 SDOUT2 O Second 125 interface serial data output 43 BCLK2 Second I2S interface serial bit clock 42 LRCK2 I O Second 25 interface synchronous clock 33 SDIN3 I Third I2S interface serial data input 34 SDOUT3 O Third I2S interface serial data output 37 BCLK3 Third I2S interface serial bit clock 36 LRCK3 I O Third 125 interface synchronous clock TWI interface serial data Open drain 51 SDA VO RSB interface serial data TWI interface serial clock input 53 SCK I RSB interface serial clock input 38 IRQ AUDIO IRQ for accessory insert and button detect Open drain 54 IRQ RTC O IRQ for alarm interrupt Open drain 60 X32KI I The external oscillator input singal 61 X32KO The external oscillator output singal 55 CKOI RTC 32 768 KHz clock
38. formats of write and read instructions are shown in below Write Word Protocol 1 T 1 8 8 1 1 S Device Address Wr Register Address ata Byte High A P Read Word Protocol 7 1 8 1 8 1 8 1 8 a S Device Address Wr Register Address S Device Address Rd A Data Byte High Data Byte Low A 5 start Condition A 0 for 1 NACK Slave Address 7 bit Device Address Data Byte 16 bit Mixer data Wr 0 for Write Command Master to Slave Rd 1 for Read Command Slave to Master Command Code 8 bit Register Address Figure8 TWI Read and Write 11 4 2 RSB Interface RSB interface supports a special protocols with a simplified two wire protocol on a push pull bus So the transfer speed can be up to 10MHz and the performance will be improved much AC100 works only in slave mode RSB support multi slaves It uses CK as clock and uses CD to transmit command and data the Bus Topology is showed below Master CK CD L Figure9 RSB Bus Topology The start bit marks the beginning of a transaction with the slave device When CK is high a change from high to low on CD is defined as a start condition This start condition notifies the selected device to start a transfer Figure 10 Start signal RSB protocol uses parity bit to check the correction of every byte The checked object i
39. output Push pull 56 CKO2 RTC O RTC 32 768 KHz clock output Open drain 57 CKO3 RTC O RTC 32 768 KHz clock output Open drain Analog IO Pin 2 MICIP I Positive differential input for MICI 3 MICIN I Negative differential input for MICI 4 MIC2P I Positive differential input for 2 5 MIC2N I Negative differential input for MIC2 64 MIC3P I Analog Positive differential input for MIC3 DMICCLK Digital microphone clock output 66 MIC3N I Negative differential input for MIC3 DMICDAT Digital microphone data input 8 LINEINL I Left single end or differential input for LINE IN 7 LINEINR I Right single end or differential input for LINE IN 68 AXIL I Auxiliary left Channel input 67 AXIR I Auxiliary right Channel input 25 HPOUTL O Headphone amplifier left channel output 27 HPOUTR Headphone amplifier right channel output 19 SPOLP Differential positive output to speaker amplifier 20 SPOLN O Differential negative output to speaker amplifier 17 SPORP Differential positive output to speaker2 amplifier 18 SPORN O Differential negative output to speaker2 amplifier 14 EAROUTP O Earpiece amplifier positive differential output 15 EAROUTN O Earpiece amplifier negative differential output LINEOUTP O Positive output for LINE OUT 10 LINEOUTN O Negative output for LINE OUT Filter Reference 65 MBIAS O First bias voltage output for main microphone
40. signal has levels lower than the noise threshold and thus is detected as noise or silence In such a condition the AGC applies a gain of 0 dB Gain applied by AGC is a read only register setting which gives a real time feed back to the system on the gain applied by the AGC to the recorded signal This a long with the target setting can be used to determine the input signal level In a steady state situation TargetLevel dB GainAppliedbyAGC dB Input SignalLevel dB When the AGC noise threshold flag is set then the status of gain applied by AGC is not valid saturation flag is a read only flag indicating that the ADC output signal has not reached its target level However the AGC is unable to increase the gain further because the required gain is higher than the maximum allowed PGA gain Such a situation can happen when the input signal has low energy and the noise threshold is also set low When the AGC noise threshold flag is set the status of AGC saturation flag should be ignored ADC saturation flag is a read only flag indicating an overflow condition in the ADC channel On overflow the signal is clipped and distortion results This typically happens when the AGC target level is kept high and the energy in the input signal increases faster than the attack time The signal level detect LPF AGC Figure 37 Signal level detect An AGC low pa
41. their own RTSADDR The device s RTSADDR is setted by set run time slave address RTSADDR command 1 7 1 7 1 8 1 8 1 8 1 2 1 2 HOST 0 27 0 2 0 31 C RTSADDR DADDR DATAO 05 c py Device on len 1 2 4 Figure 14 Write command 11 5 I2S PCM Interface There are three I2S PCM interfaces which can be configured as master mode or slave mode in AC100 The three I2S PCM interfaces provide flexible connectivity with multiple processors e g Application processor Baseband processor and Wireless transceiver Interface 1251 and 1252 can be configured as Master or Slave the third interface 1253 operates in Master mode and supports PCM mode only In the general case the digital audio interface uses four pins as below BCLK Bit clock for data synchronization LRCK Left Right data alignment clock SDOUT output data for ADC data SDIN input data for DAC data 1251 and 1252 audio interface support four different data formats as below But 1253 supports PCM short mode only On the first digital audio interface 1251 TDM is available for all four farmart and AC100 can use it to transmit or receive up to four channel data on timeslotO and timeslot simultaneously 128 mode Left justified mode Right justified mode PCM short mode LRCK DIV I LRCK Fr 5 2 ela 2 mm
42. 0 Disable 1 Enable 0x0 0x0 I2S2_DACR_AGC_ENA I2S2 DAC right channel AGC enable 0 Disable 1 Enable ADCL_AGC_ENA left channel AGC enable 0 Disable 1 Enable 0x0 ADCR_AGC_ENA ADC right channel AGC enable 0 Disable 1 Enable 5 0 R W 0x0 Reserved Reg b5h_DAC DAP Enable Register Default 0x0000 Register Name DAC_DAP_ENA Bit Read Write Default Description 1281 1281 DAC timeslot 0 enable 15 R W 0x0 0 Disable Enable 14 R W 0 0 Reserved 1251 DRC ENA 1251 DAC timeslot 1 DRC enable 13 R W 0 0 0 Disable Enable 12 R W 0x0 Reserved 1252 DAC DRC 1252 DAC DRC enable 11 R W 0 0 0 Disable Enable 10 8 R W 0 0 Reserved 7 R W 0 0 DAC DAC DRC enable 0 Disable 1 Enable 6 0 R W 0 0 Reserved Reg b8h_SRC1 Control 1 Register Default 0x0000 Register Name SRC1 CTRL1 Bit Read Write Default Description 15 R W 0 0 5 SRCI Manual setting ratio enable 0 disable 1 enable 14 R 13 R 0x0 0x0 SRC1_LOCK_STS SRCI Ratio lock status 0 not locked 1 locked SRCI FIFO SRCI FIFO Overflow status O normal 1 overflowed 12 10 R 0 0 5 FIFO LEV 8 6 SRCI FIFO Level high 3 bit 9 0 R W 0 0 5 SET 25 16
43. 00 disable 0001 4 fs 7 4 R W 0x0 0010 8 fs 1111 16 4096 fs 3 0 0 0 2 except 0 Right Signal debounce time 0000 disable 0001 4 fs 0010 8 fs 1111 16 4096 fs T 2 fs except 0 Reg 84h ADC DAP Left Target Level Register Default 0x2C28 Register Name AC ADC DAPLTL Bit Read Write Default Description 15 14 0 2 Left channel target level setting 1dB 13 8 R W 20dB 30dB 6 0format 2s complement 0x28 Left channel max gain setting 0 40dB 7 1format 2s 7 0 R W 20dB complement Reg 85h ADC DAP Right Target Level Register Default 0x2C28 Register Name AC ADC DAPRTL Bit Read Write Default Description 15 14 Right channel target level set ng IdB 13 8 R W Ox2C 20dB 30dB 6 0format 2s complement Right channel max gain setting 0 40dB 7 1format 2s 7 0 R W 0x28 20dB complement Reg 86h ADC DAP Left High Average Coef Register Default 0x0005 Register Name AC ADC DAPLHAC Bit Read Write Default Description 15 11 Left channel output signal average level coefficient 10 0 R W 0 0005 setting the coefficient reg86 10 0 reg87 is 3 24 format 2s complement Reg 87h_ADC DAP Left Low Average Coef Register Default OX 1EB8 Register Name AC_ADC_DAPLLAC Bit Read Write Default Description Left channel output signal
44. 119 25dB Ox9F 0 75dB 0xA0 0dB 1 0 75dB OxFF 71 25dB Reg 26h 1252 Volume Control 2 Register Default 0xA0A0 Bit Read Write Default Register Name ID2D 2 VOL CTRL2 Description 15 8 7 0 OxAO OxAO 1252 DACL VOL 1252 DAC left channel volume 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01 119 25dB Ox9F 0 75dB 0 0dB 0 75dB OxFF 71 25dB 1252 VOL 1252 DAC right channel volume 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01 119 25dB Ox9F 0 75dB 0 0dB OxA1 0 75dB OxFF 71 25dB Reg 28h 1252 Digital Mixer Gain Control Register Default 0x0000 Register Name 1252 GAIN Bit Read Write Default Description 15 12 0 0 1252 ADCL GAIN 1252 left channel mixer gain control 0 0dB 1 6dB Bit15 DS1 DAOL data Bitl4 1251 data Bit13 1252 data Bit12 ADCL data 11 8 0 0 1252 GAIN 1252 right channel mixer gain control 0 0dB 1 6dB Bit11 DS1 DAOR data Bit10 DS1 DAIR data Bit9 1252 DACL data Bit8 ADCR data 7 0 R W 0 0 Reserved Reg 30h 1253 BCLK LRCK Control Register Default 0x0000 Bit Read Write Default Register Name 1293 CLK CTRL Description 15 R W 0 0 Reserved 14 R W 0 0 1283 BCLK 1253 BCL
45. 2 DACR 2 7 4 R W 0 0 Reserved 0x0 I282 DACP 1252 DAC Companding enable 8 bit mode only 00 Disable 01 Enable 0 0 1282 DACP SEL 1252 DAC Companding mode select 0 A law 1 u law 0x0 Reserved 0x0 1252 LOOP EN 1252 loopback enable 0 No loopback 1 Loopback SDOUT data output to SDOUT2 data input Reg 23h 1252 Digital Mixer Source Select Register Default 0x0000 Register Name 1252 SRC Bit Read Write 15 12 R W Default 0 0 Description 1252 ADCL SRC 1252 ADC left channel mixer source select 0 Disable 1 Bit15 1281 DAOL data Bit14 I2S1_DA1L data Bit13 1252 DACR data Bit12 ADCL data 11 8 R W 0 0 1252 5 1252 right channel mixer source select 0 Disable 1 Enable Bit11 DS1 DAOR data Bit10 DS1 DAIR data Bit9 1252 DACL data Bit8 ADCR data 7 0 R W 0x0 Reserved Reg 24h 1252 Volume Control 1 Register Default 0xA0A0 Register Name 1282 VOL CTRL1 Bit Read Write Default Description 15 8 R W OxAO I282 ADCL VOL 1252 ADC left channel volume 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01 119 25dB Ox9F 0 75dB 0xA0 OdB OxA1 0 75dB OxFF 71 25dB 7 0 R W OxAO 1252 VOL 1252 right channel volume 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01
46. 3 ADC Right channel input Gain control From 4 5dB to 6dB 1 5dB step default is OdB 11 R W 0x0 ADCLEN Left channel Enable 0 Disable 1 Enable ADCLG 10 8 R W 0 3 Left channel input Gain control From 4 5dB to 6dB 1 5dB step default is OdB MBIASEN 7 R W 0x0 Master microphone BIAS Enable 0 Disable 1 Enable MMIC BIAS CHOPPER EN 6 R W 0x1 Main MICrophone BIAS chopper Enable 0 Disable 1 Enable MMIC_BIAS_CHOPPER_CKS Main MICrophone BIAS chopper Clock select 00 250k 01 500k 10 Meg 11 2Meg 3 5 4 R W 0x0 HBIASMOD HBIAS amp ADC working mode 0 HBIAS is enabled only when with load 1 HBIAS is enabled when HBIASEN write 1 2 R W 0 0 HBIASEN 1 R W 0 0 Headset microphone BIAS Enable 0 Disable 1 Enable HBIASADCEN 0 R W 0 0 Headset microphone BIAS Current sensor amp ADC Enable 0 Disable 1 Enable Reg 51h ADC Source Select Register Default 0x0000 Register Name ADC SRC Bit R W Default Description 15 14 RADC MIXMUTE Right ADC Mixer Mute Control 0 Mute 1 On Bit 13 MICI Boost stage Bit 12 MIC2 Boost stage Bit 11 LINEINL LINEINR Bit 10 LINEINR Bit 9 AUXINR Bit 8 Right output mixer 13 7 R W 0x0 Bit 7 Left output mixer LADC MIXMUTE Left ADC Mixer Mute Control 0 Mute 1 On Bit 6 MICI Boost stage 6 0 R W 0 0 Bit 5 MIC2 Boost stage
47. 39dB Gain 83 dB THD N 30mV 1 KHz 39dB Gain 79 SNR A weighted 10mV 1 KHz 48dB Gain 74 dB THD N 10mV 1 KHz 48dB Gain 73 dB LINEIN to Headphone via output mixer FScale Input Level OdB 1KHz 1 Vrms SNR A weighted 1dB 1KHz 98 dB THD N 1dBFS 1dB 1KHz 92 dB Crosstalk L R 1dB 1KHz 89 89 dB to Headphone via output mixer FScale Input Level OdB 1KHz 1 Vrms SNR A weighted 1dB 1KHz 102 dB THD N 1dBFS 1dB 1KHz 93 dB Crosstalk L R 1dB 1KHz 88 88 dB 10 Power Consumption Default Test Conditions LDOIN CPVDD 1 5V AVCC 3 0V VCC IO1 VCC IO2 1 8V VCC RTC 3 0V OPERATING TEST CONDITIONS LDOIN AVCC vcc IO1 1 2 CPVDD VCC RTC MODE RTC only LDOIN VCC RTC supplies 1 8V 3 1 8V 3 1 8V 3 LDO enabled 32 768KHz clock XTAL enabled OuA OuA OuA 12uA three output enable Standby supplies present 1 8V 3V 18 3V 1 8V 3V LDO enabled No clocks supply XTAL enabled 7314 62uA OuA 12uA Default register settings Music Playback to Headphone 32 load fs 44 1 KHz 1 8V 3V 1 8V 3V 1 8V 3V AIFI to DAC to SYSCLK MCLK 24 576MHz HPOUT stereo 24bit I2S Slave mode 1 5mA 4 1mA 0 013mA 2 4mA 12uA Voice record to AIF1 fs 44 1KHz 1 8V 3V 1 8V 3V 1 8V 3V MICI to ADC to SYSCLK MCLK 24 576MHz AIF1 mono 24bit I2S Slave mode 14mA 4 5m
48. 53 Signal Path Control Register Default 0x0000 Register Name I283 SGP Bit Read Write Default Description 15 12 R W 0 0 Reserved 11 10 0x0 1253_ _5 1253 PCM output source select 00 None 01 1252 ADCL 10 1252 ADCR 11 Reserved 9 8 R W 0 0 1252 DAC 5 1252 DAC input source select 00 1252 ADCL 1252 ADCR 01 Left input from 1253 DAC Right input from 1252 10 Left input from 1252 ADCL Right input from 1253 DAC 11 Reserved 7 0 R W 0 0 Reserved Reg 40h ADC Digital Control Register Default 0x0000 Bit Read Write Default Register Name ADC DIG CTRL Description 15 14 R W R W 0x0 0x0 ENAD ADC Digital part enable 0 Disable 1 Enable ENDM Digital microphone enable 0 Analog ADC mode 1 Digital microphone mode ADFIR32 Enable 32 tap FIR filter 0 64 tap 1 32 tap 13 R W 0x0 12 4 R W 0x0 Reserved ADOUT_DTS ADC Delay Time For transmitting data after ENAD 00 5ms 01 10ms 10 20ms 11 30ms 3 2 R W 0x0 ADOUT_DLY ADC Delay Function enable for transmitting data after ENAD 0 Disable 1 Enable 1 R W 0x0 0 R W 0x0 Reserved Reg 41h ADC Volume Control Register Default 0xA0A0 Register Name ADC VOL CTRL Bit Read Write Default Description ADC VOLL ADC left channel volume
49. A 0 023mA 12uA Analog Analog Voice Path eg Analog Voice call 1 8V 3 1 8V 3V 1 8V 3V Micl to Lineout fs 8 kHz Linein to Hp SYSCLK MCLK 24 576MHz 0 75mA 4 ImA OmA OmA 2 0mA 12uA 11 Function Description 11 1 Power There are Power Reset circuit in 100 uesed to reset all the circuit and register to a standby state after power up The Power Reset circuit make all the supply power need no specific timing All the supply voltages are illustrated in the below figure 100 POWER DOMAIN Figure5 Power Management VDD CORE is 1 2V for audio digital core power generated from LODIN pin which also can be direct supplied from VDD CORE pin VDD IO1 is digital I O power for 1251 1252 VDD IO2 is digital I O power for 253 AVCC is for analog power CPVDD for charge pump power VIO RTC is RTC digital core power generated from VCC RTC When the AC100 is not working it need to set the supply properly to prevent power leakage There two settings to select It s best to power off all the supply The other is to make sure AVCC and CPVDD both power on At the setting below AC100 has the best performance LDOIN VDD CORE AVCC CPVDD VCC IOI VCC IO2 RTC VIO RTC 1 5 3 3 V 1 2 V 1 8V 1 8 3 3 V 1 8 3 3 V 1 8 3 3 V 1 2V Supplied N A Supplied Supplied Supplied Supplied Supplied N A VDD CORE and VIO RTC generated by i
50. A IRQ Hmic Data Irq Enable 0 disable 1 enable Reg 45h HMIC Control 2 Register Default 0x0000 Register Name HMIC CTRL2 Bit Read Write Default Description 15 14 0x0 HMIC_SAMPLE_SELECT Down Sample Setting Select 00 Down by 1 128Hz 01 Down by 2 64Hz 10 Down by 4 32Hz 11 Down by 8 16Hz 13 12 8 R W R W 0 0 0 0 TH2 HYSTERESIS Hmic Hysteresis Threshold2 0 no Hysteresis 1 Key Up when Data Hmic th2 1 HMIC TH2 Hmic th2 for detecting Key down or Key up 7 6 R W 0 0 HMIC SF Hmic Smooth Filter setting 00 by pass 01 1 2 2 10 1 2 3 4 4 11 1 2 3 4 5 6 7 8 8 R W 0 0 KEYUP CLEAR Key Up Irq Pending bit auto clear when Key Down Irq 0 don t clear 1 auto clear 4 0 R W 0 0 Hmic th1 4 0 detecting eraphone plug in or pull out Reg 46h HMIC Status Register Default 0x0000 Register Name HMIC STATUS Bit Read Write Default Description 15 13 R W 0x0 Reserved 12 8 R 0x0 HMIC_DATA HMIC Average Data 7 5 R W 0x0 Reserved R W 0x0 HMIC_PULLOUT_PENDING Hmic Earphone Pull out Irq pending bit write 1 to clear 0 No Pending Interrupt 1 Pull out Irq Pending Interrupt R W R W R W 0 0 0 0 0 0 HMIC PLUGIN PENDING Hmic Earphone Plug in Irq p
51. DC left channel enable 0 Disable 1 Enable 14 R W 0x0 I282 ADCR EN 1252 ADC right channel enable 0 Disable 1 Enable 13 12 0 0 Reserved 11 10 9 8 R W 0 0 0 0 1252 ADCL SRC 1252 ADC left channel data source select 00 1252 ADCL 01 1252 ADCR 10 252 ADCL DS2 ADCR 11 252 ADCL I282 ADCR 2 1252 ADCR SRC 1252 ADC right channel data source select 00 1252 ADCR 01 1252 ADCL 10 1252 ADCL DS2 ADCR 11 2S2_ADCL I282_ADCR 2 7 4 R W 0 0 Reserved R W 0 0 1252 ADCP ENA 1252 ADC Companding enable 8 bit mode only 00 Disable 01 Enable 1 0 R W 0x0 I282 ADCP SEL 1252 ADC Companding mode select 0 A law 1 u law Reg 22 1252 SDIN Control Register Default 0x0000 Bit Read Write Default Register 1252 SDIN Description 15 R W 0x0 I2S2_DACL_ENA 1252 DAC left channel enable 0 Disable 1 Enable 14 R W 0x0 I2S2_DACR_ENA 1252 DAC right channel enable 0 Disable 1 Enable 13 12 R W 0x0 Reserved 11 10 R W 0x0 I2S2_DACL_SRC I2S2 DAC left channel data source select 00 I2S2_DACL 01 I2S2_DACR 10 12S2_DACL I2S2_DACR 11 d2S2_DACL I2S2_DACR 2 9 8 R W 0 0 1252 DACR 5 1252 DAC right channel data source select 00 1252 01 1252 DACL 10 1252 _ 1252 11 1252 125
52. Earpiece Output Control Register Default 0x8200 Register Name ERPOUT CTRL Bit R W Default Description 15 R W 0x1 Reserved 14 12 R W 0x0 12 11 R W 0 0 EAR RAMP TIME Earpiece ramp time select 00 256ms 01 512ms 10 640ms 11 768ms 10 9 0x1 ESPA OUT CURRENT Earpiece output stage current set 00 1s minimum 1115 maximum 8 7 0x0 ESPSR Earpiece input source select 00 DACR 01 DACL 10 Right Analog Mixer 11 Left Analog Mixer 0x0 ESPPA_MUTE All input source to Earpiece PA mute including Left Output mixer and Internal DACL 0 1 On 0x0 ESPPA_EN Earpiece Power Amplifier Enable 0 Disable 1 Enable 4 0 0x0 ESP_VOL Earpiece Volume Control Total 31 level from OdB to 43 5dB 1 5dB step mute when 00000 amp 00001 Reg 58h Speaker Output Control Register Default 0x0880 Register Name SPKOUT CTRL Bit R W Default Description 15 13 R W 0 0 Reserved RSPKS Right speaker input source select 0 MIXR 1 MIXL MIXR 12 R W RSPKINVEN 11 R W 0x1 Right speaker negative output enable 0 Disable 1 Enable 10 RSPK EN 9 R W 0x0 Right Speaker Enable 0 Disable 1 Enable LSPKS Left speaker input source select 0 MIXL 1 MIXL MIXR LSPKINVEN 7 R W 0x1 Left speaker negative output enable 0 Disable 1 Enable 8 R W 0x0 6
53. I2S1_DACLO_ENA 1251 DAC Timeslot 0 left channel enable 0 Disable 1 Enable 14 R W 0 0 1251 DACRO 1251 DAC Timeslot 0 right channel enable 0 Disable 1 Enable 13 R W 0 0 I2S1_DACL1_ENA 1251 DAC Timeslot 1 left channel enable 0 Disable 1 Enable 12 R W 0 0 1251 DACRI 1251 DAC Timeslot 1 right channel enable 0 Disable 1 Enable 11 10 R W 0 0 1251 DACLO SRC I2S1 DAC Timeslot 0 left channel data source select 00 1251 DACLO 01 1251 10 251 0 1251 DACRO 11 1251 0 1251 DACRO 2 9 8 R W 0x0 DS1 DACRO SRC 1251 DAC Timeslot 0 right channel data source select 00 2S1 DACRO 01 1251 DACLO 10 1251 DACLO DS1 DACRO 11 2S1_DACL0 I2S1_DACR0 2 7 6 R W 5 4 R W 0x0 0x0 I2S1_DACL1_SRC 1251 DAC Timeslot 1 left channel data source select 00 1251 01 1251 DACRI 10 1251 DACLI DS1 DACRI 11 1251 1 1281 DACR1 2 1281 DACRI SRC 1251 DAC Timeslot 1 right channel data source select 00 1251 DACRI 01 2S1 DACLI 10 1251 DACL1 I2S1 DACR1 11 1251 DACL1 2S1 DACR1 2 0 0 1251 DACP 1251 DAC Companding enable 8 bit mode only 00 Disable 01 Enable 0x0 DS1 DACP SEL 1251 DAC Companding mode select 0 A law 1 u law 0 0 Reserved 0 0 1251 LOOP 1251 loopback enable 0 No loopback 1 Loopbac
54. K Polarity 0 Normal 1 Inverted 13 R W 0 0 1253 1253 LRCK Polarity 0 Normal 1 Inverted 12 6 R W 0 0 Reserved 5 4 R W 0 0 1283 WORD SIZ 1253 digital interface world length 00 8bit 01 16bit 10 20bit 11 24bit 3 2 1 0 R W R W 0 0 0 0 Reserved 1283 CLOC SRC 1253 BCLK LRCK source control 0 BCLK LRCK Come from 1251 1 BCLK LRCK Come from 1252 2 BCLK LRCK is generated by 1253 and the source clock is DSICLK 3 Reserved Reg 31h 1253 SDOUT Control Register Default 0x0000 Register Name I283 SDOUT Bit Read Write Default Description 15 4 R W 0 0 Reserved I283 ADCP ENA 1253 ADC Companding enable 3 R W 0x0 00 Disable 01 Enable 12583 ADCP SEL 1253 ADC Companding mode select 2 R W 0x0 0 A law 1 u law 1 0 R W 0x0 Reserved Reg 32h 1253 SDIN Control Register Default 0x0000 Register Name I283 SDIN CTRL Bit Read Write Default Description 15 4 R W 0x0 Reserved I2S3_DACP_ENA 1253 DAC Companding enable 8 bit mode only 3 R W 0x0 00 Disable 01 Enable 1253 DACP SEL 1253 DAC Companding mode select 2 R W 0x0 00 u law 01 A law 1 R W 0x0 Reserved 1253 1253 loopback enable 0 R W 0x0 0 No loopback 1 Loopback SDOUT3 data output to SDOUT3 data input Reg 33h 12
55. KOUTLN R 10KQ FScale Output Level OdB 1KHz 1 8 Vrms SNR A weighted OdB 1KHz 102 dB THD N OdB 1KHz 82 dB DC Offset at load OdB 1KHz 0 7 mV DAC to LINEOUT signal on LINEOUTP and LINEOUTN R 10KQ FScale Output Level OdB 1KHz 0 9 Vrms SNR A weighted OdB 1KHz 98 dB THD N OdB 1KHz 81 dB DC Offset at load OdB 1KHz 0 5 mV ADC Input Path MIC1 2 3to ADC via ADC mixer Performance FScale Input Level 0dB Gain 1KHz 0 5 Vrms SNR A weighted 1dB 1KHz 0dB Gain 96 dB Bypass Path Performance THD N 1dB 1KHz OdB Gain 85 dB SNR A weighted 30mV 1 KHz 30dB Gain 81 dB THD N 30mV 1 KHz 30dB Gain 76 SNR A weighted 30mV 1 KHz 39dB Gain 81 dB THD N 30mV 1 KHz 39dB Gain 76 SNR A weighted 10mV 1 KHz 48dB Gain 73 dB THD N 10mV 1 KHz 48dB Gain 72 LINEIN to ADC via mixer FScale Input Level OdB 1KHz 0 9 Vrms SNR A weighted 1KHz 93 dB THD N 1KHz 85 dB Crosstalk L R 1KHz 85 85 dB AXIIN to ADC via ADC mixer FScale Input Level OdB 1KHz 0 9 Vrms SNR A weighted 1KHz 92 dB THD N 1KHz 82 dB Crosstalk L R 1KHz 88 88 dB MIC1 2 3 to Headphone via output mixer FScale Input Level OdB Gain 1KHz 0 5 Vrms SNR A weighted 1dB 1KHz OdB Gain 98 dB THD N 1dB 1KHz OdB Gain 91 SNR A weighted 30mV 1 KHz 30dB Gain 83 dB THD N 30mV 1 KHz 30dB Gain 78 SNR A weighted 30mV 1 KHz
56. M 42 2382 1 24 576M 19 2M 25 96 1 24 576 Table2 clock setting for SYSCLK 22 5792 MHz FOUT 22 5790M 22 5792 22 5792 22 5792 22 5792 22 5789M 22 5789M 22 5792 11 4 TWI RSB Interface 100 can support two series control interface protocol for writing to or readback from registers on SCK and SDA pins One is TWI interface the other is RSB interface RSB is top priority for higher efficiency and lower power consumption 11 4 1 TWIInterface TWI is a 2 wire SCK SDA half duplex serial communication interface supporting only slave mode SCK is used for clock and SDA is for data SCK clock supports up to 400 KHz rate and SDA data is a open drain structure A master controller initiates the transmission by sending a start signal which is defined as a high to low transition at SDA while SCK is high The first byte transferred is the slave address It is 7 bit chip address followed by a R W bit The chip address must be 0011010x The R W bit indicates the slave data transfer direction Once an acknowledge bit is received the data transfer starts to proceed on a byte by byte basis in the direction specified by the R W bit The master can terminate the communication by generating a stop signal which is defined as a low to high transition at SDA while SCK is high e w Jd 4 Wi START ADDRESS R W ACK DATA ACK DATA ACK STOP Figure7 TWI Interface The
57. Ox1F 90dB the same as Ox1E Reg 8fh ADC DAP Left Input Signal High Average Coef Register Default 0x0005 Register Name AC ADC DAPLHNAC Bit Read Write Default Description 15 11 Left input signal average filter coefficient to check noise or not the coefficient reg8f 10 0 reg90 is 3 24 format 2s complement always the same as the left output signal 10 0 R W 0x0005 average filter s Reg 90h ADC DAP Left Input Signal Low Average Coef Register Default OX IEBS Register Name AC ADC DAPLLNAC Bit Read Write Default Description Left input signal average filter coefficient to check noise or not the coefficient reg8f 10 0 reg90 is 3 24 format 2s complement always the same as the left output signal 15 0 R W 0x0005 average filter s Reg 91h ADC DAP Right Input Signal High Average Coef Register Default 0x0005 Register Name AC ADC DAPRHNAC Bit Read Write Default Description 15 11 Right input signal average filter coefficient to check noise or not the coefficient reg91 10 0 reg92 is 3 24 format 2s complement always the same as the right output signal 10 0 R W 0x0005 average filter s Reg 92h ADC DAP Right Input Signal Low Average Coef Register Default OX LEB8 Register Name AC ADC DAPRLNAC Bit Read Write Default Description Right input signal average filter coefficient to check no
58. Register List Register Name Offset Description CHIP AUDIO RST 00H Chip Soft Reset PLL 02H PLL Configure Control 1 PLL_CTRL2 03H PLL Configure Control 2 SYSCLK_CTRL 04H System Clocking Control MOD_RST_CTRL 05H Module Clock Enable Control ADDA_SR_CTRL 06H ADDA Sample Rate Configuration DSILCK CTRL 10H DS1 BCLK LRCK Control DS1 SDIN 11H 1281 SDIN Control DS1 SDOUT CTRL 12H DS1 SDOUT Control 1251 DIG MIXER 13H 1251 Digital Mixer Control DSi VOL CTRLI 14H I2S1 Volume Control 1 DSi VOL 2 15H I2S1 Volume Control 2 DS1 VOL CTRL3 16H 1251 Volume Control 3 DS1 VOL CTRIA 17H 1251 Volume Control 4 DSi GAIN 18H 1251 Digital Mixer Gain Control DS2 CLK CTRL 20H DS2 BCLK LRCK Control DS2 SDIN CTRL 21H 1252 SDIN Control DS2 SDOUT 22H 1252 SDOUT Control 1252 DIG MIXER 23H 1252 Digital Mixer Control 1282 VOL CTRLI 24H I2S2 Volume Control 1 DS2 VOL CTRL2 26H I2S2 Volume Control 2 1252 GAIN 28H 1252 Digital Mixer Gain Control 1263 CTRL 30H 1253 BCLK LRCK Control 1263 SDIN 31H I283 SDIN Control 1253 SDOUT 32H 1253 SDOUT Control DS3 SGP CTRL 33H 1253 Signal Path Control ADC DIG CTRL 40H ADC Digital Control TBD ds us RTC CTRL REG BO h RTC Control Register RTC RESET REG Bl h RTC Reset Register ALM_INT_ENA_REG B2 h Alarm Interrupt Enable Register ALM_IN
59. SDIN MQ 2 1 2 IPM LSBIMSB 1 58 6050 SIZE y SIZE y Pem mode B BCLK INV 1 Figure21 Pcm mode B mono LRCK INV 1 LRCK SDIN SDOUT LRCK DIV Left channel Right channel SLOTO Left channel SLOTI Left channel SLOTO Right channel SLOTl Right channe 1 MSB 2 Tic Tus 1 2 n BARS n TAEA LSB MSB LSB MSB LSB SB LS lt WORD SIZE lt WORD SIZE l WORD SIZE WORD SIZE 5107507 Nu SLOT SIZE yy 4 SLOT SIZE pa SLOT SIZE y 125 TDM mode Figure 22 125 TDM mode LRCK DIV i Left channel SLOTI Left channelSLOTO Right channellSLOT1 Right channe I2 een Lies 5 LSB MSB S MSB LSB MSB LSB lt WORD SIZE lt WORD SIZE lt WORD SIZE a WORD SIZE SLOT 512 SLOT 512 SLOT 512 SLOT 5127 p lt gt q gt lt a Figure 23 PCM TDM mode PCM TDM mode Y 11 6 Stereo ADC The stereo ADC is used for recording stereo sound The sample rate of the stereo ADC can not be independent of DAC sample rate In other words the stereo ADC and DAC must work at a same sample rate The sample rate is configured by the register ADDA FS 1251 or ADDA FS 1252 depending on which I2SnCLK selected
60. SET 5 0 R W 0x1 These bits represent the current day value coded in BCD format The value should be from 1 to 31 Reg ddh Alarm Months Register Default 0x0001 Register Name ALM MON REG Bit Read Write Default Description ALM MON ENA 15 R W 0 0 alarm enable bit 0 Disable month alarm 1 Enable month alarm 14 5 ALM MON SET 4 0 R W 0 1 These bits represent the current day value coded BCD format The value should be from 1 to 12 Reg deh Alarm Years Register Default 0x0000 Register Name ALM YEA REG Bit Read Write Default Description YEA Year alarm enable bit 15 R W 0x0 0 Disable year alarm 1 Enable year alarm 14 5 7 0 R W 0x0 ALM_YEA_SET These bits represent the current day value coded in BCD format Reg dfh Alarm Update Trigger Default 0x0000 Register Name ALM_UPD_TRIG Bit Read Write Default Description Time Week Date write trigger 0 Nothing will happen 15 R W 0 0 E MEOS 1 Writing a 1 to this bit will update the alarm Time Week Date value This bit will always be 0 when being read 14 1 R W 0x0 Reserved REG D8H REG DEH Read control 0 R W 0 0 0 Read the effective alarm setting value 1 Read the value of D8H REG written by host Reg e0h efh RTC General Purpose Register n n 0 15 Default 0x0000 Regist
61. T_STA_REG B3 h Alarm Interrupt Status Register RTC_SEC_REG B4 h RTC Seconds Register RTC_MIN_REG BS h RTC Minutes Register RTC_HOU_REG B6h RTC Hours Register RTC WEE REG B7 h RTC Weekdays Register RTC_DAY_REG BS8 h Days Register RTC MON REG B9 h RTC Months Register RTC YEA REG BAh Years Register ALM SEC REG C3 h Alarm Seconds Register ALM_MIN_REG Alarm Minutes Register HOU C5 h Alarm Hours Register WEE C6 h Alarm Weekdays Register ALM DAY REG CTh Alarm Days Register MON REG C8 h Alarm Months Register ALM YEA REG Ch Alarm Years Register RTC_GP_REGn DO h RTC General Purpose Register n n 0 1 2 31 Reg 00 Chip Soft Reset Register Default 0x0101 Bit Read Write Default Register Name CHIP AUDIO RST Description 15 0 R W 0 0101 Writing to this register resets all register to their default state Reading from this register will indicate device type and version Reg 01h PLL Configure Control 1 Register Default 0x0141 Register Name CTRL1 Bit Read Write Default Description 15 14 R W 0x0 DPLL_DAC_BIAS 00 min 11 max 13 8 R W 0x1 PLL_POSTDIV_M PLL Post Divider Factor M Factor 0 M 64 Factor 1 M 1 Factor 63 M 63 R W 0x0 Reserved R W 0x1 Close_loop 1 work as a PLL 0 work as a free run
62. be enabled in the digital recording path of AC100 It automatically adjusts the ADC recording volume gain to a target volume level Input Signal Output Target Signal Level 1 1 Gain 1 Figure 36 Response Characteristic The ADC Digital Part includes automatic gain control AGC for ADC recording AGC can be used to maintain a nominally constant output level when recording speech As opposed to manually setting the PGA gain in the AGC mode the circuitry automatically adjusts the PGA gain as the input signal becomes overly loud or weak such as when aperson speaking into a microphone moves closer to or farther from the microphone The AGC algorithm has several programmable parameters including target gain attack and decay time constants noise threshold and max PGA applicable that allow the algorithm to be fine tuned for any particular application The algorithm uses the absolute average of the signal which is the average of the absolute value of the signal as a measure of the nominal amplitude of the output signal Because the gain can be changed at the sample interval time the AGC algorithm operates at the ADC sample rate The AGC programs to a wide range of attack and decay skew time from 32 fs to 2 15 32 fs When noise cancellation used in system the should be implement by soft because of hardware noise cancellation The AGC process should be after noise cancella
63. ble 1 Enable 11 9 7 0 R W R W Oxf 0x80 HP DCRM EN Headphone DC offset remove function enable 0 Disable 1 Enable To remove the headphone buffer DC offset this bit must be set Oxf before headphone PA enabled and this bit must be set 0x0 before headphone PA disabled Reserved Reg 54h_Output Mixer Source Select Register Default 0x0000 Register Name OMIXER_SR Bit R W Default Description 15 14 0 0 RMIXMUTE Right Output Mixer Mute Control 0 Mute 1 On Bit 13 MICI Boost stage Bit 12 MIC2 Boost stage Bit 11 LINEINL LINEINR Bit 10 LINEINR Bit 9 AUXINR Bit 8 DACR Bit 7 DACL 6 0 0 0 LMIXMUTE Left Output Mixer Mute Control 0 Mute 1 Bit 6 MICI Boost stage Bit 5 MIC2 Boost stage Bit 4 LINEINL LINEINR Bit 3 LINEINL Bit 2 AUXINL Bit 1 DACL Bit 0 DACR Reg 55h Output Mixer Source Boost Register Bit Default 0x56DB R W Default Register Name OMIXER BST1 CTRL Description 15 14 R W 0x1 HBIASSEL HMICBIAS voltage level select 13 12 11 9 R W R W 0x1 0x3 00 1 88V 01 2 09V 10 2 33V 11 2 50V MBIASSEL MMICBIAS voltage level select 00 1 88V 01 2 09V 10 2 33V 11 2 50V AXG AXin to L or R output mixer Gain control From 4 5dB to 6dB 1 5dB step default 15 OdB 8 6 5 3 0 3 0 3
64. coded in BCD format The value should be from 0 to 6 000 Sunday 001 Monday 2 0 R W 0x0 010 Tuesday 011 Wednesday 100 Thursday 101 Friday 110 Saturday Reg cch_RTC Days Register Default 0x0001 Register Name RTC DAY_REG Bit Read Write Default Description 15 6 RTC DAY 5 0 R W 0x1 These bits represent the current day value coded in BCD format The value should be from 1 to 31 Reg cdh_RTC Months Register Default 0x0001 Register Name RTC_MON_REG Bit Read Write Default Description 15 5 RTC MON 4 0 R W 0 1 These bits represent the current day value coded in BCD format The value should be from 1 to 12 Reg RTC Years Register Default 0x0000 Register Name RTC YEA REG Bit Read Write Default Description LEAP YEAR 0 Not leap year 15 R W 0x0 1 Leap year This bit will not set by hardware It should be set or clear by 14 8 software 7 0 0 0 YEA These bits represent the current day value coded BCD format The max value is 99 0x10011001 Reg cfh RTC Update Trigger Default 0x0000 Register Name UPD TRIG Bit Read Write Default Description Time Week Date write trigger 15 0 0 0 will 1 Writing 1 to this bit will update the Time Week Date value This bit will always be
65. ending bit write 1 to clear 0 No Pending Interrupt 1 Plug in Irq Pending Interrupt HMIC KEYUP PENDING Hmic Key Up Irq pending bit write 1 to clear 0 No Pending Interrupt 1 Key up Irq Pending Interrupt HMIC KEYDOWN PENDING Hmic Key Down Irq pending bit write 1 to clear 0 No Pending Interrupt 1 Key down Irq Pending Interrupt R W 0 0 DATA PENDING Hmic Data Irq pending bit write 1 to clear 0 No Pending Interrupt 1 Data Irq Pending Interrupt Reg 48h DAC Digital Control Register Default 0x0000 Register Name DAC DIG Bit 15 Read Write Default 0x0 Description ENDA DAC Digital Part Enable 14 13 12 R W R W R W 0 0 0 0 0 0 0 Disabe 1 Enable ENHPF HPF Function Enable 0 Enable 1 Disable DAFIR32 Enable 32 tap FIR filter 0 64 tap 1 32 tap Reserved 11 8 0 0 MODQU Internal DAC Quantization Levels Levels 7 21 MODQUJ3 0 128 Default levels 7 21 128 1 15 7 0 R W 0 0 Reserved Reg 49h DAC Volume Control Register Default 0xA0A0 Register Name DAC VOL CTRL Bit Read Write Default Description 15 8 7 0 OxAO OxAO DAC VOL L DAC left channel volume 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01 119 25dB Ox9F 0 75dB 0 0dB 0 75dB OxFF 71 25dB DAC VOL R DAC ri
66. er Name RTC GP REGn Bit Read Write Default Description RTC GP DATn 15 0 R W 0x0 These bits art used to save data n 0 15
67. g In EarPhones Pull Out Key Down Key Up mu HOOOH Figure31 HBIAS Detect IRQ Timing Diagram 11 13 Interrupt Interrupt circuits ac100 generate an Interrupt IRQ event to enable the detection of audio jack status The Interrupt pin IRQ AUDIO is open drain It s usually drives a high level voltage via the external pull up resistor while it output a low level when the IRQ is active It supports the following triggered events illustrated in the figure below DAC IRQ EN DAC IRQ gt AND ADC IRQ EN ADC IRQ AND KEYDOWN IRQ EN KEYDOWN IRQ AND IRQ KEYUP IRQ EN KEYUP IRQ AND OR PLUGIN IRQ PLUGIN IRQ AND PULLOUT IRQ EN PULLOUT IRQ AND HMICDATA IRQ HMICDATA_IRQ AND L Figure 32 Interrupt trigger Diagram 11 14 Digital Audio Process for The DAP System Block Diagram For ADC Dc audio DAC ENA Oxb4 15 6 I Figure 33 ADC DAP System Block DAP for ADC Data Flow DAP for ADC 0 78 13 Alpha filter Lvolume Rvolume Alpha filter 0 7 13 Figure34 ADCDAPData Flow 11 14 1 High Pass Filter The High Pass Filter HPF 3dB cutoff lt remove DC offset from ADC recording data The HPF can also be bypassed Figure 35 HPF Characteristic in DAP 11 14 2 Auto Gain Control The automatic gain control AGC can
68. ght channel volume 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01 119 25dB Ox9F 0 75dB 0dB 0 75dB OxFF 71 25dB Reg 4ch DAC Digital Mixer Source Select Register Default 0x0000 Register Name DAC MXR SRC Bit Read Write Default Description 15 12 0 0 DACL_MXR_SRC DAC left channel mixer source select 0 Disable 1 Bit15 I2S1_DAOL Bitl4 I2S1_DA1L Bit13 DS2 DACL Bit12 ADCL 11 8 0 0 DACR SRC DAC right channel mixer source select 0 Disable Bit11 1251 DAOR Bit10 DS1 DAIR Bit9 1252 DACR Bit8 ADCR 7 0 R W 0 0 Reserved Reg 4dh DAC Digital Mixer Gain Control Register Default 0x0000 Register Name DAC GAIN Bit 15 12 Read Write Default 0x0 Description DACL_MXR_GAIN DAC left channel mixer gain control 0 0dB 1 6dB Bit15 2S1_DAOL Bitl4 1251 DAIL Bit13 2S2 DACL Bit12 ADCL 11 8 0 0 GAIN DAC right channel mixer gain control 0 0dB 1 6dB Bit11 1251 DAOR Bit10 DS1 DAIR Bit9 1252 DACR Bit8 ADCR 7 0 R W 0 0 Reserved Reg 50h ADC Analog Control Register Default 0x3340 Register Name ADC Bit R W Default Description ADCREN 15 R W 0x0 ADC Right channel Enable 0 Disable 1 Enable ADCRG 14 12 R W 0x
69. grated charge pump for reference 18mW 1 8V Mono differential earpiece driver gt 65 mW CH THD N lt 70dB 16Ohm Load Two stereo differential speaker outputs using external amplifier to drive the loud speaker Differential Line output with 1 Vrms full scale output voltage Five audio inputs Three differential analog microphone inputs with 30dB 48dB boost amplifier gain One mono differential or single ended line in input One stereo auxiliary input for external accessory connection Two low noise analog microphone bias Audio jack insert button press detection TWI RSB control interface 24 bit SKHz 192KHz 25 interface Support Dynamic Range Controller DRC adjusting the DAC playback output Support Automatic Gain Control AGC adjusting the ADC recording output SRC for synchronisation between audio interface or digital audio data mixing Soft mute circuit for pop noise suppression Support digital microphone interface RTC and Three clock output QEN 68 pin package 8mm x 8mm 3 Applications Tablets Smart Phone and Music phone 4 Functional Block Diagram 4 1 Functional Block Diagram
70. is ensures that noise is not amplified in the absence of speech Noise threshold level in AGC algorithm is programmable from 30dB to 90dB of full scale This operation includes hysteresis and debounce to avoid AGC gain from cycling between high gain and OdB when signals are near the noise threshold level The noise or silence detection feature can be entirely disabled by the user PGA applicable allows the designer to restrict the maximum gain applied by the This be used for limiting PGA gain in situations where environmental noise is greater than the programmed noise threshold Microphone input Max PGA applicable can be programmed from OdB to 40dB in steps of 0 5dB Hysteresis as the name suggests determines a window around the noise threshold which must be exceeded to detect that the recorded signal 1s indeed either noise or signal If initially the energy of the recorded signal is greater than the noise threshold then the AGC recognizes it as noise only when the energy of the recorded signal falls below the noise threshold by a value given by hysteresis Similarly after the recorded signal is recognized as noise for the AGC to recognize it as a signal its energy must exceed the noise threshold by a value given by the hysteresis setting In order to prevent the AGC from jumping between noise and signal states which can happen when the energy of recorded signal is close to the noise threshold a n
71. ise or not the coefficient reg91 10 0 reg92 is 3 24 format 2s complement always the same as the right output signal 15 0 R W Ox1EB8 average filter s Reg 93h_ADC DAP High HPF Coef Register Default OxOOFF Register Name AC_DAPHHPFC Bit Read Write Default Description 15 11 10 0 0 00 HPF coefficient setting the coefficient reg93 10 0 reg14 is 3 24 format 2s complement Reg 94h ADC DAP Low HPF Coef Register Default OXFACI Register Name AC DAPLHPFC Bit Read Write Default Description 15 0 R W OxFACI HPF coefficient setting the coefficient reg93 10 0 reg14 is 3 24 format 2s complement Reg 95h ADC DAP Optimum Register Default 0x0000 Register Name AC DAPOPT Bit Read Write Default Description 15 11 Left energy default value set ng include the input and 10 R W 0 0 1 Left channel gain hystersis setting The different between target level and the signal level must larger than the hystersis when the gain change 9 8 R W 00 00 0 4375db 01 0 9375db 10 1 9375db 11 3db 7 6 The input signal average filter coefficient setting 5 R W 0 0 15 the reg8f 10 0 reg90 and reg91 1 0 reg92 1 is the reg86 10 0 reg87 and reg88 1 0 reg89 AGC output when the channel in noise state 4 R W 0 0 output is zero 1
72. k SDOUT1 data output to SDOUT data input Reg 13h 1251 Digital Mixer Source Select Register Default 0x0000 Register Name 1251 SRC Bit Read Write Default Description 15 12 R W 0 0 1251 ADCLO MXL SRC 1251 ADC Timeslot 0 left channel mixer source select 0 Disable 1 Enable Bit15 I2S1_DAOL data Bit14 1252 DACL data Bit13 ADCL data Bit12 I282 DACR data 11 8 R W 0x0 1251 ADCRO SRC 12851 ADC Timeslot 0 right channel mixer source select 0 Disable 1 Enable Bit11 1251 DAOR data Bit10 1252 data Bit9 ADCR data Bit8 I282 DACL data 7 6 R W 0x0 I2S1_ADCL1_MXR_SRC 1251 ADC Timeslot 1 left channel mixer source select 0 Disable 1 Enable Bit7 I2S2_DACL data Bit6 ADCL data 5 4 R W 0 0 Reserved 3 2 R W 0x0 I2S1_ADCR1_MXR_SRC I2S1 ADC Timeslot 1 right channel mixer source select 0 Disable 1 Enable Bit3 282 DACR data Bit2 ADCR data 1 0 R W 0 0 Reserved Reg 14h 1251 Volume Control 1 Register Default 0xA0A0 Bit Read Write Default Register Name I2 1 VOL Description 15 8 R W 7 0 R W OxAO OxAO DSi ADCLO VOL 1251 Timeslot 0 left channel volume 119 25dB To 71 25dB 0 75dB Step 0x00 Mute 0x01 119 25dB Ox9F 0 75dB 0dB 1 0 75dB OxFF 71 2548 1251 ADCRO VOL 1251 ADC Timeslot 0 right channel volume
73. kage Noe eee sadness 13 T Pin Signal Desctiption s uber Moore ee emet 14 8 Electrical Chatactetistics os atomorum tere eet RARE 16 8 1 Absolute 2 12 1244 0 thin A 16 8 2 Recommended Operating Conditions essent nennen 16 8 3 Static Chiaracte WCS iere tere e Rie a nen 17 9 Analog Pefformance TE uon iere ferner eee te bern 18 10 Typidial POWER COnSUg DOR se rit tte er re ete 20 IH Winction Desclption ected dee hain 21 lh 21 D 22 Clock eet EORR RE 22 S 24 11 4 TWI RSB Interface 25 LEA T EW interface etre 25 11 45 RSB Interface eme RP RR RON E de reta 26 11 5 ID2S PCM Int rf ce erret t ett RO re CR et evi o n erae een 28 TA Os SterEO De EE 32 TT Stereo DAC decore e e EO 32 1156 ett dedidit edited cett dietis 32 11 8 1 DAC Output Mixers rer rte tn ent Nee epe 32 11 8 2 ADC Record Mixers cect cece sette 32 11 8 3 Digital Mixets Oe ee 33 11 9 Analogue Audio
74. l playback path of 100 It automatically adjusts the wide volume gain to flatten volume level 1 1 Transfer Function Implemented Transfer Function DRC Compensated Output T DRC Input Level Figure 41 DRC Response Characteristic The DRC supports the main feature below Compression Smooth Filter Control filter 0x46 a 0x48 T decay attack 0x47 1 a 0x49 K 0x4B a 0x4D 0x4A 0 Ox4C 1 Ox4E 1 Note The address is the coefficient ram address Figure 42 DRC Block and Register Control Adjustable threshold offset and compression levels Programmable energy coefficient attack and decay time constants Transparent compression Compressors can attack fast enough to avoid apparent clipping before engaging and decay times can be set slow enough to avoid pumping DRC parameter setting Numbers formatted as N M numbers means that there are N bits to the left of the decimal point including the sign bit and M bits to the right of the decimal point For example Numbers formatted 3 24 means that there are 3 bits at the left of the decimal point and 24 bits at the right decimal point Energy Filter The Energy Filter is to estimate of the RMS value of the audio data stream into DRC and has two parameters which determine the time window over which RMS to be made The parameter is computed by a 1 y n Alpha filter structure Figure 43 Energ
75. lt 0x0000 Register Name I282 CTRL Bit Read Write Default Description 15 R W 0 0 1252 MSTR MOD 1252 Audio Interface mode select 0 Master mode 1 Slave mode 14 R W 0x0 I2S2_BCLK_INV I2S2 BCLK Polarity 0 Normal 1 Inverted 13 R W 0x0 I2S2_LRCK_INV 1252 LRCK Polarity 0 Normal 1 Inverted 12 9 8 6 5 4 R W R W R W 0x0 0x0 0x0 I2S2_BCLK_DIV Select the I2S2CLK BCLK2 ratio 0000 DS2CLK 1 0001 DS2CLK 2 0010 I2S2CLK 4 0011 I2S2CLK 6 0100 DS2CLK 8 0101 DS2CLK 12 0110 I2S2CLK 16 0111 DS2CLK 24 1000 DS2CLK 32 1001 I2S2CLK 48 1010 DS2CLK 64 1011 I2S2CLK 96 1100 I2S2CLK 128 1101 I2S2CLK 192 1110 Reserved 1111 Reserved 1252 LRCK Select BCLK2 LRCK2 ratio 000 16 001 32 010 64 011 128 100 256 1xx Reserved 1282 WORD SIZ 1252 digital interface world length 00 8bit 01 16bit 10 20bit 11 24bit 3 2 R W 0 0 1282 FMT 125 digital interface data format 00 I2S mode 01 Left mode 10 Right mode 11 DSP mode I282 MONO PCM 1252 Mono PCM mode select 1 R W 0 0 0 Stereo mode select 1 Mono mode select 0 R W 0 0 Reserved Reg 21h 1252 SDOUT Control Register Default 0x0000 Register Name I282 SDOUT CTRL Bit Read Write Default Description 15 R W 0 0 12582 ADCL 1252 A
76. n this bit is set 1 the relevant registers will stop rolling over such as second minute hour ext 0 No stop 1 Stop rolling over 0 0 12H 24 MODE 0 12 hour mode 1 24 hour mode Reg c8h Seconds Register Default 0x0000 Register Name RTC SEC REG Bit Read Write Default Description 15 7 RTC SEC These bits represent the current second value coded in BCD format 6 0 R W 0x0 The value should be from 0 to 59 For example if the 6 0 is 1011001 this represents the value 59 Reg c9h Minutes Register Default 0x0000 Register Name RTC MIN REG Bit Read Write Default Description 15 7 RTC MIN 6 0 R W 0x0 These bits represent the current minute value coded in BCD format The value should be from 0 to 59 Reg Hours Register Default 0x0001 Register Name REG Bit Read Write Default Description 15 9 AM PM SEL select 8 R W 0x0 0 AM 1 PM 7 6 5 0 0x1 RTC These bits represent the current hour value coded BCD format The value should be from 0 to 23 Reg cbh_RTC Weekdays Register Default 0x0000 Register Name RTC WEE REG Bit Read Write Default Description 15 3 RTC WEE These bits represent the current weekday value
77. nd product software developers The manual assumes that the reader has a background in computer engineering and or software engineering and understands concepts of digital system design microprocessor architecture Input Output I O devices industry standard communication and device interface protocols Organization This document aims to describe the 100 from following aspects block diagram pin assignment pin signal description electrical characteristics typical application system description and register description Revision History Version Date Description V0 1 2014 3 3 Complete Draft V0 2 2014 5 14 Modify the format V1 0 2014 6 10 Modify the format Table of Contents Declaration 4c v A s a T 2 About Documentation dede tte detiene oi e e et EA Ies 3 Revision eterne te ect te Re ere nce Ati ee ecu re ec te 4 Table OF COMMS A 5 k D eScriptIOnc saei oce RES 8 MEE AME 9 3 Applications tute tete tete eene ee Dee eie 10 4 Functional Block be KR coe ee etiem etse 10 4 1 Functional Block Diagram 10 4 2 Data Path Diarani iueiio o Net ein en ee e n enn 11 5 Pin Ascignment ente aro EES PE mmt 12 6 Pac
78. ning VCO at a pre fixed frequency 5 0 R W 0x1 INT Integ 5 0 the loop bandwidth config 0 works as free running mode 1 small bandwidth need more time to lock 63 large bandwidth need less time to lock but may result in failing Reg 02h PLL Configure Control 2 Register Default 0x0000 Register Name CTRL2 Bit 15 Read Write R W Default 0 0 Description PLL EN PLL Enable 0 Disable 1 Enable The PLL output FOUT FIN N M 2K 1 NZN 1 3 f 14 0 0 PLL Locked status 0 Not locked or not enabled 1 Enabled and locked 13 4 R W 0 0 PLL PREDIV PLL Integer Part of Pre Divider Factor N Factor 0 N 1 0 1 i 1 Factor 1023 N_i 1023 2 0 R W 0 0 PLL POSTDIV NF PLL Fractional Part of Pre Divider Factor N Factor 0 1 0 0 2 Factor 1 N 1 0 2 Factor 7 f27 0 2 Reg 03h System Clocking Control Register Default 0x0000 Register Name SYSCLK Bit Read Write Default Description 15 R W 0 0 PLLCLK PLLCLK Enable 0 Disable 1 Enable 14 R W 0x0 Reserved 13 12 0x0 PLLCLK_SRC PLL Clock Source Select 00 MCLK1 01 MCLK2 10 BCLK1 11 BCLK2 11 R W 0x0 DSICLK ENA I2S1CLK Enable 0 Disable 1 Enable 10 R W 0 0 Reserved 9
79. nternal LDO 11 2 Clock The system clock SYSCLK of AC100 must be 512 fs fs 48KHz or 44 1KHz So the system should arrange the divider to generate 24 576MHz for audio clock series of 48KHz or 22 5792MHz for series of 44 1KHz SYSCLK be selected from I2S1CLK or I2S2CLK which derived from MCLKI MCLK2 or PLL MCLK1 and MCLK2 are always provided externally while the PLL reference clock can be select from MCLK1 MCLK2 BCLK1 BCLK2 DSICLK is the reference of the first 125 clocking zone I2S2CLK is the reference of the second 125 clocking zone The third I2S only support master mode Its clocking zone must be synchronized with either of the I2SnCLK n 1 2 In master mode LRCK and BCLK are derived internally from I2SnCLK In slave mode LRCK and SCLK are supplied externally and BCLK can be used as the PLL input reference SYSCLK is the reference of ADC DAC DVC MIXER AGC and DRC module If SRC1 or SRC2 is used SYSCLK must be set by PLL then the SRCnCLK is auto provided for SRC module If all the relevant module above is not used the SYSCLK needn t be configured There are also an internal Oscillator to generate a clock signal for direct path mode In this mode the oscillator supply clock to charge pump adjustment circuit headphone detect circuite g In direct path case no external clock need MCLKI C4 MCLK2O BCLKI BCLK AC100 CLOCK SYSTEM
80. nual setting ratio low 16 bit Reg beh SRC2 Control 3 Register Default 0x0040 Register Name SRC2 CTRL3 Bit Read Write Default Description SRC2 FIFO LEV 5 0 15 10 R 0x0 SRC2 FIFO Level low 6 bit SRC2 RATI VAL 25 16 Calculated ratio high 10 bit 9 0 R 0 0 Reg bfh_SRC2 Control 4 Register Default 0x0000 Register Name SRC2_CTRL4 Bit Read Write Default Description SRC2 RATI VAL 15 0 Calculated ratio low 16 bit 15 0 R 0x0 Reg c0h_RTC Analog Control Register Default 0x003F Register Name CLK32KOUT ACTRL Bit Read Write Default Description 15 8 R W 0x00 Reserved 6 4 3 2 R W R W R W 0 0 0 3 0 3 0x1 0x1 CLK32AP_OD_CTR CLK32KAP Output Pin Open Drain mode control 0 push pull 1 reserved VBG_TRM VIO RIC Voltage trimming 0 1 08V 1 1 12V 2 1 16V 3 12V 4 1 24V 5 1 28V 6 1 32V 7 1 36V XTAL G xtal gain control 3 largest gain 0 smallest gain XTAL DEB xtal fater startup config 0 slower startup 1 faster startup xtal enable 0 xtal disable 1 xtal enable Reg clh CK32K Output Control Register 1 Default 0x00e1 Register Name 2 OUT CTRL1 Bit Read Write Default Description 15 8 R W 0 0 Reserved 7 5 0 3 CK32KAP PRE DIV Pre division after 4MHz input from ADDA 000 1 001 2
81. o smooth the gain and control the ratio of gain increase and decrease The decay time and attack is shown in Figure 5 The structure of the Gain Smooth filter is also the Alpha filter so the rise time computation is the same as the Energy filter which is 2 2 a l e ain 8 Attack time gt Figure 44 Smooth Filter Characteristic 11 16 Module There a real time clock RTC module in 100 for calendar usage The module provides second minute hour weekday day month and year information as well as alarm wakeup The external 32 768kHz crystal oscillator is need to provide a low power accurate reference The RTC fans out three 32 768 kHz outputs CKO2 and CKO3 derived from external oscillator while the source also can be congigured as 4MHz frequency dividing output from ADDA oscillator The outputs are seperately controlled by register CK32K OUT CTRLx x 1 2 3 The first output CKO1_RTC is push pull pin connected with AP the CKO2 and outputs are open drain pins for other components such as baseband or wifi module The general purpose registers eOh efh are used for storing data since the RTC domain is always power on The block diagram is as below 32 768kHz OSC32KOUT OSC32KIN CLK32KAP CLK32KBB 52 CLK32KMD ALM_INT VIO_RTC VCC_RTC Figure 45 RTC Block Dia 12
82. on zero hysteresis value should be chosen The hysteresis feature can also be disabled Debounce time noise and signal determines the hysteresis in time domain for noise detection The AGC continuously calculates the energy of the recorded signal If the calculated energy is less than the set noise threshold then the AGC does not increase the input gain to achieve the target level However to handle audible artifacts which can occur when the energy of the input signal is close to the noise threshold the AGC checks if the energy of the recorded signal is less than the noise threshold for a time greater than the noise debounce time Similarly the AGC starts increasing the input signal gain to reach the target level when the calculated energy of the input signal is greater than the noise threshold Again to avoid audible artifacts when the input signal energy is close to noise threshold the energy of the input signal must continuously exceed the noise threshold value for the signal debounce time If the debounce times are kept small then audible artifacts can result by rapid enabling and disabling the AGC function At the same time if the debounce time is kept too large then the AGC may take time to respond to changes in levels of input signal swith respect to the noise threshold Both noise and signal debouncet ime can be disabled The AGC Output Information noise threshold flag is a read only flag indicating that the input
83. output mixer or left right output mixer The SPORP N input source can be selected from right output mixer or left right output mixer So mono speaker application The best choice for SPOLP N or SPORP N input source is selected from leftt right output mixer avoiding sound loss The volume control is logarithmicwith an 43 5dB rang in 1 5dB step from 43 5dB to OdB The left and right speaker output buffer can independently power up or down by register CTRL Bit11 amp Bit7 set 11 10 4 Line Output LINEOUTP N provides one differential BTL output to drive line level signals to external audio equipment or baseband module The LINEOUTP N input source can be selected from MICI pre amplifier output MIC2 pre amplifier output left output mixer or right output mixer The volume control is logarithmic with an 10 5dB rang in 1 5dB step from 4 5dB to 6dB The LINEOUT output buffer power up or down by register CTRL Bit4 set 11 11 Digital Microphone Interface 100 supports a stereo digital micriphone interface The DMICCLK DMICDAT pins are multiplexed on the MIC3P MIC3N pins The circuit share decimation filter with audio ADC And DMICCLK can be output 128fs fs ADC sample rate Digital Microphone power usually falls between the range 1 6V 3 6V typical 1 8V And the Clock frequency is between the the range 1 0MHz 3 25MHz typical 2 4MHz Digital Microphone Block Diagram as below ADC 2b 5b
84. r The inputs are suited to receiving line level signals such as external audio equipment or baseband module When the linein input is set as differential signal input LINEINL LININR to the ADC or to DAC mixer the linein gain is logarithmically adjustable from 9dB to 12dB in 1 5dB step by the register LINEIN DIFF PREG set 11 10 Analogue Audio Output Path The Codec supports five Analogue Audio Output paths HPOUTL R HPOUTFB SPOLP N SPORP N EAROUTP N LINEOUTP N 11 10 1 Headphone Output HPOUTLIR provides two channel single ended output to headphone driver The HPOUTL R PA input source can be selected from output mixer or directly from DAC by register HPOUT CTRL Bit15 amp Bitl4 set It also can be muted by register HPOUT CTRL Bit13 amp Bit12 set The headphone PA power up or down by register HPOUT Bit11 set HPOUTL R can drive a 16R or 32R headphone load without DC capacitors by using Charge Pump to generate the negative rails HPOUTFB is the ground loop noise rejection feedback HBIAS provides reference voltage for electret condenser type ECM microphones Audio jack insert button press detection function is also provided through measuring the HBIAS current HPOUTL HPOUTR Figure 27 Suggested Headphone Output Application HPOUTL R volumes can be independently adjusted under software control using the HP VOL 5 0 of the headphone output control registers The adjus
85. rage filter coefficient setting the 10 0 R W 0x0100 coefficient reg a3 10 0 reg a4 is 3 24 format 2s complement Reg a4dh DAC DAP Left Low Energy Average Coef Register Default 0x0000 Register Name AC DAC DAPLLAVC Bit Read Write Default Description Left channel energy average filter coefficient setting the 15 0 R W 0 0000 coefficient rega3 10 0 ega4 is 3 24 format 2s complement Reg 5 DAC DAP Right High Energy Average Coef Register Default 0x0100 Register Name AC DAC DAPRHAVC Bit Read Write Default Description 15 11 Right channel energy average filter coefficient setting the 10 0 R W 0x0100 coefficient reg 5 10 0 reg is 3 24 format 2s complement Reg a6h DAC DAP Right Low Energy Average Coef Register Default 0x0000 Register Name AC DAC DAPRLAVC Bit Read Write 15 0 R W Default 0x0000 Description Right channel energy average filter coefficient setting the coefficient reg a5 10 0 reg is 3 24 format 2s complement Reg a7h_DAC DAP High Gain Decay Time Coef Register Default 0x0100 Register Name AC_DAC_DAPHGDEC Bit Read Write Default Description 15 11 Gain smooth filter decay time coefficient setting the 10 0 R W 0x0100 coefficient reg a7 10 0 reg a8 is 3 24 format 2s complement Reg a8h_DAC DAP Low Gain Decay Time Coef Register
86. rnal amplifier to drive the loud speaker It can also be configured as single ended output pin for some application of external single ended amplifier The flexible analogue and digital mixers form a varied signal routing to support a complicated application 100 is controlled through TWI 2 wire serial interface or RSB reduced serial bus It works only in the slave mode The integrated DRC Dynamic Range Controller function in 100 provide an useful digital sound processing capability in DAC playback path to speaker It is uesed to attenuate the peak signals and boost the low level signals by adjusting the output signal gain in some conditions The DRC functions can be enable or disable in the playback path The integrated AGC Automatic Gain Controller function can be used to maintain a constant recording level in ADC record path The DRC can make an improvement in background noise by setting a programmable Noise Gate to attenuate very low level input signals Note D The RSB is independent R amp D by x powers supports a special protocols with a simplified two wire protocol on a push pull bus The transfer speed in 100 can be up to 10 2 2 Features The AC100 features 2 ADCs and 2 DACs 24 bit and inter PLL processing with flexible clocking scheme Up to 100dB SNR during DAC playback path A weight Up to 95dB SNR during ADC record path A weight Capless stereo headphone driver Inte
87. s the 7 8 or 15 bit in front of the parity bit Figure 11 Parity bit bit is the acknowledgement from device to host The is active low When device finds the parity bit is error it will not send ACK to host so host can know that an error happens in the transaction Set run time slave address RTSADDR command It is used to set run time slave address RTSADDR for different devices in the same system There are 15 devices in a system at most The RTSADDR can be selected from the command code set and a device s RTSADDR can be modified many times by using set run time slave address command 1 7 1 15 1 7 2 1 2 HOST 1 0x74 SADDR RTSADDR c BH Device Figure 12 RTSADDR command Read command is used to read data from device It has byte half word and word operation When devices receives the command they shall check if the command s RTSADDR matches their own RTSADDR The device s RTSADDR is setted by set run time slave address RTSADDR command 1 7 1 7 1 8 1 2 8 1 8 i 2 Host 0x45 0x4E 0x53 RTSADDR DADDR DATAO c DATAn c Device e 1 21 24 Figure 13 Read command Write command is used to write data to the devices It has byte half word and word operation When devices receive the command they shall check if the command s RTSADDR matches
88. ss filter is used to help determine the average level of the input signal This average level is compared to the programmed detection levels in the AGC to provide the correct functionality This low pass filter is in the form of a first order IIR filter The transfer function of the filter implemented for signal level detection is given by a Pe ye Where Coefficient 3 24 format 15 26 bit 2s complement and will determine the time window over which average level to be made The parameter is computed by a Qm Default time window is 108 8963 Ts The AGC Characteristics x n 50 p gt y n x n g n Aca m yl Zz Ga yor T gt E n 0 Alpha filter 054 4 pq _ 0 5db 4 gt x 0db 4 Figure38 Module Characteristic 11 15 Digital Audio Process for DAC The DAP System Block Diagram For DAC Dap sell 0x60131 DAP and System Fuction View Figure 39 DAC DAP System Block DAP for DAC Data Flow 0 0 1 Alphba filer Alphba filer 0 2 0 0 Figure 40 DAC DAP Data Flow 11 15 1 High Pass Filter The DAP has individual channel high pass filter that can be enabled and disabled The filter cutoff frequency is less than 1Hz Dez I H z l az 11 15 2 Dynamic Range Control The dynamic range control DRC can be enabled in the digita
89. tion process The AGC Control Parameters Target level represents the nominal output level at which attempts to hold the ADC output signal level The ADC allows programming of different target levels which can be programmed from 1dB to 30dB relative to a full scale signal Because the ADC reacts to the signal absolute average and not to peak levels it is recommended that the target level be set with enough margins to avoid clipping at the occurrence of loud sounds Attack skew time determine show quickly the AGC circuitry reduces the PGA gain when the output signal level exceeds the target level due to increase in input signal level A wide range of attack time programmability is supported in terms of number of samples 1 number of ADC sample frequency clock cycles Decay skew time determine show quickly the PGA gain is increased when the output signal level falls below the target level due to reduction in input signal level A wide range of decay time programmability is supported in terms of number of samples i e number of ADC sample frequency clock cycles Noise threshold is a reference level If the input speech average value falls below the noise threshold the AGC considers it as asilence and hence brings down the gain to OdB in steps of 0 5dB every sample period and sets the noise threshold flag The gain stay sat OdB unless the input speech signal average is es above the noise threshold setting Th
90. tment is logarithmic with 64dB rang in 1dB step from OdB to 62dB The headphone outputs can be muted by writing codes 0x0 to HP VOL 5 0 bits There are a DC offset cancellation circuit to remove the headphone output DC offset for preventing POP noise in 100 The function can be enabled or disabled by the register HP DCRM EN This bit must be set Oxf before headphone PA enabled and this bit must be set 0x0 before headphone PA disabled A zero cross detect circuit is provided at the input to the headphones under the control of the ZCROSS EN bit Using these controls the volume control values are only updated when the input signal to the gain stage is close to the analogue ground level This minimizes and audible clicks and zipper noise as the gain values are changed or the device muted 11 10 2 Earpiece Output EAROUTP N provides one differential output to drive handset receiver The EAROUTP N input source can be selected from left DAC right DAC left output mixer or right output mixer The earpiece volume controlled by the register ERPOUT_CTRL Bit4 0 set The volume control is logarithmic with an 43 5dB rang in 1 5dB step from 43 5dB to OdB The earpiece power up or down by register ERPOUT CTRL Bit5set 11 10 3 Speaker Output SPOLP N SPORP N provides two differential output without internal speaker amplifier Using external amplifier a stereo speakers can be implemented The SPOLP N input source can be selected from left
91. vide reference voltage for electret condenser type ECM microphones MICBIAS MICXP 1 MICXN Figure 4 Suggested External Microphone Input Drawing Figure 25 Suggested External Microphone Input 11 9 2 AXIL R Input Auxiliary inputs AXIL and AXIR provide 2 channel stereo single ended input that can be mixed into the DAC output mixer and ADC record mixer The inputs are high impedance and low capacitance thus ideally suited to receiving line level signals from external audio equipment or audio FM module Both auxiliary inputs include programmable volume level adjustments and ADC input mute The scheme is illustrated below Passive RF and active Anti Alias filters are also incorporated within the auxiliary inputs These prevent high frequencies aliasing into the audio band otherwise degrading performance The gain between the AXI inputs and the ADC is logarithmically adjustable from 9dB to 12dB in 1 5dB step by the register AXI PREG set The ADC Full Scale input is 1 0Vrms at AVCC 3 0volts Any voltage greater than full scale will possibly overload the ADC and cause distortion Note that the full scale input tracks directly with AVCC Figure 2 AXI input Schematic Figure 26 AXI Input Schematic 11 9 3 LINEINL R Input LINEINL R provide one channel mono differential input or stereo single ended input that can be mixed into the ADC record mixer or the stereo output mixe
92. y Filter Structure Compression Control This element has three parameters T K O which are all programmable and the computation will be explained as below T parameter Threshold Parameter Computation The threshold is the value that determines the signal to be compressed or not When the signal s RMS is larger than the threshold the signal will be compressed The value of threshold input to the coefficient register is computed by it 6 0206 There T must less than zero the positive value is illegal For example it desired to set the T 30dB then 30 4 982 and the 8 24 format of the is 6 0206 0x04FB_9EDO K parameter Slope Parameter Computation The is the slope within compression region For example a n 1 compression means that an output increase 1dB as RMS input increase n dB The k input to the coefficient register is computed by There n is from 1 to 50 and must be integer 1 For example for n 5 the k 5 0 8 and the 3 24 format of the k is 0x733_ 3333 O parameter Offset Parameter Computation The is the offset of the compression static curve The offset input to the coefficient register is computed by 10 There is 24dB to 244 For example it desired to set O 6dB then 1097 1 995 and the 5 24 format of the O is Ox1FE C982 Gain Smooth Filter The Gain Smooth Filter is t

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