"user manual"
Contents
1. 1 2 gc M A Dimension b is measured at the 1 maximum solder ball diameter K parallel to datum plane 2 7 Datum 2 seating plane is defined by the spherical crowns of the solder balls Parallelism measurement shall exclude any effect of mark on top surface of package Millimeters DIM Min Max A 1 25 1 60 1 0 27 0 47 2 1 16 M b 0 45 0 55 D 15 00 BSC E 15 00 BSC Metalized mark for e 1 00 BSC pin 1 identification in this area 5 0 50 BSC A 4646 OOOO OOO 9 9 p AA 9 9 6 E 7 0 2012 9 9 9 9 9 T J Al C3 0 10 Z 9 0 0 0 z A 9 9 9 1 Detail 0 0 6 Rotated 90 Clockwise 9 9 N 9 9 P 196 2 b e 015 ZIX Y View M M 20 08 2 Figure 4 196 MAPBGA Package Dimensions Case No 1128A 01 MCF5271 Integrated Microprocessor Hardware Specification Rev 4 14 Freescale Semiconductor Mechanicals Pinouts and Part Numbers 6 3 Pinout 160 Figure 5 shows a pinout of MCF5271CABxxx package m 9 2 555 28 BERR 8 SEBESRBESERRERBERISTBEEERIS2 IBRERI22238327 gt gt gt gt gt lt lt lt lt lt2. 0 3 Single Pin Limit 1 0 1 0 mA Total processor Limit Includes sum of all stressed pins 10 10 mA Refer to Table 10 for additional PLL specifications Refer to the MCF5271 signals section for pins having weak internal pull up devices This parameter is characterized before qualification rather than 100 tested pF load ratings are based on DC loading and are provided as an indication of driver strength High speed interfaces require transmission line analysis to determine proper drive strength and termination See High Speed Signal Propagation Advanced Black Magic by Howard W Johnson for design guidelines Current measured at maximum system clock frequency all modules active and default drive strength with matching load All functional non supply pins are internally clamped to Vss and their respective Vpp Input must be current limited to the value specified To determine the value of the required current limiting resistor calculate resistance values for positive and negative clamp voltages then use the larger of the two values Power supply must maintain regulation within operating Vpp range during instantaneous and operating maximum current conditions If positive injection current Vi gt Vpp is greater than Ipp the injection current may flow out of Vpp and could result in external power supply going out of regulation Insure external Vpp load will shunt current greater than maximum injection current This will be the greates
3. 2 4 V to 0 5 V 1 ms 16 Clock high time 4 I7 Data setup time 0 ns IB Start condition setup time for repeated start condition only 2 19 Stop condition setup time 2 Table 17 lists specifications for the Pc output timing parameters shown in Figure 15 Table 17 Output Timing Specifications between I2C_SCL I2C_SDA Num Characteristic Min Max Units Start condition hold time 6 tcyc 121 Clock low period 10 teye I3 12C_SCL I2C_SDA rise time 0 5 V to 2 4 V us I4 Data hold time 7 teye 53 12C_SCL 2C_SDA fall time 2 4 V to Vi 0 5 V 3 ns 61 Clock high time 10 Lye I7 Data setup time 2 teye IB Start condition setup time for repeated start condition only 20 91 Stop condition setup time 10 1 Note Output numbers depend on the value programmed into the IFDR an IFDR programmed with the maximum frequency IFDR 0x20 results in minimum output timings as shown in Table 17 The interface is designed to scale the actual data transition time to move it to the middle of the 2 SCL low period The actual position is affected by the prescale and division values programmed into the IFDR however the numbers given in Table 17 are minimum values 2 Because 2 SCL I2C_SDA are open collector type outputs which the processor can only
4. The below table lists thermal resistance values Table 8 Thermal Characteristics Characteristic Symbol M 160QFP Unit Junction to ambient natural convection Four layer board 2s2p 3212 4012 Junction to ambient 200 ft min Four layer board 252 2912 3612 C W Junction to board 203 253 C W Junction to case 104 10 C W Junction to top of package Y 215 215 C W Maximum operating junction temperature Tj 104 105 j parameters are simulated in conformance with EIA JESD Standard 51 2 for natural convection Motorola recommends the use of and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices Conformance to the device junction temperature specification can be verified by physical measurement in the customer s system using the parameter the device power dissipation and the method described EIA JESD Standard 51 2 Per JEDEC JESD51 6 with the board horizontal Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51 8 Board temperature is measured on the top surface of the board near the package Thermal resistance between the die and the ca
5. actively drive low the time 12 SCL 2 SDA take to reach a high level depends on external signal capacitance and pull up resistor values Specified at a nominal 50 pF load Figure 15 shows timing for the values in Table 16 and Table 17 MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 31 Electrical Characteristics 2 SCL oH br i I2C_SDA d X Figure 15 12 Input Output Timings 7 10 Fast Ethernet AC Timing Specifications MII signals use TTL signal levels compatible with devices operating at either 5 0 V or 3 3 V 7 10 1 MII Receive Signal Timing ERXD 3 0 ERXDV ERXER and ERXCLK The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz 1 The processor clock frequency must exceed twice the ERXCLK frequency Table 18 lists MII receive channel timings Table 18 MII Receive Signal Timing Num Characteristic Min Max Unit M1 ERXD 3 0 ERXDV ERXER to ERXCLK setup 5 ns M2 ERXCLK to ERXD 3 0 ERXDV ERXER hold 5 ns M3 ERXCLK pulse width high 3596 6596 ERXCLK period M4 ERXCLK pulse width low 35 65 ERXCLK period Figure 16 shows MII receive signal timings listed in Table 18 0 ERXCLK input ERXD 3 0 ee 552 X 552 ERXER Figure 16 Receive Signal Timing Diagram MCF5271 Integrated Microprocessor Hardware
6. 11 12 23 0 X Row Y Column a 1 9 1 SDSRAS 1 Z N SD SCAS oom D 31 0 TM 08 lt RAS 1 0 m c CAS x ACTV NOP WRITE NOP PALL DACR CASL 2 Figure 12 SDRAM Write Cycle 7 7 General Purpose I O Timing Table 14 GPIO Timing NUM Characteristic Symbol Min Max Unit G1 CLKOUT High to GPIO Output Valid tcHPov 10 ns G2 CLKOUT High to GPIO Output Invalid tcHPOI 1 5 ns G3 _ GPIO Input Valid to CLKOUT High tPvcH 9 ns G4 CLKOUT High to GPIO Input Invalid 1 5 ns 1 GPIO pins include INT UART Timer DREQn and DACKn pins MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 29 Electrical Characteristics CLKOUT VSN GPIO Outputs 63 G SE Figure 13 GPIO Timing 7 8 Reset and Configuration Override Timing Table 15 Reset and Configuration Override Timing 2 7 to 3 6 V Vss 0 V T Tt to Tr NUM Characteristic Symbol Min Max Unit R1 RESET Input valid to CLKOUT High 9 ns R2 CLKOUT High to RESET Input invalid tcHRI 1 5 ns R3 RESET Input valid Time 2 taivt 5 High to RSTOUT Valid 10 ns R5 RSTOUT valid to Config Overrides vali
7. 5 TDI Input Data Hold Time after TCLK Rise tTAPBHT 10 ns 411 TCLK Low to Data Valid ttpopv 0 26 ns J12 TCLK Low to TDO High Z trpopz 0 8 ns J13 TRST Assert Time tTRSTAT 100 ns J14 TRST Setup Time Negation to TCLK High trRSTST 10 ns JTAG EN is expected to be a static signal Hence specific timing is not associated with it ae TCLK input Figure 21 Test Clock Input Timing MCF5271 Integrated Microprocessor Hardware Specification Rev 4 36 Freescale Semiconductor Electrical Characteristics TCLK j Vis Q9 Data Inputs Data Outputs Input Data Valid Output Data Valid pe uu Data Outputs E T lt 7 gt Data Outputs TCLK if Output Data Valid Figure 22 Boundary Scan JTAG Timing TDI f 69 TMS Input Data Valid lt Output Data Valid TDO TDO gt if Output Data Valid TCLK Figure 23 Test Access Port Timing TRST Figure 24 TRST Timing MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 37 Electrical Characteristics 7 14 Debug AC Timing Specifications Table 25 lists specificati
8. P11 L10 MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor Design Recommendations 5 5 1 5 2 Table 2 MCF5270 and MCF5271 Signal Information and Muxing continued MCF5270 MCF5270 Signal Name GPIO Alternate 1 Alternate 2 Dir MCF5271 MCF5271 160 QFP 196 MAPBGA Test TEST 19 5 PLL_TEST Power Supplies VDDPLL 87 M13 VSSPLL 84 114 OVDD 1 18 32 41 55 5 E7 E10 F7 69 81 94 105 F9 G6 G8 H7 114 128 138 H8 H9 46 J8 145 J10 K5 K6 K8 VSS 17 31 40 54 1 A14 6 9 67 80 88 93 6 F8 F10 G7 104 113 127 G9 H6 J5 J7 137 144 160 J9 K7 P1 P14 VDD 16 53 103 D6 F11 G4 14 1 Refers to pin s primary function All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception of PBUSCTL 7 PBUSCTL 4 0 PADDR PBS PSDRAM 2 f JTAG is asserted these pins default to Alternate 1 JTAG functionality The GPIO module is not responsible for assigning these pins Design Recommendations Layout Use a 4 layer printed circuit board with the VDD and GND pins connected directly to the power and ground planes for the MCF5271 See application note AN1259 System Design and Layout Techniques for Noise Reduction in
9. Processor Based Systems Match the PC layout trace width and routing to match trace length to operating frequency and board impedance Add termination series or therein to the traces to dampen reflections Increase the PCB impedance if possible keeping the trace lengths balanced and short Then do cross talk analysis to separate traces with significant parallelism or are otherwise noisy Use 6 mils trace and separation Clocks get extra separation and more precise balancing Power Supply 33 uF 0 1 uF and 0 01 uF across each power supply MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor Design Recommendations 5 2 1 Supply Voltage Sequencing and Separation Cautions Figure 2 shows situations in sequencing the I O OVpp PLL Vpp and Core Vpp OV pp is specified relative to V pp 3 3V OVpp VpppLL Supplies Stable 2 5V 1 5V 4 Vpp DC Power Supply Voltage Time Notes 1 VDD should not exceed OVDD or VDDPLL by more than 0 4 V at any time including power up 2 Recommended that VDD should track OVDD VDDPLL up to 0 9 V then separate for completion of ramps 3 Input voltage must not be greater than the supply voltage OVDD VDD or VDDPLL by more than 0 5 V at any time including during power up 4 Use 1 ms or slower rise time for all supplies Figure 2 Supply Voltage Sequencing and Separation Cautions 5 2 1
10. 31 0 high impedance tcupoz 9 ns 1 5 transitions after the falling edge of i BS transitions after the falling edge of CLKOUT 3 transitions after the falling edge of CLKOUT MCF5271 Integrated Microprocessor Hardware Specification Rev 4 24 Freescale Semiconductor Electrical Characteristics Read write bus timings listed in Table 12 are shown in Figure 8 Figure 9 and Figure 10 50 Sl 52 53 54 S5 SO 51 52 53 54 55 CLKOUT gt lt gt CSn 23 0 69 lt o gt E 88 gt 69 gt lt gt X 6 gt B8 gt BS 3 0 D 31 0 Figure 8 Read Write Internally Terminated SRAM Bus Timing MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 25 Electrical Characteristics Figure 9 shows a bus cycle terminated by TA showing timings listed in Table 12 A 23 0 TSIZ 1 0 TIP BS 3 0 D 31 0 50 51 52 53 54 55 50 51 Figure 9 SRAM Read Bus Cycle Terminated by MCF5271 Integrated Microprocessor Hardware Specification Rev 4 26 Freescale Semiconductor Electrical Characteristics Figure 10 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 12 50 S1 52 S3 54 55 50 S1 A 23 0 TSIZ 1 0 TS TIP BS 3 0 D 31 0 lt Figure 1
11. Specification Rev 4 32 Freescale Semiconductor 7 10 2 Transmit Signal Timing ETXD 3 0 ETXEN ETXCLK Table 19 lists MII transmit channel timings Electrical Characteristics The transmitter functions correctly up to a ETXCLK maximum frequency of 25 MHz 1 The processor clock frequency must exceed twice the ETXCLK frequency Table 19 MII Transmit Signal Timing Num Characteristic Min Max Unit M5 ETXCLK to ETXD 3 0 ETXEN ETXER invalid 5 ns M6 ETXCLK to ETXD 3 0 ETXEN ETXER valid 25 ns M7 ETXCLK pulse width high 35 65 ETXCLK period M8 ETXCLK pulse width low 35 65 ETXCLK period Figure 17 shows MII transmit signal timings listed in Table 19 ETXCLK input lt gt ETXD 3 0 outputs NC ETXEN ETXER Figure 17 MII Transmit Signal Timing Diagram 7 10 3 Async Inputs Signal Timing ECRS and ECOL Table 20 lists MII asynchronous inputs signal timing Table 20 MII Async Inputs Signal Timing Num Characteristic Min Max Unit M9 ECRS ECOL minimum pulse width 1 5 ETXCLK period Figure 18 shows MII asynchronous input timings listed in Table 20 ECRS ECOL Figure 18 Inputs Timing Diagram MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 33 Electrical Characteristics 7 10 4 Serial Management Channe
12. o gt lt Inputs Figure 7 General Input Timing Requirements 7 6 Processor Bus Output Timing Specifications Table 12 lists processor bus output timings Table 12 External Bus Output Timing Specifications Name Characteristic Symbol Min Max Unit Conirol Outputs CLKOUT high to chip selects valid 1 0 5 5 ns B6b CLKOUT high to byte enables BS 3 0 valid tcHBV 0 5 9 ns CLKOUT high to output enable OE valid tcHov 0 5 5 ns B7 CLKOUT high to control output BS 3 0 OE invalid 0 5 1 5 5 7 CLKOUT high to chip selects invalid 0 5 1 5 5 MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 23 Electrical Characteristics Table 12 External Bus Output Timing Specifications continued Name Characteristic Symbol Min Max Unit Address and Attribute Outputs B8 CLKOUT high to address A 23 0 and control TS 9 ns TSIZ 1 0 TIP RAN valid B9 CLKOUT high to address A 23 0 and control TS 1 5 ns TSIZ 1 0 TIP R W invalid Data Outputs B11 CLKOUT high to data output D 31 0 valid tcupov 9 ns B12 CLKOUT high to data output D 31 0 invalid 1 5 ns B13 CLKOUT high to data output D
13. reference for the PLL then the crystal start up time must be added to the PLL lock time to determine the total start up time 9 tip 64 4 5 5 where Tret 1 Fret crystal 1 Fret_ext 1 1 1 and 1 57 10 6 2 MFD 2 PLL is operating in 1 1 PLL mode is the average deviation from the programmed frequency measured over the specified interval at maximum Isys 2 Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal Noise injected into the PLL circuitry and Vsssyn and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval 1 Values are with frequency modulation disabled If frequency modulation is enabled jitter is the sum of Cjitter Cmod 13 Modulation percentage applies over an interval of 10us or equivalently the modulation rate is 100 2 14 Modulation rate selected must not result in 2 Value greater than the maximum specified value Modulation range determined by hardware design fysi2 fico 2 2 10 11 MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 21 Electrical Characteristics 7 5 External Interface Timing Characteristics Table 11 lists processor bus input timings NOTE All processor bus timings are synchronous that is input setup hold and output delay with respect to the rising edge o
14. 0 SRAM Read Bus Cycle Terminated by TEA MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 27 Electrical Characteristics Figure 11 shows an SDRAM read cycle 1 2 4 5 7 9 10 12 13 14 15 23 0 X Row Columh Ax SD_SRAS a SD CAS a a 22 lt lt 1 D 31 0 a RAS 1 0 CASO Pa READ NOP NOP PALL 1 DACR CASL 2 Figure 11 SDRAM Read Cycle Table 13 SDRAM Timing NUM Characteristic Symbol Min Max Unit 01 CLKOUT high to SDRAM address valid lcHDAV 9 ns D2 CLKOUT high to SDRAM control valid tcupcv 9 ns D3 CLKOUT high to SDRAM address invalid 1 5 ns D4 CLKOUT high to SDRAM control invalid 1 5 5 05 SDRAM data valid to CLKOUT high tppvcH 4 ns 06 CLKOUT high to SDRAM data invalid 1 5 5 07 CLKOUT high to SDRAM data valid tcHDDvw 9 ns D8 CLKOUT high to SDRAM data invalid tcHDDIW 1 5 ns D7 and D8 are for write cycles only MCF5271 Integrated Microprocessor Hardware Specification Rev 4 28 Freescale Semiconductor Electrical Characteristics Figure 12 shows an SDRAM write cycle 11213 4 5 7 10
15. 1 Power Up Sequence If OVpp 1 powered up with Vpp at 0 V then the sense circuits in I O pads cause all pad output drivers connected to the OVpp to be in a high impedance state There is no limit on how long after OVpp powers up before must power up Vpp should not lead the OVpp by more than 0 4 V during power ramp up or there will be high current in the internal ESD protection diodes The rise times on the power supplies should be slower than 1 us to avoid turning on the internal ESD protection clamp diodes The recommended power up sequence is as follows 1 Use 1 ms or slower rise time for all supplies 2 Vpp and OVpp V pppu should track up to 0 9 V then separate for the completion of ramps with OV pp going to the higher external voltages One way to accomplish this is to use a low drop out voltage regulator 5 2 1 2 Power Down Sequence If Vpp is powered down first then sense circuits in the I O pads cause all output drivers to be in a high impedance state There is no limit on how long after powers down before OV pp V ppp must power down V pp should not lag OVpp or going low by more than 0 4 V during power down or there MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 9 Design Recommendations will be undesired high current in the ESD protection diodes There are no requirements for the fall times of the power supplies The r
16. 20 1 236 DATUM PLANE H DIMENSIONS 8 AND V TO BE DETERMINED AT SEATING PLANE C DIMENSIONS AND DO NOT INCLUDE MOLD 013 0005 PROTRUSION ALLOWABLE PROTRUSION IS 0 25 0 ATE 0 110 0 004 0 010 PER SIDE DIMENSIONS A AND B DO 31 00 31 40 1 220 1 236 INCLUDE MOLD MISMATCH AND ARE DETERMINED 04 ome 1 60 REF 0 063 REF 1 33 REF 0 052 REF 1 33 REF 0 052 REF AT DATUM PLANE H DETAIL C 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 08 0 003 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT Case 864A 03 Figure 6 160 QFP Package Dimensions N xIx ci2 o orv zizr e ropmmjojo m MCF5271 Integrated Microprocessor Hardware Specification Rev 4 16 Freescale Semiconductor Electrical Characteristics 6 5 Ordering Information Table 6 Orderable Part Numbers Description Package Speed Lead Free Temperature MCF5270AB100 MCF5270 RISC Microprocessor 160 QFP 100MHz Yes 0 to 70 C MCF5270CAB100 MCF5270 RISC Microprocessor 160 QFP 100MHz Yes 40 to 85 C MCF5270VM100 MCF5270 RISC Microprocessor 196 MAPBGA 100 2 Yes 0 to 70 C MCF5270CVM150 MCF5270 RISC Microprocessor 196 MAPBGA 150MHz Yes 40 to 85 C MCF5271
17. 271RM 4 Signal Descriptions This section describes signals that connect off chip including a table of signal properties For a more detailed discussion of the MCF5271 signals consult MCF5271 Reference Manual 5271 4 1 Table 4 lists all of the signals grouped by function The Dir column is the direction for the primary function of the pin Refer to Section 6 Mechanicals Pinouts and Part Numbers for package diagrams NOTE In this table and throughout this document a single signal within a group is designated without square brackets i e A24 while designations for multiple signals within a group use brackets 1 A 23 21 and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon Signal Properties NOTE The primary functionality of a pin is not necessarily its default functionality Pins that are muxed with GPIO will default to their GPIO functionality Table 2 MCF5270 and MCF5271 Signal Information and Muxing MCF5270 MCF5270 Signal Name GPIO Alternate 1 Alternate 2 Dir MCF5271 MCF5271 160 QFP 196 MAPBGA Reset RESET 83 N13 RSTOUT 82 P13 Clock EXTAL 86 M14 XTAL 85 N14 CLKOUT 89 K14 Mode Selection CLKMODf 1 0 EE 20 21 G5 H5 RCON 79 K10 External Memory Interface and Ports A 23 21 PADD
18. CAB100 MCF5271 RISC Microprocessor 160 QFP 100MHz Yes 40 to 85 C MCF5271CVM100 MCF5271 RISC Microprocessor 196 MAPBGA 100 2 Yes 40 to 85 C MCF5271CVM150 MCF5271 RISC Microprocessor 196 MAPBGA 150MHz Yes 40 to 85 C 7 Electrical Characteristics This chapter contains electrical specification tables and reference timing diagrams for the MCF5271 microcontroller unit This section contains detailed information on power considerations DC AC electrical characteristics and AC timing specifications of MCF5271 NOTE The parameters specified in this processor document supersede any values found in the module specifications 7 1 Maximum Ratings Table 7 Absolute Maximum Ratings 2 Rating Symbol Value Unit Core Supply Voltage Vpp 0 5 to 2 0 V Pad Supply Voltage OVpp 0 3 to 4 0 V PLL Supply Voltage VppPLL 0 8 to 44 0 V Digital Input Voltage i VIN 0 3 to 4 0 V Instantaneous Maximum Current Ip 25 mA Single pin limit applies to all pins 342 Operating Temperature Range Packaged TA 40 to 85 TL Ty Storage Temperature Range 6510 150 1 Functional operating conditions are given DC Electrical Specifications Absolute Maximum Ratings are stress ratings only and functional operation at the maxima is not guaranteed Continued operation at these levels may affect device reliability or cause permanent damage to the de
19. Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Number MCF5271EC Rev 4 08 2009 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer applicati
20. F5270CVM150 and MCF5271CVM150 Removed features list This information can be found in the MCF5271RM Removed SDRAM address multiplexing section This information can be found in the MCF5271RM 1 4 Added Section 5 2 1 Supply Voltage Sequencing and Separation Cautions Updated 196MAPBGA package dimensions Figure 4 2 Table 2 Changed SD CKE pin location from 139 to for the 160QFP device Table 2 Changed QSPI_CS1 pin location from to 139 for the 160QFP device Table 2 Changed pin s alternate 2 function from to QSPI CS2 Table 2 Changed DT3OUT pin s alternate 2 function from to QSPI CS3 Figure 5 Changed pin 139 label from SD CKE QSPI CS1 to QSPI CS1 SD Removed second sentence from Section 7 10 1 MII Receive Signal Timing ERXD S3 0 ERXDV ERXER and and Section 7 10 2 Transmit Signal Timing ETXD 3 0 ETXEN ETXER regarding no minimum frequency requirement for TXCLK Removed third and fourth paragraphs from Section 7 10 2 MII Transmit Signal Timing ETXD 3 0 ETXEN ETXER as this feature is not supported on this device 3 Section 5 2 1 Supply Voltage Sequencing and Separation Cautions changed PLLVpp to Vpppi to match rest of document Section 5 2 1 Supply Voltage Sequencing and Separation Cautions Changed Vpppi voltage level from 1 5V to 3 3V throughout secti
21. Freescale Semiconductor Document Number MCF5271EC Data Sheet Technical Data Rev 4 08 2009 VRoHS MCF5271 Integrated Microprocessor Hardware Specification by Microcontroller Solutions Group The MCF5271 family is a highly integrated Contents implementation of the ColdFire family of reduced 1 MCF5271 Family Configurations 2 instruction set computing RISC microprocessors This document describes pertinent features and functions of MCF5271 family The MCF5271 family includes the 5 Design Recommendations 8 MCF5271 and 5270 microprocessors The 7 Characters differences between these parts are summarized below in 8 Documentation 39 Table 1 This document is written from the perspective of 9 Document Revision m the MCF5271 and unless otherwise noted the information applies also to the MCF5270 The MCF5271 family combines low cost with high integration on the popular version 2 ColdFire core with over 144 Dhrystone 2 1 MIPS at 150 MHz Positioned for applications requiring a cost sensitive 32 bit solution the MCF5271 family features a 10 100 Ethernet MAC and optional hardware encryption to ensure the application can be connected and protected In addition the MCF5271 family features an enhanced multiply accumulate unit MAC large on chip memory 64 Kbytes SRAM 8 Kb
22. Literature Distribution Center or through the Freescale web address at http www freescale com coldfire 9 Document Revision History The below table provides a revision history for this document Table 26 MCF5271EC Revision History Rev No Substantive Change s 0 Initial release Fixed several clock values Updated Signal List table e Removed duplicate information in the module description sections The information is all in the Signals Description Table E Removed detailed signal description section This information be found in the MCF5271RM Chapter 2 Removed detailed feature list This information can be found in the MCF5271RM Chapter 1 Changed instances of Motorola to Freescale Added values for Maximum operating junction temperature in Table 8 Added typical values for Core operating supply current master mode in Table 9 Added typical values for Pad operating supply current master mode in Table 9 Removed unnecessary PLL specifications 6 9 in Table 10 e e MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 39 Document Revision History Table 26 MCF5271EC Revision History continued Rev No Substantive Change s 1 3 Device is now available in 150 MHz versions Updated specs where necessary to reflect this improvement Added 2 new part numbers to Table 6 MC
23. OUT tskew 1 1 ns and EXTAL 10 10 Duty Cycle of reference 5 tac 40 60 11 Frequency un LOCK Range fuL 3 8 4 1 sys 2 12 Frequency LOCK Range fL cK 1 7 2 0 fsys 2 13 CLKOUT Period Jitter 6 811 12 Ciitter Measured 5 0 sys 2 Peak to peak Jitter Clock edge to clock 01 edge Long Term Jitter Averaged over 2 ms interval 14 Frequency Modulation Range Limit 4 5220 0 8 2 2 2 fsys 2 must not be exceeded 15 ICO Frequency fico fret x 2 x MFD 2 15 fico 48 150 MHz All values given are initial design targets and subject to change All internal registers retain data at 0 Hz Loss of Reference Frequency is the reference frequency detected internally which transitions the PLL into self clocked mode Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f on with default MFD RFD settings This parameter is guaranteed by characterization before qualification rather than 100 tested Proper PC board layout procedures must be followed to achieve specifications This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register SYNCR Assuming a reference is available at power up lock time is measured from the time Vpp and Vppsyn are valid to RSTOUT negating If the crystal oscillator is being used as the
24. QSPI3 146 QSPI_CLK PQSPI2 2 SCL 147 5 QSPI_DIN PQSPI1 I2C_SDA mE 148 5 QSPI DOUT PQSPIO 149 5 MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor Signal Descriptions Table 2 MCF5270 and MCF5271 Signal Information and Muxing continued MCF5270 MCF5270 Signal Name GPIO Alternate 1 Alternate 2 Dir MCF5271 MCF5271 160 QFP 196 MAPBGA UARTs U2TXD PUARTH1 A8 U2RXD PUARTHO A7 U1CTS PUARTL7 U2CTS 136 B8 U1RTS PUARTL6 U2RTS 135 C8 U1TXD PUARTL5 133 09 U1RXD PUARTL4 134 08 UOCTS PUARTL3 12 UORTS PUARTL2 15 UOTXD PUARTL1 14 1 UORXD PUARTLO 13 2 DMA Timers DT3IN PTIMER7 U2CTS QSPI CS2 H14 DT3OUT PTIMER6 U2RTS QSPI CS3 O G14 DT2IN 5 DREQ2 DT2OUT 66 M9 DT2OUT PTIMER4 DACK2 L9 DT1IN PTIMER3 DREQI DT1OUT 61 L6 DT1OUT PTIMER2 DACK1 6 DTOIN PTIMER1 DREQO 10 4 DTOOUT PTIMERO DACKO 11 4 BDM JTAG DSCLK TRST 70 PSTCLK TCLK 68 TMS 71 10 DSI TDI 73 M10 DSO TDO 72 N10 JTAG_EN 78 K9 DDATA 3 0 M12 N12 P12 L11 PST 3 0 77 74 M11 N11
25. R 7 5 CS 6 4 126 125 124 B11 C11 D11 MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor Signal Descriptions Table 2 MCF5270 and MCF5271 Signal Information and Muxing continued MCF5270 MCF5270 Signal Name GPIO Alternate 1 Alternate 2 Dir MCF5271 MCF5271 160 QFP 196 MAPBGA A 20 0 123 115 12 B12 C12 112 106 102 98 A13 B13 B14 C13 C14 D12 D13 D14 E11 E12 E13 E14 F12 F13 F14 G11 G12 G13 0 31 16 22 30 33 39 G1 G2 H1 H2 H3 H4 J1 J2 44 K1 K2 K4 11 12 D 15 8 PDATAH 7 0 42 49 1 1 2 2 2 13 D 7 0 PDATAL 7 0 50 52 56 60 P3 M4 N4 P4 15 M5 5 5 BS 3 0 PBS 7 4 CAS 3 0 143 140 B6 C6 D7 C7 OE PBUSCTL7 62 6 PBUSCTL6 96 H11 TEA PBUSCTL5 DREQ1 J14 R W PBUSCTL4 O 95 J13 TSIZ1 PBUSCTL3 DACK1 6 TSIZO PBUSCTL2 DACKO 7 5 PBUSCTL1 DACK2 97 H13 TIP PBUSCTLO DREQO E H12 Chip Selects 5 7 4 PCS 7 4 9 10 C10 11 CS 3 2 PCS 3 2 SD CS 1 0 132 131 9 9 51 PCS1 130 10 50 129 010 SDRAM Controller SD_WE PSDRAM5 92 K13 SD_SCAS PSDRAM4 91 K12 SD_SRAS PSDRAM3 90 50 PSD
26. RAM2 E8 SD CS 1 0 PSDRAM 1 0 112 113 MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 5 Signal Descriptions Table 2 MCF5270 and MCF5271 Signal Information and Muxing continued MCF5270 MCF5270 Signal Name GPIO Alternate 1 Alternate 2 Dir MCF5271 MCF5271 160 QFP 196 MAPBGA External Interrupts Port IRQ 7 3 PIRQ 7 3 IRQ7 63 7 M7 L7 P8 IRQ4 64 N8 IRQ2 PIRQ2 DREQ2 M8 IRQ1 PIRQ1 65 L8 FEC EMDC PFECI2C3 2 SCL U2TXD 151 04 EMDIO PFECI2C2 2 SDA U2RXD y o 150 D5 ECOL 9 2 ECRS 8 1 ERXCLK EX 7 D1 ERXDV 6 02 ERXD 3 0 5 2 1 2 1 ERXER 159 2 ETXCLK 158 2 mE 157 156 ETXD 3 0 155 152 4 4 4 2 SDA PFECI2C1 yo J12 SCL PFECI2CO TX y o J11 DMA DACK 2 0 and DREQ 2 0 do not have a dedicated bond pads Please refer to the following pins for muxing TS and DT2OUT for DACK2 TSIZ1and DT1OUT for DACK1 TSIZO and DTOOUT for DACKO IRQ2 and DT2IN for DREQ2 and DT1IN for DREQ1 and and DTOIN for DREQO QSPI QSPI CS1 PQSPI4 SD_CKE 139 B7 QSPI_CSO P
27. chronous Mode Table 3 shows the behavior of SDRAM signals in synchronous mode MCF5271 Integrated Microprocessor Hardware Specification Rev 4 10 Freescale Semiconductor Design Recommendations Table 3 Synchronous DRAM Signal Connections Signal Description SD_SRAS Synchronous row address strobe Indicates a valid SDRAM row address is present and can be latched by the SDRAM SD_SRAS should be connected to the corresponding SDRAM SD SRAS Do not confuse SD SRAS with the DRAM controller s SD_CS 1 0 which should not be interfaced to the SDRAM SD_SRAS signals SD_SCAS Synchronous column address strobe Indicates a valid column address is present and can be latched by the SDRAM SD_SCAS should be connected to the corresponding signal labeled SD_SCAS on the SDRAM DRAMW DRAM read write Asserted for write operations and negated for read operations SD CS 1 0 Row address strobe Select each memory block of SDRAMs connected to the MCF5271 One SD_CS signal selects one SDRAM block and connects to the corresponding CS signals SD_CKE Synchronous DRAM clock enable Connected directly to the CKE clock enable signal of SDRAMs Enables and disables the clock internal to SDRAM When CKE is low memory can enter a power down mode where operations are suspended or they can enter self refresh mode SD_CKE functionality is controlled by DCR COC For designs using external multiplexing setting COC allows 50 to pr
28. d trovcv 0 ns R6 Configuration Override Setup Time to RSTOUT invalid tcos 20 tcyc R7 Configuration Override Hold Time after RSTOUT invalid tcoH 0 ns R8 RSTOUT invalid to Configuration Override High Impedance troicz 1 to system Thus RESET must be held minimum of 100 ns _ Lez eS an f N CN Or All AC timing is shown with respect to 50 Vpp levels unless otherwise noted During low power STOP the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously RESET RSTOUT Configuration Overrides Refer to chip configuration module CCM chapter in device s reference manual for pa RCON Override pins Figure 14 RESET and Configuration Override Timing information MCF5271 Integrated Microprocessor Hardware Specification Rev 4 30 Freescale Semiconductor Electrical Characteristics 7 9 Input Output Timing Specifications Table 16 lists specifications for the PC input timing parameters shown in Figure 15 Table 16 12 Input Timing Specifications between 2 SCL and I2C_SDA Num Characteristic Min Max Units Start condition hold time 2 2 Clock low period 8 13 I2C SCL I2C SDA rise time Vi 0 5 V to 2 4 V 1 ms 4 Data hold time 0 ns I5 12C_SCL I2C_SDA fall time
29. ecommended power down sequence is as follows 1 Drop Vpp to 0 V 2 Drop OVpp Vpppj j supplies 5 3 Decoupling Place the decoupling caps as close to the pins as possible but they can be outside the footprint of the package 0 1 and 0 01 uF at each supply input 5 4 Buffering Use bus buffers on all data address lines for all off board accesses and for all on board accesses when excessive loading is expected See Section 7 Electrical Characteristics 55 Pull up Recommendations Use external pull up resistors on unused inputs See pin table 5 6 Clocking Recommendations Use a multi layer board with a separate ground plane Place the crystal and all other associated components as close to the EXTAL and XTAL oscillator pins as possible Do not run a high frequency trace around crystal circuit Ensure that the ground for the bypass capacitors is connected to a solid ground trace the ground trace to the ground pin nearest EXTAL and XTAL This prevents large loop currents in the vicinity of the crystal ground pin to the most solid ground in the system Do not connect the trace that connects the oscillator and the ground plane to any other circuit element This tends to make the oscillator unstable Tie XTAL to ground when an external oscillator is clocking the device 5 7 Interface Recommendations 5 7 1 SDRAM Controller 5 7 1 1 SDRAM Controller Signals in Syn
30. f a reference clock The reference clock is the CLKOUT output All other timing relationships can be derived from these values Table 11 Processor Bus Input Timing Specifications Name Characteristic Symbol Min Max Unit freq System bus frequency sys 2 50 75 MHz BO CLKOUT period 1 75 ns Control Inputs Bia Control input valid to CLKOUT high 9 ns 1 BKPT valid to CLKOUT high tBKVCH 9 ns B2a CLKOUT high to control inputs invalid 0 ns B2b CLKOUT high to asynchronous control input BKPT invalid tBKNCH 0 ns Data Inputs B4 Data input 0 31 0 valid to CLKOUT high tpivcH 4 ns B5 CLKOUT high to data input D 31 0 invalid tcHDII 0 ns Timing specifications are tested using full drive strength pad configurations a 50ohm transmission line environment 3 TEA and TA pins are being referred to as control inputs Refer to figure A 19 MCF5271 Integrated Microprocessor Hardware Specification Rev 4 22 Freescale Semiconductor Electrical Characteristics Timings listed in Table 11 are shown in Figure 7 The timings are also valid for inputs sampled on the negative clock edge CLKOUT 75MHz 1 5V TsETUP Input Setup And Hold Invalid Invalid 1 5V Valid 1 5V trise Input Rise Time tfall Input Fall Time CLKOUT lt
31. kage Dimensions 160 QFP Figure 6 shows MCF5270 71CAB80 package dimensions DETAIL C a a m m lt lt m e e ve DETAIL A Y 0 20 0 008 amp c Slo 9 METAL _ 0 20 0 008 A B GY i S gt 020 0 008 9 p Ly 4 L 0 13 0 005 Q c AB S D SECTION H MILLIMETERS INCHES MIN MAX MIN MAX 27 90 28 10 1 098 1 106 27 90 28 10 1 098 1 106 3 35 3 85 0 132 1 106 0 22 0 38 0 009 0 015 3 20 3 50 0 126 0 138 0 22 0 33 0 009 0 013 0 65 BSC 0 026 REF 0 25 0 35 0 010 0 014 NOTES DIMENSIONING AND TOLERINCING PER ANSI Y14 5M 1982 CONTROLLING DIMENSION MILLIMETER 3 DATUM PLAN IS LOCATED BOTTOM OF 0 11 0 23 0 004 0 009 LEAD AND IS COINCIDENT WITH THE LEAD WHERE 0 70 _ 0 90 0 028 0 035 THE LEAD EXITS THE PLASTIC BODY AT THE 25 35 BSC 0 998 REF BOTTOM OF THE PARTING LINE 5 16 5 16 4 DATUMS B AND D TO BE DETERMINED 0 11 0 191 0 004 0 007 0 325 BSC 0 013 REF o 17 0 T 0 13 0 30 0 005 0 012 31 00 31 40 1 2
32. l Timing EMDIO and EMDC Table 21 lists MII serial management channel timings The FEC functions correctly with a maximum MDC frequency of 2 5 MHz Table 21 Serial Management Channel Timing Num Characteristic Min Max Unit M10 EMDC falling edge to EMDIO output invalid minimum propagation delay 0 ns M11 EMDC falling edge to EMDIO output valid max prop delay m 25 ns M12 EMDIO input to EMDC rising edge setup 10 ns M13 EMDIO input to EMDC rising edge hold 0 ns M14 pulse width high 40 60 MDC period M15 pulse width low 40 60 MDC period Figure 19 shows MII serial management channel timings listed in Table 21 gt EMDC output ws lt gt EMDIO output lt gt gt lt EMDIO input gt lt DuC oe Figure 19 Serial Management Channel Timing Diagram gt lt MCF5271 Integrated Microprocessor Hardware Specification Rev 4 34 Freescale Semiconductor Electrical Characteristics 7 11 32 Bit Timer Module AC Timing Specifications Table 22 lists timer module AC timings Table 22 Timer Module AC Timing Specifications 0 66 MHz Name Characteristic Unit Min Max T1 DTOIN DT1IN DT2IN DT3IN cycle time 3 tcvc T2 DTOIN DT1IN DT2IN DT3IN pulse width 1 7 12 QSPI Electrical Specifications Table 23 list
33. lt Ov i t cn CI v g iO wv t o ND wy wv vy wv v v v wv ov wv t 4t t e c c e e wo C C an tees en ree a ua a Gua S rath A17 ERXDO r 2 16 ERXDI 3 O 15 ERXD2 4 14 ERXD3 5 A13 ERXDV 6 A12 ERXCLK 4 7 ECRS 8 VSS ECOL All UOTIN 10 UOTOUT A9 UOCTS A8 UORXD UORTS 5 Core VDD 1 O VDD VSS VSS O VDD Core 3 TEST A4 CLKMODI MCF5271 A3 CLKMODO A2 DATA31 Al DATA30 0 DATA29 TS DATA28 TA DATA27 R W DATA26 O VDD DATA25 vss DATA24 SD_WE DATA23 SD_SCAS vss SD_SRAS CLKOUT DATA22 VSS DATA21 VDDPLL DATA20 EXTAL 19 XTAL DATA18 VSSPLL DATA17 RESET DATA16 RSTOUT vss O VDD 71 TDO DsO 72 50 DATA6 51 DATAS 52 Core 2 53 DATA4 56 DATA3 57 DATA2 58 DATAI 59 DATAO 60 C 6 O VDD r 69 TRST DSCLK 70 O VDD 41 DATAI5 D 42 DATAI4 43 DATAI3 DATAI2 45 46 0 47 DATA9 48 DATAS C 49 C TMS BKPT L TDI DSI 73 TCLK PSTCLK 68 Figure 5 MCF5270 71CABxxx Pinout 160 QFP MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 15 Mechanicals Pinouts and Part Numbers 6 4 Pac
34. n for seven wire serial mode connections to the external transceiver are shown in Table 5 Table 5 Seven Wire Mode Configuration Signal Description MCF5271 Pin Transmit clock ETXCLK Transmit enable ETXEN Transmit data ETXD 0 Collision ECOL Receive clock ERXCLK Receive enable ERXDV Receive data ERXD 0 Unused configure as PB14 ERXER Unused input tie to ground ECRS Unused configure as PB 13 11 ERXD 3 1 Unused output ignore ETXER Unused configure as PB 10 8 ETXD 3 1 Unused configure as PB15 EMDC Input after reset connect to ground EMDIO Refer to the M5271EVB evaluation board user s manual for an example of how to connect an external PHY Schematics for this board are accessible at the 5271 site by navigating to http www freescale com coldfire 5 7 3 BDM Use the BDM interface as shown in the M5271EVB evaluation board user s manual The schematics for this board are accessible at the Freescale website at http www freescale com coldfire 6 Mechanicals Pinouts and Part Numbers This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF5271 devices See Table 4 for a list the signal names and pin locations for each device MCF5271 Integrated Microprocessor Hardware Specification Rev 4 12 Freescale Semiconductor Mechanicals Pinouts and Part Numbers 6 1 Pinout 196 MAPBGA The following figure show
35. nterparts For further information see http www freescale com or contact your Freescale sales representative For information on Freescale s Environmental Products program go to http www freescale com epp 4 77 freescale semiconductor
36. on Section 5 2 1 1 Power Up Sequence first bullet changed Use 1 us to Use 1 ms Corrected position of spec D5 in Figure 11 Figure 3 Corrected M4 ball location from DATAS to DATA6 changed DATAn labels to Dn for consistency Table 14 Added DACKn and DREQn to footnote Table 9 added PLL supply voltage row 4 Added part number MCF5270CAB100 in Table 6 MCF5271 Integrated Microprocessor Hardware Specification Rev 4 40 Freescale Semiconductor Document Revision History MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 41 How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information
37. on by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2009 All rights reserved RoHS compliant and or Pb free versions of Freescale products have the functionality and electrical characteristics as their non RoHS compliant and or non Pb free cou
38. ons for the debug AC timing parameters shown in Figure 26 Table 25 Debug AC Timing Specification 150 MHz Num Characteristic Units Min Max DEO PSTCLK cycle time 0 5 DE1 PST valid to PSTCLK high 4 ns DE2 PSTCLK high to PST invalid 1 5 ns DE3 DSCLK cycle time 5 4 DSI valid to DSCLK high 1 DE5 DSCLK high to DSO invalid 4 DE6 input data setup time to CLKOUT rise 4 ns DE7 CLKOUT high to BKPT high 2 0 10 ns input relative to the rising edge of 1 Figure 25 shows real time trace timing for the values in Table 25 DSCLK and DSI are synchronized internally D4 is measured from the synchronized DSCLK PSTCLK L gt lt PST 3 0 0 Figure 25 Real Time Trace AC Timing Figure 26 shows BDM serial port AC timing for the values in Table 25 MCF5271 Integrated Microprocessor Hardware Specification Rev 4 38 Freescale Semiconductor Documentation V LF LS VS LS VS DSCLK DSI X Current X Next 080 X Past Figure 26 Serial Port AC Timing 8 Documentation Documentation regarding the MCF5271 and their development support tools is available from a local Freescale distributor a Freescale semiconductor sales office the Freescale
39. ovide command bit functionality BS 3 0 Column address strobe For synchronous operation BS 3 0 function as byte enables to the SDRAMs They connect to the DQM signals or mask qualifiers of the SDRAMs CLKOUT Bus clock output Connects to the CLK input of SDRAMs 5 7 1 2 Address Multiplexing See the SDRAM controller module chapter in MCF5271 Reference Manual for details on address multiplexing 5 7 2 Ethernet PHY Transceiver Connection The FEC supports both an MII interface for 10 100 Mbps Ethernet and a seven wire serial interface for 10 Mbps Ethernet The interface mode is selected R CNTRL MII MODE In MII mode the 802 3 standard defines and the FEC module supports 18 signals These are shown in Table 4 Table 4 Mode Signal Description MCF5271 Pin Transmit clock ETXCLK Transmit enable ETXEN Transmit data ETXD 3 0 Transmit error ETXER Collision ECOL Carrier sense ECRS Receive clock ERXCLK Receive enable ERXDV Receive data ERXD 3 0 MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 11 Mechanicals Pinouts and Part Numbers Table 4 Mode continued Signal Description MCF5271 Pin Receive error ERXER Management channel clock EMDC Management channel serial data EMDIO The serial mode interface operates in what is generally referred to as AMD mode The MCF5271 configuratio
40. rom SRAM backdoor Block Diagram EIM CHIP SELECTS Arbiter FAST ETHERNET CONTROLLER FEC 4 CH ME DREQ 2 0 DACK 2 0 PE is V2 ColdFire CPU BDM DIV EMAC JTAG Watchdog Timer MDHA Cryptography Modules PADI Pin Muxing SDRAMC lt QSPI 4 2C_SDA q 2 lt p gt UnT XD 4 9 UnRXD UnRTS H4 UnCTS DTnOUT lt DTnIN 4 39 FEC 4 gt D 31 0 P 23 0 4 t gt CS 3 0 lt TA lt 15211 0 TEA 4 BS 3 0 64 Kbytes SRAM 8Kx16 x4 8 Kbytes CACHE 1Kx32 x2 To From Arbiter PORTS GPIO lt gt CIM PLL CLKGEN PITO PIT1 PIT2 To From INTC Edge Port Figure 1 MCF5271 Block Diagram MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor Features 3 Features For a detailed feature list see the MCF5271 Reference Manual MCF5
41. s QSPI timings Table 23 QSPI Modules AC Timing Specifications Name Characteristic Min Max Unit 51 QSPI CS 1 0 to 1 510 952 QSPI_CLK high to QSPI DOUT valid 10 5 083 QSPI high to QSPI DOUT invalid Output hold 2 ns 054 QSPI DIN to QSPI Input setup 9 ns QS5 QSPI DIN to QSPI CLK Input hold 9 ns The values in Table 23 correspond to Figure 20 QSPI CS 1 0 os QSPI_CLK X X DXX sal QSPI_DIN x x Figure 20 QSPI Timing QSPI DOUT MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 35 Electrical Characteristics 7 13 JTAG and Boundary Scan Timing Table 24 JTAG and Boundary Scan Timing Num Characteristics Symbol Min Max Unit J1 TCLK Frequency of Operation 1 4 fsys 2 42 Cycle Period 4 tcyc J3 TCLK Clock Pulse Width tucw 26 ns 44 TCLK Rise and Fall Times 0 3 ns J5 Scan Input Data Setup Time to TCLK Rise tBspsT 4 ns 46 Boundary Scan Input Data Hold Time after TCLK Rise 26 ns 47 Low to Boundary Scan Output Data Valid tBspv 0 33 ns 48 Low to Boundary Scan Output High Z tBspz 0 33 ns 49 5 TDI Input Data Setup Time to TCLK Rise tTAPBST 4 m ns 410
42. s a pinout of the MCF5270 71CVMxxx package 1 2 4 5 6 7 3 8 9 QSPI_ m A ETXCLK ETXD3 ETXD2 Pour QSPLCSO UPRXD U2TXD ERXDO ETXDO QSPLDIN BS3 QSPICS1 U1CTS C ERXD2 ERXD1 ETXEN QSCK BS2 D ERXCLK ERXDV ERXD3 EMDIO U1RXD1 U1TXD E ECRS ECOL SD CKE F UoRXD UOCTS DTOUTO TEST e 1 4 3 2 1 9 10 1 5 2 2 2 2 DOODDE o Boe EEE lt lt 2 3 6 7 8 9 10 11 Figure 3 MCF5270 71CVMxxx Pinout 196 MAPBGA MCF5271 Integrated Microprocessor Hardware Specification Rev 4 12 DDATA2 DDATA1 12 A A A A A A A 13 3 7 6 4 1 7 4 0 ET 1 1 1 1 1 5 RW 5 gt gt DTOUT3 G DTINS H VSSPLL L 4 m o Freescale Semiconductor 13 Mechanicals Pinouts and Part Numbers 6 2 Package Dimensions 196 MAPBGA Figure 4 shows MCF5270 71CVMxxx package dimensions X D Laser mark for pin 1 X identification in this area NOTES Dimensions are in millimeters Interpret dimensions and tolerances per ASME Y14 5M 1994
43. se top surface as measured by the cold plate method MIL SPEC 883 Method 1012 1 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51 2 When Greek letters are not available the thermal characterization parameter is written in conformance with Psi JT The average chip junction temperature Ty in C can be obtained from T TA 1 Where MCF5271 Integrated Microprocessor Hardware Specification Rev 4 18 Freescale Semiconductor T Ambient Temperature C Package Thermal Resistance Junction to Ambient C W Pint Ipp x Watts Chip Internal Power Electrical Characteristics Power Dissipation on Input and Output Pins User Determined For most applications lt and can be ignored An approximate relationship between Pp and T if is neglected is Py K T 273 C Solving equations and 2 for K gives K Pp x Ta 273 Oma 3 where K is a constant pertaining to the particular part K can be determined from equation 3 by measuring Pp at equilibrium for a known TA Using this value of the values of Pp and 2 Ty can be obtained by solving equations 1 and 2 iteratively for any value of 73 DC Electrical Specifications Table 9 DC Elec
44. t risk when the processor is not consuming power Examples are if no system clock is present or if clock rate is very low which would reduce overall power consumption Also at power up system clock is not present during the power up sequence until the PLL has attained lock Ron 7 4 Oscillator and PLLMRFM Electrical Characteristics Table 10 HiP7 PLLMRFM Electrical Specifications sg Min Max Num Characteristic Symbol Value Value Unit 1 PLL Reference Frequency Range MHz Crystal reference fret crystal 8 25 External reference fret ext 8 25 1 1 mode NOTE fsys 2 2 x 1 1 fret 1 1 24 75 2 Core frequency fsys 150 MHz CLKOUT Frequency 0 75 MHz External reference fsys 2 fref 32 75 MHz On Chip PLL Frequency 3 Loss of Reference Frequency 32 flor 100 1000 kHz 4 Self Clocked Mode Frequency fsom 10 25 15 25 MHz 5 Crystal Start up Time 5 6 tat 10 ms MCF5271 Integrated Microprocessor Hardware Specification Rev 4 20 Freescale Semiconductor Electrical Characteristics Table 10 HiP7 PLLMRFM Electrical Specifications continued xm Min Max Characteristic Symbol Value Value Unit 6 XTAL Load Capacitance 5 30 pF 7 PLL Lock Time gt 713 750 us 8 Power up To Lock Time 5 6 8 tipik With Crystal Reference includes 5 time 11 ms Without Crystal Reference 750 us 9 1 1 Mode Clock Skew between CLK
45. trical Specifications Characteristic Symbol Min Typical Max Unit Core Supply Voltage Vpp 1 4 1 6 Pad Supply Voltage OVpp 3 0 3 6 V PLL Supply Voltage VppPLL 3 0 xS 3 6 V Input High Voltage 0 7 x OVpp 3 65 V Input Low Voltage ViL Vas 0 3 0 35 x OVpp V Input Hysteresis Vuys 0 06 x OVpp mV Input Leakage Current lin 1 0 1 0 uA Vin Vpp or Vss Input only pins High Impedance Off State Leakage Current loz 1 0 1 0 uA Vin Vpp or Vss All input output and output pins Output High Voltage All input output and all output pins Vou OVpp 0 5 V 5 0 mA Output Low Voltage All input output all output pins VoL 0 5 V lot 5 0mA Weak Internal Pull Up Device Current tested at Max 10 130 uA Input Capacitance 3 Cin pF All input only pins mE 7 All input output three state pins 7 MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 19 Electrical Characteristics Table 9 DC Electrical Specifications continued Characteristic Symbol Min Typical Max Unit Load Capacitance Low drive strength C 25 pF High drive strength 50 pF Core Operating Supply Current 5 135 150 mA Pad Operating Supply Current Olpp Master Mode 100 mA Low Power Modes TBD DC Injection Current 3 6 7 8 lic VuEGcLAMP Vss 0 3 V
46. vice MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor 17 Electrical Characteristics 2 This device contains circuitry protecting against damage due to high static voltage or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level e g either Vss or OVpp Input must be current limited to the value specified To determine the value of the required current limiting resistor calculate resistance values for positive and negative clamp voltages then use the larger of the two values All functional non supply pins are internally clamped to Vss and OVpp Power supply must maintain regulation within operating OVpp range during instantaneous and operating maximum current conditions If positive injection current Vin gt OVpp is greater than Ipp the injection current may flow out of and could result in external power supply going out of regulation Insure external OVpp load will shunt current greater than maximum injection current This will be the greatest risk when the processor is not consuming power ex no clock Power supply must maintain regulation within operating OVpp range during instantaneous and operating maximum current conditions 7 2 Thermal Characteristics
47. ytes configurable cache and a 32 bit SDR SDRAM memory controller Freescale Semiconductor Inc 2009 All rights reserved freescale semiconductor MCF5271 Family Configurations 1 2 MCF5271 Family Configurations Table 1 MCF5271 Family Configurations Module MCF5270 MCF5271 ColdFire V2 Core with EMAC and Hardware Divide x x System Clock 150 MHz Performance Dhrystone 2 1 MIPS 144 Instruction Data Cache 8 Kbytes Static RAM SRAM 64 Kbytes Interrupt Controllers INTC Edge Port Module EPORT External Interface Module 4 channel Direct Memory Access DMA SDRAM Controller Fast Ethernet Controller FEC Hardware Encryption Watchdog Timer WDT Four Periodic Interrupt Timers PIT 32 bit DMA Timers QSPI UART s 2 x x JTAG IEEE 1149 1 Test Access Port x x Package 160 160 196 196 Block Diagram The superset device in the MCF5271 family comes in a 196 mold array plastic ball grid array MAPBGA package Figure 1 shows a top level block diagram of the MCF5271 MCF5271 Integrated Microprocessor Hardware Specification Rev 4 Freescale Semiconductor To From PADI lt To From PADI To From PADI To F
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