µPD78F0058
Contents
1. 4 P04 INTP5 P05 510 Serial interface serial data input P25 SBO Si P20 512 P70 RxD 500 Output Serial interface serial data output P26 SB1 501 21 502 P71 TxD SBO Serial interface serial data input output P25 SIO SB1 26 500 SCKO Serial interface serial clock input output P27 SCK1 P22 SCK2 P72 ASCK STB Output Strobe output for serial interface automatic transmission reception P23 TxD1 BUSY Input Busy input for serial interface automatic transmission reception P24 RxD1 RxDO Input Serial data input for asynchronous serial interface P70 SI2 RxD1 P24 BUSY TxDO Output Serial data output for asynchronous serial interface P71 SO2 TxD1 P23 STB ASCK Input Serial clock input for asynchronous serial interface P72 SCK2 TIOO Input External count clock input to 16 bit timer TMO POO INTPO TIO1 Capture trigger signal input to capture register CROO PO1 INTP1 TH External count clock input to 8 bit timer TM1 P33 2 External count clock input to 8 bit timer 2 P34 TOO Output 16 bit timer output shared with 14 bit PWM output P30 TO1 8 bit timer output P31 TO2 P32 PCL Output Clock output for trimming of main system clock and subsystem clock P35 BUZ Output Buzzer output P36 RTPO RTP7 Output Real time output port to output data in synchronization with triggers P120 P1272. 21 5 3 Connection of Flashptro ete 22 6 PACKAGE DRAWINGS AR ARRR RR asa 24 APPENDIX A DEVELOPMENT 27 APPENDIX RELATED DOCUMENTS 29 uPD78F0058 1 DIFFERENCES BETWEEN uPD78F0058 AND MASK ROM VERSIONS The 78 0058 is a product provided with a flash memory which enables on board reading erasing and rewriting of programs with device mounted on target system The functions of the uPD78F0058 except the functions specified for flash memory and mask option of P60 to P63 pins can be made the same as those of the mask ROM versions by setting the memory size switching register IMS and internal expansion RAM size switching register IXS Table 1 1 shows the differences between the flash memory version uPD78F0058 and the mask ROM versions uPD780053 780054 780055 780056 and 780058 Table 1 1 Differences between uPD78F0058 and Mask ROM Versions uPD78F0058 Mask ROM Versions Internal ROM structure Flash memory Mask ROM Internal ROM capacity 60 Kbytes LPD780053 24 Kbytes 780054 32 Kbytes 780055 40 Kbytes 780056 48 Kbytes 780058 60 Kbytes Internal expansion RAM capacity 1024 by
3. P27 SCKO 18 P67 ASTB P40 ADO 19 P66 WAIT P41 AD1 20 P65 WR P42 AD2 O P43 AD3 O P44 AD4 P45 AD5 P46 AD6 P47 AD7 P50 A8 P51 A9 P52 A10 P53 A11 P54 A12 P55 A13 Vss1 P56 A14 P57 A15 P60 O P61 P62 P63 O P64 RD O Note Under planning Cautions 1 Connect the Vpr pin directly to Vss in normal operation mode 2 Connect the AVss pin to Vsso Remark When the uPD78F0058 is used in application fields that require reduction of the noise generated from inside the microcontroller the implementation of noise reduction measures such as supplying voltage to and individually and connecting Vsso and Vssi to different ground lines is recommended uPD78F0058 A8 A15 ADO AD7 ANIO ANI7 ANOO ANO1 ASCK ASTB AVREFO 1 AVss BUSY BUZ P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P67 P70 P72 P120 P127 P130 P131 Address Bus Address Data Bus Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Reference Voltage Analog Ground Busy Buzzer Clock INTPO INTP6 0 5 PO7 Interrupt from Peripherals 0 Porti Port2 Port3 Port4 Port5 Port6 Port7 Port12 Port13 PCL RD RESET RTPO RTP7 RxD1 SBO SB1 SCK0 SCK2 510 512 SO0 SO2 STB TIOO TIO1 TH 2 TOO TO2 TxDO TxD1 1 VPP
4. 80 pin plastic QFP 14 x 14 mm resin thickness 2 7 mm 80 pin plastic QFP 14 x 14 mm resin thickness 1 4 mm Note 3 80 pin plastic TQFP fine pitch 12 x 12 mm The flash memory capacity can be changed with the memory size switching register IMS 2 The internal expansion RAM capacity can be changed with the internal expansion RAM size switching register IXS 3 Under planning uPD78F0058 PIN CONFIGURATION Top View 80 pin plastic 14 x 14 mm resin thickness 2 7 mm uPD78F0058GC 3B9 80 pin plastic 14 x 14 mm resin thickness 1 4 mm uPD78F0058GC 8BTNote 80 pin plastic TQFP fine pitch 12 x 12 mm uPD78F0058GK BE9 QN 285g gt 24434 AE T 2 22222 8 gt Eran CoO lt gt gt gt gt OO Q DO O Q O O O 15 5 nud O RESET 16 6 2 127 7 P17 ANI7 3 P126 RTP6 AVss O 4 O P125 RTP5 P130 ANOO 5 P124 RTP4 P131 ANO1 O 6 P123 RTP3 AVrer1 7 P122 RTP2 P70 SIZ RXDO 8 P121 RTP1 P71 SO2 TxDO 9 P120 RTPO P72 SCK2 ASCK 10 P37 20 911 11 P36 BUZ P21 SO1 12 P35 PCL P22 SCK1 13 P34 TI2 P23 STB TxD1 14 P33 TM P24 BUSY RxD1 15 P32 TO2 25 510 5 0 16 1 1 P26 SO0 SB1 17
5. 780024 uPD780964 0780924 uPD78014H 8 K 32 K 16 bit Watch 10 bit A D Serial Interface 3 ch UART 1 ch External Expansion 2 ch Time division 3 wire 1 ch 3 ch Time division UART 1 ch 3 ch UART 1 ch 3 ch UART 1 ch Time division 3 wire 1 ch uPD78018F uPD78014 uPD780001 uPD78002 uPD78083 uPD780208 32 K 60 K uUPD78044F 16 K 40 K uPD78024 0780308 24 K 32 K 48 K 60 K uPD78064B 32K uPD78064 uPD78098 uPD78P0914 Note 10 bit timer 16 K 32 K 32 K 60 K 32K 1 channel 2 ch UART 2 ch 1 ch UART 1 ch 3 ch Time division UART 1 ch 2 ch UART 1 ch 3 ch UART 1 ch 2 ch uPD78F0058 OVERVIEW OF FUNCTION Internal Flash memory Function 60 KbytesNote 1 memory High speed RAM 1024 bytes Expansion RAM 1024 bytesNote 2 Buffer RAM 32 bytes Memory space 64 Kbytes General purpose registers 8 bits x 32 registers 8 bits x 8 registers x 4 banks Instruction cycle On chip instruction execution time cycle modification function When main system clock selected 0 4 us 0 8 5 1 6 us 3 2 us 6 4 us 12 8 us at 5 0 MHz operation When subsystem clock selected 122 us at 32 768 kHz operation Instruction set
6. ADO AD7 I O Lower address data bus for extending memory externally P40 P47 A8 A15 Output Higher address bus for extending memory externally P50 P57 Output Strobe signal output for read operation of external memory P64 Strobe signal output for write operation of external memory P65 12 uPD78F0058 2 2 Non Port Pins 2 2 Pin Name WAIT Input Funciton Inserting wait for accessing external memory After Reset Alternate Function P66 ASTB Output Strobe output which externally latches address information output to port 4 and port 5 to access external memory P67 ANIO ANI7 Input A D converter analog input P10 P17 ANOO ANO1 Output D A converter analog output P130 P131 Input A D converter reference voltage input shared with analog power supply AVRreF1 Input D A converter reference voltage input AVss A D converter ground potential Voltage equal to Vsso RESET Input System reset input Input Connecting crystal resonator for main system clock oscillation Input Connecting crystal resonator for subsystem clock oscillation Positive power supply voltage for ports Ground potential of ports Positive power supply except ports and analog parts Ground potential except ports and analog parts Applying high voltage for progr
7. 16 bit operation Multiplication division 8 bits x 8 bits 16 bits 8 bits Bit manipulation set reset test Boolean operation BCD correction etc ports Total 68 CMOS input 2 22 CMOS I O 62 N ch open drain I O 2524 A D converter 8 bit resolution x 8 channels D A converter 8 bit resolution x 2 channels Serial interface e 3 wired serial l O SBI 2 wire serial I O mode selectable 1 channel 3 wired serial I O mode 32 byte on chip automatic transmission reception function 3 wired serial I O UART mode on chip time division transfer function selectable 1 channel 1 channel 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Timer output 3 14 bit PWM output capable 1 Clock output 19 5 kHz 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz 2 5 MHz 5 0 MHz main system clock at 5 0 MHz operation 32 768 kHz subsystem clock at 32 768 kHz operation Buzzer output 1 2 kHz 2 4 kHz 4 9 kHz 9 8 kHz main system clock at 5 0 MHz operation Vectored interrupt Maskable Internal 13 External 7 Source Non maskable Internal 1 Software 1 Test input Internal 1 External 1 Power supply voltage 1 8 5 5 V Operating ambient temperature Ta 40 to 85 C Package
8. Vsso Vss1 WAIT WR X1 X2 XT1 XT2 Programmable Clock Read Strobe Reset Real Time Output Port Receive Data Serial Bus Serial Clock Serial Input Serial Output Strobe Timer Input Timer Input Timer Output Transmit Data Power Supply Programming Power Supply Ground Wait Write Strobe Crystal Main system Clock Crystal Subsystem Clock uPD78F0058 BLOCK DIAGRAM TE 16 bit TIMER 0 00 TIO1 INTP1 PO1 EVENT COUNTER TO1 P31 8 bit TIMER TH P33 EVENT COUNTER 1 TO2 P32 8 bit TIMER TI2 P34 EVENT COUNTER 2 SIO SBO P25 500 5 1 26 5 27 11 20 1 21 1 22 STB TxD1 P23 BUSY RxD1 P24 BUSY RxD1 P24 STB TxD1 P23 SI2 RxDO P70 SO2 TxD0 P71 SCK2 ASCK P72 ANIO P10 ANI7 P17 AVss AVREFO ANOO P130 ANO1 P131 AVss AVnEF1 00 INTP5 P05 BUZ P36 PCL P35 WATCHDOG TIMER WATCH TIMER SERIAL INTERFACE 0 SERIAL INTERFACE 1 SERIAL PORTO PORT1 PORT2 PORT3 PORT4 5 6 PORT7 INTERFACE 2 A D CONVERTER D A CONVERTER INTERRUPT CONTROL BUZZER OUTPUT CLOCK OUTPUT CONTROL 78K 0 FLASH cpu MEMORY 60 K
9. Technical 011538 OS for 78K 0 Series 78 0 Basic EEU 5010 Fuzzy Knowledge Data Creation Tool EEU 829 EEU 1438 78K 0 78 87AD Series Fuzzy Inference Development Support System Translator EEU 862 EEU 1444 78K 0 Series Fuzzy Inference Development Support System Fuzzy Inference Module EEU 858 EEU 1441 78K 0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger Other Documents Document Name IC PACKAGE MANUAL EEU 921 EEU 1458 Document No Japanese C10943X English Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grade on NEC Semiconductor Devices C11531J C11531E Reliable Quality Maintenance on NEC Semiconductor Devices C10983J C10983E Electrostatic Discharge ESD Test MEM 539 Semiconductor Devices Quality Guarantee Guide C11893J MEI 1202 Microcomputer Product Series Guide U11416J Caution contents of the above related documents are subject to change without notice The latest documents should be used for design etc 30 uPD78F0058 MEMO 31 uPD78F0058 MEMO 32 uPD78F0058 MEMO 33 uPD78F0058 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide
10. U11517J U11517E Language U11518J U11518bE CC78K 0 C Compiler Application Note Programming Know how EEA 618 EEA 1208 CC78K Series Library Source File EEU 777 78000 EEU 810 U11376E 78000 010057 U10057E IE 78000 R BK EEU 867 EEU 1427 78308 011362 U11362E EP 780058GC R Planned Planned EP 780058GK R Planned Planned SM78KO System Simulator Windows based Reference 010181 U10181E SM78K Series System Simulator External Parts User Open Interface Specification U10092J U10092E ID78KO Integrated Debugger EWS based Reference U11151J ID78KO Integrated Debugger PC based Reference U11539J U11539E ID78KO0 Integrated Debugger Windows based Guide U11649J U11649E SD78KO0 Screen Debugger PC 9800 Series MS DOS based Introduction EEU 852 Reference U10952J SD78K 0 Screen Debugger IBM PC AT PC DOS based Guide EEU 5024 EEU 1414 Reference U11279J U11279E Caution The contents of the above related documents are subject to change without notice The latest documents should be used for design etc 29 uPD78F0058 Embedded Software Documents User s Manual Document Name 78K 0 Series Real time OS Basic Document No Japanese U11537J English Installation U11536J
11. 4 uPD78F0058 80 pin plastic QFP 14 x 14 Unit mm 80 PIN PLASTIC 14 14 detail of lead end R Q NOTE ITEM MILLIMETERS INCHES Each lead centerline is located within 0 13 mm 0 005 inch of A 17 20 0 20 0 677 0 008 its true position at maximum material condition 0 009 B 14 00 0 20 0 5513 0 009 0 009 14 00 0 20 0 55170 008 17 20 0 20 0 677 0 008 F 0 825 0 032 G 0 825 0 032 0 002 H 0 32 0 06 0 01370 003 0 13 0 005 9 0 65 0 026 K 1 60 0 20 0 063 0 008 0 009 L 0 80 0 20 0 03178 008 0 03 0 001 M 0 177595 0 0077 0 003 0 10 0 004 1 40 0 10 0 055 0 004 Q 0 125 0 075 0 005 0 003 7 7 3 13 8 13 5 1 70 0 067 P80GC 65 8BT 25 uPD78F0058 80 pin plastic TQFP fine pitch 12 x 12 Unit mm 80 PIN PLASTIC FINE PITCH 0212 detail of lead end no i ITEM MILLIMETERS INCHES Each lead centerline is located within 0 10 mm 0 004 inch of A 14 0 0 2 0 551 0 009 its true position T P at maximum material condition 9 008 0 009 B 12 0 0 2 0 472 0 009 0 009 12 0 0 2 0 472 30 003 0 009 14 0 0 2 0 551 0
12. OUT data output disable gt H heh Vsso 77 ap Medium breakdown input buffer 17 uPD78F0058 3 MEMORY SIZE SWITCHING REGISTER IMS This register sets a part of internal memory unused by software The memory mapping can be made the same as that of mask ROM versions with different types of internal memory ROM and RAM by setting the memory size switching register IMS The IMS is set with an 8 bit memory manipulation instruction RESET input sets the IMS to CFH Figure 3 1 Format of Memory Size Switching Register Symbol 7 6 5 4 3 2 1 0 Address At reset R W IMS RAM2 0 ROMS ROM ROM1 ROMO FFFOH CFH R W ROMO Selection of Internal ROM Capacity 24 Kby 32 40 48 Kby 56 Kby 60 Kby Setting prohibited RAMO 1 1 0 Others Note When using external device expansion function set the internal ROM capacity to less than 56 Kbytes Table 3 1 shows the IMS set value to make the memory mapping the same as those of mask ROM versions Table 3 1 Set Value of Memory Size Switching Register Target Mask ROM Versions IMS Set Value 780053 C6H uPD780054 C8H 780055 780056 CCH 780058 18 uPD78F0058 4 INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER IXS This register sets
13. Reset Alternate Function ADO AD7 50 57 5 8 bit input output port LED can be driven directly Input output can be specified bit wise When used as an input port an internal pull up resistor can be connected by software Port 6 8 bit input output port Input output can be specified bit wise N ch open drain input output port LED can be driven directly When used as an input port an internal pull up resistor can be connected by software RD WR WAIT ASTB P72 Port 7 3 bit input output port Input output can be specified bit wise When used as an input port an internal pull up resistor can be connected by software 512 SO2 TxDO SCK2 ASCK P120 P127 Port 12 8 bit input output port Input output can be specified bit wise When used as an input port an internal pull up resistor can be connected by software RTPO RTP7 P130 Port 13 2 bit input output port Input output can be specified bit wise When used as an input port an internal pull up resistor can be connected by software ANOO ANO1 11 uPD78F0058 2 2 Non Port Pins 1 2 Pin Name Funciton After Reset Alternate Function INTPO External interrupt request input by which the effective edge rising Input POO TIOO INTP1 edge falling edge or both rising edge and falling edge can be PO1 TIO1 specified INTP2 P02
14. and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS device behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 3 STATUS BEFORE INITIALIZATION OF
15. 00 Series MS DOS based IBM PC AT and compatibles PC DOS IBM DOS MS DOS based HP9000 Series 300 HP UX based HP9000 Series 700 HP UX based SPARCstation SunOS based EWS4800 Series EWS UX V based IBM PC AT and compatibles PC DOS IBM DOS MS DOS Windows based Remarks 1 For third party development tools refer to the 78K 0 Series Selection Guide U11126E 28 2 The RA78K 0 CC78K 0 SM78KO0 ID78K0 SD78K 0 and RX78K 0 are used in combination with the DF780058 uPD78F0058 APPENDIX B RELATED DOCUMENTS Device Related Documents Document No Document Name 780058 780058Y Subseries User s Manual Japanese 112013 English Planned 780053 780054 780055 780056 780058 Preliminary Product Information U12182J Planned HPD78F0058 Preliminary Product Information U12092J This manual 78K 0 Series User s Manual Instruction IEU 849 IEU 1372 78K 0 Series Instruction Table U10903J 78K 0 Series Instruction Set U10904J Development Tools Documents User s Manual Document No Document Name RA78K Series Assembler Package Operation Japanese EEU 809 English EEU 1399 Language EEU 815 EEU 1404 RA78K Series Structured Assembler Preprocessor EEU 817 EEU 1402 CC78K Series C Compiler Operation EEU 656 EEU 1280 Language EEU 655 EEU 1284 78 Compiler Operation
16. 098 1 25 0 049 G 1 25 0 049 0 22 002 0 009 0 002 0 10 0 004 J 0 5 0 020 T P 0 009 K 1 00 2 0 039 0 06 0 008 L 0 5 0 2 0 020 0 009 M 0 145 0 058 0 006 0 002 0 10 0 004 1 05 0 041 0 05 0 05 0 002 0 002 R 5 5 5 5 8 1 27 0 050 P80GK 50 BE9 4 26 uPD78F0058 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for system development using the uPD78F0058 Language Processing Software RA78K ONotes 1 2 3 4 CC78K oNotes 1 2 3 4 DF78005gNotes 1 2 3 4 8 CC78K 0 LNotes 1 2 3 4 78K 0 Series common assembler package 78K 0 Series common C compiler package Device file for uPD780058 Subseries 78K 0 Series common C compiler library source file Flash Memory Writing Tools Flashpro II FL PR2 Dedicated flash writter Product of Naitou Densei Machidaseisakusho Co Ltd FA 80GCNote 8 FA 80GKNote 8 Debugging Tool 78000 Adapter for flash memory writting Product of Naitou Densei Machidaseisakusho Co Ltd 78K 0 Series common in circuit emulator 78000 78K 0 Series common in circuit emulator for integrated debugger 78000 78K 0 Series common brake board 780308 780308 Subseries common emulation board EP 780058GC RNote 8 Emulation probe for 4PD780058 Subseries EV 9200GC 80 Socket to be mounted on a targe
17. 211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r 1 Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 01 504 2787 Fax 01 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 NEC Electronics Hong Kong Lid Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Lid Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd United Square Singapore 1130 Tel 253 8311 Fax 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 719 2377 Fax 02 719 5951 NEC do Brasil S A Sao Paulo SP Brasil Tel 011 889 1680 Fax 011 889 1689 J96 8 35 uPD78F0058 FIP IEBus and QTOP are trademarks of NEC Corporation MS DOS and Windows are trademarks of Microsoft Corporation IBM DOS PC AT and PC DOS are trademarks of IBM Corporation HP9000 Series 300 HP9000 Series 700 and HP UX are trademarks of Hewlett Packard Company SPARCstation is a trademark of SPARC International Inc SunOS is a trademark of Sun Microsyste
18. 924 64 pins Inverter control circuit and UART provided low EMI noise model 64 pins Low noise model of mPD78018F 64 pins Low voltage model 1 8 V ofmPD78014 with increased choice of ROM and RAM capacities 64 pins Adds A D and 16 bit timer to mPD78002 64 pins Adds A D to mPD78002 64 pins Basic subseries for control applications 42 44 pins UART provided low voltage 1 8 V operation For driving FIP 100 pins Enhanced l O FIP of mPD78044F Total number of display outputs 53 78 0 80 pins Adds 6 bit U D counter to mPD78024 Total number of display outputs 34 series 64 pins Basic subseries for driving FIP Total number of display outputs 26 driving LCD 100 pins 780308 xPD780308Y Enhanced SIO of mPD78064 with extended ROM and RAM 100 pins J 2 078064 Low EMI noise model of the mPD78064 100 pins Subseries for driving LCD with UART provided Supporting IEBus m 80 pins Adds IEBus controller to mPD78054 For LV 64 PD78P0914 PWM output LV digital code decoder Hsync counter provided Note Under planning uPD78F0058 The following lists the main functional differences For control For FIP driving For LCD driving For IEBus For LV Function uPD78078 ROM Capacity 32 K 60 K Timer 78070 uPD780018 48 K 60 K 0780058 24 K 60 K uPD78058F 48 K 60 K uPD78054 16 K 60 K uPD780034
19. Bytes RAM 2048 Bytes Vsso Vss1 PORT12 PORT13 REAL TIME EXTERNAL OUTPUT PORT ACCESS SYSTEM CONTROL 01 05 P07 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P67 P70 P72 P120 P127 P130 P131 120 RTP7 P127 ADO P40 AD7 P47 A8 P50 A15 P57 RD P64 WR P65 WAIT P66 ASTB P67 RESET X1 2 XT1 P07 XT2 uPD78F0058 CONTENTS 1 DIFFERENCES BETWEEN MPD78F0058 AND MASK 5 9 2 PIN 2 10 2 4 10 2 2 Non POrtPInS E E A 12 2 3 Pin I O Circuits and Recommended Connection of Unused Pins 2 22222222 14 3 MEMORY SIZE SWITCHING REGISTER 18 4 INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER IXS 19 5 FLASH MEMORY PROGRAMMING R4 nnmnnn mnnn 20 5 1 Selection of Transmission Method eeeeeeeeee eene enne nn nnne nenennnanuaa hana a nana nana ananas aa naa 20 5 2 Function of Flash Memory Programming
20. MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production 34 process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function uPD78F0058 Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 800 366 9782 Fax 800 729 9288 NEC Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0
21. PRELIMINARY PRODUCT INFORMATION NEC MOS INTEGRATED CIRCUIT PD78F0058 8 BIT SINGLE CHIP MICROCONTROLLER DESCRIPTION The uPD78F0058 is a product of the 780058 Subseries in the 78K 0 Series and equivalent to the 780058 with a flash memory in place of internal ROM This device is incorporated with a flash memory which can be programmed without being removed from the substrate Functions are described in detail in the following user s manuals which should be read when carrying out design work HPD780058 780058Y Subseries User s Manual U12013E 78K 0 Series User s Manual Instruction IEU 1372 FEATURES Pin compatible with mask ROM versions except Vr pin Flash memory 60 KbytesNote 1 Internal high speed RAM 1024 bytes Internal expansion RAM 1024 bytesNote 2 Buffer RAM 32 bytes Operable with the same power supply voltage as that of mask ROM version Voo 1 8 to 5 5 Notes 1 The flash memory capacity can be changed with the memory size switching register IMS 2 The internal expansion RAM capacity can be changed with the internal expansion RAM size switching register IXS Remark For the differences between the flash memory versions and the mask ROM versions refer to 1 DIFFERENCES BETWEEN 4PD78F0058 AND MASK ROM VERSIONS ORDERING INFORMATION Part Number Package Internal ROM LPD78F0058GC 3B9 80 pin plastic QFP 14 x 14 mm resin thickness 2 7 mm Flash memory uPD78F0058GC 8BTNe
22. am write verify Connected directly to Vsso in normal operation mode 13 uPD78F0058 2 3 Pin I O Circuits and Recommended Connection of Unused Pins 14 Pin Name 100 Table 2 1 shows the circuit type of each and the recommended connection of unused pins For the configuration of each I O circuit type refer to Figure 2 1 Table 2 1 Circuit Type of Each Pin 1 2 Circuit Type Recommended Connection when Not Used Connected to Vsso 1 1 101 PO2 INTP2 POS INTPS PO4 INTP4 P05 INTP5 Independently connected to Vsso through a resistor PO7 XT1 Connected to 17 7 P20 SI1 P21 SO1 P22 SCK1 P23 STB TxD1 P24 BUSY RxD1 P25 SI0 SBO P26 SO0 SB1 P27 SCKO P30 TOO P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 PCL P36 BUZ P37 Independently connected to or Vsso through a resistor P40 AD0 P47 AD7 Independently connected to through a resistor P50 A8 P57 A15 60 6 Independently connected to or Vsso through a resistor P64 RD P65 WR P66 WAIT P67 ASTB Independently connected to through a resistor P70 S12 RxDO P71 SO2 TxDO P72 SCK2 ASCK P120 RTPO P127 RTP7 Independently connected to or Vs
23. ashpro and the wPD78F0058 differs according to the transmission method The connection for each transmission method is shown in Figures 5 2 to 5 4 Figure 5 2 Connection of Flashpro for 3 wired Serial I O System Flashpro mPD78F0058 n 0 2 Figure 5 3 Connection of Flashpro for UART System Flashpro mPD78F0058 n 0 1 22 uPD78F0058 Figure 5 4 Connection of Flashpro for Pseudo 3 wired Serial I O System Flashpro mPD78F0058 RESET P32 serial clock P30 serial input P31 serial output Vss 23 uPD78F0058 6 PACKAGE DRAWINGS 80 pin plastic QFP 14 x 14 Unit mm 80 PIN PLASTIC 14 14 A detail of lead end 5 1 b LQ R NOTE ITEM MILLIMETERS INCHES Each lead centerline is located within 0 13 mm 0 005 inch of A 17 2 0 4 0 677 0 016 its true position at maximum material condition 0 009 B 14 0 0 2 0 551 0 008 0 009 14 0 0 2 0 551 9 908 17 2 0 4 0 677 0 016 F 0 825 0 032 G 0 825 0 032 0 004 H 0 30 0 10 0 01220 005 0 13 0 005 J 0 65 T P 0 026 K 1 6 0 2 0 063 0 008 0 009 L 0 8 0 2 0 0311 903 4 0 004 M 61510410 0 006 5 503 N 0 10 0 004 P 2 7 0 106 Q 0 1 0 1 0 004 0 004 5 5 5 5 5 3 0 0 119 24 580 65 3 9
24. gramming Functions Reset Descriptions Used to stop write operation and detect transmission cycle Batch verify Compares the entire memory contents with the input data Block verify Compares the contents of the specified memory blocks with the input data Batch delete Deletes the entire memory contents Block delete Deletes the contents of the specified memory block setting 16 Kbytes as one memory block Convergence Prevents over deletion Batch blank check Checks the deletion status of the entire memory Block blank check Checks the deletion status of the specified block High speed write Performs write to the flash memory based on the write start address and the number of data to be written number of bytes Continuous write Performs continuous write based on the information input with high speed write operation Status Used to confirm the current operating mode and operation end Oscillation frequency setting Sets the frequency of the resonator Delete time setting Sets the memory delete time Baud rate setting Sets the transmission rate in transmission using UART system Convergence time setting Sets the correction time in convergence Silicon signature read Outputs the device name and memory capacity and device block information 21 uPD78F0058 5 3 Connection of Flashpro The connection of the Fl
25. idaseisakusho Co Ltd 5 1 Selection of Transmission Method Writing to a flash memory is performed using the Flashpro with a serial transmission mode One of the transmission method is selected from those in Table 5 1 The selection of the transmission method is made by using the format shown in Figure 5 1 Each transmission method is selected by the number of Vee pulses shown in Table 5 1 Table 5 1 List of Transmission Method Transmission Method Channels i Pulses 3 wired serial I O P27 SCKO 26 500 5 1 25 510 5 0 P22 SCK1 P21 SO1 20 511 P72 SCK2 ASCK P71 SO2 TxDO P70 SI1 RxDO P71 SO2 TxDO P70 SI2 RxDO P23 TxD1 P24 RxD1 Pseudo 3 wired serial ONote P32 TO2 serial clock input output P31 TO1 serial data output P30 TOO serial data input Note Serial transmission is performed by controlling the port using software Caution Select a communication system always using the number of Ver pulses shown in Table 5 1 20 uPD78F0058 Figure 5 1 Format of Transmission Method Selection 10V vee Vss 1 2 n gt RESET Vss 5 2 Function of Flash Memory Programming Operations such as writing to a flash memory are performed by various command data transmission and reception operations according to the selected transmission method Table 5 2 shows major functions of flash memory programming Table 5 2 Major Functions of Flash Memory Pro
26. ms Inc NEWS and NEWS OS are trademarks of Sony Corporation The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based ona customer designated quality assu
27. rance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircrafts aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices is Standard unless otherwise specified in NEC s Data Sheets or Data Books If customers intend to use NEC devices for applications other than those specified for Standard quality grade they should contact an NEC sales representative in advance Anti radioactive design is not implemented in this product M4 96 5
28. so through a resistor P130 ANOO P131 ANO1 Independently connected to Vsso through a resistor uPD78F0058 Pin Name RESET Table 2 1 Circuit Type of Each Pin 2 2 Circuit Type Recommended Connection when Not Used XT2 Open AVREF1 AVss Connected to Vsso Connected to Connected to Vsso Connected directly to Vsso 15 uPD78F0058 Figure 2 1 List of Pin I O Circuits 1 2 Schmitt trigger input with hysteresis characteristics pullup enable output disable data 4 IN OUT pullup enable carte data IN OUT output disable input enable Type 10 B pullup enable open drain output disable data TY IN OUT Type 5 N IN OUT 16 Type 11 D pullup enable disable Comparator input Vrer threshold voltage enable uPD78F0058 Figure 2 1 List of Pin I O Circuits 2 2 Type 12 C 16 feedback gt P ch san Eror IN OUT output disable 77 sso y input enable P ch E Analog output voltage N ch XT1 XT2 T Vsso Type 13 K L 1 9O IN
29. t system board made for the 80 pin plastic GC 3B9 GC 8BT type EP 780058GK RNote 8 Emulation probe for 4PD780058 Subseries TGK 080SDW Adapter to be mounted on a target system board made for the 80 pin plastic QFP GK BE9 type Product of TOKYO ELETECH Corporation Consult NEC sole agent for purchase SM78Ko0Notes 5 6 7 78K 0 Series common system simulator ID78KONotes 4 5 6 7 Integrated debugger for IE 78000 R A SD78K ONotes 1 2 Screen debugger for IE 78000 R DF780058Notes 1 2 3 4 5 6 7 8 Device file for uPD780058 Subseries Notes 1 PC 9800 Series MS DOS M based 2 PC AT and compatibles PC DOS IBM DOS MS DOS based 3 HP9000 Series 300 HP UXTM based 4 HP9000 Series 7007 HP UX based SPARCstation SunOS based EWS4800 Series EWS UX V based 9800 Series MS DOS Windows based IBM PC AT and compatibles PC DOS IBM DOS MS DOS Windows based NEWSTM NEWS OS based Under development 27 uPD78F0058 Real time OS 78 0 1 2 3 4 78 0 Series real time OS MX78KONotes 1 2 3 4 78K 0 Series OS Fuzzy Inference Development Support System FE9000Nete 1 9200 5 Fuzzy knowledge data creation tool FT9080Note 1 9085 2 Translator FI78KNotes 1 2 Fuzzy inference module FD78KoNetes 1 2 Fuzzy inference debugger Notes 1 2 3 4 PC 98
30. te 80 plastic 14 x 14 mm resin thickness 1 4 mm Flash memory LPD78F0058GK BE9 80 pin plastic TQFP fine pitch 12 x 12 mm Flash memory Note Under planning Caution Two types of packages are available for uPD78F0058GC refer to 6 PACKAGE DRAWINGS For the suppliable package consult an NEC sales representative The information contained in this document is being issued in advance of the production cycle for the device The parameters for the device may change before final production or NEC Corporation at its own discretion may withdraw the device prior to its production Document No U12092EJ1VOPMOO 1st edition Date Published March 1997 N Printed in Japan Corporation 1997 uPD78F0058 78K 0 SERIES DEVELOPMENT The products in the 78 0 series are listed below The names enclosed in boxes are subseries names Under mass production Y subseries supports bus For control ix 100 pins Adds timer to mPD78054 with enhanced external interface function 100 pins ROM less model of mPD78078 100 pins CU Enhanced serial I O of mPD78078 with limited function 80 pins Enhanced serial I O of mPD78054 low EMI noise model 80 pins Low EMI noise model of mPD78054 80 pins Adds UART and D A to mPD78014 with enhanced I O 64 pins Enhanced A D of mPD780024 64 pins Enhanced serial O of mPD78018F low EMI noise model 64 pins Enhanced A D of mPD780
31. tes 780053 None 780054 None uPD780055 None 780056 None LPD780058 1024 bytes Internal ROM capacity changeable not ChangeableNote 1 Not changeable changeable with memory size switching register IMS Internal expansion RAM capacity ChangeableNote 2 Not changeable changeable not changeable with internal expansion RAM size switching register IXS IC pin Not provided Provided pin Provided Not provided P60 to P63 pin mask option with internal Not provided Provided pull up resistors Notes 1 Flash memory is set to 60 Kbytes by RESET input 2 Internal expansion RAM is set to 1024 bytes by RESET input Caution The noise resistance and noise radiation differ between flash memory versions and mask ROM versions When considering the replacement of flash memory versions with mask ROM versions in the process from trial manufacturing to mass production adequate evaluation should be carried out using CS products not ES products of mask ROM versions Remark Only the uPD780058 and 78F0058 are provided with IXS uPD78F0058 2 PIN FUNCTIONS 2 1 Port Pins 1 2 Pin Name 1 2 4 5 Po7Note 1 Funciton Port 0 Input only After Reset Input Alternate Function INTPO TIOO Input output can be specified bit wise When used as an input port an internal pull up resistor can be connected by software 7 bit input ou
32. the internal expansion RAM capacity by software The memory mapping can be made the same as that of mask ROM versions with different types of internal expansion RAM by setting the internal expansion RAM size switching register IXS The IXS is set with an 8 bit memory manipulation instruction RESET input sets the IXS to Figure 4 1 Format of Internal Expansion RAM Size Switching Register Symbol 7 6 1 0 Address At reset R W 5 4 3 2 IXS o o o o 2 IXRAM1 IXRAMO OAH Ww IXRAM2 IXRAM1 Selection of Internal Expansion RAM Capacity 0 bytes 1024 bytes Setting prohibited Table 4 1 shows the IXS set value to make the memory mapping the same as those of mask ROM versions Table 4 1 Set Value of Internal Expansion RAM Size Switching Register Target Mask ROM Versions IMS Set Value 780053 780054 780055 780056 780058 Remark Even if a uPD78F0058 program in which MOV IXS 0CH is written is executed on the uPD780055 and 780056 the operation will not be affected 19 uPD78F0058 5 FLASH MEMORY PROGRAMMING Writing to a flash memory can be performed without removing the memory from the target system on board Writing is performed connecting the dedicated flash programmer Flashpro to the host machine and the target system Remark Flashpro is a product of Naitou Densei Mach
33. tput port Input INTP1 TIO1 INTP2 4 5 Input only XT1 P10 P17 Port 1 8 bit input output port Input output can be specified bit wise When used as an input port an internal pull up resistor can be connected by software Note 2 ANIO ANI7 Port 2 8 bit input output port Input output can be specified bit wise When used as an input port an internal pull up resistor can be connected by software 511 501 SCK1 STB TxD1 BUSY RxD1 510 5 0 SOO SB1 SCKO Notes 1 10 Port 3 8 bit input output port Input output can be specified bit wise When used as an input port an internal pull up resistor can be connected by software resistor is automatically set unused TOO TO1 2 TH 2 PCL BUZ When using 7 as an input port set 1 to the bit 6 FRC of the processor clock control register Do not use the feedback resistor of the subsystem clock oscillator When using P10 ANIO to P17 ANI7 pins as analog inputs of A D converter the internal pull up uPD78F0058 2 1 Port Pins 2 2 Pin Name P40 P47 Funciton Port 4 8 bit input output port Input output can be specified in 8 bit units When used as an input port an internal pull up resistor can be connected by software Test input flag KRIF is set to 1 by the falling edge detection After
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