EVBUM2078 - NB4N840MMNEVB Evaluation Board User`s Manual
Contents
1. T za s veti orun sema Derim s ss se sei I 1 Specified parts are RoHS compliant 2 Only RoHS compliant equivalent parts may be substituted Board Lay Up This board is implemented in four layers and provides a high bandwidth 50 Q controlled impedance environment The pictures in Figures 5 through 9 show views of the four layers of the evaluation board Board material is FR4 Top Silkscreen Fe A e Top Soldermask Top Plating Cu 1 2 oz 0 0007 Dielectric 0 014 Cu 1 2 0z 0 0007 Cu 1 2 0z 0 0007 Dielectric 0 014 Cu 1 2 0z 0 0007 01 Top Metal Plane o N o Plane 0 062 0 010 o E Bottom Metal Figure 5 Evaluation Board Lay Up http onsemi com 5 NB4N840MMNEVB th R w d econ KD z it NDA bs Mep k ot n NS 04 48 0256 Y lai 16 DA h PEANN ELB bp UN amp a3 purea PP vw yx deri tate Figure 7 Ground Layer hitp onsemi com 6 NB4N840MMNEVB z key 4 Pra ar 0 de 5 M M N EEES TCA MEA te bes MANGN Es e 9 0006 osi vo dis XS EES o QAR Figure 8 Povver Layer Figure 9 Bottom Layer http onsemi com 7 NB4N840MMNEVB ON Semiconductor and are registered trademarks of Semiconductor Components Industries LLC S2. CILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of d
3. NB4NS40MMNEVB Evaluation Board User s Manual for NB4N840M Description The NB4N840M Evaluation Board was designed to provide a flexible and convenient platform to quickly evaluate characterize and verify the performance and operation of the NB4N840M dual 2 x 2 Crosspoint Switch This user s manual provides detailed information on the board s contents layout and use The manual should be used in conjunction with the NB4N840M data sheet which contains full technical details on device specifications and operation The NB4N840M is a high bandwidth fully differential dual 2 x 2 crosspoint switch with CML inputs outputs that is suitable for applications such as SDH SONET DWDM and high speed switching Fully differential design techniques are used to minimize jitter accumulation crosstalk and signal skew which make this device ideal for loop through and protection channel switching ON Semiconductor hitp onsemi com EVAL BOARD USER S MANUAL applications Each 2 x 2 crosspoint switch can fan out and or multiplex up to 3 2 Gb s data and 2 7 GHz clock signals Internally terminated differential CML inputs accept AC coupled LVPECL Positive ECL or direct coupled CML signals By providing internal 50 input and output termination resistor the need for external components is eliminated and interface reflections are minimized Differential 16 mA CML outputs provide matching internal 50 terminations and 400 mV output
4. irectly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 SA 3 Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2078 D
5. swings when externally terminated 50 Q to Vcc Single ended LVCMOS LVTTL SEL inputs control the routing of the signals through the crosspoint switch which makes this device configurable as 1 2 fan out repeater or 2 x 2 crosspoint switch The device is housed in a low profile 5 x 5 mm 32 pin QFN package Figure 1 NB4N840M Evaluation Board Semiconductor Components Industries LLC 2012 February 2012 Rev 2 Publication Order Number EVBUM2078 D NB4N840MMNEVB Board Features e Fully assembled evaluation board e Accommodates the electrical characterization of the NB4N840M in the QFN32 package e Equal length input and output data lines to minimize skew Selectable jumpers Single 3 3 V supply This Evaluation Board Manual Contains e Information on the NB4N840M Evaluation Board Appropriate Lab Setup Details Evaluation Board Layout e Bill of Materials Setup for Measurements Step 1 Basic Equipment Signal Generator e Oscilloscope Power Supply e Voltmeter e Matched High Speed Cables with SMA Connectors Step 2 Power Supply Connections 3 3 V must be provided to the board for Vcc Table 1 Power Supply Connections Voc J21 ve v v Tn Step 4 Control and Select Pins Power Supply 3 3 V Figure 2 Power Supply Connections Step 3 Input Connections DAn and DBn require CML drive levels and provide internal 50 to Vcc termination resistors to eliminate ex
6. ternal components and minimize reflections Ensure that the CML devices driving these inputs are not redundantly terminated Table 2 Input Connectors Jumpers JP1 JP2 JP5 and JP6 select the input signals for channel A and B outputs Jumpers JP3 JP4 JP7 and JP8 enable the output drivers for channel A and B refer to Table 3 for output routing Table 3 Output Routing ROUTING CONTROLS SELAO SELBO SELAT SELB1 JP6 JP2 JP5 JP1 H OUTPUT CONTROLS ENAO ENA1 ENBO ENB1 JP7 JP8 JP3 JP4 OUTPUT SIGNALS Signal at Signal at QAO QBO QA1 QB1 DAO DBO H DAO DBO MEZUN o T_T T F ss http onsemi com NB4N840MMNEVB J13 DAO ub QAO J12 QAO J11 SELAO JP6 1 110 15 1 16 9 1 Ps SELA1 JP5 7 QB0 6 QBO J5 ENBO JP3 SELBO JP2 1 J8 J1 DB1 02 DBT QBI U7 ENB1 Pa SELB1 JP1 Figure 3 NB4N840M Evaluation Board Connector Configuration Step 5 Output Connections 2 Monitoring CML Outputs vith High Impedance The CML outputs QAn and QBn must be AC coupled Oscilloscope Inputs to a 50 Q termination 100 Q differential load On board a Leave the coupling capacitors in series vvith the 100 862 differential terminations are provided to reduce outputs noise on outputs that are not used Connect the QAn QBn b Make sure the differential load resistors are on all the CML outputs to
7. the oscilloscope with equally matched outputs R9 R12 cables 1 Monitoring One or More CML Outputs with 50 Q Table 4 Output Connectors Oscilloscope Inputs a Leave the coupling capacitors in series with the outputs b Remove the associated 100 Q differential load resistors from the evaluation board on the outputs R9 R12 c It is important to remove the 100 Q resistor on the output monitored otherwise the load impedance will not match the characteristic impedance of the line and the resulting reflections will cause a degradation in the output signal quality d If you are observing a single ended output balance the other half with a 50 Q termination to ground through the AC coupling capacitor http onsemi com 3 NB4N840MMNEVB C3 C23 C24 0 1 uF 0 1 uF 0 1 uF E eau Vec C11 JP8 O O et JP6 0 1 uF C12 J15 LIE O 13 _J14 L R82 R7 lt RES R5 0 1 uF 1kQ 1kQ 1kQS1kQ p JP40 0 1 wr 1 O p NB4N840M JP20 JP10 RIS R2 R3 R4 mov 1 kO 1kO 1kO 1kQ Voc C22 C19 0 1 uF 0 1 uF C30 C27 J19 J20 1 4 0 1 uF 0 1 uF J5 J6 2 2 Figure 4 Evaluation Board Schematic http onsemi com 4 NB4N840MMNEVB Table 5 BILL OF MATERIALS ammo Rte Ref Number Qty Description Notes 1 2 2 C3 24 27 26 0 1 uF 1096 0402 Ceramic Capacitors Kemet C0402C104K4RAC TU C29 C31 L1 er F rm e ei Sr s Scese fume
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