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HMC984LP4E - Analog Devices

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1. BIT TYPE NAME DEFLT DESCRIPTION 19 0 R Measured Phase Error 20 0 Measured duration of the PFD Sign is available in Reg 12h bit O 20 R Phase Error Overflow Flag 1 0 PFD pulse measurement overflow flag Table 18 Reg 12h STATUS Read Only Register BIT TYPE NAME Ww DEFLT DESCRIPTION 0 R Phase Error Sign 1 0 Sign of PFD duration 1 R ro PRESE S For 1 0 Lock Detect result from pulse duration based Lock Detect circuit Measurement 2 R LD Output from Legacy Lock Detect 1 0 Lock Detect result from legacy one shot Lock Detect circuit For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com H gt QD H O LLI H Q D gt e gt O 2 6 LLI LL erittite S HwcosaaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR E NOTES H 0 D or O H O H IT O D or gt gt O 2 O or TE For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com
2. 48 Free Running VCO PN at 1 kHz offset 30 log10 1e3 PNoise normalized to 1 Hz offset 20 log10 7e9 Pnoise normalized to 1 Hz carrier 154 9 dBc Hz at 1 Hz VCO Flicker FOM We can see from Figure 3 and Figure 4 respectively that the PLL FOM floor and FOM flicker parameters in fractional Mode A are approximately Fpo dB 227 dBc Hz at 1 Hz Fp1_dB 267 dBc Hz at 1 Hz Each of the Figure of Merit equations result in straight lines on a log frequency plot We can see in the example below the resulting PLL floor at 7 GHz 2010g10 fvco 10log10 fpd 227 196 9 80 110 1 dBc Hz PLL Flicker at 1 kHz Fi 20logtO fvco 10logtO fm 267 196 9 30 100 1 dBc Hz VCO at 1 MHz Fy gp 20l0g10 fvco 20logtO fm 206 9 196 9 120 130 dBc Hz VCO flicker at 1 KHz gg 20log10 fvco 30log10 fm 154 9 196 9 90 48 dBc Hz These four values help to visualize the main contributors to phase noise in the closed loop PLL Each falls on a linear line on the log frequency phase noise plot shown in Figure 25 Spurious Performance Integer Operation The VCO always operates at an integer multiple of the PD frequency in an integer PLL In general spurious signals originating from an integer PLL can only occur at multiples of the PD frequency These unwanted outputs are often simply referred to as reference sidebands Spurs unrelated to the reference frequency must originate from outside sources
3. O H O LLI H LLI Q QD gt e gt O 2 oc LL erittite nHwcosaaE MICROWAVE CORPORATION v02 0112 RoHS DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY The PD has several features and controls including Phase Swap UP DN Enable Forced Outputs Phase swap The input phase signals to the PD can be swapped internally by writing Reg OSh 4 1 When swapped the PD gain will be reversed This feature enables the HMC984LP4E to be interfaced with reverse polarity VCOs VCOs that have negative gain curve as well as systems that use an active loop filter where the operational amplifier introduces a reverse phase polarity Forced Outputs The UP or DN outputs from the PD can be forced with SPI control to keep constantly active in order to achieve faster lock to force UP write Reg O4h 26 1 to force DN write Reg 04h 27 1 This capability is used in CSP Cycle Slip Prevention feature when large phase errors are detected In such a case the CP is continuously turned on the appropriate direction UP or DN by the internal state machine to force faster phase convergence and thus achieve faster lock Forced otput capability is also useful for testing purposes It can be used to bring the VCO tune control voltage to supply or ground and observe the limits of the VCO Cycle Slip Prevention When the frequency of the synthesizer is changed and the current VCO frequency is far f
4. Use SPI Chip Enable 1 0 Q 1 Ignore CEN and use SPI chip en bit 1 R W SPICE 1 1 Chip enable from SPI 1 allows chip control through SPI software o 2 R W R Divider Enable 1 1 Enable Reference Divider enabled dp 1 PFD enabled 3 R W PFD Enable 1 1 0 PFD disabled LL 4 R W CSP Enable 1 1 Enable cycle slip prevention 5 R W Charge Pump Enable 1 1 Enable Charge Pump gt 6 R W Lock Detect Enable 1 1 Main Lock Detect enable O 7 R W Lock Detect Watch Dog Enable 1 1 Lock Detected Watch Dog Declares unlock if no UP DN pulses are received from PFD 8 R W One Shot Lock Detect Enable d 1 Legacy Lock Detect enable O 1 GPIO output enable DO pin is output Z 9 R W GPO Enable 1 1 LLI 0 DO pin configured as input 5 10 R W Reference Buffer Enable 1 1 Enable Reference Buffer 11 R W Test Clocks Enable jl 1 Enable test clocks to digital Xtal Rdiv Vdiv LLI 12 R W Bias Enable 1 1 Enables the bias currents to the analog blocks 13 R W CSP Output Enable 1 1 Enables the output pad for LL 14 R W CP OP AMP Enable 1 1 Enables the charge pump operational amplifier 17 15 R W Unused bits 3 111b 18 R W VCO Input Test Clock Enable 1 0 Enable for VCO Divider input test clock 19 R W Unused bit 4 0 Table 7 Reg 02h REFDIV Reference Divider Register BIT TYPE NAME W DEFLT DESCRIPTION Reference Divider Division Ratio R Minimum 1 Maximum
5. 1 10 nsec t4 SCK Low Duration 10 nsec t5 SEN Low Duration 20 nsec tg SEN High Duration 20 nsec t7 SCK to SEN 3 8 nsec tg SCK to SDO out IBI 8 nsec 1 The SPI is relatively insensitive to the duty cycle of SCK 2 SEN must rise after the 3219 falling edge of SCK but before the next rising SCK edge If SCK is shared amongst several devices this timing must be respected 3 Typical load to SDO is 10 pF maximum 20 pF For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com erittite nmwcosaaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY Register Map Table 5 Reg 00h Chip ID Soft Reset Read Register H BIT TYPE NAME DEFLT DESCRIPTION gt 6 0 R W Read Address Register 7 0 Address of the register to be read in the next cycle op Soft Reset Writing 1 generates soft reset Resets all the digital 7 R W Soft Reset 1 0 and registers to default states Writing O resumes normal chip dp operation s 31 8 R W Chid ID 24 97331h Part Number Description Read regOOh returns chip ID Table 6 Reg 01h Enable Register W DEFLT DESCRIPTION H 0 Use CEN pin for chip enable 0 R W
6. 13 0 R W R Divider Ratio 14 1 16383d For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com H gt D O H O LLI H LLI Q QD gt e gt O 2 6 LLI oc LL E Hittite MICROWAVE CORPORATION 02 0112 RoHS v EARTH FRIENDLY Table 8 Reg 03h PFD Settings Register HMC984LP4E DIGITAL PHASE FREQUENCY DETECTOR BIT TYPE NAME W DEFLT DESCRIPTION 2 0 R W CSP Reset Delay 3 100b The number of reference clock cycles after which the saturation detection is reset 3 R W CSP Auto Disable 1 1 When 1 PD saturation is disabled when Lock Detect becomes 1 4 R W PD Phase Swap 1 0 Swap PD inputs when 1 1 Apply reference to both PFD inputs when pfd swap phase 5 R W PD Short Mode Enable 1 0 RegO8h 4 0 or applies Divider output to both PFD inputs when pfd swap phase RegO08h 4 1 1 Enable UP output from PD 6 R W PD Up enable 1 0 Disable UP output from PD 1 Enable DN output from PD Ui BU 1 1 0 Disable DN output from PD 8 R W PD Force Up 1 0 1 Forces UP output from the PD to stay continuously on 0 Normal UP operation 9 R W PD Force Down 1 0 1 Forces DN output from the PD to stay contin
7. 2 5mA max 7 SpA cp_offset_up_en 127 20uA steps Steps 635uA max Loop Filter DN DN DN Offset cp_DNmag_x20uA cp_offsemag_x5uA 2 5mA max 7 7 SpA cp_offset_up_en 127 20uA steps Steps 635uA max Figure 31 Charge Pump Block Diagram PFD Jitter and Lock Detect Background In normal phase locked operation the divided VCO signal arrives at the phase detector in phase with the divided crystal signal known as the reference signal Despite the fact that the device is in lock the phase of the VCO signal and the reference signal vary in time due to the phase noise of the crystal and VCO oscillators the loop bandwidth used and the presence of fractional modulation or not The total integrated noise on the VCO path normally dominates the variations in the two arrival times at the phase detector if fractional modulation is turned off To determine weather the VCO is in lock or not it is necessary to distinguish between normal phase jitter when in lock and phase jitter when not in lock First the meaning of jitter of the synthesizer that is observed at the phase detector in integer or fractional modes needs to be understood The standard deviation of the arrival time of the VCO signal or the jitter in integer mode may be estimated with a simple approximation if it is assumed that the locked VCO has a constant phase noise 2 f0 at offsets less than the loop 3 dB bandwidth and a 20 dB per decade roll off at greater offsets The si
8. 360 28 8 degrees or 163 5 2000 pA 20 ns 1 6 ns phase offset at the PD input Charge Pump High Gain HiK Mode Operating the CP of the HMC984LP4E in High Gain mode Reg 04h 23 1 can improve PLL phase noise performance by up to 3 dB In High Gain mode the charge pump can deliver current of 3 5 mA normal programmed CP current High gain mode can be used without the normal charge pump current in which case the loop filter should be designed with a current of 3 5 mA In the case where high gain mode is used with the normal CP current the loop filter should be designed with a charge pump current of 3 5 mA programmed CP current The high gain mode current is depended on the loop filter voltage therefore the high gain mode should be used with active loop filters to keep a constant voltage a the charge pump output For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com H gt QD O H O LLI H LLI Q QD LLI gt e gt O 2 6 LLI LL H gt N as O H O LLI H LLI Q QD gt e gt O 2 6 LLI oc LL erittite HwcosaaE MICROWAVE CORPORATION v02 0112 ROHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY UP Offset cp_UPmag_x20uA cp_offsemag_x5uA
9. 5 r1 EARTH FRIENDLY HMC984LP4E DIGITAL PHASE FREQUENCY DETECTOR Table 14 Reg 09h REFDIVSET Reference Divider Settings Register BIT TYPE NAME Ww DEFLT DESCRIPTION 2 0 R W HMC983LP5E Chip Address 001 Chip address of the Prescaler Divider HMC983LP5E When a new REFDIV value is selected through the SPI either of the two chips will take the same command This makes it unnecessary to issue two separate WRITE cycles to change the REFDIV value To disable this feature write the chip address of the HMC984LP4E itself so that it will not listen to the command issued to the other chip See Chip Address Pins on page 25 for more information R W Force R Divider to Bypass Table 15 Reg 0Ah Spare Register 1 Force REFDIV bypass when RDIV is not equal to 1 BIT TYPE NAME Ww DEFLT DESCRIPTION 9 0 R W Not used 10 3FFh 10 R W XtalDisSat 1 0 Disables saturation protection on reference Xtal buffer 11 R W XtalHighFreq 1 0 Extends bandwidth of the reference buffer Table 16 Reg 10h MEAS REF Read Only Register BIT DEFLT DESCRIPTION 19 0 R Measured Reference Duration 20 0 Measured duration of the reference period for Lock Detect calibration 20 R Reference Measure Overflow Flag 1 0 REF measurement overflow flag Table 17 Reg 11h MEAS PFD Read Only Register
10. AVG VCO PHASE OFFSET lt gt 0 2 AVG VCO PHASE OFFSET 22 FRACTIONAL MODE FRACTIONAL MODE Figure 34 Lock Detect Window Fractional Mode with Offset Lock Detect with Phase Measurement Lock Detect with Phase Measurement is based on phase error measurement at the PFD output The phase error measurement is done in terms of the reference period at the PFD input The period of the reference is first measured with a delay line and this count is available in read only register Reg 10h The phase error at the output of the PFD is then measured with the same delay line and this count is available in the read only register Reg 11h When the PLL is not locked the measured phase error count will vary every time the Reg 11h is read and will become a stable value once PLL is locked The phase error count will then be proportional to the static phase error at the PFD output For example assuming that PLL is locked if the reference duration count is 150 in Reg 10h and Reg 11h reads 35 then the approximate static phase error at the PFD output is 20 35 150 4 7 ns assuming a 20 ns reference period or Fpfd of 50 MHz Reg 06h 13 0 defines the low and high thresholds for current phase error count Reg 06h 23 14 defines the number of reference cycles that the phase error has to be within the thresholds before the lock is declared For example if the low threshold is set to Reg 06h 6 0 20d and high threshold is set to Reg 06h 13 7 50d and the LD OK Count i
11. EARTH FRIENDLY Table 2 Pin Descriptions Continued Pin Number Function Description Interface Schematic H DVDD 19 SENb Serial Port Enable Input Pin Active Low SEND SD o4 20 SDI Serial Port Data Input Pin SCLK 21 SCLK Serial Data Clock Input Pin LL DYDD O 4 4 i CHIP3 o 22 CHIP3 Chip Address Bit 3 gt c PVDD 2 23 UPSAT Reference Saturation Output 4 O UPSAT O DVDD VCO Saturation Output Fla 24 DNSAT t t O DNSAT Also Multiplexed with Crystal Oscillator Clock For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com erttite HwcosaeaE MICROWAVE CORPORATION v02 0112 ROHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY Table 19 Absolute Maximum Ratings Max VDC to Paddle on Supply Pins 6 0 3 0 3 6 V Reflow Soldering 7 11 13 16 Peak Temperature 260 C VCCPD VPPCP VDDCP 0 3 to 45 5 V Time IN 405 VCOp VCOn Common Mode Voltage VCCPD 1 4 V eee ey Class 1B XREFP 50 Source 12 dBm Digital Input Voltage Range 0 25 to DVDD 0 5 V Stresses above those listed under Absolute Maximum Ratings may Digital Load 1
12. External spurious sources can modulate the VCO indirectly through power supplies ground or output ports or bypass the loop filter due to poor isolation of the filter It can also simply add to the output of the PLL The HMC984LP4E together with the HMC983LP5E have been designed and tested for ultra low spurious performance Reference spurious levels can be typically below 100 dBc with a well designed board layout A regulator with low noise and high power supply rejection such as the HMC860LP3E is recommended to minimize external spurious sources Reference spurious levels of below 100 dBc require superb board isolation of power supplies isolation of the VCO from the digital switching of the synthesizer and isolation of the VCO load from the PLL Typical board layout regulator design demo boards and application information are available for very low spurious operation Operation with lower levels of isolation in the application circuit board from those recommended by Hittite can result in higher spurious levels For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com CATHIE mHwcosaaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY Of course if the application environment contains other interfering frequencies unrelate
13. Minimum cause permanent damage to the device This is stress rating only functional operation of the device at these or any other conditions Range above those indicated in the operational section of this specification Operating Temperature Range 65 to 125 C is not implied Exposure to absolute maximum rating conditions for Maximum Junction Temperature 125 C extended periods may affect device reliability Storage Temperature 65 to 125 C Thermal Resistance Rth ELECTROSTATIC SENSITIVE DEVICE junction to ground paddle OBSERVE HANDLING PRECAUTIONS Outline Drawing H gt QD O H O LLI H LLI Q QD LLI gt e gt O 2 6 LL TOP VIEW BOTTOM VIEW 161 38 PIN 24 016 0 40 REF 193 5490 s 638 1 008 0 20 MIN 24 19 U U 1 18 tow ae PN r 34 mm cox 4984 amp 1 oti 022 0 56 00 94 Zia 917 0 44 oN EX E tS Te 6 13 7 K ST EXPOSED 12 N Lor NUMBER 116 28 BROUND 104 2 65 5 SQUARE 002 0 05 000 938 ge PACKAGE BODY MATERIAL LOW STRESS INJEC
14. PLL Performance at 7000 01 MHz 41 60 Bol jii 100 _ 120 140 PHASE NOISE dBc Hz 160 _ 180 Let 0 10 10 10 10 10 107 10 OFFSET FREQUENCY Hz Figure 8 HMC984LP4E amp HMC983LP5E PLL Floor vs CP Current 2 218 FLOOR FOM dBc Hz 0 5 0 75 1 1 25 1 5 1 75 2 2 25 2 5 CHARGE PUMP CURRENT mA Figure 10 HMC984LP4E amp HMC983LP5E PLL Floor FOM vs CP Voltage 131 195 200 205 210 215 220 FLOOR FOM dBc Hz 225 Imager Mode Hi K Integer Mode CHARGE PUMP VOLTAGE V Figure 12 HMC984LP4E amp HMC983LP5E PLL Performance at 4100 01 MHz 51 60 100 7 120 140 PHASE NOISE dBc Hz 160 10 10 10 10 10 107 10 OFFSET FREQUENCY Hz 2 PLL operated in Mode B CP Votage 2 5 V Active Loop Filter with 220 kHz bandwidth used 3 Charge Pump Current 2 5 mA 4 Crystal frequency 100MHz PD frequency 50MHz CP current 2 5mA CP offset current 255 yA Loop bandwidth 87 kHz PLL in Mode B 5 Reference frequency 100 MHz PD frequency 50 MHz current 2 5 mA CP offset current 280 pA Loop bandwidth 87 kHz PLL in Mode B For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com H gt D
15. as O H O LLI H Q D gt e gt O 2 6 LLI LL H gt D as O H O LLI H LLI Q D gt e gt O 2 oc LL E Hittite MICROWAVE CORPORATION v02 0112 RoHS v r1 EARTH FRIENDLY Figure 13 HMC984LP4E amp HMC983LP5E PLL Performance at 2100 01 MHz 61 60 80 Er Lua 120 140 PHASE NOISE dBc Hz 160 180 La is 10 10 10 10 10 107 10 OFFSET FREQUENCY Hz Figure 15 HMC984LP4E amp HMC983LP5E PLL In Band Fractional Spurs vs Offset Current 81 20 20 4400 MHz 4700 MHz 5000 MHz INBAND SPUR AT 15 kHz OFFSET dBc Hz zH 98P 3SION 3S vHd 800 600 400 200 0 200 400 600 800 OFFSET CURRENT mA Figure 17 HMC984LP4E amp HMC983LP5E PLL Flicker FOM vs RF Input Power 264 5 265 __ 265 5 266 266 5 267 FLICKER FOM dBc Hz Hi K Integer Mode 267 5 268 E Integer Mode 268 5 30 25 20 15 10 5 0 5 10 RF INPUT POWER dBm HMC984LP4E DIGITAL PHASE FREQUENCY DETECTOR Figure 14 HMC984LP4E amp HMC983LP5E 16 80 100 _ I TT 8 Calculated PLL Integer Mode g 120 sa ul 7 Q Measured Mode B 140 9 porre Simulated Mode 160 Simulated Integer Mode i Measured Integer Mode 8 180 TEN MENTIS LL 10 10 10 10 10 107 10 OFFSET
16. 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com erittite nHwcosaeaE MICROWAVE CORPORATION v02 0112 ROHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY 3 HMC984LP4E registers the data bits D29 DO in the next 29 rising edges of SCK total of 30 data bits 4 Host places the 7 register address bits A6 A0 on the next 7 falling edges of SCK MSB to LSB while the HMC984LP4E reads the address bits on the corresponding rising edge of SCK 5 Host places the chip address bits CA2 CA0 110 on the next falling edges of SCK MSB to LSB Note the HMC984LP4E chip address is fixed as 4d or 100b 6 SEN goes from low to high after the 40th rising edge of SCK This completes the WRITE cycle 7 HMC984LP4E also exports data back on the SDO line For details see the section on READ operation Serial Port READ Operation The SPI can read from the internal registers in the chip The data is available on SDO pin This pin itself is tri stated when the device is not being addressed However when the device is active and has been addressed by the SPI master the HMC984LP4E controls the SDO pin and exports data on this pin during the next SPI cycle HMC984LP4E changes the data to the host on the rising edge of SCK and the host reads the data from HMC984LP4E on the falling edge A typical READ cycle is shown in Figure 1 Read cyc
17. the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown unless mentioned otherwise A sufficient number of via holes should be used to connect the top and bottom ground planes The evaluation circuit board shown is available from Hittite upon request Table 20 Evaluation Order Information Item Contents Part Number HMC984LP4E and HMC983LP5E PLL Chipset Evaluation PCB USB Interface Board Evaluation Kit 6 USB A Male to USB B Female Cable EKITO1 HMC983LP5E CD ROM Contains User Manual Evaluation PCB Schematic Evaluation Software For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com erittite nwcosaaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY Evaluation PCB Block Diagram Optional DIV_OUT IN To USB Board III Iii 232 AMA 7 _ Typical Power Optional Internal VCO Addam HMC984LP4E Externa Ref M RF Divider PFD npu J28 i STAD Det 44 Configura Optio Vtune Out lt 4 Configura ANN 44 Control J5 III I AAA H it t it For details on optional Passive LPF Active LPF 600 00253 00 1 configurations See use RF 2 RF 4
18. vs Phase Difference in Amps radians The UP and DOWN gain currents are configured in Reg 04h 6 0 Reg 04h 13 7 respectively Both UP and DOWN currents can be programmed to provide up to 2 5 mA independently 127 steps 20 p A step Resulting phase detector gain is the total current from one side divided by 2rr For example if both UP and DOWN currents are set 2 mA each the gain would be 2 mA 2r 318 31 pA radian Typically both of the gain currents are set to the same value Charge Pump Phase Offset Either of the UP or DOWN charge pumps may have a DC offset current added to it Offset current allows the phase detector to operate with a phase offset between the reference and the divided VCO inputs The phase offset is proportional to the ratio of the offset current to the main current times the period of the phase comparison clock PD Phase offset A 5 CP Current fp It is recommended to operate the HMC984LP4E with a phase offset when using fractional mode to reduce non linear effects from any UP and DN pump mismatches that may exist Phase noise in fractional mode is strongly affected by charge pump offset The magnitude of offset current is set in Reg 04h 20 14 and can be added to the UP Reg 04h 21 1 or DOWN Reg 04122 1 pumps As an example if the main pump gain was set at 2 mA an offset of 160 pA Reg 04h 20 14 20h and 50 MHz PFD rate would represent a phase offset of about 160 2000
19. 2 Measured with 100 external termination AC coupled on HMC984LP4E amp HMC983LP5E evaluation board 13 Measured with HMC983LP5E HMC984LPAE chip set as fractional N synthesizer Crystal input frequency 100 MHz CP current 2 5 mA CP offset current 245 uA Loop filter bandwidth 87 KHz DSM Mode B selected Cycle Slip Prevention CSP is disabled in HUC984LP4E by setting Reg 01h 4 0 Setting Reg 01h 4 1 enables CSP in the two chip PLL For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com H gt QD as O H O LLI H Q D gt e gt O 2 6 LLI LL erittite nwcosaaE MICROWAVE CORPORATION v02 0112 ROHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY Table 2 Pin Descriptions Pin Number Function Description Interface Schematic H o VOD 1 1 REF EN Gate control output for TCXO clock export REF_EN H OE H gt LD DO LLI 2 DTSTO Lock Detect GPIO bit 0 VCCPD C gt 50 ee 3 VCOp Positive Input Pin for PFD JN esp Q VCOp L gt Z ESD 2 N VCCPD so 4 VCOn Negative Input Pin for PFD RED LL VCOn EN BN N ESD PADDLE GND 5 VCCPD 5 V Analog Supply for Differential PFD 6 7 VDD
20. 4LP4E amp HMC983LP5E PLL Floor FOM vs Frequency 111 226 227 Mode B 228 i i Hi K Mode 229 i Hi K Mode A 230 e Ss Integer Mode FLICKER FOM dBc Hz 231 232 Hi K Integer Mode FREQUENCY GHz Figure 6 HMC984LP4E amp HMC983LP5E PLL Floor vs Reference Power 1 225 226 227 228 229 Hi K Mode B 230 FLOOR FOM dBc Hz 231 Integer Mode 232 Hi K Integer Mode 15 10 5 0 5 10 15 REFERENCE POWER dBm 1 Crystal frequency 100 MHz PFD frequency 50 MHz Active Loop Filter with 220 KHz Bandwidth Measured at 4101 MHz in fractional mode and 4100 MHz in integer mode For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com EJ Hittite MICROWAVE CORPORATION v02 0112 HMC984LP4E RoHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY Figure 7 HMC984LP4E amp HMC983LP5E PLL Flicker FOM vs CP Current 2 FLICKER FOM dBc Hz 0 5 0 75 1 1 25 1 5 1 75 2 2 25 2 5 CHARGE PUMP CURRENT mA Figure 9 HMC984LP4E amp HMC983LP5E PLL Flicker FOM vs CP Voltage 131 230 235 240 245 250 255 FLICKER FOM dBc Hz 260 265 CHARGE PUMP VOLTAGE V Figure 11 HMC984LP4E amp HMC983LP5E
21. 5 C AVDD RVDD VDDPD1 VDDPD2 DVDD 3 V VCCPD VPPCP VDDCP 5 V GND 0 V Parameter Conditions Min Typ Max Units 1 5 Integer Boundary Spurs Fpd 50 MHz 85 dBc Logic Inputs VIH Input High Voltage DVDD 0 4 VIL Input Low Voltage 0 4 Logic Outputs VOH Output High Voltage DVDD 0 4 VOL Output Low Voltage 0 4 DC Load 1 5 mA Serial Port Serial Port Clock Frequency 30 MHz Power Supplies AVDD RVDD Analog Supplies AVDD should equal 28 3 33 v DVDD VCCPD 5 V Analog Supply for PD 4 5 5 5 5 V VPPCP CP Analog Supply 4 5 5 5 5 V VDDCP CP Digital Supply 4 5 5 5 5 V DVDD VDDPD1 VDDPD2 Digital Supplies 2 8 3 3 8 V Current Consumption IDD Total Current Consumption 123 6 mA I AVDD 3 V AVDD Current 4 8 mA I RVDD 3 V Reference Path Current 22 mA I VCCPD 5 V PD Current 83 5 mA I VDDPD 1 3 V PD Digital Supply Current 2 7 mA I VDDPD2 3 V PD Digital Supply Current 2 7 mA I VPPCP 5 V CP Analog Supply Current 3 mA I VDDCP 5 V CP Digital Supply Current 2 9 mA I DVDD 3 V Total DVDD Current 2 mA Bias Reference Voltage Measured with 10 GO Volt Meter 1 58 1 72 1 86 V 2 Bias voltage cannot drive external load It must be measured with a 10 GO voltmeter such as Agilent 34410A A typical 10 MO Digital Volt Meter will read erroneously For price delivery and to place orders Hittite Microwave Corporation 2 E
22. ANALOG Mittite DEVICES MICROWAVE PRODUCTS FROM ANALOG DEVICES Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED www analog com www hittite com THIS PAGE INTENTIONALLY LEFT BLANK H gt D O H O LLI H LLI Q QD gt e gt O 2 6 LLI oc LL E Hittite MICROWAVE CORPORATION v02 0112 RoHS v EARTH FRIENDLY Typical Applications The HMC984LP4E is suitable for Test Equipment Portable Instruments HMC984LP4E DIGITAL PHASE FREQUENCY DETECTOR High Performance Fractional N Frequency Synthesizers with Ultra Low Spurious Emissions Military Functional Diagram e kb V x lt pu 4 N z z a T a D e 2 N 24 23 122 21 20 19 i bor iy REFEN 1 N 18 SDO DATA REGISTER AND SPI DTSTO 2 le 17 CEN VCOp i 16 DVDD bt R VCOn 4 15 VCCPD 5 RC 14 XREFP L CP VDDPD1 6 13 RVDD 7 8 9 ho 11 D e 5 a o PACKAGE 5 8 m LSS gt gt GND Features Ultra Low Noise 231 dBc Hz FOM Integer Mode 227 dBc Hz FOM Fractional Mode Ultra Low Spurious Emissions Less Than 60 dBc Fractional Spurious Differential P
23. E pump Gain OP Duron a Ms CP HiK See Charge Pump High Gain HiK 3 5 6 mA Mode section Offset Current 7 bit Programmable 5 uA Step 5 635 Phase noise 1 Integer Mode 230 dBc Hz Fractional Modes A amp B 227 dBc Hz Floor Figure of Merit FOM HiK Integer Mode 232 dBc Hz HiK Fractional Mode A 230 dBc Hz HiK Fractional Mode B 229 dBc Hz Integer Mode 269 dBc Hz Fractional Modes A amp B 267 dBc Hz Flicker Figure of Merit FOM HiK Integer Mode 268 dBc Hz HiK Fractional Mode A 266 dBc Hz HiK Fractional Mode B 266 dBc Hz Spurious Int B d s 21GH Frequency offsets less than loop band 60 BB dBc nteger Boundar urs z Ven width Fpp 50 MHz Mode A Int B d s 21GH Frequency offsets less than loop band 70 5 dBc nteger Boundar urs z width Fpp 50 MHz Mode 1 2 Integer Boundary Spurs Fpp 50 MHz 75 70 dBc 1 3 Integer Boundary Spurs Fpp 50 MHz 85 80 dBc 1 Measured with HMC983LP5E HMC984LP4E as fractional N synthesizer chip set For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com E Hittite MICROWAVE CORPORATION v02 0112 RoHSv EARTH FRIENDLY HMC984LP4E DIGITAL PHASE FREQUENCY DETECTOR Table 1 Electrical Specifications Continued 2
24. EARTH FRIENDLY where p Phase Noise Contribution of the PLL 2 2 fo Frequency of the VCO Hz fpa Frequency of the Phase Detector Hz fm Frequency offset from the carrier Hz Foo Figure of Merit FOM for the phase noise floor Fpi Figure of Merit FOM for the flicker noise region PLL 1 f Flicker Noise VCO 1 12 Noise ae 1 f4 Noise o am 0 Typical Closed Loop 9 PLL Noise Floor Phase Noise lt Closed Loop germ a Bandwidth LOG OFFSET FREQUENCY fm Figure 26 Figure of Merit Noise Models for the PLL If the free running phase noise of the VCO is known it may also be represented by a figure of merit for both 1 f2 Fys and the 1 3 Fy regions VCO PHASE 5 NOISE D hfn LT NT Eq 2 in fa The Figures of Merit are essentially normalized noise parameters for both the PLL and VCO that can allow quick estimates of the performance levels of the PLL at the required VCO offset and phase detector frequency Normally the PLL IC noise dominates inside the closed loop bandwidth of the synthesizer and the VCO dominates outside the loop bandwidth at offsets far from the carrier Hence a quick estimate of the closed loop performance of the PLL can be made by setting the loop bandwidth equal to the frequency where the PLL and free running phase noise are equal The Figure of Merit is also useful in estimating the noise parameters to be entered into a closed loop design tool such
25. FREQUENCY Hz Figure 16 9841 amp HMC983LP5E PLL Floor FOM vs RF Input Power 226 FLOOR FOM dBc Hz N N Integer P 30 25 20 15 10 5 0 5 10 RF INPUT POWER dBm Figure 18 HMC984LP4E amp HMC983LP5E PLL Two Way Auto Frequency Sweep 19 7000 6900 6800 o E o o FREQUENCY MHz o o o a o o 0 5 10 15 20 TIME ms 6 Crystal frequency 100 MHz PFD frequency 50 MHz CP current 2 5 mA CP offset current 280 Loop bandwidth 87 kHz PLL Mode 7 Measured at 7 GHz in Integer Mode and 7 001 GHz in Fractional mode B PD Frequency 50 MHz and loop filter BW 87 kHz Simulated results were obtained using Hittite PLL Design software 8 Active Loop filter bandwidth 150 kHz measured at 10 kHz offset PFD Frequency 50 MHz Offset polarity should be positive for inverting configurations and negative otherwise 9 50 MHz PFD For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com E Hittite MICROWAVE CORPORATION v02 0112 RoHS v E Figure 19 HVC984LP4E amp HMC983LP5E PLL One Way Triggered Frequency Sweep 107 7000 6900 6800 6700 6600 FREQUENCY MHz 6500 6400 0 200 400 600 800 1000 TI
26. Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com CAHMEIC HwcosaaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR r1 EARTH FRIENDLY The HMC984LP4E has two outputs UPSAT and DNSAT which indicate to the HMC983LP5E whether the Reference or the VCO is leading in phase These outputs are CMOS signal with DVDD levels When HMC983LP5E detects saturation large phase error it configures itself and the HMC984LP4E in order to eliminate or reduce cycle clipping There are additional controls for adjusting the CSP operation in HMC983LP5E The controls for CSP feature are 1 Register OEh bits 18 15 control the step size where step is a VCO cycle 2 Register OEh bit 29 increases the step size by a factor of 16 for operations with low reference frequencies The actual operation of CSP will depend on the Reference and VCO frequencies and will need to be tailored for each application Charge Pump The charge pump in HMC984LP4E converts the phase detector digital outputs to appropriate current level that is proportional to phase difference between the reference and the VCO A simplified block diagram of the charge pump is shown in Figure 25 The HMC984LP4E CP has programmable current gain and offset current Charge Pump Gain Current CP gain current defines the gain of Phase Detector
27. ME ms Figure 21 HMC984LP4E amp HMC983LP5E PLL Floor Vs Square Wave Ref Input Level 111 216 218 220 222 224 FLOOR FOM dBc Hz 226 REFERENCE POWER dBm Figure 23 HMC984LP4E amp HMC983LP5E PLL Cycle Slip Prevention at 100 MHz PD 7050 CSP Enabled RegOEh 18 15 1h gt E o e o CSP Enabled 6950 RegoEh 18 15 8h 6900 6850 6800 PLL OUTPUT FREQUENCY MHz 6750 6700 0 50 100 150 200 250 300 TIME us HMC984LP4E DIGITAL PHASE FREQUENCY DETECTOR Figure 20 HMC984LP4E amp HMC983LP5E PLL Floor Vs Sine Wave Ref Input Level 111 210 FLOOR FOM dBc Hz REFERENCE POWER dBm Figure 22 HMC984LP4E amp HMC983LP5E PLL Reference Input Return Loss 12 RETURN LOSS dB 0 100 200 300 400 500 600 FREQUENCY MHz Figure 24 HMC984LP4E amp HMC983LP5E PLL Cycle Slip Prevention at 50 MHz PD 3 7050 CSP Enabled RegOEh 18 15 8h 7000 CSP Enabled 6950 RegOEh 18 15 1h 6900 6850 6800 PLL OUTPUT FREQUENCY GHz 6750 6700 0 50 100 150 200 250 300 TIME us 10 Using 10 Hz external trigger PFD frequency 10 MHz Measured with HMC983LP5E HMC984LP4E fractional N synthesizer chip set 11 Measured with a 100 external resistor termination resulting in 50 effective input impedance of Reference Full FOM performance up to maximum 3 3 Vpp input voltage 1
28. Out guide TT HMC507 12 14 AA On board VCO F ister Supply POWER Optional amp Regulators J27 Jm H gt QD oc O H O LLI H Q D gt e gt O 2 6 oc LL For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com H gt D O H O LLI H LLI Q QD gt e gt O 2 6 LLI oc LL erttite HwcosaaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY Typical Performance Characteristics Theory of Operation Primary target application of the HMC984LP4E is to be used with the HMC983LP5E as shown in Figure 25 Together these two components form a high performance low noise ultra low spurious emissions fractional N frequency synthesizer The two components are separated in order to maximize isolation between them and minimize common distortion and modulation by products that exist in all PLLs Careful IC design and increased isolation between the two components result in high performance high spectral efficiency PLL with extremely low spurious emissions HMC984LP4E Loop Filter 9 reference Ph source ase N fvco N fpd Detector N amp De
29. PD1 VDDPD2 3V Phase Detector Supply 1 3 V Phase Detector Supply 2 8 VDDCP 5 V Charge Pump Supply For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com EJ Hittite MICROWAVE CORPORATION v02 0112 RoHS v EARTH FRIENDLY HMC984LP4E DIGITAL PHASE FREQUENCY DETECTOR Table 2 Pin Descriptions Continued Pin Number Function Description Interface Schematic VPPCP UP M ESD o ihe 9 Charge Pump Output Pin ERA dp A ESD 10 VPPCP 5 V Analog Power Supply Pin Charge Pump 11 AVDD 3 V Analog Supply LLI 12 BIAS External Decoupling for Analog Bias Circuits Q 13 RVDD 3 V Supply Pin for Reference Circuits RVDD 14 XREFP Reference TCXO Input Pin 15 NC No Connect Pin Z 16 DVDD 3 V Digital Supply Pin DVDD 2 17 CEN Chip Enable Pin CEN LL o PVDD 18 SDO Serial Data Output Pin ane For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR
30. TH JITTER PHASE JITTER PHASE JITTER AVG PHASE orrset 0 AVG PHASE OFFSET 0 3 INTEGER MODE INTEGER MODE Figure 33 Normal Lock Detect Window Integer Mode Zero Offset Lock Detect with Phase Offset When operating in fractional mode the linearity of the phase detector and charge pump is more critical than in integer mode The phase detector linearity deteriorates when operating with zero phase offset Hence in fractional mode it is necessary to offset the phase of the reference and the VCO at the phase detector In such a case for example with an offset delay the mean phase of the VCO will always occur after the reference as shown in Figure 10 The lock detect circuit window can be made more selective with a fixed offset delay by setting Reg 05h 0 1 and Reg O5h 1 1 The offset can be assigned in advance of the reference by setting Reg 05h 1 20 and Reg 05h 0 1 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com Crittite HwcosaeaE MICROWAVE CORPORATION v02 0112 RoHS DIGITAL PHASE FREQUENCY DETECTOR E EARTH FRIENDLY T 10nsec AVG PHASE OFFSET WINDOW LOCK DETECT WINDOW SOMHz PFD VCO AT PFD WITH FRAC JITTER REF PHASE ARRIVAL _ REF PHASE ARRIVAL ll ARRIVAL DISTRIBUTION AT
31. TION MOLDED PLASTIC n o SEATING SILICA AND SILICON IMPREGNATED E NONE 2 LEAD AND GROUND PADDLE MATERIAL COPPER ALLOY 3 LEAD AND GROUND PADDLE PLATING 100 MATTE TIN C 003 0 08 C 4 DIMENSIONS ARE IN INCHES MILLIMETERS C 5 LEAD SPACING TOLERANCE IS NON CUMULATIVE 6 PAD BURR LENGTH SHALL BE 0 15mm MAX PAD BURR HEIGHT SHALL BE 0 25m MAX 7 PACKAGE WARP SHALL NOT EXCEED 0 05mm 8 ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND 9 REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN Package Information Part Number Package Body Material Lead Finish MSL Rating 21 Package Marking HMC984LP4E RoHS compliant Low Stress Injection Molded Plastic 100 matte Sn MSL1 ma 1 4 Digit lot number XXXX 2 Max peak reflow temperature of 260 C For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com erittite nHwcosaaE MICROWAVE CORPORATION v02 0112 ROHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY Evaluation PCB BS 200000 20000 00000 H 0 D or e H O H IT O D or T gt gt O z O TE The circuit board used in the application should use RF circuit design techniques Signal lines should have 50 Ohms impedance while
32. as Hittite PLL Design which can give a more accurate estimate of the closed loop phase noise and PLL loop filter component values Given an optimum loop design the approximate closed loop performance is simply given by the minimum of the PLL and VCO noise contributions o min 45 7 Eq 3 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com H gt QD O H O LLI H LLI Q QD LLI gt e gt O 2 LL H gt D O H O LLI H LLI Q QD gt e gt O 2 6 LLI oc LL erittite nwcosaaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY An example of the use of the FOM values to make a quick estimate of PLL performance Estimate the phase noise of an 7 GHz closed loop PLL with a 100 MHz reference operating in Fractional Mode B with the VCO operating at 7 GHz Assume an HMC505LP4E VCO has free running phase noise in the 1 f region at 1 MHz offset of 130 dBc Hz and phase noise in the 1 f3 region at 1 kHz offset of 48 dBc Hz Fu 130 Free Running VCO PN at 1 MHz offset 20 log10 1e6 PNoise normalized to 1 Hz offset 20 log10 7e9 PNoise normalized to 1 Hz carrier 206 9 dBc Hz at 1 Hz VCO FOM
33. ctor of 20Log10 N after division to the reference the jitter is a constant The rms jitter from the phase noise is then given by Toi Tref 2m In this example if the reference was 50 MHz 20 nsec and hence 178 femto sec A normal 3 sigma peak to peak variation in the arrival time therefore would be 34277 0 756 ps If the synthesizer was in fractional mode the fractional modulation of the VCO divider will dominate the jitter The exact standard deviation of the divided VCO signal will vary based upon the modulator chosen however a typical modulator will vary by about 3 VCO periods 4 VCO periods worst case If for example a nominal VCO at 5 GHz is divided by 100 to equal the reference at 50 MHz then the worst case division ratios will vary by 100x4 Hence the peak variation in the arrival times caused by modulation of the fractional synthesizer at the reference will be Tj xpk max N min 2 Eq 8 In this example 200 ps 104 96 2 800 psec If it is assumed that the distribution of the delta sigma modulation is approximately Gaussian T pk could be approximated as a 3 sigma jitter and hence the rms jitter of the gt modulator could be estimated as 1 8 of or 267 psec in this example Hence the total rms jitter T expected from the delta sigma modulation plus the phase noise of the VCO would be given by the rms sum where Tj T jon y Eq 9 It is apparent that th
34. d to the PD frequency and if the application isolation from the board layout and regulation are insufficient then the unwanted interfering frequencies will mix with the desired PLL output and cause additional spurs The level of these spurs is dependant upon isolation and supply regulation or rejection PSRR Fractional Operation Unlike an integer PLL spurious signals in a fractional PLL can occur due to the fact that the VCO operates at frequencies unrelated to the PD frequency Hence intermodulation of the VCO and the PD harmonics can cause spurious sidebands Spurious emissions are largest when the VCO operates very close to an integer multiple of the PD When the VCO operates exactly at a harmonic of the PD then no in close mixing products are present Interference is always present at multiples of the PD frequency fpa and the VCO frequency If the fractional mode of operation is used the difference A between the VCO frequency and the nearest harmonic of the reference will create what are referred to as integer boundary spurs Depending upon the mode of operation of the PLL higher order lower power spurs may also occur at multiples of integer fractions sub harmonics of the PD frequency That is fractional VCO frequencies which are near n fpa fpg d m where n d and m are all integers and d lt m mathematicians refer to d m as a rational number We will refer to f yd m as an integer fraction The denominator m is the orde
35. e HMC984LPAE is housed in a compact 24 pin 4x4 mm LP4 package For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com erittite HwcosaaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY Table 1 Electrical Specifications 25 C AVDD RVDD VDDPD1 VDDPD2 DVDD 3 V VCCPD VPPCP VDDCP 5 V GND 0V Parameter Conditions Min Typ Max Units Ref Input Characteristics Frequency Range DC 50 350 MHz Ref Input Power Range 50 Q Source 6 12 dBm Ref Input Impedance 100113 Ref Divider Range 14 bit 1 16383 Phase Detector PD PD Input Internal Pull Up Resistance VCOp VCOn Each Side 50 Q PD Input Current VCOp VCOn 2 5 mA Steps 12 5 15 17 5 mA PD Input Voltage Swing Single Ended Peak to Peak 625 750 875 mV Fractional Mode H gt D O H O LLI H LLI Q QD gt e gt O 2 6 LLI oc LL 12 dBm Sine Wave Input Mode A amp B DC 50 125 MHz Phase Detector Frequency 2 dBm Square Wave Input Mode A amp B DC 50 90 MHz Integer Mode 12 dBm Sine Wave Input DC 50 175 MHz Phase Detector Frequency 2 dBm Square Wave Input DC 50 150 MHz Charge Pump CP erate aCe S
36. e jitter from EQ 9 at the phase detector is dominated by the fractional modulation In general t x0 8 nsec of normal variation in the phase detector arrival times has to be expected when in fractional mode In addition lower VCO frequencies with high reference frequencies will have much larger variations For example a 1 GHz VCO operating at near the minimum nominal divider ratio of 36 would according to EQ 8 exhibit about 4 nsec of peak variation at the phase detector under normal operation The lock detect circuit must not confuse this modulation as being out of lock For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com H gt QD O H O LLI H LLI Q QD LLI gt e gt O 2 LL H gt D as O H O LLI H LLI Q D LLI 2 e gt O 2 6 LLI oc LL CATHIE nwcosaaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY HMC984LP4E Lock Detect Circuits HMC984LP4E includes two lock detect circuits Legacy Lock Detect Function Phase Measurement Based Lock Detect Function Reg 01h 6 8 enables the lock detect functions of the HMC984LP4E The LD output is available either from the GPO pin DO or through SPI register Reg 12
37. generate phase comparison frequency that meets the limits of the phase detector The minimum reference frequency can be as low as 100 kHz provided that sharp rise and fall times less than 500 ps are guaranteed Internally the reference signal is used by other circuitry besides the phase detector For best performance it is recommended to use a higher reference frequency that is divided by the internal R Divider to generate the required phase comparison frequency Table 3 Reference Sensitivity Table Square Input Sinusoidal Input Frequency Slew 0 5V ns Recommended Swing Vpp Recommended Power Range dBm MHz Recommended Min Max Recommended Min Max lt 10 YES 0 6 2 5 x x x 10 YES 0 6 2 5 x x x 25 YES 0 6 2 5 ok 8 15 50 YES 0 6 2 5 YES 6 15 100 YES 0 6 5 150 ok 0 9 4 200 ok 1 2 3 200 to 350 x Yes 5 10 Note For greater than 200 MHz operation use buffer in High Frequency Mode Reg 08h 11 1 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com erittite HwcosaaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY Differential Phase Frequency Detector As shown in Figure 25 the HMC984LP4E features an ultra low noise digital differential Phase Detector PD w
38. gt 3 ns 11 Force when phase error gt 5 ns For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com H gt QD O H O LLI H LLI Q QD LLI gt e gt O 2 LL erittite HwcosaaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY Table 11 Reg 06h LKDOS Lock Detect Register BIT TYPE NAME DEFLT DESCRIPTION 6 0 R W LD High Threshold Duration 7 7Fh High threshold for measuring PFD pulse width 13 7 R W LD Low Threshold Duration 7 0x00 Low threshold for measuring PFD pulse width Number of consecutive counts within the time window to declare 23 14 R W LD OK Count Threshold 10 200h lock Theory of Operation on page 14 Table 12 Reg 07h LKDOS Legacy Lock Detect Register BIT TYPE NAME DEFLT DESCRIPTION 0x1000 Number of consecutive counts within the time window to declare 15 0 R W LKDOS OK Count 16 40969 lock Legacy Lock Detect Function on page 24 18 16 R W LKD One Shot Pulse Width 3 100b Set ring oscillator speed or frequency 20 19 R W LKDOS Ring Oscillator Speed 2 006 00 fastest 11 slowest 21 R W LKDOS Ring Osci
39. h Legacy Lock Detect Function The Lock Detect circuit in the HMC984LP4E places a one shot window around the reference The one shot window may be generated by either an analog one shot circuit or a digital one shot based upon an internal ring oscillator timer Clearing LKDOS One Shot Select Reg 07h 22 0 will result in a nominal 10 nsec analog window of fixed length as shown in Figure 9 Setting this bit to 1 will result in a variable length digital widow The digital one shot window is controlled by LKDOS Ring Oscillator Speed Reg 07h 20 19 The resulting lock detect window period is then generated by the number of ring oscillator periods defined in LKDOS One Shot Pulse Width Reg 07h 18 16 The lock detect ring oscillator may be observed on the GPO port by setting Reg 07h 21 1 and configuring the Reg 08h 7 0 C1h in GPO Lock detect does not function when this test mode is enabled LKDOS OK Count Reg 07h 15 0 defines the number of consecutive counts of the VCO that must land inside the lock detect window to declare lock If for example LKDOS OK Count 1000 then the VCO arrival would have to occur inside the selected lock window 1000 times in a row to be declared locked When locked the Lock Detect flag Reg 12h 2 1 is set Reg 12h is a read only register A single occurrence outside of the window will result in clearing the Lock Detect flag T 10nsec LOCK WINDOW LOCK WINDOW DETECT WINDOW 50MHz PFD VCO WI
40. hase Detector Input 14 bit Reference Frequency Divider Lock Indicator Output Phase Measurement Capability GPIO General Purpose Input Output Test Pin Cycle Slip Prevention Support with HMC984LP4E 24 pin 4 x 4mm LP4E Package General Description HMC984LP4E is a high performance ultra low phase noise SiGe BiCMOS Phase Frequency Detector and Charge Pump targeted to be used together with the HMC983LP5E Fractional Frequency Divider to together form a high performance low noise ultra low spurious emission fractional N frequency synthesizer Although best performance and maximum features are achieved when used together with the HMC983LP5E the HMC984LP4E can also be used as a stand alone low phase noise phase frequency detector The HMC984LP4E can receive differential VCO input and a reference frequency as high as 150 MHz It features a 14 bit reference frequency R Divider and automatic and or configurable Lock Detect Indicator as well as integrated CSP Cycle Slip Prevention capability when used together with the HMC983LP5E that significantly improves frequency lock time Integrated Charge Pump phase swap option enables seamless interfaced to VCOs and active loop filters with inverted polarity Additional features include adjustable Charge Pump gain and offset current that improve linearity and performance and a Soft Reset feature that resets all register to default values without having to perform a power cycle Th
41. ith two differential inputs One input comes from the reference path divider and the other from VCO path divider The reference input is internal to 9841 whereas the divided VCO input is external The output from the PD is fed to the charge pump in HMC984LP4E which converts the PD digital output to a current with programmable gain The output of the CP is directly proportional to the phase difference between the divided reference and the VCO path signals VCCPD 5V HMC984LP4E Figure 28 HMC984LP4E Input Interface The input of PD is a differential current input The input interface configurations are shown in Figure 25 and Figure 25 The HMC984LP4E is designed to work with its companion divider part the HMC983LP5E that provides an open collector output The inputs are internally pulled up to VCCPD with on chip 50 O resistors Thus any open collector buffer can drive the PD inputs A minimum of 750 mVpp single ended level is needed to drive the PD inputs VCCPD 5V HMC983LPSE HMC984LP4E Figure 29 HMC984LP4E Input Interface with Companion Part HMC983LP5E For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com H gt D as O H O LLI H Q D gt e gt O 2 6 LLI LL H gt D
42. le is 40 clock cycles long To specifically read a register the address of that register must be written to dedicated Reg OOh This requires two full cycles one to write the required address and a 2nd to retrieve the data A read cycle can then be initiated as follows 1 The host asserts SEN active low Serial Port Enable followed by a rising edge SCK 2 HMC984LP4E reads SDI the MSB on the 1 rising edge of SCK after SEN 3 HMC984LP4E registers the data bits in the next 29 rising edges of SCK total of 30 data bits The LSBs of the data bits represent the address of the register that is intended to be read 4 Host places the 7 register address bits on the next 7 falling edges of SCK to LSB while the HMC984LP4E reads the address bits on the corresponding rising edge of SCK For a read operation this is 0000000 5 Host places the 3 chip address bits 100 on the next 3 falling edges of SCK MSB to LSB Note the HMC984LP4E chip address is fixed as 4d or 100b 6 SEN goes from low to high after the 40th rising edge of SCK This completes the first portion of the READ cycle 7 The host asserts SEN active low Serial Port Enable followed by a rising edge SCK 8 HMC984LP4E places the 30 data bits 7 address bits and 3 chip id bits on the SDO on each rising edge of the SCK commencing with the first rising edge beginning with MSB 9 The host de asserts SEN i e sets SEN high after reading the 40 bits from the SDO
43. lizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com H gt QD as O H O LLI H LLI Q D gt e gt O 2 LL H gt D as O H O LLI H LLI Q D gt e gt O 2 oc LL E Hittite MICROWAVE CORPORATION v02 0112 HMC984LP4E ROHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY TYPICAL PERFORMANCE CHARACTERISTICS Figure 1 HMC984LP4E amp HMC983LP5E PLL Flicker FOM vs Temperature 11 HiK Mode b eset Integer Mode FLICKER FOM dBc Hz 50 25 0 25 50 75 100 TEMPERATURE C Figure 3 HMC984LP4E amp HMC983LP5E PLL Flicker FOM vs Frequency 11 265 5 LARA i s Hi K Mode A 266 Hi K Mode B i 1 i i 5 m m o o o a FLICKER FOM dBc Hz 8 N in m o a o2 269 5 FREQUENCY GHz Figure 5 HMC984LP4E amp HMC983LP5E PLL Flicker FOM vs Reference Power 1 264 5 265 7265 5 266 266 5 Hi K ___ 267 gt i FLICKER FOM dBc Hz HiK Integer Mode Integer Mode 15 10 5 0 5 10 15 REFERENCE POWER dBm Figure 2 HMC984LP4E amp HMC983LP5E PLL Floor FOM vs Temperature I1 Hi K Mode B Integer Mode FLICKER FOM dBc Hz HiK Integer Mode 50 25 0 25 50 75 100 TEMPERATURE C Figure 4 HMC98
44. llator Mode 1 0 T Foros Nng 0 Normal operation 22 R W LKDOS One Shot Select 1 1 1 Select digital one shot 0 Select analog one shot Table 13 Reg 08h GPIO Register BIT TYPE NAME DEFLT DESCRIPTION Select signal to be probed on the GPIO output pin 0000 gpo_test 0001 Locked 0010 PFD UP output to LKD 0011 PFD dn output to LKD 0100 R Divider output to digital 0101 R Divider output 0110 PFD saturation reset 3 0 R W GPO Output Signal Select 4 0000b 0111 PFD saturation DN VCO output 1000 PFD saturation UP REF output 1001 Ring oscillator test output 1010 One shot pulse output 1011 One shot trigger output 1100 Pull up hard 1101 Pull down hard 1110 VCO divider output to digital 1111 Crystal oscillator buffer output H gt D as O H O LLI H LLI Q D LLI 2 e gt O 2 LL 5 4 R W GPO Static Test Value 2 00b Static test values for GPIO Only LSB is used 7 6 R W GPO Output Enable 2 116 1 Enable GPIO output 0 Configure GPIO as input For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com E Hittite MICROWAVE CORPORATION v02 0112 RoHS v
45. lta Sigma Modulator Synthesizer HMC983LPSE Figure 25 Typical Application of HMC984LPA4E with HMC983LP5E to Form a Frequency Synthesizer HMC984LP4E is a high performance low noise phase detector and charge pump It consists of the following main functional blocks 1 Reference Crystal Buffer Reference Path R Divider Differential Phase Frequency Detector 5 V Charge Pump Two Lock Detect Circuits 2a Serial Port Interface PLL Performance Metrics Figure of Merit Noise Floor and Flicker Noise Models The phase noise of an ideal phase locked oscillator is dependent upon a number of factors a Frequency of the VCO and the Phase detector b VCO Sensitivity kvco and VCO and Reference Oscillator phase noise profiles c Charge Pump current Loop Filter and Loop Bandwidth d Mode of Operation Integer Fractional modulator style The contributions of the PLL to the output phase noise can be characterized in terms of a Figure of Merit FOM for both the PLL noise floor and the PLL flicker 1 f noise regions as follows PLL PHASE m NOISE 95 6 pd Eq 1 m For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com erittite HwcosaeaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR
46. mple locked VCO phase noise approximation is shown on the left of Figure 25 Po e H Figure 32 Synthesizer Phase Noise amp Jitter With this simplification the single sideband integrated VCO phase noise 2 in rads at the phase detector is given by osse C Eq 6 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com erittite nwcosaaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY where ss f0 is the single sideband phase noise in rads Hz inside the loop bandwidth B is the dB corner frequency of the closed loop PLL and N is the division ratio of the prescaler The rms phase jitter of the VCO in rads results from the power sum of the two sidebands J20 ssp Eq 7 Since the simple integral of EQ 6 is just a product of constants the integral in the log domain can easily be done For example if the VCO phase noise inside the loop is 100 dBc Hz at 10 kHz offset and the loop bandwidth is 100 kHz and the division ratio N 100 then the integrated single sideband phase noise at the phase detector in dB is given by dB 10log f Bm N 100 50 5 40 85 dBrads or equivalently 10 997 56 urads rms or 3 2 milli degrees rms While the phase noise reduces by a fa
47. output The 40 bits consists of 30 data bits 7 address bits and the 3 chip id bits This completes the read cycle Note that the data sent to the SPI by the host during this portion of the READ operation is stored in the SPI when SEN is de asserted This can potentially change the state of the HMC984LP4E If this is undesired it is recommended that during the second phase of the READ operation that Reg 00h is addressed with either the same address or the address of another register to be read during the next cycle For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com H gt QD O H O LLI H LLI Q QD LLI gt e gt O 2 LL H gt D O H O LLI H LLI Q QD gt e gt O 2 6 LLI oc LL erittite nwcosaaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY SEN from Master SCK from Master SDI from Master SDO To Master Figure 35 SPI Timing Diagram DVDD 5 V 21096 GND 0 Table 4 Main SPI Timing Characteristics Parameter Conditions Min Typ Max Units ty SDI to SCK Setup Time 8 nsec to SDI to SCK Hold Time 8 nsec tg SCK High Duration
48. parison is the comparison frequency Hz Igp where Ea 4 Note that this calculation can be performed for the center frequency of the VCO and does not need refinement for small differences lt 25 in center frequencies Also operation with unreasonably large charge pump offset may cause Lock Detect to incorrectly indicate an unlocked condition To correct reduce the offset to recommended levels Reference Crystal Input Buffer The ultra low noise phase detector requires the best possible reference signal The low phase noise reference input buffer is optimized for this purpose The input pin XREFP is DC coupled internally and there is 800 mV DC bias on the pin The reference source should be AC coupled to the pin The maximum input power can be up to 12 dBm from a 50 source In order to achieve best phase noise performance the reference source should have a phase noise floor of 160 dBc Hz or better Reference Path R Divider HMC984LP4E has 14 bit frequency divider that divides the incoming reference frequency by any number from 1 to 214 1 16 383 inclusive The maximum frequency at which the phase detector can work depends on the mode of operation when working as a PLL with its companion chip HMC983LP5E In integer mode the reference buffer and divider can work up to 175 MHz and in fractional mode the maximum frequency is typically 125 MHz Hence higher crystal frequencies need to be divided down by the R divider in order to
49. pical serial port operation can be run with SCK at speeds up to 30 MHz The details of SPI access for the 9841 are provided in the following sections Note that the READ operation below is always preceded by a WRITE operation to Register O to define the register to be queried Also note that every READ cycle is also a WRITE cycle in that data sent to the SPI while reading the data will also be stored by the HMC984LP4E when SEN goes high If this is not desired then it is suggested to write to Reg 00h during the READ operation so that the status of the device will be unaffected Power on Reset and Soft Reset The HMC984LP4E has a built in Power On Reset POR and a serial port accessible Soft Reset SR POR is accomplished when power is cycled for the HMC984LP4E while SR is accomplished via the SPI by writing Reg 00h 80h followed by writing Reg 00h OOh All chip registers will be reset to default states approximately 250 us after power up Serial Port WRITE Operation The host changes the data on the falling edge of SCK and the HMC984LP4E reads the data on the rising edge A typical WRITE cycle is shown in Figure 1 It is 40 clock cycles long 1 The host both asserts SEN active low Serial Port Enable and places the MSB of the data on SDI followed by a rising edge on SCK 2 HMC984LP4E reads data on SDI the MSB on the 1st rising edge of SCK after SEN For price delivery and to place orders Hittite Microwave Corporation
50. r of the spurious product Higher values of m produce smaller amplitude spurious at offsets of mA and usually when gt 4 spurs are small or unmeasurable The worst case in fractional mode is when d 1 and the VCO frequency is offset from n fyg by less than the loop bandwidth This is the in band fractional boundary case fvco n integer d 1 Integer m 1 1st order Integer Boundary A lt Loop Bandwith Boundary 1st Order Integer Boundary Spur nfpa n 1 2 fpa n 1 f pa n integer d 1 fvco m 2 2nd order Integer A lt Loop Bandwith Integer Boundary 2A 2A 2nd Order Boundary dandi Spur nfpa n 1 2 fpa n 1 fpa Figure 27 Fractional Spurious Example Characterization of the levels and orders of these products is not unlike a mixer spur chart Exact levels of the products are dependent upon isolation of the various synthesizer parts Hittite can offer guidance about expected levels of spurious with our PLL and VCO application boards Regulators with high power supply rejection ratios PSRR are recommended especially in noisy applications When operating in fractional mode charge pump and phase detector linearity is of paramount importance Any non linearity degrades phase noise and spurious performance Phase detector linearity degrades when the phase error is very small and is operating back and forth between reference lead and VCO lead To mitigate these non linearities in fractional mode it is critical
51. rent in down direction VCO 22 R W Down Offset Current Enable 1 0 Divider is lagging when phase swap is 0 Enables high gain mode for the charge pump with uncontrolled 1 23 RAW High Gain Enable 1 0 mA 3 5 mA of additional charge pump current Charge Pump Op Amp bias select 00 540 pA 25 24 R W OP Amp Bias 2 11b 01 689 uA 10 943 pA 11 1503 pA 26 R W CP Force Up Enable 1 0 Force Up current from the charge pump output 27 R W CP Force Down Enable 1 0 Force Down current from the charge pump output Force the charge pump output to mid rail voltage cp force up 28 R W CP Force Mid Rail Enable 1 0 RegO9h 26 or cp force dn RegO9h 27 have precedence over this bit 29 R W Ring Oscillator Output to CP Enable 1 0 Exports ring oscillator to pulluphard pulldnhard for test purpose Table 10 Reg 05h LKD FLXCPGAIN Lock Detect Register BIT TYPE NAME w DEFLT DESCRIPTION 0 R W LD Asymmetric Window Enable 1 0 Enable asymmetric window for Lock Detect 0 Reference is expected first 1 R W LD Asymmetric Direction Select 1 0 1 VCO Divider is expected first 2 R W Reference Edge for LD Select 1 g O Userfalling adgs 1 Use rising edge Forces UP or DN if phase error exceeds the register value 00 Disabled 4 3 R W Flex CP Mode Select 2 00b 01 Force when phase error gt 1 ns 10 Force when phase error
52. rom the desired locked frequency the phase difference at the PD varies rapidly over a range larger than 27 radians Since the gain of the PD varies linearly with phase only to 27 the gain of conventional PDs will cycle from high gain when the phase difference approaches a multiple of 271 to low gain when the phase difference is slightly more than 2r radians This phenomena is known as cycle slipping Cycle slipping causes the pull in rate during the phase acquisition to vary cyclically as shown in the red curve in Figure 25 Cycle slipping can dramatically increase the time to lock to a value far greater than that predicted by normal small signal Laplace analysis time fo VCO with CSP 5 8 VCO Frequency with Conventional PFD Cycle Sliping Figure 30 Cycle Slipping The HMC984LP4E PD features Cycle Slip Prevention CSP only when working in conjunction with the companion part the HMC983LP5E When enabled the CSP feature holds the PD gain in the appropriate polarity until such time as the frequency difference is near zero This enables significantly faster lock times as shown in Figure 25 The use of CSP feature is enabled with CSP Enable Reg O1h 4 1 and CSP Output Enable Reg 01h 13 1 The CSP feature may be optimized for a given set of PLL dynamics by adjusting the PD sensitivity to cycle slipping This is achieved by adjusting CSP Reset Delay Reg O3h 2 0 For price delivery and to place orders
53. s Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com H gt QD oc O H O LLI H Q D gt e gt O 2 6 LLI oc LL H gt D O H O LLI H LLI Q QD gt e gt O 2 oc LL ervittite nHwcosaeaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY General Purpose Input Output Pin DO HMC984LP4E has one GPIO pin DO This pin normally functions as the output for the lock detect It can be programmed to test and probe several internal signals Following signals are available Reg O8h 3 0 gpo test out Lock Detect or Lock Indicator output PFD UP output going to Lock Detect PFD DN output going to Lock Detect R Divider output to digital R Divider output Saturation reset Signal PFD saturation DN VCO output PFD saturation UP REF output 10 Ring oscillator test output o 0o Noc mo0owm 11 One shot pulse output 12 One shot trigger output 13 Pull UP hard 14 Pull down hard 15 VCO divider output to digital 16 Crystal oscillator buffer output See the serial port section for programming configuration Reg 08h Serial Port Interface The HMC984LP4E features a four wire serial port for simple communication with the host controller Ty
54. s set to Reg 06h 23 14 512d then the phase error count has to be between 20 and 50 for 512 consecutive reference cycles before that lock is declared The thresholds make it easier to define lock condition in case of fractional operation where the static phase error is expected to be larger due to charge pump offset currents Chip Address Pins HMC984LP4E has three programmable chip address bits which enable the HMC984LP4E to be used in an SPI bus configuration Two LSB chip address bits are internal and bond wire programmable at the time of packaging The MSB bit is available externally as pin CHIP3 The chip address pins are read at power up and every time the chip is reset By default all CHIPS is internally pulled to DVDD thus there is no need to connect the pin to DVDD if the address bit is to be set as logic high To assign a 0 to address bit pin should be connected to ground The internal CHIP1 and CHIP2 bits are internally tied to ground The chip address for the companion chip HMC983LP5E is stored in Reg 09h 2 0 of HMC984LP4E In cases when an SPI command is common to both devices it is not necessary to send separate commands to each part Both parts are always listening to the SPI bus and when a common command is issued they will take the command and update the corresponding registers Writing its own chip address to the companion chip address register Reg O9h 2 0 will disable this feature For price delivery and to place order
55. to operate the phase detector with some finite phase offset such that either the reference or VCO always leads To provide a finite phase error extra current sources can be enabled which provide a constant For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com H gt QD O H O LLI H LLI Q QD LLI gt e gt O 2 LL H gt D O H O LLI H LLI Q QD gt e gt O 2 6 oc LL erittite nHwcosaaE MICROWAVE CORPORATION v02 0112 RoHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY DC current path to VDD VCO leads always or ground reference leads always These current sources are called charge pump offset and they are controlled via Reg 04h 20 14 The time offset at the phase detector should be 2 5 ns 4 Tps where Tps is the RF period at the fractional prescaler input in nanoseconds The specific level of charge pump offset current is determined by this time offset the comparison frequency and the charge pump current and can be calculated from Required CP Offset 2 5 10 9 4754 Fsomparison Tps is the RF period at the fractional prescaler input sec lop is the full scale current setting of the switching charge pump A Fcom
56. uously on 0 Normal DN operation 10 R W PD Outputs to LD Enable 1 1 1 Enables PD outputs to Lock Detect in the Digital 1 resets the PD when crystal is exported to the companion Poo ae Reser PDwhenatal Gate Prescaler Sigma Delta chip HMC983LP5E For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 978 250 3343 tel 978 250 3373 fax Order On line at www hittite com Application Support apps hittite com erittite nwcosaaE MICROWAVE CORPORATION v02 0112 ROHS v DIGITAL PHASE FREQUENCY DETECTOR EARTH FRIENDLY Table 9 Reg 04h Charge Pump Settings Register BIT TYPE NAME W DEFLT DESCRIPTION Charge Pump DOWN MAIN current 20 pA step 127 steps 0000000 Tristate if PFD also disabled 0000001 20 pA 6 0 R W Up Current 7 Ox7h 0000010 40 pA 1111111 2 2 54 mA Charge Pump UP MAIN current 20 pA step 127 steps 000 Tristate if PFD also disabled 0000001 20 pA 13 7 R W Down Current 7 Ox7h 0000010 40 yA 1111111 2 54 mA Charge Pump offset current magnitude 5 pA step 127 steps 0000000 Tristate if PFD also disabled 0000001 5 pA 20 14 R W Offset Current 7 Ox7h 0000010 10 pA 1111111 635 pA Enable for Charge pump offset current in up direction Reference 21 R W Up Offset Current Enable 1 0 signal is lagging when phase swap is O Enable for Charge pump offset cur

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