APPLICATION NOTE AP-28
Contents
1. Directional control DIEN for the 8226 s is exer cised by the I O read command IORC or the memory read command MRDC in situations where memory mapped I O is used If the read command is asserted by the bus master and the module s base address is present the data buffer s receiver circuits are enabled The chip select CS for the data buffer is enabled when a command is gated onto the board Bus Address Decoding The bus address decoding logic decodes the appro priate address bits into device selects When mem ory mapped I O is used all ones on the high order 8 bits of the address are decoded The GPSI logic also produces an enable for the read write com mand decode logic and the MULTIBUS inhibit signals 11 The base address is decoded by an Intel 8205 one of eight binary decoder Ag This device is enabled by either ADR7 or ADR7 as determined by the wire wrap connections When enabled Ag decodes address bits ADR4 ADR5 and ADR6 into of eight outputs The base address enable BASE ADR may be taken from any one of the eight Ag outputs When the ADR4 through ADR7 bits correspond to the selected base address an enable is provided by Ag to a device select generator Ag and the read write command gates The device select generator consists of an Intel 8205 decoder Ag that is enabled by the base address When enabled Ag decodes address bits ADRI ADR2 and ADR3 into of eight2. Warburton Frankie Industries Melbourne Pty Ltd 220 Park Street South Melbourne Victoria 3205 AUSTRIA Bacher Elektronische Gerate GmbH Meidlinger Hauptstrasse 78 A 1120 Vienna Tel 0222 83 63 96 TELEX 01 1532 BELGIUM Inelco Belgium S A Avenue Val Duchesse 3 B 1160 Brussels Tel 02 660 00 12 TELEX 25441 DENMARK Scandinavian Semiconductor Supply A S Nannasgade 18 DK 2200 Copenhagen N Tel 01 93 50 90 TELEX 19037 FINLAND Oy Fintronic AB Loennrotinkatu 35D SF 00180 Helsinki 18 90 664 451 TELEX 12426 Tekelec Airtronic Cite des Bruyeres Rue Carle Vernet 92310 Sevres Tel 1 027 75 35 TELEX 250997 GERMANY Alfred Neye Enatachnik GmbH Schillerstrasse 14 D 2085 Quickborn Hambuig Tel 04106 6121 TELEX 02 13590 Electronic 2000 Vertriebs GmbH Neumarkter Strasse 75 D 8000 Muenchen 80 Tel 089 434061 TELEX 522561 Jermyn GmbH Postfach 1146 D 6277 Kamberg Tel 06434 6005 TELEX 484426 MARYLAND cont Mesa Inc 11900 Parklawn Drive Rockville 20852 MASSACHUSETTS Intel Corp 187 Billerica Road Suite 14A Chelmsford 01824 Tel 617 256 6567 TWX 710 343 6333 Computer Marketing Associates 235 Bear Hill Road Waltham 02154 Tel 617 890 1776 MICHIGAN Intel Corp 26500 Northwestern Hwy Suite 401 Southfield 48075 Tel 313 353 0920 TWX 910 420 1212 TELEX 2 31143 Lowry amp Associates Inc 135 W North Str
3. A1 12 A6 3 A2 2 A2 4 A13 5 A13 6 A14 1 A12 2 A8 16 A9 16 A11 16 A10 16 A12 14 A1 14 A2 14 A14 14 A3 16 A7 14 A6 14 A5 14 A13 14 A3 1 A7 13 A8 4 A9 4 A13 3 A8 8 A9 8 A11 8 A10 8 A12 7 A1 7 A2 7 A14 7 A3 8 A7 7 A6 7 Ab 7 A13 7 A8 A9 A10 A11 A12 A13 A14 8205 8205 8226 8226 74164 741502 74504 41 INTO 42 INT 1 39 INT2 37 INT4 38 INT5 35 INT6 36 INT7 57 ADRO 58 ADR1 51 ADR6 52 ADR7 49 ADR8 10 8 EQ ADR9 gt Md Ar 47 ADRA 48 ADRB 45 ADRC 46 ADRD gt 9 43 ADRE 44 ADRF 4 24 INH1 26 INH2 lt 0 19 MRDC 20 MWTC 21 IORC 22 IOWC 31 CCLK 14 INIT 23 XACK 25 AACK 73 DATAO 74 DATA1 71 DATA2 72 DATA 69 DATA4 70 DATAS 67 6 13 68 DATA7 o0 o o 40 INT3 o MR 6 o lt 9 74510 10 8 11 55 ADR2 56 ADR3 15 53 ADR4 1 Ay KY O 54 ADR5 OQ OO OQ Q MMIO GENERAL PURPOSE SLAVE BUS INTERFACE BASE ADR 1 2 3 4p 5 lo 6 70 XINTRO XINTR1 XINTR2 XINTR3 XINTR4 XINTR5 XINTR6 050 DS1 DS2 DS3 DS4 DS5 DS6 DS7 WRT BD ENABLE BD INIT BD INIT DBINO DBOUTO DBIN1 DBOUT1 DBIN2 DBOUT2 DBIN3 DBOUT3 DBIN4 DBOUTA DBINS DBOUTS D
4. APPLICATION AP 28 NOTE PRICE 1 00 Related Intel Publications INTELLEC Microcomputer Development System Hardware Reference Manual 98 132 System 80 10 Microcomputer Hardware Reference Manual 98 316 8080 Microcomputer Systems User s Manual 98 153 SBC 501 Direct Memory Access Controller Hardware Reference Manual 98 294 The material in this Application Note is for informational purposes only and is subject to change without notice Intel Corporation has made an effort to verify that the mate rial in this document is correct However Intel Corporation does not assume any respon sibility for errors that may appear in this document The following are trademarks of Intel Corporation and may be used only to describe Intel Products ICE 30 MCS ICE 80 MEGACHASSIS INSITE MICROAMP INTEL MULTIBUS INTELLEC PROMPT LIBRARY MANAGER UPI Intel MULTIBUS Interfacing Contents INTEL MULTIBUS MULTIBUS SIGNAL DESCRIPTIONS OPERATING CHARACTERISTICS MULTIBUS INTERFACE CIRCUITS ADDRESS DECODING BUS DRIVERS TET CONTROL SIGNAL LOGIC GENERAL PURPOSE SLAVE INTERFACE piod eR orare FUNCTIONAL PROGRAMMING CHARACTERISTICS THEORY OF OPERATION USER SELECTABLE OPTIONS PROTOTYPING APPLICATIONS SUMMARY Pc APPENDIX A MULTIBUS PIN ASSIGNMENT APPENDIX B MULT
5. device select outputs When memory mapped I O is used the high order 8 bits of the address bus are also decoded The address bits ADR8 through ADRF are used as inputs to 74LS27 The outputs of are ANDed by a 74510 A5 producing an active low output only when ADR8 ADRF are all active This output signal MMIO is used to generate optional inhibit signals as well as to enable the memory read and write commands when a connec tion is made between 2 3 and 5 The MMIO signal is inverted twice first by a 74504 and then by 7406 open collector drivers Ag At that point the signal can be con nected to the system and or INH2 bus signal lines The only situation in which the inhibit lines are required is if there is ROM or RAM in the system which physically occupies the upper 256 bytes of memory When this is the case you may choose to disable the memory mapped I O capability and use direct I O Otherwise you must select the proper inhibit connection to allow use of the memory mapped I O INHI is used to inhibit RAM while INH2 inhibits ROM With a worst case delay of 53 nanoseconds the decode circuit that produces the inhibit signals meets the bus AC requirement for inhibit delay tcp However the acknowledge of the inhibiting slave tAccp is a much more difficult specification to satisfy The difficulty arises because the latest possible acknowledgement from the inhib
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7. NOR gate 13 The output of is designated CMD CMD is enabled by the decoded base address at OR gate A to produce the board enable This signal BD ENABLE controls the three state gates that drive AACK and XACK onto the MULTIBUS BD ENABLE also controls the chip selects for the data bus buffers The output of the I O and memory write buffer is inverted with 74504 and forwarded as WRT to the user logic This internal write enable should be qualified at each of these destinations by the appropriate device select The output of the I O and memory read buffer is inverted and then enabled by the decoded base address at The resulting internal read enable RD is applied to the user logic and to the direc tion control DIEN on the bidirectional bus driver chips Ajo and 12 Advance Transfer Acknowledge Generation The advance transfer acknowledge generation logic provides a transfer acknowledge response XACK to notify the bus master that data has either been accepted from the MULTIBUS during a write operation or placed on the MULTIBUS during a read operation An advance acknowledge re sponse AACK is also provided for use in certain 8080 based systems where it can decrease by one the number of Wait states needed to complete a read or write operation Both acknowledge responses are generated by 12 an 8 bit serial in parallel out shift register When enabled by CMD A shifts CCLK
8. OF OPERATION In the preceding section each of the GPSI func tional blocks was identified and briefly defined This section explains how these functions are implemented For detailed circuit information refer to the GPSI schematic in Appendix C The schematic is on a foldout page so that you can relate the following text to the schematic GPSI contains those logic elements that participate directly in the following types of MULTIBUS activity Bus address control and data buffering 2 Bus address decoding 3 Bus control signal propagation 4 Advance Transfer acknowledge generation 5 Interrupt signal buffers The five groups of logic responsible for these tasks are described in the following paragraphs Bus Address Control and Data Buffers Only one bit of the bus address is buffered and passed directly onto the user logic The rest of the address bits are used to drive decoders ADR is buffered by 741502 The control signal buffer circuit consists of a 74832 A1 and a 74810 A5 for the memory and I O read write com mands These circuits are used to provide very high switching speed The data buffers are formed by two Intel 8226 inverting bidirectional driver receiver chips Ajo and A11 The system data bus is connected to the device s DB pins The DO and DI pins of each chip can be connected to the user logic providing either an independent input and output bus or a bidirec tional bus
9. Width 100 ns Inhibit Delay 1 5 us 2 gt The max is imposed only if the bus timeout feature is engaged a field option Data Transfers The MULTIBUS provides a maximum bandwidth of 5 MHz for single or multiple read write trans fers Figure 1 shows the read data transfer timing dia gram Read Data The address must be stable tas for a minimum of 50 ns before command This time is typically used by the bus interface to decode the address and thus provide the required device selects The device selects establish the data paths on the user system in anticipation of the strobe signal command which will follow The minimum command pulse width is 100 ns The address must remain stable for at least 50 ns following the command tay Relative to Address Acknowledge of Inhibiting slave is a function of the Cycle time of the inhibited slave Valid data should not be driven onto the bus prior to command and must not be removed until com mand goes away The XACK signal which is a response indicating the specified read write oper ation has been completed must coincide or follow both the read access tacc and valid data tp xr XACK must be held until the command goes away tcx Write Data The write data transfer timing diagram is shown in Figure 2 During a write data transfer valid data must be presented in parallel with a stable address Thus the write data setup time tps has th
10. not all bus masters will respond to AACK Since XACK and AACK timing requirements depend on both the CPU of the bus master and characteristics of the user logic a circuit is needed which will provide a range of easily modified acknowledge responses The transfer acknowledge signals must be driven by three state drivers which are enabled when the bus interface is addressed and a command is present Interrupt Signal Lines The asynchronous interrupt lines must be driven by open collector devices with a minimum drive of 16 mA In a typical system logic must be provided to assert and latch up an interrupt signal The latched interrupt signal would be removed at a later time by an I O operation such as reading the module s status GENERAL PURPOSE SLAVE INTERFACE Learning by example is often the most effective means for absorbing technical information With this idea in mind a detailed description of a general purpose slave interface GPSI has been included in this application note The description is generally directed towards the implementation of an I O interface However the GPSI can also be used as a slave memory interface by simply buffer ing the additional address signals and using the appropriate MULTIBUS memory commands The most significant aspect of the GPSI is that all the information required to actually construct the interface is contained in Appendix C You can make use of the schematic and wire list to pr
11. pulses This produces a sequence of high true pulses at A15 s outputs The outputs occur at approximately 100 ns intervals The appropriate Q outputs are selected by wire wrap connections to the inputs of a pair of three state gates A3 These gates drive the XACK and AACK outputs onto the MULTIBUS when enabled by BD ENABLE As mentioned in the previous discussion on inhibit operations the maximum of about 800 ns delay provided by A15 may not be adequate This can be extended by either using a flip flop to pre divide CCLK or by adding a second shift register in series with Although both techniques double the range the first cuts the resolution in half Interrupt Signal Buffers The GPSI only provides buffering for the bus inter rupt signal lines Two 7406 open collector drivers As and Ag are used for this function The MULTIBUS interrupt signals should be driven with levels rather than pulses unless the bus master has an edge triggered interrupt controller The user s logic must latch and hold the interrupt signal until serviced by the bus master USER SELECTABLE OPTIONS In this section each of the options available to the user is reviewed and the specific information required to implement the desired characteristic is summarized Base Address Selection The GPSI s base address is selected by wire wrap connections from one of the output pins of Ag to an enable input E2 of Ao Table 3 identifies the b
12. the capacity for an additional 80 16 pin loca tions for wire wrap sockets or the equivalent mix of 14 16 18 22 24 28 or 40 pin sockets SUMMARY This application note has shown the structure of the Intel MULTIBUS The structure supports a wide range of system modules from the Intel OEM Computer Product Line that can be extended with the addition of user designed modules Because the user designed modules are no doubt unique to particular applications a goal of this application note has been to describe in detail the singular common element the bus interface Material has also been presented to assist the systems designer in understanding the bus functions so that successful systems integration can be achieved SBC 905 COMPONENT SIDE Figure 7 Prototype Board Layout APPENDIX A MULTIBUS PIN ASSIGNMENT COMPONENT SIDE CIRCUIT SIDE PIN MNEMONIC DESCRIPTION m MNEMONIC DESCRIPTION Signal GND Signal GND 5 VDC 5 VDC Power 5 VDC 5 VDC Supplies 12 VDC 12 VDC 5 VDC 5 VDC Signal GND Bus Clock Bus Priority In Bus Busy Memory Read Command Read Command XFER Acknowledge Special Acknowledge Signal GND Initialize Bus Priority Out Bus Request Memory Write Command Write Command Inhibit 1 Disable RAM Inhibit 2 Disable PROM or Bus Controls Interrupts ROM Reserved Reserved Reserved Reserved Const
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14. BING DBOUTG DBIN7 DBOUT7 APPENDIX MECHANICAL SPECIFICATIONS 0 25 X 45 2 PLACES gt 9 109 DIA 3 HOLES COMPONENT SIDE 6 75 REF 0 06R d 4 TYP 0 55 0 30 3 080 0 390 4 570 0 015 0 005 45 6 767 0 005 CHAMEERUADE CONNECTOR EDGES 0 040 45 NOTES gt BOARD THICKNESS 0 062 EJECTOR TYPE SCANBE 25203 MULTIBUS CONNECTOR 86 PIN 0 156 SPACING 5 BUS DRIVERS AND RECEIVERS SHOULD BE LOCATED AS CLOSE AS POSSIBLE CDC VFBO1E43D00A1 THEIR RESPECTIVE MULTIBUS PIN CONNECTIONS VIKING 2VH43 1ANE5 E 6 BOARD SPACING 0 6 AUXILIARY CONNECTOR 60 PIN 0 100 SPACING CDC VPB01B30D00A1 7 COMPONENT HEIGHT 0 435 TI H311130 AMP 14559 8 CLEARANCE ON CONDUCTOR NEAR EDGES 0 050 18 Intel MULTIBUS Interfacing intel AP 28 REQUEST FOR READER S COMMENTS The Microcomputer Division Technical Publications Department attempts to provide documents that meet the needs of all Intel product users This form lets you participate directly in the documentation process Please restrict your comments to the usability accuracy readability organization and completeness of this document 1 Please specify by page any errors you found in this manual 2 Does the document cover the information you expected or required Please make suggestions for improvement 3 Is this the right type of document for your needs 15 it at the right level What other types of documents are needed 4 Did you have
15. IBUS DC REQUIREMENTS APPENDIX C GPSI INTERFACE SCHEMATIC AND WIRE LIST um ERRARE APPENDIX D MECHANICAL SPECIFICATIONS Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product No other circuit patent licenses are implied INTRODUCTION A significant measure of the power and flexibility of the Intel OEM Computer Product Line can be attributed to the design of its system bus the Intel MULTIBUS The bus structure provides com mon element for communication between a wide variety of system modules which include Single Board Computers memory and I O expansion boards peripherals and controllers The purpose of this application note is to help you develop a basic understanding of the Intel MULTI BUS This knowledge is essential for configuring a system containing multiple modules Another purpose is to provide you with the information necessary to design a bus interface for a slave module One of the tools that will be used to achieve this goal is the complete description of a general purpose slave interface The detailed description includes a wire list that you can use to build the interface on a prototype board Thus you can connect your external logic to the MULTIBUS via this interface Other portions of this application note provide an indepth examination of the bus signals oper ating characteristics AC and DC requirements and bus interface ci
16. ake control of the bus with the next falling edge of BCLK completing the actual bus exchange Master B takes control by asserting BUSY and enabling its drivers Thus a full BCLK period in addition to the synchronization of the internal transfer request is required for the bus exchange between masters and must be included in bus latency calculations DC Requirements The drive and load characteristics of the bus signals are listed in Appendix B The physical locations of the drivers and loads as well as the pull up down resistor of each bus line are also specified The MULTIBUS DC requirements for drive and loading are guidelines only These guidelines are used on Intel OEM products MULTIBUS INTERFACE CIRCUITS There are three basic elements of a bus interface address decoders bus drivers and control signal logic This section discusses each of these elements in general terms A description of a detailed imple mentation of a slave interface is presented in a later section of this application note ADDRESS DECODING This logic decodes the appropriate MULTIBUS address bits into RAM requests ROM requests or I O selects Care must be taken in the design of the address decode logic to ensure flexibility in the selection of base address assignments Without this flexibility severe restrictions may be placed upon various system configurations Ideally switches and jumper connections should be associated with the decode logic to pe
17. ant Clk Reserved Reserved Reserved Parallel Interrupt Requests Parallel Interrupt Requests Address Bus Address Bus Data Bus Signal GND Signal GND 10 VDC 10 VDC Power 12 VDC 12 VDC Supplies 5 VDC 5 VDC 5 VDC 5 VDC Signal GND Signal GND For MDS 800 compatibility APPENDIX B MULTIBUS DC REQUIREMENTS BURG DRIVER LOAD PER BOARD PULL UP DOWN LOCATION DRIVE Min LOCATION SOURCING Max RESISTOR INIT Master TTL 32mA AI None BCLK CCLK Master TTL 48 mA Master 220 3300 termination on Motherboard Master TTL 16 mA 1 pull up on Motherboard BPRN Master TTL 16 mA Master None BPRO Master TTL 32mA Master None BUSY Master OC 20mA Master 1 0 pull up MRDC MWTC Master TRI 32 Slave 1 1 pull up IORC IOWC Master TRI 32mA Board 1 1 pull up XACK AACK Slave TRI 16 mA Master 510 Q pull up DATF DATO Master TRI 15 mA Slave 2 2 pull up ADRF ADRG Master TRI 15 mA Slave 2 2 pull up INH1 INH2 All OC 16 mA RAM PROM 1 pull up Memory Mapped 1 INT7 INTO OC 16 mA Master 1 pull up NOTES 1 Input voltage levels High 2 4V to 5 0V Low 0 0V to 0 8V 2 Output voltage level High 2 0V to 5 25V Low 0 0V to 0 45V OC open collector TTL totem pole output TRI three state 3 Leakage current of an input lt 40 LA Leakage current of an output 100 uA 4 Maximu
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19. ase address that is implemented for each jumper combination Table 3 BASE ADDRESS SELECTION TO A8 6 A8 5 P1 52 GND Advance Transfer Acknowledge Timing The GPSI s advance acknowledge and transfer acknowledge response timing is selected in approxi mately 100 ns increments by wire wrap connec tions at the outputs of Table 4 shows the range of response timing for each possible connec tion in terms of CCLK periods This range occurs Table 4 TO A8 5 A8 6 because of the skew introduced into the acknowl edge circuit by the use of CCLK to drive Actual time values for these periods depend of course on the frequency of CCLK For the SBC 80 10 or 80 20 bus masters CCLK is 9 216 MHz which provides a clock period of 108 5 nano seconds ADVANCE TRANSFER ACKNOWLEDGE TIMING DELAY FROM RECEIPT OF CMD GENERATION Immediate to CCLK Periods to to to to to to 0 1 2 3 4 b 6 7 to CCLK Periods PROTOTYPING APPLICATIONS The GPSI should be well suited for most prototyp ing applications by constructing the interface on a SBC 905 Universal Prototype Board A complete wire list is provided in Appendix C to further simplify the task The complete general purpose slave interface requires 14 IC s and can best be laid out by placement from left to right A1 A14 across the bottom of the SBC 905 Figure 7 Using the GPSI constructed on an SBC 905 you have
20. ationship among the bus conten tion resolution signals using the parallel bus prior ity technique p READ DATA MASTER A MASTER NOTE BUSPRIORITY MUST BE RESOLVED WITHIN ONE BCLK PERIOD MASTER A MASTER B BCLK D gt TRANSFER REQUEST BREQ BPRN TRANSFER REQUEST BREQ BPRN ON BUS MASTER A ON BUS BUSY ADDRESS COMMAND k T OFF p TRI STATE ON EN DRIVER ENABLE ADDRESS COMMAND DRIVER ENABLE Figure 4 Bus Control Exchange Operation In this example master A has been assigned a lower priority than master B The bus exchange occurs because master B asserts a bus request during a time when master A has control of the bus The exchange process begins when master B requires the bus to access some resource such as an I O or memory module This internal transfer request is synchronized with the falling edge of BCLK to generate a bus BREQ signal The active BPRN signal to master A goes inactive because of the BREQ from master B When the BPRN signal to master is inactive and master A has completed a command which may have been in operation the falling edge of BCLK is used to synchronize BUSY going inactive This allows the actual exchange to occur because control of the bus has been relinquished and another master may then assume control During this time the drivers of master A are disabled Master B must t
21. device problem may arise if data hold time requirements must be satisfied for user logic fol lowing write operations When bus commands are used to directly produce both the chip select for the bidirectional bus driver and a strobe to a latch in the user logic removal of that signal may not provide the user s latch with adequate data hold time Depending on the specifics of the user logic this problem may be solved by permanently enabling the data buffer s receiver circuits CONTROL SIGNAL LOGIC The control signal logic consists of the circuits that forward the I O and memory read write commands to their respective destinations provide the bus with transfer acknowledge responses and drive the system interrupt lines Bus Command Lines The MULTIBUS information transfer protocol lines MRDC MWTC IORC and IOWC should be buffered by devices with very high speed switch ing Because the bus DC requirements specify that each board may load these lines with 2 0 mA Schottky devices are recommended The com mands are gated with the signal indicating whether or not the base address has been decoded to gener ate read and write strobes for the user logic Transfer Advance Acknowledge Generation The user interface transfer advance acknowledge generation logic provides a transfer acknowledge response XACK to notify the bus master that write data provided by the bus master has been accepted or that read data it has requested i
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23. e same requirement as the address setup time tas The requirement for stable data both before and after command enables the bus interface circuitry to latch data on either the leading or trailing edge of command x tAS tcmD STABLE ADDRESS VALID DATA COMMAND XACK tacc t tx ACK E Figure 1 Read Data Transfer DXT dde STABLE ADDRESS VALID DATA COMMAND tXACK i Figure 2 Write Data Transfer Inhibit Operations Bus inhibit operations are required by certain boot strap and memory mapped I O configurations The purpose of the inhibit operation is to allow a com bination of RAM ROM or memory mapped I O to occupy the same memory address space In the case of a bootstrap it may be desirable to have both ROM and RAM memory occupy the same address space selecting ROM instead of RAM for low order memory only when the system is reset system designed to use memory mapped I O which has actual memory occupying the memory mapped I O address space may need to inhibit RAM or ROM memory to perform its functions There are two essential requirements for a success ful inhibit operation The first is that the inhibit signal must be asserted as soon as possible within a maximum of 100 ns tcp after stable address The second requirement for a successful inhibit operation is that the acknowledge must be delayed taccp to all
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26. evice selects for the user A single line to implement a control data select function is provided by ADRQ 10 USER LOGIC MULTIBUS g CN ERN DEVICE J ADRO ADRF ADDRESS ux SELECTS DECODING cn 7 ADDRESS MWTC CONTROL TM RD IORC LOGIC pem P WRT IOWC P P D Ec XACK ACKNOWLEDGE acknomLense AACK INTERRUPT LINE BUFFERS INTERRUPT REQUEST LINES INTO INT7 Figure 6 GPSI Block Diagram Effectively this signal is used to select one of the two 8 device address groups yielding a total of 16 device addresses The control data line can also be used directly with Intel peripheral chips such as the 8251 GPSI may be configured to provide either direct or memory mapped I O for program access to its devices When direct I O is used the various devices are accessed by the addresses shown in Table 2 Table 2 GPSI ADDRESSING DEVICE C D 0 C D 1 1 0 x1 2 x2 X3 3 X4 X5 4 X6 X7 5 X8 X9 6 XA XB 7 XC XD 8 XE X hex digit assigned by jumper X is the same for all GPSI devices When the GPSI is configured for memory mapped I O the low order 8 bits of the 16 bit address are identical to those shown in Table 2 for direct I O However the upper 8 bits of the address must be all ones Thus the addressable devices occupy space within the upper 256 bytes of memory Hex to FFFF Hex THEORY
27. he memory address on the system address bus INH1 effectively allows ROM memory devices to override RAM devices when ROM and RAM memory are assigned the same memory addresses INH1 may also be used to allow memory mapped I O devices to override RAM memory INH2 Inhibit ROM signal prevents ROM memory devices from responding to the memory address on the system address bus INH2 effectively allows auxiliary ROM e g a bootstrap pro gram to override ROM devices when ROM and auxiliary ROM memory are assigned the same memory addresses INH2 may also be used to allow memory mapped I O devices to over ride ROM memory Data Lines DAT DATF 16 bidirectional data lines used to transmit or receive information to or from a memory location or I O port DATF being the most significant bit In 8 61 systems only lines DAT DAT7 are used DAT7 being the most significant bit Bus Contention Resolution Lines BCLK Bus clock the negative edge high to low of BCLK is used to synchronize bus contention resolution circuits BCLK is asynchronous to the CPU clock It has a 100 ns minimum period and a 3596 to 6596 duty cycle BCLK may be slowed stopped or single stepped for debug ging CCLK Constant clock a bus signal which provides a clock signal of constant frequency for unspeci fied general use by modules on the system bus CCLK has a minimum period of 100 ns and a 3596 to 65 duty cycle BPRN Bus prior
28. ited slave memory tacca must be known to ensure an adequate taccp In the worst case must be at least 1 5 microseconds The acknowledge delay circuit which will be described later provides for a maximum of approximately 800 nsec In situa tions where a 1 5 usec tAccp is required the clock frequency of the delay circuit must be halved or another device added to extend the selectable delay to 1 5 usec In this situation it may well be a better choice to disable the memory mapped I O in favor of the simple direct I O technique If the GPSI module is to reside in an Intel Micro computer Development System Intellec the memory mapped I O capability must be disabled This restriction exists because the Intellec has ROM program memory which occupies the entire memory mapped I O region to FFFFH and must not be overridden by the GPSI Bus Control Signal Propagation A pair of 74S32 OR gates A1 buffer the MRDC memory read command and MWTC memory write command inputs from the MULTIBUS These gates are enabled by the MMIO memory mapped I O signal from the high one address decoder The gated and buffered memory read and write commands are then each ORed and buffered with their respective I O read and write commands by a pair of 74810 NAND gates A5 The output of these gates are active high read and write com mands These commands are passed on to the advance transfer acknowledge generator via
29. ity in signal indicates to a particular master module that no higher priority module is requesting use of the system bus BPRN is synchronized with BCLK This signal is not bused on the motherboard BPRO Bus priority out signal used with serial daisy chain bus priority resolution schemes BPRO is passed to the BPRN input of the master module with the next lower bus priority BPRO is synchronized with BCLK This signal is not bused on the motherboard BUSY Bus busy signal driven by the bus master cur rently in control to indicate that the bus is currently in use BUSY prevents all other master modules from gaining control of the bus BUSY is synchronized with BCLK BREQ Bus request signal used with parallel bus prior ity network to indicate that a particular master module requires use of the bus for one or more data transfers BREQ is synchronized with BCLK This is not bused mother board Information Transfer Protocol Lines A bus master provides separate read write com mand signals for memory and I O devices MRDC MWTC IORC and IOWC as explained below When a read write command is active the address signals must be stabilized at all slaves on the bus For this reason the protocol requires that a bus master must issue address signals and data signals if write at least 50 ns ahead of issuing a read write command to the bus initiating the data transfer The bus master must kee
30. m number of Master devices 16 using parallel priority network 5 Maximum bus capacitance is 300 pF 16 APPENDIX C GPSI INTERFACE SCHEMATIC AND WIRE LIST FOLDOUT 17 SIGNAL NAME ADRO ADR 1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR8 ADR9 ADRA ADRB ADRC ADRD ADRE ADRF MRDC MWTC lOWC CCLK INIT XACK AACK DATAO DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 BOTTOM 1 57 A132 1 58 9 1 1 55 9 2 P1 56 9 3 P1 53 8 1 1 54 8 2 1 51 8 3 P1 49 7 9 P1 50 7 10 1 47 7 11 P1 48 7 3 1 45 7 4 1 46 7 5 143 7 1 P144 7 2 1 19 1 13 P1 20 1 9 P1 21 2 13 P1 22 2 5 P1 31 A128 P1314 A32 P1 23 13 1 25 A311 P173 A113 1 74 116 P171 A11 10 P1 72 11 13 P1 69 10 3 P1 70 106 P1 67 10 10 P1 68 A10 13 A1 74532 2 74510 8098 4 1K RP A5 7406 A6 7406 A7 74LS27 GPSI WIRE LIST SIGNAL NAME BASE ADR RD BD ENABLE 8A7 6A7 12A7 MMIO 4A14 11A1 8 1 12 2 6A2 8A14 CMD 2A14 4A4 INIT 6A9 Vcc Vss PARTS LIST BOTTOM 9 5 1 4 1 6 11 15 A1 3 A3 15 A11 1 A10 1 A7 8 A2 9 A7 6 A2 10 A7 12 A2 11 A4 3 A14 3 1 12 1 10 14 4 6 1 1 11 2 1 1 8 2 3 2 12 14 9 2 6 A14 5 A14 8 1 5 A13 4 A1 2 A14 2 A12 9 A4 4 A12 1 A3 3 A3 4 A9 6 A4 2 A4 16 A1 4 A11 15 A3 15 A14 3 A6 1 A2 1 A2 3 A14 9 A14 5 TOP A1 1 A10 15 A11 1
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32. ontrol of the bus but does not restrict the speed at which faster modules can transfer data via the same bus Once a bus request is granted single or multiple read write transfers can proceed The most obvious applications for the master slave capabilities of the bus are multi processor configurations and high speed direct memory access DMA operations However the master slave capabilities of the MULTIBUS are by no means limited to these two applications MULTIBUS SIGNAL DESCRIPTIONS This section defines the signal lines that comprise the Intel MULTIBUS Most signals on the MULTI BUS are active low For example the low level of a control signal on the bus indicates active while the low level of an address or data signal on the bus shows logic 7 17 value NOTE In this application note a signal will be designated active low by placing a slash character after the mnemonic for the signal Appendix A contains a pin assignment list of the following signals Initialization Signal Line INIT Initialization signal resets the entire system to a known internal state INIT may be driven by one of the bus masters or by an external source such as a front panel reset switch _ Address and Inhibit Lines ADRO ADRF 16 address lines used to transmit the address of the memory location or I O port to be accessed ADRF is the most significant bit INH1 Inhibit RAM signal prevents RAM memory devices from responding to t
33. oth the AC and DC requirements of the bus The AC require ments outline the timing of the bus signals and in particular define the relationships between the various bus signals On the other hand the DC requirements specify the bus driver characteristics maximum bus loading per board and the pull up down resistors AC Requirements The AC requirements are best presented by a dis cussion of the relevant timing diagrams Table 1 contains a list of the MULTIBUS AC requirements The most basic bus operations are those of read and write data transfers A majority of the user designed bus interfaces will provide a slave func tion with direct I O rather than memory mapped I O or master module capability Because of this you may only be interested in data transfers and can therefore skip the other timing diagrams dis cussed in this section MULTIBUS AC REQUIREMENTS 0 35 X 0 65 X tgcv Ons 100 ns Ons 10 ms Ons tXACK DXL 100 ns Bus Clock Period Bus Clock Width ns Address Setup Time ns Write Data Setup Time 50 ns Address Hold Time 50 ns Write Data Hold Time ns Read Data Setup Time Ons Read Data Hold Time Acknowledge Hold Time Relative to Active Command Relative to Active Command Relative to Command Removal Relative to Command Removal Relative to Acknowledge Relative to Command Removal Relative to Command Removal Acknowledge Delay Read Access Time 100 ns Command Pulse
34. oto type your application FUNCTIONAL PROGRAMMING CHARACTERISTICS This section briefly describes the organization of the GPSI from two points of view The principal functions performed by the hardware are identified and the general data flow is illustrated This first point of view is intended as an introduction to the detailed information provided in the next section Theory of Operation In the second point of view the information needed by a programmer to access the GPSI is summarized Functional Description Ihe function of the GPSI is to provide bus inter face logic which consists of those circuit elements most directly involved with communication be tween the bus master and the GPSI These ele ments include bus address control line receivers bidirectional data buffer device select decode logic transfer acknowledge generation and line driver circuits A functional block diagram of the GPSI is shown in Figure 6 Programming Characteristics The GPSI addressing provides 8 unique device selects and a single line which may be used to indicate control data The module s base address is assigned through the use of wire wrap connec tions on the prototype board Two such jumpers are part of the board s address decode circuit for system address bits ADR4 ADR7 They allow the selection of a base address for the GPSI on a 16 byte boundary Address bits ADR1 ADR3 are decoded by other logic to provide 1 of 8 d
35. ow the inhibited slave to terminate any irreversible timing operations initiated by detection of a valid command prior to its inhibit This situation may arise because a command can be asserted within 50 ns after stable address tas and yet inhibit is not required until 100 ns after stable address The acknowledge delay time tAccB is a function of the cycle time of the inhibited slave memory Inhibiting the SBC 016 RAM board for example requires a minimum of 1 5 psec Less time is typically needed to inhibit other memory modules For example the SBC 104 board requires 475 ns Figure 3 depicts a situation in which both RAM and PROM memory have the same memory ad dresses In this case PROM inhibits RAM produc ing the effect of PROM overriding RAM After ADDRESS DATA COMMAND DRIVER ENABLE SLAVE A RAM XACK LOCAL SEA SELECT Pad DRIVER ENABLE XACK SLAVE B PROM INH1 e LOCAL SU SELECT Figure 3 Inhibit Operation address is stable local selects are generated for both the PROM and the RAM The PROM local select produces the INHI signal which then removes the RAM local select and its driver enable Because the slave RAM has been inhibited after it had already begun its cycle the PROM XACK must be delayed taccg until after the latest possible acknowledgement from the RAM tacca Bus Control Exchange Operations The bus control exchange operation Figure 4 illustrates the rel
36. p address signals un changed until at least 50 ns after the read write command is turned off terminating the data transfer A bus slave must provide an acknowledge signal to the bus master in response to a read or write com mand signal MRDC Memory read command indicates that the address of a memory location has been placed on the system address lines and specifies that the contents of the addressed location are to be read and placed on the system data bus MRDC is asynchronous with BCLK MWTC Memory write command indicates that the address of a memory location has been placed on the system address lines and that a data word 8 or 16 bits has been placed on the system data bus MWTC specifies that the data word is to be written into the addressed memory loca tion MWTC is asynchronous with BCLK IORC I O read command indicates that the address of an input port has been placed on the system address bus and that the data at that input port is to be read and placed on the system data bus IORC is asynchronous with BCLK IOWC I O write command indicates that the address of an output port has been placed on the system address bus and that the contents of the system data bus 8 or 16 bits are to be output to the addressed port IOWC is asynchronous with BCLK XACK Transfer acknowledge signal the required re sponse of a memory location or I O port which indicates that the specified read write opera
37. rcuits INTEL MULTIBUS The Intel MULTIBUS includes the following signal lines 16 address lines 16 bidirectional data lines and 8 multi level interrupt lines The address and data lines are driven by three state devices while the interrupt and some other control lines are open collector driven Modules that use the MULTIBUS have a master slave relationship A bus master module can drive the command and address lines it can control the bus A Single Board Computer is an example of a bus master On the other hand a bus slave cannot control the bus Memory and I O expansion boards are examples of bus slaves Notice that a system may have a number of bus masters Bus arbitration results when more than one master requests control of the bus at the same time The bus clock is usually provided by one of the bus masters and is derived independently from the processor clock The bus clock provides a timing reference for resolving bus contention among multiple requests from bus masters For example a processor and a DMA direct memory access module may both request control of the bus This feature allows different speed masters to share resources on the same bus Actual transfers via the bus however proceed asynchronously with respect to the bus clock Thus the transfer speed is dependent on the transmitting and receiving devices only The bus design prevents slow master modules from being handicapped in their attempts to gain c
38. rmit field modification of base address assignments The initial step in designing the address decode portion of a MULTIBUS interface is to determine the required number of unique address locations This decision is influenced by the fact that address decoding is usually done in two stages The first stage decodes the base address producing an enable for the second stage which generates the actual device selects for the user logic A conveni ent implementation of this two stage decoding scheme utilizes a single decoder driven by the high order bits of the address for the first stage and a second decoder for the low order bits of the address bus This technique forces the number of unique address locations to be a power of two based at the address decoded by the first stage Consider the scheme illustrated in Figure 5 DECODER BASE ADDRESS SWITCH DECODER 2ND STAGE USER DEVICE SELECTS 1ST STAGE BASE ADDRESS DECODER Figure 5 Two Stage Decoding Scheme As shown in Figure 5 the address bits are used to produce switch selected data outputs of the first stage of decoding one of eight decoder has been used with two of the address bits Ag and A7 driving enable inputs The address bits A2 A9 enter the second stage decoder to produce 8 user device selects when enabled by an address that corresponds to the switch selected base address Address decoding must be completed before
39. s available on the MULTIBUS XACK allows the bus master to conclude its current instruction Another signat advanced acknowledge can be used in some 8080 based systems as an advance notification that requested data will be valid when the bus master is ready to use it This early acknowledge may decrease by one the num ber of Wait states needed to complete a read or write operation You should have a thorough knowledge of the 8080 as provided in the 8080 Microcomputer System User s Manual 98 153 before attempting to use AACK can be used in certain applications where an early acknowledgment to the 8080 is needed to allow it to proceed to the T3 state following the current T2 or Wait state Such applications have the following characteristics XACK is generated too late for the 8080 to detect it in the current state but l valid read data will be placed on the bus by the time the 8080 needs it in the current state or 2 write data will be accepted from the bus by the time the 8080 has completed its write operation In either case AACK is sent to the 8080 CPU based bus master early enough in the current state T2 or Wait to prevent the CPU from entering a subsequent Wait state The read or write transac tion is completed during the current T2 or Wait state and the CPU moves on to T3 It is important to note that XACK must be driven whether or not AACK is used This requirement exists because
40. the arrival of a command Since the command may become active within 50 ns after stable address the decode logic should be kept simple with a minimal number of layers of logic Furthermore the timing is extremely critical in systems which make use of the inhibit lines A linear select scheme in which no decoding is performed is not recommended for the following reasons First the scheme offers no protection in case multiple devices are simultaneously selected And second the addressing within such a system is restricted by both the lack of flexibility in base address selection and by the extent of the address space occupied by such a scheme BUS DRIVERS The Intel MULTIBUS requires three state drivers on the bidirectional data lines For user designed logic which simply receives data from the MULTI BUS this portion of the bus interface logic may only consist of buffers Buffers would be required to ensure that maximum allowable bus loading is not exceeded by the user logic In systems where the user designed logic must place data onto the MULTIBUS three state drivers are required These drivers should be enabled only when a memory read command MRDC or an I O read command IORC is present and the module has been addressed When both the read and write functions are re quired parallel bidirectional bus drivers e g Intel 8216 8226 are used A note of caution must be included for the designer who uses this type of
41. tion has been completed That is data has been placed on or accepted from the system data bus lines XACK is asynchronous with BCLK AACK Advanced acknowledge signal a bus signal used as a special acknowledge signal with 8080 CPU based systems AACK is an advance acknowl edge in response to a memory read or write command This signal allows the CPU to com plete the specified operation without requiring it to wait Interfaces which use AACK must also provide XACK This requirement must be met because not all bus masters will respond to the AACK signal AACK is asynchronous with BCLK Asynchronous Interrupt Lines INT INT7 8 Multi level parallel interrupt request lines used with a parallel interrupt resolution net work 0 has the highest priority while INT7 has lowest priority Power Supplies The power supply bus pins are detailed in Appen dix A which contains the pin assignment of signals on the MULTIBUS motherboard It is the designer s responsibility to provide ade quate bulk decoupling on the board to avoid cur rent surges on the power supply lines It is also recommended that you provide high frequency decoupling for the logic on your board Reserved Several bus pins are unused However they should be regarded as reserved for dedicated use in future Intel products OPERATING CHARACTERISTICS Beyond the definition of the MULTIBUS signals themselves it is important to examine b
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