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Manual - Phaedsys

1. 62 RW_READ8 RW_READ16 RW_READ32 RW_WRITE8 RW_WRITE16 RW_WRITE32 RW_ALL 5 Some mathematical manipulations are allowed Single instances of all but the RW_ALL values can be added together and single instances of each value may be subtracted from RW_ALL define ALL_READS RW_READ8 RW_READ16 RW_READ32 define NON_ACCESS32S_ RW_WRITE32 RW_READ32 In this example ALL_READS is defined as any read access be it an 8 16 or a 32 bit read cycle NON_ACCESS32S is defined as all 8 and 16 bit read and write cycles Register Enumerated Data Type Each target has its own enumerated data types for its own registers The following is a list of the enumerated registers for each target z eTPU Enumerated Registers TPU Enumerated Registers CPU32 Enumerated Registers CPU16 Enumerated Registers eTPU Register Enumerated Data Types The eTPU register enumerated data types provide the mechanism for referencing the eTPU registers These enumerated data types are used in commands that reference the TPU registers such as the register write commands that are defined in the Write Register Script Commandssection The following enumeration provides the mechanism for referencing the eTPU s registers enum REGISTERS _U32 REG P enum REGISTERS_U24 REG_A REG_B REG_C REG_D REG_DIOB REG_SR REG_ERTA REG_ERTB REG_TCR1 REG_TCR2 REG_TICK_RATE REG_MACH REG_MACL REG_P enum REGISTERS_U16 REG_TOOTH_PROGRAM REG
2. Executing to a precise time View node selection The active waveform The left and right cursors Bringing an out of view cursor into view Using the mouse The vertical yellow context cursor Scroll bars Waveform boundary time indicators Buffer data start indicator Context time indicator Current time indicator Left right and delta cursor time indicators Auto scroll the waveform display as the simulator executes Button controls Data storage buffer m TpuSim Logic Analyzer UART_RCV X UART_XMT v 000 000 0 uS Mouse 004 149 4 vS 008 000 0 uS Data Start 000 000 0 vS Context 004 479 1 uS Current Time 007 651 6 uS Set Left Cursor 002 191 1 vS Delta Cursor 000 936 0 vS Right Cursor 003 127 1 vS Executing to a Precise Time It is informative to consider how to execute the simulator to the precise time of the falling edge indicated by the arrow 1 shown in the picture below 135 Use the keyboards up and down arrows to highlight the UART_RCV waveform Drag the Left Cursor near to the desired edge using the mouse Snap to the actual edge using the left and right arrow keys on your keyboard In the picture below this edge is shown to occur at 2 191 1 microseconds Place the cursor over the field showing the time of the left cursor indicated by the second arrow An open hand ni will appear indicating that this time can be copied a dragging the time by holding the left mouse button down t
3. Takna RSE na Time Base Configuration TBCR TBCR 42018004 TCR2CTL 31 29 TCR2 Clock source is falling external TCRCLK Signal Physical tooth detection on falling TCRCLK pin edge TCRF 28 27 External TCRCLK signal is filtered by system clock 2 2 sample mode AM 25 25 ETPU ANGLE mode EAC is ENABLED TCR2P 21 16 TCR2 prescaler divides by 2 TCR2P 61 TCRICTL 15 14 TCR1 prescaler clock source is system clock 2 TCR1P 7 0 TCR1 prescaler divides by 5 TCRIP 64 TCR1 Period 166 6 nS SSSotsHTSseses Tooth Program Register TPR TPR 663B LAST 15 15 Not the last tooth MISSCNT 14 13 6 missing teeth IPH 12 12 No operation HOLD 11 11 Normal operation TICKS 9 6 63B 1 Angle ticks in the current physical tooth l 66 dec angle ticks in each tooth tick Saas SSasS Tick Rate Register TRR TRR 6S5F786 INT 17 9 62FB Integer part of TCR1 clocks in one angle tick FRAC 8 6 186 Fractional part of TCR1 clocks in one angle tick Timer Counter 2 TCR2 TCR2 66028F Rotations 8 Current Rotations Tooth Count Resets Tooth Ticks 34 Current tooth tick counts Angle Ticks 55 Current angle tick counts Angle 349 17 Current Angle CIERTO ONE Analyses sesdcsnes nnn nnn nnn nnn nnn Mode Normal PLL operating next physical tooth not yet detected TCRCLK Physical Tooth Detection Window Open a physical pin transition can be d
4. TestOpString ExprString The expression string ExprString can be numerical constants or simple symbolic expressions Constants can be supplied as decimal signed integers unsigned hexadecimal numbers prepended with 0x or floating point numbers A symbolic expression can be just a local global symbol or a simple expression such as V de reference V constant V member or V gt member where V is a symbol of the appropriate type TestOpString is a C test operator Supported operators are s gt gt lt lt amp amp and Il If the result of the specified operation on the expressions is 0 or false a verification error is generated at_code_tag amp amp TestlHere amp amp verify_val FailFlag 0 In the example above the target is run until it gets to the address associated with the source code 35 that contains the text amp amp TestlHere amp amp Once this address is reached the value of symbol FailFlag is read and a verification error is generated if it does not equal ze ro verify_str SymbolString TestOpString CheckString If a character pointer is resolved from SymbolExprString then the string at that location is compared to CheckString using the comparator specified in TestOpString If the outcome of this is true non zero the verification test passes otherwise a failure is reported Supported comparator operators are gt and lt Greater than and
5. 0 1MhZ Frequency is expressed in MHz this is a modification of a previous version of the User Manual frequency 0 1 CREATE DEFINE THE SYNCH WAVE FORM This generates a one degree 10us pulse every 360 degrees 3600us wave SYNCH synch_pulse 1 synch_wait 364 end CREATE DEFINE THE SPARK WAVE FORM Each spark is equally spaced every 1 2 revolution or 180 degrees 1800us Each spark plug triple fires and each fire lasts one degree 10us In addition there is a 17 degree 170us lag of this wave form relative to the synch wave form wave SPARKS no_fire 17 This creates a 17 degree lag Enclose the following in a bracket to generate a loop The first plug fire cycle lasts five degrees 50us The spark plug fires three times firel 1 no_fire 1 firel 1 no_fire 1 firel 1 The delay between fire cycles is 180 degrees less the five degree fire cycle 180 5 175 degrees no_fire 175 The third plug fires next fire3 1 no_fire 1 fire3 1 no_fire 1 fire3 1 Give another 175 degree delay no_fire 175 The second plug fires next fire2 1 no fire 1 fire2 1 no_fire 1 fire2 1 Give another 175 degree delay no_fire 175 The fourth plug fires next fire4 1 no_fire 1 fire4 1 no_fire 1 fire4 1 Give another 175 degree delay no_fire 175 Enclose the loop and put the infinity character end The following wave form is generated from the above example 73
6. ALL_SPACES RW_ALL 2 3 In this example even accesses are set to two clocks per access and odd accesses are set to three clocks per access In this example these settings apply to all address spaces and for all read and write accesses though it is possible to indicate the specific set of address spaces and access types for which this applies Address Fault Control For each address space and access type an address fault can be set to occur on odd accesses Note that this is generally not applicable to 8 bit accesses though it is still available define CODE_SPACE CPU32_SUPV_CODE_SPACE CPU32_USER_CODE_SPACE set_block_to_addrs_fault MyCpu Rom CODE_SPACE READ_ALL In this example odd read accesses to the memory block s code space are configured to cause an address fault Bus Fault Control For each address space and access type a bus fault can be set to occur set_block_to_bus_fault MyCpu Rom CPU32_USER_CODE_SPACE RW_ALL In this example any access while at the user privilege level result n a bus fault This might be useful in a protected system in which a user process is prevented from accessing hardware Sharing Memory A fundamental aspect of multiple target simulation is the ability to share memory MtDt employs docking to implement shared memory If two targets are to share memory one target must dock memory blocks to another target There is a fundamental and important lack of symmetry in that one
7. SIMCR EXOFF F F CLKOUT Pin On FRZSW E E On FREEZE the watchdog amp periodic interrupt timer are Off FRZBH D D On FREEZE the bus monitor is Off SLUEN B B The IMB is Not Available to external bus master SHEN 9 8 Show Cycles Enable is 66 SUPU 7 7 SIM SZU registers access at Supu priviledge level MM 6 6 Internal modules at FFF O66 FFFFFF IARB 3 6 SIM interrupt arbitration priority F SYNCR 5F68 W F F W freq ctrl VCO multiplied by 1 x E E X freq ctrl UCO divided by 2 IY D 8 Y freq ctrl VCO divided by 1F 1 Clock frequency is 8 388668 MHz assuming 32 768 KHz crystal EDIU 7 7 ECLK pin addr 23 divide rate is system clock divided by 8 SLIMP 4 4 Crystal reference is ok SLOCK 3 3 UCO is locked or external RSTEN 2 2 Loss of reference causes limp mode STSIM 1 1 During low power stop SIM clock is driven by an external source STEXT 6 6 During low power stop the CLKOUT pin is held low RSR 66 EXT 7 7 Reset caused by an external signal No Pow 6 6 Reset caused by the power up reset circuit No sw 5 5 Reset caused by a software watchdog timeout No HLT 4 4 Reset caused by the halt monitor No Loc 2 2 Reset caused by a loss of clock No SYS 1 1 Reset caused by a RESET instruction No TST 6 6 Reset caused by the test submodule No SYPCR 86 SWE 7 7 The software watchdog is ENABLED SUP 6 6 First watchdog prescaler is divide by 1 SUT
8. s parameter RAM word 3 bit 14 is verified to be equal to 1 If the value is indeed equal to 1 then the simulation continues If the bit is instead a zero an error message is printed to the screen For instance if channel 10 s RAM word three is equal to 4000 hex the verification would pass while if it were instead equal to zero the test would fail and an error message would be displayed eTPU TPU Host Service Request Register Script Commands write_chan_hsrr ChanNum Val This command writes channel ChanNum s HSRR bits to value Val write_chan_hsrr 4 0 In this example channel 4 s HSRR bits are written to zero If channel 4 had a pending host service request it would be cleared TPU Channel Interrupt Service Register Script Commands clear_cisr ChanNum This command clears a Channel Interrupt Service Request CISR from channel ChanNum This command accepts a single argument clear_cisr 7 In this example the CISR is cleared from channel 7 clear_this_cisr This command clears the CISR of the active channel from within an ISR script commands file Note that in the primary script commands file there is no channel context so this command cannot be used and use of this command generates a warning message No arguments are required with this command clear_this_cisr Assume in this example that an ISR script commands file that is associated with TPU channel 3 executes this command This file gets executed upon assertion
9. t 0 Concatenation It is often desirable to concatenate stings The following exa mple illustrates a case in which this is particularly useful define TEST_DIR _ TestDataFiles read_behavior_file TEST_DIR Test bv vector TEST_DIR Example C Style Escape Sequences In the C language special characters are specified within a string using the backslash character For instance a new line character is specified with the backslash character followed by the letter wo n or n The character following the backslash character is treated as a special character The following special characters are supported References a backslash character File dat Planned Obsolescence of Single Backslash within Strings In previous versions of this software a Gstyle escape sequence was not supported and a single backslash character was treated as a just that a single backslash character In anticipation of future software versions supporting enhanced Gstyle escape sequences the single backslash character within a string now causes a warning ASH WARE recommends using a double backslash to ensure compatibility with future versions of this software The following string causes a warning File dat Script Commands Groupings Listed below are the available script command functional groups Clicking on the desired command functional group will access the command listing for that group All Target Types Script Comm
10. 24 MtDt Build Script Commands File Naming Conventions In order to prevent future installations of ASH WARE software from overwriting build script files that you have created or modified ASH WARE recommends that you follow the following naming convention g Build script files from ASH WARE begin with zzz Build script files not from ASH WARE don t begin with zzz The string zzz was chosen so that these files would appear at the end of a directory listing sorted by file name ASH WARE recommends that when you modify a build batch file you remove the letters zzz from the file name When you create a new file ASH WARE recommends that the file name not begin with the string zzz The following is a list of some of the build batch files loaded by the ASH WARE installation utility zzz_ TpuSim MtDtBuild 7 zzz_2Sim32_1TpuSim MtDtBuild zzz_1Sim32 MtDtBuild zzz_1Bdm32 MtDtBuild How would you modify the zzz_1Sim32 MtDtBuild file to create a larger RAM ASH WARE recommends the following procedure Copy file zzz_1Sim32 MtDtBuild to file BigRamSim32 BuildScript Modify file BigRamSim32 BuildScript Script Commands File Format and Features The script commands file must be ASCII text It may be generated using any editor or word processor such as WordPerfect or Microsoft Word that supports an ASCII file storage and retrieval capability The following is a list of script command features Multiple target scripts Dir
11. 6626 a 6166 diob 61B4 sr 1A99 ert 1EAF p 66 68 6668 dec F link 6 chan D A Bus 6669 B Bus 6666 Result 6668 BRANCH PLA FLAGS clr Flag2 clr Flagi SET clr Flag 8 SET clr HSQ1 clr MRL SET HSQ6 clr TDL clr PSL clr LSL clr PIN ScoZzOn This window displays the information associated with the microengine registers and the branch PLA flags The A bus source B bus source and result before any shifting are also displayed The ERT register is that of the active channel An important consideration is that the branch PLA flags are for the most part latched on a time slot transition Therefore they do not necessarily match the values displayed in the channel windows The following list shows those branch PLA flags that may change during a channel service routine The four execution unit flags Z C N and V are latched whenever the CCL is specified on an AU subcommand is The Pin State Latch PSL gets latched two microinstructions after the CHAN_REG is written FLAG2 FLAGI and FLAGO are always input directly to the branch PLA They are not latched at all Two microinstructions after the CHAN_REG is changed these flags reflect the new channel When MtDt is in TPU2 or TPU3 mode the FLAG2 flag and PIN branch conditional are displayed FLAG2 is an additional TPU2 flag similar to the existing FLAG and FLAGO flags PIN branch conditional is a new branch condition available in the TPU2 that is
12. 7 highest IVB 7 0 Interrupt vector base is 3C l l 2 1sb s cannot be written and always read 8 QACRG 6133 MUX F F Internally multiplexed 16 possible channels PSH 8 4 PSH 13 gt Prescaler clock hi time is 661 192 1 ns PSA 3 3 QCLK high and low times are not modified PSL 2 0 PSL 3 gt Prescaler clock lo time is 666 238 4 ns QACR1 6066 CIE1 F F Queue 1 completion interrupt is disabled PIE1 E E Queue 1 pause interrupts are disabled SSE1 D D Enables a single scan after trigger event l This bit always reads as a zero MgQ1 A 8 Disabled mode conversions do not occur QACR2 6627 CIE2 F F Queue 2 completion interrupt is disabled PIE2 E E Queue 2 pause interrupts are disabled SSE2 D D Enables a single scan after trigger event l This bit always reads as a zero Q2 C 8 Single scan mode 3 6 6 Interval is micro seconds l Disabled mode conversions do not occur QASR 6666 CF1 F F Queue 1 scan is not complete PF1 E E Queue 1 has not reached a pause CF2 D D Queue 2 scan is not complete PF2 C C Queue 2 has not reached a pause TOR1 B B No queue 1 trigger events have occured TOR2 B B No queue 2 trigger events have occured Qs 9 6 Queue 1 idle Queue 2 idle CWP 5 80 Conversion Command Word 66 is currently or last executed The QADC Main window displays the QADC Module Configuration Register QADCMCR the QADC Interrupt Register QADCINT
13. Logic Analyzer uaRT_RcV UART_RCV Tal Vv 7 ii 225 LO oo p Data Start 000 000 0 vS Context 000 000 0 uS Current Time 006 229 3 vS Set Left Cursor 001 047 1 uS Delta Cursor 005 132 1 vS Right Cursor 006 179 2 uS The simulation can execute to precisely the left or right cursor s time by dragging and dropping the time into the current time as explained in the Executing to a Precise Time section The cursor can also be moved by dragging and dropping a time into a vertical cursor s time indicator Left Right and Delta Cursor Time Indicators The left and right time cursor time indicators show the time associated with the respective vertical cursors The Delta Cursor indicator shows the difference in time between the left cursor and the right cursor These time indicators are capable of extremely precise time measurement with accuracies approaching one femto second This is because the cursors can be snapped to the precise pin transition time using your keyboard s left and right arrow keys Mouse Functionality In the waveform display panel the mouse has two purposes It is used to provide a goto time function and also is used to move the left and right cursors To get MtDt to execute to a particular point in time move the mouse to a location corresponding to that time and click the right mouse button If the selected time is earlier than the current Simulator time MtDt automatically resets be
14. This causes one action to be performed This action may be execution of a single instruction execution of a script command or simply a tick of the CPU clock This is helpful for advancing execution by as small an amount of possible allowing you to really zoom in on a problem Script This runs MtDt until one script command from the active target is executed If no new script commands become available MtDt continues to run until stopped by selecting the Stop submenu in the Run menu Time Slot This runs MtDt until a TPU time slot transition occurs MtDt stops just before execution of the first microinstruction of the TPU channel service routine If no time slot transitions occur MtDt continues to run until stopped by selecting the Stop submenu in the Run menu Assembly This runs the active target until a single assembly instruction occurs If instructions occur MtDt continues to run until stopped by selecting the Stop submenu in the Run menu Assembly N This runs the active target until a user specified number of assembly instructions occur A dialog box opens allowing specification of the desired number of assembly instructions If no assembly instructions occur MtDt continues to run until stopped by selecting the Stop submenu in the Run menu Help This accesses this help screen 158 Run Menu Goto Cursor This runs MtDt until an instruction associated with the current cursor location is about to be executed or a breakpoint
15. This window displays common TPU CPU registers whose function is primarily to control These registers include the Channel Function Select Registers CFSRs Channel Priority Registers CPRs the Host Service Request Register HSRR the Host Sequence Registers HSQRs and the Channel Interrupt Service Request Register CISR Each register is broken down by TPU channel so that the value for each channel is easily found All register values are displayed in both binary and hexadecimal formats The user can modify the value of each of these registers in a repeatable fashion via the script commands file Alternatively these registers an be modified directly using the keyboard and mouse See the Script Commands File Window section for an explanation of this capability The TPU affects the states of the registers in the normal execution of its microcode For example the HSRR bits for a TPU channel are cleared when the microengine services that channel TPU Scheduler Window Availability TPU Simulation Target F E DC BAY 8 7 6 5 3 2 1 86 Prty D HH H H H HH Srl 6 61 6 6 6 6 6 6 6 6 6 6 6 6 B S gl 6 61 6 6 6 6 6 6 6 6 6 6 6 6 B6 HSRR 66 66 66 66 66 66 66 66 AA 66 66 66 66 66 66 A LSR 6 6 6 6 6 6 6 6 Q A 6b AGAGAGAB M TSR 6 6 1 6 6 6 6 6 6 6 6 6 6 6 6 Time Slot Assignments Med Hi Hi Med Hi Lo Hi The TPU s microengine responds to the various channels based on a round robin scheduler The scheduler bases its serv
16. To associate workshops with targets see the Workshops Options Dialog Box section In that section there are descriptions of putting workshop buttons on the toolbar renaming workshops or automatically giving a workshop the same name of its associated target and associating workshops with targets When a target is assigned to a workshop the windows associated with that target are automatically made visible within the assigned workshop It is often desirable to override this either to make individual windows visible in multiple workshops or to remove window from specific targets See the Occupy Workshop Dialog Box section for a detailed description of how this is done 86 OPERATIONAL STATUS WINDOWS Overview The target state is displayed in various operational status windows These windows correspond to the various functional blocks associated with the specific target Each of these windows can be re sized scrolled iconized minimized and maximized Multiple instances of each window may be opened Below is a listing of all operational status windows Window Groups Common Windows The following windows are available on multiple target bevy Threads Window Source Code File Windows Script Commands File Windows 2 Watch Window Local Variables Window Call Stack Window Trace Window Complex Breakpoint Memory Dump Window Timers Window Logic Analyzer eTPU Specific Windows The following windows are ava
17. allowed Assuming the EPSCKE bit is set the clock frequency fed to the TCR1 prescaler is the system clock divided by the TCR1 enhanced prescaler where the enhanced prescaler is equal to EPSCKV plus times 2 write_epscke 1 write_epsckv 20 write_tcr1_prescaler 2 Available in all TPUs The three commands in this example set the TCR counter to increment at 99 87 KHz assuming the CPU clock is set to 16 778 MHz write_tcr2psck2 Val This command writes the TCR2 pre divider prescaler The only allowed values are 0 and 1 This with the next command select the system clock 8 write_t2cg 1 write_t2csl 0 Set the TCR2 prescaler to divide by 8 write_tcr2_prescaler 3 Set the pre divider prescaler to divide by 2 write_tcr2psck2 1 The above script command sequence sets the TCR2 counter to be clocked at the system clock frequency divided by 128 TPU Bank and Mode Control Script Commands set_tpu_type X Y MtDt automatically determines the TPU type from the source TPU microcode so this command is not normally required except for the TPU3 in which TPU2 should be specified because bug in the Freescale TPU assembler prevents selection of TPU3 so this script command is required to specify a TPU3 target In addition there are subtle differences among the TPUI TPU2 and TPU3 that the TPU assembler hides from the user Use of this instruction can cause significant behavioral 51 deviations between MtDt and the actual
18. and Technical Support Version 3 41 3 40 3 20 3 10 3 00 2 1 and 2 0 Enhancements Supported Targets and Available Products Full System Simulation Project Sessions Source Code Files Script Commands Files Script Commands Groups Test Vector Files Functional Verification External Logic Simulation Integrated Timers Workshops Operational Status Windows Dialog Boxes Menus Hot Keys Toolbar Status Window 12 OVERVIEW Multiple Target Development Tool MtDt is a technology from which a variety of products are derived This manual covers all the current MtDt products These products include single and multiple target simulators and hardware debuggers MtDt has been developed using an object orientated and layered approach such that the bulk of the code within MtDt can be applied to any target It matters little if the target is big endian or little endian 8 16 32 or 64 bits hardware debugger or simulation engine This allows us to quickly and inexpensively provide support for additional targets Targets and Products From a tools development standpoint there is very little to differentiate one target from another CPUs execute code while peripherals have a host interface and wiggle and respond to I O pins Hardware interfaces provide different means to the same end Current MtDt targets include a eTPU simulation engine a TPU simulation engine a CPU32 simulation engine a CPU16 simulation engine and a CPU32 across a
19. important tool for determining the performance of your code Two important columns are WC Steps and WC Time These display the worst case number of execution steps including flushes and execution time also including flushes for that thread Note that this thread will normally execute many many times in the course of a simulation run and each time the thread executes it may take a different path such that the execution time may vary The worst case number shows the very worst longest amount of time that the thread takes to execute through the entire simulation run Finding a Thread s Source Code To find the line of source code for each thread move the cursor within the thread window The first source code line of that thread automatically pops into view and turns yellow as shown below eTpu1 Source eTPU etpuc_arinc mc lol x Ff IE HE HE IE IE IE E JE JE IE E JE JE JE E JE JE JE E JE JE JE IE JE JE JE E JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE E JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE EFEN Received an expected data bit bits 24 31 else if IsTransitionhEvent amp amp flag 0 amp amp iagi RECEIVED_DATA_BIT_24_31 shift_reg data data31_24 gt gt 1 shift_reg dataB data31_31 chan_ eg dataC data _8 THREAD Cou Cnt 171 2 i 360 nS INITIALIZE 174 646 NS RE_INIT_INTERRUPT 1 4 506 nS RECEIVED DATA BIT 6 23 VALID_GAP_AND_DATA UALID_G
20. is displayed User defined tests are part of script commands files See the Script Commands Groupings section for a description of the various script commands that support user defined tests CPU32 Simulator Busses Window Availability CPU32 Simulator MySim32 Busses Ioj x Instruction Sub Instruction Instruction Size This is a 16 bit Word instruction areas A BUS Source 16 Bit 1234 Addr 66666266 Operand Address Register Indirect with Data16 Displacement Space Supervisor Data Space Sees B BUS Source 16 Bit FO6FG Destination 16 Bit 6324 Operand Data Register Space s cS anne CLOCKS Instruction Fetch A Bus Load 3 B Bus Load 8 Instruction min 2 B Bus Store 6 The CPU32 Simulator Busses window displays detailed information regarding the just executed instruction This includes the data flow within the simulated CPU32 the data flow between the simulated CPU32 and external memory and timing information CPU32 Simulator Interrupt Window Availability CPU32 Simulator 131 32 Host32 Interrupts ioj x Source Vec Lul IARB Time Clocks Ej TpuSin 8 40 3 2 004 796 8 6660613A66 TpuSim E 4E 3 2 664 796 8 000013A 0 TpuSin F 4F 3 2 664 796 8 666613N66 No more pending interrupts No more pending interrupts X ET Z The CPU32 Simulator Interrupt window displays detailed information regarding the currently pending CPU32 interrupts Towards the top are the highest priority first
21. script commands provide the capability to verify that minimum coverage percentages have been achieved A discussion of this topic is found in the Code Coverage Analysis section The following are the script commands that provide these capabilities write_coverage_file Report Coverage verify_file_coverage MyFile uc instPct braPct verify_all_coverage instPct braPct II eTPU Only Stat verify_file_coverage_ex MyFile c instPct braPct entPct Nea verify_all_coverage_Ex instPct braPct entPct The write_coverage_file command generates a report file that lists the coverage statistics Statistics for individual files are listed as well as a cumulative file for the entire loaded code The verify_file_coverage and verify_file_coverage_ex commands are used as part of automation testing of a specific source file The instPct and braPct parameters are the minimum required branch and coverage percentages in order for the test to pass The entPct parameter is the 38 minimum require entry percentage and is available only in the eTPU simulator These parameters are both expressed in floating point notation The valid range of coverage percentage is zero to 100 Note that for each branch instruction there are two possible branch paths the branch can either be taken or not taken Therefore in order to achieve full branch coverage each branch instruction must be encountered at least twice and the branch must both be taken and n
22. the QADC Control Registers 0 1 and 2 QACRO QACRI1 QACR2 and the QADC Status Register QASR QADC Ports Window Availability 683xx Hardware Debugger 128 32 My68376 QADC Ports loj x DDRQ 7166 AN59 F F Input 6 PORTQ 4166 ANSS E E PQA 6 Output 1 ANS D D PQA 5 Output 8 ANS6 ETRIG2 C C PQA 4 Output 8 ANSS ETRIG1 B B PQA 3 ANSS Input 8 ANS4 MA2 A A PQA 2 ANS4 Input 8 AN53ZMA1 9 9 PQA 2ZAN54 Input 6 ANS2 MAB 8 8 PQA 2 Output 1 AN51 7 7 PQB 7 A51 always 8 AN58 6 6 PQB 6Z A50 always 8 AN49 5 5 PQB 5 A49 always 8 AN48 4 4 PQB 4ZA48 always 8 AN 3 ANz 3 3 PQA 3 AN3 8 AN 2 ANY 2 2 PQA 2 AN2 8 AN 1 ANx 1 1 PQA 1 AN1 8 AN 6 ANW 6 6 PQA 6 ANG 8 The QADC Ports window displays the QADC Port Data Direction Register DDRQA and the QADC Port A and B registers PORTQA PORTQB QADC Channels Window Availability 683xx Hardware Debugger 32My68376 QADC Channels E 10 x P PAUSE after executing current CCW l BYP Use BYPASS amplifier RESULTS l l l IST Input sample time ns RHT LFT LFT l CHAN JST JST JST CCW X VAL 9 9 8 8 7 6 5 8 UNS SND UNS 5 B FF no 16 QCLK s 022 888 2 3F gt PQA 6 ANG 62FF 3FC BFCA 1 3FF PAUSE YES 16 QCLK s 022 888 2 3F gt PQA 6 ANG 0357 55C0 D5CO 2 O3FF PAUSE YES 16 QCLK s 022 888 2 3F gt PQA 6 ANG 613F CFCG 4FCO 3 62D9 PAUSE no 16 QCLK s 622 888 2 19
23. the future because using this feature the concept of past events is dropped All events are effectively considered to occur in the future This field is displayed in the Channel window Setting the TPU Mode MtDt automatically sets the TPU mode when the source microcode files are parsed The type command is located and the appropriate TPU mode TPU1 TPU2 or TPU3 is set based on the values of this field MtDt also supports a script command described in the TPU Bank and Mode Control Script Commands section for setting the TPU mode Use of this command is highly discouraged since there are subtle differences among the TPU1 TPU2 and TPU3 that the TPU assembler hides from the user Support for TPU3 Version 2 1 of MtDt supports the TPU3 The following is a list of new and supported features of the TPU3 Enhanced TCR prescaler 2 TCR2 pre divider prescaler TCR2 controllable clock edge rising falling or both The prescaler options listed above are accessible using script commands described in the TPU Clock Control Script Commands section 168 CPU32 Simulation Engine The CPU32 is sold on a number of Freescale microcontrollers including the very popular 68332 The CPU32 Simulation Engine can be used both in stand alone mode and in conjunction with other CPUs and peripherals including multiple CPU32s CPU32 Hardware across a BDM Port The 683xx line of microcontrollers can debugged using this BDM Debugger CPU16 Simulati
24. 0 4 8 that 24 bit numbers must be located on a single odd boundary 1 5 9 that 16 bit accesses must be located on even boundaries 0 2 4 and that 8 bit numbers can be on any address boundary define UART_CHAN 12 write_chan_data32 UART_CHAN 0x20 0xC6E2024 lt A verify_chan_data32 UART_CHAN 0x20 0xC6E2024A verify_chan_data24 UART_CHAN 0x21 0xE2024 lt A verify_chan_datal6 UART_CHAN 0x20 OxC6E2_ verify_chan_data16 UART_CHAN 0x22 0x024A verify_chan_data8 UART_CHAN 0x20 0xC6 j verify_chan_data8 UART_CHAN 0x21 0xE2 verify_chan_data8 UART_CHAN 0x22 0x02 verify_chan_data8 UART_CHAN 0x23 0x44 In this example channel 12 s data a an address offset of 0x20 relative to that channel s base address word is written with a 32 bit value 0xC6E2024A hex The written value is then verified as 32 24 and 8 bit sizes In the Byte Craft eTPU C Compiler the address offset can be automatically generated using the following macro pragma write h define MY_ADDR_OFFSET ETPUlocation Pwm MyFuncVar eTPU Channel Base Address Script Commands write_chan_base_addr ChanNum Addr This command writes channel ChanNum s address Addr Note that this writes the CPBA register value define PWM1_CHAN 3 define PWM2_CHAN 4 define PWM1_CHAN_ADDR 0x300 define PWM2_CHAN_ADDR PWM1_CHAN_ADDR PWM_RAM write_chan_base_addr PWM1_CHAN PWM1_CHAN_ADDR write_chan_base_ad
25. 3 U32 valid range is 0 to OXFFFFFFFF U64 valid range is 0 to OxFFFFFFFFFFFFFFFF Referenced Memory in Script Commands Files Memory can be directly accessed by referencing an address Two parameters must be available for this construct an address and a memory access size In addition there is an implied address space which for most targets is supervisor data For some targets the address space may be explicitly overridden U8 ADDRESS References an 8 bit memory location U16 ADDRESS References a 16 bit memory location U32 ADDRESS References a 32 bit memory location 7 U64 ADDRESS References a 64 bit memory location bg U128 ADDRESS References a 128 bit memory location The following are examples of referenced memory constructs Note that these examples do not form complete script commands and therefore in this form would cause load errors U8 0x20 Refers to an 8 bit byte at address 0x20 U32 0x40 Refers to a 32 bit word at address 0x40 Assignments in Script Commands Files Assignments can be used to modify the value of referenced memory a practice commonly referred to as bit wiggling Using this it is possible to set clear and toggle specific groups of bits at referenced memory The following is a list of supported assignment operators gS Assignment Arithmetic assignment of addition and subtraction 7 t S Arithmetic assignment multiply divide and rema
26. 5 4 Additional watchdog prescaler is 2 X9 l Watchdog period is 015 625 0 micro seconds assuming 32 768 KHz C HME 3 3 Halt monitor function Disabled BHE 2 2 Bus monitor is Disabled for external bus cycles BHT 1 0 Bus monitor timeout is 64 system clocks PICR 6800F PIRQL A 8 Interrupt priority disabled PIV 7 0 Periodic interrupt vector OF PITR 66606 PTP 8 8 First periodic interrupt timer prescaler is divide by 1 PTH 7 0 Additional periodic interrupt timer prescaler is 66 1 I l Periodic interrupt timer period is 666 122 1 micro seconds assur m mii The SIM Main window displays the Module Configuration Register SIMCR the Clock Synthesizer Control Register SYNCR the Reset Status Register RSR the System Protection Control Register SYPCR the Periodic Interrupt Control Register PICR and the Periodic Interrupt Timer Register PITR SIM Ports Window Availability 683xx Hardware Debugger 114 32 MyBdm32 SIM Ports oy x xxxxx PORT C DATA AND CHIP SELECT PIN ASSIGNMENT REGISTER 1 xxx PRIMARY ALTERNATE DISCRETE BITS PORTC S16 ADDR23 ECLK 9 8 16 Bit CS CSPAR1 6355 CS9 ADDR22 PC 6 7 6 ADDR22 css ADDR21 PC 5 5 4 ADDR21 CS7 ADDR26 PC 4 3 2 ADDR26 CS ADDR19 PC 3 1 6 ADDR19 xxx PORT C DATA AND CHIP SELECT PIN ASSIGNMENT REGISTER O xxx PORTC 7F CSS FC2 PC 2 D C 16 Bit CS CSPARG 3FFF CS4 FC1 PC 1 B A 16 Bit CS Cs
27. 6 6 86 6 66661 A 41 Time Slot Assignments Med Hi L Hi i n The eTPU s microengine responds to the various channels based on a round robin scheduler The scheduler bases its servicing decisions on the Channel Priority Register CPR the Service Request Latch SRL and the Service Grant Latch SGL These latches are affected by the Host Service Request Register HSRR the Link Service Requests LSRs and the Match or Transition Service Requests M TSRs which are also displayed The M TSR is generated from the Match Recognition Latch MRL Transition Detection Latch TDL and the Match Transition Service Request Inhibit SRI latch The M TSR is formed from the following logical expression MRL and TDL or SRI Each register s broken down by eTPU channel so that the value for each channel is easily found Most of these registers can be modified only by the eTPU eTPU Execution Unit Registers Window oxi tcr ELEELE 000000 ert 666666 000000 p 64 C3226C diob C22ABD sr 4E1EC a b 84317A 3B4A62 c d 3E23D1 D5676F rar 6666 link 66 chan 66 Bus 666666 666666 Result 666666 MAC FD66F3 3E7DE9 BRANCH PLA FLAGS SET MZ SET SET WC SET SET MN clr clr MU clr LSR clr MBsy clr MRLA clr MRLB clr TDLA clr TDLB clr Fi clr FMO clr PSS clr PST clr P6116 61686 ScoZOn The Timer Counter Global Registers TCR1 TCR2 are displayed The Event Register Timers for action units A and B are displayed ERTA ERT
28. A When the target hits the start address of an armed timer the timer state changes to started When the target hits the stop address the timer state changes to finished MtDt then computes the amount of time it took to get from the timer start address to the timer stop address and this information is displayed in both clock ticks and micro seconds in the timer s window An overrun occurs when a timer exceeds the capacity of the timing device For the simulated timers the limitation is IE96 femto seconds of simulated time This corresponds to 1E72 years of simulated time This is significantly less ominous than Y2K Virtual Timers in Hardware Targets For targets that do not support the full number of timers that MtDt supports the concept of virtual timers is introduced MtDt remembers the start and stop addresses of all 16 virtual timers The arming of any virtual timer causes a hardware timer to be assigned to that virtual timer If more virtual timers are armed than are actually supported by the target hardware s timing device then the last armed virtual timer is automatically disabled 85 WORKSHOPS Workshops bring order to a chaotic situation The problem is that with multiple targets each of which have many windows the number of windows may become overwhelming In fact it may become so overwhelming that without workshops the multiple target simulator would be unusable Workshops allow you to group windows together and view o
29. All tests are done endif _ ASH _WARE_AUTO_RUN 58 Determining the Interrupt Number ISR script commands execute in response to an enabled and asserted interrupt as described in the ISR Script Commands Files section On the eTPU TPU each of these script commands has a unique number as follows eTPU Targets Channel interrupts for channels 0 31 are numbered 0 31 Data interrupts for channels 0 31 are numbered 31 63 ye The global exception interrupt number is 64 TPU Targets Channel interrupts for channels 0 15 are numbered 0 15 The define is formed using the target name as follows _ASH_WARE_ lt TargetName gt _ISR_ When running under a target named ETPU the ISR script loaded for channel 25 s channel interrupt is automatically defined as follows define ASH WARE_ETPU_ISR_ 25 If this same script command file is also loaded for the DATA interrupt then the automatic define would be as follows define _ASH WARE_ETPU_ISR_ 57 An example of how this can be used is as follows define THIS ISR NUM _ASH_WARE_ETPU_ISR_ define THIS CHAN_NUM _ASH_WARE_ETPU_ISR_ amp 0x1F clear_this_intr Write a signature to indicate that this ISR ran write_chan_data24 THIS_CHAN_NUM 0xD 0xFD12A4 THIS_ISR_NUM Passing Defines from the Command Line When launching the simulator or debugger application it is often useful to pass define directives to the primary script commands file fro
30. Build E Mtdt Gui TESTFILES BuildScripts 2Sim16_1TpuSim MtDtBuild Source Code make asc Script No File Open Script Report No File Open Script Startup No File Open Test Vector Example Vector Build No File Open Master Behavior No File Open ISR Files Isr 6 No File Open Isr 1 No File Open Isr 2 No File Open Isr 3 No File Open Isr 4 No File Open Isr 5 No File Open Isr 6 No File Open Isr 7 No File Open Isr 8 No File Open Isr 9 No File Open Isr A No File Open Isr B No File Open Isr C No File Open Isr D No File Open Isr E No File Open Isr F No File Open Clocks Counters The simulated CPU clock frequency is displayed The TCR1 prescaler TCR2 prescaler PSCK control bit and T2CG control bit are displayed When MtDt is in TPU2 mode the DIV2 and T2CSL control bits are displayed These control bits 106 which are new to the TPU2 add capabilities to the TCR1 and TCR2 counters These control bits are automatically hidden when in TPU1 mode since they apply only to the TPU2 These bits are controlled using script commands described in the TPU Clock Control Script Commands section When MtDt is in TPU3 mode the enhanced prescaler enable bit ESPCKE the enhanced prescaler bit ESPCK and the TCR2 pre divider prescaler enable bit TCR2PSCK2 are displayed These control bits which are new to the TPU3 add capabilities to the TCR1 and TCR2 counters These control bits are a
31. Build Script Commands Build script commands Clock Control Script Commands The script commands described in this section provide control over the clock and frequency settings The set_cpu_frequency script command has been deprecated Instead use the set_clk_period script command described in this section A warning message is generated when this command is used This message can be disabled from the Message Options dialog box set_clk_period femtoSecondPerClkTick The script command listed above sets the target s clock period in femto seconds per clock tick Note that one femto second is le 15 of a second or one billionth of a micro second A simple conversion is to invert the desired MHz and multiply by a billion 1e9 16 778 59601860 femto seconds set_clk_period 59601860 In this example the CPU clock frequency is set to 59 601 860 femto seconds which is 16 778 MHz Many Freescale MC683xx microcontrollers use an external low frequency crystal to generate the CPU s clock source This crystal generally has a frequency of 32 768 KHz or 2 to the 15 cycles per second A crystal of this frequency is known as a watch crystal because a simple 15 bit ripple counter can be used to generate a one second clock tick A phase lock loop within the 683xx microcontroller uses this to synthesize the main CPU clock The 683xx Hardware Debugger assumes that this external crystal oscillates at 32768 cycles per second and a number o
32. Dump Window Availability CPU16 Simulator 133 MySim16 Dis Assembly Dump 814e 37b5 0004 6152 aa 6154 37b5 6669 6158 aa 615a b 615c a5 615e fa 6162 a1 6164 aa 6166 fa 616a a5 616c al 616e aa 6176 a5 2 16 8 869A 6172 2723 8 6176 37b8 6667 617a bd 817c a5 817e 3f 6186 35 i dc 4 66 66 LDD 4h STD Gh z LDD 9h STD 2h z BRA 176h LDD 6h z JSR 9ah ADDD 2h z STD 2h z JSR 1 ah LDD 2h z ADDD 6h z STD 4h z LDD Gh z INCW 6h z CPD 7h BLT 15ch LDD 4h z AIS 6h PULM k z The CPU16 Disassembly Du mp window displays instructions in memory starting with the program counter The instructions address the hexadecimal value of the instruction the actual disassembled instruction and the parse mode are displayed Note that the disassembled instructions are viewable in a generally more useful fashion by selecting mixed assembly viewing mode from within source code windows Unsupported Window This window for diagnostic purposes only and is not supported for customer use 134 LOGIC ANALYZER Overview The Logic Analyzer displays node transitions in a graphical format similar to that of a classical logic analyzer The display can be continuously updated as MtDt runs or the user can turn off the automatic display update and scroll through previously recorded transition data The following topics are available regarding the Logic Analyzer
33. Goto Current Time Plus This sets MtDt to go to the current simulation time plus some user specified additional time User specified time is entered as thousands of seconds ksec seconds secs milliseconds ms microseconds us and nanoseconds ns MtDt s resolution is two CPU clock cycles For the 16 778 MHz two to the 24th cycles per second CPU clock this equates to approximately 124 nanoseconds Help This accesses this help window Goto This closes the Goto Time dialog box and runs MtDt until the specified time OK Save This closes the Goto Time dialog box and saves any changes MtDt remains idle Cancel This closes the Goto Time dialog box without saving any changes Occupy Workshop Dialog Box The Occupy Workshop dialog box provides the apability of specifying for individual windows which workshop s the window will be visible OK This closes the dialog box and saves any changes Cancel This closes the dialog box and discards all changes 145 Help This accesses this help window Occupy All This causes the window to be visible in all workshops Leave All This causes the window to not be visible in any workshop This should be treated as a shortcut for clearing all selections Note that this is not the same as closing the window as the window will still exist within MtDt Revert This causes any settings made since the dialog box was opened to be discarded Options This open
34. MyBdm32 SIM Chip Selects lol x CS CSBAR CSOR ADDR SIZE MODE BYTE R W STRB WAITS SPACE IPL AVEC PIN WIDTH Boot 6007 7876 666666 1M Asynch Both Both AS xD S U All Off 16 Bit CS CSG 6606 6686 666666 2K Asynch Disable Rsud AS Cpu All Off 16 Bit CS CS1 6006 7876 666666 2K Asynch Both Both AS O6xD S U All Off 16 Bit CS CS2 6006 7876 666666 2K Asynch Both Both AS xD S U All Off 16 Bit CS CS3 6606 6666 666666 2K Asynch Disable Rsud AS Cpu All Off 16 Bit CS CS4 66606 6866 666666 2K Asynch Disable Rsud AS Cpu All Off 16 Bit CS CS5 6666 6686 666666 2K Asynch Disable Rsud AS Cpu All Off 16 Bit CS CS6 OOOO 6660 666806 2K Asynch Disable Rsud AS 6 Cpu All Off CS7 6606 6866 696666 2K Asynch Disable Rsud AS Cpu All Off ADDR26 CS8 6666 66866 666666 2K Asynch Disable Rsud AS Cpu All Off ADDR21 CS9 6606 6666 666666 2K Asynch Disable Rsud AS Cpu All Off ADDR22 CS16 6666 6666 666666 2K Asynch Disable Rsud AS Cpu All Off 16 Bit CS The SIM Chip Selects window displays information for each of the SIMS chip select The second and third fields from the left are the Chip Select Base Address CSBARX and the Chip Select Options register CSORX where X denotes the selects one of the 11 chip selects 115 Starting from the left and going to the right are the Base Address Block Size Asynchronous Synchronous EClock Mode Upper Lower Byte Option Read Write Address Data Strobe Wait States Address Space Select Interrupt Priority Level Auto
35. Register bit field indicates if a bit within the ASH WARE development board s PLD is set or cleared See the Development Board documentation for a detailed explanation of this bit CPU32 Simulator Configuration Window Availability CPU32 Simulator 32 MySim32 Configuration iol xi Files Project E Mtdt TargetCode Cpu32_ Test1 1Sim32 MtDtProject MtDt Build E Mtdt Gui TESTFILES BuildScripts 1Sim32 MtDtBuild Source Code main e68 Script No File Open Script Report No File Open Script Startup No File Open Auto Build No File Open Verification Script Failures 66666666 130 Files The name of the project file is displayed See the Project Sessions chapter for a detailed explanation of this capability The name of the MtDt build script file is displayed See the Full System Simulation chapter and the MtDt Build Commands File section for detailed explanations of the available capabilities and format of this file The names of the open source code executable image primary script primary script report and startup script files are displayed These files are listed relative to the path of the open project file The auto build file name is displayed The auto build file allows direct building of the executable image from within MtDt and is covered in the Auto Build Batch File Options Dialog Box section Verification The count of the number of user defined verification tests that have failed since the last MtDt reset
36. SPARK 4 M SPARK 3 SPARK 2 Il ill SPARK 1 ill SYNCH 74 FUNCTIONAL VERIFICATION Overview The functional verification capabilities are currently intended solely for the eTPU TPU Stand Alone Simulators Future versions of this software will extend these capabilities so they are useful for other targets and in a multiple target environment Version 2 0 of MtDt has an increased emphasis on functional verification and especially the automation of these functional verification capabilities using script commands These capabilities can be grouped as data flow verification pin transition behavior verification and code coverage verification The following diagram shows a hardware perspective of functional verification Data Flow Pin Transition Verification Behavior Verification TPU CPU Interface Pin External Registers TPU Microcode Transitions Hardware Code Coverage Verification Data flows between the TPU and the CPU via interface registers Data flow verification provides the capability of verifying this data flow Pin transitions are generated by the TPU or by external hardware Pin transition verification capabilities allow the user to verify this pin transition behavior Code coverage provides the capability to determine the thoroughness of a test suite Code coverage verification allows the user to verify that a test suite thoroughly exercises the microcode A Full Life Cycle Verification Perspective
37. The following describes a typical software life cycle Initially a set of requirements is established Then the code is designed to meet these requirements Following design the code is written and debugged A set of formal tests is then developed to verify that the software meets the requirements The software is then released Now the software enters a maintenance stage In the maintenance stage changes must be made to support new features and perhaps to fix bugs Along with this the formal tests must be modified and rerun Then the software must be re released This life cycle can be described as having three stages development verification and maintenance While version 1 0 of MtDt was primarily a development tool version 2 0 has an increased emphasis T9 on capabilities that address the verification and maintenance stages As such while version 1 0 answers the development question of What is the TPU doing version 2 0 answers the verification question of Are the tests complete and the maintenance question of What has changed Version 2 0 also emphasizes the automation of these tests and the generalization of results in terms of simple pass fail criteria In fact two pass fail criteria can be defined for an entire test suite Data Flow Verification Data flow verification is one of the verification capabilities for which an overview is given in the Functional Verification chapter Data flows between the TPU and the CPU prim
38. U32 address U16 mask U16 val verify_mem_u32 enum ADDR_SPACE U32 address U32 mask U32 val This command uses the following algorithm z Read the memory location in the specified address space and address 7 Perform a logical and of the mask with the value that was read from memory Compare the result to the expected value If the expected value is not equal to the masked value generate a verification error The following example verifies register values of a CPU32 target verify_mem_u8 CPU32_SUPV_DATA_SPACE 0x7 0xc0 0x80 In the example above a script file which is acting on a CPU32 target verifies that the two most significant bits found at address 0x7 are equal to 10b The lower 14 bits are ignored If the bits are not equal to 10b a script failure message is generated and the target s script failure count is incremented verify_mem_u16 CPU32_SUPV_DATA_SPACE 0x100 Oxffff 0x55aa 33 In the example above a 16 bit two byte memory at address 100h is verified to equal Ox55aa By using a mask of FFFFh the entire word is verified verify_mem_u32 CPU32_SUPV_DATA_SPACE 0x200 1 lt lt 27 1 lt lt 27 In the example above bit 27 of a 32 bit four byte memory location at address 200h is verified to be set All other bits except bit 27 are ignored Write Register Script Commands Write register script commands provide the mechanism for changing the values of the target registers The first argument is a reg
39. a script command will run is specified as shown above etpu2 write_chan_hsrr LAST_CHAN 1 wait_time 10 verify_mem_u32 ETPU_DATA_SPACE SLAVE_SIGNATURE_ADDR OxfffffF DATA_TRANSFER_INTR_SIGNATURE etpu2 verify_data_intr LAST_CHAN 1 etpul verify_data_intr LAST_CHAN 0 In this example a host service request is applied to target etpul Ten microseconds later script commands verify that the host service request generated a data interrupt on etpul but not etpu2 Directives The define directive Script commands files may contain the C style define directive The define directive starts with the pound character followed by the word define followed by an identifier and optional replacement text When the identifier is encountered subsequently in the script file the identifier text is replaced by the replacement text The following example shows the define directive in use define THIS_CHANNEL 8 define THIS FUNC 4 set_chan_func THIS_CHANNEL THIS_FUNC Since the define directive uses a straight text replacement more complicated replacements are also possible as follows define THIS_SETUP 8 4 set_chan_func THIS_SETUP There are a number of automatic and predefined define directive as described in the like named section 26 The include lt FileName h gt directive Allows inclusion of multiple files within a single script file Note that included files do not support things like script breakpoints script s
40. aforementioned lists Watch Options Dialog Box The Watch Options dialog box is currently featureless This dialog box is provided to maintain forward compatibility with future versions of this software About ASH WARE s Multiple Target Development Tool MtDt is copyrighted in 1994 through 2000 by ASH WARE Inc All rights are reserved Various national and international laws and treaties protect these rights Any misuse or other violation of the copyright will be prosecuted to the full extent of the law MtDt may not be copied except for the purpose of creating a backup copy for archival purposes BDM Port Dialog Box The BDM Port dialog box is used only in the rare event that MtDt finds BDM target hardware on multiple parallel ports In this case you are asked to select target hardware from a list found during BDM auto detection 155 MENUS The menus allow the user to access the various capabilities of MtDt The menus appear at the top of MtDt Pointing the arrow at the menu by moving the mouse and then clicking the left mouse button accesses them They are also accessed by the lt F10 gt and the lt ALT gt function keys The menu structure is organized as a series of submenus within each menu When a menu item is clicked the submenu structure pops up into view Clicking on the corresponding items can then access a submenu Selection MtDt provides the following menus Files Menu Step Menu Run Menu Breakpoints Menu A
41. as in the TPU2 or might change the values returned when these locations are accessed In any case these warning messages can be disabled WMER Instruction at N 1 after CHAN_REG Change The TPU behavior in this situation is undefined so MtDt generates a message READ_MER Instruction at N 2 after CHAN_REG Change The TPU behavior in this situation is undefined so MtDt generates a message 148 Subroutine Return from Outside a Subroutine When the TPU performs a subroutine call the calling address is pushed unto the stack It would be legal but highly suspicious to do multiple subroutine returns following a single subroutine call Sequential TCRx Write than Read This is actually legal but it is unlikely that it does what you want it to You see the read finds the pre written value having to do with some usual TPU craziness Entry Bank Register Accessed Multiple Times In the real TPU the register holding the entry bank number can be written only once The TPU Simulator allows this register to be written multiple times but gives a warning if you choose to do so Address Rollover Within a Bank TPU2 and TPU3 support multiple banks TPU behavior is not defined if a non end and non return last bank instruction is executed Source Code Search Options Dialog Box The Source Code Search Options dialog box is opened from the Options menu by selecting the Source Search submenu When the executable image is loaded there are normally a numbe
42. buffer can be loaded only with pin transition behavior data from a previously saved file This file forms a behavioral model of the source microcode Changes can be made in the source microcode and the changed microcode can be verified against these behavioral models These files are generated by selecting the Behavior Verification Open submenu from the File menu or by the read_behavior_file filename bv script command There are two options for verifying pin transition behavior against the previously generated behavioral model The first option is to continuously check the running pin transition behavior buffer against the master pin transition behavior buffer This is selected either by the enable_continuous_behavior script command or from the Enable Continuous Verification submenu from the Options menu The second option is to perform a complete check of the running buffer against the master buffer all at once This is selected using the verify_all_behavior script command or from the Options menu A count of failures is displayed in the Configuration window This count is incremented whenever a behavior verification failure occurs There are several considerations regarding these behavioral models The first is buffer size The maximum behavioral buffer size is currently set at 100 000 records though this may increase in future releases If the number of recorded pin transitions equals or exceeds this buffer size then the buffer rolls over
43. dialog box provides a project session capability where MtDt settings are associated with MtDt project files This submenu allows the user to open a previously saved project session The Project Save As Submenu The Project Save As submenu opens the Project Save As Dialog Box Each dialog box provides a project session capability where MtDt settings are associated with MtDt project files This submenu provides the capability to both create a new MtDt project file and overwrite an existing project file with the currently active configuration The MtDt Build Script Run Submenu This opens the Run MtDt Build Script Commands File dialog box and runs the selected MtDt build script commands file This action has a large impact on MtDt so care must be taken when selecting it The MtDt Build Script Fast Submenu This provides a fast repeat run MtDt build script commands file By selecting this submenu the last run MtDt build script file is re run This is useful when debugging a custom MtDt build script file The Auto Build Edit Submenu This opens the Auto Build Batch File Options dialog box for selection and editing of the auto build batch file The Auto Build Fast Submenu This provides a fast repeat build capability By selecting this submenu or using the lt CTRL A gt hot key the default auto build batch file is executed The Behavior Verification Open Submenu This opens the Open Behavior Verification dialog box This is used to
44. eTPU TPU Pin Transition Behavior Script Commands Ne eTPU TPU Resizing the Pin Transition Buffer Neu Thread Script Commands Disable Messages Script Commands eTPU System Configuration Script Commands eTPU Time Base Configuration Script Commands Ney eTPU Channel Data Script Commands eTPU Channel Base Address Script Commands 22 23 23 24 24 25 25 26 26 26 27 27 27 27 28 28 29 29 29 30 30 30 31 31 32 32 33 34 34 35 36 37 38 42 42 42 42 43 GEEES 45 46 46 eTPU Channel Function Mode FM Script Command eTPU Event Vector Script Commands eTPU Interrupt Script Commands TPU Parameter RAM Script Commands eTPU TPU Host Service Request Register Script Commands TPU Channel Interrupt Service Register Script Commands TPU Host Sequence Request Register Script Commands TPU Clock Control Script Commands TPU3 Specific Script Commands TPU Bank and Mode Control Script Commands Setting the TPU Code Bank TPU Match Transition and Link Script Commands eTPU TPU Interrupt Association Script Commands eTPU TPU External Logic Commands eTPU Considerations TPU Considerations Build Script Commands Automatic and Pre Defined Define Directives Target Specific Scripts Determining the Auto Run Mode Determining the Interrupt Number Passing Defines from the Command Line TPU Target Pre Defined Define Directives Pre Defined Enumerated Data Types Script FILE_TYPE Enumerated Data Type Sc
45. execution unit address and the address to which the unit 101 will begin executing should a return statement be encountered are displayed The state of the Microcode Global Exception MGE1 MGE2 and the Illegal Instruction Flag ILF1 ILF2 are displayed which are both part of the ETPUMCR register The state of continuous verification enabled or disabled is displayed as well as the number of pin transition behavior and script command failures are displayed The eTPU version size of its Shared Code Memory SCM and parameter RAM are shown The eTPU simulation engine build are shown The code generation generally the Byte Craft eTPU C compiler and version numbers are shown when available The simulator executable with full path project file and MtDt build file eTPU source code file are displayed The primary script file along with its parse report file are displayed The startup script file is a special file that runs to completion immediately following reset It is generally not used The test vector file and build batch file and any master behavior verification file names gold file are displayed The state locked or free of each of the four semaphores along with an indicator of which eTPU is locking the semaphore is displayed eTPU Global Timer and Angle Counters Window eTpul Counters i Ue t loj x mamamana amne Module Configuration Register MCR HCR CELELLGU GTBE 6 6 Time bases in both engines are ENABLED
46. files ENDIAN_MSB_LSB ENDIAN_LSB_MSB Selects data size in image and C data structure files DATA8 DATA16 DATA32 Selects decimal data instead of hexadecimal for C data structure files OUT_DEC Specifies default options DUMP_FILE_DEFAULT Save Trace File Enumerated Data Types The following enumerated data type is used to specify the event options when saving a trace buffer to a file enum TRACE EVENT_OPTIONS STEP EXCEPTION MEM_READ MEM_WRITE DIVIDER TPU Targets only TPU_TIME_SLOT TPU_NOP TPU_PIN_TOGGLE TPU_STATE_END Hardware debugger only options FREE_RUN All options ALL The following enumerated data type is used to specify the file format options when saving a trace buffer to a file enum TRACE _FILE_OPTIONS VIEWABLE This format is optimized for viewing PARSEABLE This format is optimized for parsing Base Time Enumerated Data Type The following enumerated data type is used to specify the base time for various script commands 61 enum BASE_TIME US NS PS Script TARGET_TYPE Enumerated Data Type The following enumerated data type is used to specify the target type No mathematical manipulation of this data type is valid enum TARGET_TYPE TPU_SIM TPU_DBG SIM32 BDM32 SIM16 SIM32 Build Script ADDR_SPACE Enumerated Data Type This enumerated data type is used when specifying the applicable address spaces for various build scrip
47. in the test vector file using the NODE command as defined in the test vector file section Because it displays only the information from a single channel it may not reflect the true worst case eTpu1 ThreadStats RevA o x j THREAD STEPS Addr Cou cnt WC Tot WC Time o 62D 1 1 4 18 18 360 nS INITIALIZE 1 2FC 1 4 2 2 4 948 nS RE_INIT_INTERRUPT 2 6304 1 4 115 25 23390 560 nS RECEIVED DATA BIT 6 23 3 6368 1 4 25 23 529 466 nS RECEIVED DATA BIT 24 31 4 O3E8 1 4 9 16 123 320 nS UALID GAP AND DATA 5 0478 0 4 8 UALID_GAP_NO DATA 6 6498 6 2 8 TOO MANY BITS FAULT 7 4By 6 2 8 BIT DETECTED IN GAP_HUNT 8 OLE 6 4 6 LINE_WENT_IDLE_FAULT 9 0500 6 3 s 8 INUALID_ THREAD FAULT ales mi One issue with this window is that the worst case threads during initialization are often much worse that is seen during execution of the function Since these initialization threads are not normally an issue it is helpful to be able to clear out all thread data following initialization This is done using the script commands described in the Thread Script Commands section Note that in the above window the Cov coverage column shows for most of the threads This is because each of these threads has been configured to respond to four different event vector combinations yet the simulation run to this point has covered only one of these Which of these event vector combinations has been covered Sele
48. less than operations follow the same rules as the stremp standard library function at_code_tag StringTest1 verify_str somePtr Hello World In the example above the target is run until it gets to the address associated with the source code that contains the text StringTest1 Once this address is reached the ASCII values are read until the terminating character a byte of value zero is reached The resulting string is compared case sensitively with the string Hello World If the two strings are not equal a verification error is generated System Script Commands system commandString verify_system commandString returnVal These commands invoke the operating system command processor to execute an operating system command batch file or other program named by the string lt commandString gt The first command system ignores the return value while the second command verify_system verifies that the value returned is equal to the expected value returnVal If the returned value is not equal to the expected value than a script verification error is generated system copy c temp report txt check txt verify_system fc check txt expected txt 0 In this example the operating system is invoked to generate a file named check txt from a file named report txt The file check txt is then compared to file expected txt using the fc utility A script verification error is generated if the files do not ma
49. load previously saved behavior files The Behavior Verification Save Submenu This opens the Save Behavior Verification dialog box This is used to save the recorded Simulator behavior into a behavior verification file The Coverage Statistics Save Submenu This opens the Coverage Statistics dialog box This is used to store a coverage statistics report to a file 157 Help This accesses this help screen Step Menu Into This runs the active target until one line of source code is executed If a function is called MtDt halts on the first instruction within that function If no instructions associated with source code lines occur MtDt continues to run until stopped by selecting the Stop submenu in the Run menu Over This single steps the target by one line of source code stepping over any function call This is the same as the above Into function except the Into function will halt on a line of source code within the function that is called If no instructions associated with source code lines occur MtDt continues to run until stopped by selecting the Stop submenu in the Run menu Out This runs the active target until the current function returns Execution is halted on the next line of source to be executed in the calling function If no instructions associated with source code lines associated with a calling function occur MtDt continues to run until stopped by selecting the Stop submenu in the Run menu Anything
50. of channel 3 s interrupt When this command is executed channel 3 s interrupt request bit is cleared verify_cisr ChanNum Val This command verifies that the CISR bit from channel ChanNum is equal to Val This command accepts a pair of arguments Argument Val must be between zero and one inclusive If the verification fails a verification failure message is printed to the screen This verification failure message can be disabled from the Message Options dialog box The count of verification failures is available in the Configuration Window verify_cisr 5 1 49 In this example channel 5 s CISR bit is verified to be a 1 If the bit is indeed a 1 then the simulation continues If the bit is instead a 0 a verification failure message is printed to the screen The accumulated count of verification failures is available in the Configuration Window TPU Host Sequence Request Register Script Commands write_chan_hsqr ChanNum Val This command writes channel ChanNum s HSQR bits to value Val The HSQR bits of all other registers remain unchanged write_chan_hsqr 8 0x2 In this example two is written to channel 8 s HSQR bits TPU Clock Control Script Commands These commands control the TCR counter the TCR2 input pin frequency and the TCR2 counter See the Clock Control Script Command section for information on how to set the clock period The set_cpu_frequency script command has been deprecated Instead use the set_clk_p
51. purchased products but we were unable match the license files with the purchase This dialog box is intended to reduce this confusion thereby allowing us to serve you better All information is optional Generally it is best to include at least your company s purchase order number or the ASH WARE invoice number if available BDM Options Dialog Box The following describes the Background Debug Mode BDM Options dialog box 153 Halt Target for Periodic Update When this is selected the free running hardware is halted when MtDt redraws its windows The advantage of selecting this is that the windows can be updated as the target runs The disadvantages are that it effectively disables the target s ability to service interrupts and in some cases the target will execute significantly slower Memory Tool Dialog Box This tool supports specialized memory functions listed below The dump file functions are also accessible from the dump_file script command listed in the File Script Commands section Fill memory with data or text Search for data or text Dump to disassembly file g Dump to Motorola SRecord SREC file Dump to Intel Hexadecimal IHEX file 3 Dump to image file Dump to C structure file For each function the address space and memory range can be specified Earlier address ranges are stored in a buffer and can be retrieved using the recall button For the file dump options selecting the change button can spec
52. scrolled into view TPU Simulator Target Only The following settings are only available for TPU Simulator targets View Coverage TPU Targets Only This specifies whether the code coverage indicators are visible within source code windows These are the color coded boxes at the far left of each line of text that is associated with an instruction These boxes indicate if the associated instruction has been executed and if it is a branch instruction if the true and false cases have been traversed Active Target Settings The following settings act only on the target that was active at the time that the dialog box was opened Each target can be individually set Source Code Spaces per Tab Specifies the number of spaces that correspond to each tab character Workshops Options Dialog Box The Workshops Options dialog box is used to associate targets with workshops specify workshop names and place workshop buttons in the toolbar When adding a new target association to a workshop you will be prompted to indicate whether you would like all windows belonging to that target to be made visible within that workshop It is generally desirable to select the yes or yes to all option The very first workshop is special in that all windows initially visible within this workshop This prevents windows from becoming lost To avoid confusion this workshop name is always All This dialog box allows you to remove a target association from a wo
53. settings associated with the Logic Analyzer Logic Analyzer Window 150 Log TCRCLK eTPU and TCR2 TPU Pin Transition This controls whether the TCRCLK TCR2 input pin transitions are logged to the data storage buffer This pin can be used to clock and or gate in the eTPU and TPU Disabling this increases the effective data storage buffer size Log TCR1 TCR2 Counter Transitions The least significant bit of the TCR and TCR2 global counters can be logged and thereby displayed as a waveform in the logic analyzer Disabling this increases the effective data storage buffer size Log Angle Mode Transitions Various aspect of angle mode can be displayed in the logic analyzer as a waveform These include the mode high speed Normal Wait angle ticks synthesized PLL tooth ticks etc Disabling this increases the effective data storage buffer size Log Threads Threads can be grouped into thread groups and the thread group activity can be displayed in the logic analyzer window Disabling this increases the effective data storage buffer size Configure Thread Groups There are eight thread groups labeled from A to H This opens the Thread Group Dialog Box allows configuration of which thread s are associated with each of these groups Time Display The Logic Analyzer can base the timing display on either target clock count or Simulator time Both of these are set to zero when MtDt is reset This field allows the user to select between t
54. similar to the PSL latch But whereas the PSL reflects the pin state on the last time slot transition or channel register change the PIN reflects the current pin state Both the FLAG2 flag and the PIN branch conditional are features of the TPU2 that do not exist in the TPU1 and therefore are not displayed when in TPU1 mode TPU Channel Window Availability TPU Simulation Target 110 Match Reg IT Capture Reg 4399 Her HSQ1 TUT puSim Channel 3 Pel E3 Match Reg 5123 i TpuSim Channel pa g a Capture Reg 6668 Flag2 HSQ6 SET mrle 4SQ1 SET nrl Flag6 clr tdl Flag1 clr ori Flag2 lsl mrle SET Match r1 clr Captur cdl er Hatch Sri clr Direct 151 clr Pin st Match ENABLE High c Capture TCR1 Hatch Match TCR1 Direction Output Pin State Low High on Match Match on There are two versions of the TPU Channel window The active channel version displays information on the active channel or previously active channel if none is currently active while the fixed channel version displays information on a particular channel The following information is displayed The match and capture registers z The channel s bits from the Host Sequence Request HSQR register Flag2 TPU2 and TPU3 mode only Flag1 and Flag0 The states of the Match Request Latch Enable MRLE Match Recognition Latch MRL Transition Detection Latch TDL Match Transition Service Request Inhibit SRI and Link S
55. specifically single target capabilities such as single stepping When the active target is single stepped the entire system simulation proceeds until the active target completes the commanded single step With an essentially limitless number of targets and with the large number of possible windows per 170 target the vast number of windows can become unwieldy to say the least Actually without some mechanism to bring order to the chaos of having way too many windows MtDt becomes unusable Workshops bring order to this chaos and are therefore a key enabling feature that makes MtDt usable Each target can be associated with a specific workshop Those target s windows are displayed only when the workshop associated with that target is activated Individual windows can be overridden to appear in more than one target A target other than the active target can halt a simulation In this situation the workshop is changed to one associated with the halting target This can be caused for instance if a breakpoint is encountered in a non active target In this case the simulation is halted the halting target becomes the active target and the workshop is switched to the one associated with the newly active target Building the MtDt Environment With MtDt an entire hardware or simulation environment can be built This is done using a dedicated build script file that gets loaded when the project file is loaded A detailed description of each command
56. target s accesses Docking target accesses within the block BlockName in the address space ADDR_SPACE are projected to the docked to target at on offset address AddressOffset The address range corresponds exactly to a previously defined block within the docking target There is no such requirement for the docked to target add_mem_block Cpu_A 0x0 OxFFFF Shared ALL_SPA CES add_non_mem_block Cpu_B 0x600 0x6FF ShareRange ALL_SPACES set_block_to_dock Cpu_B ShareRange ALL_SPACES Cpu_A 0x250 In this example a memory share is setup between targets Cpu_A and Cpu_B The memory that is shared resides in Cpu_A The shared block is accessed by Cpu_B between addresses 600 and 6FF hexadecimal An offset of 250 hexadecimal is applied to the address of each of Cpu_B s accesses such that from the perspective of Cpu_A the accesses occur between 850 and 94F hexadecimal Note that as required the set_block_to_dock script command has the identical address range a previous add_non_mem_block script command Interestingly there is no such restriction on the Cpu_A target set_block_dock_space TargetName BlockName enum ADDR_SPACE DockFromSpace enum READ_WRITE enum ADDR_SPACE DockToSpace This command supports an address space transformation for a docked memory access Read and or write cycles enum READ_WRITE from target TargetName between within the block BlockName in the address spaces enum ADDR_SPACE Doc
57. the Logic Analyzer Below the left side of the wave form display panel are the three fields that display the time or CPU clock counts associated with the left cursor right cursor and delta cursor Delta refers to the time or CPU clock counts difference between the left and right cursors Below the right side of the wave form display are three fields that display the time or CPU clock counts associated with the current Simulator time the oldest available transition data and the mouse The mouse field is visible only when the window s cursor is within the wave form display panel Data Storage Buffer As MtDt runs transition information is continuously stored in a data storage buffer Data is stored only when there is an actual transition on a node When no transitions occur no buffer space is used This is an important consideration since the user can significantly increase the effective data storage by disabling the logging of the TCR2 input pin assuming it is active This is disabled from within the Logic Analyzer Options dialog box All buffer data is retained as long as it predates the current Simulator time and there is enough room to store it Therefore if MtDt time is reset to zero all buffer data is lost When the amount of data reaches the size of the buffer i e the buffer becomes full new data overwrites the oldest data In this fashion the buffer always contains continuous transition data starting from the current
58. the same physical memory The following diagram depicts the address spaces accessed by the TPU simulation engine 172 The TPU simulation model fetches code between 0 and 1FFF hexadecimal from its CODE space It accesses its parameter RAM and host interface registers between 0 and 1FF hexadecimal of its DATA space And it accesses its channel pins in the first four bytes of a simulated PINS space Note that its code banks are unrolled and placed linearly in memory In order for accesses to these spaces to behave properly simulated memory devices must be placed into these address spaces The following build script commands create the required memory for a stand alone TPU Simulation engine Create a target TPU instantiate_target TPU_SIM TpuSim Create a simulated memory block for the TPU s code microcode add_mem_block TpuSim 0 Ox1fff Code TPU_CODE_SPACE add_non_mem_block TpuSim 0x2000 OxFFFFFFFF UnusedCode TPU_CODE_SPACE Create a simulated memory block for the TPU s data host interface add_mem_bl ock TpuSim 0 0x1ff Data TPU_DATA_SPACE add_non_mem_block TpuSim 0x200 OxFFFFFFFF UnusedData TPU_DATA_SPACE Create a simulated memory block for the TPU s pins channel pins and TCR2 counter pin add_mem_block TpuSim 0x0 0x3 Pins TPU_PINS_SPACE add_non_mem_block TpuSim 0x4 OxFFFFFFFF UnusedPins TPU_PINS_SPACE Be sure to provide a non_mem block
59. the use of place_x script commands Several types of external logic are available The script command used to instantiate each type of logic is listed below See the External Logic Simulation chapter for a detailed description of the use of external Boolean logic gates place_buffer X Y Instantiates a buffer follower place_inverter X Y Instantiates an inverter place_and_gate X Y Z Instantiates an and gate place_or_gate X Y Z Instantiates an or gate 7 place_xor_gate X Y Z Instantiates an exclusive or gate 53 place_nand_gate X Y Z Instantiates a nand gate 7 place_nor_gate X Y Z Instantiates a nor gate place_nxor_gate X Y Z Instantiates an inverting exclusive or gate remove_gate Z Removes the gate whose output drives channel Z eTPU Considerations The eTPU has up to two pins per channel which depending on the specific device may or may not actually be connected together or to from outside of the microcontroller In any case indexes are defined as follows for the eTPU Oto 31 Channels 0 through 31 inputs respectively 32 to 63 Channels 0 through 31 outputs respectively 64 TCRCLK pin place_and_gate 5 33 64 This example places an and gate with eTPU channels 5 s input pin and eTPU channel 2 s output pin as inputs and the TCRCLK pin as the output TPU Considerations Note that for the TPU 16 is the index used for the TCR2 pin place_buffer 5 16 This example instantiates a buff
60. the various Simulator windows for viewing MtDt allows multiple instances of each window to be open simultaneously When there are multiple targets a submenu for each target appears Otherwise all available windows are available directly within the view menu See the Operational Status Windows chapter for a listing of the available windows for each target Help This accesses this help screen Window Menu The Window menu accesses the four standard windows functions Cascade Tile Arrange Icons and Close All The standard Windows size toggle function switches the window between maximized and normal size In addition there is a list of all open windows Selecting an open window from this list causes that window to pop to the front Occupy Workshop This opens the Occupy Workshop dialog box This allows display of the currently active window within the various workshops to be enabled and disabled 160 Redraw All This causes all windows to be redrawn In addition all windows caches are invalidated thereby forcing MtDt to go out to the hardware for hardware targets to refresh window data This is helpful on hardware targets for updating the display of hardware registers that may be changing even while execution is halted Help This accesses this help screen Options Menu The Options menu provides the user with the capability of setting various Simulator options These are listed below IDE This opens the IDE Options dialo
61. to 30 nodes may be grouped define ADDRESS1 ch5 define ADDRES S2 ch7 define DATA ch3 70 group PORT1 ADDRESS1 ADDRESS2 DATA In this example a group with the name PORTI is associated with TPU channel pins 5 7 and 3 Test Vector State Command state lt STATE_NAME gt lt BIT_VALUE gt The state command assigns a bit value BIT_VALUE to a user defined state name STATE_NAME State names may contain any ASCII printable text These state names are case insensitive Bit values must consist of a sequence zeros and ones The total number of zeros and ones must be between one and 30 state NULL 0110 In this example a user defined state NULL is associated with the bit pattern 0110 Master Test Vector Clock Frequency Command frequency lt FREQUENCY gt The frequency command sets the master test vector clock to FREQUENCY which is a floating point number whose terms are million cycles per second MHz All test vectors are set by this frequency Since the entire test vector file is loaded at once if a test vector file contains multiple frequency commands only the last frequency command is used and all previous frequency commands are ignored frequency 1 In this example the master test vector generation frequency is set to one MHz This is a convenient test vector frequency because its period of one microsecond makes timing easy to calculate Test Vector Wave Command The wave command creates and defines a new wave form generat
62. to be serviced interrupts and towards the bottom are the lowest priority last to be serviced interrupts Once interrupts are serviced they are removed from this window CPU32 Registers Window Availability CPU32 Simulator and 683xx Hardware Debugger 52 MyBdm32 Registers ioj x PC LELEECERIS UBR 00000000 SSP 00030000 USP 00000013 SFC 60000005 DFC 66600005 AB 22222222 D 44444uhhh A1 11111111 D1 33333333 A2 66660622 D2 66666632 A3 66000623 D3 66666033 A4 686000024 D4 66600034 AS 6860000625 DS 66660035 A 86000626 D6 66660036 A7 686636666 D7 66666637 SR 2763 The CPU32 Registers window displays the CPU32 s registers These are the Program Counter PC the Vector Base Register VBR the Supervisor and User Stack Pointers SSP and USP the Alternate Function Code registers SFC and DFC the Address registers AO through A7 the Data registers DO through D7 and the Status Register SR CPU32 Disassembly Dump Window Availability CPU32 Simulator and 683xx Hardware Debugger The CPU32 Disassembly Dump window displays disassembled code starting at the target s program counter CPU16 Simulator Configuration Window Availability CPU16 Simulator MySim16 Configuration _ O x Files Project E Mtdt TargetCode Cpu16 Simple Cpu16 Simple MtDtProject MtDt Build E Mtdt Gui TESTFILES BuildScripts 1Sim16 MtDtBuild Source Code main e16 Script Simple2 Cpu16Command Script Report Simple2 Report Scrip
63. when the target is paused to examine this variable at_time T When this command is reached no subsequent commands are executed until T microseconds from the simulation s start time At that time the script commands following the at_time statement are executed wait_time T No script commands are executed until the simulation s current time plus the T microseconds wait_time 33 5 assume current time 50 microseconds set_link 5 0 wait_time 100 0 set_link 2 0 In this example at 83 5 microseconds from the start of the simulation channel 5 s Link Service Latch LSL will be set No script commands are executed for an additional 100 microseconds At 183 5 microseconds from the start of the simulation channel 2 s LSL will be set Modify Memory Script Commands Memory is modified within script commands using the assignment operator See the Assignments in Script Commands Files section for a description Verify Memory Script Commands Verify memory script commands provide the mechanism for verifying the values of the target memory The first argument is an address space enumerated type The second argument is the address at which the value should be verified The third argument is a mask that allows certain bits within the memory bcation to be ignored The fourth argument is the value that the memory location must equal verify_mem_u8 enum ADDR_SPACE U32 address U8 mask U8 val verify_mem_u16 enum ADDR_SPACE
64. you purchased are now fully functional All other software products are still available at a demonstration level World Wide Web Software Upgrades All versions since 2 1 can be upgraded directly through the World Wide Web The following procedure is required when performing this upgrade Note that versions prior to 2 1 cannot be upgraded via the World Wide Web Upon receiving notification from ASH WARE that a new version of MtDt is available download and re install MtDt After the initial software upgrade ASH WARE no longer requires a new software key Hearing about Software Releases In order to be notified about ASH WARE s software releases be sure to provide your e mail address to ASH WARE This will ensure that you are automatically alerted to production and beta software releases Otherwise you will have to periodically check the ASH WARE Web site to find out about new software releases Note that your email address and other contact information will never be released outside of ASH WARE Further ASH WARE will only add you to our e mail list if you specifically request us to do so MtDt automatically displays an informational message when your software subscription is close to expiration Note that the software license has no expiration so it is legal to use the TPU Simulator beyond the software subscription expiration date The software subscription entitles you to free technical support and Web based software upgrades 15 Te
65. 062D9B1 GBxe5e 3678 007 472 2 00002D9B4 6x2604 8196 667 472 4 G86662D9BA 0x590 1424 667 472 5 G86662D9BD Gx48e7 18663 607 472 8 688662D9C3 32 Bit Write using Supervisor Data Space at address FFC4 32 Bit Write using Supervisor Data Space at address FFC6 32 Bit Write using Supervisor Data Space at address FFBC 6x6 8 007 473 5 00002D9D5 32 Bit Write using Supervisor Data Space at address FFB8 6x6 0 667 473 7 000902D9DB OxffdO 65488 667 473 68 86662D9C9 6x6 8 667 473 2 B6662D9CF 32 Bit Write 32 Bit Write 32 Bit Write 29 Rit Write using Supervisor Data Space using Supervisor Data Space using Supervisor Data Space ngina Sunernicar Nata Snare at address FFB4 at address FFB6 at address FFAC at address FFAR 4 97 6x6 8 667 474 06 66662D9E1 Oxfffele 16776734 007 474 2 00002D9E7 Oxfffete 16776734 007 474 4 B86662D9ED AxA A AAF 7h 7 AAAAPNGFA l 4 i Tpusim Trace 2 lol x Step 6 807 101 60 666628576 0078 aj Negate SGL s 6 667 161 1 6666 6666 000028578 16 Bit Read using Program Space at address 07E8 0x402a 16426 007 110 0 00002B 5 16 Bit Read using Data Space at address 0104 Ox6cOa 27658 007 110 0 66662B656 Time Slot 6 667 116 6 6661 6661 606628656 32 Bit Read using Program Space at address 66A8 OxacifffFF 1467188993 007 110 4 66662B668 L Step 6 667 116 4 666628666 BOAS 32 Bit Read using Program Space at address 66AC OxakGdfFFF 1542586369 66
66. 3 FCO PC 8 9 8 16 Bit CS CS2 BGACK 7 6 16 Bit CS csi BG 5 4 16 Bit CS CS8 BR 3 2 16 Bit CS CSBOOT 1 6 16 Bit CS xxxx PORT E PIN ASSIGNMENT DATA DIRECTION AND DATA REGISTERS x PEPAR 121 121 126 PORTE AS AS DS RNC RHC e S AVEC 7 5 DS 4 3 2 AVEC 3 1 DSACK1 FF DDRE size FF 7 6 5 4 3 2 1 6 DSACKS E xxxx PORT F PIN ASSIGNMENT DATA DIRECTION AND DATA REGISTERS xxx PFPAR 66 IRQ 7 PF 7 Input DDRF 66 6 PORTF 61 5 4 3 2 1 6 IRQ6 PF 6 Input IRQS PF 5 Input PF 4 Input PF 3 Input I IRQ2 IRQ1 HODCLK PF 2 Input PF 1 Input PF 6 Input a 6 5 IRQS 4 IRQ3 3 2 1 a oqgooococe The SIM Ports window contains the registers that determine the port pin usage pin direction input or output and value These registers are the Port C Port E and Port F Data Registers PORTC PORTE PORTEF the Chip Select Pin Assignment Registers one and zero CSPARI CSPARO Port E and Port F Pin Assignment Registers PEPAR PFPAR and the Port E and Port F Data Direction Registers DDRE DDRF To the right of the bit position field are a variable number of fields Depending on the specific capability of each port the usage direction and value can be selected SIM Chip Selects Window Availability 683xx Hardware Debugger 32
67. 4MsHI FFEF RX14MsLO FFFE RX15MsHI FFEF RX15MsLO FFFE IMASK 454E IFLAG 6666 RXECTR 66 TXECTR 66 32My68376 TouCAN Main STOP FRZ HALT NotRdy Wake sk SoftRst Frzack SUPU S 1fWake APS StopAck IARB ILCAN IUBA Bofflsk Errtisk Rx1Mode Rx 6Mode TxMode SAMP Loop TSYNC LBUF PROPSEG PRESDIU RJW PSEG1 PSEG2 RVMNNN EMAC DAMM ANDHOFMANDODAAmMn SWAOoe eo FMOAn ODaoamMnmrauvnge FuwManwovrvaomn TouCAN clocks are ENABLED TouCAN is allowed to enter debug mode On FR2 1 TouCan goes to debug mode TouCAN is in low power stop or debug mode Wake up interrupt is ENABLED Soft reset cycle completed TouCAN has entered debug mode and the prescaler is Disabled S U registers access at Supu priviledge level Self wake is ENABLED Auto power save ENABLED clocks stop and restart as needed TouCAN is in low power stop mode Interrupt arbitration priority 8 Interrupt request is disabled Interrupt vector base upper 3 bits are 2 BUS OFF interrupt is Disabled ERROR interrupt is ENABLED On the CANRX1 pin a logic 6 is dominant 1 is recessive On the CANRXG pin a logic 1 is dominant 6 is recessive Full CMOS positive polarity CANTX6 6 CANTX1 1 is dominant Sample each receive bit three times Internal loopback is Disabled Timer synchrnization Disabled Message buffer with lowest ID is transmitted first PROPSEG 6 gt Propogation Segment Time 666 659 6 ns PRESDIU 66 gt Clock 666 659 6 ns RJW 0 g
68. 5 5 Counter overflow Interrupt ENABLED PAII 4 4 Input pulse Interrupt ENABLED TFLG1 TFLG2 1636 PAOUF 5 5 Counter overflow flag PAIF 4 4 Input pulse flag is SET The GPT Pulse Accumulate window displays the Pulse Accumulate Control Register PACTL the Pulse Accumulate Counter Register PACNT the Timer Interrupt Mask Registers 1 and 2 TMSK1 TMSK2 and the Timer Interrupt Flag Registers 1 and 2 TFLG1 TFLG2 GPT Pulse Width Modulation Window Availability 683xx Hardware Debugger 22 MySim32 GPT PWM Pulse Width Modu lol x Force Force Pin Fast Period Period Width Width Output State Use Slow CNTs us Val Percent PWH A Yes lo TCNT FAST 256 666 632 6 66 6 PWH B Yes lo slow 32768 664 698 4 66 6 CFPRC PWHC 2B84 The GPT Pulse Accumulate Width Modulation window displays the Compare Force Register CFORC and the PWM Control Register C Register PWMC 122 CTM4 CTM6 Bus Interface and Clocks Window Availability 683xx Hardware Debugger 32My68376 CTM4 Bus I F and Clocks 15 x Configirable Timer Module 4 clocks are ENABLED BIUMCR 1A61 STOP F F FR21 E E When FREEZE on IMB ignore it VECT C B Interrupt vector base is C6 plus submodule offset IARB A 8 CTM4 interrupt arbitration priority 2 TBRS1 5 5 Time Base Select Bit 1 is 6 TBRSG G6 6 Time Base Select Bit 6 is 1 l Use Time Base Bus 2 TBB2 BIUTBR 6666 F 6 The value of Time Base Bus 2 is 6
69. 66 66 OO OO OO OO OO OO OO OO OO OO OA 0G 0G 0000 00900 HSRR 66 66 66 OO OO OO OO OO OO OO OO OO 66 OG 0G 0G 0000 00090 HSQR 66 66 66 66 OO OO OO OO OO OO OO OO OO OG BB 0G 0000 0000 CISR 6 6 6 6 6 6 6 6 6 6 6 0 6 6B BB 9068 CIER 6 6 6 6 6 6 6 6 6 6 6 6 BB BBA 9068 The TPU Host Interface window displays the Channel Function Select Register CFSR the Channel Priority Register CPR the Host Service Request Register HSRR the Host Sequence Register HSQR the Channel Interrupt Status Register CISR and the Channel Interrupt Enable Register CIER TPU Parameter RAM Window Availability 683xx Hardware Debugger 6 EELE 6634 6802 6166 2811 6661 6666 6666 6616 1040 6C34 2128 A616 6621 6666 6666 4011 6934 6666 96005 1120 104E 6666 6660 8600 8114 6666 6281 6669 6554 6666 6666 6319 6628 6461 6611 6216 2004 6666 6666 2440 4034 6965 6624 3C96 16A6 6666 6666 DOGG C266 8665 8636 6696 64606 6666 6666 4614 OC54 4886 6112 8621 6234 6666 6666 8040 6666 662A 6041 8000 1664 6666 6666 62F2 6D14 6236 110C 2866 E666 6666 6666 6168 6761 2661 6615 6636 3000 6666 6666 4370 GABE 1246 2000 6612 6814 6666 6666 4011 6936 9626 4612 8204 0140 6666 66600 1212 6528 C466 6046 6668 A282 6666 6666 B284 4166 4662 1626 1626 82606 4A61 4661 6266 6266 856A 6566 AG22 5569 6258 418B T AMOEOOBDDOAwouw fon The TPU Parameter RAM window displays the TPU Parameter RAM Each row in the window displays the parameter RAM belonging to the row number s TPU ch
70. 666 CPCR 6662 PRUN 3 3 Prescaler divider is held in reset and not running DIV23 2 2 First prescaler stage divides by two PSEL 1 6 PCLK6 post DIU23 prescaler is hos PCLK1 PCLK2 PCLK3 PCLK4 PCLKS PCLK6 Clock Period ns 615 258 8 661 967 3 666 953 7 660 476 8 666 238 4 660 119 2 Total Prescaler 256 32 16 8 4 2 The CTM4 CTM6 Bus Interface and Clocks window displays the BIU Module Configuration Register BIUMCR the BIU Time Base Register BIUTBR and the CPSM Control Register CPCR In addition the prescaler clock period is calculated and listed in both nano seconds and division ratio CTM4 CTM6 Free Running Counter Submodule Window Availability 683xx Hardware Debugger A free running counter overflow has not occured FCSMSIC 1866 COF F F IL E C Interrupt is level 1 IARB3 B B Interrupt arbitration bit 3 is SET l Concatenated with BIUHCR IARB 2 0 DRU 9 8 Time base bus IN 7 7 The CTM2C clock input pin is Low CLK 2 6 The counter clock source is PCLK1 FCSHCNT 23D2 F 6 The value of the FCSM counter register is 23D2 The CTM4 CTM6 Free Running Counter Submodule window displays the FCSM Status Interrupt Control Register FCSMSIC and the FCSM Counter Register FCSMCNT CTM4 CTM6 Modulus Counter Submodule Window Availability 683xx Hardware Debugger My68376 CTM4 Modulus 0 x HHH HHH HH HHH NHCSHB2 HHH HHH HH JE JE JE JE JE HHH JE JE JE JE JE JE JE JE JE JE JE JE JE J
71. 6x92 v mi ay Although there are several types of script commands windows only two styles can be viewed within a window primary and ISR The primary script commands file window displays the open or active primary script commands file whereas an ISR script commands file window displays a script commands file that is associated with a TPU channel interrupt See the Script ISR section for an explanation of these two types of script commands files A list of the available script commands functional groups is given in the Script Commands Groupings section The primary script commands file is loaded from the Files menu by selecting the Scripts Open submenu and following the instructions of the Open Primary Script File dialog box The primary script commands file can be reread at anytime This is done from the Files menu by selecting the Script Fast submenu MtDt re executes the file starting from the first command When the primary script commands file is reread MtDt state is not modified When MtDt is reset the user has the option of re initializing the primary script commands file opening a new or modified primary script commands file or taking no action If no action is taken primary script commands file execution will continue from where it left off before the reset The user selects the desired option via the Reset submenu in the Options menu This submenu activates the Reset Options dialog box When the primary script c
72. 7 116 5 66662B662 Step 6 667 116 55 66662B662 ONAC 32 Bit Read using Program Space at address 66B6 Ox673bFFFF 1731985467 007 110 6 66062B664 Step E T E E v ojm WZ The Trace window displays information relating to the instructions that were executed The Trace window displays all information that has been stored in the trace buffer See the Trace Options Dialog Box section for information on how to modify the information that is stored in this buffer For most simulation models the data flow between processor and memory can be displayed Timing information is included but it should be noted that the most ASH WARE simulation models use an intuitive rather than a true timing model so these will vary slightly relative to the real CPU TPU or other target model type Note that in hardware targets like the 683xx Hardware Debugger this window will not function correctly because many hardware targets do not contain trace buffers Therefore MtDt does not know which instructions executed last The instructions that are displayed are those from previous single steps of the target Gaps in the trace buffer are noted and the displayed execution times are an approximation based on the real time clock of the PC Saving Trace Data to a File The trace data can be saved to a file either directly through the GUI or from within a script commands file This is explained in the TRACE BUFFER AND FILES section TPU Simulation Considerations The TPU sim
73. A Out in the same directory where the project file is located vector filename Vector The TPU test vectors found in file filename Vector are loaded by this script command This command is available only for the TPU Simulator target Test vector files normally have a vector suffix Note that the vector suffix is preferable Test vector files can also be loaded via the Open Test Vector File dialog box which is opened from the Files menu by selecting the Vector Open submenu vector UART Vector This example loads the test vectors found in file UART Vector in the directory where the project file is located The file path is resolved relative to the directory in which the project file is located dump_file startAddress stopAddress enum ADDR_SPACE filename dump enum FILE_TYPE enum DUMP_FILE_OPTIONS This command creates the file filename dump of type FILE_TYPE using the options specified by DUMP_FILE_OPTIONS The file is created from the image located between startAddress and stopAddress out of the address space ADDR_SPACE dump_file 0 Oxffff CPU32_SUPV_DATA_SPACE Dump S19 SRECORD DUMP_FILE_DEFAULT define MY_OPTIONS NO_ADDR NO_SYMBOLS dump _file 0 Oxffff CPU32_SUPV_CODE_SPACE Dump dat DIS_ASM MY_OPTIONS This example creates a Motorola SRECORD file Dump S19 from the first 64K of the CPU32 s supervisor data space The default options are used for this dump An assembly file Dump dat is also
74. AP_NO_DATA TOO_MANY_BITS FAULT BIT_DETECTED_IN GAP_HUNT LINE_WENT_IDLE_FAULT INUALID_THREAD_FAULT e Re Executing the Worst Case Thread If the thread has executed at least once such that there is a worst case thread time available then the 95 time at which the thread occurs appears as a yellow vertical line in the logic analyzer window and the time at which the thread occurred is shown as the context time in the logic analyzer window as shown below To re execute this thread grab this context time by moving the cursor over the context time such that an open hand appears and depressing the left mouse button such that a closed hand appears With the left mouse button depressed move the closed hand cursor to the right Position the cursor over the field labeled current time and then release the left mouse button The simulation will reset then run until it reaches the context time which was the time at which the worst case thread executed eTpul Logic Analyzer Reva v 3 280 361 8 n Mouse 3 393 293 1 nS Data Start 000 000 0 nS Context 3 332 040 0 nS Current Time 3 382 000 0 nS Set Left Cursor 112 931 3 nS Delta Cursor 3 167 430 5 nS Right Cursor 3 280 361 8 nS The window shown below is similar to the window set to the ARINC_FX function except that it is configured to show only the information from the channel named RcvA Note that this name has been assigned to this channel
75. B The standard register P DIOB SR A B C D are displayed The Return Address Register RAR link chan are displayed 105 The execution unit s A Bus source B Bus source and result bus are shown These are the buses internal to the execution unit The Multiply Accumulate register MACH MACL are shown The Zero Carry Negative and overflow flags for both the execution unit and the MAC unit are shown Z C N V MZ MC MN M as is the Mac Busy flag MBSY Conditionals are displayed as seen by the execution unit in that these are the versions of these flags that are sampled at the beginning of the thread These include the Link Service Request LSR Match Recognition Latch and Transition Detection Latch for both action units MRLA MRLB TDLA TDLB the Function Mode Bits FM1 FMO the sampled and current input pin states PSS PST The upper 8 bits of the P register which are treated as conditionals by the execution unit are also displayed TPU Configuration Window Availability TPU Simulation Target W TpuSim Configuration OF x Clocks Counters CPU Frequency Prescalers TCR1 6 TCR2 6 PSCK 1 DIU2 ESPCKE ESPCK T2CG 6 T2CSL TCR2PSCK2 Verification Continuous Behavior Off Behavior Failures 66666666 Script Failures 66066660 Versions Device TPU 1 512 Instructions TPU Simulator 99 98 Build Z TPU Assembler 5 6 Files Project E Mtdt TargetCode HelpWindows DemoEngine NtDtProject MtDt
76. B 19 O3FF PAUSE YES 16 QCLK s 622 888 2 3F gt PQA 6 ANG Q3FF 7FCG FFCO 4A Q 3FF PAUSE YES 16 QCLK s 622 888 2 3F gt PQA 6 ANO O3FF 7FCG FFCO 1B 03D9 PAUSE YES 16 QCLK s 022 888 2 19 gt PQA BZAN 63D9 7646 F646 1C B FF no 16 QCLK s 022 888 2 3F gt PQA 6 ANG GOFF BFCG 3FCO 1D 3FF PAUSE YES 16 QCLK s 022 888 2 3F gt PQA 6 ANG Q3FF 7FCG FFCO 1E O3FF PAUSE YES 16 QCLK s 022 888 2 3F gt PQA 6 ANO O3FF 7FCG FFCO 1F O3D9 PAUSE YES 16 QCLK s 022 888 2 19 gt PQA 6 ANG 03D9 7646 F646 28 3D9 PAUSE YES 16 QCLK s 622 888 2 19 gt PQA 6 ANG GOFF BFCG 3FCO 29 O1FD YES 16 QCLK sS 622 888 2 3D gt PQA 6 AND O3FF 7FCG FFCO 2A 62DB PAUSE no 16 QCLK s 022 888 2 1B gt PQA 6 ANG Q3FF 7FCO FFCO 2B 0391 PAUSE YES 8 QCLK s 011 444 1 11 gt PQA 6 ANG 63D9 7646 F646 2C B FF no 416 QCLK s 022 888 2 3F gt PQA 6 ANG GFF BFCO 3FC8 2D Q3FF PAUSE YES 16 QCLK s 622 888 2 3F gt PQA 6 ANS 63FF 7FCG FFCS 2E Q 3FF PAUSE YES 16 QCLK s 622 888 2 3F gt PQA 6 ANG Q3FF 7FCG FFCO 2F O3D9 PAUSE YES 16 QCLK s 622 888 2 19 gt PQA 6 ANO 83D9 7646 F646 129 The QADC Channels window displays the Conversion Command Word Table Registers CCWO to CCW 2P the Right Justified Unsigned Result Registers RJURRO to RJURR2PF the Left Justified Signed Result Registers LJSRRO to LJSRR63 and the Left Justified Unsigned Result Registers LJURRO to LJURR27 Note that the QADC normally has up to 16 analog input channels but can directly support up to 40 analog cha
77. BDM port Support for additional targets will soon be added But from a customer s standpoint there are specific requirements that must be met Individual products are therefore derived from MtDt to meet these customer requirements As single target products we offer a eTPU Stand Alone Simulator a TPU Stand Alone Simulator a CPU32 Stand Alone Simulator a CPU16 Stand Alone Simulator and a 683xx Hardware Debugger As full system simulation products we offer a CPU32 TPU System Simulator and a CPU16 TPU System Simulator Although not offered as a specific product MtDt supports mixing hardware and simulated targets This would allow for instance a software model of a new CPU to be linked to a real peripheral across a BDM Port Driver code could be developed for a CPU that exists only as a software model but controls real hardware Concurrently Developing Code for Multiple Targets Code for multiple targets can be developed and debugged concurrently Interactions between and among multiple targets are modeled precisely and accurately All the normal debugging techniques such as single stepping setting breakpoints stepping into functions etc are available for each target The IDE supports instantaneous target switching such that it is possible for example to run to a CPU32 breakpoint and then switch to a TPU and single step it All the while all targets are kept fully synchronized The Freescale eTPU and TPU Of special interest is the
78. BIT 6 23 29 887A 478 8 UALID_GAP_NO_DATA 30 007C 8368 8 RECEIVED DATA BIT 24 31 31 007E B3E0 8 UALID_GAP_AND DATA a The group and ungroup commands allow the same threads from different event vector response combinations to be grouped together The window shown has this option set to ungroup Note that there are 32 event vector combinations To get good testing coverage all of these event combinations should be tested By setting the window to show all event response combinations it becomes clear that the simulation run on this window is not fully excersizing the function and as such the event vector coverage is poor Trace Window ff EHH HHH HHH HHH HHH JE JE JE HE JE JE JE JE JE JE JE JE JE JE JE JE JE JE E JEJE JEE GESE tf EXCEPTION ff External Interrupt 16 Bit Write using Supervisor Data Space 32 Bit Write using Supervisor Data Space at address FFCA 16 Bit Write using Supervisor Data Space at address FFC8 32 Bit Read using Supervisor Data Space at address 2566 Ff RHE JE HK E IE JE JE JE JE E IE IE JE JE JE JE JE E E JE JE JE JE JE JE E IE JE JE JE JE JE HE MEE EJE AAAS 16 Bit Read using Supervisor Program Space at address 6596 16 Bit Read using Supervisor Program Space at address 6592 Oxfffe 2 667 472 9 686662D9C6 0590 48E7 FFFE MOVEM L a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d6 A7 Move Multiple Registers HE ee 667 472 6 666062D9B1 at address FFCE 0x100 256 607 472 86 66
79. CNT Force Input Pin Match Match pin Val Interrupt Match Comparex Output Is ocs s och toggle op SET 1233 Disabled No clr Input HI 0c3 set op SET 3366 Disabled No SET Output HI 0c2 clear op clr GABG Disabled Yes clr Input HI oc1 op clr CDEE Disabled No SET Output lo TCTL1 TCTL2 1ED8 OC1M OC1ID F8E6 THSK1 TMSK2 82B8 TFLAG1 TFLAG2 1636 CFPRC PWHC 2B84 DDGRP 2F PORTGP F2 xx Note Force Compare always reads zero The GPT Output Captures window displays the Timer Control Registers 1 and 2 TCTL1 TCTL2 the OCI Action Mask Register OCI1M the OC1 Action Data Register OC1D the Timer Interrupt Mask Registers 1 and 2 TMSK1 TMSK2 the Timer Interrupt Flag Registers 1 and 2 TFLG1 TFLG2 the Compare Force Register CFORC the PWM Force Register PWMC the Port G Data Direction Register DDGRP and the Port G Data Register PORTGP GPT Pulse Accumulate Window Availability 683xx Hardware Debugger J2 MySim32 GPT PA Pulse Accumulate lo x Pulse accumulator input pin state is lo PACTL PACNT 6466 PAIS F F PAEN E E Pulse accumulator is Disabled PAMOD D D External event counting PEDGE C C PAI falling edge increments counter PCLKS B B PCKLK pin state is lo 14 05 A A Output compare 5 Disable Input capture 4 ENABLE PACLK 9 8 Clock source System clock divided by 512 Clock period is 666 632 6 ns PACNT 7 6 Pulse accumulator count is 66 THSK1 TMHSK2 82B8 PAQUI
80. Capture on falling edge SASM18B 6191 8DB6A No DIS clr dis B HI 8 SET OP gt Output Port pin set low SASH24A 6526 6666 No DIS clr EN B lo 1 clr IC gt Input Capture on falling edge SASH24B 6686 6666 No DIS clr dis A HI 6 clr IC gt Input Capture on falling edge The CTM6 Single Action Submodule window displays the SASM 12A 12B 14A 14B 18A 18B 24A 24B Status Interrupt Control Registers SIC12A SIC12B SICI4A etc and the SASM 12A 12B 14A 14B 18A 18B 24A 24B Registers S12DATA S12DATB S14DATA etc CTM6 Double Action Submodule Modes Window Availability 683xx Hardware Debugger 52 MySim32 CTM6 Double Actions Modes DASM E iol x DASHO4 OPWH Output pulse width modulation E A compare on channel A sets the ouptut pin to logic 1 A compare on channel B clears the ouptut pin to logic 8 pasmes Channel A captures on a rising edge Channel B captures on a falling edge DASHG6 IC Input capture xl The CTM6 Double Action Modes Submodule window displays the DASM 4 5 6 7 8 9 10 26 27 28 and 29 Status Interrupt Control Registers DASM4SIC DASMS5SIC DASME6SIC DASM7SIC DASM8SIC DASM9SIC DASM10SIC DASM26SIC DASM27SIC DASM28SIC DASM29SIC See the Bits form of the CTM6 Double Action Submodule window for display of additional information CTM6 Double Action Submodule Bits Window Availability 683xx Hardware Debugger 32MySim32 CTM6 Double Actions Bits DASM 05 x A
81. E AF 75 Disabled cir 12 NZA FFD 75EB 7B F4 FF FF 6F EF 8F 9B Disabled clr 11 NZA BBFB FFDF A4 5F 5B 67 CF CD 7D E7 Disabled clr 16 NZA FEFF BZF7 7F C9 FC EF OGF 76 9A A3 ENABLED clr 9 N A AEA ES9D FD CF 57 72 FF EF DD F Disabled clr 8 NZA DDF6 7DFF FE FF 56 EF DE 3F CF D 7 ENABLED clr 7 NZA 5DBF EBDF FD 3F D9 27 CD B6 B7 BF Disabled clr 6 N A FEC FFDF EF DE FB F DF DC FF FF ENABLED clr 5 NZA 73F9 EF3A FF CF 7F EB 1F B4 71 FA Disabled clr 4 N A S7FE F7AF 7F D3 F2 FF 9D 7A DF FF Disabled clr 3 NZA 2AF EAEB F 7 FF DF BF F7 F 7D F7 ENABLED clr 2 NZA FD 7D F67F 7D B5 D9 FB 2F FF B5 E7 ENABLED clr 1 NZA FF7B FFFF EE F9 FF EB FF AE FD 7D ENABLED clr 6 N A FFEA F79E AF DF FF 7F B7 5D FC BE Disabled clr The TouCAN Buffers window displays information for each of the 16 buffers For each buffer the status identification high and low eight data bytes interrupt enable disable and interrupt set clear state is displayed QADC Main Window Availability 683xx Hardware Debugger 32My68376 QADC Main E 10 x QADCHCR 4684 STOP F F The QADC clock is enabled FRZ E E QADC finishes any current conversion then freezes SUPU 7 7 All tables and registers are supervisor only IARB 3 8 QADC interrupt arbitration priority M QADCINT 313C IRLQ1 E C Queue 1 interrupt is level 3 6 disabled 7 highest IRLQ2 A 8 Queue 2 interrupt is level 1 6 disabled
82. E JE JE JE HHH HHH zi SIC 2921 COF F F A overflow has not occured IL E C Interrupt level is level 2 IARB3 B B Interrupt arbitration bit 3 is SET I Concatenated with BIUMCR IARB 2 0 DRU 9 8 Time base bus A is driven IN2 7 7 The CTH2C clock input pin is Low IN1 6 6 The CTD9 modulus load input pin is Low EDGE 5 4 CTD9 edge detection negative edge only CLK 2 6 The counter clock source is PCLK2 CNT 1232 F 6 Counter register value is ML 1232 F 6 Modulus latch value is 1232 HHH KKK HEHEHE MCSH11 HH HHH HHH HHH HHH HHH HHH HHH HHH JE JE JE JE JE JE ME JE MEJE EME E SIC 6666 COF F F A overflow has not occured be 4 uy 123 The CTM4 CTM6 Modulus Counters Submodule window displays the MCSM 2 and 11 Status Interrupt Control Registers MCSM2SIC MCSM1I1SIC the MCSM 2 and 11 Counter Registers MCSM2CNT MCSMIICNT and the MCSM 2 and 11 Modulus Latch Registers MCSM2ML MCSMI11ML CTM amp 4 Double Action Submodule Window Availability 683xx Hardware Debugger 32My68376 CTM4 Double Actions DASM sS 5 x Z An input capture or output compare has 4 SIC 2B88 FLAG F F IL E C Interrupt is level 2 IARB3 B B Int arbitration bit 3 is SET BIUMCR IARB 2 6 WOR 9 9 If output then buffer operates in wired or mode BSL 8 8 Connected to time base bus B IN 7 7 If input then the pin is High FORCA 6 6 Set to force channel A compare always re
83. EGISTERS U4 REG_XK REG_YK REG_ZK REG SK REG PK REG EK 5 The following enumeration provides the mechanism for referencing the CPU16 s 8 bit registers enum REGISTERS _U8 REG_A REG_B REG_XMSK REG_YMSK 5 The following enumeration provides the mechanism for referencing the CPU16 s 16 bit registers enum REGISTERS_U16 REG_D REG_E REG_IX REG_TY REG_IZ REG_SP REG_PC REG_CCR REG_HR REG_IR REG_AMLO 5 The following enumeration provides the mechanism for referencing the CPU16 s 32 bit register enum REGISTERS_U32 REG_AMHI MAC Accumulator MSB bits 35 16 65 TRACE BUFFER AND FILES Overview Trace files have two primary purposes they are useful for generation of a file that appears identical to the trace window but can be loaded into a file viewer to access advanced search capabilities and they are used to load into a post processing facility for advanced trace analyses The various capabilities and settings are focused on these two purposes Generating Viewable Files Viewable trace files can be generated by selecting the Trace buffer Save As submenu from the Files menu Note that the trace buffer is about five times larger than what appears in the trace window A viewable trace file can also be generated using script commands See the File Script Commands section Because viewable files are appropriate only for things like advanced search capabilities no error or warning is generated if the underlyin
84. E_OPTIONS enumerated data type Script BASE_TIME enumerated data type Script TRACE_OPTIONS enumerated data type Script TARGET_TYPE enumerated data type Script ADDR_SPACE enumerated data type Build Script READ_WRITE enumerated data type Build script Register enumerated data type eTPU Register enumerated data types TPU Register enumerated data types CPU32 Register enumerated data types CPU 16 Register enumerated data types Script FILE_TYPE Enumerated Data Type The following enumerated data type is used to specify the file type used in various script commands This specifies a dis assembly Freescale S Record Intel Hexadecimal or C data structure file type enum FILE_TYPE DIS_ASM SRECORD THEX IMAGE C_STRUCT 60 Script DUMP_FILE_OPTIONS Enumerated Data Type The following enumerated data type is used to specify the options when dumping data to a file The available options depend on the type of file being dumped enum FILE_OPTIONS Disables listing of address information in dis assembly and C data structure files NO_ADDR Disables listing of hexadecimal dump addressing mode and symbol data in dis assembly files NO_HEX NO_ADDR_MODE NO_SYMBOLS Adds a pragma format val to each dis assembly line This is helpful for non deterministic assembly languages to cause the assembler to generate a deterministic opcode YES_PRAGMA Selects the endian ordering for image and C data structure
85. Enhanced Time Processor Unit eTPU and TPU from Freescale For those wishing more information on the eTPU refer to the Freescale user manuals For those wishing to develop their own TPU microcode it is imperative that you obtain the book TPU Microcoding for Beginners from AMT Publishing Do not be misled by the title This book 5 essential for beginners and experts alike The eTPU and TPU training seminars are also highly recommended 13 Script Commands Files MtDt script commands files have several purposes Each target has a primary script file used to automate things like loading code initialization and functional verification ISR script files can be associated with specific interrupts and execute only when that interrupt is activated Startup script commands files are executed following an MtDt controlled reset or when the application is initially launched The primary purposes of the startup script commands file is initialization and getting the target into the correct state for loading code when MtDt is launched MtDt build script files instantiate and connect targets For most users no knowledge of MtDt build script files is required because the standard build script files provided by ASH WARE provide all the required features But power users may tailor the MtDt build script files to take advantage of MtDt s advanced full system simulation capabilities Test Vector Files Test vector files provide the user with one means of exercisin
86. Entry shows if the event vector entry table for that channel is being treated as the standard or alternate event vector table The Channel Interrupt Status Register CISR shows if this interrupt has been issued by the eTPU the CIER indicates if the interrupt is enabled and the CIOR indicates if an attempt to set the interrupt when it was already set occurred and therefore there was an overflow The Channel Data Transfer Request Status Register CDTRSR shows if this interrupt has been issued by the eTPU the CDTRER indicates if the interrupt is enabled and the CDTROSR indicates if an attempt to set the interrupt when it was already set occurred and therefore there was an overflow 103 Note that in response to these enabled and asserted interrupts special ISR script command files can execute as described in the Script ISR section eTPU Channel Window eTpul Ch3 K 4 5 xj A B Match GULGPALH 001144 TCR2 TCR2 Capture 16DCE8 130997 TCR1 TCR1 mrle SET SET mrl clr clr tdl clr clr ENABLE Match and transition servicing lsr clr During thread ENABLE matches Input Pin Low Output Pin Low Output Buffer Disabled Output Not Delayed IPAC A Do not detect transitions IPAC B Do not detect transitions OPAC A Match sets output signal high OPAC B Do not change output signal Either Match Non Blocking Double Transition Flags 6 clr 1 clr Frame Addr 6566 Active 66 066 Threads 11 Steps 551 Longest Thread 89 step
87. Hardware Targets WORKSHOPS OPERATIONAL STATUS WINDOWS Overview Window Groups Source Code File Windows Script Commands File Windows Watches Window Local Variables Window Call Stack Window Neus Thread Window Trace Window Complex Breakpoint Window Memory Dump Window Timers Window eTPU Channel Function Frame Window eTPU Configuration Window 71 71 72 75 75 75 76 76 71 78 78 78 78 80 80 80 81 81 82 83 83 83 85 85 86 eTPU Global Timer and Angle Counters Window eTPU Host Interface Window eTPU Channel Window eTPU Scheduler Window eTPU Execution Unit Registers Window TPU Configuration Window TPU Host Interface Window TPU Scheduler Window TPU Microsequencer Registers Window TPU Execution Unit Window TPU Channel Window TPU Parameter RAM Window 683xx Hardware Debugger Configuration Window SIM Main Window SIM Ports Window SIM Chip Selects Window QSM Main Window QSM Port Window QSM QSPI Window QSM SCI UART Window Masked ROM Window Standby RAM Submodule Window 68336 68376 Static RAM Submodule Window 68338 TPU Emulation RAM Window 68332 68336 68376 TPU Main Window TPU Host Interface Window TPU Parameter RAM Window GPT Main Window GPT Input Captures Window GPT Output Compares Window GPT Pulse Accumulate Window GPT Pulse Width Modulation Window CTM4 CTM6 Bus Interface and Clocks Window CTM4 CTM6 Free Running Counter Submodule Window CTM4 CTM6 Modulu
88. LL DIVIDER MEM_READ PARSEABLE US 3 1 print _to_trace Fee Fee eE Eee EERE EERE E EERE EERE EE EEE AEE meee START OF TEST n SR 2 26 2 SB 2 26 2 ee 2 OE 2 OR RR RE OE D wait_time 1500 end_trace_stream The above example begins streaming all trace data except dividers and memory reads to a trace file named Stream Trace Time is recorded in micro seconds with three trailing digits following the period such that the least significant digit represents nano seconds The isResetTime field is set to true so that script execution time of 400 micro seconds is subtracted from the time and the clocks field save_trace_buffer FileName trace enum TRACE _EVENT_OPTIONS enum TRACE_FILE_OPTION enum BASE_TIME U32 numTrailingDigits This command is the same as the start_trace_stream command except that the current trace buffer is saved to a file save_trace_buffer ThisTraceFile Trace STEP MEM_READ VIEWABLE US 3 In this example a file named ThisTraceFile trace is generated Only step events and memory read events are saved The selected file format is optimized for viewing rather than parsing Because this is a VIEWABLE file the base_time and numTrailingDigits fields are ignored Code Coverage Script Commands An important index of test suite completeness is the coverage percentage that a test suite achieves MtDt provides several script commands that aid in the determination of coverage percentages In addition
89. Multiple Target Development Tool Version 3 41 User Manual Developed by John Diener Andrew Klumpp Keith Kroeker Michael Schwager and Tony Zabinski Edited by Margaret Frances Stan Ostrum Richard Soja and Mike Pauwels of Freescale Inc contributed ideas for key features as did Marc Peters from Mot Consulting GmbH Walter Banks of Byte Craft Limited provided the critical companion technology in the eTPU C Compiler ASH WARE Inc 2610 NW 147th Place Beaverton OR 97006 www ashware com TABLE OF CONTENTS TABLE OF CONTENTS FOREWORD ACKNOWLEDGEMENTS ON LINE HELP CONTENTS OVERVIEW Targets and Products Concurrently Developing Code for Multiple Targets The Freescale eTPU and TPU Script Commands Files Test Vector Files Sharing Memory between Multiple Targets Miscellaneous Capabilities SOFTWARE DEPLOYMENT UPGRADES AND TECHNICAL SUPPORT World Wide Web Software Deployment World Wide Web Software Upgrades Hearing about Software Releases Technical Support Contact Information Overview of Version 3 41 3 40 3 20 3 10 3 00 2 1 and 2 0 Enhancements PROJECT SESSIONS SOURCE CODE FILES Theory of Operation Source Code Search Rules Absolute and Relative Paths Supported Compilers and Assemblers SCRIPT COMMANDS FILES Overview Types of Script Commands Files 10 11 12 13 13 13 13 14 14 14 14 15 15 15 15 16 19 20 20 20 21 21 22 22 22 Simila
90. MyTpu TpuBuildReport txt In this example report files named C Temp CpuBuildReport txt and TpuBuildReport txt are generated for the MyCpu and MyTpu targets respectively Note that C style double backslashes are required when separating directory names Automatic and Pre Defined Define Directives Target Specific Scripts It is often desirable to have a single script commands file run on multiple targets In this case target dependent behavior is accomplished using the target define The target define is generated using the target name as follows define _ASH_WARE_ lt TargetName gt _ 1 TargetName is defined in the build batch file and is found in a pull down menu in the upper right hand side of the simulator ifdef _ASH_WARE_DBG32 set_crystal_frequency 32768 endif ASH _WARE_DBG32 In the this example the set_crystal_frequency script command executes only if the script command is running under a target named DBG32 Determining the Auto Run Mode The Simulator Debugger is often launched as part of an automated test suite Under these conditions the test starts running and executes to completion assuming no failures with no user intervention The following is automatically defined when the application is launched in auto run mode ASH_WARE_AUTO_RUN The following is typically found at the end of an script file used as part of an automated test suite ifdef_ ASH WARE _AUTO_RUN exit else print
91. Note that as the target executes the contents of the Local Variables window will usually change quite a bit This is because each function generally has a unique set of local variables that are displayed As the target moves from function to function only the local variables of the currently executed function are displayed Global variables are not displayed within this window See the description of the Watches window for information on how to display global variables Local Variable Window Automation In conjunction with the Call Stack window the Local Variables window can display the local variables of functions that have been pushed unto the call stack In a Call Stack window move the cursor to a line associated with a function that has been pushed onto the call stack This causes the local variables from that function s context to be displayed in the Local Variables window 93 Occasionally it is desirable to lock the local variable to display the local variables of a particular function To do this you must disable the automation This is done within a Local Variables window by opening the Local Variable Options Dialog Box and selecting the lock the local variables option Locking and unlocking of the current function s context can also be done more quickly by selecting either the lock or the unlock options from the popup menu that appears when you right click the mouse within a Local Variable window Call Stack Window A l
92. Only This commands loads ISR script commands file filename TpuCommand or filename eTpuCommand and associates them with the various types of interrupts from channel ChanNum close_chan_isr ChanNum eTPU only close_data_isr ChanNum eTPU only close_exception_isr eTPU only close_isr ChanNum TPU only These commands close the ISR script command that is associated with the channel ChanNum load_isr ISR_5 TpuCommand 5 write_chan_cier 5 1 Enable the TPU interrupt wait_time 2000 close_isr 5 write_chan_cier 5 0 Disable the TPU interrupt This TPU exmple loads the file ISR_5 TpuCommand and associates it with the interrupt from channel 5 Any asserted and enabled interrupt on channel 5 during that 2ms window will cause the script commands in the file to be run load_data_isr ISR_22 eTpuCommand 22 enable_data_intr 22 wait_time 5000 close_data_isr 22 disable_data_intr 22 This eTPU DATA isr example loads the file ISR_22 eTpuCommand and associates it with the data interrupt from channel 22 If the interrupt for channel 22 is both asserted and enabled within the first Sms then the script commands in the file will run load_exception_isr GlobalExc eTpuCommand eTPU Only This eTPU example loads the file GlobalExc eTpuCommand and associates it with the global interrupt eTPU TPU External Logic Commands Boolean logic that is external to the eTPU TPU is instantiated in MtDt through
93. PPR 6 4 PPR 6 PWM CNT input is 666 125 14 ns or Fsys 2 l l PRESCL 6633 F 6 9 Bit prescaler is 0633 Bits F 9 always zero The GPT Main window displays the GPT Module Configuration Register GPTMCR the GPT Interrupt Configuration Register GPTICR the Port G Data Direction Register DDGRP the Port G Data Register PORTGP the OC1 Action Mask Register OC1M the OC1 Action Data Register OCID the Timer Counter Register TCNT the Pulse Accumulator Control Register PACTL the Pulse Accumulate Counter PACNT the Timer Interrupt Mask Registers 1 and 2 TMSK1 TMSK2 the Timer Interrupt Flag Registers 1 and 2 TFLG1 TFLG2 the Compare Force Register CFORC the PWM Control Register C PWMC and the GPT Prescaler PRESCL GPT Input Captures Window Availability 683xx Hardware Debugger ix Capture Reg Input Pin Edge Val Interrupt Output Is Ic4 both 6666 ENABLED Input Ic3 rising 6666 Disabled Output lo Ic2 falling 6666 ENABLED Output HI IC1 disabled 6666 Disabled Output lo TCTL1 TCTL2 1ED8 THMSK1 TMSK2 82B8 DDGRP 2F PORTGP F2 The GPT Input Captures window displays the Timer Control Registers 1 and 2 TCTL1 TCTL2 the Timer Interrupt Mask Registers 1 and 2 TMSK1 TMSK2 the Port G Data Direction Register DDGRP and the Port G Data Register PORTGP GPT Output Compares Window Availability 683xx Hardware Debugger 121 32MySim32 GPT OC Output Compares E 0 x On On OC1 On 0C1 Reg T
94. Percent 100 0 pwm UC Instructions 24 Instruction Hits 14 Instruction Coverage Percent 58 3 Branches 12 Branch Hits 3 Branch Coverage Percent 25 0 linkchan uc Instructions 8 Instruction Hits 0 Instruction Coverage Percent 0 0 Branches 0 Branch Hits 0 Branch Coverage Percent 100 0 uart UC Instructions 58 Instruction Hits 38 Instruction Coverage Percent 65 5 Branches 30 Branch Hits 13 Branch Coverage Percent 43 3 79 Regression Testing Regression Testing supports the ability to launch MtDt from a DOS command line shell Command line parameters allow specific tests to be run From the command line the project file that is run and the primary script file s that are loaded into each target are specified Command line parameters also are used to specify that the target system automatically start running with no user intervention and to accept the license agreement thereby bypassing the dialog box that would otherwise open up and require user intervention A script command is used to terminate MtDt once all the tests have been run Upon termination MtDt sets the error level to zero if no verification tests failed and otherwise error level is set to be non zero This error level is the application s termination code and can be queried within a batch file running under the operating system s DOS shell By launching MtDt multiple times each time with a different set of tests specified and by checki
95. RAM Test Script Commands RAM test script commands provide a method for verifying internal or external RAM These tests provide both a verification and a diagnostic capability test_address_lines startAddress stopAddress enum ADDR_SPACE numiterations This command runs the address line RAM test between stopAddress and startAddress in the address space ADDR_SPACE for the number of iterations specified by numIterations The test attempts to provide diagnostics on any errors For instance it will attempt to isolate specific address lines as stuck high or stuck low and if successful will report the suspected problem Note that this test verifies only those address lines that are dynamic within memory range being tested For instance address bit 16 which selects between 64K blocks will not be tested unless the memory block straddles a 64K block boundary test_data_lines startAddress stopAddress enum ADDR_SPACE numlIterations This command runs the data line RAM test between stopAddress and startAddress in the address space ADDR_SPACE for the number of iterations specified by numIterations The test attempts to provide diagnostics on any errors For instance it will attempt to isolate specific data lines as stuck high or stuck low and if successful will report the suspected problem test_random startAddress stopAddress enum ADDR_SPACE numlterations This command runs the data line RAM test between stopAddress and startAddress
96. SMSA etc See the Modes form of the CTM6 Double Action Submodule window for display of additional information Real Time Clock Window Availability 683xx Hardware Debugger 32MySim3z2 Real Time Clock RTC z iol x SIC 6047 TICKF F F A 1H2 tick has occured No IL E C Interrupt is disabled when TICKF sets IARB3 B B Interrupt arbitration bit 3 is l Concatenated with BIUMCR IARB 2 0 WEN 9 9 Writes to prescaler and counter are Disabled EN 8 8 The RTC is not running PRR 6166 F 6 RTC prescaler 6166 FRCH 6C66 F 6 Free running counter hi 6C66 FRCL F83A F 6 Free running counter lo F83A The Real Time Clock window displays the RTC Status Interrupt Control Register RT16SIC the RTCSM Prescaler Register RTCSM and the RTCSM Free Running Counter High and Low Registers RI6FRCH RI6FRCL Parallel Port I O Submodule Window Availability 683xx Hardware Debugger SpMySim32 Parallel Port 1 0 CARPA DATA FY Bit Input HI DDR 66 Bit 6 Input lo Bits Input lo Bits Input lo Bit3 Input HI Bit2 Input HI Bit1 Input lo Bit6 Input lo The Parallel Port I O Submodule window displays the PIOSM Control Register PIO17A which controls data direction and either reads or writes the port data TouCAN Main Window Availability 683xx Hardware Debugger 126 CANHCR AIE CANICR 0804F CANCTRLO 4480 PRESDIUZCTRL 6666 ESTAT XXXX RXGMSKHI FFEF RXGHSKLO FFFE RX1
97. TPU hardware This command sets the TPU type and the instruction space size Valid types are 1 through 3 which correspond to TPU1 through TPU3 respectively The instruction space size is expressed in 32 bit long words Supported combinations of types and instruction space sizes are as follows TPU1 256 TPU1 512 TPU2 512 TPU2 1024 TPU2 2048 TPU3 1024 TPU3 2048 write_entry_bank X This command writes the TPU entry bank Valid values depend on the instruction space sze Each bank consists of 512 32 bit long words so the number of valid banks is equal to the instruction space size divided by 512 For the common size of 1024 there are two valid banks so the maximum valid entry bank is 1 Zero is always a valid entry bank set_tpu_type 1 1024 write_entry_bank 1 The commands in this example set the TPU type to TPU1 the instruction space size to 1024 32 bit long words and the entry bank to 1 Setting the TPU Code Bank The following code bank discussion is applicable only to TPU2 and TPU3 There are no script commands for setting the code bank At run time the active code bank is determined during each time slot transition Bits 10 and 9 from the entry table determine the code bank The TPU assembler generally handles this field by determining the bank in which the code is located The user has control over which bank the code is located from within the source TPU microcode One method of specifying the bank in which the co
98. Tpu 0 0x80000 Make sure that no matter which space the TPU accesses within this dock the TPU s data space is always accessed set_block_dock_space HostCpu TpuDataDock ALL_SPACES RW_ALL TPU_DATA_SPACE Create a CPU for modeling the external system instantiate_target SIM32 ModelCpu Add a half meg RAM add_mem_block ModelCpu 0 OXBFFFF RAM ALL_SPACES Add three empty spaces add_non_mem_block ModelCpu 0xC0000 0xC0003 TpuPinsDock ALL_SPACES add_non_mem_block ModelCpu 0xC0004 0xD0003 CpuCpuShare ALL_SPACES add_non_mem_block ModelCpu 0xD0004 MEM_END B2 ALL_SPACES Set the lowest empty block to dock with the TPU target set_block_to_dock ModelCpu TpuPinsDock ALL_SPACES Tpu 0 0xC0000 Make sure that no matter which space the TPU accesses within this dock the TPU s pins space is always accessed set_block_dock_space ModelCpu TpuPinsDock ALL_SPACES RW_ALL TPU_PINS_SPACE Set the middle empty block to dock with the HOST CPU set_block_to_dock ModelCpu CpuCpuShare ALL_SPA CES HostCpu 0x70000 0xC0000 In this example the shared memory architecture from the above figure is generated Simulating Mirrored Memory Mirrored memory is memory that is accessible at multiple address ranges within a memory map This can occur for instance when not all address bits are decoded for a memory device The following figure depicts an 8K memory de
99. U PINS Space FFFFFFFF The following build script commands instantiate the shared memory architecture found in the above figure define MEM_END Oxffffffff Create a target TPU instantiate_target TPU_SIM Tpu Create a simulated memory block for the TPU s code microcode add_mem_block Tpu 0 0x1 fff Code TPU_CODE_SPACE add_non_mem_block Tpu 0x2000 MEM_END B1 TPU_CODE_SPACE Create a simulated memory block for the TPU s data host interface add_mem_block Tpu 0 0x1ff Data TPU_DATA_SPACE add_non_mem_block Tpu 0x200 MEM_END B2 TPU_DATA_SPACE Create a simulated memory block for the TPU s pins channel pins and TCR2 counter pin add_mem_block Tpu 0x0 0x3 Pins TPU_PINS_SPACE add_non_mem_block Tpu 0x4 MEM_END B3 TPU_PINS_SPACE Be sure to provide a non_mem block for the unused address spaces add_non_mem_block Tpu 0x0 MEM_END B4 TPU_LUNUSED_SPACE Create a target host CPU instantiate_target SIM32 HostCpu Add a half meg RAM add_mem_block HostCpu 0 0x7FFFF RAM ALL_SPACES Add three empty spaces add_non_mem_block HostCpu 0x80000 0xFFDFF B1 ALL_SPACES 178 add_non_mem_block HostCpu 0xFFE00 0xFFFFF TpuDataDock ALL_SPACES add_non_mem_block HostCpu 0x100000 MEM_END B2 ALL_SPACES Set the middle empty block to dock with the TPU target set_block_to_dock HostCpu TpuDataDock ALL_SPACES
100. V is a symbol of the appropriate type SymbolExprString must be a symbolic expression as described above an I value in compiler parlance The write_str command is provided as a shorthand way to write a string into the memory pointed to by a symbolic expression Use write_str with caution no effort is made to check that the destination buffer has sufficient space available and the resulting bug induced by such a buffer overflow can be extremely difficult to debug Symbol is defined within the user s code and is determined from the debugging information associated with the executable image Value is the value to which the symbol will be set at_code_tag amp amp Testi Here amp amp write_val FailFlag 0 In the above example the target is run until it gets to the address associated with the source code that contains the text amp amp TestlHere amp amp Once this address is reached symbol FailFlag is set equal to Zero at_code_tag amp amp Test23Here amp amp write_val PlayerBuffer Michael Jordan In this case the string Michael Jordan is written to the buffer named PlayerBuffer If the buffer has insufficient space to hold this string a bug that is difficult to identify would result Verify Symbol Value Script Commands These verify symbol value commands have the same limitations as those commands described in the Write Symbol Value Script Co mmand section moo n verify_val ExprString
101. Variables window automatically displays all local variables in the current context along with their current values Variable names are listed in a column on the left hand side of the window Values are displayed in a matching column on the right hand side The displayed format is relevant to the variable type Additionally if the variable is assigned a register the register is output Based upon type variables are automatically expanded For example if a variable is of type int the dereferenced pointer is displayed on the next line as an integer Default expansion is up to three levels deep with pointers arrays and structures unions bitfields supported An alternative expansion level can be specified See the Local Variable Options Dialog Box section for more information Future enhancements will give the user control over expansion and collapse of variables Note that in order for this feature to be available code must be compiled with symbolic debug information In order for this window to correctly identify and display local variables the proper options for each compiler must be chosen For instance debugging information needs to be included and certain stack frame requirements must be met In certain cases highly optimized code may cause erratic behavior in this window See the ASH WARE Web page for a detailed explanation of the correct compiler settings for each target and limitations when using certain specific compiler settings
102. Wrap to The first QSPI channel to transfer is 6 pointer address 6 The last QSPI channel to transfer is 6 QSPI interrupts are disabled HALTA and MODF interrupts are disabled Halt is not enabled QSPI is not finished Another SPI node requested to become master no QSPI is not halted The last channel executed is 6 4 EFB3 7872 ED DEAS BITS DTL CK 2 HI HI lo HI 5 66DB 96BA DC DEAS BITS std DSCK HI HI lo lo 6 B8F2 FEDB FD DEAS BITS DTL DSCK HI HI lo HI 7 E6FF DBF FF DEAS BITS DTL DSCK HI HI HI HI l l l l l l l l for a delay of 666 615 3 micro seconds l l l l l l l l l l l l 8 9 A B 6747 97F3 EAAF 25AA 15EB E4C7 BF6F F987 1B FD DA 8F PORT DEAS DEAS DEAS 8 BITS BITS 8 std DTL std std DSCK DSCK DSCK CK 2 HI HI HI HI lo HI lo HI HI lo HI HI HI HI lo HI E 9F7A F77B D2 DEAS BITS std DSCK lo lo HI lo Lol x The QSM QSPI window displays the QSPI Control registers 0 1 2 and 3 SPCRO SPCR1 SPCR2 and SPCR3 In addition the QSPI s Receive Transmit and Command RAM RR 0 F TR 0 F and CR 0 F are displayed for each of the 16 locations Below the Command RAM field each of the 16 command RAM locations is broken down by bit groupings These fields are the Continue CONT the Bits per Transfer Enable BITSE the Delay After Transfer DT and the PCS to SCK Delay DSCK QSM SCI UART Window Availab
103. Y_VAL write_chan_entry_condition PWM2_CHAN PWM_ALTERNATE_ENTRY_VAL System configuration commands In this example the UART channels are programmed to use the standard event vector table and the PWM channels are programmed to use the alternate event vector table In the Byte Craft eTPU C Compiler the event vector condition alternate standard for the eTPU function is specified as follows pragma ETPU_function Pwm alternate void Pwm int24 Period int24 PulseWidth In the Byte Craft eTPU C Compiler the event vector mode can be automatically generated using the following macro pragma writ h define PWM_ALTERNATE_ENTRY_VAL ETPUentrytype Pwm Note that setting of the event vector table s base address is covered in the System configuration commands section write_chan_entry_pin_direction ChanNum Val This command writes channel ChanNum s event vector pin direction to Val Note that this writes the CxCR register s ETPD field A value of 0 uses the channel s input pin and a value of 1 uses the output pin define ETPD_PIN_DIRECTION_INPUT 0 define ETPD_PIN_DIRECTION_OUTPUT 1 write_chan_entry_pin_direction UART1_CHAN ETPD_PIN_DIRECTION_INPUT write_chan_entry_pin_direction UART2_CHAN ETPD_PIN_DIRECTION_OUTPUT 47 In this example the UART1 chan event vector table thread selection is based on the input pin and UART2 event vector thread selection is based on the output pin eTPU Interrupt Scr
104. _RETURN_ADDR enum REGISTERS _U8 REG_LINK enum REGISTERS _U5 REG_CHAN enum REGISTERS _U1 REG_Z REG_C REG_N REG_V REG_MZ REG_MC REG _MN REG MV The following are examples of how the enumerated register types are used 63 write_reg32 0x12345678 REG P verify_reg32 REG_P 0x12345678 write_reg24 0x123456 REG_A verify_reg24 REG_A 0x123456 write_reg16 0x1234 REG_RETURN_ADDR verify_reg16 REG_RETURN_ADDR 0x1234 write_reg5 0x12 REG_CHAN verify_reg5 REG_CHAN 0x12 write_reg1 0x1 REG_Z verify_regl REG_Z 0x1 TPU Register Enumerated Data Types The TPU register enumerated data types provide the mechanism for referencing some of the TPU registers These enumerated data types are used in commands that reference the TPU registers such as the register write commands that are defined in the Write Register Script Commands section There are no enumerated types for the TPU s 8 bit registers and the TPU has no 32 bit registers The following enumeration provides the mechanism for referencing the TPU s 16 bit registers Note that this covers only those TPU registers that are newly accessible with this software version Future software versions will make greater use of this enumerated data type enum REGISTERS_U16 REG_TCR1 REG_TCR2 Counter registers CPU32 Register Enumerated Data Types The CPU32 register enumerated data types provide the mechanism for refe
105. able Continuous Verification This enables continuous verification of behavior against the currently active master behavior verification file This provides immediate feedback if the microcode behavior has changed See the Pin Transition Behavior Verification section for a description of this capability Disables Continuous Verification This disables continuous verification of behavior against the currently active master behavior verification file This prevents a large number of verification errors from being displayed if microcode behavior has changed significantly See the Pin Transition Behavior Verification section for a description of this capability Timer This lists a variety of options available for timers These options are only available if a Source Code File window is selected Options include setting the timer s start or stop address to be equal to that associated with the cursor location within the Source Code File window A timer can also be enabled or disabled Watch This lists a variety of options available for a watch These options are available only if a Watches window is selected Options include inserting and removing a watch moving a watch up or down and setting the options for a specific watch Help This accesses this help screen Help Menu The Help menu provides the following options Contents This accesses the contents screen of MtDt s on line help program Using Help This accesses the standar
106. abled 66661666 66662666 FFFFFFFF 666 666 6 H Disabled 66661666 66062666 FFFFFFFF 006 000 0 D Disabled 66661666 66662666 FFFFFFFF 666 666 6 E F Finished 66666692 G66066AE 66666667 66660607 666 661 4 Disabled 66661606 66662666 FFFFFFFF 666 666 56 The Timers window displays the state of the 16 ASH WARE timers See the Integrated Timers chapter for a detailed explanation Each row of the window contains information regarding a single timer The ID field on the far left indicates which of the 16 timers the row represents The State field is to the right of the ID field This field indicates the current state of the timer The possible states are generally disabled armed started finished and overrun Double clicking with the left mouse button forces the timer into the next state The timer can also be forced into a specific state by typing the first letter of the desired state The Start Address and Stop Address fields are to the right of the State field These fields contain the addresses that when accessed by the target cause the state to change For instance a timer in the armed state changes to the started state when the start address is executed Then when the stopped state is executed the timer progresses to the finished state The This Ticks and the Last Ticks fields are to the right of the Stop Address field These fields indicate how many clock ticks of the target have occurred for any timer calculation Why are these spli
107. ads In this example the channels are issued a host service request then after 100 microseconds presumably sufficient time to initialize the threads indices are reset Disable Messages Script Commands Pin transition verification failures and script command verification failures result in a non zero return code when the application exits as well as display of a dialog box to inform the user of the failure This dialog box can be disabled in the Messages dialog box but this must be done manually each time the application is launched In certain cases such as tool qualification under DO178B it is desirable to disable display of the dialog box such that the test of the verification test can be automated This is done as follows disable_message PIN_TRANSITION_FAILURE disable_message SCRIPT_FAILURE THESE COMMANDS SHOULD BE USED WITH EXTREME CAUTION They remove observe ability from verification failures 44 In all cases except automation of test of the verification tests it is preferable to disable the display of the verification messages manually from within the Messages dialog box eTPU System Configuration Script Commands write_entry_table_base_addr Addr This command writes the Event Vector Table s address It writes a value into the ETPUECR register s ETB field that corresponds to address Addr define MY_ENTRY_TABLE_BASE_ADDR 0x800 write_entry_table_base_addr MY_ENTRY_TABLE_BASE_ADDR In the above e
108. ads 6 FORCB 5 5 Set to force channel B compare always reads 6 EDPOL 4 4 is A compare on channel A sets the ouptut pin to logic 1 l l A compare on channel B clears the ouptut pin to logic 8 MODE 3 0 OPWM Output pulse width modulation 16 bit resolution DATA A GBBS F 6 The DATA A register value is 6BBS DATA B E97B F 6 The DATA B register value is E97B a a a etd DASH 4 SSeS SS SSSaee Sessa Sa Sessa SSS esses sssSSSSsS sic 6606 FLAG F F I An input capture or output compare has not occured zi The CTM4 Double Action Submodule window displays the DASM 3 4 9 and 10 Status Interrupt Control Registers DASM3SIC DASM4SIC DASM9SIC DASM10SIC and the DASM 3 4 9 and 10 Data Register A and B registers DASM3A DASM4A DASM9A DASM10A DASM3B DASM4B DASM9B and DASM10B CTM4 Pulse Width Modulation Submodule Window Availability 683xx Hardware Debugger x SIC 2800 FLAG F F A PWM period is not complete IL E C PWM interrupt is level 2 IARB3 B B PWM interrupt arbitration bit 3 is l Concatenated with BIUMCR IARB 2 6 PIN 7 7 The PWM output pin is Low LOAD 5 5 SET to load pulse width always reads 6 POLZEN 4 3 Always low POLZEN 4 3 CLK 2 0 CLK is 6 for a period of 666 119 2 Fsys 2 PER F463 F 6 The PERIOD is F463 PW 9D1E F 6 The PULSE WIDTH is 9D1E CNT 6661 F 8 The COUNTER is 6601 Sasnals esse PH G SS Saseeeessesee asia se srisea ess ee aS a
109. alue is also displayed The active channel number is displayed Since the active channel can be changed via the microcode when the CHAN register is modified the active channel numbers corresponding to the current previous and second most previous microcycles are displayed The last channel number is that of the channel that was initially being serviced after the time slot transition This allows the user to calculate which channel a particular parameter is associated with for those parameters that take multiple microcycles to adjust after the CHAN register is changed The current opcode and prefetch opcode are displayed in this window Sequencing microinstructions that affect program flow may flush the prefetch opcode causing a NOP to be executed Loading a OXFFFFFFFF as the current opcode simulates this situation The DEC register is used for various purposes such as loop indexing and subroutine termination The current DEC usage is displayed When MtDt is in TPU2 or TPU3 mode the two bank fields are displayed The code bank is the bank in which code is being executed The entry bank is the bank from which the active entry table is stored In the real TPU the entry bank is specified via the TPUMCR2 register at bit positions 5 and 6 In MtDt this entry bank register is modified by the write_entry_bank script command TPU Execution Unit Window Availability TPU Simulation Target 109 A TpuSim Exec Unit AU Male Ea tert peg terz
110. ame The size of the memory block is equal to one plus stopAddress minus startAddress Only a single copy of this memory is created regardless of how many address spaces the block occupies 54 add_mem_block MyCpu 0 0xFFFF RAM1 ALL_SPACES In this example a 64K block of simulated memory is created and the name RAM1 is assigned to this memory block This memory is accessible from all of the CPU s address spaces add_non_mem_block TargetName StartAddress StopAddress enum ADDR_SPACE This command adds a blank block of simulated memory to the target TargetName It indicates that no physical memory exists in the specified memory range and specified address spaces ADDR_SPACE The name BlockName is assigned to this block and is used by other script commands when referencing this block The block name must be unique within its target but other targets can have a block with this same block name Since no memory is actually modeled by this command it effectively uses almost none of your computer s virtual memory This is important since the entire four GB address space must be represented by memory blocks regardless of whether or not the simulation target actually supports this large of an address space define DATA_SPACE CPU32_SUPV_DATA_SPACE CPU32_USER_DATA_SPACE add_non_mem_block MyCpu 0x1000 Oxffffffff Empty DATA_SPACE This example specifies that no physical memory exists above the first 64K for both user an
111. and verification against this buffer is not possible A warning is generated if the user attempts to save a master behavior verification file when the buffer has rolled over The second consideration is TCR2 pin recording Normally TCR2 pin transitions are not written in these buffers This is because the recording of TCR2 pin transitions very quickly fills up the buffer and causes the buffer to quickly roll over When the buffer rolls over verification is not possible 77 Code Coverage Analysis Code coverage analysis is one of the verification capabilities for which an overview is given in the Functional Verification chapter There are two aspects to code coverage The first aspect is the code coverage visual interface while the second aspect is the coverage verification commands Code Coverage Visual Interface The visual interface is enabled and disabled using within the IDE Options dialog box When this is enabled black boxes appear as the first character of each source code line that is associated with a microinstruction As the code executes and the instruction coverage changes these black boxes change to reflect the change in the coverage This is summarized below A black box indicates a non branch instruction that has not been executed A blue box indicates a branch instruction that has not been executed A green box indicates a branch instruction where the branch path has been traversed T A red box indicates a branch i
112. ands Clock control script commands Timing script commands Modify memory script commands 30 Verify memory script commands Register write script commands Register verification script commands Symbol value write script commands Symbol value verification script commands System script commands File script commands Trace script commands Code coverage script commands RAM test script commands 4 ETPU TPU Script Commands Channel function select register script commands Channel priority register script commands Host service request register script commands Interrupt association script commands External boolean logic script commands Pin control and verification script commands Pin transition behavior script commands Ney Pin transition buffer script commands Disable messages script commands heon Clear Worst Case Thread Indices Commands eTPU Script Commands System configuration commands Timing configuration commands Channel data commands Channel base address commands Channel function mode FM commands ys Channel event vector entry commands Interrupt script commands TPU Script Commands TPU parameter RAM script commands 2 TPU channel interrupt service register script commands 9 TPU host sequence request register script commands 31 TPU clock control script commands TPU bank and mode control script commands TPU match transition and link script commands
113. annel GPT Main Window Availability 683xx Hardware Debugger 120 32MySim32 GPT Main g la x GPTHCR 3881 STOP F F GPT clocks are not shut down FRZ1 E E FR21 is not used FR26 D D When FREEZE on IMB halt the GPT STOPP C C NJIA LE eT ee Tee ert ule eee ee La E LEE INCP B B On STOPP increment prescaler amp input synchronizers once SUPU 7 7 SZU registers access at Supu priviledge level IARB 3 6 Interrupt arbitration priority 1 GPTICR 2366 IPA F C Make Input Capture 2 highest priority IPL A 8 Interrupt priority is level 3 IUBA 7 4 Interrupt vector base address is 6X DDGRP PORTGP 2FF2 DDGRP F 8 Pin Direction is 2F see other windows PORTGP 7 6 Pin Data is F2 see other windows oc1N 0C1D F8E0 OC1M F B OC1M Action Mask is 1F see Output Compare window IPA 7 3 OC1D Action Data is 1C see Output Compare window TCNT 1344 F 6 Timer counter register is 1344 PACTL PACNT 6466 14705 A A Output compare 5 Disable Input capture 4 ENABLE l See Pulse Accumulator window for most settings TMSK1 TMSK2 82B8 See other windows for most settings TOI 7 7 Interrupt requested when TOF flag is set CPROUT 3 3 TCNT clock driven out 0C1 pin CPR 2 0 CPR 6 TCNT Capture Compare clock period is 606 256 1 ns or Fsys 4 l l TFLG1 TFLG2 1636 TOF 7 7 Timer Overflow flag is clr CFORC PWHC 2B84 See Output Compare and PWH windows for most settings
114. ariables thereby viewing a reference to the beginning of the buffer Note that the function name and frame address are determined by the window s current display state The functionName is a symbolic name of a function e g main char argc char argv The frame address is the address such as 0x 1000 Maximum Expansion Level for Structure Members Pointers etc It is common for structures to be members of other structures or to be referenced from within structures The local variable window expands these contained and referenced structures This setting specifies the number of levels to expand Maximum Number of Array Elements to Display This specifies the number of local variable array members that are displayed For example an integer array might consist of multiple members but the actual number of members is generally not available in the symbol table This setting allows you to specify how many elements to display License Options Dialog Box This dialog box allows you to enter additional information prior to sending a license file to ASH WARE Inc A license file is generated whenever you install an ASH WARE product Unfortunately the license file generated at install time contains very little information other than a computer identifier This dialog box allows you to add additional information such as your name purchase order number etc The license file has been a problem for ASH WARE in that users have sent in license files for
115. arily across the Channel Interrupt Service Request CISR register and the parameter RAM The data flow verification capabilities address data flow across these registers The parameter RAM data flow is verified using the verify_ram_word X Y Z and verify_ram_bit X Y Z V script commands described in the TPU Parameter RAM Script Commands section The data flow across the CISR register is verified using the verify_cisr X Y script command described in the TPU Channel Interrupt Service Register Script Commands section In the following example data flow across channel 10 s CISR and parameter RAM is verified at a simulated time of 100 microseconds and again at 250 microseconds Wait until MtDt has run 100 micro seconds at_time 100 Verify that channel 10 s CISR is set verify_cisr Oxa 1 Verify that channel 10 s parameter 2 bit 14 is set verify_ram_bit 0xa 2 14 1 Verify that channel 10 s parameter 3 is 1000 hex verify_ram_word 0xa 3 0x1000 Verify that channel 10 s parameter 5 is 1500 hex verify_ram_word 0xa 5 0x1500 Clear channel 10 s CISR clear_cisr Oxa Wait until MtDt runs an additional 150 microseconds wait_time 150 Verify that channel 10 s CISR is set verify_cisr Oxa 1 Verify that channel 10 s parameter 2 bit 14 is cleared verify_ram_bit 0xa 2 14 0 Verify that channel 10 s parameter 3 is 3000 hex verify_ram_word 0xa 3 0x3000 Verify that channel 10
116. as hen neenS ae SIC 6666 FLAG F F A PYM period is not complete zl The CTM4 Pulse Width Modulation Submodule window displays the DASM 5 6 7 and 8 Status Interrupt Control Registers PWM5SIC PWM6SIC PWM7SIC PWMBSIC the DASM 5 6 7 and 8 Period Registers PWM5PER PWM6PER PWM7PER PWM8PER the DASM 5 6 7 and 8 Pulse Width Registers PWM5PW PWM6PW PWM7PW PWM8PW and the DASM 5 6 7 and 8 Count Registers PWMSCNT PWM6CNT PWM7CNT PWM8CNT CTM6 Single Action Submodule Window Availability 683xx Hardware Debugger 124 52 MySim32 CTM6 Single Actions SASM Input capture or output compare has occured I Interrupt level is Shared by A and B l Interrupt arbitration bit 3 IARB BIUMCR IARB 2 6 I Interrupts are disabled enabled l Use time base bus A or time base bus B I l I Pin state when input or flip flop state when output l l l Set to force output compare always reads 6 I l Capture edge match action or output pin state l l l l Operating mode lo0 x SIC DAT FLAG IL IARB IEN BSL IN FORCE EDOUT MODE SASH12A 6661 6666 No DIS clr dis A lo 6 clr gt Output Port pin set high SASMH12B E364 6666 Yes DIS clr dis B lo 1 clr IC gt Input Capture on falling edge SASMH14A 1861 6666 No 1 SET dis A lo 8 clr OP gt Output Port pin set high SASH14B 6645 6666 No 14 SET dis A lo 6 clr OP gt Output Port pin set high SASH18A 6666 6666 No DIS clr dis A lo 8 clr IC gt Input
117. as not detected on the received data PE 6 6 A parity error did not occur on the received data SCDR 6656 RDR 8 6 Receive data register 6056 read only l 8 6 Transmit data register 6655 write only read value is meaningless The QSM SCI window displays the SCI Control registers 0 and 1 SCCRO and SCCR1 the SCI Status Register SCSR and the SCI Data Register SCDR Masked ROM Window Availability 683xx Hardware Debugger CS lt lt 2101x MRMCR ERY STOP F F ROM array is is in low power stop mode BOOT C C ROM does not responds to bootstrap word locations during reset vector fetch LOCK B B ROM Write lock enabled Protected registers and fields cannot be written ASPC 9 8 ROM array is accessible at the unrestricted program and data priviledge level WAIT 7 6 ROM array accesses take 2 wait states ROMBAH 6456 AD HI 7 6 ROMBAL 4666 AD LO F C Base address is 04564606 RSIGHI 1234 RS HI 7 6 ROM signature high register is 1234 RSIGLO 5678 RS LO F 6 ROM signature low register is 5678 ROMBS6 1661 BS 6 F 6 ROM bootstrap word 6 is 1661 ROMBS1 2222 BS 1 F 6 ROM bootstrap word 1 is 2222 ROMBS2 3333 BS 2 F 6 ROM bootstrap word 2 is 3333 ROMBS3 12AC BS 3 F 6 ROM bootstrap word 3 is 12AC The Masked ROM window displays the Masked ROM Module Configuration Register MRMCR the ROM Array Base Address High Register ROMBAH the ROM Base Address Low Register ROMBAL t
118. ase address is 606666666 RAMDS 6 6 TPURAM array is Disabled The TPU Emulation RAM window displays the TPURAM Module Configuration Regis ter TRAMMCR and the TPURAM Base Address Register TRAMBAR TPU Main Window Availability 683xx Hardware Debugger 32 MyBdm32 TPU Main oy x TPUNCR STOP F F TPU Module is operating normally TCR1P E D TCR1 prescaler divides by 1 TCR2P C B TCR2 prescaler divides by 1 ENU A A TPU executes out of standard mask ROM T2CG 9 9 TCR2 pin used as clock source for TCR2 STF 8 8 TPU is operating normally SUPU 7 7 TPU SZU registers access at Supu priviledge level PSCK 6 6 Clock input to the TCR1 input is the system clock 32 IARB 3 6 TPU interrupt arbitration priority 6 l TCR1 counter clock period is 666 663 8 micro seconds l TCR2 counter clock period is micro seconds l The TCR2 counter clock source is the TCR2 input pin divided by 1 TICR 66066 CIRL A 8 Channel interrupt request level is 6 CIBU 7 4 Channel interrupt base vector is 6 l l interrupt vector is 6x66 plus channel number The TPU Main window displays the TPU Module Configuration Register TPUMCR and the TPU Interrupt Configuration Register TICR TPU Host Interface Window Availability 683xx Hardware Debugger 119 32 MyBdm32 TPU Host I F oO x FEDcCGeBAS 8 7 6 5 amp 8 21 8B cs E 6 6 6 6 6 6 6 6 6 6 6 6 6B BB 0000 0666 66600 60600 CPR 66
119. ation of an arbitrary number and combination of TPUs and CPU32s A dedicated external system modeling CPU32 could be used for instance to model the behavior of an automobile engine Executable code can be individually loaded into each of these targets Synchronization between and among targets is fully retained as the full system simulation progresses Standard single target debugging capabilities such as single stepping breakpoints goto cursors etc are fully supported within this full system simulation environment For instance breakpoints can be inserted and activated within several targets simultaneously The full system simulation is halted as soon as a breakpoint is encountered in any target TPU CPU16 System Simulator Our TPU CPU16 System Simulator supports instantiation and simulation of an arbitrary number and combination of TPUs and CPU16s A dedicated external system modeling CPU16 could be used for instance to model the behavior of an automobile engine Executable code can be individually loaded into each of these targets Synchronization between targets is fully retained as the full system simulation progresses Standard single target debugging capabilities such as single stepping breakpoints goto cursors etc are fully supported within this full system simulation environment For instance breakpoints can be inserted and activated within several targets simultaneously The full system simulation is halted as soon as a break
120. ation would be one excellent application All such utilities will remain in the public domain Trace Buffer Size Considerations The trace buffer is a set size To increase the effective size it is often desirable to disable certain 66 types of events Disabling and enabling of trace events is accomplished by selecting the Trace submenu from the Options menu 67 TEST VECTOR FILES Overview Test vector files are currently available only for TPU and eTPU targets and are target centric in that they can act only on the specific target into which they have been loaded Future versions of this software will globalize test vector files so that they can act on multiple targets and on any addressable bit in any target s address space The TPU simulation engine provides a complex test vector generation capability This allows the user to exercise the simulated TPU with signals similar to those found in a typical TPU environment Test vector scripts are read from user supplied test vector files and normally have a vector extension Test vector files are used for creation of high or low states typically at the TPU s I O pins Note that this capability is available only for the TPU simulation engine It is helpful to compare test vector files to primary and ISR script commands files Roughly test vector files represent the external interface to the TPU while script commands files represent the CPU interface Test vector files are treated q
121. ble information is not The instruction hits line lists the number of instructions that have been fully covered The instruction coverage percent line lists the percent of instructions that have been covered The branches line lists the total number of branch paths This is always an even number because for each branch instruction there are two possible paths branch taken and branch not taken If the branch path has been traversed then this counts as a single branch hit Conversely if the non branch path has been traversed then this also counts as a single branch hit The branch instruction is considered fully covered when both the branch path and the non branch path have 78 been traversed The branch coverage percent line contains the percentage of branch paths that have been traversed Flushed instructions for which a NOP has been executed are not counted as having been covered An example of such a file follows Code coverage analysis file Copyright 1996 1997 ASH WARE Inc Sun June 02 09 30 30 1996 Total Instructions 135 Instruction Hits 57 Instruction Coverage Percent 42 2 Branches 60 Branch Hits 16 Branch Coverage Percent 26 7 MAKE ASC Instructions 2 Instruction Hits 0 Instruction Coverage Percent 0 0 Branches 0 Branch Hits 0 Branch Coverage Percent 100 0 toggle UC Instructions 5 Instruction Hits 5 Instruction Coverage Percent 100 0 Branches 0 Branch Hits 0 Branch Coverage
122. can move the cursor within the file using the Home End up arrow down arrow Page Up and Page Down keys When adding or toggling breakpoints and using the Goto Cursor function the cursor location is an important reference MtDt searches first down then up starting from the cursor to find a source line corresponding to an instruction The executable source code can be quickly reloaded from the Files menu by selecting the Executable Fast submenu This is normally required when the user has made a change to the executable source code and has re built it Mixed Assembly View To make visible the dis assembled instructions associated with each line of source code select the Toggle Assembly Mixed submenu from the Options menu For TPU targets the 32 bit 90 hexadecimal equivalent of the micro instruction is displayed For CPU targets the actual disassembly is displayed Coverage Indicators The little black green red and white indicators on the left side of the source code window are graphical indications of code coverage as explained in the Code Coverage Analyses section Script Commands File Windows Model16 Script Demo Cpu16Command ioj x Script File Dump an image to a disassembly dump file dump_file 6x22 6x4444 CPU16_CODE_SPACE DumpFile Disfsm DIS_ASH INCLUDE_ADRS INCLUDE_HEX Write E write_reg4 0xC REG_ZK Write and verify memory U8 U8 0x7000 6x92 verify_mem_u8 6x7666
123. cannot redirect a memory access to another target is said to be intrinsic For example a CPU32 hardware such as a 68332 exposed across a BDM port is intrinsic All memory accesses initiated by the CPU32 must occur within the address space of that CPU32 and cannot for example be redirected to memory owned by a simulated TPU Miscellaneous Capabilities MtDt has a number of additional features not yet mentioned These include project sessions source code files functional verification external logic simulation integrated timers multiple workshops a rich set of dialog boxes a standard Windows style menu system and a Windows style IDE with hot keys a toolbar and target status indicators 14 SOFTWARE DEPLOYMENT UPGRADES AND TECHNICAL SUPPORT World Wide Web Software Deployment All ASH WARE software is now deployed directly from the World Wide Web This is done using the following procedure Download and install a demo version of the desired software product All software products supported by MtDt are available at a demonstration level Purchase the software product s either from ASH WARE or one of our distributors E mail to ASH WARE the license file named AshWareComputerKey ack found in the installation directory Wait until you receive an email notification that the information from your license file has been added to the MtDt installation utility 2 Download and re install MtDt again The software product s
124. chnical Support Contact Information With the purchase of this product comes a one year software subscription and free technical support This technical support is available through Email the World Wide Web and telephone Contact information is listed below 503 533 0271 phone www ashware com support ashware com Overview of Version 3 41 3 40 3 20 3 10 3 00 2 1 and 2 0 Enhancements bev The following is a list of the features that are new to the MtDt version 3 41 Ney Extended eTPU code coverage to include event vectors Ney Inferred event vector coverage Ney Accumulate coverage over multiple tests Ney View channel nodes Neu Write and verify chan_datal6 commands bea View critical thread execution indices Ney Clear Worst Case Thread Indices Commands Ney Resizing the Pin Transition Buffer Testing Ney Cumulative Logged Regression Testing The following is a list of the features that are new to the MtDt version 3 40 and 3 30 Complex Breakpoint Window eTPU Stand Alone Simulator Product eTPU CPU System Simulator Product Multiple target scripting Added ability to view thread group activity in the logic analyzer window Improved Regression Testing section Added the include directive to script commands files Added ifdef ifndef else endif preprocessing to script command files Added automatic defines to script command files The following is a list of the features that ar
125. cle gt lt TeethPerCycle gt This command supports specification of angle indices required to display current angular information in various portions of the visual interface including the Global Time and Angle Counters window In a typical automotive application the angle hardware is used as a PLL on the actual engine Typically two engine revolutions is defined as a cycle so a cycle is defined as 720 degrees Also a typical crank has 36 teeth and rotates twice per engine revolution The following script command generates this configuration This configures the visualization of the crank define DEGREES_PER_CYCLE 720 45 define TEETH_PER_CYCLE 72 set_angle_indices DEGREES_PER_CYCLE TEETH_PER_ CYCLE These command configures an angle visualization for a cycle of 720 degrees and a crank with 36 teeth which rotates twice per cycle yielding 72 teeth per cycle 1 ETPU Channel Data Script Commands write_chan_data32 ChanNum AddrOffset Val write_chan_data24 ChanNum AddrOffset Val _ write_chan_datal16 ChanNum AddrOffset Val Neus write_chan_data8 ChanNum AddrOffset Val verify_chan_data32 ChanNum AddrOffset Val verify_chan_data24 ChanNum AddrOffset Val _ verify_chan_datal6 ChanNum AddrOffset Val Bere verify_chan_data8 ChanNum AddrOffset Val This command writes channel ChanNum s data at address AddrOffset to value Val Note that 32 bit numbers must be located on a double even address boundary
126. created from the first 64K of supervisor code space and both address mode and symbolic information are excluded Assuming the target processor is a CPU32 the generated assembly code is for the CPU32 Trace Script Commands start_trace_stream FileName Trace enum TRACE_ EVENT_OPTIONS enum TRACE_FILE_OPTIONS enum BASE_TIME U32 numTrailingDigits U32 isResetTime This command saves the target s trace buffer to file FileName trace with the options set by TRACE_EVENT_OPTIONS TRACE_FILE_OPTION and BASE_TIME_ OPTIONS The time field has numTrailingDigits trailing digits and the initial time can be set to the time at which the trace file is executed by setting the isResetTime field to non zero Note that all events specified in the script command must be currently enabled within MtDt for the command to succeed Note also that the BASE TIME and numTrailingDigits digits apply ONLY if the TRACE_FILE_OPTION is set to PARSEABLE If the specified file type is VIEWABLE than these options are taken from the trace window settings so that the trace file looks like the trace window end_trace_stream 37 This command stops tracing to a stream and closes the file so that it can be opened by a text viewer that requires write permission on the file print_to_trace Message This command prints the string Message to the trace assuming it is enabled in the Trace Options dialog box at_time 400 start_trace_stream Stream Trace A
127. ct the ungroup option to see 96 eTpu1 ThreadStats RevA c loj x Table THREAD STEPS Addr Addr Cnt WC Tot WC Time O 6046 62FC 2 2 4 O49 nS RE_INIT_INTERRUPT 1 0042 62FC 6 8 RE_INIT_INTERRUPT 2 6044 62FC 8 RE_INIT_INTERRUPT 3 68646 62FC a 8 RE_INIT_INTERRUPT 4 6648 6200 4 18 18 368nS INITIALIZE 5 664A 6508 8 INUALID_THREAD_FAULT 6 OOC 8560 8 INVALID THREAD FAULT 7 OOE 8560 8 INVALID THREAD FAULT 8 0050 G4E4 8 LINE_WENT_IDLE_FAULT 9 0052 0478 8 VALID GAP_NO DATA HO 6054 OMEN o B LINE _VENT_IDLE_FAULT 11 0056 63E8 9 16 123 3290nS VALID GAP AND DATA 12 0058 Q4E4 8 LINE _WENT_IDLE_FAULT 13 OOSA 0478 8 UALID_GAP_NO_DATA 14 005C O4EY 8 LINE _WENT_IDLE_FAULT 15 005E 436 8 UALID_GAP_AND DATA 16 6660 6304 8 RECEIVED DATA BIT 6 23 17 6062 G4B4 8 BIT_DETECTED_IN_GAP_HUNT 18 0664 6368 8 RECEIVED DATA BIT 24 31 19 0666 6498 6 8 TOO MANY BITS FAULT 20 6668 6304 115 25 2338 50 nS RECEIVED DATA BIT 6 23 21 OOSA B4B4 8 BIT_DETECTED_IN GAP_HUNT 22 986C 6368 25 23 529 460 nS RECEIVED DATA BIT 24 31 23 006E 6498 8 TOO MANY BITS FAULT 24 0070 6304 8 RECEIVED DATA BIT 6 23 25 0072 0478 8 UALID_GAP_NO_DATA 26 0074 6368 8 RECEIVED DATA BIT 24 31 27 0676 83E0 8 UALID_GAP_AND DATA 28 0078 6304 6 8 RECEIVED DATA
128. ctivate Menu View Menu Window Menu Options Menu Help Menu Files Menu The Executable Open submenu This opens the Load Executable dialog box The Executable Fast Submenu This provides a fast repeat capability for the Load Executable dialog box By selecting this submenu the actions set up in the Load Executable dialog box are quickly repeated without having to actually open the dialog box The Primary Script Open Submenu This opens the Open Primary Script File dialog box The Primary Script Fast Submenu This provides a fast repeat capability for the Open Primary Script File dialog box By selecting this submenu the actions set up in the Open Primary Script File dialog box are quickly repeated without having to actually open the dialog box The Primary Script Report Submenu This opens the Save Primary Script Commands Report File dialog box This report file is generated when the primary script commands file is parsed The Startup Script Open Submenu This opens the Open Startup Script Commands File dialog box This script commands file is 156 executed after MtDt resets its targets The Vector Open Submenu This opens the Open Test Vector File dialog box The Vector Fast Submenu This provides a fast repeat load test vector file capability By selecting this submenu the last loaded test vector file is reloaded The Project Open Submenu The Project Open submenu opens the Project Open dialog box Each
129. d supervisor data spaces Data space is defined by the define declaration as consisting of a combination of the supervisor data space and the user data space set_block_to_off TargetName BlockName enum ADDR_SPACE enum READ_WRITE This command allows accesses of a simulated memory blocks can be turned off using this script command Using this command a read only memory device such as a ROM can be created Accesses to target TargetName within the block BlockName and specified address spaces ADDR_SPACE and read and or write cycles lt enum READ_WRITE gt are turned off A turned off write access behaves exactly like a normal write access except the actual memory is not written A turned off read cycle behaves exactly like a regular read cycle except that the value returned is the OFF_DATA constant defined for the entire block The affected address spaces and read and or write cycles must be subsets of those of the referenced memory block add_mem_block MyCpy 0 0xFFFF ROM ALL_SPACES define ALL_WRITES RW_WRITES8 RW_WRITE16 RW_WRITE32 set_block_to_off MyCpu ROM ALL_SPACES ALL_WRITES This example creates a 64K memory device and configures it to be a read only or ROM memory device set_block_off_data TargetName BlockName enum ADDR_SPACE OFF_DATA This command specifies that read cycles to the target TargetName within the block BlockName return the data lt OFF_DATA gt but only if the block is either a
130. d Microsoft Windows help on help program Latest Enhancements This accesses information on the enhancements added in the various versions of this software Technical Support This accesses information on obtaining technical support for this product About This gives general information about MtDt 162 HOT KEYS TOOLBAR AND STATUS INDICATORS Pointing and clicking with the mouse activate Toolbar buttons The toolbar is located toward the top of the main screen Toolbar buttons also allows you to quickly switch between workshops These are the text buttons located at the top right of the main screen An execution status indicator appears at the top right of the main screen This indicator appears as a moving error while the targets are executing When the targets are stopped a bitmap appears that depicts the cause of the halt An active target button appears at the top right of the main screen This button lists the active target Depressing this button causes a list of all targets to appear as a menu Selection of a target from this menu causes that target to become activated The status window is located at the bottom of MtDt Miscellaneous information is displayed in this window Both the toolbar and the status window can be hidden as explained in the Options Menu section At the bottom right of the main window is a menu help indicator This indicator shows the function of all menus and toolbar buttons prior to selectio
131. d by depressing the lt F1 gt function key when the window is active Theory of Operation MtDt associates the user s source code with the executable code generated by the compiler assembler and linker This ability provides the following important MtDt functionality R Highlight the active instruction 2 Set toggle breakpoints 7 Execute to cursor In order for MtDt to read the executable code the source code must be compiled assembled and linked The resulting executable file can then loaded into MtDt The name of the executable file varies quite a bit from one vendor and tool to another Generally TPU microcode executable files have a LST suffix while a compiler linker might produce a file named A OUT Source Code Search Rules Source code files may be contained in multiple directories In order to provide source level debugging MtDt must be able to locate these files Source code search rules provide the mechanism for these files to be located by the MtDt The search rules are as shown below These rules are performed in the order listed If multiple files with the same name are located in different directories the first encountered instance of that file per the search rules will be used Search relative to the directory where the main build file such as A OUT is located Search relative to the directories established for the specific target associated with the source code Search relative to the global directories es
132. d file allows direct building of the executable image from within MtDt and is covered in the Auto Build Batch File Options Dialog Box section The pin transition behavior verification file name is displayed This new feature supports the verification of TPU behavior against previously saved pin transition behavior files This allows the user to make changes to a test suite and automatically determine which pin transition behaviors have changed and which behaviors have stayed the same See the Pin Transition Behavior Verification section ISR Files The currently loaded script commands ISR files associated with each TPU interrupt are listed Script commands files can be associated with TPU interrupts When the interrupt associated with a particular TPU channel becomes asserted the ISR script commands file associated with that channel gets executed Script commands ISR files are loaded using script commands See the ISR Script Commands Files section for a description 107 TPU Host Interface Window Availability TPU Simulation Target 32 MyBdm32 TPU Host I F ioj x FEDcCBA 8 7 6 5 amp 3 21 86 crsk E 6 6 6 6 6 6 6 8 6 8 6 6 6 BB 8660 6600 0000 0000 CPR 66 OO OO OG OG OO ON OO OO OO OG OA GO OO OG 0G 009090 0000 HSRR 66 66 66 66 66 OO OO OO OO GO OG OG O HO HA 0G 9660 6060 HSQR 66 OO 66 OO 66 OO ON OO OO OO OG 66 OO ON OG 0G 00090 0009 CISR 0 0 6 6 6 6 6 6 6 6 6 AAGA GAG 9000 CIER 6 0 6 6 6 6 6 6 68 6 6 GAA A 9060
133. de will reside is the ORG statement This and other methods are described in the TPU assembler literature TPU Match Transition and Link Script Commands set_mrl ChanNum set_tdl ChanNum set_link ChanNum These commands directly sets the Match Recognition Latch MRL the Transition Detection Latch TDL or a Link Service Request LSR of channel ChanNum set_mrl 5 set_tdl 3 set_link 8 In this example channel 5 s MRL is set channel 3 s TDL is set and a link is generated on channel 8 eTPU TPU Interrupt Association Script Commands Interrupt association script commands associate a script commands file with the firing of interrupts such that when the interrupt is both enabled and active the script commands file executes See the Script Commands Files chapter for a description of the use of ISR script commands files load_chan_isr filename eTpuCommand ChanNum eTPU Only 52 load_data_isr filename eTpuCommand ChanNum eTPU Only load_exception_isr filename eTpuCommand eTPU Only load_isr filename TpuCommand ChanNum TPU Only In order for the ISR script to actually execute the ISR must be enabled The following script commands enable and disable ISRs for both the eTPU and TPU enable_chan_intr chanNum eTPU Only disable_chan_intr chanNum eTPU Only enable_data_intr chanNum eTPU Only disable_data_intr chanNum eTPU Only write_chan_cier chanNum isEnable TPU
134. dgement It is convenient to name each test run That is when MtDt is launched the command line parameter shown below applies a name the test run This name shows up in the log file This allows the particular test run that is causing any failures to be easily identified when perusing the log file 2 tn lt TestName gt Note that command line parameters do not handle spaces will To include spaces in the name enclose the parameter in quotes as shown below In the following example the name Angle Mode is specified tnAngle Mode File Location Considerations Although this discussion is equally applicable to the MtDt as a whole it is important to point out how MtDt locates files within the context of Regression Testing MtDt uses a project file relative approach to searching and finding almost all files This means that the user should generally locate the project files near the source code and script files within the directory structure Consider the following directory structure C BaseDir SubDirA Test Sim32Project C BaseDir SubDirB Test Cpu32Command To load the script command file Test Cpu32Command the following option could be used s SubDirB Test Cpu32Command By employing this project file relative approach the testing environment can be moved around without having to modify the tests and therefore the files names can be smaller and easier to use Note that this does NOT apply to the log file The log file is w
135. dr PWM2_CHAN PWM2_CHAN_ADDR In this example channel 3 s data will start at address 0x300 Note function variables and static local variables use this Each channel should be given its own In the Byte Craft eTPU C Compiler the amount of parameter RAM that needs to be allocated to 46 each channel for that eTPU function is determined as follows pragma write h define PWM_RAM ETPUram Pwm eTPU Channel Function Mode FM Script Command write_chan_mode ChanNum ModeVal This command writes channel ChanNum s to function mode ModeVal Note that this modifies the FM field of the CxSCR register This is a two bit field so valid values are 0 1 2 and 3 define PWM1_CHAN 17 write_chan_mode PWM1_CHAN 3 In this example channel 17 s function mode is set to 3 eTPU Event Vector Script Commands write_chan_entry_condition ChanNum Val This command writes channel ChanNum s event vector entry condition to Val Note that this writes the CxCR register s ETCS field A value of 0 designates the standard table and 1 designates alternate Note that each function has a set value and that this value MUST match that of the eTPU function to which the channel is set define UART_STANDARD_ENTRY_VAL 0 define PWM_ALTERNATE_ENTRY_VAL 1 write_chan_entry_condition UART1_CHAN UART_STANDARD_ENTRY_VAL write_chan_entry_condition CUART2_CHAN UART_STANDARD_ENTRY_VAL write_chan_entry_condition PWM1_CHAN PWM_ALTERNATE_ENTR
136. dulation Window Counter Timer Module 4 and 6 Windows CTM4 CTM6 Bus Interface and Clocks Window CTM4 CTM6 Free Running Counter Submodule Window CTM4 CTM6 Modulus Counter Submodule Window CTM4 Double Action Submodule Window CTM4 Pulse Width Modulation Submodule Window 2 CTM6 Single Action Submodule Window CTM6 Double Action Submodule Modes Window CTM6 Double Action Submodule Bits Window Miscellaneous Windows Real Time Clock Window Parallel Port I O Submodule Window TouCAN Windows TouCAN Main Window P TouCAN Buffers Window Queued Analog to Digital Converter Windows QADC Main Window QADC Ports Window a QADC Channels Window CPU32 Simulator Specific Windows The following window is available for CPU32 Simulator targets CPU32 Simulator Configuration Window CPU32 Simulator Busses Window CPU32 Simulator Interrupt Window Universal CPU32 Windows The following windows are available for both the CPU32 hardware and the CPU32 Simulator targets CPU32 Registers Window CPU32 Disassembly Dump Window CPU16 Simulator Windows The following windows are available for CPU16 Simulator targets CPU 16 Simulator Configuration Window CPU16 Register Window CPU16 Disassembly Dump Window 89 Source Code File Windows ia i TpuSim Source uart UC TpuSim Source toggle UC a cond hsr1 1 hsr6 6 Init TOGGLE ram diob lt TOGGLE_HI au ert tcri diob chan neg_tdl
137. e Addr 2866 ETB 65 TCRCLK Input Pin High Active Channel T 6 T 4 6 6 6 Address 67C6 Rtn FFFC ETPU Phase Not Supported Interrupts Microcode Global Exception clr Illegal Instruction clr Verification Continuous Behavior Off Behavior Failures 66660666 Script Failures 660606660 Versions ETPU 1 Size 12 K SCM 3 K PRAM Simulator 3 36 Build R Code ByteCraft COD BCLETPUC 6 91 7 987 Files Application C Mtdt Gui TESTFILES MtDt exe Project C Mtdt TestDataFiles ETpuCode AutoRunOregontETpu ETpuSimProject NtDt Build C Mtdt Gui TESTFILES BuildScripts zzz_1ETpuSim MtDtBuild Source Code CompilerTest cod Script IsrTestPrimary ETpuCommand Script Report IsrTestPrimary Report Script Startup No File Open Test Vector No File Open Build No File Open Master Behavior No File Open Semaphores Semaphore 6 Free Semaphore 1 Free s Semaphore 2 by eTpu1 Semaphore 3 Free The CPU frequency is displayed The eTPU executes at half of this CPU frequency in that a single eTPU instruction takes two CPU clocks to execute The CPU clocks shows the number of CPU clock ticks that have occurred since the last reset The latest thread in both steps opcode execution and NOPs and CPU clocks is displayed The execution unit activity level since reset is shown This is the total number of CPU clocks divided by the number in which the eTPU was either in a Time Slot Transition or in a thread The current
138. e and remainder amp 4 Bitwise AND OR EXCLUSIVE OR and INVERSE lt lt gt gt Bitwise shift left and shift right The following example makes use of simple expressions to specify the channel base define PARAMETER_RAM 0x100 define BYTES_PER_CHANNEL 16 define SPARK_CHANNEL_BASE PARAMETER_RAM BYTES_PER_CHANNEL 5 Write a 77 hexadecimal byte to address 150 hexadecimal U8 SPARK_CHANNEL_BASE 0x22 0x55 The normal C precedence rules can be overridden using brackets as follows write_chan_func 1 3 4 2 Sets channel 1 to function 11 write_chan_func 1 3 4 2 Sets channel 1 to function 14 Comments Legacy C and the new C style comments are supported as follows This is a comment set_tdl 3 This is a legacy C style comment This is also a comment This is the end of the multiple line comment set_tdl more comment 3 Decimal Hexadecimal and Floating Point Notation Decimal and Hexadecimal notation are interchangeable 29 357 Decimal Notation 0x200 Hexadecimal Notation In certain cases floating point notation is also supported 3 3e5 Floating Point String Notation The following is the accepted string notation STRING The characters between the first quote and the second quote are interpreted as a string File dat This denotes a string with eight characters and termination character as follows F i l e d a
139. e command line Had this been a test running in a multiple target environment the target name would have to be specified along with each script file echo off path path C Program Files ASH WARE TPU Simulator TpuSinulator exe pTest1 TpuSimProject sTest1 TpuCommand AutoRun IAcceptLicense if SERRORLEVEL NEQ 0 goto errors TpuSimulator exe pTest2 TpuSimProject sTest2 TpuCommand AutoRun IAcceptLicense if MERRORLEVEL NEQ 0 goto errors echo 2 7K k k akk aak k a ak a ak a a a ak k 2 2 ak k 2 k ak k ak k a ak 2 ak ae ak 2 k ak ak 9K 2K 2K 2 2K 2k echo SUCCESS ALL TESTS PASS echo 7H G a 2 k k k kk k k kk k k 2 k ak 2 ak ee 2K he ak ak ae 2 ee 2 afe ee 2 2 oe 2K 2 he 2 2K 2k goto end Crrors echo 7 7 7 k k a akk ak a ak k ak 9 ak a kak k a ak k ae ak ak ak ae 2 k 2 a KK a ak 2K 2K 2K 2 2K K 2K 2 2 echo YIKES WE GOT ERRORS echo OKK K K K K K EK K K K K K KOK K K KK K K K K K K K K KK K K K K K K K KK K K K K K K K K K end If the above test were named TestAll bat then the test would be run by opening a DOS shell and typing the following command C TestDir TestAll Cumulative Logged Regression Testing Cumulative logged regression testing supports the ability to run an entire test suite without user intervention even if one or more of the tests fail This capability overcomes the problem in which a failure halts the entire test suite until acknowledged by the user Using this capability the al
140. e new to the MtDt version 3 20 Testing automation via command line capabilities Verification and modification of symbolic data 16 Superior Logic Analyzer Window including precise event timing measurement Improved simulation speed by between 2x and 2 6x depending on loading conditions Superior tracing including pin transitions parameter RAM I O and capture match events saved to the trace buffer Trace data can be saved to a file The application wide font can be specified The following is a list of the features that are new to the MtDt version 3 10 Replaced the set_cpu_frequency command with the set_clk_period script command Additional script commands New call stack window Improved local variables window Improved trace window Additional 683xx Hardware Debugger support for 68331 68336 68338 and 68376 New TPU Standard Mask Simulator supports 683xx and MPC5xx New local variable options dialog box Additional IDE options Additional operation status windows The following is a list of the features that are new to the MtDt version 3 00 Source code search rules Enhanced script files Definitions using define declaration Enumerated types Simple expressions Improved assignment operators Breakpoints Complete grammar check at load time Editable register style windows Integrated timers Watch local variable and memory dump windows Workshops The following is a list of
141. ectives R Enumerated data types Integer data types Referenced memory Assignment operators J Operators and expressions Comments 2 Numeric Notation z String notation 25 Script Commands Format The command is case insensitive and in general has the following format command data1 data2 data3 The contents within the parenthesis datal data2 and data3 are command parameters The actual number of such data parameters varies with each particular command Data parameters may be integers floating point numbers or strings Integers are specified using either hexadecimal or decimal notation Floating point parameters are specified using floating point notation and strings are specified using string notation Hexadecimal and decimal are fully interchangeable Multiple Target Scripts In a multiple target environment each target has its own script commands file and each of these files runs independently As such the scripts in each of these files acts by default on its own target For example a script that modifies memory will do so in the memory space of the target in which that script commands file is executing But there are situations in which it is convenient to be able to have a script command within a single script commands file act on the various other targets in the system besides the one in which that script commands file is executing lt TargetName gt lt ScriptCommand gt The specific target for which
142. ed via the Files menu by selecting the Vector Open submenu It is only available when a TPU simulation target is active This dialog box specifies a test vector file to be loaded The entire file is loaded at once Loading additional files causes existing test vectors to be removed This dialog box allows full specification of drive directory and filename The default filename is VECTORS Vector and the default search is Vector Project Open and Project Save As Dialog Boxes The Project Open and Project Save As dialog boxes are opened from the Files menu by selecting the Project Open submenu or the Project Save submenu From the Project Open dialog box a MtDt project filename is specified MtDt loads a new configuration from this file From the Project Save As dialog box a MtDt project filename is specified The current configuration is saved to this file Run MtDt Build Script Dialog Box The Run MtDt Build Script dialog box specifies which MtDt build script is to be run Running a MtDt build script has a large impact Before the new script is run open windows are closed and all target information is deleted from within MtDt This effectively erases most of the Project information so it is usually best to create a new project before opening a new MtDt build script 143 Save Behavior Verification Dialog Box The Behavior Verification dialog box is opened from the Files menu by selecting the Behavior Verification Save submenu Th
143. en selected The line is automatically displayed and highlighted yellow as shown below 98 Pa Source pta uc z ol x neg_trans6 if Match then goto accum_time_pta flush Can only be Low Pulse au chan_reg chan_reg It s O K to update PSL here since p chan neg_tdl there are no more Match states U6 3 R Soj a SCART 2636363696969 2696 96 9696 9 HEHE IE JE JE JE JE JE JE JE JE HEH HE JE JE JE HH HEH HEHE HHH HHH HEE HE HE JE JE JE JE JE FE JE E JE IE JE FE JE JE JE JE JE JE JE JE E JE HE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JE JEJE JEJE JEJE JEJEJE FE Extra code to check for short pulses during flag8 0 states in High and Low Pulse measurement functions HEHEHE HEE HEHEHE HEHE HEHE HEHE HEHEHE HE JE JE JE HEHE JE JE HEHE HE HE JE JE HE JE HE HEHE JE JE HEHE JE JE HEHE JE E JE JE JE JE JE HEHE JE JE HEHE HEHE HEHEHE Do aop al al ay Complex Breakpoint Window eTpui Complex Breakpoints ComplexBreakpoint Cr Output Pin UART_XMT Set Channel Flag UART Sa ComplexBreakpoint Program Counter UART_XMT UART_WRAP UART_RCY addr 0x100 Complex breakpoints are added removed and modified from within the complex breakpoint window Complex breakpoints support the ability to halt the target on the occurrence of one or more combinations of conditions Each complex breakpoint operates independently of all other complex breakpoin
144. entirely on the particular target and how it is specified in the build script file For instance a simulated TPU target makes use of three address spaces Code Data and Pins By treating its I O pins as shared memory the simulated TPU exposes its pins to other targets This allows for instance a simulated engine model to read and modify the TPU s pins With the nearly universal acceptance of the superiority of a single unified large address space why does MtDt still support non unified memory space architecture The answer is twofold First the MtDt supports older but still popular architectures such as CPU16 in which a split code data and space might actually be employed Second the multiple address space model provides the required mechanism for support of advanced simulation features These mechanisms do not necessarily exist in the actual hardware For example an engine modeling CPU might be set up to query and modify TPU channel I O pins To support this the TPU pins have been exposed in a purely theoretical PINS address space MtDt can be configured so that a read or write in the engine modeling CPU s DATA_SPACE occurs in the TPU s PINS space thus allowing the engine modeling CPU to react to and drive the TPU s pins This mechanism does not have a hardware corollary but it provides the powerful capability of simulating the full system In many cases a uniform address model is desirable This is achieved by mapping all address spaces to
145. enu or the Reset and Go submenu is selected Reread Primary Script Commands File Selecting this option causes the primary script commands file to be reread every time MtDt resets the targets Rewrite Code Image Selecting this option causes a cached version of the executable image to be re written every time MtDt resets the targets The executable image file is not reread instead a cached version of the executable image is used Since a cached version is used source code files are also not changed Note that this option should be selected with care as the executable image in the target should generally not be modified during target execution and reloading every reset could mask such a bug Reread Test Vector File eTPU and TPU Targets Only Selecting this option causes the test vector file to be reread every time MtDt resets the targets PRAM Variable Memory eTPU and TPU Targets Only This option specifies whether the PRAM memory is not changed written to all zeroes or is randomized on reset TCR1 and TCR2 Counters eTPU and TPU Targets Only This option specifies whether the TCR1 and TCR2 counters are not changed written to zero or are randomized on reset Help This accesses this help menu Cancel This discards and changes and exits the Reset Options dialog box OK This saves any changes and exits the Reset Options dialog box Logic Analyzer Options Dialog Box The Logic Analyzer Options Dialog box defines the
146. er follower with TPU channel 5 as the input and the TCR2 pin as the output Build Script Commands instantiate_target enum TARGET_TYPE TargetName instantiate_target_exl enum TARGET_TYPE enum_TARGET_SUB_TYPE TargetName These commands instantiate a target enum TARGET_TYPE and assigns it the name TargetName Subsequent references to this target use the target name specified in this command The second extended version of this command supports sub targets instantiate_target_ex1 TPU_SIM TPU_MASK MyTpu instantate_target CPU32_SIM MyCpu This example instantiates two simulation models a TPU and a CPU32 The name MyTpu is assigned to the TPU and the name MyCpu is assigned to the CPU32 A special standard mask style of TPU is generated that will load only the Standard Mask TPU microcode Subsequent build script commands use these names when referring to these targets These names are also referenced in a variety of other places such as in workshops and the menu system add_mem_bl ock TargetName StartAddress StopAddress BlockName enum ADDR_SPACE This command adds a memory block to a range of simulated memory The memory appears between stopAddress and startAddress in the memory space ADDR_SPACE The name BlockName is assigned to this block and is used by other script commands when referencing this block The block name must be unique within its target but other targets can have a block with this same block n
147. erify_reg4 REG_ZK 0x12 verify_reg16 REG_PC 0x5557 In the example above a script file which is acting on a CPU 16 target verifies that the index register Z s address extension register is equal to 12 hexadecimal and verifies that the program counter is equal to 5557 hexadecimal If either of these conditions fails to verify a script failure message is generated and the target s script failure count is incremented Write Symbol Value Script Command Write symbol value script commands provide the mechanism for writing the values of symbolic data for both variables as well as strings Symbols are variables and strings defined within the user s 34 code A key concept is that of symbol scope A variable defined within a particular function goes out of scope if that function is not being executed To get around this a script command can be set to execute when the function becomes active using the at_code_tag script command See the Timing Script Commands section for a description write_val symbolExprS tring exprString write_str symbolExprString valueString The expression string ExprString can be a numerical constant or a simple symbolic expression Constants can be supplied as decimal signed integers unsigned hexadecimal numbers prepended with Ox or floating point numbers A symbolic expression can be just a local global symbol or a simple expression such as V de reference V constant V member or V gt member where
148. eriod script command described in the Clock Control Script Command section A message is generated when this command is used This message can be disabled from the Message Options Dialog Box write_psck Val This command writes the prescaler clock source bit Only 0 and 1 are allowed values A 1 selects the system clock divided by 4 A zero selects the system clock divided by 32 write_div2 Val This is available in TPU2 mode only Writes the divide by 2 control bit Only 0 and 1 are allowed values A 1 selects the system clock divided by 2 and bypasses the prescaler A 0 selects the clock source specified in the PSCK bit write_tcr1_prescaler Val This command writes the TCR1 prescaler Valid Val values are 0 1 2 or 3 A O causes a division by 1 no prescaler A 1 causes a division by 2 A two causes a division by 4 A 3 causes a division by 8 write_psck 1 write_div2 0 Available in TPU2 mode only write_tcr1_prescaler 2 The two commands in this example set the TCR1 counter to increment at 1 0486 MHz assuming the CPU clock is set to 16 778 MHz write_t2cg Val This command writes the TCR2 configuration bit Valid Val values are zero and one write_t2csl Val This is available in TPU2 mode only It writes the TCR2 counter clock source edge control bit Only 0 and 1 are allowed values This control bit along with the T2CG control bit specify the source for the TCR2 counter With both control bits at 0 the TCR2 c
149. ert is logged to a file rather than being displayed in a dialog box Test completion occurs when the exit script command is encountered At this time a PASS or FAIL indicator is appended to the end of the log file Because it is appended to the end of the log file the normal usage would be do delete the log file prior to beginning the test suite Then upon 81 completion of a test run the log file grows At the end of the test suite the log file can be perused and any failing tests are quickly identified Note that only certain types of failures bypass the normal message dialog box For instance if the failure log file itself cannot be written then this generates a failure message in a dialog box which must be manually acknowledged This capability is envoked using a combination of two command line options shown below cs LFSMyLogFile log Quite The first command L5MyLogFile log specifies that message are appended to the end of a log file named MyLogFile log The second command Quite specifies that the dialog boxes that normally carry test errors or warnings are not displayed Note that this command only works in conjunction with AutoRun TAcceptLicense and LF5 lt LogFileName log gt If any of these options is not selected then this Quite command is ignored Note also that if the user halts the simulation then this option is disabled such that messages shown in dialog boxes will require manual acknowle
150. ervice Latch LSL Z The disable match bit from the entry point This bit controls whether a match is inhibited during channel servicing The active counter for capture and match TCR1 or TCR2 The pin direction input or output The current pin state high or low The PAC setting which determines the pin action on a match if the pin is an output or the transition to be detected if the pin is an input 2 The effective match condition greater than or equal to or greater than Since this field applies to TPU2 and TPU3 only when in TPU1 mode this field is not displayed Unlike previous versions of this software the active channel is not specified directly from the menu when the window is opened Instead the active channel is specified from within the window by accessing the popup menu To do this right click the mouse and select the desired channel number from the menu This makes it easier to view the various channel settings without having to have lots of channel windows open During channel servicing the active channel can be changed by the microcode The microcode changes the active channel by writing to the CHAN register found in the TPU Execution Unit window When the active channel is changed by the microcode the effective active channel is somewhat murky Some channel parameters migrate after a number of instructions to the new channel while other parameters remain attached to the channel that originally caused the c
151. es It can execute microcode out of its internal ROM or it may execute custom microcode out of its internal RAM In order to execute custom microcode the microcontroller s operational software must first copy the microcode into its internal RAM and then configure the TPU to execute out of RAM Support for TPU1 MtDt supports the TPU1 This is the original TPU Support for TPU2 MtDt supports the TPU2 The following is a list of new and supported features of the TPU2 not available in TPU1 g Entry table bank ETBANK Code bank Full parameter RAM Load zero using a RAM sub instruction Additional TCR2 and TCR1 clock options z Flag2 set clear and conditional execution 3 Branch on current pin state Negation of MRL and TDL using TBS sub instruction Match on equal The entry bank is controlled in the TPU simulation engine using a write_entry_bank script command as described in the TPU Bank and Mode Control Script Commands section The current state ofthis field is displayed in the microsequencer window The code bank is set during a time slot transition using bits 10 and 9 of the entry table The user 167 modifies this directly within the source microcode The current state of this field is displayed in the microsequencer window The TPU1 does not implement parameters six and seven of the parameter RAM for channels zero through 13 The TPU2 supports a full complement of parameter RAM for all channels The TPU2
152. etected TCRCLK Last Tooth Open a physical pin transition can be detected The Module Configuration Registers MCR Global Time Base Enable GTBE field indicates if the time bases in the eTPU s are enabled The Time Base Configuration Register s TBCR TCRICTL and TCR2CTL fields displays the configuration of the TCR1 and TCR2 counters The TCR1P and TCR2P fields show both the field value and the actual divisor of the prescaler The TCRF displays the filtering options though these are not simulated by the eTPU Simulation engine The Angle Mode AM bit indicates if angle mode is enabled The Tooth Program Register TPR is only used in angle mode This register may be written only by the eTPU code The LAST bit indicates that angle mode should be reset on the next tooth The 102 MISSCNT field indicates how many incoming teeth are expected to be missing such that the angle mode PLL will continue to count synthesized teeth and not wait for incoming physical tooth signals The Insert Physical tooth IPH field allows the eTPU code to tell the angle mode hardware to proceed as if an incoming physical tooth had been detected The HOLD field forces the angle mode logic to halt as if more incoming physical teeth had been detected than were expected The TICKS field specifies the number of angle ticks TCR2 increments that are in each physical tooth As such this is effectively the PLL multiplier for the difference between the frequency of the i
153. ew to the transition data at the center of the display Zoom Out P Selecting the Zoom Out button widens the view so that more transition data is displayed Zoom Back ZS Selecting the Zoom Back button restores the previous view The last five views are always saved MtDt stores the view information in a circular buffer so that if the Zoom Back button is selected five times the original view is restored Note that only the view and not the cursors are affected This allows the user to shift views while retaining the timing information associated with the vertical cursors 140 Zoom To Cursors E mm Selecting the Zoom To Cursors button causes the view to display the transition data between the left and right cursors Setup Set Selecting the Setup button causes the Logic Analyzer Options dialog box to be opened This dialog box accesses various setup options as described in the Logic Analyzer Options Dialog Box section Help BE Selecting the Help button accesses the Logic Analyzer section of the on line help Timing Display Below the Logic Analyzer s horizontal scroll bar are two fields that display the time or CPU clock counts corresponding to the left hand and right hand sides of the wave form display panel The display region can be modified using the horizontal scroller located below the wave form view panel It can also be modified using the buttons described in the Button Controls section found earlier in the description of
154. f calculations such as TPU frequency QSM frequency etc are based on this assumption Unfortunately the 683xx Hardware Debugger has no way of verifying that this is in fact the correct crystal frequency so the following script command allows the user to override the default set_crystal_frequency cylesPerSecond This code sets the assumed external clock frequency to cyclesPerSecond Note that the cyclesPerSecond must be a decimal or hexadecimal number A floating point number will not work set_crystal_frequency 34000 The code in this example overrides the default external clock crystal value and sets it instead to 34 KHz Timing Script Commands at_code_tag TagString This command prevents subsequent commands from executing until the target hits the sourcecode that contains the string lt TagString gt Note that all source code files are searched and that the string should be unique so that it is found at just one location for otherwise the command will fail at_code_tag MyTest1 verify_val failFlag 0 32 In the example above the target executes until it gets to the point in the source code that contains the text MyTest1 and then verifies that the variable named failFlag is equal to zero It is important to note that the variable could be local to the function that contains the tag string such that it may be only briefly in scope The only scoping requirement is that the variable is valid right
155. fer size is changed such that it can hold 500K pin transitions This script command should only be executed at time zero Note that resizing the pin transition buffer can have serious affects on performance For instance it can cause along delay when the simulator is reset It can also significantly slow down the logic analyzer redraw rate such that the simulation speed is bound by the redraw rate Simulation speed reductions can be obviated by hiding or minimizing the logic analyzer while the simulator runs such that redraws are not required thereby improving simulation speed The effective pin transition buffer size can also be increased in other ways This is discussed in the the Logic Analyzer Options Dialog Box section 4 Thread Script Commands The simulator stores worst case latency information for each channel This is very useful for optimizing system performance But in some applications the initialization code which generally does not contribute to worst case latency experiences the worst case thread length In this case it is best to ignore the initialization threads when considering the worst case thread length for a function This command ignoring the initialization threads Initialize the channels write_chan_hsrr RCV_15_A ETPU_ARINC_RX_INIT write_chan_hsrr RCV_15_B ETPU_ARINC_RX_ INIT Wait for initialization to complete then reset the worst case thread indices wait_time 100 clear_worst_case_thre
156. ferences between the User Manual and the On line Help program are listed below The On line Help program is an electronic file The Windows help program uses this file The User Manual is a book The On line Help program contains special codes that allow the user to dectronically browse through and jump from topic to topic These codes are stripped from the User Manual The User Manual has page numbers while the On line Help program does not The User Manual contains a Table of Contents while the On line Help program does not The User Manual contains this Foreword while the On line Help does not There are both advantages and disadvantages of the similarities between the User Manual and the On line Help program The most important advantage is that by becoming familiar with either medium the user automatically becomes familiar with both media The primary disadvantage is that the constraints imposed on the On line Help program are also imposed on the User Manual and visa versa For instance the On line Help program imposes the constraint that the different browse sequences may not be intermixed This forces the organization of the manual to be by browse sequence rather than by subject although the latter would be preferable 10 ACKNOWLEDGEMENTS The story of ASH WARE must necessarily begin with the TPU so thank you Vernon for your wonderful invention and Celso amp Co for bringing it to the next level The last few yea
157. for the unused address spaces add_non_mem_block TpuSim 0x0 Oxffffffff B4 TPU_UNUSED_SPACE In this example the TPU s code data and pins address spaces are filled with the memory devices required for proper operation Unused space above and below the simulated devices is filled in with blank blocks This is required as all space must be filled in even unused space must be provided with memory block s Memory Block Size Each memory block has a specific size The size is equal to the stop address minus the start address plus one A common error is to overlap by one byte the end of one device with the start of the next device MtDt cannot support multiple devices occupying the same address in the same address space so this causes an error One method for avoiding this error is to cascade define directives and thereby ensure that contiguous devices form the proper zero byte seam define FLASH_SIZE 0x10000 64K FLASH device define RAM_SIZE 0x8000 32K RAM device define FLASH_START 0 define FLASH_END FLASH_START FLASH_SIZE 1 define RAM_START FLASH_END 1 define RAM_END RAM_START RAM SIZE 1 define BLANK_START RAM_END 1 define BLANK_END FFFFFFFF instantiate_target SIM32 MyCpu add_mem_block MyCpu FLASH_START FLASH_END Flash ALL_SPACES add_mem_block MyCpu RAM_START RAM_END RAM ALL_SPACES add_non_mem_block MyCpu BLANK_START BLANK_END Empty ALL_SPACES In this exa
158. fore executing The simulation runs until the selected time is reached The second mouse function is to move the left and right cursors These cursors are displayed as blue and green vertical lines The user may move either cursor using the mouse The times or CPU clocks associated with both cursors as well as the delta between cursors are displayed in the cursor time indicators Note that the left and right cursors can also be moved using the left and right arrow keys on your LOGIC_ANALYZER_CURSOR_INDICATORS 138 keyboard This causes the cursors to snap to edges on the active waveform Cursor display and movement follow these rules Cursors may be located beyond the edge of the wave form display panel If the left cursor gets beyond the right display edge it is automatically moved back into the display If the right cursor gets beyond the left display edge it is automatically moved back into the display P Cursors outside the display retain their timing association 7 To allow the user to pick up a cursor that is not in the display the cursor is considered to be just outside the display edge for the drag and drop operation The Vertical Yellow Context Time Cursor The vertical yellow context cursor is the time of some referenced event occurring elsewhere in the IDE For instance open a trace window and scroll backward through the trace data The vertical yellow context cursor will show the time at which the trace
159. g TPU simulation targets with complex test vectors While a script commands file functionally represents the CPU interface a test vector file represents the external interface And whereas a script commands file provides a broad range of functions the test vector file provides the narrow but powerful capability of driving nodes to high or low states and assigning application specific names to nodes and node groups A second method of exercising the TPU simulation target is to create a model of the external system using a dedicated modeling CPU target Using this method the user need not necessarily use test vector files Sharing Memory between Multiple Targets The key ingredient to the full system simulation capability is shared memory Targets expose their address spaces to other targets Two levels of address space exposure are possible extrinsic and intrinsic Extrinsic exposure is the most powerful but is not supported by all targets Extrinsically mapped address spaces allow memory accesses to that section of the memory map to occur in a target different from the one in which the access originated For example a simulated TPU might perform a write to data memory The section of data memory could be extrinsically mapped to a CPU32 across a BDM port The access would be transferred across the BDM port and would actually occur in the CPU32 s address space Intrinsic exposure is less powerful but is supported by all targets A target that
160. g box Workshop This opens the Workshops Options dialog box Messages This opens the Message Options dialog box Reset This opens the Reset Options dialog box It specifies the actions taken when MtDt is reset from the Reset menu by selection of the Reset submenu Logic Analyzer This opens the Logic Analyzer Options dialog box Note that a Logic Analyzer window must be active for this submenu item to be available BDM This opens the BDM Options dialog box Note that a 683xx Hardware Debugger target must be active for this submenu item to be available Memory Tool This opens the Memory Tool dialog box Note that if a Memory Dump Window is selected when this dialog box is opened settings from the window are automatically loaded into the dialog box This supports a variety of capabilities including dumping memory to files searching for patterns in memory and filling memory Memory This lists a variety of settings available for a Memory Dump Window Note that this type of window must be selected for these options to be available Toggle Mixed Assembly This toggles the visibility of assembly within Source Code File windows Note that this type of window must be selected for these options to be available 161 Verify Recorded Behavior This verifies the recorded behavior against the currently active master behavior verification file See the Pin Transition Behavior Verification section for a description of this capability En
161. g the exit script command as described in the System Commands section This command causes the application s termination error level to be set to be non zero if any verification tests failed or zero if all the tests passed The overall strategy in ensuring that a zero error level truly represents that all tests have run error free and to completion is to treat any unusual situation as a failure Specifically a failing non zero termination code will result unless the following set of conditions have been met No verification tests are allowed to fail in any target 80 All targets must have executed all their script commands MtDt must terminate through the exit script command Abnormal termination such as detection of a fatal internal diagnostic error results in a non zero error level If the user closes the application manually for instance by selecting close from the system menu then the error level is set to non zero Regression Test Example The keys to successful Regression Testing is the ability to launch MtDt multiple times within a batch file that runs in a DOS command line shell and to verify within this batch file that the tests that were automatically run had no errors These multiple launches of MtDt and the tests contained therein form a test suite The following is a batch file used to launch the TPU Simulator multiple times Note that there is only a single target such that no target must be specified on th
162. g trace buffer has overflowed Generating Parseable Files Parseable files can be generated only by using the script commands described in the File Script Commands section To ensure generation of deterministic parseable trace files these files can be generated only if the selected trace events are enabled within MtDt and the trace buffer has not overflowed when generating a trace file from the buffer For large trace files it is best to use the streaming capability thereby avoiding possible trace buffer overflow issues Parsing the Trace File All post processing on the trace files should be done on files generated using the parseable option Although the file format is intended to be self explanatory it is purposely left undocumented to retain flexibility for future enhancements Instead it is recommended that those wishing to post process the trace files use the free trace file parse source code available from ASH WARE The public methods in the TraceParser class are fully documented and will remain stable for all future releases The trace file parser s source code is released to the public domain under the GNU licensing agreement You should familiarize yourself with the restrictions imposed by the GNU license before using the source code ASH WARE intends to provide as a service the generation of parser file post processing capabilities For instance TPU latency calculations such as minimum maximum average and standard devi
163. gate clock input pin In the example shown below the name UART is assigned to the TPU s channel 5 I O pin define UART CH5 Thread Activity Nodes Thread activity can be extremely useful in both understanding and debugging eTPU and TPU functions The simulator provides the following thread activity nodes ThreadsGroupA ThreadsGroupB ThreadsGroupC ThreadsGroupD ThreadsGroupE ThreadsGroupF ThreadsGroupG ThreadsGroupH These nodes can be renamed In the following example the ThreadsGroupB node is assigned the name A429RcvThreads Note that the primary purpose of renaming these nodes is to provide a more intuitive picture in the logic analyzer window as shown below See the Logic Analyzer Options Dialog section for more information on how to specify groups for monitoring of TPU and eTPU thread activity node RcvThreads ThreadsGroupB eTpu1 Logic Analyzer T aweserot af a im SSI 1 846 820 1 aS Mouse 1 959 751 4 nS Data Start 000 000 0 nS Context 000 000 0 nS Current Time 3 382 000 0 nS Set Left Cursor 1 848 531 2 nS Delta Cursor 109 509 2 aS Right Cursor 1 958 040 3 nS Test Vector Group Command group lt GROUP_NAME gt lt NODE 1 gt NODE 2 NODE N The group command assigns multiple nodes NODEs to a group name GROUP_NAME These nodes can be referred to later by this group name The group name may contain any ASCII printable text These group names are case insensitive Up
164. gger Target 112 52 MyBdm32 Configuration iof x Files Project MtDt Build C TESTFILES BuildScripts 1Bdm32 MtDtBuild Source Code main e68 Script No File Open Script Report No File Open Script Startup Startup Cpu32Command Build No File Open Verification Script Failures 66666066 Files The name of the project file is displayed See the Project Sessions chapter for a detailed explanation of this capability The name of the MtDt build script file is displayed See the Full System Simulation chapter and the MtDt Build Script Commands File section for detailed explanations of the available capabilities and format of this file The names of the open source code executable image primary script primary script report and startup script files are displayed These files are listed relative to the path of the open project file The auto build file name is displayed The auto build file allows direct building of the executable image from within MtDt and is covered in the Auto Build Batch File Options Dialog Box section Verification The count of the number of user defined verification tests that have failed since the last MtDt reset is displayed User defined tests are part of script commands files See the Script Commands Groupings section for a description of the various script commands that support user defined tests SIM Main Window Availability 683xx Hardware Debugger 113 32 MyBdm32 SIM Main ioj x
165. gt PQA 6 ANG 3C8 7266 F266 4 621F PAUSE no 2 QCLK s 002 861 6 1F gt D BOZTCME sore BECO 3ECO 5 B2FF PAUSE no 16 QCLK s 622 888 2 3F gt PQA 6 ANG Q3EF 7BCG6 FBCO 6 2FF PAUSE no 16 QCLK s 622 888 2 3F gt PQA 6 ANG O3BE 6F86 EFS86 7 62D1 PAUSE no 16 QCLK s 622 888 2 11 gt PQA 6 ANG 3EB 7ACG FACS 8 B1FF YES 416 QCLK s 022 888 2 3F gt PQA 6 ANG O3FA 7E80 FE8O 9 Q 3FF PAUSE YES 16 QCLK s 622 888 2 3F gt PQA 6 ANG 61F5 FD40 7D46 A O3FF PAUSE YES 16 QCLK s 9022 888 2 3F gt PQA 6 ANO Q 06F 9BCG 1BC8 B O3D8 PAUSE YES 16 QCLK s 622 888 2 18 gt PQA 6 ANG 03DE 7786 F786 H 9097F no 4 QCLK S 665 722 6 3F gt PQA 6 ANG GOFF BFCG 3FCO D 3BE PAUSE YES 8 QCLK S 611 444 1 3E gt PQA 6 ANG Q3FF 7FCG FFCO E O 3FE PAUSE YES 16 QCLK s 622 888 2 3E gt PQA 6 ANO O3FF 7FCG FFCO F 8915F YES 4 QCLK S 665 722 6 1F gt PQA 6 ANG 63D9 7646 F646 10 B1BE YES 8 QCLK S 611 444 1 3E gt PQA 6 ANG GOFF BFCG 3FC8 11 OO5F no 4 QCLK S 605 722 6 1F gt PQA 6 ANG O3FF 7FCG FFCO 12 e18 YES 416 QCLK s 022 888 2 18 gt PQA 6 ANG Q3FF 7FCO FFCO 13 3DD PAUSE YES 16 QCLK s 022 888 2 1D gt PQA 6 ANG 03D9 7646 F646 14 O 3EA PAUSE YES 16 QCLK s 622 888 2 2A gt PQA 6 ANO GOFF BFCG 3FCO 15 QOFE no 16 QCLK s 622 888 2 3E gt PQA 6 ANG Q3FF 7FCG FFCO 16 QOEF no 16 QCLK s 622 888 2 2F gt PQA 6 ANG Q3FF 7FCG FFCO 17 BIFF YES 16 QCLK s 022 888 2 3F gt PQA 6 ANG 3D9 7646 F646 18 OOFF no 16 QCLK s 622 888 2 3F gt PQA 6 ANG GOFF BFCG 3FC
166. hannel 111 servicing How does MtDt handle this situation since the active channel version of the channel window is intended to show channel information of the active channel This is answered in the following paragraph The active channel version of the channel window shows the channel information corresponding to the active parameters For instance the effective flag changes from the old channel to the new channel two microcycles after the CHAN register is changed MtDt also switches the displayed flag two microcycles later In this way the user always views the affective channel TPU Parameter RAM Window Availability TPU Simulation Target 2030 7866 6666 6666 6666 662C aj 6631 222C 2041 4C4C 5F53 5641 S3B6A 7365 745F 626C 6F63 6B5F 6F63 6B28 2248 6F73 7431 3622 5055 5F44 6174 6122 2026 414C 6661 61B4 666C 6668 6666 166D 0609F 6266 6366 3636 293B GA73 6574 SF62 6691 4299 6166 6466 4699 6C6F 6462 66066 ba ot O T OE O T oEoOnmBDoe The parameter RAM is accessible by both the CPU and the TPU It typically is used to pass information between the CPU and TPU and is used by the TPU for scratch and storage For instance the CPU might store the number of signal edges the TPU should measure in one parameter RAM location The TPU would then keep a running count of the current number of edges measured in another parameter RAM location MtDt displays all existing RAM parameters in this window The window is arranged in r
167. havior verification file Script Verification Failure Script verification failure messages are generated when a user defined script verification test fails Bad at_time Script Command Bad at_time script commands specify when a particular script command is to be executed A message appears when this command specifies a time earlier than the current time Obsolete set_cpu_frequency Script Command The set_cpu_frequency script command is being deprecated and users should switch to the set_period script command to achieve this functionality The problem with the set_cpu_frequency command is that the simulation engine now calculates all times in periods rather than frequency This command requires an inversion which can generate extremely small error and this error over many billions of simulation cycles can become significant Consider a two targets one running half the frequency of the other If one clock is 333 MHz and the other is 666 MHz after the inversion the resulting clock periods may not be exactly double anymore TPU Messages An Instruction Accessed Unimplemented Parameter RAM The message that reports an access of un implemented parameter RAM locations may be disabled Some users have taken advantage of the un documented feature that accesses to these un implemented parameter RAM locations return zero Taking advantage of this un documented feature is dangerous because Freescale might choose to implement these locations such
168. he ROM Signature High Register RSIGHI the ROM Signature Low Register RSIGLO and the ROM Bootstrap Words 0 through 3 Registers ROMBSO ROMBS1 ROMBS2 and ROMBS3 Standby RAM Submodule Window 68336 68376 Availability 683xx Hardware Debugger UTI cx RAMMCR 6866 STOP F F Standby RAM SRAM is RLCK B B SRAM base address registers are locked RASP 9 8 SRAM is accessible at the unrestricted program and data priviledge level RAMBAH 6656 AD HI 7 86 l F C RAMBAL 2666 AD LO Base address is 606562666 The Standby RAM Submodule window 68336 68376 displays the RAM Module Configuration Register RAMMCR the RAM Array Base Address High Register RAMBAH and the RAM 118 Array Base Address Low Register RAMBAL Static RAM Submodule Window 68338 Availability 683xx Hardware Debugger 32 MySim32 Static RAM Submodule 1S Oj xi FFF500 6666 OOOO 6666 660668 6686 HOHO 000G 000G FFF516 1111 BEET 9000 6666 aooo 6666 oooo agoa FFF526 6668 6666 66660 HOOG 6666 6666 000G 000G FFF536 6666 6666 6666 66066 6686 HOHO HOOG 000G The Static RAM Submodule Window 68338 consists of 16 contiguous 16 bit words of RAM TPU Emulation RAM Window 68332 68336 68376 Availability 683xx Hardware Debugger 32 MyBdm32 Standby RAM x TRAMMCR GRE STOP F F TPURAM Module is operating normally RASP 8 8 TPURAM array is accessible at the Supu priviledge level TRAMBAR 6661 ADDR F 3 TPURAM array b
169. he simulation engine The input detection and output action fields show how the IPACs and OPACs have been configured The Predefined Channel Mode PDCM is shown Each channel has two flags and these are shown Each channel can have its own private variables within the Channel Function Frame and the Channel Parameter Base Address CPBA of the channel within this frame is shown The channel s bandwidth is shown Bandwidth is defined as the number of clocks in which either a thread or a Time Slot Transition TST for this channel was active divided by the total number of 104 clocks since the last reset Additionally the number of threads and the number of steps instruction or NOPs is displayed The longest thread in both steps instructions plus NOPs plus the longest thread time is displayed Click on the longest thread address to display this location in the source code window and to show this time in the Logic Analyzer window eTPU Scheduler Window eTpul Scheduler 10 x 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 18 F EDCBA9 8 7 65 43 21 86 Prty MM HI HI HI HIHI HI HI HI HI HI HI HI HI HI HI HI HI HI HIHI Srl 6 6666 6 66 A 6 6 6 8 6 66666 66 868 6 6 661 86 86 Sgl 6 6 6 6 6 6 6 6 8 6 6 6 8 6 6 6 6 6 6 6 SB 6 6 6 6 6 6 6 86 HSRR 6 6 6 6 6 6 6 6 6 6 6 8 6 6 6 6 6 6 6 86 6 6 6 6 6 6 6 86 LSR 6 6 6 6 6 6 6 86 8 6 6 6 8 6 6 6 6 6 6 6 86 6 6 6 6 6 6 6 86 M TSR 6 6 6 6 6 6 A 6 6 6 6 8 6 6 6 6 6
170. he two display options Target Clocks Display See the above description from the time display Channel Group Options Dialog Box The Channel Group Options Dialog box is used to select groups of one or more channels It is accessed in different locations for different purposes This dialog box is accessed from the Logic Analyzer Options Dialog box to specify groups for monitoring of eTPU thread activity Note that thread group activity is displayed as a waveform in the Logic Analyzer This dialog box also is used by the Complex Breakpoint Conditional Dialog to select which channels a complex breakpoint conditional acts upon Complex Breakpoint Conditional Dialog Box The complex breakpoint conditional dialog box allows the user to add conditionals to complex breakpoints Each complex breakpoint must contain one or more conditionals This dialog box is accessed from the complex breakpoints window 151 Trace Options Dialog Box Instruction Execution Selecting this option causes each instruction execution to be logged to the trace buffer Instruction Boundary Selecting this option causes each instruction boundary to be logged in the trace buffer While an instruction boundary contains no useful information the resulting dividing line makes the trace window easier to read Memory Read Selecting this option causes each memory read to be logged to the trace buffer Memory Write Selecting this option causes each memory write
171. hese access combinations are supported the test will fail if this is not a valid assumption test_byte_order address enum ADDR_SPACE numlterations This command runs the byte order RAM test at address lt address gt in the address space ADDR_SPACE for the number of iterations specified by numlterations It verifies the byte order of the target processor This was developed to verify proper functionality of shared memory 41 between two targets that have different byte orders A shared memory between two targets that do not have the same byte ordering can be tricky eTPU TPU Channel Function Select Register Script Commands write_chan_func ChanNum Val This command sets channel CHANNUM to function Val define MY_FUN_NUM 0x10 write_chan_func 7 0x10 In this example channel 7 is set to function 10 decimal All other channel function selections remain unchanged In the Byte Craft eTPU C compiler the function number can be automatically generated using the following macro pragma wri te h define MY_FUNC_NUM ETPUfunctionnumber Pwm eTPU TPU Channel Priority Register Script Commands write_chan_cpr ChanNum Val This command writes the priority assignment Val to the CPR for channel ChanNum write_chan_cpr 6 2 In this example a middle priority level 2 middle priority is assigned to channel 6 by writing a two to the CPR bits for channel 6 All other TPU channel priority assignments remain unchanged eTPU TPU Pi
172. icing decisions on the Channel Priority Register CPR the Service Request Latch SRL and the Service Grant Latch SGL These latches are affected by the Host Service Request Register HSRR the Link Service Requests LSRs and the Match or Transition Service Requests M TSRs which are also displayed The M TSR is generated from the Match Recognition Latch MRL Transition Detection Latch TDL and the Match Transition Service Request Inhibit SRI latch The M TSR is formed from the following logical expression MRL and TDL or SRI Each register is broken down by TPU channel such that the value for each channel is easily found Most of these registers can be modified only by the TPU 108 TPU Microsequencer Registers Window Availability TPU Simulation Target Time GLIIMELPS us CPU Clock 666611282 TCR1 1D66 TCR2 6626 TCR2 Input Pin High Active Channel T 6 T 4 D D D D Address O6F6 Rtn 0034 Prefetch 66F4 Prefetch Opcode 9445FFFF Dec Inactive Banks Code Entry The TPU Microsequencer Registers window displays miscellaneous information generally applying to the microsequencer This window is something of a catch all The current Simulator time is displayed The time is expressed in microseconds The count of CPU clocks since the last Simulator reset is als o displayed The TCR1 and TCR2 counter values are displayed These 16 bit counters are displayed in hexadecimal The TCR2 input pin s v
173. ified symbol MtDt automatically displays it in this field Otherwise MtDt displays a message indicating that the user specified symbol could not be resolved The user can edit the user resolution field In future versions of this software this will cause the actual variable values within the targets to be modified Symbolic Data Options The Watches window supports both global and local variables Variables are resolved by looking at the innermost local scope first followed by any outer scopes in order then followed by any static variables and finally the global scope Currently a subset of C syntax is supported for the left hand side symbol input 2 Pointers can be dereferenced with the operator 92 Array elements can be accessed with the operator where the subscript is an integer Structure members can be accessed via the or gt operators In the current release only a single operator per watch is supported Future versions will support a more full feature C syntax Note that code must be compiled with symbolic debug information for this functionality to be available Local Variables Window 32 MyBdm32 Local Variables ioj x Function watchExample in watchExample c data 2004318071 0x77777777 cnt 3 THREE packet Ox2FFS4 packet size 13 6xd packet buffer 6x26632 ABCDEFGHI JKLM xpacket buffer 65 A c 78 N register D3 i 13 6xd register D2 mimi The Local
174. iftDown Waveform Boundary Time Indicators The left and right time indicators show the time associated with the left most and right most visible portions of the waveform pane The waveform pane can be changed so that a different portion of the waveform is in view For example use the mouse to drag the current time by depressing the left mouse button over the current time indicator Holding the left mouse button down move the mouse over the right time indicator the release the left mouse button Buffer Data Start Indicator The data start indicator shows the time associated with the very first data in the buffer This time indicator generally shows zero because the buffer can usually hold all the previously saved pin transition data But occasionally the buffer overflows so that the very oldest data must be discarded and in this case the indicator shows the non zero time associated with the oldest valid data Current Time Indicator The current time indicator is the latest time associated with any target in the system Drag and drop any time into this field as explained in the Executing to a Precise Time section Auto Scroll the Waveform Display as the Target Executes Selecting auto scroll causes the Logic Analyzer to continuously update the view as the simulation runs De selection causes the Logic Analyzer to cease updating the view as the simulation runs Button Controls Zoom In Es Selecting the Zoom In button narrows the vi
175. ify the file name In disassembly dump files inclusion of address raw values addressing mode information and symbolic information can be selected When creating an image file or a C data structure file or when using the fill function data word size can of eight bits 16 bits or 32 bit For the fill function verification after the fill can be selected The find capability allows a specific byte pattern to be located in memory Options include the ability to search for between one and eight sequential bytes as well as the ability to search for both a case sensitive or case insensitive string C data files can be written with the address included within a comment Output format can be either hexadecimal which is the default or decimal Selection of endian ordering is available for where the data size is exceeds one byte This option is available when dumping to an image or a C structure file or when using the find function In cases where the selected endian ordering does not match the natural endian ordering of the target a warning is displayed Insert Watch Dialog Box The Insert Watch dialog box is used whenever a new watch is added to the watch window using the insert function Two lists support the ability to either re select and presumably modify a currently active watch and the ability to re select a previously discarded watch string You can also edit a brand new string 154 or modify any string selected from the
176. ilable on eTPU Simulator targets eTPU Channel Function Frame eTPU Configuration Window 2 eTPU Global Timer and Angle Counters Window eTPU Host Interface Window eTPU Channel Window eTPU Scheduler Window eTPU Execution Unit Registers Window TPU Simulator Specific Windows The following windows are available on TPU Simulator targets 87 TPU Configuration Window TPU Host Interface Window TPU Scheduler Window TPU Microsequencer Registers Window TPU Execution Unit Registers Window TPU Channel Window TPU Parameter RAM Window Logic Analyzer 683xx Hardware Debugger Windows The following windows are available for 683xx Hardware Debugger targets 683xx Hardware Debugger Configuration Window 683xx ASH WARE Hardware Window System Integration Module Windows SIM Main Window SIM PortsWindow SIM Chip SelectsWindow Queued Serial Module Windows a QSM Main Window QSM Port Window QSM QSPI Window QSM SCI UART Window RAM and ROM Windows Masked ROM Submodule Window 68336 68376 Standby RAM Submodule Window 68336 68376 H Static RAM Submodule Window 68338 TPU Emulation RAM Window 68332 68336 68376 Timer Processor Unit Windows TPU Main Window TPU Host Interface Window TPU Parameter RAM Window General Purpose Timer Windows GPT Main Window GPT Input Captures Window GPT Output Compares Window GPT Pulse Accumulation Window 88 GPT Pulse Width Mo
177. ile that can be used to wiggle the TPU s I O pins The relative timing of targets is maintained with one femto second precision Each target has its own atomic execution step size that must be a multiple of the femto second precision Negative numbers and zero are valid steps sizes Since the currently supported targets are all execution cycle simulators the step size is equal to the amount of simulated time it takes to execute a single opcode As each target executes it is advanced by the amount of time the last opcode took to execute It is then scheduled to execute again when the simulation time is equal to the target s next scheduled time The current simulation time is defined as the time that the next scheduled target will execute Although all the currently supported targets are execution cycle simulation engines this is not a fundamental restriction of MtDt In fact MtDt can support targets that have much finer execution granularities This would allow for instance a VHDL target that properly models inter target interaction down to the transistor level Debugging Capabilities All standard single target debugging capabilities such as single stepping breakpoints goto cursor etc have been extended to the multiple target environment For instance if breakpoints are injected and activated within multiple targets the simulation halts on whichever breakpoint is encountered first A concept of an active target is employed to support
178. ile was passed on the command line Otherwise the MtDt project file passed on the command line is opened The paths to all other files are stored and retrieved relative to the MtDt project file This allows the entire set of project files to be bundled and moved together as a group Whenever the MtDt application is exited the configuration is automatically written to the active MtDt project file 19 SOURCE CODE FILES User executable files are generated from source code using compilers assemblers and linkers For TPU simulation engines Freescale s TPU Microcode Assembler can be used though this will soon be replaced with ASH WARE s own integrated assembler linker For other targets industry standard compilers such as Introl Diab Data or GNU can be used These executable files are loaded into the target s memory space MtDt also loads the associated source code files and displays them in source code windows highlighting the line associated with the instruction being executed Several hot keys allow the user to set breakpoints execute to a specific line of code or execute until a point in time The executable code is loaded by selecting the Executable Open submenu from the Files menu and following the instructions of the Load Executable dialog box The loaded source code file is then displayed in a context window The window can be scrolled re sized minimized etc Help is available for the source code file window and is accesse
179. ility 68332 Hardware Debugger 117 32 MyBdm32 QSM SCI ioj x sccre EEE scar C 6 SCI clock period 666 615 3 micro seconds l assuming 32 768 KHz crystal SCCR1 6666 LOOP E E Normal SCI operation no looping feedback path disabled WONS D D If configured as an output TXD is a normal CHOS output ILT C C short idle line detect PT B B even parity PE A A SCI parity is disabled M 9 9 16 bit SCI frame WAKE 8 8 SCI receiver awakened by idle line detection TIE 7 7 SCI transmit TDRE interrupts are disabled TCIE 6 6 SCI transmit complete interrupts are disabled RIE 5 5 SCI receive recieve data register flag RDRF l and overrun error OR interrupts are disabled ILIE 4 4 Idle line interrupts are disabled TE 3 3 SCI receiver is disabled TXD pin can be used as I 0 RE 2 2 SCI receiver is disabled status bits inhibited RWU 1 1 Normal receiver operation received data recognized SBK 6 6 Normal operation SCSR 6186 TDRE 8 8 A new character can now be written to register TDR Te 7 7 SCI transmitter is idle RDRF 6 6 Receive data register RDR is empty or contains previously read data RAF 5 5 SCI receiver is idle IDLE 4 4 SCI receiver did not detect an idle line condition OR 3 3 Receive data register RDRF is cleared before new data arrives NF 2 2 Noise was not detected on the received data FE 1 1 A framing error or break w
180. in the address space ADDR_SPACE for the number of iterations specified by numlterations This is the most robust test but it provides no diagnostic capabilities It writes a pseudo random number sequence to the entire memory device and then verifies that it reads back correctly The most difficult to detect errors will generally be detected by this test test_increment startAddress stopAddress startVal enum ADDR_SPACE numlterations This command runs the block increment RAM test between stopAddress and startAddress in the address space ADDR_SPACE for the number of iterations specified by numIterations using the start value startVal as the initial value from which to incre ment This is the least robust test but it is excellent for human factors purposes Folks like you and I are generally quite good at picking out breaks in patterns For a typical memory error this test sets the memory to a convenient pattern so that we can easily spot errors by scrolling down through a memory dump window test_seam address enum ADDR_SPACE numlterations This command runs the seam RAM test at address in the address space ADDR_SPACE for the number of iterations specified by numIterations This was developed to verify proper functionality of all read and write accesses at the boundary between two memory devices All combinations of even odd and double odd addresses and 8 16 and 32 bit wide accesses are exercised Note that the test assumes that all t
181. inder 2 lt lt gt gt Bitwise assignment of shift right and shift left A Bitwise assignment of and or and exclusive or lt lt gt gt Bitwise assignment of shift left and shift right The following examples perform assignments on memory 28 Writes a 44 decimal to the 8 bit byte at address 17 U8 0x17 44 Sets bits 31 and 15 of the 32 bit word at address 0x200 U32 0x200 I 0x10001000 Increments by one the 16 bit word at address 0x3300 U16 0x3300 1 Using an optional memory space qualifier memory from a specific address space can be modified See the Build Script ADDR_SPACE Enumerated Data Type section for a listing of the various available address spaces Sets the TPU I O pins for channel 15 and channel 3 TPU_PINS_SPACE U16 0x0 l 1 lt lt 15 1 lt lt 3 Sets the TPU s HSQR bits such that channel 7 s isa 11b TPU_DATA_SPACE U32 0x14 3 lt lt 7 2 Injects a new opcode into the TPU s code space TPU_CODE_SPACE U32 0x20 0x12345678 Operators and Expressions in Script Commands Files Operators can be used to create simple expressions in script commands files Note that these simple expressions must be fully resolved at load time The precedence and ordering is the same as in the C language The following is a list of the supported operators Arithmetic addition and subtraction Arithmetic multiply divid
182. int then the breakpoint is deleted A source code window must be active for this to work If the cursor is beyond the last instruction associated with the file then this will not work Disable All This disables all active breakpoints Disabled breakpoints remain disabled MtDt remembers which breakpoints have been disabled such that the Enable Breakpoints submenu can reactivate all disabled breakpoints 159 Enable All This enables all disabled breakpoints Delete All This deletes all active and disabled breakpoints Selecting this submenu causes MtDt to forget which instructions had breakpoints Help This accesses this help screen Activate Menu The Activate menu allows you to specify which workshop and target are active These capabilities are accessed via the following submenus Workshop This displays a list of workshops that can be activated Activation of a workshop causes all windows within that workshop to be displayed and the target associated with that workshop if any to be activated Activation of an associated target upon workshop activation is a feature that can be disabled within the Workshop Options dialog box Target This displays a list of targets that can be activated The active target is the one used when target specific functions such as single stepping are selected This feature is useful only in a multiple target environment Help This accesses this help screen View Menu This menu opens
183. ion Behavior Verification section read_behavior_file filename bv This command loads the pin transition behavior file into the master pin transition behavior buffer This buffer forms a behavioral model of the pin transition behavior of the source code verify_all_behavior Q This command verifies all recorded pin transition behavior against the master pin transition behavior buffer It generates a behavior verification error message and increments the behavior failure count for each deviation from the behavioral model enable_continuous_behavior This command enables continuous verification of pin transition behavior against the master pin transition behavior buffer During source code simulation each functional deviation generates a behavior verification error message and causes the behavior verification failure count to be incremented This is useful for identifying the specific areas in which the microcode behavior has changed disable_continuous_behavior This command disables continuous verification of pin transition behavior against the master pin 43 transition behavior buffer Note that pin transition behavior is still recorded in the pin transition behavior buffer 1 ETPU TPU Resizing the Pin Transition Buffer resize_pin_buffer lt NumPinTransitions gt This command resizes the pin transition buffer The default size is 100K transitions resize_pin_buffer 500000 In this example the pin transition buf
184. ions are available To change a viewing option activate a memory window and from the Options menu by select the desired option from the Memory submenu 99 Memory is viewable in 8 16 or 32 bit mode The ASCII equivalent text on the right side can be turned off or on The address space can be specified The base address of the window can be specified A common development tool deficiency is that the vertical scroll bar is unusable because it causes too much memory to be traversed MtDt addresses this problem by limiting the scroll range of the vertical scroll bar A memory dump window displays only a small amount of the total address space The portion of memory that the memory window displays is specified by the base address parameter Timers Window Model16 Timers lolx Start Stop This Last Last Time ID State Address Address Ticks Ticks micro seconds 6 Ores 86666196 00000194 66066628 66666628 006 010 0 1 Disabled 66661666 66662666 FFFFFFFF 666 660 6 2 Finished 66666146 6666616A 66662A73 66662A73 662 931 6 3 Disabled 66661666 66062666 E FFFFFFFF 006 0006 0 4 Disabled 66661666 66662666 oa FFFFFFFF 666 666 6 5 Disabled 66661666 66662666 FFFFFFFF 666 666 6 6 Disabled 66661666 66062666 FFFFFFFF 006 000 0 7 Disabled 66661666 66662666 FFFFFFFF 666 666 6 8 Finished 66666698 66666164 66662AE3 66662AE3 662 957 4 9 Started 66606613A 666666A6 FFFFFFFF 006 000 0 A Disabled 66661666 66662666 FFFFFFFF 666 666 6 B Dis
185. ipt Commands Interrupts can cause special script ISR file to execute as described in the Script ISR section clear_chan_intr ChanNum clear_chan_overflow_intr ChanNum clear_data_intr ChanNum clear_data_overflow_intr ChanNum These commands clear the interrupts for channel ChanNum It is equivalent to setting the bit associated with the channel in the CICX DTRC CIOC or DTROC fields verify_chan_intr ChanNum Val verify_chan_overflow_intr ChanNum Val verify_data_intr ChanNum Val verify_data_overflow_intr ChanNum Val verify_illegal_instruction ChanNum Val verify_microcode_exception ChanNum Val These commands verify that the respective interrupts are either asserted Val 1 or de asserted Val 0 clear_global_exception This command clears the global exception along with the exception status bits It is equivalent to setting the GEC field in the ETPUMCR field disable_chan_intr ChanNum enable_chan_intr ChanNum disable_data_intr ChanNum enable_data_intr ChanNum These commands enable disable the interrupt for channel ChanNum Note that if you associate a script ISR file with an interrupt these commands allow or prevent that file from running on assertion of the interrupt clear_this_intr This command can only be run from within a script ISR file It clears the interrupt that caused the command to execute TPU Parameter RAM Script Commands write_par_ram ChanNum ParamNum Val This com
186. is capability is only available for the eTPU and TPU simulation targets The recorded behavior is saved to this file Save Coverage Statistics Dialog Box The Save Coverage Statistics dialog box is opened from the Files menu by selecting the Coverage Statistics Save submenu This dialog box is currently only available for TPU Simulation targets From the Save Coverage Statistics Dialog Box a coverage filename is specified An overview of the coverage statistics since the last reset on both a project and a file by file basis is written to this file Auto Build Batch File Options Dialog Box The Auto Build Batch File Options dialog box provides the capability of building the executable image file source code from within MtDt This dialog box is opened from the Files menu by selecting the Auto Build Open submenu The auto build batch file is a console window batch file In this batch file the user puts the shell commands that build the executable image from the source code MtDt executes this auto build batch file The following describes the various capabilities accessed from within the Auto Build Batch File Options dialog box Edit Window From within this window the user can edit the currently selected auto build batch file Edits to this file are saved only if the user hits the OK button the OK Build button or the Build button If the Cancel button is hit or if a new file is selected before one of these buttons is hit then all edits a
187. is encountered A source code window must be active for this command to work Goto Time This opens the Goto Time dialog box Runs MtDt until the specified time or until a breakpoint is encountered Goto Time Fast This behaves exactly like the Goto Time submenu except the goto time dialog box is not opened Instead the previously specified Goto Time options are used Go This causes MtDt to execute indefinitely MtDt executes until a breakpoint is encountered or until the user terminates execution by selecting the Stop submenu in the Run menu Stop This causes MtDt to stop executing This is normally used to stop MtDt when the expected event such as step breakpoint time slot transition etc failed to occur Reset and Go This causes MtDt to reset and immediately begin execution The reset actions are specified in the Reset Options submenu MtDt will execute until a breakpoint is encountered or until interrupted by the user selecting the Stop submenu from the Run menu Reset This causes MtDt to reset The reset actions are specified in the Options submenu in the Reset menu Help This accesses this help screen Breakpoints Menu The breakpoints menu controls the various functions associated with the breakpoint capabilities of the MtDt These capabilities are accessed via the following submenus Set Toggle This toggles a breakpoint at the instruction source code window s cursor If the instruction already has a breakpo
188. ister enumerated type with a definition that depends on the specific target and register width on which the script command is acting The second argument is the value to which the register will be set write_reg4 U4 enum REGISTERS _U4 write_reg8 U8 enum REGISTERS_U8 write_reg16 U16 enum REGISTERS_U16 write_reg32 U32 enum REGISTERS_U32 write_reg64 U64 enum REGISTERS_U64 The following example modifies register values of a CPU 16 target write_reg4 0x12 REG_ZK write_reg16 0x5557 REG_PC In the example above a script file which is acting on a CPU16 target writes 12 hexadecimal to the index register Z s address extension register and writes 5557 hexadecimal to the program counter Verify Register Script Commands Verify register script commands provide the mechanism for verifying the values of the target registers The first argument is a register enumerated type with a definition that depends on the specific target and register width on which the script command is acting The second argument is the value against which the register will be verified verify_regl1 enum REGISTERS_U1 U1 verify_reg4 enum REGISTERS_U4 U4 verify_reg5 enum REGISTERS_U5 U5 verify_reg8 enum REGISTERS_U8 U8 verify_reg16 enum REGISTERS _U16 U16 verify_reg24 enum REGISTERS _U24 U24 verify_reg32 enum REGISTERS _U32 U32 verify_reg64 enum REGISTERS _U64 U64 The following example verifies register values of a CPU16 target v
189. k that has been marked as blank Read Write Control It is possible to disable specific types of memory accesses In this example a memory device is configured as read only A write to this memory device will not cause the values in memory to change This read only behavior could be used to model a ROM device define ROM_STOP Oxffff define BLANK_START ROM_STOP 1 define MEM_END Oxffffffff instantiate_target SIM32 MyCpu add_mem_block MyCpu 0 ROM_STOP Rom ALL_SPACES add_non_mem_block MyCpu BLANK_START MEM_END Empty ALL_SPACES Turn off READ access for the ROM device define WRITE_ALL RW_WRITES8 RW_WRITE16 RW_WRITE32 set_block_to_off MyCpu Rom ALL_SPACES WRITE_ALL The command specifies that for all address spaces all write accesses will be empty Despite this 174 being an empty access other parameters such as clocks per even cycle remain valid The last two arguments specify the aldress spaces and access types affected by this script command It is possible to indicate specific address spaces and a specific type of access For instance using this script command one could specify 32 bit writes to user data space Clocks per Access Control For each memory block and type of access the clocks per even access and the clocks per odd access can be specified This capability effectively provides the capability of setting the number of wait states set_block_timing MyCpu Rom
190. kFromS pace are transformed to occur in address space enum ADDR_SPACE DockToSpace The DockToSpace argument must specify a single space It is important to fully specify all shared memory accesses between dissimilar targets Docks with unspecified address space transformations result in indeterminate results For instance a CPU16 sharing memory with a CPU32 could easily result in a opcode being fetched out of data space even though both targets have both code and data spaces Assumptions about similarity of address spaces between dissimilar targets simply should not be made add_non_mem_block MyCpu 0x1000 0x1003 ShareRange ALL_SPACES set_block_to_dock MyCpu ShareRange ALL_SPACES MyTpu 0 0x1000 set_block_dock_space MyCpu ShareRange ALL_SPACES RW_ALL 57 TPU_PINS_SPACE In this example a target MyCpu is docked to target MyTpu An address space transformation is specified such that accesses to any of the CPU s address spaces occur in the TPU s PINS address space tot check TargetName ReportFileName This command does a check on the simulated memory for a target TargetName and creates a report file ReportFileName The check invoked by this command occurs whether or not this script command is included in the script file Use of this command allows you to specify the name of the report file and limit the scope of the check to a single target check MyCpu C Temp CpuBuildReport txt check
191. le on a variety of microcontrollers There are currently three varieties known as TPU1 TPU2 and TPU3 MtDt 166 supports all three varieties The TPU simulation engine can be used both as a stand alone device and in conjunction with other targets including multiple TPUs When used in stand alone mode of primary importance are script commands files and test vector files The TPU simulation engine is used for developing debugging and verifying operation of TPU microcode User microcode is loaded from files currently generated by Freescale s TPU Microcode Assembler These files are loaded into the TPU simulation target s microcode space The storage format is the binary equivalent of the microcode actually executed by the TPU MtDt also displays user microcode source files in source code windows highlighting the line associated with the actual microinstruction being executed Additional TPU operational status information is displayed in various context windows The windows include information about channel control registers host CPU interface registers microengine control registers the scheduler script commands files source microcode files etc The Time Processor Unit TPU The TPU is a microsequencer developed by Freescale for measurement and generation of time critical waveforms It is a single silicon target that is offered on several microcontroller products such as the MC68332 and the HC16 The TPU has two operational mod
192. le that is available differentiates the language for each application Each file is arranged as a sequential array of commands i e MtDt executes the script commands in sequential order This allows MtDt to know when to execute the commands Timing commands cause MtDt to cease executing commands until a particular point in time At that point in time MtDt begins executing subsequent script commands until it reaches the next timing script command Timing commands are not allowed in startup or MtDt build script files The following script help topics are found later in this section 7 Script Commands File Format Script Command Groups Multiple Target Scripts Automatic and Predefined define Directives Predefined Enumerated Data Types Types of Script Commands Files There are four types of script commands files These are listed below and a description of each can be found later in this section The Primary Script Commands Files ISR Script Commands Files 2 The Startup Script Commands File 2 The MtDt Build Commands File MtDt can have only a single active MtDt build batch file Each target may have only a single primary script commands file and a single startup scripts commands file active at any one time ISR script commands files are associated with interrupts Although each interrupt may have only a single associated ISR script commands file it is important to note that each script commands file may be associated with multi
193. m the command line This is explained in detail in the Regression Testing section The following command line is found in the batch files used as part of the automated testing of the eTPU simulator echo Running ALUOP ADD NORMAL Tests eTpuSim pAutoRun ETpuSysSimProject AutoRun AcceptLicense d_AUTO_TEST_AU_ALUOP_ADD_NORMAL_ if Z ERRORLEVEL NEQ 0 goto errors In the primary script file that is part of this project the following command is used to load the executable file that is specific to this test ifdef AUTO_TEST_AU_ALUOP_ADD_NORMAL_ load_executable AuAluopAddNormal gxs endif _AUTO_TEST_AU_ALUOPI_ADD_NORMAL_ TPU Target Pre Defined Define Directives The following define directives are automatically loaded and available for both TPU Simulator and TPU Debugger targets 59 define CFSRO U16 0x0C define CFSR1 U16 OxOE define CFSR2 U16 0x10 define CFSR3 U16 0x12 define HSQ U32 0x014 define HSQO U16 0x014 define HSQ1 U16 0x016 define HSRR U32 0x018 define HSRRO U16 0x018 define HSRR1 U16 Ox01A define CPR U32 0x01C define CPRO U16 0x01C define CPR1 U16 0x01e Pre Defined Enumerated Data Types Listed below are the predefined enumerated data types used on a variety of script commands Clicking on the desired enumerated data type will access a listing a Script FILE_TYPE enumerated data type Script FIL
194. mand writes channel ChanNum s 16 bit parameter ParamNum to value Val write_par_ram 3 1 0x2222 In this example channel 3 s parameter one RAM word is written to value 2222 hex verify_ram_word ChanNum ParamNum Val This command verifies that channel ChanNum s RAM word number ParamNum is equal to Val If the verification fails a verification failure messages is printed to the screen This verification failure message can be disabled from the Message Options dialog box The accumulated count of verification failures is available in the Configuration Window verify_ram_word 0xa 3 0x1324 In this example channel 10 s parameter RAM word three is verified to be equal to 0x1324 hex If 48 the value is indeed equal to 0x1324 hex then the simulation continues If the value is not equal to 0x1324 hex an error message is printed to the screen verify_ram_bit ChanNum ParamNum BitNum V al This command verifies that channel ChanNum s RAM word number ParamNum bit BitNum is equal to Val Bit 15 is defined as the most significant while bit 0 is defined as the least significant Val must be between zero and one inclusive If the verification fails a verification failure messages is printed to the screen This verification failure message can be disabled from the Message Options dialog box The accumulated count of verification failures is available in the Configuration Window verify_ram_bit 0xa 3 14 1 In this example channel 10
195. mmand applies only to memory spaces ADDR_SPACE and for the read and or write cycles enum READ_WRITE Even accesses are set to ClocksPerEvenAccess while odd accesses are set to ClocksPerOddAccess define NOT_DATA_SPACE ALL_SPACES CPU16_DATA_SPACE add_mem_block MyCpu16 0 OxFFFF SlowMem ALL_SPACES set_block_timing MyCpu16 SlowMem CPU16_DATA_SPACE RW_READ 4 8 set_block_timing MyCpu16 SlowMem CPU16_DATA_SPACE RW_WRITE 2 3 set_block_timing MyCpu16 SlowMem NOT_DATA_SPACE RW_ALL 5 6 56 In this example the even data reads are set to take four clocks while odd data reads are set to take eight clock cycles Even data writes take two clock cycles while odd accesses take three All non data even reads and writes take five clocks while odd take six This example illustrates an important aspect of timing design A separate copy of the timing data is kept for each address space and for both read and write cycles So even though only a single memory block was created in this example timing data for each address space is able to be individually specified set_block_to_dock FromTargetName BlockName enum ADDR_SPACE ToTargetName AddressOffset This script establishes a memory share between a docking target FromTargetName and a docked to second target ToTargetName Memory accesses for the docking target actually occur in the second target while this command has no effect on the second
196. mmands sets either channel chanNums s or the TCR2 s pin hi logical 1 or lo logical 0 pin_hi 0xC pin_lo 5 ter2_loQ In this example channel 12 s pin is set to a one channel 5 s and the TCR2 pin are set lo verify_pin chanNumber pinState This command verifies that channel chanNumbers s pin is equal to pinState logical one or zero If the verification fails a verification failure messages is printed to the screen This verification failure message can be disabled from the Message Options dialog box verify_pin 3 1 In this example channel 3 s pin is inspected and if it not a one a verification failure message is printed to the screen and the verification failure count is incremented eTPU TPU Pin Transition Behavior Script Commands The pin transition behavior capabilities allow the user to generate behavioral models of the source code and to verify the source code against these saved behavioral models The script commands allow the user to automate this second verification process Script command capabilities include the ability to load pin transition behavior files the ability to enable continuous verification against these models and the ability to perform a complete verification of all recorded behavior at once A more complete discussion of functional verification is given in the Functional Verification chapter while a discussion of the specifics of pin transition behavioral modeling is given in the Pin Transit
197. mple two devices are created in such a way that a zero byte seams between them is guaranteed All memory for every address spaces is covered Notice that the FLASH and RAM sizes can be changed at a single location and that the devices will remain contiguous in memory 173 Memory Block Access Control The purpose of the memory block access control is to make a simulated model match the behavior of real hardware For instance you might want to make a ROM read only such that reads are simply ignored or perhaps cause a bus fault An odd access may cause an address fault or an additional wait state Memory block access control allows the required level of control to achieve this This section serves as a high level guide rather than a detailed description Each memory block supports the following access types 8 bit read 8 bit write 2 16 bit read 16 bit write Z 32 bit read 32 bit write 64 bit read not yet implemented 64 bit write not yet implemented For each access type the user can specify a number of parameters The following parameters are available Clocks per even access Clocks per odd access Odd access causes bus fault yes no Bus fault yes no Blank access yes no Dock offset applicable docked accesses only Dock function code applicable to docked accesses only In addition there is a block wide default blank access value This is the value that is returned on a read access to a memory bloc
198. n To the right of the menu help indicator is the ticks indicator This displays the number of ticks since the last target reset if available This indication may not be valid for hardware targets that have been free run since the last reset as MtDt is not able to determine the number of clock ticks under this condition To the right of the ticks indicator is the steps indicator This indicates the number of opcodes that have been executed for the active target since the last reset The limitations listed above for the ticks indicator also applies to the steps indicator To the right of the steps indicator is the failures indicator The failures indicator lists the number of script commands and behavior failures respectively To the right of the failures indicator is the target type indicator This is a bitmap that depicts the type of target that is currently active To the right of the target type indicator is the current time indicator This displays the amount of time that has occurred since the last target reset The limitations listed above for the ticks indicator also applies to the current time indicator To the right of the current time indictor is a clock A clock is a clock Use this to determine if it is time to go home 163 SUPPORTED TARGETS AND AVAILABLE PRODUCTS Due to its layered design MtDt supports a variety of both simulated and hardware targets Customer requirements dictate that these capabilities to be offered as
199. n Control and Verification Script Commands eTPU input pins and TPU I O pins configured as inputs are normally controlled using test vector files eTPU output pins and TPU I O pins configured as outputs are normally controlled by the eTPU TPU and are verified using master behavior verification test files described in the Functional Verification section Therefore these commands are not the primary method for controlling and verifying pin states Instead these commands serve as a secondary capability for pin state control and verification eTPU Topics write_chan_input_pin ChanNum Val write_tcrclk_pin Val verify_chan_output_pin ChanNum Val verify_ouput_buffer_disabledQ verify_ouput_buffer_enabledQ These commands write either ChanNum s or the TCRCLK pin to value Val verify that ChanNum s pin is equal to Val or verify that an output buffer is enabled or disabled write_chan_input_pin 25 0 write_tcrclk_pin 1 In this example channel 25 s input pin is cleared to a low and the TCRCLK pin is set high verify_chan_output_pin 5 1 verify_ouput_buffer_disabledQ wait_time 5 verify_chan_output_pin 5 0 verify_ouput_buffer_enabledQ 42 In this example channel 5 s output pin is verified to have a falling transition within a 5 micro second window It is also verifying that the pin is acting like an open drain active low passive high TPU Topics pin_hi chanNum pin_lo chanNum ter2_hiQ ter2_loQ These co
200. n input capture or output compare has occured l Interrupt level is l Interrupt arbitration bit 3 IARB BIUMCR IARB 2 0 If output then buffer operates mode is mode Connected to time base bus Pin function when input l Set to force chan A compare always reads 6 I Set to force chan B compare always reads 8 l l l l l l l l l l l l l l Edge Polarity l l l l l Mode selecte string l l l l l Bits of resolution L IN FORCA FORCB EDPLO MODE I l l l l l l l l L l SIC D A D B FLAG l l l l l I IARB3 WOR BS DASHOY 938C 9266 988A Yes 1 clr wired or B High 6 6 6 C 12 OPWH DASHOS 6224 6666 6666 No DIS clr wired or A Low 6 1 6 4 16 OCB DASH66 8003 1900 6666 W DIS clr normal A Low 68 6 8 3 16 IC DASHO7 6664 0101 6666 No DIS clr normal A Low 8 8 8 4 16 OCB DASHOS 6326 6666 693A No DIS clr wired or B Low 8 1 8 6 unused DASH69 198D 6666 BAGOI No 1 SET normal B High 86 6 6 D 11 OPWH DASH16 BOGS 6761 6666 Yes 3 clr normal A Low 8 8 8 5 16 OCAB DASH26 6222 6666 6666 No DIS clr wired or A Low 6 1 6 2 16 IPH DASH27 6641 6666 6666 No DIS clr normal A Low 1 6 6 1 16 IPWH DASH28 6666 6666 6666 No DIS clr normal A Low 6 6 6 6 E DIS DASH29 6666 6666 6666 No DIS clr normal A Low 6 8 8 6 E unused 125 The CTM6 Double Action Bits Submodule window displays the DASM 4 5 6 7 8 9 10 26 27 28 and 29 Status Interrupt Control Registers DASM4SIC DASMSSIC etc and the DASM Data A and B registers DASM4A DASM4B DA
201. ncoming teeth and the frequency of the synthesized angle ticks The Tick Rate Register should be updated by the eTPU code on each incoming physical tooth It is calculated based on the time difference between the last two incoming physical teeth and specifies the time of each angle tick in TCR2 ticks In order to reduce error both an integer INT and fractional FRAC portion of the ratio of TCR1 counter ticks to TCR2 ticks is supported In angle mode the TCR2 s tick rate is proportional to angle instead of time As such the TCR2 counter may be reset when it completes a rotation which is every 720 degrees in a typical car The number of such rotations since the last reset is shown as are the number of PLL synthesized teeth and the number of synthesized angle ticks Additionally the current angle is shown which is based on 720 degrees per rotation Some analysis is provided of the operational state of angle mode Angle mode is in normal wait or high speed depending on whether the PLL is on track ahead or behind Channel 0 can be programmed to form a sampling window and the open or closed state of this window is displayed The edge which the angle mode hardware is displayed and it should be noted that this edge must be programmed to correspond the edge that is also shown which is the edge being detected by channel 0 and which forms a detection window Spurious operation could result if these do not correspond Also channel 0 can be programmed t
202. ndred kilobytes This is a trivial amount of memory for a modern computer When many megabytes are required you are limited to the amount of virtual memory availabk for the MtDt application that your computer can provide If you attempt to simulate a 100 gigabyte memory device for example but have only 50 gigabytes of available virtual memory on your computer the build script file will fail to execute Note that since modern computer systems employ virtual memory the amount of simulated memory can exceed the amount of RAM actually in your computer Adjusting the available amount of virtual memory on your computer can increase the total amount of memory devices that you can simulate A description of how to increase the swap file size of your computer is beyond the scope of this manual 180
203. nds file is open Only one primary script 142 commands file may be opened for each target at one time The default search is XXXCommand where XXX denotes the type of target For instance for TPU Targets the default search is TpuCommand Save Primary Script Commands Report File Dialog Box This dialog box specifies the report file that is generated when the primary script commands file is parsed Note that selection of a file name does not actually cause the report file to be written Rather the report file is written only when the primary script commands file is parsed Open Startup Script Commands File Dialog Box This dialog box specifies which startup script commands file is open Only one startup script commands file may be opened for each target at one time This file is very similar to the primary script file Almost all script commands that are supported in the primary script file are also supported in the startup script file The primary difference between primary and startup script command files is when they are executed Startup script command files are executed only when MtDt resets a target Primary script files execute as the target executes Startup script files do not support specification of a report file name The report file name generated for the startup script is always the same as the startup script file name except the file suffix is changed to report Open Test Vector File Dialog Box This dialog box is access
204. ne TPU mapped at 0xFFFE00 MASK G 683xx with one TPU mapped at 0xFFFE00 MASK MPC5xx MPC555 with two TPUs mapped at 0x304000 and 0x304400 CPU32 Stand Alone Simulator Our CPU32 Stand Alone Simulator allows you to load code into a single simulated CPU32 You can also load the standard mask TPU microcode into a simulated TPU CPU16 Stand Alone Simulator Our CPU16 Stand Alone Simulator allows you to load code into a single simulated CPU16 You can also load the standard mask TPU microcode into a simulated TPU 683xx Hardware Debugger Our 683xx Hardware Debugger allows you to control any 683xx microcontroller across a BDM port You can load and execute code Standard debugging capabilities such as single step breakpoints goto cursor etc are supported Operational status windows support viewing of CPU32 registers memory peripherals etc eTPU Simulation Engine The Enhanced Time Processing Unit or eTPU is a microsequencer sold by Freescale on a variety of microcontrollers This is sold as a stand alone product and also as a system simulator in which it is co simulated along with one or more CPU targets The eTPU simulation engine can be used both as a stand alone device and in conjunction with other targets including multiple TPUs When used in stand alone mode of primary importance are script commands files and test vector files TPU Simulation Engine The Time Processing Unit or TPU is a microsequencer sold by Freesca
205. neg_mrl neg_lsl pac high_low pin high write_mer end G6c6 fa 03DE JSR 3deh EXT26 4 STATE low write chan cpr 14 3 G6ca 37b5 0063 LDD 3h TMN16 4 PRELOAD PARAMETER g 6ce 34 01 PSHM d IMM8 2 f 6d8 37b5 E LDD Beh IMM16 4 a ENTER WHEN 101 g6q4 fa 625A JSR 25ah EXT26 4 A ACTION 4 1 Setup channel 13 to function 12 UART B6dc 34 61 PSHM d IMM8 2 ses 36K EK EKER Hed 37b5 GOOD LDD 6dh IMM16 4 sentry start_address gge2 fa 0312 JSR 342h EXT26 4 name TECH Lou hti write_chan_hsrr 13 3 cond hsr1 6 hsr6 6 m e 37b5 6003 LDD 3h IMM16 4 Bea 34 01 PSHM d IMM8 2 Bec 37b5 GHOD LDD Adh IMM16 4 Epas ra AAna Ien sanh ryran ret kil 4 These windows display the executable source code that is currently loaded in the target Each window displays one source file The executable source code is loaded into the target s memory via the Files menu To load the executable source code select the Executable Open submenu and follow the instructions of the Load Executable dialog box As the executable source code is executed the source line corresponding to the active instruction is highlighted Usually the source file is too large to be displayed in its entirety The user can use the scroll bars to view different sections of the file As the code is executed the source code line corresponding to the active instruction appears highlighted in the window The user
206. nel pins will be what actually gets read 176 Shared Memory Address Offset Shared memory need not appear in the same address from the perspective of each target Indeed shared memory usually appears at different addresses for each target that is sharing that memory The following illustrates this sce set_block_to_dock HostCpu TpuDataDock ALL_SPACES Tpu TPU_DOCK_OFFSETT I In this example an offset of TPU_DOCK_OFFSETT is applied to any HostCpu access within the docking block For example if the docking block is at address FFEOO hexadecimal and an offset of FFEOO hexadecimal is applied by defining TPU_DOCK_OFFSETT to this value a CPU access at address FFE20 occurs at address 20 within the TPU Shared Memory Timing Timing transformations allow the clock per access to be specified for the docking block For instance a shared memory block between a TPU and a CPU might take the CPU two clocks to access but might take the TPU only a single clock There is no special method for doing this The timing parameters specified by each of the targets own dock block apply to the docking target A Complete Shared Memory Example The example in this section creates a TPU simulation engine a host CPU simulation engine and a modeling CPU simulation engine The shared memory architecture from the following figure is generated 177 TPU DATA Space Host CPU All Spaces FFFFFFFF Modeling CPU All Spaces IFF FFFFFFFF 0 TP
207. ng the error level each time MtDt terminates multiple tests can be run automatically and a single pass meaning all tests passed or fail meaning one or more tests failed result can be determined Note that this only works in operating systems that support access to exit codes from a batch file Windows 98 does not support this True operating systems such as Windows XP Professional Windows 2000 Professional and Windows NT 4 0 do support automation 4 Command Line Parameters When launching any MtDt application such as a debugger or simulator the following command line options support Regression Testing h Prints a list of all the command line options p lt ProjectFileName gt Loads the specified project file 2 s lt ScriptFileName gt Loads the specified script file single target s lt TargetName gt lt ScriptFileName gt Loads a script file into a specific target 7 d lt DefinedText gt In script commands file define DefinedText i lf5 lt LogFileName log gt Logs messages to end of this file tn lt TestName gt Assigns a name to a test used in log file 3 Quite Disables display of dialog boxes 2 IAcceptLicense Skips the startup license agreement dialog box AutoRun Sets the target system to running Test Termination Termination of MtDt and the passing of the test results to the command line batch file is a key element of Regression Testing At the conclusion of a script file MtDt can be shut down usin
208. nly those windows belonging to that group Generally it is best to group by target so that each workshop is associated with a specific target though this is completely configurable by the user Some windows such as watch windows and the logic analyzer windows are often made visible in multiple workshops Menus and toolbar buttons allow instantaneous switching between workshops and selection of the active target The name of the active target is also prominently displayed in the top right toolbar button Closely coupled with workshops is the concept of the active target It is generally best to associate targets with workshops Thusly when the workshop is switched the active target is also automatically switched to the one associated with the newly activated workshop The active target is important in that MtDt acts on the active target in a variety of situations For instance if the user commands a single step the active target is the one that gets single stepped and all other targets are treated as slave devices and are stepped however much is required in order to cause the active target s simulation to progress by one step MtDt makes use of the active target when a new executable code image is loaded Clearly the user needs to have the ability to select a new executable image into a single specific target But which target should this be MtDt automatically selects the active target as the one into which the executable code image is to be loaded
209. nnels with QADC controlled external multiplexing 683xx ASH WARE Hardware Window Availability 683xx Hardware Debugger 32 MyBdm32 Hardware of x Using ELIS Rte ae BDH Port Errors 66666666 Go Mode is Lock Step Is ASH WARE Hardware Yes Hardware Revison 32 05 Build A Bypass Mode is Available Bypass Mode Read is Disabled Bypass Mode Write is Disabled Jumper6 is Installed Jumper1 is Installed PLD Register Bit SET Data Bus Size Word Data Bus Wait States 6C Clock Cycles Per Second Hex 66866666 The first field indicates to which parallel port the BDM cable is attached The BDM Port errors field gives the total number of low level communications errors encountered This field should never be greater than zero when the port communications are working properly The Lock Step field indicates if the hardware is free running or is in lock step Lock step is when the hardware is only single stepped This greatly reduces the target execution speed and generally should not be selected The Hardware Revision field gives the release number of the ASH WARE hardware Bypass mode is a special accelerated communications mode in which the normal BDM path is bypassed to speed up code download and upload The three fields indicate if the mode is available if bypass mode is enabled for reads and if bypass mode is available for writes Enabling bypass mode significantly improves code uploads downloads and window display update rates The PLD
210. non_mem block or a block in which the read cycles have been set to off The affected address spaces must be a subset of the address spaces to which the referenced memory block applies add_non_mem_block MyCpy 0xFFFF 0xFFFFFFFF Unused ALL_SPACES set_block_off_data MyCpu Unused 0x5A In this example the address space between FFFF and FFFFFFFF hexadecimal is specified to contain no memory Read cycles to this block will return the specified off data 5A hexadecimal at every address For instance a 32 bit read in this block returns SASASASA hexadecimal set_block_to_bus_fault TargetName BlockName 55 enum ADDR_SPACE enum READ_WRITE This command results in bus faults for accesses to the target TargetName within the block BlockName for the applicable address spaces ADDR_SPACE and read and or write cycles enum READ_WRITE The effected address spaces must be a subset of the spaces to which the referenced memory block applies add_mem_block MyCpu32 0x10000 0xFFFFFFFF Unused ALL_SPACES set_block_to_bus_fault MyCpu32 Unused ALL_SPACES RW_ALL In this example a memory block has been added to represent the unused address space above 64K Any access to this memory block results in a bus fault set_block_to_priv_viol TargetName BlockName enum ADDR_SPACE enum READ_WRITE This command results in privilege violations for accesses to the target TargetName for the memory block BlockName for
211. nstruction where the non branch path has been traversed U A white box indicates a fully covered instruction Code Coverage Verification Commands The code coverage verification commands described in the Code Coverage Script Commands section provide the capability to verify both instruction and branch coverage percentages on both an individual file basis and a complete microcode build If the required coverage has not been achieved then a verification error message is generated and the count of script failures found in the configuration window is incremented Code Coverage Report Files Code coverage report files can be generated using the write_coverage_file filename Coverage script command described in the Code Coverage Script Commands section Code coverage report files can also be generated directly from the File menu by selecting the Coverage submenu This is described in the Files Menu section The top of the code coverage report file contains a title line a copyright declaration line and a time stamp line Following this generic information is a series of sections The first section provides coverage data on the entire microcode build Succeeding sections provide coverage information on each file used to create the microcode build Each section contains a number of lines that provide the following information The instruction line lists the total nunber of instructions Both regular and branch instructions are counted but entry ta
212. ntext 000 000 0 vS Current Time 007 718 4 uS Left Cursor 001 915 9 uS Delta Cursor 003 480 9 vS Right Cursor 005 396 8 uS The Active Waveform The active waveform is red whereas all others are black Use the lt up gt and lt down gt arrows on the keyboard to switch the active waveform The Left and Right Cursors The logic analyzer has two cursors a left cursor and a right cursor The left cursor is blue whereas the right cursor is green One of the two cursors is always selected and this selected cursor is displayed as a solid line Conversely the unselected cursor is displayed as a dashed line The concept of an active cursor is important because the active cursor is snapped to edges on the active waveform using the keyboard s left and right arrow keys To switch between the selected and unselected cursor hold the lt CTRL gt key while pressing either the left or right arrow keys on the keyboard 137 Grabbing an Out of View Cursor Occasionally the left or right cursor may be out of view as the left cursor is in the picture seen below The right cursor is at arrow 1 But the left cursor is out of view because the waveform is only displaying a quarter microsecond of waveform at around six microseconds but the left cursor is at 1 microsecond Therefore the left cursor is to the left of the visible area To bring the left cursor back into view click the left mouse button at the location indicated by arrow 2 1 TpuSim
213. o form a closed hand Drag the time closed hand over the Current Time field shown by arrow 3 Drop the time into the current time field by releasing the left mouse button The simulator will reset and execute to precisely 2 191 1 microseconds rv TpuSim Logic Analyzer uaRT_Rcv N Mouse 005 427 4 vS 008 000 Context 004 479 1 vS Current Time 007 651 6 vS Delta Cursor 000 936 0 uS Right Cursor 003 127 1 uS A similar method can be used to execute to a context time The context time is shown at arrow 4 above The context time is the time at which some context event occurs For instance in the trace window click on any stored event By clicking on the event the time at which that event occurred becomes the context time Similarly in the thread window click on a worst case thread and the time at which the first instruction of the worst case thread occurred becomes the context time This context time can then be dragged into the current time field causing the simulator to execute to that precise time View Waveform Selection The Logic Analyzer displays nodes from the pin transition trace buffer as a waveform Nodes are added to the display when they are selected from within the drop down list box located to the left of the waveform display panel The nodes that may be displayed include the TPU channel I O pins and the TCR2 pin as well as any user defined nodes User defined nodes are tho
214. o form a detection window and the state of this detection window closed opened is displayed eTPU Host Interface Window eTpul Host Interface INE E 0 x 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 18 F E D C BA 8 765 43 21 86 CFSR GE 00 66 66 66 66 66 66 66 66 0G 66 05 05 05 05 64 64 64 64 64 64 66 63 63 63 63 63 63 66 62 61 CRESS OS Se eS Se HI HI HI HI HI HI HI HI HI HI HI HI HI HI HI HI HI HI HI HI HSRR 6 6 6 6 6 6 68 86 6 6 6 6 6 6 6 8 6 6 6 6 6 6 8 8 6 6 6 6 6 6 86 8 FHM 66 66 66 OO 66 66 HO 66 66 66 OO OO HO OG 66 66 66 66 66 66 66 66 OO OO 66 OO 66 56 66 66 66 66 Entry S S S S Ss S 8 S S S S S 85 S 858 8 S CISR 6 6 6 6 6 6 6 86 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 1 CIER 6 6 6 6 6 6 6 8 6 6 6 6 6 6 6 86 6 6 6 6 6 6 6 86 6 6 6 6 6 6 6 86 CIOR 6 6 6 6 6 6 6 86 6 6 6 6 6 6 6 86 6 6 6 6 6 6 6 8B 6 6 6 6 6 6 6 1 CDTRSR 6 6 6 0 6 6B 6 6 6 6 6 6 6 86 6 6 6 6 6 6 6 86 6 6 6 6 6 6 6 8B CDTRER 6 68 6 6 6 6 6 6 6 6 6 6 6 6 86 6 6 6 6 6 6 6 86 6 6 6 6 6 6 6 86 CDTROSR 6 6 6 6 6 GB A 6 6 6 6 6 6 6 8 6 6 6 6 6 6 6 8 6 6 6 6 6 6 6 8B For each channel the following information is shown The Channel Function Select Register CFSR shows the eTPU Function the Channel Priority Register CPR shows the priority for that channel the Host Service Request Register HSRR shows the state of the service request The Function Mode FM shows the state of these two bits the
215. ommands file is reread its execution starts back at the first line This allows the user to modify and then rerun a series of script commands without exiting MtDt Only one primary script commands file may be active at atime Multiple ISR script commands files may be open at once but only a single ISR script commands can be associated with each TPU channel Note that each ISR script commands file can be associated with multiple TPU channels Debugging Capabilities in Script Command Windows These capabilities are available starting in version 3 20 Script commands file windows support breakpoints Similar to source code windows breakpoints can be set cleared enabled and 91 disabled See the Breakpoints Menu section for a complete explanation A goto line capability is supported within the script commands file windows Although this can be activated from the Run menu as described in the Run Menu section a more convenient method is to right click on the desired line Either method causes the target execution to continue until the desired script command is executed Note that if the active line in the script file is beyond the selected goto line the target is reset and then runs to the desired line A single step capability is also provided in script commands files See the Step Menu section for a detailed explanation Watches Window 32 MyBdm32 Watches OF x global data oO 2004318071 0x77777777 global_array 7 Oo 72 H packet
216. on Engine The CPU16 is sold on a number of Freescale microcontrollers including the HC16 series The CPU16 Simulation Engine can be used both in stand alone mode and in conjunction with other CPUs and peripherals including multiple CPU16s 169 FULL SYSTEM SIMULATION This section covers how an entire system consisting of multiple CPUs peripherals and models of the external system can be simulated Of special interest are MtDt build script files because these are used to create the targets and specify how they interact In many cases such as when using a TPU Stand Alone Simulator or a 683xx Hardware Debugger the standard build batch files are sufficient and little or no knowledge of MtDt build batch files is required But when implementing complex multiple target systems the detailed description of MtDt build batch files contained in this section is required Theory of Operation MtDt is capable of instantiating and simulating multiple targets allowing them to interact via shared memory while maintaining the correct synchronization and relative timing In addition a rich set of debugging capabilities normally associated with single target systems has been extended to this multiple target environment Each target loads and runs its own executable code image Each target can have primary and startup script commands files TPU targets can also have ISR files that are associated with and activated by specific interrupts and test vector f
217. or There is no limit to the number of wave commands that may be used in a test vector file The number of wave form generators is equal to the number of wave commands found in the test vector file wave lt GROUP gt lt STATE REPEAT gt lt STATE REPEAT lt gt REPEAT gt end The wave command causes the nodes of GROUP to be stimulated by the state and repeat count pairs STATE REPEAT Multiple states and repeat counts are allowed A special infinite repeat count generates an infinite repeat count This command may span multiple lines An end statement must terminate the command wave OUTPUTS OFF 5 DRIVE_A 1 DRIVE_B 2 3 OFF end The resulting wave form from this example is shown below The wave form begins with signal A and signal B being off for five master test vector clock periods Signal A is then driven for one period Then signal B is driven for two periods These three states constitute a loop which executes three times After the loop has executed three times the OFF state is driven forever Note that the NODE GROUP STATE and FREQUENCY commands are omitted from this example for simplification purposes 71 AJL JL A Bf S Test Vector Engine Waveform Example File ENGINE Vector AUTHOR Andrew M Klumpp ASH WARE DATE 950404 DESCRIPTION This generates the test vectors associated with a four cylinder car The four spark plugs fire in the order 1 3 2 4 For convenience an engine fre
218. osition fields the use of each port pin can be specified Each pin can be specified as a generic I O or assigned to the QSM In addition both the data direction and register value can be specified QSM QSPI Window Availability 683xx Hardware Debugger 116 32 MyBdm32 QSM QSPI spcre GREE MSTR wong BITS CPOL CPHA SPBR SPCR1 64604 SPE DSCKL SPCR2 6666 SPCR3 6666 QSPI RAM 2 2 2 2 22 2 22 22 22222222222225522225225220220522222222222222252 22 6 1 Receive 6060 81E7 Transmit BBF8 7BFB Command 7F EF CONT 7 PORT DEAS BITSE 6 BITS BITS DT 5 DTL DTL DSCK 4 DSCK CK 2 PCS 3 HI HI PCS 2 HI HI PCS 1 HI HI PCS 6 HI HI 2 7FFB 1A8E 42 PORT BITS std CK 2 lo lo HI lo QSPI is a slave device Outputs have normal MOS drivers Bits field is 6 resulting in 16 The inactive state value of the SCK pin is lo Data CHANGED SPBR is 64 for a clock period of 660 601 06 microseconds QSPI is a slave device Delay from chip select assertion to leading edge of SCK is equal to DSCKL field 64 system clocks for a delay of 666 606 5 micro seconds for each channel with CMD RAM s DSCK bit asserted Delay from chip select negation to next operation is equal to DTL field 64 multipied by 32 system clocks on SCK s leading edge and captured on the trailing edge bits per transfer for each channel with CHD RAH s DT bit asserted QSPI interrupts are disabled Wraparound mode is disabled
219. ot taken The verify_all_coverage and verify_all_coverage_ex are similar to the verify_file_coverage commands except these commands focus on the entire build rather than specific source code modules As such they are less useful as a successful testing strategy will focus on specific modules rather than on the entire build Note that this capability is also available directly from the file menu wait_time 100 verify_file_coverage toggle uc 92 5 66 5 verify_all_coverage 33 3 47 5 write_coverage_file record Coverage The code in this example waits 100 microseconds and then verifies that at least 92 5 percent of the instructions associated with file toggle uc have been executed and 66 5 percent of the possible branch paths associated with file toggle uc have been traversed In addition the example verifies that at least 33 3 percent of all instructions have been executed and that 47 5 percent of all branch paths have been traversed A complete report of instruction and branch coverage is written to file record Neues Inferred Event Vector Coverage In eTPU applications it is often difficult to get complete 100 event vector coverage There are two situations in difficulties may be encountered The first situation would be a valid and expected thread that is difficult to reproduce in a simulation environment For example when measuring the time at which a rising edge occurs it may be difficult to generate a test ca
220. ounter is clocked on a rising edge With both control bits at one the TCR2 counter is clocked on both the rising and falling edges thus effectively doubling the counter frequency With T2CSL at 0 and T2CG at 1 the clock source is the gated system clock With T2CSL at 1 and T2CG at 0 the TCR2 counter is clocked on the falling edge 50 write_tcr2_prescaler Val This command writes the TCR2 prescaler Valid Val values are 0 1 2 or 3 A O causes a division by 1 no prescaler A 1 causes a division by 2 A 2 causes a division by 4 A 3 causes a division by 8 write_t2cg 0 write_t2csl 0 Available in TPU2 mode only write_tcr2_prescaler 3 The commands in this example set the external pin to be the TCR2 counter clock source and set the TCR2 prescaler to divide by 8 The TCR2 counter is setup to be clocked on the rising edge These commands together set the TCR2 counter to increment on every eighth rising edge of the signal at the TCR2 input pin TPU3 Specific Script Commands write_epscke Val This command writes the TCR1 enhanced prescaler enable bit Only 0 and 1 ae allowed values This control bit determines whether the TPU3 s new and enhanced prescaler is used or the standard prescaler is used With the enhanced prescaler the resolution of the clock period is controllable in 3 increments of the longest clock period write_epsckv Val This command writes the TCR1 enhanced prescaler value Only values between 1 and 31 are
221. ows and columns Each row displays the six or eight parameter words each word is 16 bits wide corresponding to a particular channel Across each row are the six or eight parameters belonging to that channel In the TPU1 design Freescale apparently ran out of room to provide the full eight parameters for all 16 channels In fact of the 16 channels the lower 14 contain six parameters while only the final two channels contain the full complement of eight parameters While MtDt is in TPU1 mode the un implemented parameter RAM locations are not displayed In TPU2 and TPU3 and in MtDt while in TPU2 and TPU3 mode all parameter locations are implemented While in TPU2 and TPU3 mode MtDt displays all parameter locations How do the TPU and MtDt deal with accesses to the missing locations in TPU1 mode It behooves the TPU microcoder to assume that new TPU versions will most likely have a full complement of parameter RAM For both the TPU and MtDt writes to these locations are ignored while the data returned fromreads is always zero During reset it has been observed that the parameter RAM of the actual TPU remains unchanged as long as power is not lost though this behavior is apparently not documented MtDt allows the user to specify whether the parameter RAM is cleared to all zeros or remains unchanged after a reset This is specified in the Reset Options dialog box 683xx Hardware Debugger Configuration Window Availability 683xx Hardware Debu
222. ox PTA DemoInit in platformDemo c at line 290 address Oxb94 frame OxffcB 4 platformDemoInit in platformDemo c at line 122 address Oxa4a frame Oxffd6 ash_main in main c at line 56 address Ox4d2 frame 6xfffO E ay The Call Stack window displays the function source code file name and line number address and stack frame pointer associated with stacked functions as shown above Call Stack Local Variables and Source Window Automation It is often not sufficient to simply view the functions on the call stack The Call Stack window works in conjunction with the source code and the local variable window to show both the source code line and the stacked local variables associated with any stacked function For instance the second line of the above Call Stack has been selected This line is associated with the PTA_Demolnit function When you move the cursor to this line the source code file shown below automatically pops into view and the source code line scrolls into view and is highlighted with yellow pHost source platformbemoc T E al void PTA_DemoInit U32 tpuBaseAddr U16 vecBase lt const int PTAFuncNum 6xf write chan Fee ES NEES write_chan_func tpuBaseAddr 1 PTAFuncNum write chan heerftouRaseAddr _1_21 Upon selection of the Call Stack window s second line the Local Variables window is also affected as shown below The highlighted function PTA_Demolnit had several local variable
223. ple interrupts Similarities to the C Programming Language The script commands files are intended to be a subset of the C programming language In fact with very little modification these files will compile under C The Script2C exe utility is included 22 for making the required conversions to compile script files in C The Primary Script Commands File MtDt automatically executes a primary script commands file if one is open A new or alternate script commands file must be opened before it is available to MtDt for execution The desired script commands file is opened via the Files menu by selecting the Scripts Open submenu and providing the appropriate responses in the Open Primary Script File dialog box MtDt displays the open or active script commands file in the target s configuration window Only one primary script commands file may be active at one time Help is available for this window when it is active and can be accessed by depressing the lt F1 gt function key ISR Script Commands Files Currently the ability to associate a script commands file with an interrupt is limited to the eTPU and TPU simulation targets Script commands files can be associated with interrupts When the interrupt associated with a particular eTPU TPU channel becomes asserted the ISR script commands file associated with that channel gets executed In the eTPU ISR script commands files can be associated with channel and data interrupts as well as wi
224. point is encountered in any target eTPU Stand Alone Simulator This product is a single target version that uses only a single instance of our eTPU simulation engine Because it is a stand alone product the user must use script commands files to act as the host and test vector files to act as the external system TPU Stand Alone Simulator This product is a single target version that uses only a single instance of our TPU Simulation engine Because it is a stand alone product the user must use script commands files to act as the host and TPU test vector files to act as the external system This is the original ASH WARE product TPU Standard Mask Simulator Our TPU Standard Mask Simulator allows you to develop your CPU code used in conjunction with any standard Freescale TPU microcode Currently ASH WARE supports the following three TPU Microcode builds MASK A MASKG 165 2 MASK MPC5xx This product supports all the capabilities of our system simulator products with the single exception that you cannot load microcode that you have modified Instead the only TPU microcode that can be loaded is the one of the aforementioned standard TPU microcode masks Although you can tailor your configuration to any specific microcontroller mapping the following three configurations are the defaults The default configurations are usually sufficient and intricacies of custom configuration generation need not be explored MASK A 683xx with o
225. points Menu 159 Activate Menu 160 View Menu 160 Window Menu 160 Options Menu 161 Help Menu 162 HOT KEYS TOOLBAR AND STATUS INDICATORS 163 SUPPORTED TARGETS AND AVAILABLE PRODUCTS 164 eTPU CPU System Simulator 164 TPU CPU32 System Simulator 165 TPU CPU16 System Simulator 165 eTPU Stand Alone Simulator 165 TPU Stand Alone Simulator 165 TPU Standard Mask Simulator 165 CPU32 Stand Alone Simulator 166 CPU16 Stand Alone Simulator 166 683xx Hardware Debugger 166 eTPU Simulation Engine 166 TPU Simulation Engine 166 The Time Processor Unit TPU 167 Support for TPU3 168 CPU32 Simulation Engine 169 CPU32 Hardware across a BDM Port 169 CPU16 Simulation Engine 169 FULL SYSTEM SIMULATION 170 Theory of Operation 170 Debugging Capabilities 170 Building the MtDt Environment 171 MtDt Simulated Memory 171 Memory Block Address Spaces Memory Block Size Memory Block Access Control Read Write Control Clocks per Access Control Address Fault Control Bus Fault Control Sharing Memory Shared Memory Address Space Transformation Shared Memory Address Offset Shared Memory Timing A Complete Shared Memory Example Simulating Mirrored Memory Computer Memory Considerations 171 172 173 174 174 175 175 175 175 176 177 177 177 179 180 FOREWORD This User Manual is a superset of the On line Help program The On line Help program is invoked within the IDE in various ways such as when the lt FI gt function key is pressed The dif
226. primary script commands file because the primary script commands file does not have an eTPU TPU channel context Use of timing commands within an ISR script commands file is discouraged This would be analogous to putting delays in a CPU s ISR routine Such a delay would have a detrimental effect on CPU latency and in the case of the eTPU TPU Simulator would be considered somewhat poor form 23 Ks eTPU TPU channels need not have an association with an ISR script commands file There is a automatic define that can be used to determine which channel the script command is associated with This script command appears as follows define _ASH_WARE_ lt TargetName gt _ISR_ X Where TargetName is the name of the target generally TpuSim eTPU1 or eTPU2 and X is the number of the channel associated with the executing script The following shows a couple examples of its use ifdef ASH _WARE_TPUSIM_ISR_ print this is an ISR script running on a target named TPUSIM else print this is not both an ISR running on TPUSIM endif write_par_ram _ASH_WARE_TPUSIM_ISR_ 2 0x41 write_par_ram _ASH_WARE_TPUSIM_ISR_ 3 8 clear_this_cisr Startup Script Commands Files Startup scripts provide the capability to get the target into a known state following an MtDt controlled reset It is particularly useful for the case in which MtDt is configured to load an executable image when MtDt is launched In the 683xx Hardware Debugger fo
227. pt command DS OUTPUT p GATE INPUT p 84 INTEGRATED TIMERS Integrated timers measure the amount of time that code takes to execute This capability is available for all simulated targets as well as for hardware targets outfitted with the requisite support hardware Integrated timers work with a combination of a special Timers window as well as the source code windows Specific timer stop and timer start addresses are specified from within the source code windows Completed timing measurements are viewable within the Timers window The timer number within a green circle on the far left side of the source code window identifies the start address Similarly the timer number within a red circle on the far left side of the window identifies the stop address It is possible for the same line of source code to contain multiple timer start and stop addresses In this case only a single circle timer number will be displayed though all timers still continue to function MtDt supports 16 timers Each timer has the following states armed started finished overrun and disabled The state of each timer is displayed in the Timers window Each timer can be armed in several ways Specification of a new start or stop address within a source code window automatically arms the timer The timer can also be armed from within the timer window by clicking on the state field or placing the cursor in the state field and typing the letter
228. pt files In general the enumerated data types are defined for each specific target or script file application enum TARGET_TYPE TPU_SIM ETPU_SIM eTPU TPU Targets SIM32 BDM32 CPU32 targets END OF PARTIAL LISTING 5 Note that in C it would be possible to pass an integer as the first argument and at worst a warning would be generated In fact in C even the warning could be avoided by casting the integer as the proper enumerated data type This is not possible in a script file because of tighter checking and because casting is not supported Integer Data Types in Script Commands Files In order to maximize load time checking script command files support a large number of integer data types This allows constant overflow warnings to be identified at load time rather than at run time In addition since the scripting language supports a variety of CPUs with different fundamental data sizes the script command data types are designed to be target independent This allows use of the same script files on any target without the possibility of data type errors related to different data sizes 27 The following is a list of the supported data types along with the minimum and maximum value UL valid range is 0 to 1 U2 valid range is 0 to 3 z UB valid range is 0 to 7 U4 valid range is 0 to 15 USA valid range is 0 to 16 2 USB valid range is 0 to 31 U8 valid range is 0 to OxFF 2 U16 valid range is 0 to OXFFFF
229. quency is chosen such that one degree corresponds to 10 microseconds 10 microseconds will be written as 10us A test vector frequency is chosen such that one degree corresponds to one time step The test vector frequency is MtDt s internal test vector timebase Within each engine revolution two spark plugs fire ASSIGN NAMES TO PINS Assign the descriptive names to the synch and spark plug signals node Synch ch3 node Spark ch8 node Spark2 chl1 node Spark3 ch6 node Spark4 ch4 ASSOCIATE PINS WITH A GROUP Make a group named SYNCH with only the SYNCH TPU channel as a member group SYNCH Synch Make a group named SPARKS that consists of the four spark plug signals group SPARKS Spark4 Spark3 Spark2 Spark1 DEFINE THE SYNCH STATES The synch signal can be either pulsing 1 or waiting 0 state synch_pulse 1 state synch_wait 0 DEFINE THE SPARK FIRE STATES There are five states _ There is one state for each of the four spark plugs firing There is one state for none of the spark plugs firing state FIRE4 1000 state FIRE3 0100 state FIRE2 0010 state FIRE 0001 state NO_FIRE 0000 SET THE TEST VECTOR BASE FREQUENCY In order to have a convenient relationship between time and degrees an engine revolution is made to be 3600us such that one degree corresponds 72 to 10us Thus a convenient test vector time step period of 10us is chosen frequency 1 period 1 10us
230. r commands are available Node Group State Frequency 2 Wave In addition there is an example of the waveforms generated for an automobile engine monitor system Comments Test vector files may contain the object oriented C style double backslash comments A comment field is started with two sequential backslash characters All text starting from the backslashes and continuing to the end of the line is interpreted as comment In the following example the first line is a comment while the second is an acceptable test vector command This is a comment define UART CH5 Test Vector Node Command node lt Name gt lt Node gt The node commands assign the user defined name Name to a node Node Note that depending on the microcontroller the input and output from each channel may or may not be brought to external pins Please refer to the Freescale literature for the specific microcontroller being used Standard eTPU Nodes ch0 in Channel 0 s input pin ch0 out Channel 0 s output pin chl in Channel 1 s input pin chl out Channel 0 s output pin ch31 in Channel 31 s input pin ch31 out Channel 31 s output pin 69 terclk eTPU external clock input pin In the example shown below the name A429Rcv is assigned to the eTPU s channel 5 input pin node A429Rcy ch4 in Standard TPU Nodes CHO Channel 0 s I O pin CH1 Channel 1 s I O pin CH15 Channel 15 s I O pin TCR2 TPU Counter 2
231. r instance startup scripts can be used to configure the SIM registers so that the executable image can be immediately loaded when MtDt is launched Each target can have an associated startup script Make sure the desired target is active From the Files menu select the Scripts Startup submenu A report file is generated each time the startup script is executed This file has the same name as the startup script its extension is report There are some restrictions to startup scripts These are listed below No windows are supported Flow control such as breakpoints and single step is not supported Certain script commands are not supported Restricted commands are noted as such in the reference section The MtDt Build Script Commands File MtDt supports both debugging and simulation of a variety of targets Since the single MtDt application can both simulate and debug a variety of simulation and hardware targets how does MtDt know what to do Build batch files provide the instructions that MtDt requires to create and glue together the various copies of hardware and simulation targets Although the user is encouraged to modify copies of these files when required in many cases the standard build batch files loaded during MtDt installation will suffice Typical build script files might instantiate a CPU32 and a TPU3 then instantiate RAM and ROM for the CPU32 and then cause the TPU s memory to reside in the CPU s address space
232. r of source code files associated with the executable image that get loaded MtDt needs to be able to find these files This dialog box allows specification of source code directories to be searched when searching for these source code files The search locations can be specified for each individual target and for all targets globally Specifying global search options is useful in situations in which multiple targets are using the same directories for their library files Add This button inserts a new directory into the search list Modify This button modifies a previously entered search location Delete This button removes a location from the search list Cut This button removes the currently selected search location from the search list and places it into the paste buffer Copy This button adds the currently selected search location to the paste buffer without removing it from the search list Copy This button creates a new search location using the paste buffer 149 Move Up This button moves the currently selected search location higher in the search list such that MtDt searches this location earlier Move Down This button moves the currently selected search location lower in the search list such that MtDt searches this location earlier Reset Options Dialog Box The Reset Options dialog box is accessed from the Options menu by selecting the Reset submenu It specifies the actions taken when either the Reset subm
233. re lost OK Button This saves edits makes the currently selected auto build batch file the default and closes the Auto Build Batch File Options dialog box OK Build Button This saves edits makes the currently selected auto build batch file the default and closes the Auto Build Batch File Options dialog box In addition a build is performed Cancel Button This closes the Auto Build Batch File Options dialog box Edits are not saved The default auto build file is not set to be active for future builds Instead the default auto build file reverts back to whatever the default was before the Auto Build Batch File Options dialog box was opened Build Button This saves edits and performs an auto build The Auto Build Batch File Options dialog box is not closed 144 Help Button This accesses this help menu Change File Button This allows the user to select a new auto build batch file Beside this button is listed the name of the currently selected auto build file Goto Time Dialog Box The Goto Time Dialog Box is opened via the Run menu by selecting the Goto Time submenu It provides the capability to execute MtDt until a user specified time There are two types of Goto time options one of which must be selected Goto Until Time This sets MtDt to go to an absolute simulation time The simulation time is initially set to zero The simulation time is reset to zero via the Run menu by selecting the Reset submenu
234. rencing the CPU32 registers These enumerated data types are used in commands that reference the CPU32 registers such as the register write commands that are defined in the Write Register Script Commands section The following enumeration provides the mechanism for referencing the CPU32 s 8 bit registers enum REGISTERS_US8 REG_CCR Condition Code Register 5 The following enumeration provides the mechanism for referencing the CPU32 s 16 bit registers enum REGISTERS_U16 REG_SR Status Register 5 The following enumeration provides the mechanism for referencing the CPU32 s 32 bit registers enum REGISTERS_U32 REG_PC REG_VBR Program Counter Vector Base Register REG_USP REG_SSP User and Supervisor Stack Pointers REG_SFC REG_DFC Alternate Function Code Registers REG_DO REG_D1 REG_D2 REG_D3 Data register DO to D3 REG_D4 REG_D5 REG_D6 REG_D7 Data register D4 to D7 REG_AO REG_A1 REG_A2 REG_A3 Addr register AO to A3 REG_A4 REG_A5 REG_A6 REG_A7 Addr register A4 to A7 64 CPU16 Register Enumerated Data Types The CPU16 register enumerated data types provide the mechanisms for referencing the CPU16 registers These enumerated data types are used in commands that reference the CPU16 registers such as the register write commands that are defined in the Write Register Script Commands section The following enumeration provides the mechanism for referencing the CPU16 s 4 bit registers enum R
235. ript DUMP_FILE_OPTIONS Enumerated Data Type Save Trace File Enumerated Data Types Base Time Enumerated Data Type Script TARGET_TYPE Enumerated Data Type Build Script ADDR_SPACE Enumerated Data Type Build Script READ_WRITE Enumerated Data Type Register Enumerated Data Type eTPU Register Enumerated Data Types TPU Register Enumerated Data Types CPU32 Register Enumerated Data Types CPU 16 Register Enumerated Data Types TRACE BUFFER AND FILES Overview Generating Viewable Files Generating Parseable Files Parsing the Trace File Trace Buffer Size Considerations TEST VECTOR FILES Overview Test Vector Generation Functional Model Command Reference Comments Test Vector Node Command Test Vector Group Command Test Vector State Command Master Test Vector Clock Frequency Command Test Vector Wave Command Test Vector Engine Waveform Example FUNCTIONAL VERIFICATION Overview A Full Life Cycle Verification Perspective Data Flow Verification Pin Transition Behavior Verification Pin Transition Buffers Code Coverage Analysis Code Coverage Visual Interface Code Coverage Verification Commands Code Coverage Report Files Regression Testing Bev Command Line Parameters Test Termination Regression Test Example Ney Cumulative Logged Regression Testing File Location Considerations EXTERNAL LOGIC SIMULATION Example 1 Driving the TCR2 Pin Example 2 Multi Drop Communications INTEGRATED TIMERS Virtual Timers in
236. rities to the C Programming Language The Primary Script Commands File ISR Script Commands Files Startup Script Commands Files The MtDt Build Script Commands File MtDt Build Script Commands File Naming Conventions Script Commands File Format and Features Script Commands Format Multiple Target Scripts Directives The define directive The include lt FileName h gt directive The ifdef ifndef else endif directives Enumerated Data Types in Script Commands Files Integer Data Types in Script Commands Files Referenced Memory in Script Commands Files Assignments in Script Commands Files Operators and Expressions in Script Commands Files Comments Decimal Hexadecimal and Floating Point Notation String Notation Script Commands Groupings All ao Types Script Commands Ney eTPU TPU Script Commands eTPU Script Commands TPU Script Commands Build Script Commands Clock Control Script Commands Timing Script Commands Modify Memory Script Commands Verify Memory Script Commands Write Register Script Commands Verify Register Script Commands Write Symbol Value Script Command Verify Symbol Value Script Commands System Script Commands File Script Commands Trace Script Commands Ney Code Coverage Script Commands RAM Test Script Commands eTPU TPU Channel Function Select Register Script Commands eTPU TPU Channel Priority Register Script Commands eTPU TPU Pin Control and Verification Script Commands eTPU Topics TPU Topics
237. ritten to the current working directory which is to say in the directory from which the tests are launched This exception to the normal directory locations is used so that multiple project files can exist in different sub directories and the test results can all be logged to the same log file 82 EXTERNAL LOGIC SIMULATION External logic simulation is TPU centric since it may be used solely on the I O pins of TPU targets and only on an intra TPU basis Future versions of the software will extend this capability to work between any addressable bits in any target s address space Boolean logic that is external to the TPU can be incorporated in a simulation The logic is simulated with a single pass per step each step is two CPU clocks Logic is placed via the script commands files using external logic commands There are a number of limitations to the Boolean logic There are only two logic states one and zero The logic is simulated with a single pass per step each step is two CPU clocks All output states are calculated before they are written and therefore all calculations are based on the pre calculated states Thus it takes multiple passes for state changes to ripple through sequentially connected logic 4 All Boolean logic inputs and outputs must be TPU channel I O pins Behavior of connected Boolean logic outputs and TPU channel pins configured as outputs is undefined Behavior of pins connected to Boolean logic ou
238. rkshop In this case you will also be prompted to indicate whether you would like to remove visibility of all windows belonging to the removed target from the affected workshops On Toolbar Checking this option causes a button to appear on the toolbar that automatically switches to that workshop when depressed Workshop Name This is the name of the workshop You can either type in a new name using the keyboard alternatively a button to the left of this edit control allows you to assign the associated target s name to the workshop Primary Association This is the target that is associated with the workshop A dropdown list allows selection of any target 147 Message Options Dialog Box The Message Options dialog box provides the capability to disable the display of various messages These messages warn the users in a variety of situations such as a failed script verification command failure or when suspicious code is encountered When there is a check next to the described message a message is generated when the described situation occurs To disable the message remove the check The user might wish to execute through a failing or suspicious section of code without having to acknowledge each message and would therefore disable the associated message All Targets Messages Behavior Verification Failure Behavior verification failure messages are generated when the current execution does not match that from a previously recorded be
239. rs have been particularly rewarding with the development of the Enhanced Time Processing Unit eTPU and the emergence of Los Tres Amigos Mike Walter and Me You two have been a particularly dear part of my experience as your roles have extended well beyond the purely technical Thank you To the entire team here at ASH WARE including Keith Michael and Tony who make to happen to Barbara who makes us look good to Margaret who makes us sound good and hopefully profitable and to Amy who makes it clear Thank you users too numerous to mention but certainly Stan and Josef stand out from the rest Thank you Freescale and Metrowerks and Richard the great idea man Sharon Munir Robert Dave Clint Samantha and all the others too numerous to be mentioned individually but do not be offended if you are not because yes I do mean you too Thank you John the great brain behind our products our best and most useful features are always yours Back at Allied when you first became involved with the original TPU you disappeared and did not ask me for the help which I offered and which chagrined me at first since nobody can understand the TPU without benefit of the course or the book or a colleague But of course YOU could And thank you Suzanne who stands by me Andy Klumpp Technical Director ASH WARE Inc 11 ON LINE HELP CONTENTS The following help topics are available Overview Software Deployment Upgrades
240. s 896 660 nS Addr HABA There are two versions of the eTPU Channel window The active channel version displays information on the active channel or previously active channel if none is currently active while the fixed channel version displays information on a particular channel The following information is displayed Right click the mouse when inside this window to specify or change the window flavor The value of the 24 bit Match and Capture registers for both action units are displayed The global counter either TCR or TCR2 that is used for the match comparison and also for the capture are displayed The match comparators condition either equals only or greater than and equals is displayed The states of Match Recognition Latch Enable MRLE Match Recognition Latch MRL and Transition Detection Latch TDL are displayed These are the latches in the channel hardware and may not necessarily match the value in the execution unit window since those in the execution unit window are sampled at the beginning of each thread Whether or not matches and transitions result in a service request is displayed The LSR field shows if there is a pending link into this channel During a thread matches for the channel being serviced can be enabled or disabled and this is displayed The input and output pin states are displayed as is the state of the output buffer Although the simulator tracks the state of this buffer there is no other affect in t
241. s Counter Submodule Window CTM4 Double Action Submodule Window CTM4 Pulse Width Modulation Submodule Window CTM6 Single Action Submodule Window CTM6 Double Action Submodule Modes Window CTM6 Double Action Submodule Bits Window Real Time Clock Window Parallel Port I O Submodule Window TouCAN Main Window TouCAN Buffers Window QADC Main Window QADC Ports Window QADC Channels Window 683xx ASH WARE Hardware Window CPU32 Simulator Configuration Window CPU32 Simulator Busses Window CPU32 Simulator Interrupt Window CPU32 Registers Window CPU32 Disassembly Dump Window CPU 16 Simulator Configuration Window CPU16 Register Window CPU16 Disassembly Dump Window 102 103 104 105 105 106 108 108 109 109 110 112 112 113 114 115 116 116 116 117 118 118 119 119 119 119 120 120 121 121 122 122 123 123 123 124 124 124 125 125 126 126 126 127 128 128 129 130 130 131 131 132 132 132 133 133 Unsupported Window 134 LOGIC ANALYZER 135 Overview 135 Executing to a Precise Time 135 View Waveform Selection 136 The Active Waveform 137 The Left and Right Cursors 137 Left Right and Delta Cursor Time Indicators 138 Mouse Functionality 138 The Vertical Yellow Context Time Cursor 139 Context Time Indicator 139 Scroll Bars 139 Waveform Boundary Time Indicators 140 Buffer Data Start Indicator 140 Current Time Indicator 140 Auto Scroll the Waveform Display as the Target Executes 140 B
242. s parameter 5 is 3500 hex verify_ram_word 0xa 5 0x3500 Pin Transition Behavior Verification Pin transition behavior verification is one of the verification capabilities for which an overview is given in the Functional Verification chapter Pin transition behavior verification capabilities include the ability to save recorded pin transition behavior to pin transition behavior bv files the ability to load saved pin transition behavior files into MtDt and the ability to verify that the most current pin 76 transition behavior matches the saved behavior From a behavioral model perspective these capabilities correlate to the ability to create behavioral models and the ability to compare source microcode against these behavioral models The emphasis in MtDt is on the automation of these modeling capabilities through script commands although the capabilities are also available directly from the menus Pin Transition Buffers There are two pin transition storage buffers in MtDt as shown in the following diagram Loaded as Simulator Runs Read from File Running Buffer Master Buffer of Recorded Pin Compare of Pin Transition Transition Behavior gt Behavior Saved to File The running buffer is filled as MtDt runs Whenever a pin transition occurs information regarding this transition is stored in this buffer This buffer can then be saved by selecting the Behavior Verification Save submenu from the File menu The master
243. s that were stored on the stack The values of these local variables are automatically displayed in the Local Variables window J Host Local ariable Window Automatic Tracking lol x tpuBase ddr 776704 Oxfffe 16 vecBase 64 6x46 PTAFuncNum 15 Oxf si w Thread Window This window has a number of user selectable views and options The window shown above has been configured to track all instances of the function ARINC_RX Since multiple channels can 94 run this particular function the data shown by this window is an accumulation of all the channels that have been assigned this function 5 x THREAD STEPS Addr Cov Cnt We Tot WC Time 6 62DC 1 1 2 18 36 366 nS INITIALIZE 1 G2FC 1 4 2 2 4 646 NS RE_INIT_INTERRUPT 2 6304 1 4 216 25 4365 566 nS RECEIVED_DATA_BIT_6 23 3 0368 1 4 72 23 1530 466 NS RECEIVED_DATA_BIT_24_31 4 O3E6 174 18 27 360 546 nS VALID_GAP_AND_DATA 5 0478 1 4 1 8 8 160 nS VALID_GAP_NO_DATA 6 6498 6 2 8 8 T00 MANY BITS FAULT Z G4B4 6 2 8 8 BIT DETECTED_IN_GAP_HUN 8 B4E4 68 4 8 8 LINE_WENT_IDLE_FAULT 9 65606 6 3 8 8 INVALID_THREAD_FAULT Kies a TPU and eTPU code executes in response to events This event response code is known as a thread Individual threads are assigned to each event and event combination A key performance index of your code is the amount of time each thread takes to execute Therefore this thread window is an
244. s the Workshop Options dialog box IDE Options Dialog Box The following describes the IDE Options dialog box All Targets Settings The following settings are for all targets Change the Application Wide Font Changes the fonts used by all the windows Update Windows While Target is Running This specifies whether the windows are continually updated as target runs The window update generally takes well under 1 of the application s CPU time so this option is generally selected But in certain cases deselection of this option can improve performance View Toolbar This specifies whether the toolbar and its associated buttons are visible The toolbar is the gray area located at the top of MtDt s application window View Status bar This specifies whether the status bar and its associated indicators are visible The status bar is the gray area located at the bottom of MtDt s application window Pop to Halted Target s Workshop Each target is generally assigned to a workshop In a multiple target environment when a target halts the workshop associated with the target that caused the system to halt This should generally be left selected Auto Open Window for File of Active Target s Program Counter When Target Halts When this is selected if the target halts the source code file corresponding to the program counter of the active target is closed it will automatically be opened In addition the current line is 146 automatically
245. s the following relative path has been established ControlLaws Now assume that file Spark C is referenced from the build file ACOUT Where would the MtDt search for this file The following location would be searched first because this is where the main build file ALOUT is located C MainBuild TopLevel If file Spark C were not located at the above location then the following bdcation would be searched This location is established by using the location of the main build file as the starting location for the ControlLaws relative path C MainBuild ControlLaws Supported Compilers and Assemblers We will be adding support for compilers and assemblers based on customer demand A list of these can be found on our Web site 21 SCRIPT COMMANDS FILES Overview Script commands files provide a number of important capabilities to the user In some cases script commands files provide a mechanism whereby actions available within the GUI can be automated In other cases they are used by MtDt to build a full system out of various targets They also can be used in place of missing but required pieces of a complete system such as in a TPU Stand Alone Simulator project in which script commands files take the place of the host CPU We have created a single universal scripting language rather than a distinct scripting language for each application and target The basic program construction is used for each Only the predefined symbol tab
246. scussed later Shared Memory Address Space Transformation No assumptions should be made about address spaces between or among dissimilar targets In other words the code space of a CPU32 may not map to the code space of memory shared with a TPU For memory docks between dissimilar target types it is critical to fully specify all address spaces from the docking memory block Due to the lack of symmetry this is not true for the dockee The following script command should be used to fully define all docked address spaces between dissimilar targets When docking a CPU to a TPU the following address space transformation such as that shown in the following figure is often required TPU PINS Space All Modeling CPU Spaces Other TPU Spaces FFFFFFFF FEFEFEFE 0 0 The following build script commands generate the address space transformations shown in the above figure If the modeling CPU does a read from its address C0000 hexadecimal the read will actually access the shared memory with the TPU in its PINS space Me set_block_dock_space ModelingCpu TpuPinsDock ALL_SPACES RW_ALL TPU_PINS_SPACE I a In this example all address spaces from a docked block of a modeling CPU are set to the TPU s PINS address space This is an eight to one transformation in that an access in any of the CPU s address spaces becomes an access to the TPU s PINS space For example if the CPU performs a data read within this block the value of the TPU s chan
247. se defined within Test Vector Files The waveform display panel may not be large enough to display all the desired nodes The display can be scrolled vertically using the vertical scroll bar Ne Viewing Thread Activity Nodes eTPU and TPU Only Thread activity can be viewed in the logic analyzer window as shown below There are eight user configured thread nodes Each of these thread nodes can display the thread activity for one or more channels See the Logic Analyzer Dialog box section for more information on configuring thread nodes 136 uaRT_Rcv v eama OFF X I Avto Scroll E l gt E Eas 001 765 0 uS Mouse 005 522 8 uS Data Start 000 000 0 v Context 000 000 0 vS Current Time 005 437 2 vS Set Left Cursor 001 821 9 uS Delta Cursor 003 643 9uS Right Cursor 005 465 8 uS Ney Viewing Channel Nodes eTPU and TPU Only Several eTPU and TPU channel nodes can be viewed in the logic analyzer as shown below These include the Host Service Request HSR Link Service Request LSR Match Recognition Latch output and enable MRL and MRLE and Transition Detection Latch TDL Only the nodes from a single channel can be stored and viewed at a time The channel for which the nodes will be stored is defined in the Logic Analyzer Dialog box 7 TpuSim Logic Analyzer BEE uaRT_RcV z fuarTacvta E UART_RCV Meie Ga 001 861 5 uS Mouse 005 451 2 uS Data Start 000 000 0 vS Co
248. se for when the input pin is a zero because a thread handler will normally execute immediately such that the pin is still high But an event vector handling the case of a rising edge and a low pin is valid For instance a rising edge followed by a falling edge could occur before a thread executing in another channel completes Now the thread handling this rising edge executes with a low pin state It is therefore important to test this case but how The solution to achieving event vector coverage for this case is to be clever in designing a test For example you might inject two very short pulses into two channels running the same function The channels will be serviced sequentially so if you keep the pulse width shorter than the thread length than the second thread will execute with the input pin low The second situation in which it may be difficult to achieve complete event vector coverage is when there are multiple event vectors that handle an invalid cases For instance all functions must handle links even when a link is not part of the functions normal operation Such a link could occur if there was a bug in another function Since there are number of such invalid situations the are typically grouped As such it may be justified to bundle these together using the following script command This command allows coverage of a single event vector to count as coverage for other inferred event vectors bere infer_entry_coverage FuncNum FromEn
249. sible to enable trace settings in one target and disable these same settings in another target The target on which the Trace Options Dialog Box acts is listed at the top of the dialog box This 152 corresponds with either the active target at the time that the dialog box is opened or the target associated with the active window Local Variable Options Dialog Box It is important to note that the Local Variables window automatically tracks the current function When the target transitions from running to stopped the active function s local variables are automatically displayed But in addition when you scroll through the Call Stack window the Local Variable window automatically displays the stacked local variables associated with selected line in the Call Stack window This automatic behavior is generally quite useful but in certain cases it can get in the way By locking the local variable window you are able to disable this automation Lock the local variables from lt functionName gt at stack frame lt frameAddress gt When this is checked the Local Variable window displays a particular function s local variables The normally automatic tracking of the current function s local variables is disabled For example if you are parsing through text a stacked function may point to the beginning of a buffer that is being traversed by called functions Use of this option would allow you to lock onto display of the calling function s local v
250. size ul 13 Oxd ei ul 13 Oxd register DZ ul al al mat i The Watches window displays symbolic data specified by the user Both local and global variables can be displayed within this window See the Local Variable window to automatically display local variables The watches window consists of a series of lines of text used to display user specified watches Watches can be removed moved up or moved down New watches can also be inserted before any current watch or at the bottom of the list The Insert Watch function accesses the Insert Watch dialog box which allows you to select and or modify previously defined watches These functions are accessed from the Options Menu by selecting an action listed in the Watch submenu An equivalent of the Watch submenu is also accessible by right clicking the mouse from within a Watches window The Watches window has a user specified symbol on the far left This is the symbol whose resolved value the user wishes to be displayed To the right of the user defined symbol is an options button This button accesses the Watch Options dialog box In future versions of this software this dialog box will allow individual settings for the watch to be specified To the right of the options button is a vertical separator bar You can drag the vertical separator bar left or right using the cursor To the right of the vertical separator bar is the symbol resolution field If MtDt can resolve a value from the user spec
251. specific individual products List of Available System Simulators The currently available products are listed below and are explained in greater detail later in this section eTPU CPU System Simulator TPU CPU32 System Simulator TPU CPU16 System Simulator List of Available Single Target Simulators and Debuggers bg eTPU Stand Alone Simulator g TPU Stand Alone Simulator 3 TPU Standard Mask Simulator 7 CPU32 Stand Alone Simulator CPU 16 Stand Alone Simulator 683xx Hardware Debugger List of Supported Targets The currently supported targets are listed below and are explained in greater detail later in this section eTPU simulation engine TPU simulation engine CPU32 simulation engine CPU32 hardware across a BDM port z CPU16 simulation engine eTPU CPU System Simulator Our eTPU CPU System Simulator supports instantiation and simulation of an arbitrary number and combination of eTPUs and CPUs A dedicated external system modeling CPU could be used for instance to model the behavior of an automobile engine Executable code can be individually loaded into each of these targets Synchronization between targets is fully retained as the full system simulation progresses All CPU engine targets can be used with this system simulation include the CPU32 CPU16 and soon to be released PPC simulation engines 164 TPU CPU32 System Simulator Our TPU CPU32 System Simulator supports instantiation and simul
252. supports a loading of zero using the parameter RAM sub instruction In the TPU1 one could make use of the undocumented feature that reading from the un implemented parameter RAM returned a zero In this case a zero was able to be effectively loaded This capability is supported in the TPU2 by a direct clear or write of zero using the RAM sub instruction New counter options support a higher resolution faster count for TCR1 and improved edge control clock on rising pin edge falling pin edge or both pin edges for TCR2 These include a DIV2 control bit for TCR1 and a T2CSL control bit for the TCR2 These fields are displayed in the configuration window Script commands for controlling these two bits are described in the TPU Clock Control Script Commands section A Flag2 which is quite similar to Flag and Flag0 has been added A conditional branch can now be made on the current pin state using the PIN conditional This field is displayed in the Execution Unit window Previously only the PSL conditional could be used and the PSL is updated only on a time slot transition or a write to the CHAN_REG register The PIN conditional allows a branch based on the most current pin state MRL and TDL can be negated using the TBS field of instruction format three A match can be set to occur on an equal condition Previously matches always occurred based on a greater than or equal logic This match on equal allows the user to schedule a match further out in
253. t Resynchronization Jump Width 666 6059 6 ns PSEG1 68 gt Phase Buffer Segment 1 666 659 6 ns PSEG2 68 gt Phase Buffer Segment 1 666 659 6 ns xxx THE ESTAT STATES ARE NOT DISPLAYED xxx xxx BECAUSE ESTAT READS ARE INTRUSIVE xxx Receive global mask High is FFEF Receive global mask Low is FFFE Receive buffer 14 mask High is FFEF Receive buffer 14 mask Low is FFFE Receive buffer 15 mask High is FFEF Receive buffer 15 mask Low is FFFE See buffer window See buffer window Receive error counter is 66 Transmit error counter is 66 The TouCAN Main window displays the TouCAN Module Configuration Register CANMCR the TouCAN Interrupt Configuration Register CANICR the TouCAN Control Registers 0 1 and 2 CANCTRLO CANCTRLI and CANCTRL2 the touCAN Prescaler Divide Register PRESDIV the Receive Global Mask High and Low Registers RXGMSKHI RXGMSKLO the Receive Buffer 14 and 15 High and Low Registers RXI4MSKHI RX14MSKLO RX1I5MSKHI RX15MSKLO the Interrupt Mask and Flag Registers MASK IFLAG the Receive and Transmit Error Counters RXECTR TXECTR TouCAN Buffers Window Availability 683xx Hardware Debugger 127 O2My68376 TouCAN Buffers 10 x Buf Ctrl ID ID DATA BYTES INTERRUPTS Sts HIGH LOW D8 D1 D2 D3 D4 D5 D D7 Enabled Flag 15 N A QAJ E645 FB 5F FF EE 4D AF FD F3 Disabled clr l l 14 NZA 2BF7 FFFF F7 FF FA 36 F7 F D 7 FS ENABLED cir 13 NZA FEF 7C5F 3E BE 7F B7 B6 F
254. t Startup No File Open Auto Build No File Open Verification Script Failures 660666066 132 Files The name of the project file is displayed See the Project Sessions chapter for a detailed explanation of this capability The name of the MtDt build script file is displayed See the Full System Simulation chapter and the MtDt Build Commands File section for detailed explanations of the available capabilities and format of this file The names of the open source code executable image primary script primary script report and startup script files are displayed These files are listed relative to the path of the open project file The auto build file name is displayed The auto build file allows direct building of the executable image from within MtDt and is covered in the Auto Build Batch File Options Dialog Box section Verification The count of the number of user defined verification tests that have failed since the last MtDt reset is displayed User defined tests are part of script commands files See the Script Commands Groupings section for a description of the various script commands that support user defined tests CPU16 Register Window Availability CPU16 Simulator a GE B 88 D 6666 E 0 0808 X 0 0000 Y 0 0808 Z 0 0808 SP 6 6396 PK 0 0096 FWA 66696 CCR 84E8 HR 6660 IR 6666 ACC 00000 0099 XMSK FF YMSK FF The CPU16 Register window displays the various CPU 16 registers CPU16 Disassembly
255. t address 0 to FFFF hexadecimal A 0 wait state ROM could reside at address 1000 to 1FFFF The rest of memory from 1000 to FFFFFFFF hexadecimal could be empty There are a number of rules associated with memory blocks A build of MtDt simulated memory will succeed only if both of the following rules are met Memory blocks must cover all memory Memory blocks may not occupy both the same address and address space A report file for each build attempt provides a detailed listing of the memory map including the information required to fix any problems The following is an example script commands sequence define MEM_DEVICE_STOP Oxffff define BLANK_START MEM_DEVICE_STOP 1 define MEM_END Oxffffffff instantiate_target SIM16 MySim16 add_mem_block MySim16 0 MEM_DEVICE_STOP RAM ALL_SPACES add_non_mem_block MySim16 BLANK_START MEM_END OFF ALL_SPACES In this example a single CPU16 CPU is instantiated A 64K simulated memory device is added between addresses 0 and FFFF hexadecimal and is assigned the name RAM The device resides in all address spaces A second memory block also residing in all address spaces fills the rest of memory between 1000 hexadecimal and FFFFFFFF hexadecimal and is assigned the name OFF This block is blank and as such takes up no physical memory on your computer Address Spaces All MtDt simulated memory supports eight address spaces The function of each address space depends
256. t commands enum ADDR_SPACE TPU TPU_CODE_SPACE TPU_DATA_SPACE TPU_PINS_SPACE TPU_UNUSED_SPACE eTPU ETPU_CODE_SPACE ETPU_CTRL_SPACE ETPU_DATA_SPACE ETPU_DATA_24 SPACE ETPU_NODE_SPACE ETPU_UNUSED_SPACE CPU16 amp CPU32 CPU16_CODE_SPACE CPU16_DATA_SPACE CPU16_UNUSED_SPACE CPU32_USER_CODE_SPACE CPU32_SUPV_CODE_SPACE CPU32_USER_DATA_SPACE CPU32_SUPV_DATA_SPACE CPU32_UNUSED_SPACE ALL_SPACES In the following very specific cases mathematical manipulation of this enumerated data type is allowed z Single instances of values referencing the same target may be added to each other Single instances of values referencing the same target may be subtracted from ALL_SPACES The following are some valid mathematical manipulations of this data type The following references a CPU32 s USER and SUPERVISOR code spaces CPU32_USER_CODE_SPACE CPU32_SUPV_CODE_SPACE The following references all used CPU32 address spaces ALL_SPACES CPU32_UNUSED_SPACE The following are some invalid valid mathematical manipulations of this data type MINVALID CPU32 and CPU16 cannot be intermixed CPU32_USER_CODE_SPACE CPU16_DATA_SPACE HVINVALID The same value cannot be added or subtracted to itself TPU_PINS_SPACE TPU_PINS_SPACE Build Script READ_WRITE Enumerated Data Type This enumerated data type is used when specifying the applicable read and or write cycles for various build script commands enum READ_WRITE
257. t into two fields This allows the last calculated timing to be retained while a new timer calculation is underway When a timer is re armed the This Ticks field goes blank while the Last Ticks field retains the previous value To the right of the Last Ticks field is the Last Time field The Last Time field is identical to the Last Ticks field except that the timer result is displayed in micro seconds instead of clock ticks 100 Note that the Last Ticks and This Ticks fields use the target s current clock period in the calculation Only the start time and stop time are retained by the timers This means that if the clock period changes during the course of a calculation these clock tick calculations will not be correct Note also that the time calculation on simulated targets does not use the clock period so this field will be correct even if the clock period is changed eTPU Channel Function Frame Window eTpu1 Channel 0 Context Window Context Frame Window Line 1 Context Frame Window Line 2 Context Frame Window Line 3 Context Frame Window Line 4 X 4l IZ The Channel Frame window shows the channel function and static local variables belonging to a particular channel Right click the mouse in the window to change the channel eTPU Configuration Window eTpul Configuration General CPU Frequency 166 666 MHz CPU Clock 660666198 Latest thread is 2 steps 4 clocks Active 67 167 Threads 3 Steps 16 Entry Table Bas
258. tablished for all targets In the search rules listed above the phrase search relative to the directory is used What does this mean It means that if the file is specified as Dirl Dir2 FileName xyz start at the base 20 directory and go up one then look down in directory Dir2 and search in this directory for the file FileName xyz Note that the search rules apply only to source code files in which an exact path is not available If an exact path is available the source code file will be searched only at that exact path If an exact path is provided and the file is not located at that exact path the search will fail The Source Code Search Options dialog box allows the user to specify the global directories search list as well as the search lists associated with each individual target Absolute and Relative Paths MtDt accepts both absolute and relative paths An absolute path is one in which the file can be precisely located based solely that path The following is an absolute path C Compiler Libary A relative path is one in which the resolution of the full path requires a starting point The following is an example of a relative path ControlLaws Relative paths are internally converted to absolute paths using the main build file as the starting point As an example suppose the main build file named A OUT is located at the following location C MainBuildTopLevel A out Now assume that in the search rule
259. target must provide the dock from block and the other target must be the dock to The dock to target is relatively unaffected by being the recipient of a dock other than that its physical memory might be modified on occasion On the other hand there are numerous effects to the dock from target First and foremost it must be able to support extrinsic or externally mapped memory In other words it must be able to project its memory access outside of itself and to a different target Note that this command must match exactly the memory bounds of an existing memory block for the docking device but not for the dock to target In fact the dock to target could be any target such as a MC68332 across a BDM port In fact the dock to target could be itself and this is the recommended way of modeling multiple image memory Although memory accesses are fully re entrant legal and often necessary it is possible to create an infinitely cyclic access that would 175 without guards cause a stack overflow on your computer To guard against this MtDt has limited memory accesses re entrance to a depth of 100 The following build script command is presented in a later example I set_block_to_dock HostCpu TpuDataDock ALL_SPACES Tpu 0 0x80000 ES In the above command a previously added blank block is docked to memory contained in a target named TPU The last argument ALL_SPACES is potentially problematic as will be di
260. tch exitQ This shuts down the application and sets the error level to non zero if any verification tests failed If all tests pass the error level is set to zero The error level can be examined by a batch file that launched MtDt thereby supported automated testing See the Regression Testing section for a detailed explanation of and examples showing how this command can be used as part of an automated test suite print messageString This command is geared toward promoting camaraderie between coworkers This command causes a dialog box to open that contains the string lt messageString gt The truly devious practical joker will find a way to combine this script command with sound effects print Hit any key to fuse all P wells with all N substrates in your target silicon In the example above your coworker at the adjacent lab bench pauses for a certain amount of healthy introspection A well placed and timed bzilch chord can significantly enhance its effect File Script Commands These commands support loading and saving files via script commands load_executable filename executable 36 This example loads the executable image and related source files found in file filename executable Any open source files in the previously active image are closed The file path is resolved relative to the directory in which the project file is located load_executable A Out This example loads the executable found in file
261. tepping etc include AngleMode h In this example file AngleMode h is included into the script commands file that included it The ifdef ifndef else endif directives These directives support conditional parsing of the text between the directives That is all she wrote ifdef_ ASH WARE _AUTO_RUN exitQ else print All tests are done endif _ ASH WARE_AUTO_RUN The above directive is commonly found at the very end of a script commands file that is part of an automated test suite It allows behavior dependent on the test conditions Note that ASH_WARE_AUTO_RUN_ is automatically defined when the simulator debugger is launched in such a way that it runs without user input In this case upon reaching the end of the script file the application simulator or debugger is closed when it is part of an automated test suite and otherwise a message is issued to the user Enumerated Data Types in Script Commands Files Enumerated types are only indirectly available to the user Many defined functions have arguments that require specific enumerated data as arguments Since the user cannot currently prototype new functions or recast enumerated data this discussion is only indirectly germane Despite these limitations internally enumerated data types are defined for many script commands and the tighter checking and version independence provided by enumerated data types mke them an important aspect of scri
262. th the global exceptions There are some differences between the primary script commands file and ISR script commands files Some important considerations are listed below ISR script commands files are associated with channels using the load_isr and similar script commands The primary script commands file begins execution after a Simulator reset whereas ISR script commands files execute when the associated interrupt becomes both asserted and enabled 3 The primary script commands file is preempted by the ISR script commands files ISR script commands files are not preempted even by other ISR script commands files and even if the discouraged use of timing commands with these ISR script commands files is adapted Only a single primary script commands file can be active at any given time Each interrupt source can have only a single ISR script commands file associated with it Within the interrupt service routine the ISR script commands file should clear the interrupt This is accomplished using the clear_cisr X the clear_this_cisr or similar script command Failure to clear the interrupt request causes an infinite loop a A single ISR script commands file can be associated with multiple interrupt sources such as eTPU TPU channels To make the ISR script commands file portable across multiple channels be sure to use the clear_this_cisr or similar script command Do not use the clear_this_cisr script command in the
263. that can be used within MtDt build script files is found in the MtDt Build Script Commands File section That section explains how a complete system is defined using these build script commands MtDt Simulated Memory Simulated targets require memory for executing code for holding data and for providing capabilities supported in a simulated environment The following is a list of simulated memory characteristics supported by MtDt memory Multiple address spaces Memory sizing Read only or read write accesses Shared memory is Byte word and long word access widths z Access speed based on even or odd access addresses Privilege violations Bus faults Address faults 7 Banking Mirroring The ASH WARE MtDt simulated memory model supports all of these characteristics though at the cost of increased complexity The good news is that for many applications the standard memory models work just fine so a detailed understanding of memory modeling is not required In the vast majority of other cases only a small percentage of these capabilities are required Memory Block Whereas a simulated memory map can support a large variety of characteristics that might change 171 from one memory range and address space to the next a memory block is a range of memory that has a single uniform set of characteristics A target s address space comprises a finite number of memory blocks For instance a 3 wait state RAM could reside a
264. the applicable address spaces ADDR_SPACE and read and or write cycles enum READ_WRITE The affected address spaces must be a subset of the address spaces to which the referenced memory block applies define ALL_DATA_SPACE CPU32_SUPV_DATA_SPACE CPU32_USER_DATA_SPACE add_mem_block MyCpu32 0x10000 0x1FFFF Protected ALL_DATA_SPACE set_block_to_priv_viol MyCpu32 Protected CPU32_USER_DATA_SPACE RW_ALL In this example data space accesses to the simulated memory while at the supervisor privilege level will succeed whereas accesses at the user privilege level will result in a privilege violation set_block_to_addrs_fault TargetName BlockName enum ADDR_SPACE enum READ_WRITE This command results in address faults for odd accesses to the target TargetName within the block BlockName for the applicable address spaces ADDR_SPACE and read and or write cycles enum READ_WRITE The affected address spaces must be a subset of the address spaces to which the referenced memory block applies Even accesses will not result in an address fault set_block_to_addrs_fault MyCpu16 EvenMem CPU16_CODE_SPACE RW_ALL In this example code space accesses to odd addresses are configured to result in an address fault set_block_timing TargetName BlockName enum ADDR_SPACE enum READ_WRITE ClockPerEvenAccess ClocksPerOddAccess This command sets the timing for the target TargetName in the block BlockName This co
265. the features that are new to MtDt version 2 1 Note that in this version MtDt was known as the TPU Simulator TPU3 support Association of ISR script commands files with interrupts Web based software upgrades 17 The following is a list of the features that are new to MtDt version 2 0 MtDt was known as the TPU Simulator TPU2 support Functional verification Pin transition behavior verification Code coverage analysis External logic simulation Auto build 18 Note that in this version PROJECT SESSIONS The Project Open and Project Save As dialog boxes allow association of the MtDt configuration with an MtDt project file Various global settings are stored in this file including the active microcode test vector script and auto build files To open an existing MtDt project file either double click on the file from Microsoft Windows Explorer or from the Files menu select the Project Open submenu Then select the name and existing MtDt project file Various settings from the just opened MtDt project file are loaded into MtDt Note that before opening the new project file you are given the option to save the currently active settings to the currently active project file To create a new MtDt project file from the Files menu select the Save As submenu Then specify a new file name At startup global settings are retrieved from the last active MtDt project file assuming that no MtDt project f
266. time and going backward 141 Dialog boxes provide an interface for setting the various Simulator options DIALOG BOXES has the dialog boxes listed below File Open Save and Save As Dialog Boxes Auto Build Batch File Options Dialog Box Goto Time Dialog Box Occupy Workshop Dialog Box IDE Options Dialog Box Workshop Options Dialog Box Message Options Dialog Box Source Code Search Options Dialog Box Reset Options Dialog Box Logic Analyzer Options Dialog Box Thread Options Dialog Box Complex Breakpoint Dialog Box Trace Options Dialog Box Local Variable Options Dialog Box License Options Dialog Box BDM Options Dialog Box Memory Tool Dialog Box Insert Watch Dialog Box Watch Options Dialog Box File Open Save and Save As Dialog Boxes This version of MtDt The File Open Save and Save As dialog boxes support the opening and saving of a number of files Each of these is described individually below Load Executable Dialog Box The Load Executable dialog box controls the opening of the executable image source code This enables the user to change the source code recompile the source code and reread it into MtDt It also allows a different executable image source code to be loaded into the target See the Source Code Files Windows section for information on viewing the executable image source code files Open Primary Script File Dialog Box This dialog box specifies which primary script comma
267. to be logged to the trace buffer Exception Selecting this option causes each exception to be logged to the trace buffer This is only meaningful in the context of CPU targets Time Slot Transition Selecting this option causes each time slot transition to be logged to the trace buffer This is only meaningful in the context of TPU targets State End Selecting this option causes state end to be logged to the trace buffer This is only meaningful in the context of TPU targets Pin Transition Selecting this option causes each pin transition to be logged to the trace buffer This is only meaningful in the context of TPU targets SGL Negation NOP Selecting this option causes SGL negation NOP to be logged to the trace buffer This is only meaningful in the context of TPU targets Trace Window and Trace Buffer Considerations The Trace Options Dialog Box specifies what is stored in the trace buffer The Trace Window displays all trace information stored in the trace buffer regardless of whether or not this information is enabled for storage If information has already been stored in the buffer and you disable tracing of this information the information will not disappear from the Trace Window until the buffer has been completely overwritten with new information or until the buffer is flushed following a reset Multiple Target Considerations Individual trace settings are maintained for each target In a multiple target environment it is pos
268. tputs and also driven by test vectors is undefined A typical and appropriate use of Boolean logic in conjunction with test vectors is to connect a TPU channel pin that is configured as an input to the input of the Boolean logic This pin is then driven by a test vector file Example 1 Driving the TCR2 Pin In the following example a TPU channel drives the TCR2 pin The buffer is instantiated from within a script commands file using the place_buffer X Y script command The buffer s input is connected to the TPU channel s pin and the buffer s output to the TCR2 pin The X variable is set to five to make TPU channel five the buffer s input The Y variable is set to 16 as this is the index that MtDt uses for the TCR2 pin place_buffer 5 16 Buffer created by place_buffer x y script command TPU PA XMIT gt TCR2 p Example 2 Multi Drop Communications In the following multi drop communications example TPU channel 5 is a communications channel output TPU channel 7 is used as a gate to enable and disable the output Channel 1 is the communications input An idle line is low An AND gate is instantiated using the 83 place_and_gate X Y Z script command The gate pin causes an idle LOW state on the input by going low By going high the gate pin causes the state on the output channel to be driven unto the input channel place_and_gate 5 7 1 Buffer created by place_and_gate X Y Z TPU scri
269. tryIndex ToEntryIndex Consider the following thread labeled invalid_flagO This thread is never expected to occur because the function clears flag0 at initialization and flagO is never set So thus state which handles a match or transition event in which the flagO condition is set should never execute 39 el pul Source MeasurePeriod c p 5 x else if Istaten rTrassiticastweat amp amp flagf 1 Doa terose Std Entry 13 Sfer Ox26 EmsbleNatches pe relative G24 DzU ieb e relative B24 Ost 0 s ESk MANA Liak 0 Matcea TraeS 0 Matce Trae 1 lepetPie 0 Chasflagi K C Fla g 1 DISE tbose Std Eatry 15 Sfor Ox26 Emabletatches pre relative F24 x0 die e relative F26 Gxt 0 BSa MNN Liak 0 Matcee TraeB 0 Matces Trae 1 lapetPia lt 1 Chaeflagi x Chaaflagt lt 1 Unsa trose Std Entry 21 Sfer Ox26C EmableHatches p e relative F2 Ox0 dieb relative B24 Orb 0 SS 02000 Lisk Natc s irasS 1 Hatc s Tras 1 lapetfis 0 Chaeflagi k Ch aFl gi 1 Uos terose St Entry 23 Sfor Ur26C EmabletHatches pre relative F2 x0 die e relative F24 Gxt 0 ESA MANA Liee 0 Matcha TraaB 1 MatceS Traet 1 lepetPia 1 Chasflagi K Chaat lagt lt 1 iawali flagQ Jf Merk invalid Flag state te make observable for Gebeqg perpeses D Clear Fl A shan citar Chases li lag Farnates 5 BacStateFawlt Ix Pb 9S zi 270 Oxhess3SSO0 as P Mr3bh
270. ts Each complex breakpoint can have one or more conditionals When mult iple conditionals are added to the same breakpoint then all conditionals must simultaneously resolve to true in order for the complex breakpoint to halt the target s Conditionals are added and modified using the Complex Breakpoint Conditional dialog box Depending on the target conditionals can include input output and clock pins thread activity host service requests and program counter value variable values or tests etc Memory Dump Window 60060 7FFFFEFE 3FFFFFFE BFFFFFF8 1FFFF807 5858F47E 5C5C35FA SCSC33FA E1E401C7 y 09020 SEGBFEF8 7859FEFF 7AS9FEFF 3C7FF807 D4OEFFFF 525CB5FA 163FFO0B 161DF86F OPNA QAICFFFF ZAFFRA1 I IFF ONFEFF QnHAKSEEEE NOFFAFFF CACFEARGO CHCFEANO OW QREEFE odil Hosti6 Memory Data Space ig ot OMIE 00 00 00 90 52 3 66 O OA B GO B G B B RG C OL 0010 66 B 68 B 66 B G8 B G66 B O B BH B OO B OE 0020 66 B 66 B6 66 B OA B 66 B G6 B B OO B OE 0030 66 B 66 B6 66 B GB B 66 B 66 B GH B B 61 0040 66 B 66 B6 66 B6 G8 B 66 B 66 B BH B OO B M 9056 66 B 66 B 00 B GO B 66 B GO B GO B OO B eeeeeeeee E 6066 66 B6 66 B OG B 66 B6 G6 B G6 B B B M am uy The Memory Dump Window displays memory A number of opt
271. ts Formatai 4 n274 MrAFFFFES3 ran relative E24 MD p 23 0 Format 0 3 UAFFFFES seq oeedi Format 2 4 xl ajm aj A test has been written to excersize this thread and one can see that Event vector 15 has been covered because the box on the left is white But entries 13 21 and 23 have not been executed because the boxes on the left are still black Since this is an invalid case that actually should never execute it is considered sufficient to infer coverage of entries 13 21 and 23 as long as event vector 15 is covered This is done using the following script command infer_entry_coverage MEASURE_PERIOD_FUNC 15 13 infer_entry_coverage MEASURE_PERIOD_FUNC 15 21 infer_entry_coverage MEASURE_PERIOD_FUNC 15 23 Although there are a number of restrictions listed below that are enforced by the simulator the most important restriction is not enforced Namely that this coverage by inference should only used for invalid cases where the thread exists purely as Built In Test BIT and would not n normal operation be expected to execute In fact when testing to the very highest software testing standards 100 event vector coverage should be achieved without the use of this script command Execution of an event vector that is covered by inference results in a verification failure The FromEntryIndex s thread and the ToEntryIndexthread thread must be the same Ney Cumulative Coverage To prod
272. uce the highest quality software it is imperative that testing cover 100 of instructions branches and event vectors for eTPU targets Additionally for quality control purposes this coverage should be proven using the verify_coverage scripts But most test suites consist of multiple tests such that the coverage is achieved only after all tests have run The cumulative coverage scripts provide the ability to prove that the entire test suite cumulatively has achieved 100 coverage The typical testing procedure might work as follows A series of tests is run and at the end of each test the coverage data is stored At the end of the very last test the coverage data from all previous tests are loaded such that the resulting coverage is an accumulation of the coverage of all previous tests Then the verify_coverage script command is run proving that all tests have passed The following illustrates this process Run Test A save_cumulative_file_coverage MyFunc c TestA CoverageData Run Test B save_cumulative_file_coverage MyFunc c TestB CoverageData Run Test M save_cumulative_file_coverage MyFunc c TestM CoverageData Run Test N load_cumulative_file_coverage MyFunc c TestA CoverageData 40 wo load_cumulative_file_coverage MyFunc c TestB CoverageData wow load_cumulative_file_coverage MyFunc c TestM CoverageData verify_file_coverage MyFunc c 100 100 100
273. uite differently from script commands files While script commands file lines are executed sequentially and at specific simulated times test vector files are loaded all at once Test vector files are used solely to generate complex test vectors on particular TPU Simulator nodes As MtDt executes these test vectors are driven unto the specified nodes Test Vector Generation Functional Model a TPU Wave Form Channel 7 Generator Wave Form Channel 2 Generator Wave Form T2 Clock Generator The test vector generation model consists of a single master test vector clock and a number of wave form generators The same master test vector clock clocks all wave form generators The wave form generators cannot produce waveforms whose frequencies exceed that of the master test vector clock A wave form might consist of a loop in which a node is driven high for 10 master test vector clock periods then low for 15 The loop could be set up to run forever 68 Test vector files provide the following functionality The master test vector clock frequency is specified The wave form generators are created and defined Wave form outputs are connected to TPU nodes Descriptive names are assigned to TPU nodes i e TPU channel 7 s pin is named UART_RCV Multiple TPU nodes are grouped i e group COMM consists of UART_RCV1 and UART_RCV 2 a Complex Boolean states are defined Command Reference The following test vecto
274. ulation model provides several additional events that can be viewed in the Trace window These are in addition to the normal data flow between TPU and memory and opcode execution etc that are available for most targets These events include execution steps time state transitions active channel transitions and four CPU clock NOPs This window serves two purposes It shows the thread of execution and it can be used to analyze channel service timing When the TPU services a particular channel a 10 clock time slot transition occurs The states of the Service Request Latch SRL and Service Grant Latch SGL as well as a timestamp and a channel number are displayed for each time slot transition The SRL is the fourth field from the left while the SGL field is displayed to the right of the SRL field When all pending service requests from a particular priority level have been serviced the TPU negates the service grant bits associated with those channels This requires four CPU clocks For this event MtDt displays the timestamp and the states of the SRL and the SGL Trace Source Code Automation The trace window and the Source Code window s can be used together Select a line in the Source Code Window associated with an instruction execution The source code file associated with this line automatically pops into view and the associated line scrolls into view and is highlighted in yellow In the TPU trace window shown above the seventh line has be
275. utomatically hidden when in TPU1 or TPU2 mode since they apply only to the TPU3 These bits are controlled using script commands described in the TPU Clock Control Script Commands section Verification An indication of whether behavior verification is enabled or disabled is displayed The count of the number of behavior verification errors that have occurred is displayed See the Pin Transition Behavior Verification section The count of the number of user defined verification tests that have failed since the last MtDt reset is displayed User defined tests are part of script commands files See the Script Commands Groupings section for a description of the various script commands that support user defined tests Versions Version information on the device being simulated TPUI TPU2 TPU3 the Simulator and the microcode assembler is listed Files The name of the project file is displayed See the Project Sessions chapter for a detailed explanation of this capability The name of the MtDt build script file is displayed See the Full System Simulation chapter and the MtDt Build Script Commands File chapter for detailed explanations of the available capabilities and format of this file The names of the open source microcode primary script primary script report startup script and test vector files are displayed These files are listed relative to the path of the open project file The auto build file name is displayed The auto buil
276. utton Controls 140 Timing Display 141 Data Storage Buffer 141 DIALOG BOXES 142 File Open Save and Save As Dialog Boxes 142 Load Executable Dialog Box 142 Open Primary Script File Dialog Box 142 Save Primary Script Commands Report File Dialog Box 143 Open Startup Script Commands File Dialog Box 143 Open Test Vector File Dialog Box 143 Project Open and Project Save As Dialog Boxes 143 Run MtDt Build Script Dialog Box 143 Save Behavior Verification Dialog Box 144 Save Coverage Statistics Dialog Box 144 Auto Build Batch File Options Dialog Box 144 Goto Time Dialog Box 145 Occupy Workshop Dialog Box 145 IDE Options Dialog Box 146 All Targets Settings 146 TPU Simulator Target Only 147 Active Target Settings 147 Workshops Options Dialog Box 147 Message Options Dialog Box 148 All Targets Messages 148 TPU Messages 148 Source Code Search Options Dialog Box 149 Reset Options Dialog Box 150 Logic Analyzer Options Dialog Box 150 Channel Group Options Dialog Box 151 Complex Breakpoint Conditional Dialog Box 151 Trace Options Dialog Box 152 Trace Window and Trace Buffer Considerations 152 Multiple Target Considerations 152 Local Variable Options Dialog Box 153 License Options Dialog Box 153 BDM Options Dialog Box 153 Memory Tool Dialog Box 154 Insert Watch Dialog Box 154 Watch Options Dialog Box 155 About ASH WARE s Multiple Target Development Tool 155 BDM Port Dialog Box 155 MENUS 156 Files Menu 156 Step Menu 158 Run Menu 159 Break
277. vector Enable and Pin Widths fields All except the Pin Width field are bit groupings derived from the CSBARX and the CSORX registers The Pin Width field is derived from the Chip Select Pin Assignment registers one and zero CSPARI CSPARO not shown in this window QSM Main Window Availability 683xx Hardware Debugger 32 MyBdm32 QSM Main lol x QSMMCR STOP F F The QSM Module is operating normally FR21 E E When FREEZE on IMB ignore it FR26 D D Reserved for future use SUPU 7 7 QSM SZU registers access at Supu priviledge level IARB 3 6 QSM interrupt arbitration priority 6 QILR UR GOOF ILQSPI D B QSPI interrupt priority is 6 ILSCI A 8 SCI interrupt priority is 6 INTY 7 0 QSM interrupt vecor number is OF The QSM Main window displays the QSM Configuration Register QSMMCR and the QSM Interrupt Level and Vector Register QILR QIVR QSM Port Window Availability 683xx Hardware Debugger 3 MyBdm32 QSM Port jo x PQSPAR BE TXD 7 7 PQS 7 Input 6 DDRQS 66 PCS3 6 6 PQS 6 Input 6 PORTQS 66 PCS2 5 5 PQs 5 Input 6 Pcs4 4 4 PQS 4 Input 6 PCSG SS 3 3 PQS 3 Input 6 SCK 2 2 PQS 2 Input 6 MOSI 4 1 PQS 1 Input 6 MISO 8 6 PQS 6 Input 6 The QSM Port window displays the Port QS Pin Assignment Register PQSPAR the Port QS Data Direction Register DDRQS and the Port QS Data Register PORTQS Using the bit port bit fields located to the right of the bit p
278. vice that resides in a 64K memory system Assume it is an 8 bit wide device Since the 8K device is on a byte wide bus the device itself decodes the lower 13 address bits A12 through AO Assume that the memory controller decodes only the upper two address bits A15 and A14 and enables the device when both are zero This means that nothing decodes A13 and thus the memory device is activated when A15 and A14 are zero regardless of the state of A13 179 All Spaces FFFFFFFF The memory here af Is mirrored here This mirrored memory architecture is created by implementing a dock from the address space to itself as follows instantiate_target SIM16 MyCpu add_non_mem_block MyCpu 0x0 0x1FFF Mirror ALL_SPACES add_mem_block MyCpu 0x2000 0x3FFF RAM ALL_SPACES add_non_mem_block MyCpu 0x4000 0xFFFFFFFF B1 ALL_SPACES Create a mirror at the lowest 8K of the next higher 8K set_block_to_dock MyCpu Mirror ALL_SPACES MyCpu 0x2000 In this example the previously described memory architecture with mirrored memory is implemented Computer Memory Considerations MtDt uses your computer s memory to model the memory devices belonging to your target There is roughly a one to one correspondence between the total amount of memory occupied by the simulated devices and the amount of your computer s memory that is required In the examples shown in the previous sections simulated memory totals a few hu
279. window event occurred This context capability is a powerful debugging tool The source code associated with the trace data also pops into view This allows you to line up previously executed source code the trace data and in some cases the call stack data If you want to re execute to that context time use the mouse to drag the time from the context time indicator into the current time indicator as explained in the Executing to a Precise Time section Context Time Indicator The context time indicator displays the time with the IDE wide context time For example select a past event in a trace window The time associated with this event becomes the context time This context time appears as the vertical yellow context cursor in the waveform display Drag and drop this time into the current time as explained in the Executing to a Precise Time section Scroll Bars The horizontal scroll bar provides the functionality shown in the picture below Note that this is a standard Windows scroll bar except that it has the additional functionality of the Home and End keys These keys move the view to the start or end of the simulation Home PageLeft PageRight End ShiftLeft Drag ShiftRight The vertical scroll bar provides the functionality shown in the picture below This provides the user with the ability to scroll through the 30 available nodes that the Logic Analyzer supports 139 ShiftUp PageUp Drag PageDown Sh
280. xample the event vector table is placed at address 0x8 00 write_global_time_base_enable The command enables the time bases for all the eTPUs write_entry_table_base_addr Addr In the Byte Craft eTPU C Compiler the event vector table base address can be automatically generated using the following macro pragma write h define MY_ENTRY_TABLE_BASE_ADDR ETPUentrybase 0 In the Byte Craft eTPU C Compiler the event vector table base address is specified as follows pragma entryaddr 0x800 eTPU Time Base Configuration Script Commands write_angle_mode Val write_tcr1_control Val write_tcr2_control Val These commands write their respective field values in the ETPUTBCR register write_tcr1_prescaler Prescaler write_tcr2_prescaler Prescaler These commands write the prescaler Prescaler to the ETPUTBCR register Valid values for TCR1 are 1 256 and for TCR2 are 1 64 write_angle_mode 0 Disable write_tcr1_control 1 System clock 2 write_tcr2_control 4 System clock 8 write_tcr1_prescaler 1 _ Fastest divide by 1 write_tcr2_prescaler 64 Slowest divide by 64 In this example angle mode is disabled the TCR1 counter is programmed to be equal to the system clock divide by two system clock divided by two prescaler is divides by one and TCR2 is programmed to be the system clock divided by 512 system clock divided by 8 with a 64 prescaler set_angle_indices lt DegreesPerCy

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