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USER`S MANUAL

1. S S Pio Watwooces ooo 1 Stack Area Selection Bit o Select internal register file area Select external data memory area 0 Not used for S3F80K5 NOTE The EMT register is not used for S3F80K5 because an external peripheral interface is not implemented in the S3F80K5 The program initialization routine should clear the EMT register to 00H following a reset Modification of EMT values during normal operation may cause a system malfunction ELECTRONICS 4 9 CONTROL REGISTERS S3F80K5 UM REV1 11 FLAGS System Flags Register D5H Seti Bank Reset Value D D D D D D 0 0 Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only 7 Carry Flag Bit C Operation does not generate a carry or borrow condition 1 Operation generates a carry out or borrow into high order bit 7 6 Zero Flag Bit Z Operation result is a non zero value 1 Operation result is zero 5 Sign Flag Bit S Operation generates a positive number MSB 0 Q 1 Operation generates a negative number MSB 1 A Overflow Flag Bit V Operation result is lt 127 or gt 128 1 Operation result is gt 127 or lt 128 3 Decimal Adjust Flag Bit D Add operation completed 1 Subtraction operation completed 2 Half Carry Flag Bit H No carry out of bit 3 or no borrow into bit 3 by addition or subtraction 1 Addition generated carry out of bit 3 or subtraction generated borrow into bit
2. Figure 2 15 8 Bit Working Register Addressing Example ELECTRONICS 2 19 ADDRESS SPACE S3F80K5 UM REV1 11 SYSTEM AND USER STACKS S3C8 series microcontrollers use the system stack for subroutine calls and returns and to store data The PUSH and POP instructions are used to control system stack operations The S3F80K5 architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAGS registers are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 15 High Address PCL PCH PCH Flags Stack contents Stack contents after a call after an instruction interrupt Low Address Figure 2 16 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL Register location D9H contains the 8 bit stack pointer
3. Figure 17 1 Pin Assignment Diagram 24 Pin SOP SDIP Package 17 2 ELECTRONICS S3F80K5 UM REV1 11 S3F80K5 FLASH MCU Table 17 1 Descriptions of Pins Used to Read Write the Flash ROM Main Chip Se Programming Serial data pin Output port when reading and input port when writing SDAT P0 0 can be assigned as an input or push pull output port Serial data pin Output port when reading and input port when writing SCLK P0 1 can be assigned as an input or push pull output port Tool mode selection when TEST pin sets Logic value 1 If user uses the flash writer tool mode ex spw2 etc user should connect TEST pin to VDD S3F80K5 supplies high voltage 12 5V by internal high voltage generation circuit nRESET nRESET Chip Initialization Vop Von 4 Power supply pin for logic circuit VDD should be 4 tied to 3 3V durin programming Vss Vss NOTE Test Pin Voltage The TEST pin on socket board for OTP MTP writer must be connected to Vdd 3 3V The TEST pin on socket board must not be connected Vpp 12 5V which is generated from OTP MTP Writer So the specific socket board for S3F80K5 must be used when writing or erasing using OTP MTP writer ELECTRONICS 17 3 S3F80K5 FLASH MCU S3F80K5 UM REV1 11 OPERATING MODE CHARACTERISTICS When 3 3 V is supplied to the TEST pin of the S3F80K5 the Flash ROM programming mode is entered The operating mode read write or read protection is selected accordin
4. the overflow interrupt is generated each time the 16 bit up counter reaches FFFFH After the interrupt request is generated the counter value is automatically cleared to OOH and up counting resumes By writing a 1 to T1CON 3 you can clear reset the 16 bit counter value at any time during program operation TIMER 1 CAPTURE INTERRUPT Timer 1 can be used to generate a capture interrupt IRQ1 vector F6H whenever a triggering condition is detected at the P3 0 pin The T1CON 5 and T1CON 4 bit pair setting is used to select the trigger condition for capture mode operation rising edges falling edges or both signal edges In capture mode program software can poll the Timer 1 match capture interrupt pending bit T1CON 0 to detect when a Timer 1 capture interrupt pending condition exists T1CON 0 1 When the interrupt request is acknowledged by the CPU and the service routine starts the interrupt service routine for vector F6H must clear the interrupt pending condition by writing a 0 to T1CON 0 T1CON 2 16 Bit Up Counter gt IRQ1 T1OVF Pending T1CON 0 IRQ1 T1INT Interrupt Enable Disable T1CON 1 T1CON 5 Timer 1 Data T1CON 4 Figure 11 1 Simplified Timer 1 Function Diagram Capture Mode 11 2 ELECTRONICS S3F80K5 UM REV1 11 TIMER 1 TIMER 1 MATCH INTERRUPT Timer 1 can also be used to generate a match interrupt IRQ1 vector F6H whenever the 16 bit counter value matches
5. 4 P0 4 External Interrupt INT4 Pending Flag Bit No P0 4 external interrupt pending when read 1 P0 4 external interrupt is pending when read 3 P0 3 External Interrupt INT3 Pending Flag Bit No P0 3 external interrupt pending when read 1 P0 3 external interrupt is pending when read 2 P0 2 External Interrupt INT2 Pending Flag Bit No P0 2 external interrupt pending when read 1 P0 2 external interrupt is pending when read cl P0 1 External Interrupt INT1 Pending Flag Bit No P0 1 external interrupt pending when read 1 P0 1 external interrupt is pending when read 0 P0 0 External Interrupt INTO Pending Flag Bit No P0 0 external interrupt pending when read 1 P0 0 external interrupt is pending when read NOTE To clear an interrupt pending condition write a 0 to the appropriate pending flag bit Writing a 1 to an interrupt pending flag POPND 7 0 has no effect 4 22 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS POPUR Porto Pull up Resistor Enable Register E7H Seti Bank0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P0 7 Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 6 PO o Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 5 PO al Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 4
6. Table 15 3 Characteristics of Low Voltage Detect Circuit Ta 25 C to 85 C Hysteresis Voltage of LVD AV 100 200 mV Slew Rate of LVD Low Level Detect Voltage LVD 1 65 1 75 1 85 V for Back Up Mode Low Level Detect Voltage LVD_FLAG1 rr 1 80 1 90 2 00 d for Flag Indicator iv riacs ao aso 2 y uge 210 22 200 v 15 4 ELECTRONICS S3F80K5 UM REV1 11 ELECTRICAL DATA NOTE The voltage gaps LVD GAPn n 1 4 between LVD and LVD FLAGn n 1 4 have 80mV distribution LVD and LVD FLAGn n 1 4 are not overlapped LVD_GAP3 270 350 LVD_GAP4 370 450 530 mV Table 15 4 Power On Reset Circuit Ta 25 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Power on reset POR Vpor 1 0 1 2 1 4 V Voltage Table 15 5 Data Retention Supply Voltage in Stop Mode Ta 25 C to 85 C Data Retention Supply VDDDR 1 0 3 6 V Voltage Data Retention Supply lbopr Vopoa 1 0 V 1 pA Current Stop Mode ELECTRONICS 15 5 ELECTRICAL DATA S3F80K5 UM REV1 11 Idle Mode Basic Timer Active Stop Mode GR R RE RR gt J Data Retention Mode A Normal Operating Mode Execution of STOP Instrction EXT INT Figure 15 1 Stop Mode Release Timing When Initiated by an External Interrupt Oscillation Stabilization Time I Stop Mode Normal Operating Mode A Execution of STOP Instrction nRESET 0 2VDD NOTE twar
7. The power down mode of S3F80K5 are described following that Idle mode Back up mode Stop mode IDLE MODE Idle mode is invoked by the instruction IDLE op code 6FH In Idle mode CPU operations are halted while some peripherals remain active During Idle mode the internal clock signal is gated away from the CPU and from all but the following peripherals which remain active Interrupt logic Basic Timer Timer 0 Timer 1 CounterA I O port pins retain the state input or output they had at the time Idle mode was entered IDLE Mode Release You can release Idle mode in one of two ways 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slowest clock 1 16 because of the hardware reset value for the CLKCON register If all interrupts are masked in the IMR register a reset is the only way you can release Idle mode 2 Activate any enabled interrupt internal or external When you use an interrupt to release Idle mode the 2 bit CLKCON 4 CLKCON 3 value remains unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt condition IRET occurs the instruction immediately following the one which initiated Idle mode is executed NOTE Only external interrupts built in to the pin circuit can be used to releas
8. 24 us CADATAH 2 FX CADATAH 2 x 1us CADATAH 22 12 4 ELECTRONICS S3F80K5 UM REV1 11 COUNTER A Counter A Clock CAOF 0 CADATAL 01 FFH CADATAH 00H CAOF 0 CADATAL 00H CADATAH 01 FFH CAOF 0 CADATAL 00H CADATAH 00H CAOF 1 CADATAL 00H CADATAH 00H Counter A Clock CAOF 1 CADATAL DEH CADATAH 1EH CAOF 0 CADATAL DEH CADATAH 1EH CAOF 1 CADATAL 7EH CADATAH 7EH CAOF 0 CADATAL 7EH CADATAH 7EH Figure 12 4 Counter A Output Flip Flop Waveforms in Repeat Mode ELECTRONICS 12 5 COUNTER A S3F80K5 UM REV1 11 L PROGRAMMING TIP To generate 38 kHz 1 3duty signal through P3 1 This example sets Counter A to the repeat mode sets the oscillation frequency as the Counter A clock source and CADATAH and CADATAL to make a 38 kHz 1 3 Duty carrier frequency The program parameters are 8 795 us 17 59 us gt 37 9 kHz 1 3 duty Counter A is used in repeat mode Oscillation frequency is 4 MHz 0 25 us CADATAH 8 795 us 0 25 us 35 18 CADATAL 17 59 us 0 25 us 70 36 Set P3 1 C MOS push pull output and CAOF mode ORG 0100H Reset address START DI LD CADATAL 70 2 Set 17 5 ms LD CADATAH 35 2 Set 8 75 ms LD P3CON 11110010B Set P3 to C MOS push pull output Set P3 1 to REM output LD CACON 00000110B Clock Source gt Fosc Disable Counter A interrupt Select r
9. Both kinds of timer 0 interrupts can be used in capture mode the timer 0 overflow interrupt is generated whenever a counter overflow occurs the timer O match capture interrupt is generated whenever the counter value is loaded into the TO data register By reading the captured data value in TODATA and assuming a specific value for the timer O clock frequency you can calculate the pulse width duration of the signal that is being input at the TOCAP pin See Figure 10 6 Interrupt Enable Disable TOCON 2 gt IR TOOVF Pending gt IRQO TOINT P3 0 TOCAP Mead Enable Disable Timer O Data Register TOCON 1 TOCON 5 TODATA TOCON 4 Figure 10 6 Simplified Timer 0 Function Diagram Capture Mode 10 8 ELECTRONICS S3F80K5 UM REV1 11 BASIC TIMER and TIMER 0 RESET or STOP Bits 3 2 g Basic Timer Control Register Data Bus Write 1010xxxxB to disable Clear 1 16384 When BTCNT 4 is set after releasing from RESET or STOP mode CPU clock starts Bit 0 Bits 7 6 Bit 2 Data Bus 8 Bit Up Counter TOCNT OVF gt IRQO Timer 0 Overflow R P3 2 TOCK 8 Bit Compatator Timer 0 Buffer Register Match Signal TOCON 3 Timer 0 Data Register TODATA Basic Timer Control Register Data Bus m Timer 0 Control Register NOTES 1 During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic
10. EMBEDDED FLASH MEMORY INTERFACE OVERVIEW The S3F80K5 has an on chip flash memory internally instead of masked ROM The flash memory is accessed by instruction LDC This is a sector erasable and a byte programmable flash User can program the data in a flash memory area any time you want The S3F80K5 s embedded 16K byte memory has two operating features as below Tool Program Mode Refer to the chapter 17 S3F80K5 FLASH MCU User Program Mode Flash ROM Configuration The S3F80K5 flash memory consists of 128sectors Each sector consists of 128bytes So the total size of flash memory is 128x128 bytes 16KB User can erase the flash memory by a sector unit at a time and write the data into the flash memory by a byte unit at a time 16Kbyte Internal flash memory Sector size 128 Bytes 10years data retention Fast programming Time Sector Erase 10ms min Byte Program 32us min Byte programmable User programmable by LDC instruction Sector 128 Bytes erase available External serial programming support Endurance 10 000 Erase Program cycles min Expandable OBPTM On Board Program ELECTRONICS EMBEDDED FLASH MEMORY INTERFACE S3F80K5 UM REV1 11 User Program Mode This mode supports sector erase byte programming byte read and one protection mode Hard Lock Protection The S3F80K5 has the internal pumping circuit to generate high voltage Therefore 12 5V into Vpp TEST pin is not needed To program a fla
11. FMSECL 00H R9 0CCH R10 01H R11 40H WR_BYTE RO 40H WR INSECTOR50 LD LD LD LD LD CALL FMSECH 19H FMSECL 00H R9 55H R10 19H R11 40H WR_BYTE WR INSECTOR128 LD LD LD LD LD WR BYTE1T LDC INC DJNZ LD SBO WR_BYTE LDC INC DJNZ RET FMSECH 40H FMSECL 00H R9 0A3H R10 40H R11 40H RR10 R9 R11 R1 WR_BYTE1 FMUSR 00H RR10 R9 R11 RO WR_BYTE ELECTRONICS User program mode enable Selection programming mode and Start programming Set the base address of sector located in target address to write data The sector 2 s base address is 100H Load data CCH to write Load flash memory upper address into upper register of pair working register Load flash memory lower address into lower register of pair working register Set the base address of sector located in target address to write data The sector 50 s base address is 1900H Load data 55H to write Load flash memory upper address into upper register of pair working register Load flash memory lower address into lower register of pair working register Set the base address of sector located in target address to write data The sector 128 s base address is 4000H Load data A3H to write Load flash memory upper address into upper register of pair working register Load flash memory lower address into lower register of pair working
12. PoPuR 231 Port O Control Register High Byte POCONH 232 Port 0 Control Register Low Byte mem 233 Port 1 Control Register High Byte noo 234 Port 1 Control Register Low Byte PIGONL 285 Port 2 Control Register High Byte P2CONH_ 236 Port Control Register Low Byte Leem 237 Port 2 Pul up Enable Register P2PUR 238 Port 3 Control Register pacon 239 Reserved FOH Port 0 interrupt Enable Register Pont E1H F1H ET 4 2 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS Table 4 1 Mapped Registers Continued Seereeg Mnemonic Decimal Hex mw 24 24 24 24 24 i 24 24 2 R NOTE R NOTE 4 zwee 7 peers e o 50 w Interrupt Priority Register PR 258 FR Rw NOTE You cannot use a read only register as a destination for the instructions OR AND LD or LDB ELECTRONICS 4 3 CONTROL REGISTERS S3F80K5 UM REV1 11 Table 4 2 Mapped Registers Bank1 Set1 Register Name Mnemonic Decimal ge RW Reserved E1H NOTE You cannot use a read only register as a destination for the instructions OR AND LD or LDB HAN R W R W R W R W R W R W R W R W 4 4 ELECTRONICS S3F80K5 UM REV1 11 Bit number s that is are appended to the register name for bit addressing Name of individual Register bit or bit function mnemonic Full register name FLAGS System Flags Register Bit Identi
13. The interrupt is serviced E 2 Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back The content of FLAGS FLAGS prime is copied automatically back to the FLAGS register The fast interrupt status bit in FLAGS is cleared automatically Programming Guidelines Remember that the only way to enable disable a fast interrupt is to set clear the fast interrupt enable bit in the SYM register SYM 1 Executing an El or DI instruction globally enables or disables all interrupt processing including fast interrupts If you use fast interrupts remember to load the IP with a new start address when the fast interrupt service routine ends ELECTRONICS 5 17 S3F80K5 UM REV1 11 INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAMB instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers There are 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide No special I O instructions I O control data registers are mapped directly into the register file Decimal adjustment included in binary coded decimal BCD operations 16 bit word data can be incremented and decremented Flexible instructions for bit addressing rotate
14. 0 user can have the available ISP area If ISP Reset Vector Change Selection Bit 3EH 7 is 1 3EH 6 and 3EH 5 are meaningless 2 If ISP Reset Vector Change Selection Bit 3EH 7 is 0 user must change ISP reset vector address from 0100H to some address which user want to set reset address 0200H 0300H 0500H or 0900H If the reset vector address is 0200H the ISP area can be assigned from 0100H to 01FFH 256bytes If 0300H the ISP area can be assigned from 0100H to 02FFH 512bytes If 0500H the ISP area can be from 0100H to 04FFH 1024bytes If 0900H the ISP area can be from 0100H to 08FFH 2048bytes 3 If ISP Protection Enable Disable Bit is 0 user can t erase or program the ISP area selected by 3EH 1 and 3EH 0 in flash memory 4 User can select suitable ISP protection size by 3EH 1 and 3EH 0 If ISP Protection Enable Disable Bit 3EH 2 is 1 3EH 1 and 3EH 0 are meaningless Table 13 1 ISP Sector Size Smart Option 003EH ISP Size Selection Bit Area of ISP Sector ISP Sector Size A AAA A EE e E o o o 100H 1PFH 256 Bytes 256 Bytes o po 10H 2FFH 512 Bytes 512 Bytes o 1 o 10H 4FFH 1024 Bytes 1024 Bytes o otto 1 100H 8FFH 2048 Bytes 2048 Bytes NOTE The area of the ISP sector selected by smart option bit 3EH 2 3EH 0 can t be erased and programmed by LDC instruction in user program mode ISP RESET VECTOR AND ISP SECTOR SIZE If you use ISP sectors by setti
15. 00H loads the value 70H into the destination general register 02H The user stack pointer register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET S3F80K5_UM_REV1 11 PUSH Push To Stack PUSH Operation Flags Format Examples src SP SP 1 OSP lt src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4FH OAAH SPH 00H and SPL 00H PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register 4FH OAAH stack register OFFH OAAH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value 0000H and general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of register 40H into location OFFFFH and adds this new value to the top of the stack ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET PUSHUD Push User Stack Decrementing PUSHUD Operation Flags Format Example dei erc I
16. 2008 REVISION DESCRIPTIONS Rev 1 00 1 Chapter 4 CONTROL REGISTERS In page 4 4 RESETID register should be changed Reset Indicating Register RESETID In page 4 18 LVDSEL instruction should be changed 7 and 6 LVD Flag Level Selection Bits 0 o LVD FLAG Level 1 90V 0 1 LVD FLAG Level 2 00V O LVD FLAG Level 2 10V 1 LVD FLAG Level 2 20V 2 Chapter 5 INTERRUPT STRUCTURE Interrupt level vector and source is should be changed 15 interrupt sources with 12vectors and 6levels 3 Chapter 14 LOW VOLTAGE DETECTOR In figure 15 1 LVD block diagram should be changed Resistor String IPOR LYD Control Bit smart option 7 03FH r Resistor String STOP In table 14 2 description about LVD_GAPn n 1 4 and GAP of LVD Flags is added 3 The voltage gaps LVD GAPn n 1 4 between LVD and LVD FLAGn n 1 4 have 80mV distribution LVD and LVD FLAGn n 1 4 are not overlapped sol mn Typ Max 3 150 7 4 Chapter 15 ELECTRICAL DATA In table 15 4 description about LVD_GAPn n 1 4 and GAP of LVD Flags is added NOTE The voltage gaps LVD GAPn n 1 4 between LVD and LVD FLAGn n 1 4 have 80mV distribution LVD and LVD FLAGn n 1 4 are not overlapped 5 Chapter 7 CLOCK AND POWER CIRCUIT In page 7 5 power circuit and guide line of VDD is added refer to figure7 5 7 6 and table7 1 REVISION DESCRIPTIONS Rev 1 10 1 Chapter 15 ELECTRICAL DATA In page 15
17. 8 6 Block Diagram for Back Up Mode ccc ceeeeceeeeeeeeeeseeceeeeecaaeeeeaaeseeneeesaeeesaeseeneeeaas 8 9 8 7 Timing Diagram for Back up Mode Input and Released by ND 8 9 8 8 Timing Diagram for Back up Mode Input in Stop mode 8 10 9 1 S3F80K5 I O Port Data Register Format urrrvnannvnnonvvnrnvrvnnnrrnnnnvnnerrnnnnnrrnennnnnenrenenr 9 3 9 2 Pull up Resistor Enable Registers Port O and Port 2 on 9 4 10 1 Basic Timer Control Register BTCON ceccceceeeeeeneeceeeeeceeeeeeaeeseeeeesaeeesaeeeenees 10 2 10 2 Timer 0 Control Register TOCON ceecceeeeeeeeeeeeeeeeeeeeeeeeeaaeeeeaeeseneeesaeessaeeteeeeees 10 5 10 3 Timer 0 DATA Register TODATA non nnnnn cnn rca naar rra 10 5 10 4 Simplified Timer 0 Function Diagram Interval Timer Mode urnrnnnonvnnnnrrnnnnrnnnnnnnrenr 10 6 10 5 Simplified Timer 0 Function Diagram PWM Mode rennnnrrnnnrrnnnnrnnonvvnrnrrrnnnnrnnennnnrenr 10 7 10 6 Simplified Timer 0 Function Diagram Capture Mode arrrnnnrrnannvnnnonrnnnnrrvnnnrnnnnnnnnrnr 10 8 10 7 Basic Timer and Timer 0 Block Diagoram nn nrrn carr nrccanannnnn 10 9 Simplified Timer 1 Function Diagram Capture Mode nerannvnnannvnnnonvvnnnrrvnnnrnnnnnnneenr 11 2 Simplified Timer 1 Function Diagram Interval Timer Mode oooonncccnnccnnncccnnccccancccnns 11 3 11 3 Timer 1 Block Dad ELE 11 4 11 4 Timer 1 Control Register T1CON mannrnnnnvvnrnrrvnnnrnnnnnvnnrrrrennnrrnennnnnenrennsrreennrnssnnnerenn 11
18. ADDRESS SPACE S3F80K5 UM REV1 11 8 Byte Slice Register File Contains 32 16 byte non contiguous 11110XXX 8 Byte Slices working register block RPO 07H R15 00000XXX 00H RO Figure 2 8 Non Contiguous 16 Byte Working Register Block PROGRAMMING TIP Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses 80H through 85H contains the values 10H 11H 12H 13H 14H and 15 H respectively SRPO 80H RPO lt 80H ADD RO R1 RO lt RO Ri ADC RO R2 RO lt RO R2 C ADC RO R3 RO lt RO R3 C ADC RO R4 RO lt RO R4 C ADC RO R5 RO lt RO R5 C The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H 80H lt 80H 81H ADC 80H 82H 80H lt 80H 82H C ADC 80H 83H 80H lt 80H 83H C ADC 80H 84H 80H lt 80H 84H C ADC 80H 85H 80H lt 80H 85H C Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code instead of 12 bytes and its execution time is 50 cycles instead of 36 cycles 2 12 ELECTRONICS S3F
19. Chapter 5 Interrupt Structure OVE va ee de eege A oa bek uekte EEN Interrupt Vector Addresses ooomocccconnoncconnnoccnnnnnccrrnnn nc Enable Disable Interrupt Instructions El DI System Level Interrupt Control Heoteiers nr Interrupt Processing Control Points Peripheral Interrupt Control Registers oooonnccinnccnncccnnoconnnccnnonccnnnrn non nn nano cnn rca nn rana nc System Mode Register GYM Interrupt Mask Register MH Interrupt Priority Register PRI esireket adidas Interrupt Request Register OPO Interrupt Pending Function Typesetter EE R EREET ASEE AAN REEE REUNEA ASEE EEREN R Interrupt Source Polling Sequence cooocccconococonccoconicononannnnccnnnccnn nora nnnn cnc rana rn cnn ranma Interrupt Service ROUtINGS i kran heat item at tt Generating interrupt Vector Addresses oooconnncinicccnonccnnoninonancnoncccnornn nn rn Nesting of Vectored Interrupts AA Instruction Poter UP eree rine aA AEE ia Fast Int rrupt Pr CessIngi u merito ENEE ENEE lirica talca Chapter 6 Instruction Set vi RTE Flags Register FLAGS EE Flag Descriptions srenti i ected Rea ede ce Re karet EE widen tee din Instruction Set Notation anai a nc cnn Gondition G0d s auraen aure A enes Instruction DescrplONS eii ti ti dd S3F80K5 UM REV1 11 MICROCONTROLLER Table of Contents Continued Part I Hardware Descriptions Chapter 7 Clock and Power Circuit MEDIEN Fi tte cotati sa titel ae et ainda del a eed te nd aed tine ead Ae 7 1 S
20. INT5 Enable Bit o Disable interrupt Enable interrupt ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS P2OUTMD port 2 Output Mode Selection Register F3H Seti Bank Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 0 P2 0 Output Mode Selection Bit o Push pull output mode Open drain output mode ELECTRONICS 4 29 CONTROL REGISTERS S3F80K5 UM REV1 11 P2PND Port 2 External Interrupt Pending Register E6H Seti Bank Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 0 P2 0 External Interrupt INT5 Pending Flag Bit Lo No P2 0 external interrupt pending when read P2 0 external interrupt is pending when read NOTE To clear an interrupt pending condition write a 0 to the appropriate pending flag bit Writing a 1 to an interrupt rending flag P2PND 0 7 has no effect 4 30 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS P2PUR Port 2 Pull up Resistor Enable Register EEH Seti Bank Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 0 P2 0 Pull up Resistor Enable Bit o Disable pull up resistor Enable pull up resistor ELECTRONICS 4 31 CONTROL REGISTERS S3F80K5 UM REV1 11 P3CON Port 3 Control Register EFH Seti Bank0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addre
21. If src 1 O and src 0 1then RP1 3 7 lt src 3 7 If src 1 O and src 0 Othen RPO 4 7 lt src 4 7 RPO 3 0 RP1 4 7 lt src 4 7 RP1 3 lt 1 The source data bits one and zero LSB determine whether to write one or both of the register pointers RPO and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected RP0 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src opc src 2 4 31 IM The statement SRP 40H sets register pointer 0 RPO at location OD6H to 40H and register pointer 1 RP1 at location OD7H to 48H The statement SRPO 50H sets RPO to 50H and the statement SRP1 68H sets RP1 to 68H ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET STOP Stop Operation STOP Operation The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 7F Example The statement S
22. LVDCON o0occccncccnnocnononnnonccononnnn non nano cnn rra rar Low Voltage Detector Flag Selection Register LVDSEL Chapter 15 Electrical Data Overview Chapter 16 Mechanical Data Overview Chapter 17 S3F80K5 FLASH MCU Vvs re aa ot A UN roku Acted tat otc ceca dae Operating Mode Characteristics Chapter 18 Development Tools Data ONE iia Target Tee ege dee a di Programming Socket Adapter T BSOKB Target Board ic et OTP MTP Programmer Writer S3F80K5 UM REV1 11 MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 Block Diagram 24 pm 1 3 1 2 Pin Assignment Diagram 24 Pin SOP SDIP Package 1 4 1 3 Pin Circuit Type 1 Poto 1 6 1 4 Pin Circuit Type 3 PO 2 aust dear delar dk 1 7 1 5 Pin Circuit Type 4 D30 arce 1 8 1 6 Pin Cirecuit Type AP at eneeier 1 9 1 7 Pin Circuit Type Pa cri 1 9 2 1 Program Memory Address Space ccocococinncccnncccconccononcncnncccnonn cnn cnn cnn rca rara 2 2 2 2 Smart Optio NEE 2 3 2 3 Internal Register File Organization umsrnnonnvnrorvrnnnrrrnnnvvnrnrrennrnnnnnnnnenrennnrrennnnnnnnnnenn 2 6 2 4 R gister Page Pointer PP sun gu dataene da reana Aaen ri 2 7 2 5 Set 1 Set 2 and Prime Area Register Map 2 9 2 6 8 Byte Working Register Areas Ges 2 10 2 7 Contiguous 16 Byte Working Register Block 2 11 2 8 Non Contiguous 16 Byte Working Register Block 2 12 2 9 16 Bit Register TEE 2 13 2 10 Re gister File Addressing void da utdan 2 14 2 11 Common Working R
23. Operation Flags Format Examples dei erc det AND src This instruction tests selected bits in the destination operand for a logic zero value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 73 r Ir ODC src dst 3 6 74 R R 75 R IR opc dst src 3 6 76 R IM Given RO 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM RO R1 gt RO 0C7H R1 02H Z 0 TM RO OR1 gt RO 0C7H R1 02H register 02H 23H Z 0 TM 00H 01H gt Register OOH 2BH register 01H 02H Z 0 TM 00H 001H gt Register OOH 2BH register 01H 02H register 02H 23H Z 0 TM 00H 454H gt Register OOH 2BH Z 1 In the first example if working register RO contains the value OC7H 11000111B and register R1 the value 02H 00000010B the statement TM RO R1 tests bit one in the destination register for a 0 value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of t
24. R3 04H LDE RO 1000H RR2 RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H R3 04H LDC R0 1104H RO lt contents of program memory location 1104H RO 88H LDE R0 1104H RO lt contents of external data memory location 1104H RO 98H LDC note 1105H RO 11H contents of RO is loaded into program memory location 1105H 1105H lt 11H LDE 1105H RO 11H contents of RO is loaded into external data memory location 1105H 1105H lt 11H NOTE These instructions are not supported by masked ROM type devices ELECTRONICS 6 53 INSTRUCTION SET S3F80K5_UM_REV1 11 LDCD LDED Load Memory and Decrement LDCD LDED det ar Operation Flags Format Examples dst lt src rr rr 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD references program memory and LDED references external data memory The assembler makes Irr an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory location 1033H OCDH and external data
25. S3F80K5 UM REV1 11 CONTROL REGISTERS P1CONL Port 1 Control Register Low Byte EBH Seti Bank0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 6 P1 3 Mode Selection Bits O o c MOSinputmodes 1 Open arain output mode o EDEA Push pull output mode C MOS input with pull up mode 5 and 4 P1 2 Mode Selection Bits o o EMOS impar made 0 fi Opera opt made o i o Push put pat made ooo 3 and 2 P1 1 Mode Selection Bits o 0 omo imputa Po fopendranommtmos Pi fo postea pat mode SSSCSCSC C S S S 1 and 0 P1 0 Mode Selection Bits 0 0 CMOS inputmode 1 Open drain outputmode Pa e Push pull output mode C MOS input with pull up mode ELECTRONICS 4 25 CONTROL REGISTERS S3F80K5 UM REV1 11 P1OUTPU port 1 Output Pull up Resistor Enable Register F2H Seti Bank Bit Identifier 27316 5 a 3 2 1140 0 0 0 0 0 0 0 Reset Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P1 7 Output Mode Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 6 P1 o Output Mode Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 5 P1 al Output Mode Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor A P1 A Output Mode Pull up Resistor Enable B
26. SPL that is used for system stack operations After a reset the SPL value is undetermined Because only internal memory 256 byte is implemented in The S3F80K5 the SPL must be initialized to an 8 bit value in the range 00 FFH 2 20 ELECTRONICS S3F80K5 UM REV1 11 ADDRESS SPACE e PROGRAMMING TIP Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD SPL 0FFH SPL lt FFH Normally the SPL is set to OFFH by the initialization routine PUSH PP Stack address OFEH lt PP PUSH RPO Stack address OFDH lt RPO PUSH RP1 Stack address OFCH lt RP1 PUSH R3 Stack address OFBH lt R3 POP R3 R3 lt Stack address OFBH POP RP1 RP1 lt Stack address OFCH POP RPO RPO lt Stack address OFDH POP PP PP lt Stack address OFEH ELECTRONICS 2 21 S3F80K5 UM REV1 11 ADDRESSING MODES ADDRESSING MODES OVERVIEW The program counter is used to fetch instructions that are stored in program memory for execution Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 S3F8 series instruction set supports seven explicit addressing modes Not al
27. and shift operations Data Types The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit Register Addressing To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data or 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Section 2 Address Spaces Addressing Modes There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Section 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET S3F80K5_UM_REV1 11 Table 6 1 Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst src Load LDB dst src Load bit LDE dst src Load external data memory LDC dst src Load program memory LDED dst src Load external data memory and decrement LDCD dst src Load program memory and decrement LDEI dst src Load external data memory and increment LDCI det src Load program memory and increment LDEPD det src Load external data memory with pre decrement LDCPD d
28. are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external data memory is accessed NOTE LDE command is not available because an external interface is not implemented for the S3F80K5 Figure 3 9 Indexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES S3F80K5 UM REV1 11 DIRECT ADDRESS MODE DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Used Upper Address Byte Lower Address Byte E LSB Selects Program Memory or Data Memory OPCODE 0 Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external data memory is accessed LDE command is not available because an external interface is not implemented for the S3F80K5 Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS S3F80K5 UM REV1 11 ADDRE
29. register Write data A3H at flash memory location User Program mode disable Write data written by R9 at flash memory location 13 15 EMBEDDED FLASH MEMORY INTERFACE READING S3F80K5 UM REV1 11 The read operation starts by LDC instruction The program procedure in user program mode 1 Load a flash memory upper address into upper register of pair working register 2 Load a flash memory lower address into lower register of pair working register 3 Load receive data from flash memory location area on LDC instruction by indirectly addressing mode PROGRAMMING TIP Reading LD LOOP LDC INC CP JP 13 16 R2 03H R3 00H RO GRR2 R3 R3 0FFH NZ LOOP Load flash memory s upper address to upper register of pair working register Load flash memory s lower address to lower register of pair working register Read data from flash memory location Between 300H and 3FFH ELECTRONICS S3F80K5 UM REV1 11 EMBEDDED FLASH MEMORY INTERFACE HARD LOCK PROTECTION User can set Hard Lock Protection by writing 0110B in FMCON7 4 This function prevents the changes of data in a flash memory area If this function is enabled the user cannot write or erase the data in a flash memory area This protection can be released by the chip erase execution in the tool program mode In terms of user program mode the procedure of setting Hard Lock Protection is following that In tool mo
30. to the corresponding pending bit location in the source s mode or control register In the S3F80K5 interrupt structure pending conditions for all interrupt sources except the timer O overflow interrupt the timer 1 overflow interrupt and the counter A borrow interrupt must be cleared by the interrupt service routine 5 14 ELECTRONICS S3F80K5 UM REV1 11 INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows No oO Fa NS A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks the interrupt level of source The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request can be serviced the following conditions must be met Interrupt processing must be globally enabled El SYM 0 1 The interrupt level must be enabled IMR register unmask The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register If all of the above conditions are met the interrupt reque
31. 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 6 P0 3 INT3 Mode Selection Bits 0 o C MOS input mode interrupt on falling edges fo 1 C MOS input mode interrupt on rising and falling edges EJEA Push pull output mode C MOS input mode interrupt on rising edges 5 and 4 P0 2 INT2 Mode Selection Bits olo C MOS input mode interrupt on falling edges fof 1 C MOS input mode interrupt on rising and falling edges 1 KN Push pull output mode C MOS input mode interrupt on rising edges 3 and 2 P0 1 INT1 Mode Selection Bits 0 o C MOS input mode nterupt on tating sages Sd 0 emos input mode interrupt on rising and fling edges Pr fo Push puoutputmode 1 and 0 P0 0 INTO Mode Selection Bits ESEJ C MOS input mode interrupt on falling edges fo 1 C MOS input mode interrupt on rising and falling edges HET Push pull output mode C MOS input mode interrupt on rising edges NOTES 1 The INT3 INTO external interrupts at P0 3 P0 0 are interrupt level IRQ6 Each interrupt has a separate vector address 2 You can assign pull up resistors to individual port O pins by making the appropriate settings to the POPUR register POPUR 3 POPUR 0 4 20 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS POINT Port 0 External Interrupt Enable Register F1H Seti Bank Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Address
32. 1 to this bit during normal operation a system malfunction may occur 2 Except for TOCNTH TOCNTL IRQ T1CNTH T1CNTL and BTCNT which are read only all registers in set 1 are read write addressable 3 You cannot use a read only register as a destination field for the instructions OR AND LD and LDB 8 16 ELECTRONICS S3F80K5 UM REV1 11 RESET Table 8 3 Set 1 Bank 1 Register Values After Reset RegisterName Mnemonic Address BitValuesAfterReset Dec Hex 7 6 5 4 3 2 1 0 LVD Control Register LVDCON 224 EOH J 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Flash Memory Sector Address Register FMSECH 236 ECH High Byte Flash Memory Sector Address Register FMSECL 237 EDH Low byte Flash Memory User Programming FMUSR 238 EEH Enable Register Flash Memory Control Register FMCON 239 EFH 0 Reset Indicating Register RESETID Refer to the section 4 control registers LVD Flag Level Selection Register LVDSEL 243 FiH 0 0 PORT1 Output Mode Pull up Enable P1OUTPU 244 F2 Register PORT2 Output Mode Selection P2OUTMD 245 F3H Register PORT3 Output Mode Pull up Enable P3OUTPU 246 F4H Register ELECTRONICS 8 17 RESET S3F80K5 UM REV1 11 Table 8 4 Reset Generation According to the Condition of Smart Option Smart optio
33. 13 3 Flash Memory Control Register FMCON The bit 0 of FMCON register FMCON 0 is a bit for the operation start of Erase and Hard Lock Protection Therefore operation of Erase and Hard Lock Protection is activated when you set FMCON O to 1 If you write FMCON 0 to 1 for erasing CPU is stopped automatically for erasing time min 10ms After erasing time CPU is restarted automatically When you read or program a byte data from or into flash memory this bit is not needed to manipulate FLASH MEMORY USER PROGRAMMING ENABLE REGISTER FMUSR The FMUSR register is used for a safe operation of the flash memory This register will protect undesired erase or program operation from malfunctioning of CPU caused by an electrical noise After reset the user programming mode is disabled because the value of FMUSR is 00000000B by reset operation If necessary to operate the flash memory you can use the user programming mode by setting the value of FMUSR to 10100101B The other value of 10100101B user program mode is disabled Flash Memory User Programming Enable Register FMUSR EEH Get Bank 1 R W Flash Memory User Programming Enable Bits 10100101 Enable user programming mode Other values Disable user programming mode Figure 13 4 Flash Memory User Programming Enable Register FMUSR ELECTRONICS 13 5 EMBEDDED FLASH MEMORY INTERFACE S3F80K5 UM REV1 11 FLASH MEMORY SECTOR ADDRESS REGISTERS There are two secto
34. 2 osp lt IP IP lt PC PC IP IP lt IP 2 This instruction is useful when implementing threaded code languages The contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows one example of how to use an ENTER statement Before After Address Data Address Data IP IP 0043 Address Data Address Data PC Enter PC 0110 40 Enter Address H 41 Address H Address L 42 Address L sp Address H SP 0020 43 Address H 20 IPH 00 110 Routine 21 IPL 50 22 Data Memory i 22 Data Memory Stack Stack ELECTRONICS 6 41 INSTRUCTION SET S3F80K5_UM_REV1 11 EXIT exit EXIT Operation Flags Format Example IP lt SP SP lt SP 2 PC IP IP lt IP 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 14 internal stack 2F 16 internal stack The diagram below shows one e
35. 3 1 Fast Interrupt Status Flag Bit FIS Interrupt return IRET in progress when read Fast interrupt service routine in progress when read o 0 Bank Address Selection Flag Bit BA Bank 0 is selected 1 Bank 1 is selected 4 10 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS FMCON Flash Memory Control Register EFH Seti Bank Reset Value 0 0 0 0 0 Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Flash Memory Mode Selection Bits 0101 Programming mode 1010 Erase mode 0110 Hard Lock mode NOTE Others Not used for S3F80K5 Not used for S3F80K5 Ca l 0 Flash Operation Start Bit available for Erase and Hard Lock mode only Operation stop 1 Operation start auto clear bit NOTE Hard Lock mode is one of the flash protection modes Refer to page 15 18 ELECTRONICS 4 1 wh CONTROL REGISTERS S3F80K5 UM REV1 11 FMSECH Flash Memory Sector Address Register High Byte ECH Seti Bank Bit Identifier 27316 5 a 3 2 1140 0 0 0 0 0 0 0 0 Reset Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory Sector Address High Byte Note The high byte flash memory sector address pointer value is the higher eight bits of the 16 bit pointer address FMSECL Flash Memory Sector Address Register Low Byte EDH Seti Bank1 Bit Identifier 7 6 5s ajs 2 a oo 0 0 0 0 0 0 0 0 R
36. 5 11 5 Timer 1 Registers T1CNTH T1CNTL TIDATAH T1DATAL i oa 11 6 S3F80K5 UM REV1 11 MICROCONTROLLER xi List of Figures Continued Figure Title Page Number Number 12 1 Counter A Block Diagramm 12 2 12 2 Counter A Control Register CACON mannrnnenrnnnnrrnnnnrnnnnvnnennrrvnnnrnnnnnenrrrrennnrnennnnenennne 12 3 12 3 Counter A Registers A 12 3 12 4 Counter A Output Flip Flop Waveforms in Repeat Mode 12 5 13 1 Program Memory Address Space cccococcciniccnnncccconccononcncnnccconnn conca cnn rana 13 2 13 2 Smart 0 le NEE 13 3 13 3 Flash Memory Control Register FMCON rrnrrrnnnrrnnnnvnnrnrvnnnrrvnnnnnnnenrennnrrnennrnnennennn 13 5 13 4 Flash Memory User Programming Enable Register EMUSR 13 5 13 5 Flash Memory Sector Address Register FMSECH rrrnnrnnnnnnrrnnnnnvnnrnrvnnnrrnnnnrnnnennenn 13 6 13 6 Flash Memory Sector Address Register EMSGECL 13 6 13 7 Sector Configurations in User Program Mode 13 7 13 8 Sector Erase Flowchart in User Program Mode ooooooccnnccccocccnnoocnnoncccnoncccnnnc nano nnnancccnn 13 8 13 9 Byte Program Flowchart in a User Program Mode 13 12 13 10 Program Flowchart in a User Program Mode 13 13 14 1 Low Voltage Detect LVD Block Diagramm 14 3 14 2 Low Voltage Detect Control Register LVDCON cnn 14 4 14 3 Low Voltage Detect Flag Selection Register VDGEL esenee 14 4 15 1 Stop Mode Release Timing When Initiated by an External Interrupt o 15 6 15 2 Stop Mode Rele
37. 6 and 2 7 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline we recommend that RPO point to the lower slice and RP1 point to the upper slice see Figure 2 6 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 7 RPO points to the upper slice and RP1 to the lower slice Because a register pointer can point to the either of the two 8 byte slices in the working register block you can define the working register area very flexibly to support program requirements PROGRAMMING TIP Setting the Register Pointers SRP 70H RPO lt 70H RP1 lt 78H SRP1 48H RPO lt nochange RP1 lt 48H SRPO 0A0H RPO lt AOH RP1 lt nochange CLR RPO RPO lt 00H RP1 lt nochange LD RP1 0F8H RPO lt nochange RP1 lt OF8H Register File Contains 32 8 Byte Slices 00001 XXX 16 byte e contiguous working 00000XXX register block RPO Figure 2 7 Contiguous 16 Byte Working Register Block ELECTRONICS 2 11
38. ELECTRONICS S3F80K5 UM REV1 11 ELECTRICAL DATA Table 15 2 D C Electrical Characteristics Continued Ta 25 Cto 85 C Vpp 1 65 V to 3 6 V Parameter Symbol Conditions Mn Output Low Vout Vop 1 85 V lo 8MA Kee Port 3 1 only Vop 1 85 V Io 5mA P3 0 and P2 0 Von 1 85 V Io 2mA Porto Port1 Input High lik Vin Von Gel All input pins except yo and Xout Input Low lod VIN 0V Pearse Caen All input pins except gt and Xout Vin 0 Y Xin Leakage Current All output pins Output Low ho Vour 0V Leakage Current All output pins Pull Up Resistors Vin 0 V Vpp 2 35 V Ta 25 G Ports 0 3 Feedback Vin Vpn Vpp 2 35V Resistor ELECTRONICS 15 3 ELECTRICAL DATA S3F80K5 UM REV1 11 Table 15 2 D C Electrical Characteristics Continued Ta 259Cto 85 Vpp 1 65 V to 3 6 V Max Unit Supply Current loo Operating Mode note2 6 mA note1 Vop 3 6 V 8 MHz crystal Ipp2 Idle Mode 2 Vpp 3 6 V 8 MHz crystal 8 uA Iren Operating Mode 3 mA 4 MHz crystal Idle Mode E 1 Vpp 3 6 V 4 MHz crystal NOTES 1 Supply current does not include current drawn through internal pull up resistors or external output current loads 2 IDD1 includes flash operating current flash erase write read operation 3 The adder by LVD on current in back up mode is 18uA Conditions Min Typ Max Unit LVD on current in back up mode Vpp 1 65V 18 35 uA
39. Enable Bit Timer 2 Match or Overflow Disable mask 1 Enable un mask 2 Interrupt Level 2 IRQ2 Enable Bit Counter A Interrupt Disable mask le Enable un mask 1 Interrupt Level 1 IRQ1 Enable Bit Timer 1 Match or Overflow Disable mask 1 Enable un mask 0 Interrupt Level 0 IRQ0 Enable Bit Timer 0 Match or Overflow Disable mask 1 Enable un mask ELECTRONICS 4 1 Q CONTROL REGISTERS S3F80K5 UM REV1 11 IPH Instruction Pointer High Byte DAH Seti Bank Bit Identifier 7 6 5 4 3 2 1 0 Reset Value D D D D D D x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 1 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address IP15 IP8 The lower byte of the IP address is located in the IPL register DBH IPL instruction Pointer Low Byte DBH Gett Bank Reset Value xX X x X xX x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 0 Register addressing mode only Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located in the IPH register DAH ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS IPR Interrupt Priority Register FFH Seti Bank Reset Value x X x xX xX x x x Rea
40. For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero For operations that test register bits and for shift and rotate operations the Z flag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is seldom accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits
41. LOOP is the label of a relative address SRP O0COH DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In the example working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION SET S3F80K5_UM_REV1 11 El Enable Interrupts El Operation Flags Format Example SYM 0 lt 1 An El instruction sets bit zero of the system mode register SYM 0 to 1 This allows interrupts to be serviced as they occur assuming they have highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the El instruction No flags are affected Bytes Cycles Opcode Hex opc 1 4 OF Given SYM OOH EI If the SYM register contains the value OOH that is if interrupts are currently disabled the statement El sets the SYM register to 01H enabling all interrupts SYM O is the enable bit for global interrupt processing ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET ENTER Enter ENTER Operation SP SP
42. Mode Enable FMCON lt lt 01010000B Mode Select LDC 4 ERR n R data Write data at flash FMUSR 00H User Program Mode Disable Select Bank0 Finish 1 BYTE Writing Figure 13 9 Byte Program Flowchart in a User Program Mode 13 12 ELECTRONICS S3F80K5 UM REV1 11 EMBEDDED FLASH MEMORY INTERFACE Select Bank FMSECH High Address of Sector Set Secotr Base Address FMSECL lt Low Address of Sector R n High Address to Write Set Address and Data R n 1 lt Low Address to Write R data 8 bit Data FMUSR 0A5H User Program Mode Enable FMCON lt 01010000B Mode Select Write data at flash LDC 4 CERR n R data User Program Mode Disable YES Write again NO NO Same Sector FMUSR lt 00H User Program Mode Disable Check Sector YES Select Bank0 ontinuous address Check Address Finish Writing YES n 1 3 Increse Address INC R YES E R data 4 New 8 bit Data 33 Update Data to Write Figure 13 10 Program Flowchart in a User Program Mode ELECTRONICS 13 13 EMBEDDED FLASH MEMORY INTERFACE S3F80K5 UM REV1 11 PROGRAMMING TIP Programming Case1 1 Byte Programming WR_BYTE SB1 LD LDC LD SBO Write data AAH to destination address 4010H FMUSR 0A5H User program mode enable FMCON 01010000B _ Selection programming mode FMSECH 40H Set the base address of sector 4000H FMSECL 00H R9 0AAH Load data A
43. P0 4 Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 3 P0 3 Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 2 P0 2 Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 1 PO Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 0 PO o Pull up Resistor Enable Bit Disable pull up resistor Enable pull up resistor o ELECTRONICS 4 2 Q CONTROL REGISTERS S3F80K5 UM REV1 11 P1CONH Port 1 Control Register High Byte EAH Seti Bank0 Reset Value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 6 P1 7 Mode Selection Bits 0 o C MOSinputmode 1 Open drain outputmode ESEA Push pull output mode C MOS input with pull up mode 5 and 4 P1 6 Mode Selection Bits o 0 EMOS impar made ro fi Opera pat made o i o Pust putoutputmede ooo 3 and 2 P1 5 Mode Selection Bits oo cMosinpitmeds Po fopendranommt mos Pi fo postea pat made oS 1 and 0 P1 4 Mode Selection Bits 0 0 CMOSimutmode 1 Open drain outputmode HET Push pull output mode C MOS input with pull up mode NOTE P1CONH is available in case of S3F80K5 s 32 pin not in 28 pin P1CONH s reset value is OFFH After reset initial values of port1 4 7 become CMOS input with pull up mode 4 24 ELECTRONICS
44. Seti Bank Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Not used for S3F80K5 4 and 3 CPU Clock System Clock Selection Bits 1 HOGGE ofr foss o A gt gt gt 2 0 Subsystem Clock Selection Bits 2 1 0 1 NotusedforsaFsoKs o Other value Select main system clock MCLK NOTES 1 After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 2 These selection bits CLKCON 0 1 2 are required only for systems that have a main clock and a subsystem clock The S3F80K5 uses only the main oscillator clock circuit For this reason the setting 101B is invalid 4 8 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS EMT External Memory Timing Register NOTE FEH Seti Bank0 Reset Value 0 1 1 1 1 1 0 Read Write R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 External WAIT Input Function Enable Bit Ea Disable WAIT input function for external device Enable WAIT input function for external device 6 Slow Memory Timing Enable Bit o Disable slow memory timing Enable slow memory timing 5 and 4 Program Memory Automatic Wait Control Bits No wait Wait one cycle KE CIES 1 0 Wait wo age 3 and 2 a Memory Automatic Wait Control Bits Dat SERA ros Wat once SCSC C S S SC
45. Symbot Gondiions min Se max unn mm mo v em so fv 15 12 ELECTRONICS S3F80K5 UM REV1 11 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3F80K5 micro controller is currently available in a 24 pin SOP and SDIP package 10 30 0 30 7 50 0 20 0 85 0 20 15 74 MAX 15 34 0 20 2 50 MAX o S o m A lous 0 10 0 38 0 05 NOTE Dimensions are in millimeters Figure 16 1 24 Pin SOP Package Mechanical Data ELECTRONICS MECHANICAL DATA S3F80K5 UM REV1 11 24 SDIP 300 6 40 0 20 23 35 MAX 22 95 0 20 PE Y 1 70 NOTE Dimensions are in millimeters x lt x Es Q te 3 30 0 30 Figure 16 2 24 Pin SDIP Package Mechanical Data 16 2 ELECTRONICS S3F80K5 UM REV1 11 S3F80K5 FLASH MCU S3F80K5 FLASH MCU OVERVIEW The S3F80K5 single chip CMOS microcontroller is the Flash MCU It has an on chip Flash MCU ROM The Flash ROM is accessed by serial data format NOTE This chapter is about the Tool Program Mode of Flash MCU If you want to know the User Program Mode refer to the chapter 13 Embedded Flash Memory Interface ELECTRONICS 17 1 S3F80K5 FLASH MCU S3F80K5 UM REV1 11 Vss O VDD Xin P2 0 INT5 Xout P3 1 REM TOCK TEST P3 0 TOPWM TOCAP T1CAP SDAT P0 0 INTO S3C80K5 P1 7 SCLK PO 1 INT 1 P1 6 nRESET P0 2 INT2 24 SOP SDIP P1 5 P0 3 INT3 TOP WIEW P1 4 P0 4 INT4 P1 3 PO 5 INT4 P1 2 PO 6 INT4 P1 1 PO 7 INT4 P1 0
46. TOCAP or match output Timer 0 overflow interrupt IRQO vector FAH and match capture interrupt IRQO vector FCH generation Timer 0 control register TOCON D2H Set 1 Bank0 R W NOTE The CPU clock should be faster than basic timer clock and timer 0 clock ELECTRONICS 10 1 BASIC TIMER and TIMER 0 S3F80K5 UM REV1 11 BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watch dog timer function lt is located in Set 1 and Bank0 address D3H and is read write addressable using register addressing mode A reset clears BTCON to 00H This enables the watch dog function and selects a basic timer clock frequency of fOSC 4096 To disable the watch dog function you must write the signature code 1010B to the basic timer register control bits BTCON 7 BTCON 4 For improved reliability using the watch dog timer function is recommended in remote controllers and hand held product applications Basic Timer Control Register BTCON D3H Set 1 Bank 0 R W Watch dog Timer Enable Bits Divider Clear Bit for BT and TO 1010B Disable watch dog function 0 No effect Others Enable watch dog function 1 Clear both dividers Basic Timer Counter Clear Bits 0 No effect 1 Clear BTCNT Basic Timer Input Clock Selection Bits 00 fosc 4096 01 fosc 1024 10 fosc 128 11
47. This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally is a jump to IRET at address FFH This causes the instruction pointer to be loaded with 100H again and the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H OH FFH 100H Interrupt Service Routine JP to FFH FFFFH In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last two instructions The IRET cannot be immediately proceeded by a clearing of the interrupt status as with a reset of the IPR register ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET JP Jump JP JP Operation Flags Format 1 Examples cc dst Conditional dst Unconditional If cc is true PC lt dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PG No flags are affected Bytes Cycles Opcode Addr Mode 2 Hex dst dst 3 8 ccD DA cc 0to F opc dst 2 8 30 IRR NOTES 1 The 3 byte format is used for a conditional jump
48. Time Ta 25 C to 85 C Vpp 3 6 V est conaion rm Le Lo Main crystal fosc gt 400 kHz Main ceramic Oscillation stabilization occurs when Vpp is equal to the minimum oscillator voltage range External clock Xin input High and Low width tx txp main system Oscillator tat When released by a reset note 2 ogo Im stabilization wait NOTES 1 fosc is the oscillator frequency 2 The duration of the oscillation stabilization time war when it is released by an interrupt is determined by the setting in the basic timer control register BTCON 15 10 ELECTRONICS S3F80K5 UM REV1 11 ELECTRICAL DATA fosc Main Oscillator Frequency Minimun Instruction Clock 2 MHz 8 MHz 1 5MHz 6 MHz 1MHz 4 MHz 500 kHz 2 MHz 1 MHz 400 kHz Supply Voltage V Minimun Instruction Clock 1 4n x oscillator frequency n 1 2 8 or 16 A 1 65 V 8 MHz Figure 15 6 Operating Voltage Range of S3F80K5 Table 15 10 AC Electrical Characteristics for Internal Flash ROM Ta 25 C to 85 C o a s o ms NOTES 1 The programming time is the time during which one byte 8 bit is programmed 2 The Sector erasing time is the time during which all 128 bytes of one sector block is erased 3 Inthe case of S3F80K5 the chip erasing is available in Tool Program Mode only ELECTRONICS 15 11 ELECTRICAL DATA S3F80K5 UM REV1 11 Table 15 11 ESD Characteristics Parameter
49. and the 2 byte format for an unconditional jump 2 Inthe first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL_W gt LABEL W 1000H PC 1000H JP 00H gt PC 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement JP C LABEL_W replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement JP 00 replaces the contents of the PC with the contents of the register pair 00H and 01H leaving the value 0120H ELECTRONICS 6 47 INSTRUCTION SET S3F80K5_UM_REV1 11 JR Jump Relative JR Operation Flags Format Example cc dst If cc is true PC lt PC dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See list of condition codes The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte followi
50. ara osn x x x x x x o o Register oe L aeo lfaefosmfififofofo RegisterPomert Pts oma fofolr Location D8H SPH is not mapped interrupt Request Register Read Onyy ma 220 ocn o o o o o o o o System Mode Register SYM x Xx x Register Page Pointer PP Port 0 Data Register Reserve Port 2 Data Register Port 3 Data Register pm eezr esm o oj o 1 1 Reserved Port 2 Interrupt Enable Register Port 2 Interrupt Pending Register Port 0 Pull up Enable Register Port 0 Control Register High Byte E8 Port 0 Control Register Low Byte E9 ELECTRONICS 8 15 RESET S3F80K5 UM REV1 11 Table 8 2 Set 1 Bank 0 Register Values After Reset Continued Registek Name Mismanie Address Bit Values After Reset Dee Hex 7 6 5 4 3 2 110 Por 2 Control Register Low Bye P2CONL 237 en o o o o o o o o Por 2 Pulbup Enable Register Parun 28 eEH o o o o olo o o Pors Gonrol Regstr Pacom aaa en o o olo ololo o Por Ointerupt Enable Register PONT 21 em o o o o o o o o Por Interupt Pending Register POPND 2e2 Fam o o o o o o o o Counter A Control Register cacon 263 Fam o Timer 1 Counter Register High Byte F6H roto fo fo lo Basic Timer Counter BTCNT 253 External Memory Timing Register E Interrupt Priority Register IPR 255 FF NOTES 1 Although the SYM register is not used SYM 5 should always be 0 If you accidentally write a
51. be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 63 r Ir opc src dst 3 6 64 R R 65 R IR opc dst src 3 6 66 R IM Given RO 0C7H R1 02H R2 12H register 00H 2BH register 01H 02H and register 02H 23H TCM RO R1 RO 0C7H R1 02H Z in TCM RO OR1 RO 0C7H R1 02H register 02H 23H Z 0 TCM 00H 01H gt gt gt Register 00H 2BH register 01H 02H Z 1 TCM 00H 01H Register OOH 2BH register 01H 02H register 02H 23H Z 1 TCM 00H 34 gt Register OOH 2BH Z 0 In the first example if working register RO contains the value OC7H 11000111B and register R1 the value 02H 00000010B the statement TCM RO R1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET TM Test Under Mask TM
52. by making the appropriate setting the port 3 control register P3CON Figure 9 2 Pull up Resistor Enable Registers Port 0 only 9 4 ELECTRONICS S3F80K5 UM REV1 11 BASIC TIMER and TIMER 0 BASIC TIMER and TIMER 0 OVERVIEW The S3F80K5 has two default timers the 8 bit basic timer and the 8 bit general purpose timer counter The 8 bit timer counter is called timer 0 BASIC TIMER BT You can use the basic timer BT in two different ways As a watch dog timer to provide an automatic reset mechanism in the event of a system malfunction To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release The functional components of the basic timer block are Clock frequency divider fosc divided by 16384 4096 1024 or 128 with multiplexer 8 bit basic timer counter BTCNT FDH Set 1 Bank0 Read only Basic timer control register BTCON D3H Set 1 Bank0 R W TIMER 0 Timer 0 has three operating modes one of which you select using the appropriate TOCON setting Interval timer mode Capture input mode with a rising or falling edge trigger at the P3 0 pin PWM mode Timer 0 has the following functional components Clock frequency divider fosc divided by 4096 256 or 8 with multiplexer External clock input pin TOCK 8 bit timer 0 counter TOCNT 8 bit comparator and 8 bit reference data register TODATA 1 0 pins for capture input
53. fosc 16384 Figure 10 1 Basic Timer Control Register BTCON 10 2 ELECTRONICS S3F80K5 UM REV1 11 BASIC TIMER and TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watch dog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by setting BTCON 7 BTCON 4 to any value other than 1010B The 1010B value disables the watch dog function A reset clears BTCON to 00H automatically enabling the watch dog timer function A reset also selects the CPU clock as determined by the current CLKCON register setting divided by 4096 as the BT clock A reset is generated whenever the basic timer overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occurring To do this the BTCNT value must be cleared by writing a 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter BTCNT is always broken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset
54. four bits have the same effect as 4 bit working register addressing As shown in Figure 2 13 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address The three low order bits of the complete address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address OABH 10101011B RPO RP1 Selects RPO or RP1 These address Address bits indicate register addressing 8 bit logical 8 bit working tPrfofol TTT Les Three low Register pointer order bits provides five high order bits TT TTT tty fi 8 bit physical address Figure 2 14 8 Bit Working Register Addressing 2 18 ELECTRONICS S3F80K5 UM REV1 11 ADDRESS SPACE 8 bit address from instruction LD R11 R2 Specifies working register addressing Register address OABH
55. from user System from user System nRESET LED This LED is OFF when the Reset switch is ON IDLE LED This is LED is ON when the evaluation chip S3E80KB is in idle mode STOP LED This LED is ON when the evaluation chip S3E80KB is in stop mode ELECTRONICS 18 5 DEVELOPMENT TOOLS S3F80K5 UM REV1 11 P2 3 INT8 P2 4 INT9 CINO P3 0 TOPWM TOCAP P3 1 REM VDD Vss XOUT P2 2 INT7 P2 1 INT6 P2 0 INT5 P4 0 P4 1 P4 2 P4 3 XIN PO 7 INT4 TEST PO 6 INT4 P2 5 INT9 CIN1 PO 5 INT4 P2 6 INT9 CIN2 PO 4 INT4 RESET PO 3 INT3 P3 4 PO 2 INT2 P3 5 PO 1 INT1 SCLK P2 7 INT9 CIN3 P0 0 INTO SDAT P1 0 P4 4 P3 2 TOCK P4 5 P3 3 T1CAP T2CAP P4 6 P4 7 P1 7 P1 1 P1 6 P1 2 P1 5 P1 3 P1 4 N C N C N C N C N C N C OMONOa AWD O o 3 3 o O H o did Uld 0S NOTE N C means No Connection Figure 18 3 50 Pin Connector Pin Assignment for user System Target Board User System J2 al 2 I 3 5 Q Oo 3 5 oO 2 Oo 10 uuo00 did Uld 0S Figure 18 4 TB80KB Probe Adapter Cable 18 6 ELECTRONICS S3F80K5 UM REV1 11 ELECTRICAL DATA Third parties for Development Tools SAMSUNG provides a complete line of development tools for SAMSUNG s microcontroller With long experience in developing MCU systems our third parties are leading companies in the tool s technology SAMSUNG In circuit emulator solution covers a wide range of capabilities and prices from a low cost ICE to a complete system wi
56. globally or by a specific interrupt level and source The system level control points in the interrupt structure are therefore e Global interrupt enable and disable by El and DI instructions or by a direct manipulation of SYM 0 e Interrupt level enable disable settings IMR register e Interrupt level priority settings IPR register e Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing the part of your application program that handles the interrupt processing be sure to include the necessary register file address register pointer information El Interrupt Request Register KC Read only nRESET f R Interrupt Priority Vector Register Interrupt Cycle IRQO IRQ7 Interrupts Interrupt Mask Register Global Interrupt Control El DI or SYM 0 manipulation Figure 5 4 Interrupt Function Diagram ELECTRONICS 5 7 INTERRUPT STRUCTURE S3F80K5 UM REV1 11 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by that peripheral See Table 5 3 Table 5 3 Vectored Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s in Set 1 Bank Timer 0 match capture or TOCON see Note D2H Bank0 Timer 0 overflow TODATA D1H Timer 1 match capture or IRQ1 T1CON see Note FAH Banko Timer 1 overflow T1DATAH T1
57. gt Register 01H OBCH CandS 1 V 0 In the first example if working register R1 contains the value 12H and if register R2 contains the value 03H the statement SUB R1 R2 subtracts the source value 03H from the destination value 12H and stores the result OFH in destination register R1 6 82 ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET SWAP SWAP Operation Flags Format Examples Swap Nibbles dst dst 0 3 lt dst 4 7 The contents of the lower four bits and upper four bits of the destination operand are swapped C Undefined Z Set if the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 FO R F1 IR Given Register OOH 3EH register 02H 03H and register 03H OA4H SWAP 00H gt Register OOH OE3H SWAP 02H gt Register 02H 03H register 03H 4AH In the first example if general register OOH contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and upper four bits nibbles in the 00H register leaving the value OE3H 11100011B ELECTRONICS 6 83 INSTRUCTION SET S3F80K5_UM_REV1 11 TCM test Complement Under Mask TCM Operation Flags Format Examples 6 84 dei erc NOT det AND src This instruction tests selected bits in the destination operand for a logic one value The bits to
58. is for LVD_FLAG detection LVD LVD circuit supplies two operating modes by one comparator back up mode input and system reset input The S3F80K5 can enter the back up mode and generate the reset signal by the LVD level note1 detection using LVD circuit When LVD circuit detects the LVD level in falling power S3F80K5 enters the Back up mode Back up mode input automatically creates a chip stop state When LVD circuit detects the LVD level in rising power the system reset occurs When the reset pin is at a high state and the LVD circuit detects rising edge of Vpp on the point Vi yp the reset pulse generator makes a reset pulse and system reset occurs This reset by LVD circuit is one of the S3F80K5 reset sources Refer to the page 8 3 for more LVD FLAG The other comparator s output makes LVD indicator flag bit 1 or 0 That is used to indicate low voltage level When the power voltage is below the LVD FLAG level the bit 0 of LVDCON register is set 1 When the power voltage is above the LVD FLAG level the bit 0 of LVDCON register is set 0 automatically LVDCON O can be used flag bit to indicate low battery in IR application or others ELECTRONICS 14 1 LOW VOLTAGE DETECTOR S3F80K5 UM REV1 11 NOTES A term of LVD is a symbol of parameter that means Low Level Detect Voltage for Back Up Mode A term of LVD FLAG is a symbol of parameter that means Low Level Detect Voltage for Flag Indicator The volt
59. is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 27 Rb om NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 gt Ri 06H register 01H 03H BXOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example destination working register R1 has the value 07H 00000111B and source register 01H has the value 03H 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of register 01H source with bit zero of R1 destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of source register 01H is unaffected 6 25 INSTRUCTION SET S3F80K5_UM_REV1 11 CALL Call Procedure CALL Operation Flags Format Examples dst SP lt SP 1 OSP lt PCL SP SP 1 OSP lt PCH PC lt dst The current contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The speci
60. is the same as 4096 x 16 x 1 fosc Figure 15 2 Stop Mode Release Timing When Initiated by a Reset 15 6 ELECTRONICS S3F80K5 UM REV1 11 ELECTRICAL DATA Reset Occur Stop Mode gt 4 gt gt Normal Operating Mode Oscillation Stabilization Time Back up Mode Execution of STOP Instrction Data Retention Time NOTE _ twarT is the same as 4096 x 16 x 1 fosc Figure 15 3 Stop Mode Release Timing When Initiated by a LVD Table 15 6 Input Output Capacitance Ta 25 C to 85 C Input Cin f 1 MHz 10 pF Capacitance Vop 0 V unmeasured pins Output Cour are connected to Vgs Capacitance I O Capacitance Table 15 7 A C Electrical Characteristics Ta 25 C to C Interrupt Input NTH P0 0 P0 7 P2 0 200 300 ns High Low Width NTL Vop 3 6 V ELECTRONICS 15 N ELECTRICAL DATA S3F80K5 UM REV1 11 NOTE The unit tceu means one CPU clock period Figure 15 4 Input Timing for External Interrupts Port 0 and Port 2 15 8 ELECTRONICS S3F80K5 UM REV1 11 ELECTRICAL DATA Table 15 8 Oscillation Characteristics aar 25 C to 85 C EE 1 pass io Typ mo umt ME CPU clock oscillation DE frequency XOUT Ceramic CPU clock oscillation d XIN frequency C1 I XOUT C2 External Clock Xin input frequency External Clock Open Pin Zour ELECTRONICS 15 9 ELECTRICAL DATA S3F80K5 UM REV1 11 Table 15 9 Oscillation Stabilization
61. operands are both logic ones otherwise a 0 bit value is stored The contents of the source are unaffected C Unaffected Set if the result is 0 cleared otherwise Set if the result bit 7 is set cleared otherwise Always cleared to 0 Unaffected Unaffected N tos P Bytes Cycles opc src dst 3 opc dst src 3 6 Opcode Hex 52 53 54 55 56 Addr Mode dst src r r r Ir R R R IR R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H OAH AND R1 R2 gt Ri 02H R2 03H AND R1 R2 gt R1 02H R2 03H AND 01H 02H gt Register 01H 01H register 02H 03H AND 01H 02H gt Register 01H OOH register 02H 03H AND 01H 25H gt Register 01H 21H In the first example destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in register R1 ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET BAND pit AND BAND BAND Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 AND src b or dst b lt dst b AND src 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or source The resultant bit is stored in the specified bit of the destination No other bits of the destination are
62. or when Stop mode has been released by an external interrupt In Stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of FOSC 4096 for reset or at the rate of the preset clock source for an external interrupt When BTCNT 3 overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summary the following events occur when Stop mode is released 1 During Stop mode a power on reset or an external interrupt occurs to trigger the Stop mode release and oscillation starts 2 If a power on reset occurred the basic timer counter will increase at the rate of fo5c 4096 If an external interrupt is used to release Stop mode the BTCNT value increases at the rate of the preset clock source Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows When a BTCNT 3 overflow occurs normal CPU operation resumes ELECTRONICS 10 3 BASIC TIMER and TIMER 0 S3F80K5 UM REV1 11 TIMER 0 CONTROL REGISTER TOCON You use the timer 0 control register TOCON to Select the timer 0 operating mode interval timer capture mode or PWM mode Select the timer 0 input clock frequency Clear the timer 0 counter TOCNT Enable the timer 0 overflow interrupt or timer 0 match capture interrupt Cl
63. presented in tables and graphs The information is arranged in the following order Absolute Maximum Ratings D G Electrical Characteristics Characteristics of Low Voltage Detect Circuit Data Retention Supply Voltage in Stop Mode Typical Low Side Driver Sink Characteristics Typical High Side Driver Source Characteristics Stop Mode Release Timing When Initiated by an External Interrupt Stop Mode Release Timing When Initiated by a Reset Stop Mode Release Timing When Initiated by a LVD Input Output Capacitance A C Electrical Characteristics Input Timing for External Interrupts Input Timing for Reset Oscillation Characteristics Oscillation Stabilization Time Operating Voltage Range A C Electrical Characteristics for Internal Flash ROM ELECTRONICS ELECTRICAL DATA S3F80K5 UM REV1 11 Table 15 1 Absolute Maximum Ratings Ta 25 C Input Voltage V 0 3 to Vpp 0 3 Output Voltage Vo All output pins 0 3 to Vpp 0 3 l l DD IN Output Current High OH One I O pin active All UO pins active en i 20 Ta One UO pin active 30 Output Current Low All UO pins active mA Operating 25 to 85 C Temperature Storage Ter 65 to 150 C Temperature Table 15 2 D C Electrical Characteristics Ta 25 C to 85 C Vpp 1 65 V to 3 6 V Output High Von Vpp 1 85 V lo 6mA Voltage Port 3 1 only Vous Vpp 1 85 V loy 2 2mA P3 0 and P2 0 Vous Vpp 1 85 V lop 1mA 15 2
64. register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register OOH assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of register 1BH from OFH to 10H ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET INCW Increment Word INCW Operation Flags Format Examples NOTE dst dst lt dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 AO RR Al IR Given RO 1AH R1 02H register 02H OFH and register 03H OFFH INCW RRO gt RO 1AH R1 03H INCW R1 gt Register 02H 10H register 03H OOH In the first example the working register pair RRO contains the value 1AH in register RO and 02H in register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value 03H in register R1 In the second example the statement INCW R1 uses Indirect Register IR addressing mode to increment the contents of g
65. serial MTP interface pin SDAT and SCLK P1 0 P1 7 I O port with bit programmable pins Configurable to input mode or output mode Pin circuits are either push pull or n channel open drain type I O port with bit programmable pins Configurable 3 to input mode push pull output mode or n channel open drain output mode Pull up resistors can be assigned by software Pins can be assigned individually as external interrupt inputs with noise filters interrupt enable disable and interrupt pending control 1 0 INTS IO I O port with bit programmable pin Configurable to 4 21 TOPWM TOCAP input mode push pull output mode or n channel open drain output mode Input mode with a pull up resistor can be assigned by software This port 3 pin has high current drive capability Also P3 0 can be assigned individually as an output pin for TOPWM or input pin for TOCAP I O port with bit programmable pin Configurable to input mode push pull output mode or n channel open drain output mode Input mode with a pull up resistor can be assigned by software This port 3 pin has high current drive capability Also P3 1 can be assigned individually as an output pin for REM Xin Xour System clock input and output pins System clock input and output pins clock input and output pins TEST Test signal input pin nr PTT for factory use ae must be connected to Vgc Vos Leem Vos Semon UU ELECTRONICS 1 5 PRODUCT OVERV
66. stack pointer register OOH for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET RCF Reset Carry Flag RCF Operation Flags Format Example RCF CO The carry flag is cleared to logic zero regardless of its previous value C Cleared to 0 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 CF Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero ELECTRONICS 6 69 INSTRUCTION SET S3F80K5_UM_REV1 11 RET Return RET Operation Flags Format Example PC lt OSP SP lt SP 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement that is executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex opc 1 8 internal stack AF 10 internal stack Given SP OOFCH SP 101AH and PC 1234 RET gt PC 101AH SP OOFEH The statement RET pops the contents of stack pointer location OOFCH 10H into the high byte of the program c
67. statement SBO clears FLAGS 0 to 0 selecting bank 0 register addressing ELECTRONICS 6 75 INSTRUCTION SET S3F80K5_UM_REV1 11 SB1 Select Bank 1 SB1 Operation BANK lt 1 The SB1 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some S3F8 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented 6 76 ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET SBC subtract With Carry SBC dst src Operation dst lt dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands Flags C Set if a borrow occurred src gt dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if t
68. the operation performed The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits Carry Bits 4 7 H Flag Bits 0 3 Number Added Carry Before DA Value Hex Before DA Value Hex to Byte After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 0 A F 0 0 9 60 1 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 0 0 8 1 6 F FA 06 0 1 7 F 0 0 9 AO 60 1 1 6 F 1 6 F 9A 66 1 C Set if there was a carry from the most significant bit cleared otherwise see table Z Setif resultis 0 cleared otherwise S Set if result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 40 R 4 41 IR ELECTRONICS 6 33 INSTRUCTION SET S3F80K5_UM_REV1 11 DA Decimal Adjust DA Example Continued Given Working register RO contains the value 15 BCD working register R1 contains 27 BCD and address 27H contains 46 BCD ADD R1 RO C 0 H lt 0 Bits 4 7 3 bits 0 3 C R1 lt 3CH DA R1 S R1 lt 3CH 06 If addition is performed using the BCD values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100 3CH The DA instruction adjusts this result s
69. to store program code be careful to avoid overwriting vector addresses stored in these locations The program memory address at which program execution starts after reset is 0100H default If you use ISPTM sectors as the ISPTM software storage the reset vector address can be changed by setting the Smart Option Refer to Figure 2 2 Decimal 65 536 256 byte Internal RAM Internal Program S3F80K5 16Kbyte Memory O1FFH 02FFH 04FFH or 08FFH OFFH 03FH 03CH Figure 2 1 Program Memory Address Space NOTES 1 The size of ISP sector can be varied by Smart Option Refer to Figure 2 2 According to the smart option setting related to the ISP ISP reset vector address can be changed one of addresses to be select 200H 300H 500H or 900H 2 ISPTM sector can store On Board Program Software Refer to chapter 15 Embedded Flash Memory Interface 2 2 ELECTRONICS S3F80K5 UM REV1 11 ADDRESS SPACE SMART OPTION Smart option is the program memory option for starting condition of the chip The program memory addresses used by smart option are from 003CH to 003FH The S3F80K5 only use 003EH and 003FH User can write any value in the not used addresses 003CH and 003DH The default value of smart option bits in program memory is OFFH Normal reset vector address 100H ISP protection disable Before execution the program memory code user can set the smart option bits according to the hardware option for user to want to s
70. values should not be changed curing normal operation ELECTRONICS 4 35 CONTROL REGISTERS S3F80K5 UM REV1 11 RESETID Reset Source Indicating Register FOH Seti Bank Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for S3F80K5 3 Key in Reset Indicating Bit Reset is not generated by PO P2 external INT 1 Reset is generated by PO P2 external INT 2 WDT Reset Indicating Bit Reset is not generated by WDT when read EE Reset is generated by WDT when read 1 LVD Reset Indicating Bit Reset is not generated by LVD when read 1 Reset is generated by LVD when read 0 POR Reset Indicating Bit Reset is not generated by POR when read 1 Reset is generated by POR when read State of RESETID depends on reset source POR 0 0 0 1 1 LVD 0 0 0 1 note2 WDT Key in note3 note2 NOTES 1 To clear an indicating register write a 0 to indicating flag bit Writing a 1 to an reset indicating flag RESETID 0 3 has no effect 2 Not affected by any other reset 3 Bits corresponding to sources that are active at the time of reset will be set 4 36 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS RPO Register Pointer 0 D6H Seti Bank Reset Value 1 1 0 0 0 Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 3 Register Pointer 0 Address Value Register pointer 0 can independently point
71. 0000111B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001111B ELECTRONICS 6 21 INSTRUCTION SET S3F80K5_UM_REV1 11 BOR Bit or BOR BOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 OR sre b or dst b lt dst b OR sre 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected N zk Hz o Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 07 Rb om NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Given R1 07H and register 01H 03H BOR Ri 01H 1 gt Ri 07H register 01H 03H BOR 01H 2 Ri gt Register 01H 07H R1 07H In the first example destination working register R1 contains the value 07H 00000111B and source register 01H the value 03H 00000011B The statement BOR R1 01H 1 logically ORs bit one of register 01H source with bit zero of R1 destination This leaves the same value 07H in working register R1 In the seco
72. 00101B in register R1 Because the result of the complement is not 0 the zero flag Z in the FLAGS register 0D5H is cleared ELECTRONICS 6 19 INSTRUCTION SET S3F80K5_UM_REV1 11 BITR Bit Reset BITR Operation Flags Format Example dst b dst b 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITR Ri 1 gt Ri 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET BITS pit Set BITS Operation Flags Format Example dst b dst b 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITS R1 3 gt R1 OFH If working register R1 contains the value 07H 0
73. 00H Register 00H Cc Z S Set if MSB of the result is a 1 cleared otherwise Vv D H Hex dst 3 22 84 RR 22 85 RR 22 86 RR Bytes Cycles Opcode Addr Mode src 09H register 03H 06H 01H register 01H 20H register 02H 09H 00H register 01H OCOH 06H register 01H 00H In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register OOH of the register pair OOH 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair 00H 01H ELECTRONICS 6 59 INSTRUCTION SET S3F80K5_UM_REV1 11 NEXT next NEXT Operation Flags Format Example Address 0120 Pc 0120 44 Address L PC lt OP IP amp IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two No flags are affected Bytes Cycles Opcode Hex ope 1 10 OF The following diagram shows one example of how to use the NEXT instruction Before After Data Address Data 43 Address H 44 Address L 45 Address H Address 43 45 Address H 120 130 Routine Memory Memory ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET NOP no Operation NOP Operation Flags Format Example No action is perform
74. 02H 03H and register 03H OFH LDW RR6 RR4 gt R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H gt Register 00H 03H register 01H OFH register 02H 03H register 03H OFH LDW RR2 R7 gt R2 03H R3 OFH LDW 04H 001H gt Register 04H 03H register 05H OFH LDW RR6 1234H gt R6 12H R7 34H LDW 02H OFEDH gt Register 02H OFH register 03H OEDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H 03H into the destination word 00H 01H This leaves the value 03H in general register OOH and the value OFH in register 01H The other examples show how to use the LDW instruction with various addressing modes and formats ELECTRONICS S3F80K5 UM REV1 11 MULT multiply Unsigned MULT Operation Flags Format Examples dei erc dst lt dstx src The 8 bit destination operand even register of the register pair is multiplied by the source INSTRUCTION SET operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers Set if result is gt 255 cleared otherwise Set if the result is 0 cleared otherwise Cleared Unaffected Unaffected Given Register 00H 20H register 01H 03H register 02H MULT MULT MULT src 00H 02H dst gt 00H G01H gt 00H 30H gt Register 00H Register
75. 1 11 BTJRT pit Test Jump Relative on True BTJRT Operation Flags Format Example dst src b If src b is a 1 then PC lt PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note Hex dst src opc dst 3 10 37 RA rb NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET BXOR Bit xor BXOR BXOR Operation Flags Format Examples ELECTRONICS dst src b dei ber dst 0 lt dst 0 XOR sre b or dst b lt dst b XOR sre 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or source The result bit
76. 11 L PROGRAMMING TIP Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations COH CFH using working register addressing mode only Example 1 LD 0C2H 40H Invalid addressing mode Use working register addressing instead SRP HOCOH LD R2 40H R2 C2H lt the value in location 40H Example 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead SRP HOCOH ADD R3 45H R3 C3H lt R3 45H 4 Bit Working Register Addressing Each register pointer defines a movable 8 byte slice of working register space The address information stored in a register pointer serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects RPO 1 selects RP1 The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 11 the result of this operation is that the five high order bits from the register pointer are concatenated with the
77. 11 RESET RECOMMENDATION FOR UNUSUED PINS To reduce overall power consumption please configure unused pins according to the guideline description Table 8 5 Table 8 5 Guideline for Unused Pins to Reduced Power Consumption e Set Input mode e POCONH lt 00H or OFFH e Enable Pull up Resister e POCONL lt 00H or OFFH e No Connection for Pins POPUR lt tt O0FFH Port 2 0 e Set Push pull Output mode e P2CONL lt OAAH e Set P2 Data Register to 00H P2 lt 00H e Disable Pull up resister P2PUR lt 00H e No Connection for Pins e Set Push pull Output mode P3CON lt 11010010B e Set P3 Data Register to 00H P3 lt 00H e No Connection for Pins ELECTRONICS 8 19 RESET S3F80K5 UM REV1 11 SUMMARY TABLE OF BACK UP MODE STOP MODE AND RESET STATUS For more understanding please see the below description Table 8 6 Table 8 6 Summary of Each Mode Approach e VoD is lower than V yp e The rising edge at VDD is e STOPCON lt A5H Condition detected by LVD circuit STOP When VDD gt Vivo LD STOPCON HOA5H e Watch dog timer overflow STOP signal is activated Port status All I O port is floating status All I O port is floating status e All the ports keep the previous e All the ports become input e Disable all pull up resisters status mode but is blocked e Output port data is not e Disable all pull up resister changed Control e All control register and e All control register and system Regi
78. 2 0 have the falling edge input signal in stop mode if external interrupt is disabled the stop state of S3F80K5 is unchanged Do not use stop mode if you are using an external clock source because Xin input must be cleared internally to VSS to reduce current leakage ELECTRONICS 8 13 RESET S3F80K5 UM REV1 11 SYSTEM RESET OPERATION System reset starts the oscillation circuit synchronize chip operation with CPU clock and initialize the internal CPU and peripheral modules This procedure brings the S3F80K5 into a known operating status To allow time for internal CPU clock oscillation to stabilize the reset pulse generator must be held to active level for a minimum time interval after the power supply comes within tolerance The minimum required reset operation for a oscillation stabilization time is 16 oscillation clocks All system and peripheral control registers are then reset to their default hardware values See Tables 8 2 In summary the following sequence of events occurs during a reset operation All interrupts are disabled The watch dog function Basic Timer is enabled Port 0 2 and 3 are set to input mode and all pull up resistors are disabled for the I O port pin circuits Peripheral control and data register settings are disabled and reset to their default hardware values See Table 8 2 The program counter PC is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabilization
79. 2 SMDS2 SK 1200 OPENIce l 500 Join 2 3 JP5 Board peripheral power Board peripheral power connection Connect connection JP6 When supplied 5V in target board In case of selection 3 3V of In case of selection 5V of Join 2 3 generation of 3 3V using Emulator Not use 3 3V Emulator Use 3 3V regulator regulator Regulator JP8 80K5 Von power connection 80K5 Von power connection Connect JP10 Clock source selection When using the internal clock source which is generated from Emulator Emulator join connector 2 3 and 4 5 pin If user wants to use 2 3 the external clock source like a crystal user should change the 4 5 jumper setting from 1 2 to 5 6 and connect Y1 to an external clock source JP11 Regulator 3 3 Volt Out connection Connection between regulator out voltage and 80KB s Power Vpp When using the regulator When debugging with an emulator JP11 don t need to be connect SW2 Smart option at address 3EH Dip switch for smart option This 1byte is mapped address 3EH for special function Refer to the page 2 3 SW3 Smart option at address 3FH Dip switch for smart option This 1byte is mapped address 3FH for special function Refer to the page 2 3 Y1 External clock source Connecting points for external clock source J3 Header for flash serial To program an internal flash connect the signals with flash J3 programming signals writer tool To Target System is supplied Vpp Target Board is not supplied Target Board is supplied Vip Join 2 3 User Ver Vpp
80. 20H register 01H 20H Register 01H R1 20H RO RO 01H R1 Register 00H Register 02H Register 00H Register 00H Register 00H 01H RO 01H 01H 20H register 01H 20H register OOH OAH 01H register 01H 01H register 01H RO OFFH R1 OAH Register 31H OAH RO 01H R1 OAH OAH register 01H OAH 20H 01H 10H 02 register 02H 02H ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET LDB Load Bit LDB LDB Operation Flags Format Examples dei erch dst b src dst 0 sre b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 47 Rb ro NOTE In the second byte of the instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given RO 06H and general register OOH 05H LDB RO 00H2 gt RO 07H register 00H 05H LDB 00H 0 R0 gt RO 06H register 00H 04H In the first example destination working register RO contains the value 06H and the source general register 00H the value 05H The statement LD R0 00H 2 loads the bit two value of the 00H register into bit zero of the RO re
81. 3 0 P3 1 and an additional status bit P3 7 for carrier signal on off Table 9 2 Port Data Register Summary Set 1 Bank 0 i RW O Because port 3 is a 2 bit I O port the port 3 data register only contains values for P3 0 P3 1 The P3 register also contains a special carrier on off bit P3 7 See the port3 description for details All other I O ports are 8 bit Pn 7 Because port 3 is a 2 bit I O port the port 3 data register only contains values for P3 0 P3 1 The P3 register also contains a special carrier on off bit P3 7 See the port 3 description for details Figure 9 1 S3F80K5 UO Port Data Register Format ELECTRONICS 9 3 I O PORTS S3F80K5 UM REV1 11 PULL UP RESISTOR ENABLE REGISTERS You can assign pull up resistors to the pin circuits of individual pins in port0 and port1 To do this you make the appropriate settings to the corresponding pull up resistor enable registers POPUR These registers are located in set 1 bank 0 at locations E7H respectively and are read write accessible using Register addressing mode You can assign a pull up resistor to the port 3 pins P3 0 P3 1 in the input mode using basic port configuration setting in the P3CON registers Pull up Register Enable Registers PNPUR where n 0 Set 1 E7H Bank0 R W Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor NOTE Pull up resistors can be assigned to the port 3 pins P3 0 P3 1
82. 4 Ipp12 and lpp22 should be changed refer to table 15 2 Operating Mode loo12 Vop 3 6 V 4 MHz crystal Idle Mode Ipp22 Vpp 3 6 V 4 MHz crystal Operating Mode Ibor Vop 3 6 V 4 MHz crystal Idle Mode Ipp22 Voo 3 6 V 4 MHz crystal REVISION DESCRIPTIONS Rev 1 11 1 Chapter 17 FLASH MCU In table 17 1 Descriptions of Pins should be changed Main Chip During Programming Serial data pin Output port when reading and input port when writing SDAT P0 0 can be assigned as an input or push pull output port Serial data pin Output port when reading and input port when writing SCLK P0 1 can be assigned as an input or push pull output port Tool mode selection when TEST pin sets Logic value 1 If user uses the flash writer tool mode ex spw2 etc user should connect TEST pin to VDD S3F80K5 supplies high voltage 12 5V by internal high voltage generation circuit nRESET nRESET 7 1 Chip Initialization Vop Von 24 Power supply pin for logic circuit VDD should be y V 1 tied to 3 3V durin programming SS SS Preface The S3F80K5 Microcontroller User s Manual is designed for application designers and programmers who are using S3F80K5 microcontroller for application development It is organized in two main parts Part I Programming Model Part II Hardware Descriptions Part I contains software related information to familiarize you with the microcontroller s architecture p
83. 653 All semiconductor products are designed and manufactured in accordance with the highest quality standards and Samsung Electronics Co Ltd San 24 Nongseo Dong Giheung Gu Yongin City Gyunggi Do Korea C P O Box 37 446 711 TEL 82 31 209 5238 FAX 82 31 209 6494 Home Page URL Http www samsungsemi com Printed in the Republic of Korea NOTIFICATION OF REVISIONS ORIGINATOR PRODUCT NAME DOCUMENT NAME DOCUMENT NUMBER EFFECTIVE DATE SUMMARY DIRECTIONS Samsung Electronics LSI Development Group Gi Heung South Korea S3F80K5 Microcontroller S3F80K5 User s Manual Revision 1 11 S3 F80K5 122008 December 2008 As a result of additional product testing evaluation and spelling mistakes some specifications in the S3F80K5 User s Manual Revision 1 00 have been changed These changes for S3F80K5 microcontroller which are described in detail in the Revision Descriptions section below are related to the followings Chapter 17 Flash MCU Please note the changes in your copy copies of the S3F80K5 User s Manual Revision 1 00 or simply attach the Revision Descriptions of the next page to S3F80K5 User s Manual Revision 1 10 REVISION HISTORY Revision Roma amoo oe om O Preliminary Spec for internal release only Minseok Jeong Oct 2007 First edition Minseok Jeong August 2008 Second edition Minseok Jeong September 2008 Third edition Minseok Jeong December
84. 80K5 ELECTRONICS 18 1 DEVELOPMENT TOOLS S3F80K5 UM REV1 11 Development System Configuration IBM PC AT or Compatible Emulator SK 1200 RS 232 USB Re OPENIce I 500 RS 232 or Target Application System Probe Adapter TB80K9 Target Board EVA Chip Figure 18 1 Development System Configuration 18 2 ELECTRONICS S3F80K5 UM REV1 11 ELECTRICAL DATA TB80KB TARGET BOARD The TB80KB target board can be used for development of S3F80K5 S3F80K5 and S3F80KB together But you should be careful to set the memory size to program internal flash memory The TB80KB target board is operated as target CPU with Emulator SK 1200 OPENIce 1 500 TB80KB Rev1 To User Vcc nRESET IDLE STOP of OOO On v2 74HC11 In Circuit Emulator RESET SK 1200 OPENIce 1 500 E a JP10 i OJO lO BOARD_CLK Q O 2 MDS CLK O 5 JIA J MAIN_MODE 1 10J08UUO0 Uld 00L 100 Pin Connector USER MODE by 144 QFP EVA MODE S3E80KBX TEST_MODE EVA Chip 50 Pin Connector OOO smDs2 A Figure 18 2 TB80KB Target Board Configuration NOTES 1 TB80KB should be supplied 3 3V normally So the power supply from Emulator
85. 80K5 UM REV1 11 ADDRESS SPACE REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you can access all locations in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing because H uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space n Even address Figure 2 9 16 Bit Register Pair ELECTRONICS 2 13 ADDRESS SPACE S3F80K5 UM REV1 11 Special Purpose Registers General Purpose Registers Fo Kl Bank 1 Bank 0 Control Registers System Regis
86. 80K5 UM REV1 11 EMBEDDED FLASH MEMORY INTERFACE L PROGRAMMING TIP Sector Erase Case1 Erase one sector e ERASE_ONESECTOR SB1 LD FMUSR 0A5H User program mode enable LD FMSECH 40H Set sector address 4000H sector 128 LD FMSECL 00H among sector 0 511 LD FMCON 10100001B Select erase mode enable amp Start sector erase ERASE_STOP LD FMUSR 00H User program mode disable SBO Case2 Erase flash memory space from Sector n to Sector n m Pre define the number of sector to erase LD SecNumH 00H Set sector number LD SecNumL 128 Selection the sector128 base address 4000H LD R6 01H Set the sector range m to erase LD R7 7DH into High byte R6 and Low byte R7 LD R2 SecNumH LD R3 SecNumL ERASE LOOP CALL SECTOR ERASE XOR P4 11111111B Display ERASE_LOOP cycle INCW RR2 LD SecNumH R2 LD SecNumL R3 DECW RR6 LD R8 R6 OR R8 R7 CP R8 00H JP NZ ERASE_LOOP ELECTRONICS 13 9 EMBEDDED FLASH MEMORY INTERFACE SECTOR ERASE LD R12 SecNumH LD R14 SecNumL MULT RR12 480H MULT RR14 80H ADD R13 R14 NOCARRY LD R10 R13 LD R11 R15 ERASE_START SB1 LD FMUSR 0A5H LD FMSECH R10 LD FMSECL R11 LD FMCON 10100001B ERASE_STOP LD FMUSR 00H 13 10 S3F80K5_UM_REV1 11 Calculation the base address of a target sector The size of one sector is 128 bytes BTJRF FLAGS 7 NOCARRY ING R12 User program mode enable Set sector address Select erase mode enab
87. A shift Right Arithmetic SRA Operation dst dst 7 lt dst 7 C lt dst 0 det n lt dst n 1 n 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into bit position 6 Flags Format Examples C Set if the bit shifted from the LSB position bit zero was 1 Z Setif the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst ODC det 2 4 DO R 4 D1 IR Given Register 00H 9AH register 02H 03H register 03H OBCH and C 1 SRA 00H gt Register 00H OCD C 0 SRA 02H gt Register 02H 03H register 03H ODEH C 0 In the first example if general register OOH contains the value 9AH 10011010B the statement SRA 00H shifts the bit values in register OOH right one bit position Bit zero 0 clears the C flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value OCDH 11001101B in destination register OOH ELECTRONICS 6 79 INSTRUCTION SET S3F80K5_UM_REV1 11 SRP SRPO SRP1 set Register Pointer SRP SRPO SRP1 Operation Flags Format Examples 6 80 src src src If src 1 1 and src 0 Othen RPO 3 7 lt src 3 7
88. A to write R10 40H Load flash memory upper address into upper register of pair working register R11 10H Load flash memory lower address into lower register of pair working register RR10 R9 Write data AAH at flash memory location 4010H FMUSR 00H User program mode disable Case2 Programming in the same sector WR_INSECTOR RR10 gt Address copy R10 high address R11 low address LD RO 40H SB1 LD FMUSR 0A5H User program mode enable LD FMCON 01010000B _ Selection programming mode and Start programming LD FMSECH 40H Set the base address of sector located in target address to write data LD FMSECL 00H The sector 128 s base address is 4000H LD R9 33H Load data 33H to write LD R10 40H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register WR_BYTE LDC RR10 R9 Write data 33H at flash memory location INC R11 Reset address in the same sector by INC instruction DJNZ RO WR_BYTE Check whether the end address for programming reach 407FH or not LD FMUSR 00H User Program mode disable SBO 13 14 ELECTRONICS S3F80K5 UM REV1 11 EMBEDDED FLASH MEMORY INTERFACE Case3 Programming to the flash memory space located in other sectors WR INSECTOR2 LD LD SB1 LD R0 440H R1 40H FMUSR 0A5H LD FMCON 01010000B LD FMSECH 01H LD LD LD LD CALL LD
89. ADDRESSING MODE Continued Register File ie a RPO or RP1 RPO or RP1 Selected RP points Program Memory to start of woking register A To Past se e i Register 2 SE Ear ie Address OPGODE Woking Register el org Sample Instruction Value used in OPERAND Er eee TT Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES S3F80K5 UM REV1 11 INDIRECT REGISTER ADDRESSING MODE Continued Register File MSB Points to RPO or RP1 RPO or RP1 Selected RP points to start of working register HM eee Program Memory dst Register Next 2 bit Point Pair B A a EN References either Register Pair Program Memory or 1 of 4 Data Memory 4 bit Working Register Address 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data SSES memory Value used in OPERAND Instruction me Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access LDE command is not available because an external interface is not implemented for the S3F80K5 Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS S3F80K5 UM REV1 11 ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand
90. Address Low Byte NOTE The Low Byte flash memory sector address pointer value is the lower eight bits of the 16 bit pointer address Figure 13 6 Flash Memory Sector Address Register FMSECL 13 6 ELECTRONICS S3F80K5 UM REV1 11 EMBEDDED FLASH MEMORY INTERFACE SECTOR ERASE User can erase a flash memory partially by using sector erase function only in user program mode The only unit of flash memory to be erased in the user program mode is a sector The program memory of S3F80K5 16Kbytes flash memory is divided into 128 sectors Every sector has all 128 byte sizes So the sector to be located destination address should be erased first to program a new data one byte into flash memory Minimum 10ms delay time for the erase is required after setting sector address and triggering erase start bit FMCON 0 Sector erase is not supported in tool program modes MDS mode tool or programming tool Sector 127 128 byte Sector 126 128 byte Sector 11 128 byte Sector 10 128 byte Sector 0 9 128 byte x 10 Figure 13 7 Sector Configurations in User Program Mode ELECTRONICS 13 7 EMBEDDED FLASH MEMORY INTERFACE S3F80K5 UM REV1 11 The Sector Erase Procedure in User Program Mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 Set Flash Memory Sector Address Register FMSECH and FMSECL 3 Set Flash Memory Control Register FMCON to 10100001B 4 Set Flash Memory Us
91. C C lt dst 7 dst n 1 lt dst n n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C the initial value of the carry flag replaces bit zero Flags Format Examples C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst ODC det 2 4 10 R 4 11 IR Given Register 00H OAAH register 01H 02H and register 02H 17H C O RLC 00H gt Register 00H 54H C 1 RLC 01H gt Register 01H 02H register 02H 2EH C 0 In the first example if general register OOH has the value OAAH 10101010B the statement RLC 00H rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register OOH leaving the value 55H 01010101B The MSB of register OOH resets the carry flag to 1 and sets the overflow flag ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET RR Rotate Right RR Operation dst C lt dst 0 dst 7 lt dst 0 dst n lt dst n 1 n 0 6 The contents of the destination op
92. CAOF 0 T F F is low 1 T F F is high Counter A Mode Selection Bit 0 One shot mode 1 Repeating mode Counter A Start Stop Bit 0 Stop counter A 1 Start counter A Counter A Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt A Control Register CACON Counter A Data High Byte Register CADATAH F4H Set 1 Bank 0 R W Reset Value FFH Counter A Data Low Byte Register CADATAL F5H Set 1 Bank 0 R W Reset Value FFH Figure 12 3 Counter A Registers ELECTRONICS COUNTER A S3F80K5 UM REV1 11 COUNTER A PULSE WIDTH CALCULATIONS THIGH Se w m To generate the above repeated waveform consisted of low period time D ow and high period time tHiGH When CAOF 0 tLow CADATAL 2 x 1 Fx OH lt CADATAL lt 100H where Fx the selected clock tuigh CADATAH 2 x 1 Fx OH lt CADATAH lt 100H where Fx the selected clock When CAOF 1 tLow CADATAH 2 x 1 Fx OH lt CADATAH lt 100H where Fx the selected clock tuigh CADATAL 2 x 1 Fx OH lt CADATAL lt 100H where Fx the selected clock To make tj ow 24 us and tyigy 15 US fosc 4 MHz FX 4 MHz 4 1 MHz Method 1 When CAOF 0 tLow 24 us CADATAL 2 FX CADATAL 2 x 1us CADATAL 22 ten 15 us CADATAH 2 FX CADATAH 2 x 1us CADATAH 13 Method 2 When CAOF 1 tuigh 15 us CADATAL 2 FX CADATAL 2 x 1us CADATAL 13 tLow
93. CS 8 5 RESET S3F80K5 UM REV1 11 If Vreset gt VIH the operating status is in STOP mode LVD circuit is disabled in the S3F80K5X Stop Mode LVD off Reset Low tWAIT 4096x16x1 fosc Normal Operating Mode LVD on VDD Reset pulse generated Oscillation starts POR detected POR Reset Release i E LVD Reset Releas N vi Internal Reset ET Ne Figure 8 5 Reset Timing Diagram for The S3F80K5 in STOP mode by IPOR EXTERNAL INTERRUPT RESET When RESET Control Bit smart option 03FH is set to 0 and chip is in stop mode if external interrupt is occurred by among the enabled external interrupt sources from INTO to INT5 reset signal is generated 8 6 ELECTRONICS S3F80K5 UM REV1 11 RESET STOP ERROR DETECTION amp RECOVERY When RESET Control Bit smart option bit 0 amp 03FH is set to 0 and chip is in stop or abnormal state the falling edge input of PO generates the reset signal Refer to following table and figure for more information Table 8 1 Reset Condition in STOP Mode Condition fasal The voltage level of reset pin ee System Reset Slope of Vo rosdi Rising up from Von gt Vivo Von gt Vivo VLyp Vreset V4 gt Vik Vreset2Vp TI No system reset To ar op Vop gt on VeesetsVip IL Nosystem reset Rising up from Internal POR System reset occurs Noo lt Nron Vov gt Vivo Vreset lt Via gt Nosystemreset ELECTRONICS 8 7 RESET S3F80K5 UM REV1 11 POWER DOWN MODES
94. DATAL F8H F9H Counter A IRQ2 CACON F3H Bank0 CADATAH CADATAL F4H F5H DO external interrupt IRQ7 POCONH Bank0 P0 6 external interrupt POINT P0 5 external interrupt POPND P0 4 external interrupt PO 3 external interrupt POCONL Bank0 P0 2 external interrupt POINT P0 1 external interrupt POPND PO O external interrupt P2 0 external interrupt IRQ4 P2CONL Bank P2INT P2PND NOTES 1 Because the timer 0 and timer1 overflow interrupts are cleared by hardware the TOCON and T1CON registers control only the enable disable functions The TOCON and T1CON registers contain enable disable and pending bits for the timer 0 and timer1 match capture interrupts respectively 2 Ifa interrupt is un mask Enable interrupt level in the IMR register the pending bit and enable bit of the interrupt should be written after a DI instruction is executed 5 8 ELECTRONICS S3F80K5 UM REV1 11 INTERRUPT STRUCTURE SYSTEM MODE REGISTER SYM The system mode register SYM DEH Set 1 Bank0 is used to globally enable and disable interrupt processing and to control fast interrupt processing See Figure 5 5 A reset clears SYM 7 SYM 1 and SYM 0 to 0 The 3 bit value SYM 4 SYM 2 is for fast interrupt level selection and undetermined values after reset SYM 6 and SYM5 are not used The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit O value of the SYM register An Enable Interrupt El instru
95. DC ADC ADC ADC BCP R1 IR1 r1 r2 r lr2 R2 R1 IR2 R1 R1 IM r1 b R2 INC INC SUB SUB SUB SUB SUB BXOR R1 IR1 r1 r2 ale R2 R1 IR2 R1 R1 IM r0 Rb JP SRP 0 1 SBC SBC SBC SBC SBC BTJR IRR1 IM r1 r2 r lr2 R2 R1 IR2 R1 R1 IM r2 b RA DA DA OR OR OR OR OR LDB R1 IR1 r1 r2 r lr2 R2 R1 IR2 R1 R1 IM r0 Rb POP POP AND AND AND AND AND BITC R1 IR1 r1 r2 r lr2 R2 R1 IR2 R1 R1 IM ri b COM COM TCM TCM TCM TCM TCM BAND R1 IR1 r1 r2 r lr2 R2 R1 IR2 R1 R1 IM r0 Rb PUSH PUSH TM TM TM TM TM BIT R2 IR2 r1 r2 ale R2 R1 IR2 R1 R1 IM ri b DECW DECW PUSHUD PUSHUI MULT MULT MULT LD RR1 IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 r1 x r2 RL RL POPUD POPUI DIV DIV DIV LD R1 IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 r2 x ri A INCW INCW CP CP CP CP CP LDC RR1 IR1 r1 r2 ale R2 R1 IR2 R1 R1 IM ur Irr2 xL CLR CLR XOR XOR XOR XOR XOR LDC Ri IR1 r1 r2 r lr2 R2 R1 IR2 R1 R1 IM r2 Irr2 xL C RRC RRC CPIJE LDC LDW LDW LDW LD R1 IR1 Ir r2 RA r1 Irr2 RR2 RR1 IR2 RR1 RR1 IML r1 Ir2 SRA SRA CPIJNE LDC CALL LD LD R1 IR1 Irr r2 RA r2 lrr1 1A1 IR1 IM Ir1 r2 RR RR LDCD LDCI LD LD LD LDC R1 IR1 r1 Irr2 r1 Irr2 R2 R1 R2 IR1 R1 IM rt Irr2 xs SWAP SWAP LDCPD LDCPI CALL LD CALL LDC R1 IR1 r2 lrr1 r2 lrr1 IRR1 IR2 R1 DA1 r2 Irr1 xs 6 10 ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET Table 6 5 Opcode Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX ELECTRONICS 6 11 INSTRUCTION SET S3F80K5_UM_REV1 11 CONDITION CODES The op code of a conditional
96. ELECTRONICS USER S MANUAL S3F80K5 8 BIT CMOS MICROCONTROLLERS December 2008 REV 1 11 Confidential Proprietary of Samsung Electronics Co Ltd Copyright O 2008 Samsung Electronics Inc All Rights Reserved Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3F80K5 8 Bit CMOS Microcontrollers User s Manual Revision 1 11 Publication Number 21 11 S3F 80K5 122008 Copyright O 2007 2008 Samsung Electronics Co Ltd Typical parameters can and do va
97. Examples det erc r e TT 1 dst lt src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given RO 7FH R6 21H and R7 OFFH LDCPI RR6 RO RR6 lt RR6 1 7FH contents of RO is loaded into program memory f location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH LDEPI RR6 RO RR6 RR6 1 ZFH contents of RO is loaded into external data memory f location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH ELECTRONICS 6 57 INSTRUCTION SET S3F80K5_UM_REV1 11 LDW Load Word LDW Operation Flags Format Examples dst src dst lt src The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 C4 RR RR C5 RR IR opc dst src 4 8 C6 RR IML Given R4 06H R5 1CH R6 05H R7 02H register OOH 1AH register 01H 02H register
98. Figure 5 8 Interrupt Priority Register IPR ELECTRONICS S3F80K5 UM REV1 11 INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ DCH Set 1 Bank0 to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit O to IRQO bit 1 to IRQ1 and so on A 0 indicates that no interrupt request is currently being issued for that level a 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Set 1 Bank 0 Read only IRQ1 IRQ2 S Not Not IRQ4 used IR IRQ7 Q6 used Interrupt Level Request Enable Bits 0 Interr
99. H BTCON 0AAH CLKCON 18H SYM SPL TOCON 4BH TODATA 5DH HOCOH RPO 60H RO R2 RO R3 R2 R4 RO Continued on next page ELECTRONICS Timer 0 overflow interrupt Timer 0 match capture interrupt Disable all interrupts Disable the watchdog timer Select non divided clock Disable global and fast interrupts Stack pointer low byte gt 0 Stack area starts at OFFH Write 00100101B Input clock is fosc 256 Interval timer mode Enable the timer 0 interrupt Disable the timer 0 overflow interrupt Set timer interval to 4 milliseconds 6 MHz 256 93 1 0 25 kHz 4 ms Set register pointer gt OCOH Enable interrupts Save RPO to stack RPO lt 60H RO RO 1 R2 lt R2 RO R3 lt R3 R2 Carry R4 lt R4 RO Carry 10 11 BASIC TIMER and TIMER 0 S3F80K5 UM REV1 11 PROGRAMMING TIP Programming Timer 0 Continued CP RO 32H 50x 4 200 ms JR ULT NO_200MS_SET BITS R1 2 Bit setting 61 2H NO 200MS SET LD TOCON 42H Clear pending bit POP RPO Restore register pointer 0 value TOOVER IRET Return from interrupt service routine 10 12 ELECTRONICS S3F80K5 UM REV1 11 TIMER 1 T we OVERVIEW The S3F80K5 microcontroller has a 16 bit timer counter called Timer 1 T1 For universal remote controller applications Timer 1 can be used to generate the envelope pattern for the remote controller signal Timer 1 has the following
100. Hex opc 1 4 8F Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt source control register be sure DI state ELECTRONICS 6 37 INSTRUCTION SET S3F80K5_UM_REV1 11 DIV Divide Unsigned DIV dst src Operation dst src dst UPPER lt REMAINDER dst LOWER lt QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers Flags C Set if the V flag is set and quotient is between 28 and 29 1 cleared otherwise Z Set if divisor or quotient 0 cleared otherwise S Set if MSB of quotient 1 cleared otherwise V Set if quotient is gt 28 or if divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given RO 10H R1 O3H R2 40H register 40H 80H DIV
101. However the timer 1 match capture interrupt IRQ1 vector F6H must be cleared by the interrupt service routine S W ELECTRONICS 4 41 S3F80K5 UM REV1 11 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 S3F8 series interrupt structure has three basic components levels vectors and sources The SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and I O blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are six possible interrupt levels IRQO IRQ6 also called level O level 6 Each interrupt level directly corresponds to an interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3F80K5 interrupt structure recognizes six interrupt levels The interrupt level numbers 0 through 6 do not necessarily indicate the relative priority of the levels They are simply identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup
102. IEW S3F80K5 UM REV1 11 PIN CIRCUITS Pull Up Resistor 67KQ typ Pull up Enable INPUT OUTPUT Output Disable External Noise Interrupt Filter Stop Stop Release Figure 1 3 Pin Circuit Type 1 Port 0 1 6 ELECTRONICS S3F80K5 UM REV1 11 PRODUCT OVERVIEW PIN CIRCUITS Continued Pull up Resistor 67KQ Typ INPUT OUTPUT Open Drain Output Disable Figure 1 4 Pin Circuit Type 2 Port 1 ELECTRONICS 1 7 PRODUCT OVERVIEW S3F80K5 UM REV1 11 PIN CIRCUITS Continued Pull Up Resistor 67KQ typ INPUT OUTPUT Open Drain Output Disable External Noise Interrupt Filter Figure 1 5 Pin Circuit Type 2 Port 2 1 8 ELECTRONICS S3F80K5 UM REV1 11 PIN CIRCUITS Continued Pull up Enable P3CON 2 Port 3 0 Data O TO PWM o Open Drain o Output Disable o P3CON 2 6 7 TOCAP T1CAP o Noise filter PRODUCT OVERVIEW Pull up Resistor 67kQ Typ P3 0 TOPWM TOCAP T1CAP Figure 1 6 Pin Circuit Type 4 P3 0 ELECTRONICS 1 9 PRODUCT OVERVIEW S3F80K5 UM REV1 11 PIN CIRCUITS Continued VDD Pull up Resistor 67kQ Typ Pull up Enable gt P3CON 5 Port 3 1 Data o Carrier On Off P3DAT 7 CACON 2 O P3 1 REM TOCK Open Drain 0 Output y Disable P3 1 Input o P3CON 5 6 7 TOCK O Noise filter Figure 1 7 Pin Circuit Type 5 P3 1 1 10 ELECTRONICS S3F80K5 UM REV1 11 ADDRESS SPACE ADDRESS SPACE OVERVIE
103. IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WEI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src Bit XOR TCM dst src Test complement under mask TM dst src Test under mask 6 4 ELECTRONICS S3F80K5 UM REV1 11 RL dst RLC dst RR dst RRC dst SRA dst SWAP dst CPU Control Instructions CCF DI EI IDLE NOP RCF SBO SB1 SCF SRP SIC SRPO SIC SRP1 SIC STOP ELECTRONICS INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Mnemonic Operands Rotate and Shift Instructions Instruction Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode INSTRUCTION SET S3F80K5_UM_REV1 11 FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits that describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 can be tested and used with conditional jump instructions two others FLAGS 3 and FLAGS 2 are used for BCD arithmet
104. IT gt gt Normal Operating Mode VDD Stop Mode LVD off Back up Mode gt H Normal Operating Mode VDD Reset pulse generated oscillation start Key in LVD ON Figure 8 8 Timing Diagram for Back up Mode Input in Stop mode 8 10 ELECTRONICS S3F80K5 UM REV1 11 STOP MODE RESET STOP mode is invoked by executing the instruction STOP after setting the stop control register STOPCON In STOP mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the current consumption can be reduced All system functions stop when the clock freezes but data stored in the internal register file is retained STOP mode can be released in one of two ways by a system reset or by an external interrupt After releasing from STOP mode the value of stop control register STOPCON is cleared automatically PROGRAMMING TIP To Enter STOP Mode This example shows how to enter the stop mode ORG JP ENTER STOP LD STOP NOP NOP NOP RET ORG JP ORG START LD MAIN NOP ELECTRONICS 0000H Reset address T START STOPCON 0A5H 0100H 3 T START 0100H Reset address BTCON 03 Clear basic timer counter ENTER STOP Enter the STOP mode BTCONH02H Clear basic timer counter T MAIN RESET S3F80K5 UM REV1 11 SOURCES TO RELEASE STOP MODE Stop mode is released when following sources go active System Reset by Internal Pow
105. Indirect addressing mode Indirect working register only Indirect register or indirect working register Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed short offset addressing mode Indexed long offset addressing mode Direct addressing mode Relative addressing mode Immediate addressing mode Immediate long addressing mode ELECTRONICS Actual Operand Range See list of condition codes in Table 6 6 Rn n 0 15 Rn b n 0 15 b 0 7 Rn n 0 15 RRp p 0 2 4 14 reg or Rn reg 0 255 n 0 15 reg b reg 0 255 b 0 7 reg or RRp reg 0 254 even number only where p 0 2 14 addr addr 0 254 even number only Rn n 0 15 Rn or reg reg 0 255 n 0 15 RRp p 0 2 14 RRp or Greg reg 0 254 even only where p 0 2 14 reg Rn reg 0 255 n 0 15 addr RRp addr range 128 to 127 where p 0 2 14 addr RRp addr range 0 65535 where p 0 2 14 addr addr range 0 65535 addr addr number in the range 127 to 128 that is an offset relative to the address of the next instruction data data 0 255 data data range 0 65535 6 9 INSTRUCTION SET S3F80K5_UM_REV1 11 Table 6 5 Opcode Quick Reference OPCODE MAP Telers ICI A II CI IA DEC DEC ADD ADD ADD ADD ADD BOR Ri IR1 r1 r2 r lr2 R2 R1 IR2 R1 R1 IM r0 Rb RLC RLC ADC A
106. M REV1 11 CACON 6 7 MUX SE 8 Bit Down Counter EE To Other Block P3 1 REM Repeat CACON 3 Control Interrupt INT GEN IRQ2 Counter A Data Low Byte Register CACON 2 CACON 4 5 Counter A Data High Byte Register f Data Bus The value of the CADATAL register is loaded into the 8 bit counter when the operation of the counter A stars If a borrow occurs the value of the CADATAH register is loaded into the 8 bit counter However if the next borrow occurs the value of the CADATAL register is loaded into the 8 bit counter Figure 12 1 Counter A Block Diagram 12 2 ELECTRONICS S3F80K5 UM REV1 11 COUNTER A CONTROL REGISTER CACON The counter control register CACON is located in COUNTER A F3H Set 1 Bank 0 and is read write addressable CACON contains control settings for the following functions See Figure 12 2 Counter A clock source selection Counter A interrupt enable disable Counter A interrupt time selection Counter interrupt pending control read for status write to clear Counter A Control Register CACON F3H Set 1 Bank 0 R W Counter A Input Clock Selection Bits 00 fosc 01 fosc 2 10 fosc 4 11 fosc 8 Counter A Interrupt Time Selection Bits 00 Elapsed time for low data value 01 Elapsed time for high data value 10 Elapsed time for low and high data values 11 Invalid setting Figure 12 2 Counter Counter A Output Flip Flop Control Bit
107. R IR 1 dst lt src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst src 3 8 82 IR R Given Register OOH 03H register 01H 05H and register 02H 1AH PUSHUD 00H 01H gt Register OOH 02H register 01H 05H register 02H 05H If the user stack pointer register OOH for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONICS 6 67 INSTRUCTION SET S3F80K5_UM_REV1 11 PUSHUI Push User Stack Incrementing PUSHUI Operation Flags Format Example dei erc IR IR 1 dst lt src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst src 3 8 83 IR R Given Register OOH 03H register 01H 05H and register 04H 2AH PUSHUI QG00H 01H gt Register OOH 04H register 01H 05H register 04H 05H If the user
108. R6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 RR6 1 R8 ODDH R6 10H R7 34H ELECTRONICS 6 55 INSTRUCTION SET S3F80K5_UM_REV1 11 LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD Operation Flags Format Examples dst src rr rr d1i dst lt src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes Irr an even number for program memory and an odd number for external data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src ope 2 14 F2 Inn Given RO 77H R6 30H and R7 OOH LDCPD RR6 RO RR6 RR6 1 77H contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 OFFH LDEPD RR6 RO RR6 lt RR6 1 77H contents of RO is loaded into external data memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 OFFH ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment LDCPI LDEPI Operation Flags Format
109. RRO R2 gt RO 03H R1 40H DIVRRO R2 gt RO 03H HI 20H DIVRRO 20H gt RO 03H R1 80H In the first example destination working register pair RRO contains the values 10H RO and 03H R1 and register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 6 38 ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET DJNZ Decrement and Jump if Non Zero DJNZ Operation Flags Format Example r dst rer 1 If r 0 PC lt PC dst The working register being used as a counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement NOTE Incase of using DJNZ instruction the working register being used as a counter should be set at the one of location OCOH to OCFH with SRP SRPO or SRP1 instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 jump taken rA RA 8 no jump r 0toF Given R1 02H and
110. SIGNEA EE 6 38 DJNZ Decrement and Jump Non Zem 6 39 El Enable Interrupts iv nitid khekudebi ie De eege AE eet E EE EE eee de 6 40 ENTER Ena AE lt ed te a E EA E 6 41 EXIT ENE 6 42 IDLE Idle ee 6 43 ING le 6 44 INCW increment Word EE 6 45 IRET Interrupt Return anda E dE bid 6 46 JP JUMP RS 6 47 JR JUMP elteren EE E EE EE ee 6 48 xviii S3F80K5_UM_REV1 11 MICROCONTROLLER List of Instruction Descriptions Continued Instruction Full Register Name Page Mnemonic Number LD kadre 6 49 LD A i dati Shee at See kat a Ala koa el a ta ee 6 50 LDB Kabe 6 51 LDC LDE Lodd MOMO Y ets ada dana 6 52 LDC LDE Ee gue E 6 53 LDCD LDED Load Memory and Decrement AA 6 54 LDCI LDEI Load Memory and Increment A 6 55 LDCPD LDEPD Load Memory with Pre Decrement AAA 6 56 LDCPI LDEPI Load Memory with Pre Increment urannvrnnnnnnvrnnnnnnvvnnnnnnrrnnnnnnnrrnnnennrrnnnnnsrrnnesnsrrnneenn 6 57 LDW Load Word E 6 58 MULT Multiply Ulnsionedt nn cnc 6 59 NEXT KE E 6 60 NOP NO Op ralioN nerean rise 6 61 OR O E EE 6 62 POP Pop lu Ee adapter 6 63 POPUD Pop User Stack Decrementing A 6 64 POPUI Pop User Stack Incrementing oocccnininnnncnnnnnccnncconcccnnncccn crac cnc 6 65 PUSH Push TO Stack a a ee ea aai 6 66 PUSHUD Push User Stack Decrementing arrancar 6 67 PUSHUI Push User Stack Incrementing oooonccccnnncnnncnnnnconncccnnnccon crac 6 68 RCF Reset Cary Ragua ondas 6 69 RET Ru E 6 70 RL Roe ae EE e ee 6 71 RLC Rotate eft Through Cary is s
111. SSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Memory Address Used Program Lower Address Byte Upper Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS 3 11 ADDRESSING MODES S3F80K5 UM REV1 11 INDIRECT ADDRESS MODE IA In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory k Next Instruction LSB Must be Zero dst Current OPCODE Instruction Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS S3F80K5 UM REV1 11 ADDRESSING MODES RELATIVE ADDRESS MODE RA In Relative Address RA mode a two s c
112. SYM 2 SYM 4 5 Following a reset you must enable global interrupt processing by executing an El instruction not by writing a 1 to SYM O gt ELECTRONICS 4 39 CONTROL REGISTERS S3F80K5 UM REV1 11 TOCON Timer 0 Control Register D2H Set1 Bank Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer 0 Input Clock Selection Bits KN roses 2 he 1 0 lee 222222 External clock input at the TOCK pin P3 1 or P3 2 5 and A Timer 0 Operating Mode Selection Bits EJES Interval timer mode counter cleared by match signal Capture mode rising edges counter running OVF interrupt can occur EN i ENE Capture mode falling edges counter running OVF interrupt can occur PWM mode Match and OVF interrupt can occur 3 Timer 0 Counter Clear Bit o No effect when write Clear TO counter TOCNT when write 2 Timer 0 Overflow Interrupt Enable Bit note o Disable TO overflow interrupt Enable TO overflow interrupt 1 Timer 0 Match Capture Interrupt Enable Bit o Disable TO match capture interrupt Enable TO match capture interrupt 0 Timer 0 Match Capture Interrupt Pending Flag Bit No TO match capture interrupt pending when read Clear TO match capture interrupt pending condition when write No effect when write TO match capture interrupt is pending when read NOTE A timer 0 overflow interrupt pending condition is automatica
113. Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part II If you are not yet familiar with the S3F8 series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6 Later you can reference the information in Part I as necessary Part II hardware Descriptions has detailed information about specific hardware components of the S3F80K5 microcontroller Also included in Part II are electrical mechanical MTP and development tools data It has 12 chapters Chapter 7 Clock and Power Circuits Chapter 13 Embedded Flash Memory Interface Chapter 8 RESET Chapter 14 Low Voltage Detector Chapter 9 I O Ports Chapter 15 Electrical Data Chapter 10 Basic Timer and Timer 0 Chapter 16 Mechanical Data Chapter 11 Timer 1 Chapter 17 S3F80K5 Flash MCU Chapter 12 Counter A Chapter 18 Development Tools Data S3F80K5 UM REV1 11 MICROCONTROLLER iii Table of Contents Part I Programming Model Chapter 1 Product Overview S3C8 S3F8 Series Microcontrollers AA 1 1 S3F80K5 Micro
114. Support Firmware upgrade SEMINIX TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com GW PRO2 Gang Programmer for OTP MTP FLASH MCU 8 devices programming at one time Fast programming speed 1 2Kbyte sec PC based control operation mode or Stand alone Full Function regarding OTP MTP program Read Program Verify Protection Blank e Data back up even at power break After setup in Design Lab it can be moved to the factory site Key Lock protecting operator s mistake Good Fail quantity displayed and memorized Buzzer sounds after programming User friendly single menu operation PC Operation status displayed in LCD panel SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http Awww seminix com ELECTRONICS 18 9
115. TER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space if implemented see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Remember however that locations COH FFH in set 1 cannot be accessed using Indirect Register addressing mode Program Memory Register File 8 bit register fle address asi Points to one One Operand file Instruction Example Address of operand used by instruction Value used in OPERAND instruction execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES S3F80K5 UM REV1 11 INDIRECT REGISTER ADDRESSING MODE Continued Register File Example Instruction Register Pair SEGREE LE AO EE E Memory Address Points to Program Memory Program Memory Sample Instructions Value used in OPERAND instruction CALL ORR2 ms JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS S3F80K5 UM REV1 11 ADDRESSING MODES INDIRECT REGISTER
116. TOP halts all microcontroller operations ELECTRONICS 6 81 INSTRUCTION SET S3F80K5_UM_REV1 11 SU B subtract SUB dst src Operation dst lt dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand Flags C Set if a borrow occurred cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise lt D Always set to 1 Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow I Format Bytes Cycles Opcode Addr Mode Hex dst src opc dst src 2 4 22 r r 23 r Ir ODC src dst 3 6 24 R R 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H OAH SUB R1 R2 R1 OFH R2 03H SUB R1 R2 R1 08H R2 03H SUB 01H 02H Register 01H 17H register 02H 03H gt gt SUB 01H 02H gt Register 01H 1EH register 02H 03H gt gt SUB 01H 90H Register 01H 91H C S and V 1 SUB 01H 65H
117. User Programming Enable Heotsier AAA 4 12 IMR Interrupt El e EE 4 13 IPH Instruction Pointer High Die 4 14 IPL Instruction Pointer LOW Byte AA 4 14 IPR interopt Pront de e EE 4 15 IRQ Interrupt Request Register rrrnannnnnnrrnnnnrnnnnnvonnnvrvnnnrnnnnnnnrsnrennnrnnnsnnenrsrresnnrnnsnnnnnennenn 4 16 LVDCON LVD Control Register oocooincccinncccnnicconnnccnnccnnnncccnorncn arrancar 4 17 LVDCON EVD Go trol Register uc a it WO ad Fl de 4 17 LVDSEL LVD Flag Level Selection Register ooooooconniccinnccnnninnncconncccnccrnn narra ncccrnrccnn rn 4 18 POCONH Port 0 Control Register High Dvtel nana na ncc cnn nara 4 19 POCONL Port 0 Control Register LOW Byte oooooocincccnnnnncnnnccnnnccccoccnnnornnanannnancc cnn ranma 4 20 POINT Port O External Interrupt Enable Register AAA 4 21 POPND Port O External Interrupt Pending Register AAA 4 22 POPUR Port 0 Pull up Resistor Enable Hegieter rancia 4 23 P1CONH Port 1 Control Register High Dvtel nan noncc crac 4 24 P1CONL Port 1 Control Register Low Byte oonoociniccnnnnicnnncnnnncccnocccnnorananann conc ccnnrn cnn rra 4 25 P1OUTPU Port 1 Output Pull up Resistor Enable Hegister 4 26 P2CONL Port 2 Control Register LOW Byte c cccccccesseeceeeeeceeeeeceaeeeeaaeseeeeeseaeeeesaeeeeneeenaees 4 27 P2INT Port 2 External Interrupt Enable Register rmrrrnnnnrrnnnnvnnrnrrvnnnrnnnnnvnnrrrennnrrnnnnrnnnrnnenn 4 28 P2OUTMD Port 2 Output Mode Selection Heoeter naco narcnr narran cnn 4 29 P2PND Po
118. W The S3F80K5 microcontroller has two types of address space Internal program memory Flash memory Internal register file A 16 bit address bus supports program memory operations separate 8 bit register bus carries addresses and data between the CPU and the register file The S3F80K5 has a programmable internal 16 Kbytes Flash ROM An external memory interface is not implemented There are 333 mapped registers in the internal register file Of these 272 byte are for general purpose use This number includes a 16 byte working register common area that is used as a scratch area for data operations a 192 byte prime register area and a 64 byte area Set 2 that is also used for stack operations Twenty two 8 bit registers are used for CPU and system control and 39 registers are mapped peripheral control and data registers ELECTRONICS 2 1 ADDRESS SPACE S3F80K5 UM REV1 11 PROGRAM MEMORY Program memory stores program code or table data The S3F80K5 has 16 Kbyte of internal programmable Flash memory The program memory address range is therefore 0000H 3FFFH of Flash memory See Figure 2 1 The first 256 bytes of the program memory 0H 0FFH are reserved for interrupt vector addresses Unused locations 0000H 00FFH except 03CH 03DH 03EH and 03FH in this address range can be used as normal program memory The location 03CH 03DH 03EH and 03FH is used as smart option ROM cell If you use the vector address area
119. address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory if implemented You cannot however access locations COH FFH in set 1 using indexed addressing In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to the base address see Figure 3 9 The only instruction that supports indexed addressing mode for the internal register file is the Load instruction LD The LDG and LDE instructions support indexed addressing mode for internal program memory and for external data memory if implemented Register File MSB Points to RPO or RP RPO or RP1 Selected RP Value used in points to Instruction start of working register block Program Memory Two O Base Address M perand dst src Instruction Points to one of the Example OPCODE Woking Registers 1 of 8 Sample Instruction LD RO BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Regi
120. affected The source is unaffected C Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected N zk Hz o Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 67 Rb om NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 05H BAND R1 01H 1 gt R1 06H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example source register 01H contains the value 05H 00000101B and destination working register R1 contains 07H 00000111B The statement BAND R1 01H 1 ANDs the bit 1 value of the source register 0 with the bit O value of register R1 destination leaving the value 06H 000001 10B in register R1 ELECTRONICS 6 17 INSTRUCTION SET S3F80K5_UM_REV1 11 BCP bit Compare BCP Operation Flags Format Example dst src b dst 0 sre b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison Unaffected Set if the two bits are the same cleared otherwise Cleared to 0 Undefined Unaffected Unaffected IOS NO Bytes Cycles Opcode Addr Mode He
121. age gaps LVD_GAPn n 1 4 between LVD and LVD FLAGn n 1 4 have 80mV distribution LVD and LVD FLAGn n 1 4 are not overlapped ELECTRONICS S3F80K5 UM REV1 11 LOW VOLTAGE DETECTOR Resistor String LVD gt BackupMode Reset VDIV Flagi 4 LVDCON D LVD Flag Bit Figure 14 1 Low Voltage Detect LVD Block Diagram ELECTRONICS 14 3 LOW VOLTAGE DETECTOR S3F80K5 UM REV1 11 LOW VOLTAGE DETECTOR CONTROL REGISTER LVDCON LVDCON 0 is used flag bit to indicate low battery in IR application or others When LVD circuit detects LVD FLAG LVDCONOO flag bit is set automatically The reset value of LVDCON is 00H Low Voltage Detect Control Register LVDCON EOH Sett Bank 1 R W Not used for S3F80K5 LVD Indicator Flag Bit 0 Von gt LVD Flag Voltage 1 Vbp lt LVD Flag Voltage Figure 14 2 Low Voltage Detect Control Register LVDCON LOW VOLTAGE DETECTOR FLAG SELECTION REGISTER LVDSEL LVDSEL is used to select LVD flag level The reset value of LVDSEL is 00H Low Voltage Detect Flag Selection Register LVDSEL F1H Gett Bank1 R W Not used for S3F80K5 LVDFlag LevelSelection Bit 00 LVD Flag level is1 90V 01 LVD Flag level is2 00V 10 LVD Flag level is2 10V 11 LVD Flag level is2 20V Figure 14 3 Low Voltage Detect Flag Selection Register LVDSEL 14 4 ELECTRONICS S3F80K5 UM REV1 11 ELECTRICAL DATA OVERVIEW ELECTRICAL DATA In this section S3F80K5 electrical characteristics are
122. al Characteristics coccccccccncnnnonononononononononononenonononononanonanennnnonenenenenones 15 2 15 3 Characteristics of Low Voltage Detect Circuit rnannrnnnnvvnrnrrnnnnnrnnnnvvnrnrrnnnnrnnnnnnnnennne 15 4 15 4 Power On Reset Circuit occccccccncncncncncnnnnncnonenenononononononononononenonenonanonanenanenanananenacinnnnns 15 5 15 5 Data Retention Supply Voltage in Stop Mode 15 5 15 6 Input Output Capacitance wssrenonrnnnnrrnnnnvnnonvvnnnnrrennnrnnnnnnnnsnrennnrnnnnnnnnenrenssrnnsnnnnnnennen 15 7 15 7 A C Electrical Characteristics ococicccicinicinococicinonononononononononanonanananananannnnnnononenenones 15 7 15 8 Oscillation Characteristics rrrvrvrrrrrrrrrrrrnrrrrerevrrrvrvrrvvevrererererererererererererererererersrrerrne 15 9 15 9 Oscillation Stabilization Time 15 10 15 10 AC Electrical Characteristics for Internal Flash ROM rrrnnnororvernarannnrorvonvennannnnnnnen 15 11 15 11 BIREN 15 12 17 1 Descriptions of Pins Used to Read Write the Flash DOMM 17 3 17 2 Operating Mode Selection Criteria rrrrnrnrrnnnnrrnnnnrnnnnvonnnr renn nrnnnnnnnnenrennsrrennnnnnnennenenn 17 4 18 1 Components of TBoORP cn cnn cn nnn rca nn rra rra anna 18 4 18 2 Setting of the Jumper in TB80KB ooooccnincccccccccconcnononcnanococonnnnnnn nn nano cnn nc nr nn cnn nana 18 5 xiv S3F80K5 UM REV1 11 MICROCONTROLLER List of Programming Tips Description Page Number Chapter 2 Address Spaces Setting the Register
123. all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when you execute the SBO instruction and is set to 1 select bank 1 when you execute the SB1 instruction ELECTRONICS 6 7 INSTRUCTION SET INSTRUCTION SET NOTATION S3F80K5_UM_REV1 11 Table 6 2 Flag Notation Conventions O Z S V D H 0 1 Carry flag Zero flag Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register D5H Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET Table 6 4 Instruction Notation Conventions Notation Description Condition code Working register only Bit b of working register Bit 0 LSB of working register Working register pair Register or working register Bit b of register or working register Register pair or working register pair
124. ase Timing When Initiated by a Heset 15 6 15 3 Stop Mode Release Timing When Initiated by a UND 15 7 15 4 Input Timing for External Interrupts Port O and Port 21 15 8 15 5 Operating Voltage Range of G2EOOkb nn nan cc nano nnnnn nn nnnccnins 15 11 16 1 24 Pin SOP Package Mechanical Data 16 1 16 2 24 Pin SDIP Package Mechanical Data 16 2 17 1 Pin Assignment Diagram 24 Pin SOP SDIP Package 17 2 18 1 Development System Configuration ooononnncninncnnnnnnnnnocnncccnnornn narrar cnn 18 2 18 2 TB80KB Target Board Conftguration nc nnrcccnnrnn nr 18 3 18 3 50 Pin Connector Pin Assignment for user System urrrrnannvrnannvnnrrrnnnnrrnnnnrnnnennenenn 18 6 18 4 TB80KB Probe Adapter Cable oooonnoccincccinnccinnccnonocnnoncccnonnnnnorn nn cnn rca 18 6 xii S3F80K5_UM_REV1 11 MICROCONTROLLER List of Tables Table Title Page Number Number 1 1 Pin Descriptions of 24 SOP SDIP rsrrnannrnnnnnvnnnnvrvnnnrnnnnnnnnsrrensnrnnnnnnnnrsrresnnrnnsnnnnnsnnen 1 5 2 1 The Summary of S3F80K5 Register Type rannrnnnnnvnnnnrvnnnrrnnnnrnnennnnrnnrrennnrnnsnnnnrnnnen 2 5 4 1 Mapped Registers Bank0 Gei 4 2 4 2 Mapped Registers Bank1 Gei 4 4 4 3 Each Function Description and Pin Assignment of P3CON in 24 Pin Package 4 33 5 1 S3F80K5 Interrupt VectorS citrico tae Dees te 5 5 5 2 Interrupt Control Register OvervieW vener rennnrrnnnnnnnnrnrennnrnnnnnrnnennenen 5 6 5 3 Vectored Interrupt Source Control and Data Registers w
125. charge storage for the overall system We recommend that R1 100hm C1 0 1uF and C2 100uF VBAT 3 6V Note 2 VBAT 1 65V VR Note1 VF VDD falling time should be at least 100us for stabilized IVC VDD VR VDD rising time should be at least 500us for stabilized IVC VDD Figure 7 6 Guide line of chip operating voltage Table 7 1 Falling and rising time of operating voltage NOTES 1 In order to reduce overshoot VR is longer than VF 2 Since VDD 3 6V is the worst case IVC VDD will be stabilized when VF gt 100us VR gt 500us ELECTRONICS 7 5 S3F80K5 UM REV1 11 RESET RESET OVERVIEW Resetting the MCU is the function to start processing by generating reset signal using several reset schemes During reset most control and status are forced to initial values and the program counter is loaded from the reset vector In case of S3F80K5 reset vector can be changed by smart option Refer to the page 2 3 or 15 5 RESET SOURCES The S3F80K5 has six different system reset sources as following Watch Dog Timer WTD When watchdog timer enables in normal operating a reset is generated whenever the basic timer overflow occurs Low Voltage Detect LVD When VDD is changed in condition for LVD operation in the normal operating mode reset occurs Internal Power ON Reset IPOR When VDD is changed in condition for IPOR operation a reset is generated External Interrupt INTO INT6 When RESET Control Bit is set t
126. cks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 92 R IR Given Register 00H 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 000H gt Register OOH 41H register 02H 6FH register 42H 6FH If general register OOH contains the value 42H and register 42H the value 6FH the statement POPUD 02H 00H loads the contents of register 42H into the destination register 02H The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI Operation Flags Format Example dei erc dst lt src IR IR 1 The POPUI instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 93 R IR Given Register 00H 01H and register 01H 70H POPUI 02H 00H gt Register OOH 02H register 01H 70H register 02H 70H If general register OOH contains the value 01H and register 01H the value 70H the statement POPUI 02H
127. components One control register T1CON FAH Set 1 Bank0 R W Two 8 bit counter registers T1CNTH and T1CNTL F6H and F7H Set 1 Bank0 Read only Two 8 bit reference data registers TIDATAH and T1DATAL F8H and F9H Set 1 Banko R W One 16 bit comparator You can select one of the following clock sources as the Timer 1 clock Oscillator frequency fosc divided by 4 8 or 16 Internal clock input from the counter A module counter A flip flop output You can use Timer 1 in three ways Asanormal free run counter generating a Timer 1 overflow interrupt IRQ1 vector F4H at programmed time intervals To generate a Timer 1 match interrupt IRQ1 vector F6H when the 16 bit Timer 1 count value matches the 16 bit value written to the reference data registers To generate a Timer 1 capture interrupt IRQ1 vector F6H when a triggering condition exists at the P3 0 You can select a rising edge a falling edge or both edges as the trigger In the S3F80K5 interrupt structure the Timer 1 overflow interrupt has higher priority than the Timer 1 match or capture interrupt NOTE The CPU clock should be faster than timer 1 clock ELECTRONICS 11 1 TIMER 1 S3F80K5 UM REV1 11 TIMER 1 OVERFLOW INTERRUPT Timer 1 can be programmed to generate an overflow interrupt IRQ1 F4H whenever an overflow occurs in the 16 bit up counter When you set the Timer 1 overflow interrupt enable bit T1CON 2 to 1
128. controller eer eg RE ane Ananas 1 1 A utad degenerert badge Eed eier iden Ee did 1 2 Block Diagram 24 pin package oooococconocccononoccccnononcccnonannn nano nonn cnn narnia n 1 3 PIN ASSIGA MENTES id da dt da 1 4 EIDEN EE EE 1 6 Chapter 2 Address Spaces Ve 2 1 Program Memory uti Eed betrakteren innt 2 2 RENEE SA ETE GE it a 2 5 Register Pag Pomter PP esar a deemed E arameisk dd 2 7 LEO eeh Ee ee O Ee 2 8 Register Set A EE 2 8 Prime Register ee 2 9 e le Mee EE 2 10 Using e ed Uu 2 11 RegISt r Addressing EE 2 13 Common Working Register Area COH CFH cocccccicccononinonocccnonnnnnonc nano cnn cnn 2 15 4 Bit Working Register Addressing A 2 16 8 Bit Working Register Addressing A 2 18 System and User Stacks in nnna eea atan entan aaa aa raa tada 2 20 Chapter 3 Addressing Modes OET AREA E EE E a aia ld E 3 1 Register Addressing Mode R oococoonccccccnnnocccnnonaccnnnnonccnnnnn nc 3 2 Indirect Register Addressing Mode H 3 3 Indexed Addressing Mode 9 3 7 Direct Addr ss Mode DA sce uvurderlige eger eide 3 10 Indirect Address Mode IA rrnnnonnnnnnnnnnnnnannnnnnnannnnnnnnannnnnnnannnnnnnnnnnnnnannnnnnnannnnnnnannnnnnnsannnnnnnanennnnannnnnnne 3 12 Relative Address Mode RA ernrnnnnnvnnnnnnnvnnnnnnnvnnnvnnnnnnnvnnnvnnvnnnnnnnnnannnnntnannnnnnnannnnnnnnnnnnntnnnnnnsannnnenee 3 13 Immediate dele CHA 3 14 S3F80K5 UM REV1 11 MICROCONTROLLER Table of Contents Continued Chapter 4 Control Registers Overview
129. crystal or ceramic resonator oscillation source or an external clock Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fosc divided by 1 2 8 or 16 Clock circuit control register CLKCON ELECTRONICS 7 1 CLOCK AND POWER CIRCUITS S3F80K5 UM REV1 11 C2 XOUT Figure 7 1 Main Oscillator Circuit External Crystal or Ceramic Resonator External Clock Open Pin XOUT Figure 7 2 External Clock Circuit 7 2 ELECTRONICS S3F80K5 UM REV1 11 CLOCK AND POWER CIRCUITS CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and Idle mode affect the system clock as follows In Stop mode the main oscillator is halted When stop mode is released the oscillator starts by a reset operation or by an external interrupt To enter the stop mode STOPCON STOP Control Register has to be loaded with value 40A5H before STOP instruction execution After recovering from the stop mode by a reset or an external interrupt STOPCON register is automatically cleared In Idle mode the internal clock signal is gated away from the CPU but continues to be supplied to the interrupt structure timer 0 timer 1 counter and so on Idle mode is released by a reset or by an interrupt external or internally generated STOP STOPCON Instruction CLKCON 3 A Oscillator Stop CPU CLOCK Oscillator Wake up Noise Filter INT Pin NOTES 1 An external inter
130. ction must be included in the initialization routine which follows a reset operation in order to enable interrupt processing Although you can manipulate SYM 0 directly to enable and disable interrupts during normal operation we recommend using the El and DI instructions for this purpose System Mode Register SYM DEH Set 1 Bank 0 R W ea External Interface Tri state Enable Bit Global Interrupt Enable Bit 0 Normal operation Disable all Tri state disabled Not used Fast Interrupt Level 9 SS bable a Pps 1 Enable all 1 High impedance Selection Bits Tri state enabled Fast Interrupt Enable Bit IRQO 0 Disable fast IRQ1 1 Enable fast IRQ2 IRQ4 IRQ6 IRQ7 22220000 00 00 ch OO ech OO eck OO 0 NOTE An external memory interface is not implemented Figure 5 5 System Mode Register SYM ELECTRONICS 5 9 INTERRUPT STRUCTURE S3F80K5 UM REV1 11 INTERRUPT MASK REGISTER IMR The interrupt mask register IMR DDH Set 1 Bank0 is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 in
131. ctions SBO or SB1 are used to address one bank or the other A hardware reset operation always selects bank 0 addressing The upper two 32 byte area of set 1 bank 0 E0H FFH contains 31mapped system and peripheral control registers Also the upper 32 byte area of set1 bank1 E0H FFH contains 16 mapped peripheral control register The lower 32 byte area contains 15 system registers DOH DFH and a 16 byte common working register area COH CFH You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at all times using the Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations COH FFH is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 The set 2 locations COH FFH is accessible on page 0 in the S3F80K5 register space The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 locations to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode The s
132. d Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 and 1 Priority Control Bits for Interrupt Groups A B and C o 0 0 Groupprorty undefined Pofo t e gt cea SSCS Po prpafa 0 o ififs a e 0 i folo losas mn Oe mn Mu i oha gt e8 mn Group priority undefined SSS Group priority undefined 6 Interrupt Subgroup C Priority Control Bit IRQ6 gt IRQ7 IRQ7 gt IRQ6 BG 5 Interrupt Group C Priority Control Bit IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 3 Interrupt Subgroup B Priority Control Bit See Note IRQ3 gt IRQ4 IRQ4 gt IRQ3 1 gt Interrupt Group B Priority Control Bit See Note IRQ2 gt IRQ3 IRQ4 1 IRQ3 IRQ4 gt IRQ2 0 Interrupt Group Priority Control Bit IRQO gt IRQ1 IRQ1 gt IRQO NOTE The S3F80K5 interrupt structure uses eight levels IRQO IRQ7 je ELECTRONICS 4 1 al CONTROL REGISTERS S3F80K5 UM REV1 11 IRQ interrupt Request Register DCH Seti Bank Reset Value 0 0 0 0 0 0 0 0 Read Write R R R R R R R Addressing Mode Register addressing mode only D 7 Level 7 IRQ7 Request Pending Bit External Interrupts P0 7 P0 4 Not pending o Pending 6 Lev o I 6 IRQ6 Request Pending Bit External Interrupts P0 3 P0 0 Not pending o Pending 5 Lev bd I 5 IRQ5 Request Pending Bit External Interrupts P2 7 P2 4 Not pending Pending o A Lev o 4 IRQ4 Request Pending Bit External Interru
133. d as a single 16 bit value that is decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 80 RR 81 IR Given RO 12H R1 34H R2 30H register 30H OFH and register 31H 21H DECW RRO RO 12H R1 33H DECW R2 gt Register 30H OFH register 31H 20H In the first example destination register RO contains the value 12H and register R1 the value 34H The statement DECW RRO addresses RO and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To avoid this problem we recommend that you use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 R0 JR NZ LOOP ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET DI Disable Interrupts DI Operation Flags Format Example SYM 0 lt 0 Bit zero of the system mode control register SYM O is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled No flags are affected Bytes Cycles Opcode
134. de the manufacturer of serial tool writer could support Hardware Protection Please refer to the manual of serial program writer tool provided by the manufacturer The program procedure in user program mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 Set Flash Memory Control Register FMCON to 01100001B 3 Set Flash Memory User Programming Enable Register FMUSR to 00000000B PROGRAMMING TIP Hard Lock Protection SB1 LD FMUSR 0A5H User program mode enable LD FMCON 01100001B Select Hard Lock Mode and Start protection LD FMUSR 00H User program mode disable SBO ELECTRONICS 13 17 S3F80K5 UM REV1 11 LOW VOLTAGE DETECTOR LOW VOLTAGE DETECTOR OVERVIEW The S3F80K5 micro controller has a built in Low Voltage Detector LVD circuit which allows LVD and LVD_FLAG detection of power voltage The S3F80K5 has two options in LVD and LVD_FLAG voltage level according to the operating frequency to be set by smart option Refer to the page 2 4 Operating Frequency 8MHz e Low voltage detect level for Backup Mode and Reset LVD 1 75V Typ 100mV e Low voltage detect level for Flash Flag Bit LVD FLAG 1 90 2 00 2 10 2 20V Typ 100mV After power on LVD block is always enabled LVD block is only disable when executed STOP instruction The LVD block of S3F80K5 consists of two comparators and a resistor string One of comparators is for LVD detection and the other
135. deu 2 11 Using the RPs to Calculate the Sum of a Series of Hegisters renn nrnnnnnnnnnrrenrnrrnnnnnnnrnnenen 2 12 Addressing the Common Working Register Area 2 16 Standard Stack Operations Using PUSH and DOP 2 21 Chapter 8 Reset To enter S TORMO aan E E EE 8 11 Chapter 10 Basic Timer and Timer 0 Gonfiguring the Basic TIME semi cda 10 10 Programming TIMO ada da 10 11 Chapter 12 Counter A To generate 38 kHz 1 3duty signal through D 12 6 To generate a one pulse signal through DI 12 7 To generate a one pulse signal through DI 12 7 Chapter 13 Embedded Flash Memory Interface SeclorErase EE E 13 10 Programming EE 13 15 RE Le re DEE EE 13 17 Hard Lock Protection tidad A AAA A ie 13 18 S3F80K5 UM REV1 11 MCROCONTROLLER xv List of Register Descriptions Register Full Register Name Page Identifier Number BTCON Basic Timer Control Register rrrrrrnrrnnnnrnnnnnvnrnrrvnnnvrnnnnnvnnerrennnrnnsnnnnnennenssrrensnnnnnennne 4 6 CACON Counter A Control Register ooocniccononicinoccnnncccconccononnnnnnnccnnn cnn anna nn nana nn cnn naaa narran 4 7 CLKCON System Clock Control Register oooooonncccinnccnnccnnnnonnnccnnncccnnrrnn narran cnc rn 4 8 EMT External Memory Timing Hegtsier naar nccc nana ncccnns 4 9 FLAGS System Flags Register AA 4 10 FMCON Flash Memory Control Hegleter crac nn 4 11 FMSECH Flash Memory Sector Address Register High Biel 4 12 FMSECL Flash Memory Sector Address Register Low Die 4 12 FMUSR Flash Memory
136. dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 A3 r Ir ODC src dst 3 6 A4 R R A5 R IR opc dst src 3 6 A6 R IM 1 Given R1 02H and R2 03H CP R1 R2 gt Setthe C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are Tat 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INGR1 SKIP LD R3 R1 In this example destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates C 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in working register R3 ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET CPIJE CPIJE Operation Flags Format Example Compare Increment and Jump on Equal dei erc RA If dst src 0 PC PC RA Ir Ir 1 The source operand is compared to subtracted from the destination operand If the result is 0 the relative address is added to the pro
137. e 5 7 Group A IRQO IRQ1 Group B IRQ2 IRQ3 IRQ4 Group C IRQ5 IRQ6 IRQ7 C21 IRQO IRQ1 IRQ2 IRQ6 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B gt C gt A the setting 101B would select the relationship C gt B gt A The functions of the other IPR bit settings are as follows e IPR 5 controls the relative priorities of group C interrupts e Interrupt group B has a subgroup to provide an additional priority relationship between for interrupt levels 2 3 and 4 IPR 3 defines the possible subgroup B relationships IPR 2 controls interrupt group B e PR O controls the relative priority setting of IRQO and IRQ1 interrupts ELECTRONICS 5 11 INTERRUPT STRUCTURE S3F80K5 UM REV1 11 Interrupt Priority Register IPR FEH Set 1 Bank 0 R W MSB Group Priority Group A 0 IRQO gt IRQ1 D DI 1 IRQO lt IRQ1 el N Group B 0 IRQ2 gt IRQ4 1 IRQ2 lt IRQ4 Undefined B gt C gt A A gt B gt C B gt A gt C Not used C gt A gt B C gt B gt A A gt C gt B Undefined Group C IRQ5 gt IRQ6 IRQ7 IRQ6 IRQ7 gt IRQ5 0 0 0 0 1 1 1 1 4400 4400 ch OO ch OO ch OO sch OH 0 1 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6
138. e Bit 0 Disable interrupt 1 Enable interrupt Timer 0 Overflow Interrupt Enable Bit 0 Disable overflow interrupt 1 Enable overflow interrupt Timer 0 Counter Clear Bit 0 No effect 1 Clear the timer 0 counter when write Timer 0 Operating Mode Selection Bits 00 Interval mode 01 Capture mode capture on rising edge counter running OVF can occur 10 Capture mode capture on falling edge counter running OVF can occur 11 PWM mode OVF interrupt can occur NOTE The external clock source of timer 0 is P3 1 TOCK in 32 pin package or P3 2 TOCK in 44 pin package Figure 10 2 Timer 0 Control Register TOCON Timer 0 Data Register TODATA D1H Gett Bank 0 R W Reset Value FFH Figure 10 3 Timer 0 DATA Register TODATA ELECTRONICS 10 5 BASIC TIMER and TIMER 0 S3F80K5 UM REV1 11 TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts IRQO Vectors FAH and FCH The timer 0 module can generate two interrupts the timer 0 overflow interrupt TOOVF and the timer O match capture interrupt TOINT TOOVF is interrupt with level IRQO and vector FAH TOINT also belongs to interrupt level IRQO but is assigned the separate vector address FCH A timer 0 overflow interrupt TOOVF pending condition is automatically cleared by hardware when it has been serviced The TOINT pending condition must however be cleared by the application s interrupt service routine by writing a 1 to the TOCON interr
139. e LVD Mode STOPCON Rising Edge Detector BT RESET Contorl Bit 1 dees ae STOPCON Enabled PO amp P2 External Interrupt INTO INT9 Control Block PoP Ce Noise INTO INT9 Filter SED amp R Falling Edge Circuit STOPCON D STOP D RESET Contorl Bit 1 gt RESET Control Bit smart option bit 0 03FH Figure 8 2 RESET Block Diagram of The S3F80K5 ELECTRONICS RESET 8 3 RESET S3F80K5 UM REV1 11 RESET MECHANISM The interlocking work of reset pin and LVD circuit supplies two operating modes back up mode input and system reset input Back up mode input automatically creates a chip stop state when the reset pin is set to low level or the voltage at Vpp is lower than Vi yp When the reset pin is at a high state and the LVD circuit detects rising edge of Vpp on the point Vi yp the reset pulse generator makes a reset pulse and system reset occurs When the operating mode is in STOP mode the LVD circuit is disabled to reduce the current consumption under 5uA at Vpp 3 6 V Therefore although the voltage at Vpp is lower than V yp the chip doesn t go into back up mode when the operating state is in stop mode and reset pin is High level Vreset gt Vip WATCH DOG TIMER RESET The watchdog timer that can recover to normal operation from abnormal function is built in S3F80K5 Watchdog timer generates a system reset signal if Basic Timer Counter BTCNT isn t cleared within a specific time by program For more und
140. e stop mode To release Idle mode you can use either an external interrupt or an internally generated interrupt 8 8 ELECTRONICS S3F80K5 UM REV1 11 RESET BACK UP MODE For reducing current consumption S3F80K5 goes into Back up mode If a falling level of Vpp is detected by LVD circuit on the point of Vi yp chip goes into the back up mode CPU and peripheral operation are stopped but LVD is enabled Because of oscillation stop the supply current is reduced In back up mode chip cannot be released from stop state by any interrupt The only way to release back up mode is the system reset operation by interactive work of LVD circuit The system reset of watchdog timer is not occurred in back up mode Rising Edge LVD Detector Falling Edge Detector Back Up Mode nRESET Figure 8 6 Block Diagram for Back up Mode Voltage V Slope of nRESET A VDD Pin Rising edge detected VDD gt VLVD Low level detect voltage Reset Pulse generated oscillation starts Falling edge detected oscillation stop VDD lt VLVD Normal Operation Back up Mode Normal Operation NOTES 1 When the rising edge is detected by LVD circuit Back up mode is relesased VLVD VDD 2 When the falling edge is detected by LVD circuit Back up mode is activated VLVD gt VDD Figure 8 7 Timing Diagram for Back up Mode Input and Released by LVD ELECTRONICS 8 9 RESET S3F80K5 UM REV1 11 Stop Mode LVD off WA
141. ear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer and Timer 0 2 o No effect Clear both block frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to OOH Immediately following the write operation the BTCON 1 value is automatically cleared to 0 2 When you write a 1 to BTCON O the corresponding frequency divider is cleared to 00H Immediately following the write operation the BTCON 0 value is automatically cleared to 0 4 6 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS CACON Counter A Control Register F3H Seti Bank0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 6 Counter A Input Clock Selection Bits 5 and A Counter A Interrupt Timing Selection Bits fo o Elapsed time for Low data value Elapsed time for High data value Oe Elapsed time for combined Low and High data values Not used for S3F80K5 3 Counter A Interrupt Enable Bit o Disable interrupt Enable interrupt 2 Counter A Start Bit o Stop counter A Start counter A 1 Counter A Mode Selection Bit EN One shot mode Repeating mode 0 Counter A Output Flip Flop Control Bit 0 Flip Flop Low level T FF Low Flip flop High level T FF High ELECTRONICS 4 7 CONTROL REGISTERS S3F80K5 UM REV1 11 CLKCON System Clock Control Register D4H
142. ear timer0 match capture interrupt pending conditions TOCON is located in Set 1 BankO at address D2H and is read write addressable using register addressing mode A reset clears TOCON to 00H This sets timer 0 to normal interval timer mode selects an input clock frequency of fOSC 4096 and disables all timer 0 interrupts You can clear the timer 0 counter at any time during normal operation by writing a 1 to TOCON 3 The timer 0 overflow interrupt TOOVF is interrupt level IRQO and has the vector address FAH When a timer0 overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware To enable the timer 0 mach capture interrupt IRQO vector FCH you must write TOCON 1 to 1 To detect a match capture interrupt pending condition the application program polls TOCON O When a 1 is detected a timerO match or capture interrupt is pending When the interrupt request has been serviced the pending condition must be cleared by software by writing a 0 to the timer0 interrupt pending bit TOCON O 10 4 ELECTRONICS S3F80K5 UM REV1 11 BASIC TIMER and TIMER 0 Timer 0 Control Register TOCON D2H Set 1 Bank0 R W Timer 0 Interrupt Pending Bit 0 No interrupt pending Timer 0 Input Clock Selection Bits 0 Clear pending bit when write 00 fosc 4096 1 Interrupt is pending 01 fosc 256 10 fosc 8 11 External clock NOTE Timer 0 Interrupt Match capture Enabl
143. ed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration No flags are affected Bytes Cycles Opcode Hex opc 1 4 FF When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ELECTRONICS 6 61 INSTRUCTION SET S3F80K5_UM_REV1 11 OR Logical OR OR Operation Flags Format Examples dst src dst lt dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex del src 6 43 r Ir opc src dst 3 6 44 R R 45 R IR opc dst src 3 6 46 R IM Given RO 15H R1 2AH R2 01H register OOH 08H register 01H 37H and register 08H 8AH OR RO R1 gt RO 3FH R1 2AH OR RO R2 gt RO 37H R2 01H register 01H 37H OR 00H 01H gt Register OOH 3FH register 01H 37H OR 01H G00H gt Register 00H 08H register 01H OBFH OR 00H 402H gt Register 00H OAH In the first exam
144. edges or both edges all PO pin circuits have noise filters and interrupt enable disable register POINT and pending control register POPND Pull up resistors can be assigned to individual PO pins using POPUR register settings This port is dedicated for key input in IR controller application Port 1 8 bit general purpose l O port Input without or with pull up open drain output or push pull output This port is dedicated for key output in IR controller application interrupts and P2PND bits can be polled by software for interrupt pending control Pull up resistors Port 2 8 bit general purpose I O port Input push pull output or open drain output The P2 0 can be used as external interrupt inputs and have noise filters The P2INT register is used to enable disable can be assigned to individual P2 pins using P2PUR register settings P3 0 P3 1 2 bit I O port P3 0 and P3 1 are configured input functions Input mode with or without pull up for TOCK TOCAP or T1CAP or output functions push pull or open drain output mode or for REM and TOPWM P3 1 is dedicated for IR drive pin and P3 0 can be used for indicator LED drive 9 2 ELECTRONICS S3F80K5 UM REV1 11 I O PORTS PORT DATA REGISTERS Table 9 4 gives you an overview of the register locations of all four S3F80K5 I O port data registers Data registers for ports 0 1 have the general format shown in Figure 9 1 NOTE The data register for port 3 P3 contains 2 bits for P
145. egister Arez cn nano cnn nc cra rn nnnn cnn 2 15 2 12 4 Bit Working Register Addresemg AA 2 17 2 13 4 Bit Working Register Addressing Exvample AAA 2 17 2 14 8 Bit Working Register Addreseimg nn nnn nn rnnnn cnn 2 18 2 15 8 Bit Working Register Addressing Example nano nanancccno 2 19 2 16 Eege NEE 2 20 3 1 Register Addressing ssecicisscsccecgsecestesseunetecssannes cgsuanetasseennecanasneescoaetnetesseentasenestenasaeenes cs 3 2 3 2 Working Register Addressing ccccceeeeceeeeeeeceaeeeceeeeseaeeecaaeeesaaeseeeeeseaeeesaaeeeeneeseaees 3 2 3 3 Indirect Register Addressing to Register File 3 3 3 4 Indirect Register Addressing to Program Memory 2 cccccceseeeeseseeeeeteeeeeeeeseees 3 4 3 5 Indirect Working Register Addressing to Register Elle 3 5 3 6 Indirect Working Register Addressing to Program or Data Memory sses 3 6 3 7 Indexed Addressing to Register File 3 7 3 8 Indexed Addressing to Program or Data Memory with Short Offset rnrannrnnrnnnnn 3 8 3 9 Indexed Addressing to Program or Data Memory ernrnnnvvnnnnnnnvrnnnnnnvrnnnnnnrrnnnnrnnrrnnenn 3 9 3 10 Direct Addressing for Load Instructons caca ncccn rca nrrnnn cnn 3 10 3 11 Direct Addressing for Call and Jump Instructions urnreronrrrrnrrrnnnrnnnnnrnnnnrrnnnnrnnennennn 3 11 3 12 Indirect Addressing AA 3 12 3 13 Relative ele ue WE 3 13 3 14 Immediate Addressing rn nrnnonnrennnr renn nrnnnnnnnrenrennn ane nnnnenresnnrnennnnnnennennn 3 14 4 1 Register Desc
146. elect ROM Address 003CH Not used ROM Address 003DH Not used ROM Address 003EH ISP Reset Vector Address Selection Bits 2 10 1024 bytes 00 200H ISP Area size 256 bytes Pe 01 300H e Area size 512 bytes ISP Protection Enable Disable Bit 10 500H ISP Area size 1024 bytes 0 Enable Not erasable 11 900H ISP Area size 2048 bytes 1 Disable Erasable ISP Reset Vector Change TEE Bit 1 ee used ISP Protection Size 0 OBP Reset vector address Selection Bits 1 Normal vector address 100H 00 256 bytes 01 512 bytes ROM Address 003FH Not used RESET Control Bit 0 External interrupts by PO and P2 or SED amp R generate the reset signal 1 External interrupts by PO and P2 or SED amp R do not generate the reset signal Figure 2 2 Smart Option ELECTRONICS 2 3 ADDRESS SPACE S3F80K5 UM REV1 11 2 4 NOTES By setting ISP Reset Vector Change Selection Bit 3EH 7 to 0 user can have the available ISP area If ISP Reset Vector Change Selection Bit 3EH 7 is 1 3EH 6 and 3EH 5 are meaningless If ISP Reset Vector Change Selection Bit 3EH 7 is 0 user must change ISP reset vector address from 0100H to some address which user want to set reset address 0200H 0300H 0500H or 0900H If the reset vector address is 0200H the ISP area can be assigned from 0100H to 01FFH 256bytes If 0300H the ISP area can be assigned from 0100H to 02FFH 51 2by
147. eneral register 03H from OFFH to OOH and register 02H from OFH to 10H A system malfunction may occur if you use a Zero Z flag FLAGS 6 result together with an INCW instruction To avoid this problem we recommend that you use INCW as shown in the following example LOOP INCW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS 6 45 INSTRUCTION SET S3F80K5_UM_REV1 11 IRET Interrupt Return IRET Operation Flags Format Example NOTE IRET Normal IRET Fast FLAGS lt SP PC lt IP SP e SP 1 FLAGS lt FLAGS PC lt OSP FIS lt 0 SP amp SP 2 SYM 0 1 This instruction is used at the end of an interrupt service routine lt restores the flag register and the program counter lt also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of the FLAGS register 0D5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is the settings before the interrupt occurred IRET Bytes Cycles Opcode Hex Normal opc 1 10 internal stack BF 12 internal stack IRET Bytes Cycles Opcode Hex Fast opc 1 6 BF In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped
148. epeat mode for Counter A Start Counter A operation Set Counter A Output Flip flop CAOF high LD P3 80H Set P3 7 Carrier On Off to high This command generates 38 kHz 1 3duty pulse signal through P3 1 12 6 ELECTRONICS S3F80K5 UM REV1 11 COUNTER A L PROGRAMMING TIP To generate a one pulse signal through P3 1 This example sets Counter A to the one shot mode sets the oscillation frequency as the Counter A clock source and CADATAH and CADATAL to make a 40 us width pulse The program parameters are 40 us lt gt Counter A is used in one shot mode Oscillation frequency is 4 MHz 1 clock 0 25 us CADATAH 40 us 0 25 us 160 CADATAL 1 Set P3 1 C MOS push pull output and CAOF mode ORG 0100H Reset address START DI LD CADATAH 160 2 Set 40 ms LD CADATAL 1 Set any value except 00H LD P3CON 11110010B Set P3 to C MOS push pull output Set P3 1 to REM output LD CACON 00000001B Clock Source gt Fosc Disable Counter A interrupt Select one shot mode for Counter A Stop Counter A operation Set Counter A Output Flip Flop CAOF high LD P3 80H Set P3 7 Carrier On Off to high Pulse_out LD CACON 00000101B Start Counter A operation to make the pulse at this point After the instruction is executed 0 75 ms is required before the falling edge of the pulse starts ELECTRONICS 12 7 S3F80K5 UM REV1 11 EMBEDDED FLASH MEMORY INTERFACE
149. er On Reset IPOR External Interrupt INTO INT9 SED amp R circuit Using IPOR to Release STOP Mode Stop mode is released when the system reset signal goes active by internal power on reset IPOR All system and peripheral control registers are reset to their default hardware values and contents of all data registers are unknown states When the oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in reset address Using an External Interrupt to Release STOP Mode External interrupts can be used to release stop mode When RESET Control Bit is set to 0 smart option 03FH and external interrupt is enabled S3F80K5 is released from stop mode and generates reset signal On the other hand when RESET Control Bit are set to 1 smart option 03FH S3F80K5 is only released from stop mode and does not generate reset signal To wake up from stop mode by external interrupt from INTO to INT5 external interrupt should be enabled by setting corresponding control registers or instructions Please note the following conditions for Stop mode release If you release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged If you use an external interrupt for Stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the ap
150. er Programming Enable Register FMUSR to 00000000B SB1 Select Bank1 FMUSR 4 0A5H User Programimg Mode Enable FMSECH High Address of Sector FMSECL lt Low Address of Sector poet Sector Base Address FMCON lt 10100001B Mode Select amp Start Erase FMUSR 00H User Prgramming Mode Disable Select Bank0 Finish One Sector Erase Figure 13 8 Sector Erase Flowchart in User Program Mode NOTES If user erases a sector selected by Flash Memory Sector Address Register FMSECH and FMSECL FMUSR should be enabled just before starting sector erase operation And to erase a sector Flash Operation Start Bit of FMCON register is written from operation stop 0 to operation start 1 That bit will be cleared automatically just after the corresponding operation completed In other words when S3F80K5 is in the condition that flash memory user programming enable bits is enabled and executes start operation of sector erase it will get the result of erasing selected sector as user s a purpose and Flash Operation Start Bit of FMCON register is also clear automatically If user executes sector erase operation with FMUSR disabled FMCON O bit Flash Operation Start Bit remains high which means start operation and is not cleared even though next instruction is executed So user should be careful to set FMUSR when executing sector erase for no effect on other flash sectors ELECTRONICS S3F
151. erand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C Flags Format Examples C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 EO R E1 IR Given Register OOH 31H register 01H 02H and register 02H 17H RR 00H gt Register OOH 98H C 1 RR 01H gt Register 01H 02H register 02H 8BH C 1 In the first example if general register OOH contains the value 31H 00110001B the statement RR OOH rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and overflow flag are also set to 1 ELECTRONICS 6 73 INSTRUCTION SET S3F80K5_UM_REV1 11 RRC Rotate Right Through Carry RRC Operation dst dst 7 C C lt dst 0 dst n lt dst n 1 n 0 6 The contents of the destination operand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carr
152. erstanding of the watchdog timer function please see the chapter 11 Basic Timer and Timero LVD RESET The Low Voltage Detect Circuit LVD is built on the S3F80K5 product to generate a system reset LVD is disabled in stop mode When the voltage at Vpp is falling down and passing Vi yp the chip goes into back up mode at the moment Mon VLyp As the voltage at Vpp is rising up the reset pulse is occurred at the moment Vop 2 Vivo STOPCON note 2 note 3 gt STOP Instruction Figure 8 3 RESET Block Diagram by LVD for The S3F80K5 in Stop Mode NOTES LVD is disabled in stop mode LVD always operates in any other operation modes 2 CPU can enter stop mode by setting STOPCON Stop Control Register into OASH before execution STOP instruction 3 This signal is output relating to STOP mode If STOPCON has OA5H and STOP instruction is executed that output signal makes S3F80K5 enter STOP mode So that is one of two statuses one is STOP mode the other is not STOP mode 8 4 ELECTRONICS S3F80K5 UM REV1 11 RESET INTERNAL POWER ON RESET The power on reset circuit is built on the S3F80K5 product When power is initially applied to the MCU or when Von drops below the Vpop the POR circuit holds the MCU in reset until Vpp has risen above the Vi yp level 4 gt gt Normal Operating Mode Reset Pulse Internal RESET Release Figure 8 4 Timing Diagram for Internal Power On Reset Circuit ELECTRONI
153. eset Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory Sector Address Low Byte Note The low byte flash memory sector address pointer value is the lower eight bits of the 16 bit pointer address FMUSR Flash Memory User Programming Enable Register EEH Seti Bank1 Bit Identifier 7 6 5 4 3 2 af o 0 0 0 0 0 0 0 0 Reset Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory User Programming Enable Bits o o o i o Enable user programming mode NOTES 1 To enable flash memory user programming write 10100101B to FMUSR 2 To disable flash memory operation write other value except 10100101B into FMUSR 4 12 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS IMR Interrupt Mask Register DDH Seti Bank Reset Value xX x x X Xx x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Enable Bit External Interrupts P0 7 P0 4 Disable mask 1 Enable un mask 6 Interrupt Level 6 IRQ6 Enable Bit External Interrupts P0 3 P0 0 Disable mask o Enable un mask 5 Interrupt Level 5 IRQ5 Enable Bit External Interrupts P2 7 P2 4 Disable mask o Enable un mask A Interrupt Level 4 IRQ4 Enable Bit External Interrupts P2 3 P2 0 Disable mask 1 Enable un mask 3 Interrupt Level 3 IRQ3
154. et 2 register area is commonly used for stack operations 2 8 ELECTRONICS ADDRESS SPACE S3F80K5 UM REV1 11 PRIME REGISTER SPACE The lower 192 bytes of the 256 byte physical internal register file 00H BFH are called the prime register space or more simply the prime area You can access registers in this address using any addressing mode In other words there is no addressing mode restriction for these registers as is the case for set 1 and set 2 registers The prime register area on page 0 is immediately addressable following a reset SS SSN SS SS SS IS yyy 2 w D bs Area Figure 2 5 Set 1 Set 2 and Prime Area Register Map 2 9 ELECTRONICS ADDRESS SPACE S3F80K5 UM REV1 11 WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as consisting of 32 8 byte register groups or slices Each slice consists of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any one time to form a 16 byte working register block Using the register pointers you can move this 16 byte register block anywhere in the addressable register file except for the set 2 area The terms slice and block are used in this manual to help you
155. etailed descriptions of the S3F80K5 control registers are presented in an easy to read format You can use this section as a quick reference source when writing application programs Figure 4 1 illustrates the important features of the standard register description format Control register descriptions are arranged in alphabetical order A Z according to the register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual Data and counter registers are not described in detail in this reference section More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual ELECTRONICS 4 1 CONTROL REGISTERS S3F80K5 UM REV1 11 Table 4 1 Mapped Registers Bank Gei Bereet Decimal me rw Glock Conti Register oseo a2 om aw Srem Fags egos D mo ost mL Seet m aa Rogier Pomert ef as om Sebaa sm La Instruction Pointer high Byt mem as tegen Pointer Low Byte m Ja eng Request eger 1 mo engt Register 1 m System Mode Register 1 sm mm er re rs R W R W R W R NOTE R W R W R W R W R W 220 221 222 er 224 SR 22 227 Reserved E4H Port 2 Interrupt Enable Register Pant 2 Port 2 Interrupt Pending Register P2PND 200 Port 0 Pul up Resistor Enable Register
156. f P3CON in 24 Pin Package ss ea es e2 erje m mu SES eo e a Namal ell neen Namal rope pepe aft veemer wmao propa ema mao Poppe fe fo II IO TN Tope meme ver pepe fe x Pe Namal toc SES pa fe fx fe Nema BREEDE ELECTRONICS 4 33 CONTROL REGISTERS S3F80K5 UM REV1 11 P3OUTPU port 3 Output Pull up Resistor Enable Register F4H Seti Bank Bit Identifier Reset Value Read Write Addressing Mode 7 and 2 4 34 7 6 6s 3 2 a o z z 0 0 R W R W Register addressing mode only Not used for S3F80K5 P3 1 Output Mode Pull up Resistor Enable Bit o Disable pull up resistor Enable pull up resistor P3 0 Output Mode Pull up Resistor Enable Bit o Disable pull up resistor Enable pull up resistor ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS PP Register Page Pointer DFH Seti Bank Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Destination Register Page Selection Bits o o o 0 Destination page o eeno gt 3 0 Source Register Page Selection Bits o ofofo source pageo Seno NOTE Inthe S3F80K5 microcontroller a paged expansion of the internal register file is not implemented For this reason only page 0 settings are valid Register page pointer values for the source and destination register page are automatically set to 0000B following a hardware reset These
157. fied destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR opc dst 2 14 D4 IA Given RO 35H R1 21H PC 1A47H and SP 0002H CALL 3521H gt SP 0000H Memory locations 0000H 1AH 0001H 4AH where 4AH is the address that follows the instruction CALL RRO gt SP 0000H 0000H 1AH 0001H 49H CALL 40H gt SP 0000H 0000H 1AH 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location OOOOH The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and stack pointer are the same as in the first example the statement CALL RRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of
158. fier 7 6 E A CONTROL REGISTERS Register address Set Register address Bank Register address Hexadecimal D5H Seti Bank0 3 1 0 Reset Value x x x x Read Write p R W R W R W R W Carry Flag Bit C ol Operation dose not generate a carry or borro Operation generates carry out or borrow into High order bit7 Zero Flag Bit Z x x 0 0 R W R W R W R W Sign Flag Bit S 0 Operation result is a non zero value Operation result is zero A Operation generates positive number MSB 0 0 1 R Read only W Write only R W Read write Not used bit settings Addressing mode or modes you can use to modify register values Description of the effect of specific Operation generates negative number MSB 3 1 RESET value notation Not used x Undetermind value 0 Logic zero T Logic on Bit number MSB Bit 7 LSB Bit 0 Figure 4 1 Register Description Format ELECTRONICS 4 5 CONTROL REGISTERS S3F80K5 UM REV1 11 BTCON Basic Timer Control Register D3H Seti Bank Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Watchdog Timer Function Enable Bits for System Reset 10 1 0 Disable watchdog timer function Any other value Enable watchdog timer function 3 and 2 Basic Timer Input Clock Selection Bits 1 Basic Timer Counter Clear Bit 1 EA No effect Cl
159. fofoftfof tl Enalestormode NOTES 1 To get into STOP mode stop control register must be enabled just before STOP instruction 2 When STOP mode is released stop control register STOPCON value is cleared automatically 3 Itis prohibited to write another value into STOPCON 4 38 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS SYM System Mode Register DEH Seti Bank Reset Value 0 xX X Xx 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Tri State External Interface Control Bit note1 o Normal operation disable tri state operation Set external interface lines to high impedance enable tri state operation 6 and 5 Not used for S3F80K5 note2 4 2 Fast Interrupt Level Selection Bits n te3 1 Fast Interrupt Enable Bit note4 o Disable fast interrupt processing Enable fast interrupt processing 0 Global Interrupt Enable Bit notes o Disable global interrupt processing Enable global interrupt processing NOTES 1 Because an external interface is not implemented for the S3F80K5 SYM 7 must always be 0 2 Although the SYM register is not used SYM 5 should always be 0 If you accidentally write a 1 to this bit during normal operation a system malfunction may occur You can select only one interrupt level at a time for fast interrupt processing Setting SYM 1 to 1 enables fast interrupt processing for the interrupt level currently selected by
160. for a total of 19 bit programmable pins 24 SOP 24 SDIP Carrier Frequency Generator e One 8 bit counter with auto reload function and one shot or repeat control Counter A Basic Timer and Timer Counters e One programmable 8 bit basic timer BT for oscillation stabilization control or watchdog timer software reset function e One 8 bit timer counter Timer 0 with three operating modes Interval mode Capture and PWM mode e One 16 bit timer counter Timer1 with two operating modes Interval and Capture mode S3F80K5 UM REV1 11 Back up Mode When Vpp is lower than V yp LVD is ON and the chip enters Back up mode to block oscillation When reset pin is lower than Input Low Voltage VIL the chip enters Back up mode to block oscillation and reduce the current consumption Low Voltage Detect Circuit Low voltage detect to get into Back up mode and Reset 1 75V Typ 100mV Low voltage detect to control LVD Flag bit 1 90 2 00 2 10 2 20V Typ 100mV selectable LVD Reset is enabled in the operating mode When the voltage at VDD is falling down and passing Vi yp the chip goes into back up mode The voltage at VDD is rising up the reset pulse is generated at VDD gt V yp LVD is disable in the stop mode If the voltage at VDD is not falling down to Vpop the reset pulse is not generated Operating Temperature Range 25 C to 85 C Operating Voltage Range 1 65V to 3 6V at 1 8MHz Package Ty
161. g to the input signals to the pins listed in Table 17 2 below Table 17 2 Operating Mode Selection Criteria Address V po TEST ei wus ag inl me 33v 33v 0 00004 1 Flash ROM read 33v 0 00004 o Flash ROM program OESFH 0 Flash ROM read protection NOTE 0 means Low level 1 means High level 17 4 ELECTRONICS S3F80K5 UM REV1 11 ELECTRICAL DATA DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system on a turnkey basis The development support system is composed of a host system debugging tools and supporting software For a host system any standard computer that employs Win95 98 2000 XP as its operating system can be used A sophisticated debugging tool is provided both in hardware and software the powerful in circuit emulator OPENice i500 and SK 1200 for the S3C7 S3C9 and S3C8 microcontroller families Samsung also offers supporting software that includes debugger an assembler and a program for setting options TARGET BOARDS Target boards are available for all the S3C8 S3F8 series microcontrollers All the required target system cables and adapters are included on the device specific target board TB80K9 is a specific target board for the development of application systems using S3F80K5 PROGRAMMING SOCKET ADAPTER When you program S3F80K5 s flash memory by using an emulator or OTP MTP writer you need a specific programming socket adapter for S3F
162. gister leaving the value 07H in register RO In the second example OOH is the destination register The statement LD 00H O RO loads bit zero of register RO to the specified bit bit zero of the destination register leaving 04H in general register 00H ELECTRONICS 6 51 INSTRUCTION SET LDC LDE Load Memory LDC LDE Operation Flags Format 10 dst src dst lt src S3F80K5_UM_REV1 11 This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes Irr or rr values an even number for program memory and odd an odd number for data memory No flags are affected Bytes Cycles 2 w opc src dst 2 10 ODC dst src 3 12 3 1 opc dst src XL XLy 4 14 src dst XL XLy 4 14 opc DA DAy 4 14 NOTES Opcode Hex C3 D3 E7 F7 A7 B7 A7 B7 A7 B7 Addr Mode dst sre r Irr Irr r r XS rr XS rr r r XL rr XL rr r r DA DA r r DA DA r 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats 3 and 4 the destination address XS rr and the source address XS rr are each one byte 3 For formats 5 and 6 the destination address XL rr and the source address XL rr are each two bytes 4 The DA andr source values for formats 7 and 8 are used to address p
163. gram counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src SS 3 2 rv NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 03H and register 03H 02H CPIJE R1 R2 SKIP gt R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 0000001 0B to 02H 00000010B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET S3F80K5_UM_REV1 11 CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example dst src RA If dst sre 0 PC PC RA Ir Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the p
164. he TM operation ELECTRONICS 6 85 INSTRUCTION SET S3F80K5_UM_REV1 11 WEI wait For Interrupt WFI Operation Flags Format Example The CPU is effectively halted until an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including a fast interrupt No flags are affected Bytes Cycles Opcode Hex opc 1 An 3F n 1 2 3 The following sample program structure shows the sequence of operations that follow a WEI statement Main program El Enable global interrupt WE Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed ELECTRONICS S3F80K5 UM REV1 11 XOR Logical Exclusive OR XOR Operation Flags Format Examples dei erc dst lt dst XOR src INSTRUCTION SET The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different otherwise a 0 bit is stored C Unaffected N Always reset to 0 Unaffected Unaffected SMS P ODC dst src opc src dst opc dst src Set if the result is 0 cleared otherwise Set if the result bit 7 is set cleared otherwise Bytes Cycles 2 3 3 6 O
165. he operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src 6 33 r Ir ODC src dst 3 6 34 R R 35 R IR opc dst src 3 6 36 R IM Examples Given R1 10H R2 03H C 1 register 01H 20H register 02H 03H and register 03H OAH SBC R1 R2 R1 OCH R2 03H SBC R1 R2 R1 05H R2 03H register 03H OAH SBC 01H 02H Register 01H 1CH register 02H 03H SBC 01H 02H Register 01H 15H register 02H 03H register 03H OAH SBC 01H 8AH gt Register 01H 95H C S and V 1 3 3 3 In the first example if working register R1 contains the value 10H and register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in register R1 ELECTRONICS 6 77 INSTRUCTION SET S3F80K5_UM_REV1 11 SCF set Carry Flag SCF Operation Flags Format Example Cei The carry flag C is set to logic one regardless of its previous value C Setto 1 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 DF The statement SCF sets the carry flag to logic one ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET SR
166. i Bank0 Bit Identifier A AMES AA Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 6 P0 7 INT4 Mode Selection Bits fo o C MOS input mode interrupt on falling edges Evga C MOS input mode interrupt on rising and falling edges EREM Push pull output mode C MOS input mode interrupt on rising edges 5 and A P0 6 INT4 Mode Selection Bits FAEN C MOS input mode interrupt on falling edges EES C MOS input mode interrupt on rising and falling edges 1 EN Push pull output mode C MOS input mode interrupt on rising edges 3 and 2 P0 5 INT4 Mode Selection Bits 0 o C MOS input mode ntemupt on tating sages 0 6 05 input mode interrupt on rising and fling edges Pr fo Push puoutputmode 1 and 0 P0 4 INT4 Mode Selection Bits EJES C MOS input mode interrupt on falling edges fo 1 C MOS input mode interrupt on rising and falling edges Pa e Push pull output mode C MOS input mode interrupt on rising edges NOTES 1 The INT4 external interrupts at the P0 7 P0 4 pins share the same interrupt level IRQ7 and interrupt vector address E8H 2 You can assign pull up resistors to individual port O pins by making the appropriate settings to the POPUR register POPUR 7 POPUR 4 ELECTRONICS 4 19 CONTROL REGISTERS S3F80K5 UM REV1 11 POCONL Porto Control Register Low Byte E9H Seti Bank0 Reset Value 0 0 0 0 0 0 0
167. ic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously two write will occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H Set 1 Bank0 R W Bank address status flag BA Carry flag C First interrupt Zero flag 2 status flag FIS Sign flag S Half carry flag H Overflow V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET FLAG DESCRIPTIONS C FIS BA Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6
168. ic Timer and Timer 0 OVE IVIC Wits so tastes bist DET 10 1 Basics Timer BI un nende drasse bien lib 10 1 TIME 10 1 Basic Timer Control Register BTCON non nn naar cnn rca 10 2 Basic Timer Function Description cnn nn 10 3 Timer 0 Control Register TOCON aa 10 4 Timer 0 Function Description urvsnonnrrnnvvnnnrnnvnnnnnnnennnnnnnnnnnnnnnnennnnnnnennnnnnnennnnnnnnennnnnnennnnnnnnennennnennnnnnne 10 6 Chapter 11 Timer 1 OVNI ee ee Eege 11 1 Timer 1 Overflow Interrupt us di ltd 11 2 Timer 1 Capture Interrupt a a a a a a a ae A a a raa aiana Ai aaa AA aah 11 2 Timer Ee Nu e EEN 11 3 Timer 1 Control Register T71CONI non nana 11 5 Chapter 12 Counter A OVervlem ic cita 12 1 Counter A Control Register CACON cnn 12 3 Counter A Pulse Width Calculatons canaria nnnnn nono nnnnannnn cnn nono nana nancnncnnnnns 12 4 viii S3F80K5 UM REV1 11 MICROCONTROLLER Table of Contents Continued Chapter 13 Embedded Flash Memory Interface OVE scort A E A Sara aa ISP On Board Programming SECTOR A tic ISP Reset Vector and ISP Sector Gize nnt Flash Memory Control Registers User Program Mode Flash Memory Control Register FMCON oooncccnnncccnnocononccononnnononcnn nono nnnccn narrar crac cnn rn carr Flash Memory User Programming Enable Register FMUSR Flash Memory Sector Address Registers Sector Erase Programming O Hard Lock Protection Chapter 14 Low Voltage Detector Overview LVDIELAG EE Low Voltage Detector Control Register
169. ified in inverse order 0 is highest priority 1 is the next highest and so on 2 If two or more interrupts within the same level content the interrupt with the lowest vector address usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware 3 Reset Basic timer overflow or POR interrupt vector address can be changed by smart option Refer to Table 13 3 or Figure 2 2 ELECTRONICS 5 5 INTERRUPT STRUCTURE S3F80K5 UM REV1 11 ENABLE DISABLE INTERRUPT INSTRUCTIONS EI DI Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur and according to the established priorities NOTE The system initialization routine that is executed following a reset must always contain an El instruction to globally enable the interrupt structure During normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register Although you can manipulate SYM 0 directly to enable or disable interrupts we recommend that you use the El and DI instructions instead System Level Interrupt Control Registers In addition to the control registers for specific interrupt sources four system level registers control interrupt processing e The interrupt mask register IMR enables un masks or disab
170. ing Mode Register addressing mode only 7 P0 7 External Interrupt ONT Ai Enable Bit Disable interrupt Enable interrupt BE 6 P0 6 External Interrupt INT4 Enable Bit Disable interrupt o Enable interrupt 5 P0 5 External Interrupt INT4 Enable Bit Disable interrupt o Enable interrupt A P0 4 External Interrupt ONT A Enable Bit Disable interrupt 1 Enable interrupt 3 P0 3 External Interrupt INT3 Enable Bit Disable interrupt 1 Enable interrupt 2 P0 2 External Interrupt INT2 Enable Bit Disable interrupt Enable interrupt 1 P0 1 External Interrupt INT1 Enable Bit Disable interrupt Enable interrupt o 0 P0 0 External Interrupt INTO Enable Bit Disable interrupt Enable interrupt o ELECTRONICS 4 2 mb CONTROL REGISTERS S3F80K5 UM REV1 11 POPND Port 0 External Interrupt Pending Register F2H Seti Bank Reset Value 0 0 0 0 0 0 0 0 Read Write R R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P0 7 External Interrupt INT4 Pending Flag Bit See Note No P0 7 external interrupt pending when read 1 P0 7 external interrupt is pending when read 6 P0 6 External Interrupt INT4 Pending Flag Bit No P0 6 external interrupt pending when read DOG external interrupt is pending when read BS 5 PO 5 External Interrupt INT4 Pending Flag Bit No P0 5 external interrupt pending when read 1 P0 5 external interrupt is pending when read
171. it Disable pull up resistor 1 Enable pull up resistor 3 P1 o Output Mode Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 2 P1 N Output Mode Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 1 P1 Output Mode Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 0 P1 o Output Mode Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 4 26 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS P2CONL Port 2 Control Register Low Byte EDH Seti Bank0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 1 and 0 P2 0 INT5 Mode Selection Bits olo C MOS input mode interrupt on falling edges KIES C MOS input mode interrupt on rising edges and falling edges ERR Output mode push pull or open drain output refer to P2OUTMD C MOS input mode interrupt on rising edges NOTE Pull up resistors can be assigned to individual port 2 pins by making the appropriate settings to the P2PUR control register location EEH set 1 banko ELECTRONICS 4 27 CONTROL REGISTERS S3F80K5 UM REV1 11 P2INT Port 2 External Interrupt Enable Register E5H Seti Bank Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 0 4 28 Register addressing mode only P2 0 External Interrupt
172. jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes mm Leen femmen 0000 Always false 1000 T Always true 0111 1111 note Carry note No carry NO I 0110 note 1110 note Not zero 1101 Plus 0101 Minus 0100 Overflow 1100 No overflow 0110 note Equal 1110 note Not equal 1001 Greater than or equal 0001 Less than 1010 Greater than 0010 Less than or equal Zero N ll ll O O O O O S S V V Z N nol E OR V 0 OR V 1 R S XOR V 0 R S XOR V 1 NNOO x lt O O 1111 note Unsigned greater than or equal 0111 note Unsigned less than 1011 Unsigned greater than OO I o C 0 AND Z 0 1 C OR Z 1 0011 Unsigned less than or equal NOTES 1 It indicates condition codes that are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used after a CP instruction however EQ would probably be used 2 For operations i
173. l of these addressing modes are available for each instruction Register R Indirect Register IR Indexed X Direct Address DA Indirect Address IA Relative Address RA Immediate IM ELECTRONICS 3 1 ADDRESSING MODES S3F80K5 UM REV1 11 REGISTER ADDRESSING MODE R In Register addressing mode the operand is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing because it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 Program Memory Register File Bbitregister pe i EE oints to one Ee SE register in register AAA One Operand KF file Instruction Example Value used in instruction execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Points to RPO ot RP1 e Selected RP points to start of working register Po Boch Program Memory er Working Hegisiet OPCODE Points to the OPERAND A woking register Two Operand A 1 of 8 Instruction Example Sample Instruction ADD R1 R2 Where R1 and R2 are registers in the curruntly selected working register area Figure 3 2 Working Register Addressing 3 2 ELECTRONICS S3F80K5 UM REV1 11 ADDRESSING MODES INDIRECT REGIS
174. le amp Stand alone Samsung OTP MTP FLASH Programmer for After Service e Small size and Light for the portable use e Support all of SAMSUNG OTP MTP FLASH devices e HEX file download via USB port from PC e Very fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second e Internal large buffer memory 118M Bytes e Driver software run under various O S Windows 95 98 2000 XP e Full function regarding OTP MTP programmer Read Program Verify Blank Protection e Two kind of Power Supplies User system power or USB power adapter e Support Firmware upgrade SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com ELECTRONICS S3F80K5 UM REV1 11 OTP MTP PROGRAMMER WRITER Continued ELECTRICAL DATA US pro Portable Samsung OTP MTP FLASH Programmer e Portable Samsung OTP MTP FLASH Programmer e Small size and Light for the portable use e Support all of SAMSUNG OTP MTP FLASH devices e Convenient USB connection to any IBM compatible PC or Laptop computers e Operated by USB power of PC e PC based menu drive software for simple operation e Very fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second e Support Samsung standard Hex or Intel Hex format e Driver software run under various O S Windows 95 98 2000 XP e Full function regarding OTP MTP programmer Read Program Verify Blank Protection e
175. le amp Start sector erase User program mode disable ELECTRONICS S3F80K5 UM REV1 11 EMBEDDED FLASH MEMORY INTERFACE PROGRAMMING A flash memory is programmed in one byte unit after sector erase The write operation of programming starts by LDC instruction The program procedure in user program mode 1 PON OO NO Must erase target sectors before programming Set Flash Memory User Programming Enable Register FMUSR to 10100101B Set Flash Memory Control Register FMCON to 0101000XB Set Flash Memory Sector Address Register FMSECH and FMSECL to the sector base address of destination address to write data Load a transmission data into a working register Load a flash memory upper address into upper register of pair working register Load a flash memory lower address into lower register of pair working register Load transmission data to flash memory location area on LDC instruction by indirectly addressing mode Set Flash Memory User Programming Enable Register FMUSR to 00000000B NOTE In programming mode it doesn t care whether FMCON O0 s value is 0 or 1 ELECTRONICS 13 11 EMBEDDED FLASH MEMORY INTERFACE S3F80K5 UM REV1 11 Select Bank FMSECH High Address of Sector FMSECL Low Address of Sector Set Secotr Base Address R n 4 High Address to Write R n 1 lt Low Address to Write Set Address and Data R data 8 bit Data FMUSR 0A5H User Program
176. lement addition is performed Flags C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if a carry from the low order nibble occurred Format Bytes Cycles Opcode Addr Mode Hex dst src 6 03 r Ir ODC SIC dst 3 6 04 R R 05 R IR opc dst src 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H OAH ADD R1 R2 gt R1 15H R2 03H ADD R1 R2 gt R1 1CH R2 03H ADD 01H 02H gt Register 01H 24H register 02H 03H ADD 01H 02H gt Register 01H 2BH register 02H 03H ADD 01H 25H Register 01H 46H In the first example destination working register R1 contains 12H and the source working register R2 contains 03H The statement ADD R1 R2 adds 03H to 12H leaving the value 15H in register R1 ELECTRONICS 6 15 INSTRUCTION SET AND Logical AND AND Operation Flags Format Examples dst src dst lt dst AND src S3F80K5_UM_REV1 11 The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation results in a 1 bit being stored whenever the corresponding bits in the two
177. les masks interrupt levels e The interrupt priority register IPR controls the relative priorities of interrupt levels e The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source e The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register iD RW Function Description Interrupt Mask Register IMR R W Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels IRQO IRQ7 Interrupt Priority Register R W Controls the relative processing priorities of the interrupt levels The eight levels of the S3F80K5 are organized into three groups A B and C Group A is IRQO and IRQ1 group B is IRQ2 and IRQ4 and group C is IRQ5 IRQ6 and IRQ7 Interrupt Request Register This register contains a request pending bit for each interrupt level System Mode Register SYM R W A dynamic global interrupt processing enables disables fast interrupt processing and external interface control an external memory interface is not implemented in the S3F80K5 microcontroller 5 6 ELECTRONICS S3F80K5 UM REV1 11 INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways
178. lly cleared by hardware However the timer 0 match capture interrupt IRQO vector FCH must be cleared by the interrupt service routine S W 4 40 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS T1CON Timer 1 Control Register FAH Seti Bank0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 6 Timer 1 Input Clock Selection Bits leg DOE OOOO afefe o O Internal clock counter A flip flop T FF 5 and A Timer 1 Operating Mode Selection Bits fo fo Interval timer mode counter cleared by match signal Capture mode rising edges counter running OVF can occur ERR Capture mode falling edges counter running OVF can occur Capture mode rising and falling edges counter running OVF can occur 3 Timer 1 Counter Clear Bit No effect when write Clear T1 counter T1CNT when write 2 Timer 1 Overflow Interrupt Enable Bit note Lo Disable T1 overfow interupt Enable T1 overflow interrupt 1 Timer 1 Match Capture Interrupt Enable Bit Lo Disable D matchicapturinterust id Enable T1 match capture interrupt 0 Timer 1 Match Capture Interrupt Pending Flag Bit No T1 match capture interrupt pending when read Clear T1 match capture interrupt pending condition when write T1 match capture interrupt is pending when read No effect when write NOTE A timer 1 overflow interrupt pending condition is automatically cleared by hardware
179. logic controlled by IPR register settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S8C8 S3F8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware The S3F80K5 uses twelve vectors One vector addresses are shared by four interrupt sources Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow for example Each vector can have several interrupt sources In the S3F80K5 interrupt structure there are 15 possible interrupt sources When a Service routine starts the respective pending bit is either cleared automatically by hardware or is must be cleared manually by program software The characteristics of the source s pending mechanism determine which method is used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE S3F80K5 UM REV1 11 INTERRUPT TYPES The three components of the S3C8 S3F8 series interrupt structure described above levels vectors and sources are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic There are
180. m memory option for starting condition of the chip The program memory addresses used by smart option are from 003CH to 003FH The S3F80K5 only use 003EH and 003FH User can write any value in the not used addresses 003CH and 003DH The default value of smart option bits in program memory is OFFH Normal reset vector address 100H ISP protection disable Before execution the program memory code user can set the smart option bits according to the hardware option for user to want to select ROM Address 003CH Not used ROM Address 003DH Not used ROM Address 003EH ISP Reset Vector Change ME Bit M eg used ISP Protection Size 0 OBP Reset vector address Selection Bits Y 1 Normal vector address 100H 00 256 bytes 01 512 bytes ISP Reset Vector Address Selection Bits 2 10 1024 bytes 00 200H ISP Area size 256 bytes 11 2048 bytes 01 300H gt Area size 512 bytes ISP Protection Enable Disable Bit 10 500H ISP Area size 1024 bytes 0 Enable Not erasable 11 900H ISP Area size 2048 bytes 1 Disable Erasable ROM Address 003FH Not used RESET Control Bit 0 External interrupts by PO and P2 or SED amp R generate the reset signal 1 External interrupts by PO and P2 or SED amp R do not generate the reset signal Figure 13 2 Smart Option ELECTRONICS 13 3 EMBEDDED FLASH MEMORY INTERFACE S3F80K5 UM REV1 11 NOTES 1 By setting ISP Reset Vector Change Selection Bit 3EH 7 to
181. memory location 1033H ODDH LDCD R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is decremented by one R8 OCDH R6 10H R7 32H RR6 lt RR6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 32H ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET LDCI LDEI Load Memory and Increment LDCI LDEI Operation Flags Format Examples dei erc dst lt src r e TT tr These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Ir even for program memory and odd for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory locations 1033H OCDH and 1034H OC5H external data memory locations 1033H ODDH and 1034H OD5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 RR6 1 R8 OCDH R6 10H R7 34H LDEI R8 R
182. n 1st bit 3FH Mode Reset Source P i Reset Pin O Reset O Reset Watch Dog Timer Enable O Reset O Reset Normal IPOR O Reset O Reset Operating LVD O Reset O Reset External Interrupt El PO and P2 X External ISR X External ISR External Interrupt DI PO and P2 X Continue X Continue Reset Pin O Reset O Reset Watch Dog Timer Enable X STOP X STOP IPOR O STOP Release and O STOP Release and Stop Reset Reset Mode LVD X STOP X STOP External Interrupt El Enable PO X STOP Release and O STOP Release and and P2 External ISR Reset SED amp R PO X STOP Release and O STOP Release and Continue Reset P2 0 X STOP X STOP NOTES 1 X means that a corresponding reset source don t generate reset signal O means that a corresponding reset source generates reset signal Reset means that reset signal is generated and chip reset occurs Continue means that it executes the next instruction continuously without ISR execution External ISR means that chip executes the interrupt service routine of generated external interrupt source STOP means that the chip is in stop state STOP Release and External ISR means that chip executes the external interrupt service routine of generated external interrupt source after STOP released 7 STOP Release and Continue means that executes the next instruction continuously after STOP released ELECTRONICS S3F80K5 UM REV1
183. nd example destination register 01H contains the value 03H 0000001 1B and the source working register R1 the value 07H 00000111B The statement BOR 01H 2 R1 logically ORs bit two of register 01H destination with bit zero of R1 source This leaves the value 07H in register 01H ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET BTJRF pit Test Jump Relative on False BTJRF Operation Flags Format Example dst src b If src b is a 0 then PC lt PC dst The specified bit within the source operand is tested If it is a 0 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRF instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src ope dst 3 10 37 RA tb NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 O7H BTJRF SKIP R1 3 PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3 tests bit 3 Because it is 0 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET S3F80K5_UM_REV
184. newest CPU architecture The S3F80K5 is the microcontroller which has 16 Kbyte Flash Memory ROM Using a proven modular design approach Samsung engineers developed S3F80K5 by integrating the following peripheral modules with the powerful SAM8 RC core e Internal LVD circuit and 16 bit programmable pins for external interrupts e One 8 bit basic timer for oscillation stabilization and watchdog function system reset e One 8 bit Timer counter with three operating modes e Two 16 bit timer counters with selectable operating modes e One 8 bit counter with auto reload function and one shot or repeat control The S3F80K5 is a versatile general purpose microcontroller which is especially suitable for use as remote transmitter controller It is currently available in a 24 pin SOP SDIP package ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU e SAM8 RC CPU core Memory e Program memory 16 Kbyte Internal Flash Memory 10 years data retention Endurance 10 000 Erase Program cycles Byte Programmable User programmable by LDC instruction e Executable memory 256 byte RAM e Data memory 272 byte general purpose RAM Instruction Set e 78 instructions e IDLE and STOP instructions added for power down modes Instruction Execution Time e 500 ns at 8 MHz fosc minimum Interrupts e 15 interrupt sources with 12 vectors and 6 levels I O Ports e Two 8 bit I O ports P0 P1 one 1 bit P2 and 2 bit P3
185. ng the ISP enable disable bit to 0 and the reset vector selection bit to 0 at the smart option you can choose the reset vector address of CPU as shown in Table 15 3 by setting the ISP reset vector address selection bits Refer to Figure 2 2 Smart Option Table 13 2 Reset Vector Address Smart Option 003EH r Reset Vector Usable Area for ISP heset Vector Address Selection Bit Address after POR ISP Sector ISP Sector Size 100H 1FFH 256 Bytes 100H 2FFH 512 Bytes 100H 4FFH 1024 Bytes NOTE The selection of the ISP reset vector address by Smart Option 003EH 7 003EH 5 is not dependent of the selection of ISP sector size by Smart Option 003EH 2 003EH 0 ET 13 4 ELECTRONICS S3F80K5 UM REV1 11 EMBEDDED FLASH MEMORY INTERFACE FLASH MEMORY CONTROL REGISTERS USER PROGRAM MODE FLASH MEMORY CONTROL REGISTER FMCON FMCON register is available only in user program mode to select the flash memory operation mode sector erase byte programming and to make the flash memory into a hard lock protection Flash Memory Control Register FMCON EFH Gett Bank1 R W Flash Erase or Hard Lock Protection Flash Memory Mode Selection Bits i 0101 Programming mode Operation Start Bit 1010 Erase mode 0 Operation stop 0110 Hard lock mode 1 Operation start others Not used for S3F80K5 This bit will be cleared automatically just after erase operation Not used for S3F80K5 Figure
186. ng the JR statement No flags are affected Bytes Cycles Opcode Addr Mode 1 Hex dst dst 2 6 ccB RA cc 0toF NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits Given The carry flag 1 and LABEL_X 1FF7H JR GLABEL X gt PC 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL X will pass control to the statement whose address is now in the PC Otherwise the program instruction following the JR would be executed ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET LD Load LD dei erc Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src dst opc src 2 4 rC r IM r8 r R r OtoF D7 Ir r src dst 3 6 E4 R R E5 R IR dst src 3 6 E6 R M D6 IR IM opc src dst 3 6 F5 IR R os 6 e o ox op 8 e ox ELECTRONICS 6 49 INSTRUCTION SET LD Load LD Continued S3F80K5_UM_REV1 11 Examples Given RO 01H R1 OAH register OOH 01H register 01H 20H register 02H 02H LOOP 30H and register 3AH OFFH LD RO 10H LD R0 01H LD 01H RO LD R1 RO LD RO R1 LD 00H 01H LD 02H 000H LD 00H 0AH LD 00H 10H LD 00H 02H gt gt gt Lis gt 5 gt LD RO LOOP R1 gt LD LOOP RO R1 gt RO 10H RO
187. nvolving unsigned numbers the special condition codes UGE ULT UGT and ULE must be used 6 12 ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set Information is arranged in a consistent format for improved readability and for fast referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS 6 13 INSTRUCTION SET S3F80K5_UM_REV1 11 ADC Add with carry ADC Operation Flags Format Examples dst src dst lt dst src c The source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction permits the carry from the addition of low order operands to be carried into the addition of high order operands C Se
188. o 0 smart option 03FH and chip is in stop mode if external interrupt is enabled external interrupts by PO and P2 0 generate the reset signal STOP Error Detection amp Recovery SED amp R When RESET Control Bit is set to 0 smart option bit 7 03FH and MCU is in stop or abnormal state the falling edge input of PO generates the reset signal regardless of external interrupt enable or disable ELECTRONICS 8 1 RESET S3F80K5 UM REV1 11 Watchdog Timer P0 amp P2 0 F D gt INTO INT5 El external interrupt enable RESET Contorl Bit 1 STOP po a RESET Contorl Bit 1 RESET Control Bit smart option bit 0 03FH STOP Figure 8 1 RESET Sources of The S3F80K5 The rising edge detection of LVD circuit while rising of VDD passes the level of VLVD When POR circuit detects VDD below VPOR reset is generated by internal power on reset Basic Timer over flow for watchdog timer See the chapter 11 Basic Timer and Timer 0 for more understanding When RESET Control Bit smart option 03FH is set to 0 and chip is in stop mode external interrupt input by PO and P2 0 generates the reset signal When RESET Control Bit smart option 03FH are set to 0 and chip is in stop mode or abnormal state the falling edge input of PO generates the reset signal regardless of external interrupt enable disable ELECTRONICS S3F80K5 UM REV1 11 Enable Falling Edge STOP gt Disabl
189. o that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H RO C 0 H 0 Bits 4 7 3 bits 0 3 1 DA op ORI 31 0 leave the value 31 BCD in address 27H OR1 ELECTRONICS S3F80K5 UM REV1 11 DEC Decrement DEC Operation Flags Format Examples dst dst lt dst 1 The contents of the destination operand are decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Hex opc dst 2 4 00 01 Given R1 03H and register 03H 10H DEG Ri gt R1 02H DEG R1 gt Register 039H OFH INSTRUCTION SET Addr Mode dst R IR In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value 10H contained in the destination register 03H by one leaving the value OFH ELECTRONICS 6 35 INSTRUCTION SET S3F80K5_UM_REV1 11 DECW Decrement Word DECW Operation Flags Format Examples NOTE dst dst lt dst 1 The contents of the destination location which must be an even address and the operand following that location are treate
190. ocessing you write the appropriate 3 bit value to SYM 4 SYM 2 Then to enable fast interrupt processing for the selected level you set SYM 1 to 1 5 16 ELECTRONICS S3F80K5 UM REV1 11 INTERRUPT STRUCTURE FAST INTERRUPT PROCESSING Continued Two other system registers support fast interrupt processing e The instruction pointer IP contains the starting address of the service routine and is later used to swap the program counter values and e When a fast interrupt occurs the contents of the FLAGS register are stored in an unmapped dedicated register called FLAGS FLAGS prime NOTE For the S3F80K5 microcontroller the service routine for any one of the eight interrupt levels IRQO0 IRQ7 can be selected for fast interrupt processing Procedure for Initiating Fast Interrupt To initiate fast interrupt processing follow these steps 1 Load the start address of the service routine into the instruction pointer IP 2 Load the interrupt level number IRQn into the fast interrupt selection field SYM 4 SYM 2 3 Write a 1 to the fast interrupt enable bit in the SYM register Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processing the following events occur The contents of the instruction pointer and the PC are swapped The FLAG register values are written to the FLAGS FLAGS prime register The fast interrupt status bit in the FLAGS register is set
191. omplement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Next OPCODE Program Memory Address Used Current PC Value zb ng A Current Instruction OPCODE Signed Displacement Value Displacement Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELECTRONICS 3 13 ADDRESSING MODES S3F80K5 UM REV1 11 IMMEDIATE MODE IM In Immediate IM mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The operand value is in the instruction Sample Instruction LD RO0 0AAH Figure 3 14 Immediate Addressing 3 14 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS CONTROL REGISTERS OVERVIEW In this section d
192. ounter The stack pointer then pops the value in location OOFEH 1AH into the PC s low byte and the instruction at location 101 AH is executed The stack pointer now points to memory location OOFEH ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET RL Rotate Left RL Operation dst C lt dst 7 dst 0 lt dst 7 dst n 1 lt dst n n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag Flags Format Examples C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 90 R 4 91 IR Given Register 00H OAAH register 01H 02H and register 02H 17H RL 00H gt Register 00H 55H 1 RL 01H gt Register 01H 02H register 02H 2EH C 0 In the first example if general register OOH contains the value OAAH 10101010B the statement RL OOH rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and overflow flags ELECTRONICS 6 71 INSTRUCTION SET S3F80K5_UM_REV1 11 RLC Rotate Left Through Carry RLC Operation dst dst 0
193. pcode Addr Mode Hex dst src B2 r r B3 r Ir B4 H H B5 R IR B6 R IM Given RO 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H XOR RO R1 gt XOR RO OR1 gt XOR 00H 01H gt XOR 00H 01H gt XOR 00H 54H gt RO 0C5H R1 02H RO Register 00H 29H register 01H Register 00H 08H register 01H Register 00H 7FH 0E4H R1 02H register 02H 23H 02H 02H register 02H 23H In the first example if working register RO contains the value OC7H and if register R1 contains the value 02H the statement XOR RO R1 logically exclusive ORs the R1 value with the RO value and stores the result 0C5H in the destination register RO ELECTRONICS 6 87 S3F80K5 UM REV1 11 CLOCK AND POWER CIRCUITS CLOCK AND POWER CIRCUITS OVERVIEW The clock frequency for the S3F80K5 can be generated by an external crystal or supplied by an external clock source The clock frequency for the S3F80K5 can range from 1MHz to 8 MHz The maximum CPU clock frequency as determined by CLKCON register is 8 MHz The X y and Zum pins connect the external oscillator or clock source to the on chip clock circuit Typically application systems have a resister and two separate capacitors across the power pins in order to suppress high frequency noise and provide bulk charge storage for the overall system SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External
194. pes 24 pin SOP 24 pin SDIP ELECTRONICS S3F80K5 UM REV1 11 PRODUCT OVERVIEW BLOCK DIAGRAM 24 PIN PACKAGE P0 0 INTO SDAT PO 1 INT1 SCLK P0 2 0 3 INT2 INT3 P0 4 P0 7 INT4 P1 0 1 7 BINDE TT I O Port and Interrupt Control SAM8RC CPU P3 0 TOPWM TOCAP T1CAP Ez gt P3 1 REM TOCK FLASH 16KB A 272 byte Executable RAM Register File 256 byte Memory 16 Bit Counter Timer1 A Counter Figure 1 1 Block Diagram 24 pin Counter ELECTRONICS 1 3 PRODUCT OVERVIEW S3F80K5 UM REV1 11 PIN ASSIGNMENTS O VDD P2 0 INT5 Xout P3 1 REM TOCK TEST P3 0 TOPWM TOCAP T1CAP SDAT P0 0 INTO S3C80K5 P1 7 SCLK P0 1 INT1 P1 6 nRESET P0 2 INT2 24 SOP SDIP P1 5 PO 3 INT3 TOP VIEW P1 4 PO 4 INT4 P1 3 PO 5 INT4 P1 2 PO 6 INT4 P1 1 PO 7 INT4 P1 0 Figure 1 2 Pin Assignment Diagram 24 Pin SOP SDIP Package 1 4 ELECTRONICS S3F80K5 UM REV1 11 PRODUCT OVERVIEW Table 1 1 Pin Descriptions of 24 SOP SDIP Pin Pin Description Circuit 28 Pin Shared Type W No Functions P0 0 P0 7 UO I O port with bit programmable pins Configurable Ext INT to input or push pull output mode Pull up resistors INTO INT3 are assignable by software Pins can be assigned INT4 individually as external interrupt inputs with noise SDAT filters interrupt enable disable and interrupt SCLK pending control SED amp R note circuit built in PO for STOP releasing In the tool mode P0 0 and PO0 1 are assigned as
195. ple if working register RO contains the value 15H and register R1 the value 2AH the statement OR RO R1 logical ORs the RO and R1 register contents and stores the result 3FH in destination register RO The other examples show the use of the logical OR instruction with the various addressing modes and formats ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET POP Pop From Stack POP Operation Flags Format Examples dst dst SP SP lt SP 1 The contents of the location addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one No flags affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 50 R 51 IR Given Register OOH 01H register 01H 1BH SPH OD8H OOH SPL OD9H OFBH and stack register OFBH 55H POP 00H gt Register 00H 55H SP OOFCH POP 00H gt Register 00H 01H register 01H 55H SP 00FCH In the first example general register OOH contains the value 01H The statement POP 00H loads the contents of location OOFBH 55H into destination register OOH and then increments the stack pointer by one Register 00H then contains the value 55H and the SP points to location OOFCH ELECTRONICS 6 63 INSTRUCTION SET S3F80K5_UM_REV1 11 POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example dst src dst lt src IR IR 1 This instruction is used for user defined sta
196. propriate control and clock settings before entering Stop mode If you use an interrupt to release Stop mode the bit pair setting for CLKCON 4 CLKCON 3 remains unchanged and the currently selected clock value is used 8 12 ELECTRONICS S3F80K5 UM REV1 11 RESET SED amp R Stop Error Detect and Recovery The Stop Error Detect amp Recovery circuit is used to release stop mode and prevent abnormal stop mode that can be occurred by battery bouncing It executes two functions in related to the internal logic of PO One is releasing from stop status by switching the level of input port PO and the other is keeping the chip from entering stop mode when the chip is in abnormal status Releasing from stop mode When RESET Control Bit is set to 0 smart option 03FH if falling edge input signal enters in through Port0 S3F80K5 is released from stop mode and generates reset signal On the other hand when RESET Control Bit is set to 1 smart option 03FH S3F80K5 is only released stop mode reset doesn t occur When the falling edge of a pin on Port0 is entered the chip is released from stop mode even though external interrupt is disabled Keeping the chip from entering abnormal stop mode This circuit detects the abnormal status by checking the port PO status If the chip is in abnormal status it keeps from entering stop mode NOTE In case of P2 0 SED amp R circuit isn t implemented So although 1pins P
197. pts P2 3 P2 0 Not pending o Pending 3 Lev o I 3 IRQ3 Request Pending Bit Timer 2 Match Capture or Overflow Not pending o Pending 2 Lev o 2 IRQ2 Request Pending Bit Counter A Interrupt Not pending Pending o 1 Lev bd I 1 IRQ1 Request Pending Bit Timer 1 Match Capture or Overflow ot pending ending 0 Lev o I 0 IRQO Request Pending Bit Timer 0 Match Capture or Overflow Not pending o Pending 4 16 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS LVDCON Lvp Control Register EOH Seti Bank1 Reset Value 0 Read Write R W Addressing Mode Register addressing mode only 7 1 Not used for S3F80K5 0 LVD Flag Indicator Bit DN Von gt LVD FLAG Level Vpp lt LVD FLAG Level NOTE When LVD detects LVD FLAG level LVDCONOO flag bit is set automatically When VDD is upper LVD FLAG level LVDCONOO flag bit is cleared automatically ELECTRONICS 4 17 CONTROL REGISTERS S3F80K5 UM REV1 11 LVDSEL vD Flag Level Selection Register F1H Seti Bank Reset Value 0 0 Read Write R W R W Addressing Mode Register addressing mode only 7 and 6 LVD Flag Level Selection Bits Lo o ivo naiss 19 OOO DOC i 1 LVD FLAG Level 2 10V LVD FLAG Level 2 20V 5 0 Not used for S3F80K5 4 18 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS POCONH Port 0 Control Register High Byte E8H Set
198. r address registers for the erase or programming flash memory The FMSECL Flash Memory Sector Address Register Low Byte indicates the low byte of sector address and FMSECH Flash Memory Address Sector Register High Byte indicates the high byte of sector address One sector consists of 128 bytes Each sector s address starts XXOOH or XX80H that is a base address of sector is XXOOH or XX80H So bit 6 0 of FMSECL don t mean whether the value is 1 or 0 We recommend that it is the simplest way to load the sector base address into FMSECH and FMSECL register When programming the flash memory user should program after loading a sector base address which is located in the destination address to write data into FMSECH and FMSECL register If the next operation is also to write one byte data user should check whether next destination address is located in the same sector or not In case of other sectors user should load sector address to FMSECH and FMSECL Register according to the sector Refer to page 15 16 PROGRAMMING TIP Programming Flash Memory Sector Address Register FMSECH ECH Set1 Bank 1 R W Flash Memory Sector Address High Byte NOTE The High Byte flash memory sector address pointer value is the higher eight bits of the 16 bit pointer address Figure 13 5 Flash Memory Sector Address Register FMSECH Flash Memory Sector Address Register FMSECL EDH Set1 Bank 1 R W Don t Care Flash Memory Sector
199. ram 11 4 ELECTRONICS S3F80K5 UM REV1 11 TIMER 1 TIMER 1 CONTROL REGISTER T1CON The Timer 1 control register T1CON is located in Set 1 FAH BankO and is read write addressable T1CON contains control settings for the following T1 functions Timer 1 input clock selection Timer 1 operating mode selection Timer 1 16 bit down counter clear Timer 1 overflow interrupt enable disable Timer 1 match or capture interrupt enable disable Timer 1 interrupt pending control read for status write to clear A reset operation clears T1CON to OOH selecting fosc divided by 4 as the T1 clock configuring Timer 1 as a normal interval Timer and disabling the Timer 1 interrupts Timer 1 Control Register T1CON FAH Set 1 Bank 0 R W Timer 1 Input Clock Selection Bits 00 fosc 4 01 fosc 8 10 fosc 16 11 Internal clock T F F Timer 1 Operating Mode Selection Bits 00 Interval mode 01 Capture mode capture on rising edge counter running OVF can occur 10 Capture mode capture on falling edge counter running OVF can occur 11 Capture mode capture on rising and falling edge counter running OVF can occur Timer 1 Interrupt Pending Bit 0 No interrupt pending 0 Clear pending bit when write 1 Interrupt is pending Timer 1 Interrupt Match capture Enable Bit 0 Disable interrupt 1 Enable interrupt Timer 1 Overflow Interrupt Enable Bit 0 Disable overflow inter
200. ription Format 4 4 D S3F80K5 UM REV1 11 MICROCONTROLLER List of Figures Continued Figure Title Page Number Number 5 1 S3C8 S3F8 Series Interrupt Types ceeccececeeeeeeeeeeeeeeceeeeseaeeeeeeeseeeeeesaeeeeeeseeeees 5 2 5 2 S3F80K5 Interrupt Structure ii iiaeiai aaeei nn cnc 5 3 5 3 ROM Vector Address Area 5 4 5 4 Interrupt Function Diagram EE 5 7 5 5 System Mode Register GYM 5 9 5 6 Interrupt Mask Register MP 5 10 5 7 Interrupt Request Priority Groups 0ocooccoconncccnncconocccnnonnnanaccnarcc ronca cnn carr 5 11 5 8 Interrupt Priority Register IPR ree irete ake EERE S KEE EAEE EREA RATINI RENNES 5 12 5 9 Interrupt Request Register PRO 5 13 6 1 System Flags Register EL AG 6 6 7 1 Main Oscillator Circuit External Crystal or Ceramic Resonator s s s 7 2 7 2 External Glock Ee DEE 7 2 7 3 System Clock Circuit Diagram naar aii ieie daa aaa taadi ani iia 7 3 7 4 System Clock Control Register CLKCON nn nanaccnnncnnns 7 4 7 5 Power Circuit VDD siria deals 7 5 7 6 Guide Line of Chip Operating Voltage ocooocccinncnconnccnncccnnonnonacnnnncc narnia nana nann cnn 7 5 8 1 RESET Sources of The G32EoOkb nn 8 2 8 2 RESET Block Diagram of The S3F80K5 mrnrrrrnrrnnnnvnnnnnvnrorrnnnnrrnnnnrnnerrensnsrrnennnnnenren 8 3 8 3 RESET Block Diagram by LVD for The S3F80K5 in Stop Mode n 8 4 8 4 Timing Diagram for Internal Power On Reset Circunt 8 5 8 5 Reset Timing Diagram for The S3F80K5 in STOP mode by IPDOR 8 6
201. rogram counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 3 12 D2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 03H and register 03H 04H CPIJNER1 R2 SKIP gt R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value 03H and general register 03 the value 04H The statement CPIJNE R1 ER2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET DA Decimal Adjust DA Operation Instruction ADD ADC SUB SBC Flags Format dst dst lt DA dst The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates
202. rogram memory the second set of values used in formats 9 and 10 are used to address data memory ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET LDC LDE Load Memory LDC LDE Continued Examples Given RO 11H R1 34H R2 01H R3 04H Program memory locations 0103H 4FH 0104H 1A 0105H 6DH and 1104H 88H External data memory locations 0103H 5FH 0104H 2AH 0105H 7DH and 1104H 98H LDC RO RR2 RO lt contents of program memory location 0104H RO 1AH R2 01H R3 04H LDE RO RR2 RO lt contents of external data memory location 0104H RO 2AH R2 01H R3 04H LDC note RR2 RO 11H contents of RO is loaded into program memory location 0104H RR2 working registers RO R2 R3 gt no change LDE RR2 RO 11H contents of RO is loaded into external data memory location 0104H RR2 working registers RO R2 R3 gt no change LDC RO 401H RR2 RO lt contents of program memory location 0105H 01H RR2 RO 6DH R2 01H R3 04H LDE RO 01H RR2 RO lt contents of external data memory location 0105H 3 01H RR2 RO 7DH R2 01H R3 04H LDC note 01H RR2 RO 11H contents of RO is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 RO 11H contents of RO is loaded into external data memory location 0105H 01H 0104H LDC RO 1000H RR2 RO lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H
203. rogramming model instruction set and interrupt structure It has six chapters Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to S3F80K5 with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack operations Chapter 3 Addressing Modes contains detailed descriptions of the addressing modes that are supported by the S3C8 series CPU Chapter 4 Control Registers contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the S3F80K5 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3F8 series microcontrollers
204. rrrnrannrnnorrvnnnrrvnnnrnnnnvnnnrnr 5 8 6 1 Instruction Group Summary cocicccnnccononicn conan coronan carr rr 6 2 6 2 Flag Notation Conventions ooooncccccccccnnoniconoccnoncccnnnnnnnn ocn nnnc cc nn anar rra 6 8 6 3 Instruction Set ul EE 6 8 6 4 Instruction Notation Conventions occocnnccnnnccnnccnnonannn cana noc n rra 6 9 6 5 Opcode Quick Reference ccoococcccccococcnonococononononononononconnnconnnnnanannnn ccoo nn ncanrnnnnnnnnnnn nacos 6 10 6 6 elle ge IB EEN 6 12 7 1 Falling and Rising Time of Operating Voltage 7 5 8 1 Reset Condition in STOP Mode ooococococcconociconcccnonccnnon nn nono co ronca narrar nn 8 7 8 2 Set 1 Bank 0 Register Values After Reset no ncnnnannncnnnnnos 8 15 8 3 Set 1 Bank 1 Register Values After Reset rrrnrnrrrrnnvrrrrrnnrrrrrrrnnrrrrrrnnvnrrrrnnrrrrrrrnnnnn 8 17 8 4 Reset Generation According to the Condition of Smart Option uanrrnrrrrrrnnrrnnnnvnnrr 8 18 8 5 Guideline for Unused Pins to Reduced Power Consumption rnannvvnrnrvvnnnrrnnnnrnnrenr 8 19 8 6 Summary of Each Mode ooooconcccccoccconocccconccononcnnnnncnn no cn nan cc cnn n nana nn nr rn rra 8 20 9 1 S3F80K5 Port Configuration Overview 28 GCOP 9 2 9 2 Port Data Register Summary conccccccccnonoconocinonaccncornnn rca cc 9 3 S3F80K5 UM REV1 11 MICROCONTROLLER xiii List of Tables Continued Table Title Page Number Number 13 1 Le ee 13 4 13 2 Reset Vector eeler 13 4 15 1 Absolute Maximuin HE ue ET 15 2 15 2 D C Electric
205. rt 2 External Interrupt Pending Register AA 4 30 P2PUR Port 2 Pull up Resistor Enable Hegieter nn cnn 4 31 P3CON Port 3 Control Heglster nana nn nc cnc rn 4 32 P3OUTPU Port 3 Output Pull up Resistor Enable Hegister 4 34 PP Register Page Pointer erren an rK E e EEEE EaR ROE cnn 4 35 RESETID Reset Source Indicating Hegtsier AA 4 36 RPO Register Eopter H eege ege o A Vises to A 4 37 RP1 Register Konter zeien ees a a a a a iere eet 4 37 SPL Stack Pointer Low Dvtei nt 4 38 STOPCON Stop Control Hegeter ia ssis assii a iiaii a adai a i ai 4 38 SYM System Mode Hegoieter AAA 4 39 T1CON Timer 1 Control Register AAA 4 41 S3F80K5 UM REV1 11 MICROCONTROLLER xvii List of Instruction Descriptions Instruction Full Register Name Page Mnemonic Number ADC Add with CAM E 6 14 ADD Add 6 15 AND A EE 6 16 BAND A de eee d 6 17 BCP EISE eu 6 18 BITC EIN EE 6 19 BITR BERGEN 6 20 BITS EEE E E AET A A TN 6 21 BOR BEFORE 6 22 BTJRF Bit Test Jump Relative on Fale 6 23 BTJRT Bit Test Jump Relative ON Tue 6 24 BXOR BILXOR ee ebe eege te A nda ll 6 25 CALL Ree 6 26 CCF Complement Carry Flag mico tied oie ddmd aaf dead 6 27 CLR Gears 6 28 COM Complicado 6 29 CP ele 6 30 CPIJE Compare Increment and Jump on Foul 6 31 CPIJNE Compare Increment and Jump on Non Fous 6 32 DA Decimal AdjUS Etre sitet ERAR ER EREE En ARS leia 6 33 DA BET EEE EEE EE 6 34 DEC DEGreMENt undra EE biene bd 6 35 DECW Decrement WOI DEE 6 36 DI Disable ue 6 37 DIV Divide UN
206. rupt 1 Enable overflow interrupt Timer 1 Counter Clear Bit 0 No effect 1 Clear the timer 0 counter when write Figure 11 4 Timer 1 Control Register T1CON ELECTRONICS TIMER 1 S3F80K5 UM REV1 11 Timer1 Counter High byte Register T1CNTH F6H Set 1 Bank 0 R sa 7 6 5 4 3 2 1 0 LSB Reset Value 00H Timer 1 Counter Low byte Register T1CNTL F7H Set 1 Bank 0 R Reset Value 00H Timer 1 Data High byte Register T1DATAH F8H Set 1 Bank 0 R W Reset Value FFH Timer 1 Data Low byte Register T1DATAL F9H Set 1 Bank 0 R W Reset Value FFH Figure 11 5 Timer 1 Registers T1CNTH T1CNTL T1DATAH T1DATAL 11 6 ELECTRONICS S3F80K5 UM REV1 11 COUNTER A COUNTER A OVERVIEW The S3F80K5 microcontroller has one 8 bit counter called counter A Counter A which can be used to generate the carrier frequency has the following components See Figure 12 1 Counter A control register CACON 8 bit down counter with auto reload function Two 8 bit reference data registers CADATAH and CADATAL Counter A has two functions Asa normal interval timer generating a counter A interrupt IRQ2 vector ECH at programmed time intervals To supply a clock source to the 16 bit timer counter module Timer 1 for generating the Timer 1 overflow interrupt NOTE The CPU clock should be faster than count A clock ELECTRONICS 12 1 COUNTER A S3F80K5 U
207. rupt with an RC delay noise filter for the S3F80K5 INTO 9 is fixed to release stop mode and wake up the main oscillator 2 Because the S3F80K5 has no subsystem clock the 3 bit CLKCON signature code CLKCON 2 CLKCON 0 is no meaning Figure 7 3 System Clock Circuit Diagram ELECTRONICS 7 3 CLOCK AND POWER CIRCUITS S3F80K5 UM REV1 10 SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON is located in address D4H Set1 Banko It is read write addressable and has the following functions Oscillator frequency divide by value The CLKCON 7 5 and CLKCON 2 0 Bit are not used in S3F80K5 After a reset the main oscillator is activated and the fosc 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed to fosc fosc 2 foscis or fosc te System Clock Control Register CLKCON D4H Set 1 Bank 0 R W Not used Divide by selection bits for CPU clock frequency 00 fosc 16 01 fosc 8 10 fosc 2 11 fosc non divided Figure 7 4 System Clock Control Register CLKCON 7 4 ELECTRONICS S3F80K5 UM REV1 11 CLOCK AND POWER CIRCUITS Figure 7 5 Power circuit VDD Typically application systems have a resister and two separate capacitors across the power pins R1 and C1 located as near to the MCU power pins as practical to suppress high frequency noise C2 should be a bulk electrolytic capacitor to provide bulk
208. rupts are not typically used in PWM type applications Instead the pulse at the TOPWM pin is held to low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to high level for as long as the data value is greater than gt the counter value One pulse width is equal to to k x 256 See Figure 10 5 IRQO TOINT TOPNT 0 Interrupt Enable Disable TOCON 1 Interrupt Enable Disable TOCON 2 overflow 8 bit Counter aa Pending gt IRQO TOOVF TOCNT TOPNT 0 8 bit Comparator P3 0 TOPWM High level when data gt counter Low level when data lt counter TOCON 5 TOCON 4 Buffer Register Match Signal TOCON 3 TOOVF Timer0 Data Register TODATA Figure 10 5 Simplified Timer 0 Function Diagram PWM Mode ELECTRONICS 10 7 BASIC TIMER and TIMER 0 S3F80K5 UM REV1 11 Capture Mode In capture mode a signal edge that is detected at the TOCAP pin opens a gate and loads the current counter value into the TO data register You can select rising or falling edges to trigger this operation Timer 0 also gives you capture input source the signal edge at the TOCAP pin You select the capture input by setting the value of the timer 0 capture input selection bit in the port 3 control register P3CON 2 set 1 bank 0 EFH When P3CON 2 is 1 the TOCAP input is selected When P3CON 2 is set to 0 normal I O port P3 0 is selected
209. ry in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics objectives Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24
210. sh memory in this mode several control registers will be used There are four kind functions in user program mode programming reading sector erase and one protection mode Hard lock protection ISPTM ON BOARD PROGRAMMING SECTOR ISP sectors located in program memory area can store On Board Program Software Boot program code for upgrading application code by interfacing with I O port pin The ISPTM sectors can t be erased or programmed by LDC instruction for the safety of On Board Program Software The ISP sectors are available only when the ISP enable disable bit is set 0 that is enable ISP at the Smart Option If you don t like to use ISP sector this area can be used as a normal program memory can be erased or programmed by LDC instruction by setting ISP disable bit 1 at the Smart Option Even if ISP sector is selected ISP sector can be erased or programmed in the tool program mode by serial programming tools The size of ISP sector can be varied by settings of smart option Refer to Figure 2 2 and Table 15 2 You can choose appropriate ISP sector size according to the size of On Board Program Software Decimal 65 536 256 byte Internal RAM Internal Program S3F80K5 16Kbyte Memory O1FFH 02FFH 04FFH or 08FFH OFFH 03FH 03CH Figure 13 1 Program Memory Address Space 13 2 ELECTRONICS S3F80K5 UM REV1 11 EMBEDDED FLASH MEMORY INTERFACE SMART OPTION Smart option is the progra
211. should be set 3 3V for the target board operation If the power supply from Emulator is set to 5V you should activate 3 3V regulator on the TB80KB by setting the related jumpers see Table 18 2 2 The symbol 4 marks start point of jumper signals ELECTRONICS 18 3 S3F80K5 UM REV1 11 DEVELOPMENT TOOLS Table 18 1 Components of TB80KB Symbols Usage Description JIA 100 pin connector Connection between emulator and TB80KB target board J2 50 pin connector Connection between target board and user application system RESET Push button Generation low active reset signal to S3F80K5 EVA chip VCC GND S1 POWER connector External power connector for TB80KB IDLE STOP LED STOP IDLE Display Indicate the status of STOP or IDLE of S3F80K5 EVA chip on TB80K4 target board J3 Flash Serial programming Signal points for programming Flash Rom by external programmer Don t use this one in user mode JP1 JP2 MODE Selection Selection of Flash tool user mode and Eva Main chip mode ELECTRONICS S3F80K5 UM REV1 11 ELECTRICAL DATA Table 18 2 Setting of the Jumper in TB80KB JP Description 1 2 Connection 2 3 Connection Default Setting S1 Target board power source Emulator Power User power Join 1 2 JP1 Target board mode selection H Main Mode L EVA Mode Join 2 3 JP2 Operation Mode H User Mode L Test Mode Join 1 2 JP3 MDS version SMDS
212. ssable register pages Page addressing is controlled by the register page pointer PP DFH Set 1 Bank0 In the S3F80K5 microcontroller a paged register file expansion is not implemented and the register page pointer settings therefore always point to page 0 Following a reset the page pointer s source value lower nibble and destination value upper nibble are always 0000 automatically Therefore S3F80K5 is always selected page 0 as the source and destination page for register addressing These page pointer PP register settings as shown in Figure 2 4 should not be modified during normal operation Register Page Pointer PP DFH Get 1 Bank0 R W Destination Register Page Seleciton Bits Source Register Page Selection Bits 0000 Destination page 0 0000 Source page 0 NOTE A hardware reset operation writes the 4 bit destination and source values shown above to the register page pointer These values should not be modified to address other pages Figure 2 4 Register Page Pointer PP ELECTRONICS 2 7 ADDRESS SPACE S3F80K5 UM REV1 11 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file locations COH FFH The upper 32 byte area of this 64 byte space EOH FFH is divided into two 32 byte register banks bank 0 and bank 1 The set register bank instructions SBO or SB1 are used to address one bank or the other In the S3F80K5 microcontroller bank 1 is implemented The set register bank instru
213. ssing Mode Register addressing mode only 7 and 6 Package Selection and Alternative Function Select Bits 24 pin package P3 0 TOPWM TOCAP T1CAP P3 1 REM TOCK Not used for S3F80K5 5 P3 1 Function Selection Bit o Normal UO selection Alternative function enable REM TOCK 4 and 3 P3 1 Mode Selection Bits Lo Jo Semmtrtiggr inmo oo o i open ara output mode SSCS PEO Push put opt mode Pr Sehmit tiger input wih pulp ressor 2 Function Selection Bit for P3 0 o Normal UO selection Alternative function enable P3 0 TOPWM TOCAP T1CAP 1 and 0 P3 0 Mode Selection Bits 0 Schmittriggerinputmode 1 Open drain outputmode HEN ENES Push pull output mode 1 1 Schmitt trigger input with pull up resistor 4 32 ELECTRONICS S3F80K5 UM REV1 11 CONTROL REGISTERS NOTES 1 The port 3 data register P3 at location E3H sett bank0 contains seven bit values which correspond to the following Port 3 pin functions bit 6 is not used for the S3F80K5 a Port3 bit 7 carrier signal on 1 or off 0 b Port3 bit 1 0 P3 1 REM TOCK pin bit 0 P3 0 TOPWM TOCAP T1CAP pin 2 The alternative function enable disable are enabled in accordance with function selection bit bit5 and bit2 3 Following Table is the specific example about the alternative function and pin assignment according to the each bit control of P3CON in 24 pin package Table 4 3 Each Function Description and Pin Assignment o
214. st src Load program memory with pre decrement LDEPI dst src Load external data memory with pre increment LDCPI dst src Load program memory with pre increment LDW dst src Load word POP dst Pop from stack POPUD dst src Pop user stack decrementing POPUI dst src Pop user stack incrementing PUSH Src Push to stack PUSHUD dst src Push user stack decrementing PUSHUI dst src Push user stack incrementing 6 2 ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP det erc Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dei erc Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONICS 6 3 INSTRUCTION SET S3F80K5_UM_REV1 11 Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit
215. st is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt machine cycle that completes the following processing sequence PON gt Reset clear to 0 the interrupt enable bit in the SYM register SYM 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags and sets SYM 0 to 1 allowing the CPU to process the next interrupt request ELECTRONICS 5 15 INTERRUPT STRUCTURE S3F80K5 UM REV1 11 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM except smart option ROM Cell 003CH 003DH 003EH and 003FH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location o 0 e p en Branch to the service routine specified by the concatenated 16 bit vector address NOTE A 16 bit vec
216. ster File ELECTRONICS 3 7 ADDRESSING MODES S3F80K5 UM REV1 11 INDEXED ADDRESSING MODE Continued Register File MSB Points to RPO or RP1 RPO or RP1 Selected RP points to start of working register block Program Memory OFFSET NEXT 2 BITS 4 bit Working T gt Register Register Address Point to Working Pair OPCODE Register Pair 16 Bit address added to Program Memory offset or Data Memory OPERAND Value used in pe Sample Instructions LDC R4 404H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 404H RR2 Identical operation to LDC example except that external data memory is accessed LDE command is not available because an external interface is not implemented for the S3F80K5 Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 ELECTRONICS S3F80K5 UM REV1 11 ADDRESSING MODES INDEXED ADDRESSING MODE Continued Register File MSB Points to RPO or RP1 RPO or RP1 e4 Selected RP points to start of working OFFSET register block JG OFFSET NEXT 2 BITS bit Working Register Register Address Point to Working Pair OPEODE Register Pair 16 Bit address added to Program Memory offset LSB Selects or Data Memory Program Memory OPERAND Value used in pr deene Sample Instructions LDC R4 41000H RR2 The values in the program address RR2 1000H
217. ster system register are register are initialized as list of initialized as list of Table 8 2 Table 8 2 Releasing e The rising edge of LVD e After passing an oscillation e External interrupt or reset Condition circuit is generated warm up time e SED A R Circuit Others e There is no current e There can be input leakage e It depends on control consumption in chip current in chip program 8 20 ELECTRONICS S3F80K5 UM REV1 11 I O PORTS I O PORTS OVERVIEW The S3F80K5 microcontroller has two kinds of package and different I O number relating to the package type 24 SOP package has three bit programmable I O ports PO P1 P2 P3 Two ports PO and P1 are 8 bit ports and P2 is a 1 bit port and P3 is a 2 bit port This gives a total of 19 I O pins Each port is bit programmable and can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special I O instructions are required For IR applications port0 porti are usually configured to the keyboard matrix port2 is normal UO pin and port 3 is used to IR drive pins Table 9 1 9 2 and 9 3 give you a general overview of S3F80K5 I O port functions ELECTRONICS 9 1 I O PORTS S3F80K5 UM REV1 11 Table 9 1 S3F80K5 Port Configuration Overview 24 SOP Port Configuration Options Port 0 8 bit general purpose I O port Input or push pull output external interrupt input on falling edges rising
218. t if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst src 6 13 r Ir opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Given R1 10H R2 03H C flag 1 register 01H 20H register 02H 03H and register 03H OAH ADC R1 R2 gt R1 14H R2 03H ADC R1 R2 gt R1 1BH R2 03H ADC 01H 002H gt Register 01H 24H register 02H 03H ADC 01H 02H gt Register 01H 2BH register 02H 03H ADC 01H 11H gt Register 01H 32H In the first example destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value 03H The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in register R1 ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET ADD aaa ADD dei erc Operation dst lt dst src The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s comp
219. t request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed 5 2 ELECTRONICS S3F80K5 UM REV1 11 Levels 6 Vectors 12 RESET 100H F6H F4H IRQ1 IRQ2 ECH 7 FCH FAH Sources 15 Basic timer overflow Timer 0 match capture Timer 0 overflow Timer 1 match capture Timer 1 overflow Counter A P2 0 external interrupt P0 3 external interrupt P0 2 external interrupt P0 1 external interrupt P0 0 external interrupt PO 7 external interrupt P0 6 external interrupt PO 5 external interrupt P0 4 external interrupt Figure 5 2 S3F80K5 Interrupt Structure NOTE Reset interrupt vector address Basic timer overflow can be varied by smart option ELECTRONICS INTERRUPT STRUCTURE Reset Clear H W S W H W S W H W H W 5 3 INTERRUPT STRUCTURE S3F80K5 UM REV1 11 INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3F80K5 interrupt structure are stored in the vector address area of the internal program memory ROM 00H FFH See Figure 5 3 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not
220. tendene 6 72 RR Rotae IGM PR cito 6 73 RRC Rotate Right Through Cam viii dea 6 74 SBO Select BUM o a o aed ore a 2a 6 75 SB1 Select Bak Dita tada iia id nea 6 76 SBC Subtract With Be 6 77 SCF Ser Gary A retretten at E 6 78 SRA Shift Right Artthmette AAA 6 79 SRP SRPO SRP1 Set Register e EE 6 80 STOP Stop Operaer eege ee 6 81 SUB lee EE 6 82 SWAP Eeler EE 6 83 TCM Test Complement Under Mask 6 84 TM Test Under Maskuun skiferen ind 6 85 WFI Walt Forinterrupt ikt deed dee ee ii tard 6 86 XOR LogicallExclusive OR Linnea eee areas 6 87 S3F80K5 UM REV1 11 MICROCONTROLLER xix S3F80K5 UM REV1 11 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 S3F8 SERIES MICROCONTROLLERS Samsung s S3C8 S3F8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various flash memory ROM sizes Important CPU features include e Efficient register oriented architecture e Selectable CPU clock sources e Idle and Stop power down mode release by interrupts e Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum four CPU clocks can be assigned to specific interrupt levels S3F80K5 MICROCONTROLLER The S3F80K5 single chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is based on Samsung s
221. terrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 7 and Banko Bit values can be read and written by instructions using the register addressing mode Interrupt Mask Register IMR DDH Set 1 Bank 0 R W Interrupt Level Enable Bits 7 0 0 Disable mask interrupt 1 Enable un mask interrupt NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended Figure 5 6 Interrupt Mask Register IMR 5 10 ELECTRONICS S3F80K5 UM REV1 11 INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR FFH Set 1 Bank 0 is used to set the relative priorities of the interrupt levels used in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt source is active the source with the highest priority level is serviced first If both sources belong to the same interrupt level the source with the lowest vector address usually has priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figur
222. ters CFH gt tre Pointers Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RPO points to locations COH C7H and RP1 to locations C8H CFH that is to the common working register area NOTE In the S3F80K5 microcontroller only page0 is implemented Page0 containsall of the addressable registers in the internal register file Page 0 Page 0 Hi Register Addressing Only Indirect Addressing Register Modes Indexed 1 Addressing Can be Pointed by Register Pointer Modes Figure 2 10 Register File Addressing 2 14 ELECTRONICS S3F80K5 UM REV1 11 ADDRESS SPACE COMMON WORKING REGISTER AREA COH CFH After a reset register pointers RPO and RP1 automatically select two 8 byte register slices in set 1 locations COH CFH as the active 16 byte working register block RPO gt COH C7H RP1 gt C8H CFH This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations Following a hareware reset register pointers RPO and RP1 point to the common working register area locations COH CFH RPo 1100 0000 RPi 11001 1000 Figure 2 11 Common Working Register Area ELECTRONICS 2 15 ADDRESS SPACE S3F80K5 UM REV1
223. ters and 272 registers are for general purpose use The extension of register space into separately addressable areas sets banks is supported by various addressing mode restrictions the select bank instructions SBO and SB1 Specific register types and the area occupied in the S3F80K5 internal register space are summarized in Table 2 1 Table 2 1 The Summary of S3F80K5 Register Type Register Type Number of Bytes General purpose registers including the 16 byte common working register area 272 the 64 byte set 2 area and 192 byte prime register area of page 0 CPU and system control registers Mapped clock peripheral and UO control and data registers bank 0 27 registers 39 bank 1 12 registers Total Addressable Bytes P8838 ELECTRONICS 2 5 ADDRESS SPACE Bank 0 System and Peripheral Control Register Register Addressing Mode System Register Register Addressing Mode Working Register Working Register Addressing only S3F80K5 UM REV1 11 General Purpose Data Register Indirect Register or Indexed Addressing Modes or Stack Operations Prime Data Register All Addressing Mode Figure 2 3 Internal Register File Organization 2 6 ELECTRONICS S3F80K5 UM REV1 11 ADDRESS SPACE REGISTER PAGE POINTER PP The S3C8 S3F8 series architecture supports the logical expansion of the physical 333 byte internal register files using an 8 bit data bus into as many as 16 separately addre
224. tes If 0500H the ISP area can be assigned from 0100H to 04FFH 1024bytes If 0900H the ISP area can be assigned from 0100H to 08FFH 2048bytes If ISP Protection Enable Disable Bit is 0 user can t erase or program the ISP area selected by 3EH 1 and 3EH 0 in flash memory User can select suitable ISP protection size by 3EH 1 and 3EH 0 If ISP Protection Enable Disable Bit 3EH 2 is 1 3EH 1 and 3EH 0 are meaningless External interrupts can be used to release stop mode When RESET Control Bit 3FH 0 is 0 and external interrupts is enabled external interrupts wake MCU from stop mode and generate reset signal Any falling edge input signals of PO or P2 4 P2 7 can wake MCU from stop mode and generate reset signal When RESET Control Bit 3FH 0 is 1 S3F80K5 is only released stop mode and is not generated reset signal ELECTRONICS S3F80K5 UM REV1 11 ADDRESS SPACE REGISTER ARCHITECTURE In the S3F80K5 implementation the upper 64 byte area of register files is expanded two 64 byte areas called set 1 and set 2 The upper 32 byte area of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and the lower 32 byte area is a single 32 byte common area In case of S3F80K5 the total number of addressable 8 bit registers is 333 Of these 333 registers 22 bytes are for CPU and system control registers 39 bytes are for peripheral control and data registers 16 bytes are used as shared working regis
225. th an OTP MTP programmer In Circuit Emulator for SAM8 family OPENice i500 SmartKit SK 1200 OTP MTP Programmer SPW uni AS pro US pro GW PRO2 8 gang programmer Development Tools Suppliers Please contact our local sales offices or the 3rd party tool suppliers directly as shown below for getting development tools 8 bit In Circuit Emulator OPENice i500 AL System e TEL 82 31 223 6611 e FAX 82 331 223 6613 e E mail openice aijisystem com e URL hitp www aijisystem com gt H SK 1200 Seminix TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http www seminix com ELECTRONICS 18 7 DEVELOPMENT TOOLS OTP MTP PROGRAMMER WRITER S3F80K5 UM REV1 11 SPW uni Single OTP MTP FLASH Programmer e Download Upload and data edit function e PC based operation with USB port e Full function regarding OTP MTP FLASH MCU programmer Read Program Verify Blank Protection e Fast programming speed 4Kbyte sec e Support all of SAMSUNG OTP MTP FLASH MCU devices Low cost NOR Flash memory SST Samsung NAND Flash memory SLC New devices will be supported just by adding device files or upgrading the software SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail salesOseminix com e URL http www seminix com AS pro On board programmer for Samsung Flash MCU e Portab
226. the program counter and stack pointer are the same as in the first example if program address 0040H contains 35H and program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET CCF Complement Carry Flag CCF Operation Flags Format Example C lt NOT C The carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero if C 0 the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex opc 1 4 EF Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register 0D5H changing its value from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET S3F80K5_UM_REV1 11 CLR Clear CLR dst Operation dst lt 0 The destination location is cleared to 0 Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 BO R B1 IR Examples Given Register OOH 4FH register 01H 02H and register 02H SEH CLR OOH Register 00H OOH CLR 01H gt Register 01H 02H register 02H OOH In Register R addressing mode the statement CLR 00H clears the destination register 00H value to OOH In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register
227. the value that is written to the Timer 1 reference data registers TIDATAH and T1DATAL When a match condition is detected by the 16 bit comparator the match interrupt is generated the counter value is cleared and up counting resumes from OOH In match mode program software can poll the Timer 1 match capture interrupt pending bit T1CON 0 to detect when a Timer 1 match interrupt pending condition exists T1CON 0 1 When the interrupt request is acknowledged by the CPU and the service routine starts the interrupt service routine for vector F6H must clear the interrupt pending condition by writing a 0 to T1CON 0 IRQ1 T1INT Pending T1CON 0 Interrupt Enable Disable T1CON 1 16 Bit Up Counter 16 Bit Comparator Timer 1 High Low T1CON 5 Buffer Register T1CON 4 Match Signal T1CON 3 Timer 1 Data High Low Buffer Register Figure 11 2 Simplified Timer 1 Function Diagram Interval Timer Mode ELECTRONICS 11 3 TIMER 1 S3F80K5 UM REV1 11 T1CON 7 6 T1CON 2 OVF cb RQ1 CAOF T F F __ _ __ gt g fosc 4 16 Bit Up Counter R ET E Clear Ti CON 3 fosc 8 Read Only gt f 1 mg E Match note TICON 16 Bit Compatator MUX Timer 1 High Low T1CON 5 4 T1CON O IRQ1 Buffer Register T1CON 3 Match Signal T1OVF Timer 1 Data High Low Register f Data Bus NOTE Match signal is occurrd only in interval mode Figure 11 3 Timer 1 Block Diag
228. three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 12 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC R6 is 0 which selects RPO The five high order bits stored in RPO 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B 2 16 ELECTRONICS S3F80K5 UM REV1 11 ADDRESS SPACE RPO RP1 Selects RPO or RP1 Address OPCODE NAAA III es 4 bit address procides three Register pointer low order bits provides five high order bits III we Together they create an 8 bit register address Figure 2 12 4 Bit Working Register Addressing RP1 Selects RPO i R6 OPCODE 01110 ja p ese Ge address 0110 1110 Instruction 76H INC R6 Figure 2 13 4 Bit Working Register Addressing Example ELECTRONICS 2 17 ADDRESS SPACE S3F80K5 UM REV1 11 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100B This 4 bit value 1100B indicates that the remaining
229. three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level See Figure 5 1 Type 1 One level IRQn one vector V1 one source Sy Type 2 One level IRQn one vector V1 multiple sources S4 Sn Type 3 One level IRQn multiple vectors V1 Vn multiple sources S1 Sn Sn 1 Sn m In the S3F80K5 microcontroller all three interrupt types are implemented Levels Vectors Sources Type 1 RAN Vi A DI Si Type 2 IRAN S2 S3 Sn Si Type 3 IRQn e NOTE The number of Sn and Vn value is expandable Figure 5 1 S3C8 S3F8 Series Interrupt Types The S3F80K5 microcontroller supports fifteen interrupt sources Thirteen of the interrupt sources have a corresponding interrupt vector address the remaining two interrupt sources share by two vector address Six interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrup
230. time interval has elapsed the instruction stored in reset address is fetched and executed NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON But we recommend you should use it to prevent the chip malfunction 8 14 ELECTRONICS S3F80K5 UM REV1 11 RESET HARDWARE RESET VALUES Tables 8 2 list the reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values A 1 or a 0 shows the reset bit value as logic one or logic zero respectively An x means that the bit value is undefined after a reset Adash means that the bit is either not used or not mapped but a 0 is read from the bit position Table 8 2 Set 1 Bank 0 Register Values After Reset ee EE Dec Hex 7 6 5 4 3 2 4 o Timer 0 Counter Register TOCNT 208 DOH 0 01010101 01010 Timer 0 Conor Register tocon 210 oan folofofofofofolo Basie Ter Control Register om an oan fo fo fofolfolfolfolo Clock Convoi Register acon fere oem o olfofofolofolo System Flags Register racs
231. timer counter overflows 2 It is available only in using internal mode Figure 10 7 Basic Timer and Timer 0 Block Diagram ELECTRONICS 10 9 BASIC TIMER and TIMER 0 S3F80K5 UM REV1 11 L PROGRAMMING TIP Configuring the Basic Timer This example shows how to configure the basic timer to sample specifications ORG 0100H RESET DI Disable all interrupts LD BTCON 0AAH Disable the watchdog timer LD CLKCON 18H Non divided clock CLR SYM Disable global and fast interrupts CLR SPL Stack pointer low byte gt 0 Stack area starts at OFFH SRP 0COH Set register pointer gt OCOH El Enable interrupts MAIN LD BTCON 52H Enable the watchdog timer Basic timer clock fosc 4096 Clear basic timer counter NOP NOP JP T MAIN 10 10 ELECTRONICS S3F80K5 UM REV1 11 BASIC TIMER and TIMER 0 PROGRAMMING TIP Programming Timer 0 This sample program sets timer 0 to interval timer mode sets the frequency of the oscillator clock and determines the execution sequence which follows a timer 0 interrupt The program parameters are as follows Timer 0 is used in interval mode the timer interval is set to 4 milliseconds Oscillation frequency is 6 MHz General register 60H page 0 gt 60H 61H 62H 63H 64H page 0 is executed after a timer 0 interrupt VECTOR 00FAH TOOVER VECTOR OOFCH TOINT ORG RESET DI LD SRP EI D D TOINT PUSH SRPO ING ADD ADC ADC 0100
232. to one of the 248 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RPO points to address COH in register set 1 bankO selecting the 8 byte working register slice COH C7H Not used for S3F80K5 o RP1 Register Pointer 1 D7H Seti Bank Reset Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 248 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP1 points to address C8H in register set 1 bankO selecting the 8 byte working register slice C8H CFH Not used for S3F80K5 N l o ELECTRONICS 4 37 CONTROL REGISTERS S3F80K5 UM REV1 11 SPL Stack Pointer Low Byte D9H Seti Bank0 Reset Value Xx Xx Xx Xx x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The SP value is undefined following a reset STOPCON Stop Control Register FBH Seti Bank0 Reset Value 0 0 0 0 0 0 0 0 Read Write WwW W W W W W W W Addressing Mode Register addressing mode only 7 0 Stop Control Register Enable Bits rjofi
233. to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H Reset address can be changed by smart option Refer to Table 15 3 or Figure 2 2 Decimal 16 383 16 Kbyte Internal Program Memory Flash Memory 01FFH 02FFH 04FFH or 08FFH note O0FFH 003FH 003CH 0000H Figure 5 3 ROM Vector Address Area NOTE The size of ISP sector can be varied by Smart Option refer to Figure 2 2 According to the smart option setting related to the ISP ISP reset vector address can be changed one of addresses to be selected 200H 300H 500H or 900H 5 4 ELECTRONICS S3F80K5 UM REV1 11 INTERRUPT STRUCTURE Table 5 1 S3F80K5 Interrupt Vectors Vector Address Interrupt Source Request Reset Clear Ea eee Value Value Level Level ass Jm BasioumerovemtowPoR Reser y _ ase rom _ TimerOmatchicape mo 1 v eso FAH mmeroovemow o fv CS aso rom timertmatocapre moar 1 Jf ass Fam merov SS o Y 26 E ooumera m fy as au po7exemalimemer mer ase es rosexemarimemer as em fposetemalinemm ase Em Posextematimerupt o Y aso Pm Posexemalimemm ma 3 v ess em Pozextemalinterut 2 91 C em Poneman gt yv eo rooexemalimemm o fa 00H p2oexemalimemm me v NOTES 1 Interrupt priorities are ident
234. tor address always begins at an even numbered ROM address within the range 00H FFH NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR 5 Execute an IRET Depending on the application you may be able to simplify the above procedure to some extent INSTRUCTION POINTER IP The instruction pointer IP is used by all S8C8 S3F8 series microcontrollers to control the optional high speed interrupt processing feature called fast interrupts The IP consists of register pair IPH DAH Gert Bank0 and IPL DBH Seti BankO The IP register names are IPH high byte IP15 IP8 and IPL low byte IP7 1P0 FAST INTERRUPT PROCESSING The feature called fast interrupt processing lets you specify that an interrupt within a given level be completed in approximately six clock cycles instead of the usual 22 clock cycles To select a specific interrupt level for fast interrupt pr
235. upt level is not pending 1 Interrupt level is pending Figure 5 9 Interrupt Request Register IRQ ELECTRONICS 5 13 INTERRUPT STRUCTURE S3F80K5 UM REV1 11 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits One type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other type must be cleared by the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs lt then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the S3F80K5 interrupt structure the timer O overflow interrupt IRQO the timer 1 overflow interrupt IRQ1 and the counter A interrupt IRQ2 belong to this category of interrupts whose pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit must be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written
236. upt pending bit Interval Timer Mode In interval timer mode a match signal is generated when the counter value is identical to the value written to the TO reference data register TODATA The match signal generates a timer O match interrupt TOINT vector FCH and clears the counter If for example you write the value 10H to TODATA OBH to TOCON the counter will increment until it reaches 10H At this point the TO interrupt request is generated And after the counter value is reset counting resumes With each match the level of the signal at the timer 0 output pin is inverted See Figure 10 4 IRQO TOINT TOCON 0 Interrupt Enable Disable TOCON 1 P3 0 TOCAP TOCON 5 TOCON 4 Match Signal TOCON 3 TimerO Data Register TODATA Figure 10 4 Simplified Timer 0 Function Diagram Interval Timer Mode 10 6 ELECTRONICS S3F80K5 UM REV1 11 BASIC TIMER and TIMER 0 Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TOPWM pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 0 data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from OOH Although you can use the match signal to generate a timer 0 overflow interrupt inter
237. value to 00H 6 28 ELECTRONICS S3F80K5 UM REV1 11 COM Complement COM Operation Flags Format Examples dst dst lt NOT dst INSTRUCTION SET The contents of the destination location are complemented one s complement all 1s are changed to Os and vice versa C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Bytes Cycles opc dst 2 4 Given R1 07H and register 07H OF1H COM Ri gt HI OF8H COM R1 gt HI 07H register 07H OEH Opcode Addr Mode Hex dst 60 R 61 IR In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of destination register 07H 11110001B leaving the new value OEH 00001110B ELECTRONICS 6 29 INSTRUCTION SET S3F80K5_UM_REV1 11 CP Compare CP Operation Flags Format Examples dei erc dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison C Set if a borrow occurred src gt
238. visualize the size and relative locations of selected working register spaces One working register slice is 8 bytes eight 8 bit working registers RO R7 or R8 R15 One working register block is 16 bytes sixteen 8 bit working registers RO R15 All of the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file The base addresses for the two selected 8 byte register slices are contained in register pointers RPO and RP1 After a reset RPO and RP1 always point to the 16 byte common area in set 1 COH CFH Slice 32 11111XXX RP1 Registers R8 R15 Each register pointer points to one 8 byte slice of the register space selecting a total 16 byte working register block 00000XXX RPO Registers RO R7 Slice 1 Figure 2 6 8 Byte Working Register Areas Slices 2 10 ELECTRONICS S3F80K5 UM REV1 11 ADDRESS SPACE USING THE REGISTER POINTERS Register pointers RPO and RP1 mapped to addresses D6H and D7H in set 1 are used to select two movable 8 byte working register slices in the register file After a reset they point to the working register common area RPO points to addresses COH C7H and RP1 points to addresses C8H CFH To change a register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction see Figures 2
239. x dst src NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 01H BCP R1 01H 1 gt Ri 07H register 01H 01H If destination working register R1 contains the value 07H 00000111B and the source register 01H contains the value 01H 00000001B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register 0D5H ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET BITC pit Complement BITC Operation Flags Format Example dst b dst b lt NOT dst b This instruction complements the specified bit within the destination without affecting any other bits in the destination C Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected TUSON Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITC Ri 1 gt R1 05H If working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 000
240. xample of how to use an EXIT statement Before After L 140 Exit 2F 20 IPH 7 00 21 IPL 50 Data Memory 22 Data Memory Stack Stack 22 6 42 Address Data IP 0052 Data Address Data PC 0060 PCL old 60 7 60 Main PCH 00 SP 0022 ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET IDLE idie Operation IDLE Operation Flags Format Example The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 6F The instruction IDLE stops the CPU clock but not the system clock ELECTRONICS 6 43 INSTRUCTION SET S3F80K5_UM_REV1 11 INC Increment INC Operation Flags Format Examples dst dst lt dst 1 The contents of the destination operand are incremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst r Oto F opc dst 2 4 20 R 4 21 IR Given RO 1BH register OOH OCH and register 1BH OFH INC RO gt RO 1CH INCOOH gt Register 00H ODH INCORO gt RO 1BH register 01H 10H In the first example if destination working
241. y flag the initial value of the carry flag replaces bit 7 MSB Flags Format Examples C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 CO R C1 IR Given Register OOH 55H register 01H 02H register 02H 17H and C 0 RRC 00H gt Register 00H 2AH C 1 RRC 01H gt Register 01H 02H register 00H OBH C 1 In the first example if general register OOH contains the value 55H 01010101B the statement RRC 00H rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010B in destination register OOH The sign flag and overflow flag are both cleared to 0 ELECTRONICS S3F80K5 UM REV1 11 INSTRUCTION SET SBO Select Bank 0 SBO Operation BANK lt 0 The SBO instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The
242. ystem Niege EE 7 1 Clock Status During Power Down Modes oooooococccccccccoccconocanonoccconcn non n cnn cc ronca 7 3 System Clock Control Register CLKCON canon n cnn cc narran 7 4 Chapter 8 RESET OVemMEW un EE EE AT A EE AA EE EE 8 1 Reset Sources iii A AAA ndla 8 1 Reset Mechas ic di E A 8 4 External RESET Plis id a Eat ET E ee EAT TA DEA A AS Ge 8 4 Watch Dog Timer Reset ist a 8 4 NEI Reset A A Red A A AE 8 4 Internal Power On Reset amic lidia eras iaa lat eden oa iaa diia 8 5 External Interrupt Reset rarios ii A dd 8 6 Stop Error Detection amp Recovery cooccoccccnnnncnnocinnncccconccnnoncnn nan cc rra 8 7 External Reset Plica dida 8 7 Power Down Modest ia A Aa adn toa A Di 8 8 elle ie EE 8 8 Back up Mode oone pda ekke derunder erd 8 9 Stop Mod Li areas aiid de andakter ar Rates ee ee ek bin 8 11 Sources to Release Stop Mode 8 12 System Reset Operaatio Nirien ia thw A ieee a ean as Aen 8 14 Hardware Reset Values c ccccccceceeenece cece eeteeeeesanaeceeeee ea caaaaeaeeeeeeeegeaaaeaeceeeedeeesgaaaaeeeeeseseseeaeaaeaeeeeeess 8 15 Recommendation for Unusued Pins 8 19 Summary Table of Back Up Mode Stop Mode and Reset Gtaius nnne nrnnnrrr nnee en na 8 20 Chapter 9 UO Ports OOVETVICW Hane egee ENEE Eed ae d se ee eege ane Maas 9 1 Port Data UE 9 3 Pull Up Resistor Enable Registers iaeiiai iennet aaiae aaa iiaa anaia ier aiias 9 4 S3F80K5_UM_REV1 11 MICROCONTROLLER vii Table of Contents Continued Chapter 10 Bas

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