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VR Series 64-/32-Bit Microprocessor Programming Guide AN

1. Each bit of the cache line is described below ECC ECC for Tag and Data Tag Secondary cache tag Pi Parity bit Data Cache data 56 Application Note U10710EJ5VOAN CHAPTER 3 CACHE 3 3 Cache Instructions Cache instructions CACHE are assembler instructions for Vr Series processors They are used to control caches and cache lines For the Vr Series processors cache instructions have the following format cache op offset base Each cache instruction is added to the contents of the general purpose register base with a 16 bit offset sign extension to create a virtual address The 5 bit suboperation code op specifies the cache operation corresponding to the specified cache block If the Status registers CUO has been cleared in user mode or supervisor mode the CPO is disabled and therefore a coprocessor disabled exception will occur if this instruction is executed Instruction execution is undefined if an instruction is combined with a cache operation that is not listed in Table 3 2 or Table 3 3 Instruction execution to secondary cache is undefined if there is no secondary cache Execution of this instruction is also undefined if it is for an uncached area The lower two bits 0p1 0 of the suboperation code indicate the operation s target cache Table 3 2 Cache Instructions Suboperation Code op o Cache Type a Primary instruction cache The higher three bits 0p4 2 of the suboperation code specify the cache
2. mtco 0 i cache La 8 li 59 cache clear cache 0x00 addiu 59 bgtz 59 addiu 8 d cache la 8 li 59 decache clear cache 0x09 addiu 9 bgtz 59 addiu 8 28 0x80000000 0x8000 8 S9 0x10 H H H TE Leache clear S8 0x10 0x80000000 0x4000 8 9 0x10 H H Mdcache clear 8 Ox10 set CU0 1 RE 0 BEV 0 TS 0 SR 0 CH 0 CE 0 DE 0 IM 0 KX 0 5X 0 UX 0 KSU 0 ERL 0 EXL 0 IE 0 set PAddr0 0 R 0 W 0 base addr of VPN2 number of TLB entries VPN2 increment EntryHi EntryLoO EntryLol PageMask Index Write Indexed TLB Entry TagLo vaddr 1 cache size 32KB Index Invalidate increment of line size vaddr d cache size 16KB Index Store Tag increment of line size initialize peripheral d 8 Oxaf000000 Application Note U10710EJ5VOAN 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 CHAPTER 5 CPU INITIALIZATION BCU SDRAMU etc Add change the register settings in accordance with the hardware li 9 0x0000 sh 9 0x0000 8 BCUCNTREG1 lt 0x0000 li 9 0x2222 sh 9 0x0004 8 ROMSIZEREG lt 0x2222 Ta 9 0x3007 sh 9 0x0006 8 ROMSPEEDREG lt li 9 0x0080 sh 9 0x0016 8 BCUCNTREG3 lt 0x0080
3. 5 System control coprocessor System control coprocessor instructions execute operations on CPO registers in order to perform memory management and exception processing of the processor 6 Special Special instructions execute system call exceptions and breakpoint exceptions These instructions are R type 7 Exception Exception instructions generate trap exceptions based on the comparison result These instructions are R type and l type 22 Application Note U10710EJ5VOAN CHAPTER 1 OUTLINE The following shows an example of arithmetic operation in the Vr Series Figure 1 5 Example of R type ADD r14 r11 r10 Instruction code General purpose register Figure 1 6 Example of I type ADDI r14 r11 0x0100 Instruction code General purpose register For details of the MIPS16 instruction set refer to the user s manual of each product in the Vn4100 Series Application Note U10710EJ5VOAN 23 VOLUME 2 Vr SERIES ARCHITECTURE 1 1 4 Registers The CPU of the Vr Series includes the following registers e Integer general purpose registers 64 bits x 32 e Program counter 64 bits e HI register 64 bits e LOregister 64 bits e LL bit register 1 bit the Vr4100 Series does not have this register Among these registers the program counter HI and LO registers and LL bit register are special function registers used or revised by certain instructions The program coun
4. 8 Argument 9 d None 10 Return value 11 None 12 globl initcache 13 ent initcache 14 initcache 15 mfco S8 16 Reference Config register 16 andi 10 8 Ox0E00 Check IC bit 17 srl S10 10 9 18 andi S11 8 Ox01C0 Check DC bit 19 sul Sil 11 6 20 andi 12 8 0x0020 Check IB bit pa srl 9127 25 22 andi S13 8 0x0010 Check DB bit 23 srl Slady SL3 4 24 andi 9 8 Ox1000 Check CS bit 25 bgtz S9 sesl 26 addiu 8 0 1 27 Cache size calculation when CS 0 28 addiu 10 10 10 IC 2 n 10 29 sliv 10 8 10 30 addiu bolts SITL 10 DC 2 n 10 31 sllv Sil 595 5d 32 j bsz 33 nop 34 X091 Cache size calculation when CS 1 35 addiu SLED S 9o 2 t IC 2 mera 36 sllv S10 S8 910 37 addiu Silos SLL 2 DC 2 n 12 38 sliv olle 58 SLI 39 bsz Cache block size calculation 40 addiu S12 512 4 IB 41 sllv S12 584 S12 42 addiu 513 S134 vd DB 43 sllv 513 8 13 44 _initcache Application Note U10710EJ5VOAN 93 VOLUME 3 PROGRAMMING mtco SO 28 Instruction cache initialization li 8 0x80000000 Set start virtual address add S9 8 10 Add cache size subu S9 9 12 Set end virtual address Set TagLo register to 0 cache 0x00 8 bne DO 09 Le LOOp addu S8 8 12 Data cache initialization li 8 0x80000000 add S9 8 11 subu 59 9s E CACHE instruction Index Invalidate Is initialization of cache size compl
5. Used in memory management TLB 4 fome Uwdiewsionpoees O reen Usedin memory management MB o _ 6 we Lannen o aa Usean exception procesis l _ Too seamescepionprocessn o _ femm segimemonmanagemen MB o n comparison Usedin exception pressing R Sube Usdin exception processing andorseidagrosis O 13 cause ses exception processing Re Weieen o _ e fee vesginmemowmanagomen EI Lenneng A WatchLo Used in exception processing debugging reserved in Vr5000 Series WatchHi Used in exception processing debugging reserved in VR5000 Series Used in exception processing FrameMask Used in memory management TLB Vr10000 Series only Performance Used in exception processing debugging Vr5500 Counter VR10000 Series dud ErrorEPC Used in exception processing Remark O Possible A Partially possible Not possible Application Note U10710EJ5VOAN 25 VOLUME 2 Vr SERIES ARCHITECTURE The following describes the Config register and Status register which are important in initialization etc among these CPO registers 26 1 Config register The Config register can be read written and displays sets various states of the processor The Config register of each CPU appears as shown below Figure 1 7 Config Register 1 2 a Vn4121 Vn4181 31 30 28 27 24 23 22 20 19 15 14 13 12 11 oso es ola jm 0010 vo ee we do Ts Tm Te b Vr4122 31 30 28 27 24 23 22 21 20 19 1
6. EntryHi register 5 unsigned int Lo0 EntryLo0 register 6 unsigned int Lol EntryLol register 7 unsigned int Mask PageMask register 8 13 9 10 struct tib tlbwritet int struct tlb 3 11 12 Jw TLB setting 13 define ASID 0x0 Address space ID 14 define PFN 0x0 Page frame number 15 define E 0 Algorithm 16 define D 0 Dirty bit 17 define V 0 Valid bit 18 define G 0 Global bit 19 define MASK 1 Mask 20 21 Number of TLB entries 22 ifdef Vr5000 For Vr5000 23 define MAX TLB 47 24 else Vr5000 For Vr41xx Vr43xx 25 define MAX TLB 31 26 endif Vr5000 27 28 void inittlb 29 30 Variable 31 int tlb num TLB number 32 struct tlb Tlb Structure 3 3 unsigned long vpn 20x80000 Virtual page number 34 35 Tlb Lo0 PFN lt lt 6 C lt lt 3 D lt lt 2 v lt lt 1 loe 36 T1b Lol PFN lt lt 6 C lt lt 3 D lt lt 2 V 1 la 37 1ifdef Vr41xx 38 Tlb Mask MASK lt lt 11 39 else 40 T1b Mask MASK lt lt 13 41 endif 110 Application Note U10710EJ5VOAN CHAPTER 3 TLB for tlb num 0 tlb num lt MAX TLB tlb num Tlb Hi vpn 2 13 ASID tlbwrite Clb num TL 4 vpn j 3 5 TLB Entry Replacement Because the Vn Series has a limited number of TLB entries depending on the OS monitor etc it is necessary to save TLB entries in memory etc and replace the
7. EntryLo1 EntryLoO 4 TLBWR Translation Lookaside Buffer Write Random The contents of the EntryHi EntryLoO EntryLo1 and PageMask registers are written to the TLB entry that is indicated by the Random register contents Figure 4 13 TLBWR Instruction Stores data PageMask Specifies entry EntryHi Random en TLB entry EntryLo1 EntryLoO 72 Application Note U10710EJ5VOAN CHAPTER 5 EXCEPTIONS 5 1 Types of Exceptions The Vr Series has the following exceptions e Cold reset e Soft reset e Address error e TLB e Cache error does not occur in the Vr4300 Series e Bus error e Integer overflow e Trap e System call e Breakpoint e Reserved instruction e Coprocessor unusable e Floating point arithmetic does not occur in the Vr4100 Series e Watch does not occur in the Vr5000 Series e Interrupt Application Note U10710EJ5VOAN VOLUME 2 Vr SERIES ARCHITECTURE 5 2 Priority of Exceptions When more than one exception simultaneously occurs for an instruction only one of them is selected The priority of exceptions is shown in Table 5 1 Table 5 1 Priority of Exceptions Exception Name High Cold reset Soft reset NMI Address error Instruction fetch TLB refill Instruction fetch TLB invalid Instruction fetch Cache error Instruction fetch Bus error Instruction fetch System call Breakpoint Coprocessor unusable Reserved
8. Hdefine ORIGIN 0x80000000 Cache tag display function void Print CacheTag void unsigned int vaddr tag printf I CACHE n for vaddr ORIGIN vaddr lt tag printf 08x 08x n printf D CACHE n for vaddr ORIGIN vaddr lt tag printf 08x 08x n ORIGIN ICache SIZE vaddr vaddr ORIGIN DCache SIZE vaddr vaddr int type K instruction cache size is 32 KB instruction cache block is 16 bytes data cache size is 16 KB data cache block is 16 bytes Cache BLK cache index load tag vaddr 0 tag DCache BLK cache index load tag vaddr 1 tag Application Note U10710EJ5VOAN 103 CHAPTER 3 TLB This chapter describes methods of reading from writing to and make settings to the TLB of Vr Series processors using C language and an assembler 3 1 Entry Read This section describes the creation of a C language type function tlbread by the assembler for reading the contents of a TLB entry The following shows the specification of this function struct tlbi unsigned int Hr EntryHi register unsigned int Lo0 EntryLoO register unsigned int Lol EntryLol register unsigned int Mask PageMask register rs struct tlb tlbread int struct tlb A function is created with the TLB entry number to be read and the pointer to the structure for writing the read contents a
9. Set the CE bit of the Status register to 0 Initialize the TagLo register using the MTCO instruction Write to the cache tag using the Index_Store_Tag operation of the CACHE instruction instruction Initialize data block of the cache using the SW instruction Invalidate the cache line using the Index Hit _Invalidate operation of the CACHE instruction Note that the initial value of the CPO register used in the cache instruction is not guaranteed after reset Set the values of these registers before use 92 Application Note U10710EJ5VOAN CHAPTER 2 CACHE 2 1 2 Example of cache initialization program 1 Vr4100 Series and Vr4300 Series The cache initialization method in a CPU with no parity is shown below In a CPU with parity create an initialization program referencing the above procedure The following shows the assembler source list of the initialization program As seen from the list the cache size and cache block size line size are referenced from the Config register at line numbers 14 to 43 Set the Config register before calling this function The actual cache initialization processing is performed at line number 44 or later 1 Cache initialization function 2 Description gt SH Initialize instruction cache and data cache 4 d Since the cache size and cache block size line size are referenced in this 5 program set the correct value to the Config register before calling it 6 K Format 7 void initcache void
10. 5 2 Example of Initialization Program This section shows examples of initialization programs for Vr Series processors for each CPU When initializing CPU registers set the values required by the registers used in these programs In the following programs the CPU and FPU CP1 general purpose registers are not initialized When using these registers note that their initial values are not guaranteed 5 2 1 Vn4121 An example of an initialization program for an evaluation board from TANBAC Co Ltd TB0120 21 SDRAM is shown below Add change initialization depending on the hardware BCU etc in accordance with the system used The USER PROGRAM in the list indicates the start address of the program that starts execution after initialization is complete PETE TE TE T T T T RARA RARA RAR RD GHI AT AT AT AT de de de e ie e e e e e e EE EE EE EE EE EE EE EE EE EE E Initialization program sample VR4121 PETE TE TE T TE T T RARA RARA RRHH A A HH HH HH HH HH HH HH HH HH EH EH HH HH HH HE HE HE HH Ht EE EE EE EE E globl Initialize ent Initialize Initialize clear Hi Lo registers mthi SO mtlo SO Oo NI O U AS uN F clear k0 k1 registers li S26 0x00000000 li S27 0x00000000 initialize CP0 Config register mfco S8 16 li 9 Oxf07f7ff8 clear EP AD BE KO bits and DB BI Oo li 9 0x00000003 d set K0 3 Or 8 8 9 mtco 8 16 initialize CP0 Status register li 8 0x10000000 set CU0 1 RE 0 BEV
11. 9 10 TLB setting 11 define VPN 0x0 Virtual page number 12 define ASID 0x0 Address space ID 13 fdefine PFN 0x10000 Page frame number 14 define G 0 Cache algorithm 15 define D 1 E Dirty bat 16 define V 1 Valid bit 17 define G 1 Global bit 18 define MASK 1 Mask 19 define Entry 0 TLB entry number 20 21 1ifdef Vr41xx 22 define MASKLOW OxO7ff 23 else 24 define MASKLOW Ox1fff 25 Hendif 26 27 Program 28 main 29 30 Structure definition 31 struct tlb Tips 32 33 Assignment to structure 34 Tlb Hi VPN 2 lt lt 13 ASID 35 Tlb Lo0 PFN lt lt 6 C lt lt 3 D lt lt 2 ve lt 1 lo 36 Tlb Lol PFN MASK MASKLOW 1 lt lt 6 C lt lt 3 D lt lt 2 ve lt 1 G 37 Hifdef Vr41xx 38 Tlb Mask MASK lt lt 11 39 else 40 T1b Mask MASK lt lt 13 41 dendif 42 Write to TLB entry 43 tlbwrite Entry amp Tlb 44 When compiling the following sample linking it together with the object of the tlbwrite function and executing it TLB translation from the virtual address to the physical address operates as shown in the figure below to enable the memory of the virtual address 0x0000 0000 to 0x0000 1FFF 0x0000 0000 to 0x0000 O7FF for the Vr4100 Series to be referenced 108 Application Note U10710EJ5VOAN CHAPTER 3 TLB Figure 3 4 TLB Translation a
12. define Cache SIZE 0x4000 When cache size is 16 KB define Cache BLK 0x10 When cache block is 16 bytes Start point of virtual address Hdefine ORIGIN 0x80000000 Cache writeback function void Write Back cache all void unsigned int s vaddr ORIGIN for s vaddr lt ORIGIN Cache SIZE s vaddr Cache BLK cache index write back s vaddr x 2 3 Cache Fill The cache data fill procedure is described below To write data to cache memory from the main memory by software use the Fill operation of the CACHE instruction Normally it is not necessary to execute the Fill operation by software but it may be necessary in a specific situation such as when rewriting programs instructions by software for creating monitors etc A Fill operation is not provided for the data cache To fill the data cache with data use the LW instruction etc 100 Application Note U10710EJ5VOAN CHAPTER 2 CACHE 2 3 1 Example of cache fill program The assembler source list of the function that specifies the start and end points of the virtual address and fills the cache between these points is shown below Cache fill function Fill operation Description Fills instruction data from the memory specified by vaddr to the instruction cache Format void cache fill unsigned int vaddr Argument vaddr Cache block to be filled virtual address Return value ond ON U R UN r H H H H H H H H H None
13. globl cache Till ST cache till cache fill cache 0x14 0x0 4 Fill operation jr 31 nop end cache fill The C source list of the function that specifies the start and end points of the virtual address and fills the cache between these points using the above function is shown below Cache fill sample program Description Fills instruction cache between the points specified by s vaddr to e vaddr Format void Fill cache unsigned int s vaddr unsigned int e vaddr Argument s vaddr Start address virtual address o NI O U B UN F e vaddr End address virtual address Return value None Es External function extern void cache fill unsigned int vaddr Cache block setting define Cache BLK 0x10 When cache block is 16 bytes Cache fill function void Fill cache unsigned int s vaddr unsigned int e vaddr for s vaddr lt e vaddr s vaddr Cache BLK cache ill s vadde Application Note U10710EJ5VOAN 101 VOLUME 3 PROGRAMMING x2 4 Cache Tag Display The cache tag display procedure is described below To reference the contents of the cache tag use the Index_Load_Tag operation of the CACHE instruction x 2 4 1 Example of cache tag display program The assembler source list of the function that performs the Index_Load_Tag operation is shown below Cache tag load function Index Load Tag operation Description Reads the cache block tag for the specified inde
14. 0x80000000 64 dcache clear 65 cache 0x9 0x0 6 66 bne S6 11 dcache clear 67 addi 6 6 Ox10 68 69 Jump to user program 70 l3 S31 USER PROGRAM 7i jr 31 72 nop 73 end Init Vr4300 5 2 5 Vn5000 Series noreorder initb50 init50 init50 CP0 1 reg mfco 16 16 Config reg La Oxffffeff8 and S3 52 addiu 3 0x1003 mtco S16 SE 0x1 K0 0x3 li 0xb0000000 mtco S12 ol2 Status reg XXS0x14 QUISOXI CUOSOXL mtco 13 13 Cause reg IP 1 0 0x0 etc 31 31 FPU Control Status reg cache m co 12 li 0x00010000 or 3 2 mtco 12 DESOXI Application Note U10710EJ5VOAN 131 i cache d cache tag d cache datas S cache TLB tlb 132 mtco li li cache cache cache addiu bne nop li cache addiu bne nop li cache sd sd sd sd cache addiu bne nop al li cache addiu bne nop mtco li Li mtcO mtco mtco addiu mtco mtco 50 54 5 0x8 Ox14 Ox0 4 4 94 0x9 4 4 94 Oxd 20 20 20 20 Ox1 94 94 94 96 Oxb 4 4 92 92 93 50 50 50 92 92 93 VOLUME 3 PROGRAMMING 28 0x80000000 0x80008000 0x0 4 index store tag 0x0 S54 fill 0x0 4 index invalidate S4 0x20 Sop E acne 0x80000000 0x0 4 index store tag 4 0x20 055 d cache tag 0x80000000 0x0 4 0x0 4 0
15. Application Note U10710EJ5VOAN CHAPTER 1 OUTLINE The following describes the bits in the staus register XX Enables use of MIPS IV instructions in user mode VR5000 Series Vr5500 and Vn10000 Series only 1 gt Enable 0 gt Disable CU Enables use of coprocessors Controls use of four coprocessors 1 gt Enable 0 gt Disable In the kernel mode CPO can be used regardless of the CUO bit value RP Specifies low power mode Vn4300 Series and Vn10000 Series only 1 Low power mode 0 gt Normal Set to 0 in the Vr10000 Series FR Sets the number of floating point registers that can be used Reserved in the Vr4100 Series 132 0 16 HE Inversion of endian in user mode Except VR5432 and Vr5500 1 Inverted 0 gt Disabled Since the Vr4100 Series always operates using little endian set this bit to O DS Self diagnostic status area Refer to Figure 1 9 IM Interrupt mask enabling external internal and software interrupts Controls eight interrupts 1 gt Enable O gt Disable Interrupts are assigned to each bit as follows e Vn4100 Series IM7 Masks timer interrupt IM 6 2 Masks normal interrupt Int 4 0 However Int4 is not generated IM 1 0 Masks software interrupt e Vn4300 Series IM7 Masks timer interrupt IM 6 2 Masks external normal interrupt Int 4 0 and external write request IM 1 0 Masks software interrupt e VR5000 Series IM7 Masks timer interrupt and external normal interrupt Int5 IM 6
16. DB meco S13 COSR initialize ECC Reg mtcO 0 CO ECC initialize TagLo TagHi mtcO 0 CO TagLo MECO 50 CO Faglia initialize cache initialize I cache lui 8 0x8000 Base Application Note U10710EJ5VOAN 95 VOLUME 3 PROGRAMMING li 9 0x4000 32KB 2 I CACHE cache Index Store Tag I 0x0 8 Index Store Tag Way 0 cache Index Store Tag I 0x1 8 Index Store Tag Way 1 cache Index Store Data I OxO Index Store Data Way 0 cache Index Store Data I Oxli4 Index Store Data Way 1 cache Index Store Data I 0x4 Index Store Data Way O0 cache Index Store Data I 0x5 Index Store Data Way 1 cache Index Store Data I 0x8 Index Store Data Way O0 cache Index Store Data I 0x91 Index Store Data Way 1 cache Index Store Data I Oxc Index Store Data Way O0 Index Store Data Way 1 cache Index Store Data I 0x10 Index Store Data Way O0 cache Index Store Data L 0x11 Index Store Data Way 1 cache Index Store Data I 0x14 Index Store Data Way O0 cache Index Store Data T 0X15 Index Store Data Way 1 cache Index Store Data I 0x18 Index Store Data Way O0 cache Index Store Data Lj 0x19 Index Store Data Way 1 cache Index Store Data I Oxlc Index Store Data Way O0 cache Index Store Data I 0xid Index Store Data Way 1 cache Index Store Data I 0x20 Index Store Data Way O0 cache Index Store Data L 0X21 Index Store Data Way 1 cache Index Store Data I 0x24 Index Store Data W
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18. KOs3 CU 0 15 mfcO 8 16 16 li 9 OxfOff7ff0 17 li 10 0x06008003 18 and 8 8 DO 19 Or 8 8 10 20 mtcO 58 16 21 Status register 22 CU 0x3 RP 0 FR 0 RE 0 DS 1 IM 0 KX 0 23 SX 0 UX 0 KSU 0 ERL 0 EXL 0 IE 0 24 li Soy 0x30010000 25 mtco 9 12 26 WatchLo register 27 mtco O 18 28 29 Initialization of FPU register 30 Control Status register 31 FS 0 c 0 Cause bit 0x00 Enable bit 0x00 29 Flag bit 0x00 RM 00 30 ld 58 0x00000000 32 eio 8 So 33 34 Initialization of TLB 35 di 8 0x2000 36 T 9 0x80000000 37 move 10 0 38 li 11 31 32 entries 39 mtco 0 2 Initialization of EntryLo0 register 40 mtco SO 3 Initialization of EntryLol register 41 mtco S8 S5 Initialization of PageMask register 42 tlb clear 43 mtco S10 SO Set Index register 44 mtco S9 S10 Initialization of EntryHi register 45 tlbwi From TLB entry to each TLB entry register 46 nop 47 addi 9 9 0x2000 130 Application Note U10710EJ5VOAN CHAPTER 5 CPU INITIALIZATION 48 bne Sabios Clo clear 49 addi 10 Ox1 50 nop 51 52 Initialization of cache 53 mtco 0 28 Set TagLo register to 0 54 Initialization of instruction cache 55 li Sila 0x80003 e0 56 Tui S6 0x80000000 57 lcache Clear 58 cache seo 0x0 6 59 bne 6 11 icache clear 60 addi 6 6 0x20 61 Initialization of data cache 62 li Sql 0x80001 0 63 li 6
19. POS EAS 73 Vector address i 75 Exception processing i 78 A EE 78 Multiple interrupt 0 eee eee nn 81 Sal 80 F A TE 39 EP ias da EET TEE 37 INSTUCION ap 37 Register een 37 38 122 G General purpose exception 76 H HAL Timer Shut do WN ose est Ce adeo di 122 SE naanae teens 36 87 I Index register eee 68 Initialization program EE 93 E GN ace ee pe ET 123 EXCDO iin 118 Se 122 Ee 110 Instruction A O O BEE PEPR EL 57 OPUS es 22 SEKR EE 22 EPU re eee ee Se nee XQ 37 PAZ E 87 90 RR EE 71 A lei EE 44 A N 45 E UE 45 M Mapping of address 34 Application Note U10710EJ5VOAN 139 APPENDIX INDEX Memory hierarchy sane a 35 Memory management ssssseseeesrreerrsrrerrrerrrnrre 33 Multiple interrupt ee een nen 81 N KURS enden 75 115 0 A 19 P PageMask register 64 107 Bue Re ale 34 62 let lu doo titi 20 41 85 2 Way superscalar ENNEN 21 4 way superscalar necios cid meee 21 Branchirig delay iiis ete SR ii 46 85 BYPASSING ee 48 A EE 44 Eo AA 47 86 Number Of Stages 41 Ser FANON EE 42 43 SNGIEWAY as acted seein 20 o 45 UAC EE 41 SA UE 45 Program Branching del Via lia 85 Ren E 100 Cache initialization i 93 Cache tag display nennnneenneennnennnnnnnnsnnnesernene 102 Cache et e 98 CPU initialization iia 123 Discriminating between exceptions 115 116 FPU register mmalzaton
20. Pending 0 gt No interrupt However for IP 1 0 only an interrupt exception occurs when it is set to 1 by software Interrupts are assigned to each bit as follows Vn4100 Series IP7 Timer interrupt IP 6 2 Normal interrupt Int 4 0 However Int4 is not generated IP 1 0 Software interrupt Vr4300 Series IP7 Timer interrupt IP 6 2 External normal interrupt Int 4 0 and external write request IP 1 0 Software interrupt Vr5000 Series IP7 External normal interrupt Int5 and timer interrupt IP 6 2 External normal interrupt Int 4 0 and external write request IP 1 0 Software interrupt VR5432 IP7 Timer interrupt IP 6 2 External normal interrupt Int 4 0 and external write request IP 1 0 Software interrupt VR5500 IP7 External normal interrupt Int5 or timer interrupt IP 6 2 External normal interrupt Int 4 0 and external write request IP 1 0 Software interrupt 76 Application Note U10710EJ5VOAN CHAPTER 5 EXCEPTIONS e VR10000 Series IP7 Timer interrupt IP 6 2 External normal interrupt external interrupt request IP 1 0 Software interrupt ExcCode Exception code area For details refer to Table 5 4 O This is reserved Write a zero here A zero will be returned when this area is read Table 5 4 Exception Code Area of Cause Register T ee E T Aeneon OY ean T eee O C o n rarnana OOOO Te wem ee mem jw Application Note U10710EJ5VOAN TI V
21. define define define define define define define define define define define define define define define define define define define define define define define define define CO Index 0 CO Random 1 CO EntryLo0 2 CO EntryLol 3 CO Context 4 CO PageMask 5 CO Wired 6 CO BadVAddr 8 CO Count 9 CO EntryHi 10 CO Compare 11 CO SR 12 C0 Cause 913 CO EPC 14 CO PRId 15 C0 Config 16 CO LLAddr 17 CO WatchLo 18 CO WatchHi 19 CO XContext 20 CO FrameMask 21 60 Drag 22 CO Pere 925 CO ECC 26 CU CacheErr 27 CO TagLo 28 CO TagHi 29 CO ErrorEPC 30 SR XX 0x80000000 MipsIV mode enable SR CU2 0x40000000 Coprocessor 2 usable SR CU1 0x20000000 Coprocessor 1 usable Application Note U10710EJ5VOAN 135 VOLUME 3 PROGRAMMING define SR CUO 0x10000000 Coprocessor 0 usable Hdefine SR RP 0x08000000 SP bit Hdefine SR FR 0x04000000 FR bit define SR DE 0x00010000 parity or ECC to cause exceptions define BP All Taken 2 Predict all br as taken define Diag BPModeShf 16 bits 17 16 define Init BPT 00 2 bits 1 0 A ERRATA ce ck kc ck ke ck ARA cock ck ck RRA RARA RA kkk kkk kkk kkk kkk kkk kokok ui Main program i ES SS A SIEGE Set noat Set noreorder globl ane VELOO00 ent anit vrl0000 init_vr10000 Akk kkkk kkk kkk kkk kkk kkk kkk kkk kkk kk kkk kkk kkk kkk kk kkk kk kk k
22. li 9 0x8021 sh 9 0x0400 8 SDRAMMODEREG lt li 9 0x0533 sh 9 0x0402 8 d SDRAMCNTREG lt Ta 9 0x020c sh 9 0x0404 8 BCURFCNTREG lt li 9 0x4444 sh 9 0x0408 8 SAMSIZEREG lt 0x4444 PMU li 9 0x0002 sh 9 0x00c0 8 PMUINTREG lt 0x0002 ICU da 9 0x0001 sh 9 0x008c 8 MSYSINTIREG lt dr 9 0x0000 sh 9 0x0098 8 NMIREG lt 0 NMI HH reset haltimer jal haltimerrst nop start user program Tote 31 USER PROGRAM JE S31 nop HALTIMER RESET haltimerrst globl haltimerrst ent haltimerrst lui 8 Oxaf00 Shi PMUCNTREG lh 9 0x00a2 8 ori 9 9 0x4 set HALTIMERRST sh 9 0x00a2 8 jr 53 nop end haltimerrst Application Note U10710EJ5VOAN 127 VOLUME 3 PROGRAMMING x 5 2 3 Vn4181 An example of an initialization program is shown below Add initialization depending on the hardware bus control etc in accordance with the system used The USER_PROGRAM in the list indicates the start address of the program that starts execution after initialization is complete 1 FERRE TEE T K RE T K HH RRHH HA RRHH RRHH HA RRHH A RRHH ART RH HA RRHH RHEE RHEE 2 Initialization program sample VR4181 3 HHHHARH HH RRHH RAR HH HA RRHH RRHH HA RRHH AR RH HART RH HA RRHH AR REAR 4 globl Initialize 5 ent Initialize 6 Initialize 7 clear Hi Lo registers 8 mthi SO 9 mtlo SO 10 11 clear k0 k1 registers 12
23. one in which troubles one solved simply by stopping the pipeline called stall and one in which a part of pipeline is advanced and the rest delayed called slip The Vr4300 Series and Vr5432 only have a stall x In the VR5500 and VR10000 Series the pipeline flow is not interrupted by an interlock since out of order execution is used For details refer to Vr10000 Series User s Manual Exceptions and interlock conditions are checked for all valid instructions during each cycle Figure 2 4 Relationship Betweem Interlocks Exceptions and Faults Software Hardware 44 Application Note U10710EJ5VOAN CHAPTER 2 PIPELINE Figure 2 5 State of Pipeline During Interlock Stall a Single way pipeline RF EX DC b 2 way superscalar pipeline RF EX DC WB Figure 2 6 State of Pipeline During Interlock Slip a Single way pipeline EX DC WB b 2 way superscalar pipeline RF EX DC WB DIHS O DAT k JEE ES E Application Note U10710EJ5VOAN 45 VOLUME 2 Vr SERIES ARCHITECTURE 2 3 Delay 2 3 1 Branching delay For the sake of pipeline optimization a one cycle branching delay occurs in Vn Series processors However in x processors that incorporate a branch prediction unit this delay may not occur For details of the branch prediction unit refer to the user s manual of each processor The virtual address of the branching target that is generated at the EX stage of a jump branch instruction cannot be used u
24. 8 8 0x10 K d cache li 8 0x80000000 K 9 0x1000 K dcache clear cache 0x09 8 addiu S9 9 0x10 bgtz 09 deache clear addiu 8 8 0x10 Write Indexed TLB Entry TagLo vaddr 1 cache size AED Index Invalidate increment of line size vaddr d cache size 4KB Index Store Tag increment of line size HH initialize peripheral LX 8 Oxab000000 H Bus Control Add the register settings in accordance with the hardware PMU li 9 0x0002 sh 9 0x00a0 8 d ICU li 9 0x0001 sh 9 0x008c 8 H 11 9 0x0000 sh 9 0x0098 8 K HH reset haltimer jal haltimerrst nop start user program HK T3 31 USER PROGRAM jr 531 nop HALTIMER RESET globl haltimerrst ent haltimerrst haltimerrst lui 8 Oxab00 lh 9 Ox00a2 8 Ori S9 9 0x4 K sh 9 0x00a2 8 Application Note U10710EJ5VOAN PMUINTREG lt 0x0002 MSYSINTIREG lt 0x0001 NMIREG lt O NMI h1 PMUCNTREG set HALTIMERRST 129 VOLUME 3 PROGRAMMING jc S31 nop end haltimerrst x 5 2 4 Vr4300 Series l e 2 K Initialization program sample VR43XX 3 OH TREK KEE RH HR RRHH RAF HR RRHH RATA HR ir RH HAT RHEE 4 globl Initialize 5 ent Initialize 6 Initialize 7 Initialization of CPU register 8 Hi Lo registers 9 mthi SO 10 mtlo SO 11 12 Initialization of coprocessor register 13 Config register 14 HP 6 BE 1
25. BxcCode Cause 0x00000070 gt gt 2 5 Switch ExcCode case Int Describe processing for interrupt exception 116 Application Note U10710EJ5VOAN 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 break case Mod Describe break case TLBL Describe break case TLBS Describe break case AdEL Describe break case AdES Describe break case IBE Describe break case DBE Describe break case Sys Describe break case Bp Describe break case RI Describe break Case CDU Describe break case Ov Describe break case Tr Describe break case FPE Describe break case WATCH Describe break default break j return CHAPTER 4 EXCEPTIONS processing processing processing processing processing processing processing processing processing processing processing processing processing processing processing for for for for for for for for for for for for for for for TLB modified exception TLB refill exception TLB refill exception address error exception address error exception bus error exception bus error exception system call exception breakpo
26. Entry Read and 3 2 Entry Write Correctly set each register refer to the figures below EntryHi EntryLo0 EntryLo1 and PageMask and call tlowrite function Figure 3 1 EntryHi Register In 32 Bit Mode 8 7 0 8 Note The number of bits differs depending on the processor Vn4100 Series 21 bits Vn4300 Series Vr5000 Series Vr5432 VR5500 Vn10000 Series 19 bits Figure 3 2 EntryLo0 Lo1 Register In 32 Bit Mode 6 5 3 2 31 1 0 Lk AA e jew 1 1 3 1 Note The number of bits differs depending on the processor Vn4100 Series 22 bits Vr4300 Series VR5432 20 bits VR5000 Series Vn5500 24 bits Vr10000 Series 26 bits Figure 3 3 PageMask Register 0 31 The number of bits differs depending on the processor VR4100 Series 8 bits Vr4300 Series Vr5000 Series Vr5432 Vn10000 Series 12 bits VR5500 18 bits For details of the bit position refer to VOLUME 2 Figure 4 3 PageMask Register Application Note U10710EJ5VOAN 107 VOLUME 3 PROGRAMMING For example the program that sets 4K page x 2 1K page x 2 for the Vn4100 Series from the virtual address 0x0000 0000 to the physical address 0x0 0001 0000 is as follows 1 Initial setting 2 struct Elo 3 unsigned int Hi EntryHi register 4 unsigned int Lo0 EntryLoO register 5 unsigned int Lol EntryLol register 6 unsigned int Mask PageMask register 7 13 8 struct tlb tlbwrite l int struct tlb
27. EntryHi Place the higher 7 bits of this virtual address to PTEBase in the Context register in the CPO Use 0 for the lower bits of these address 112 Application Note U10710EJ5VOAN CHAPTER 3 TLB The following shows the format of the Context register in 32 bit mode Figure 3 7 Context Register In 32 Bit Mode a VR4100 Series 25 24 4 3 0 4 21 b VR4300 Series Vr5000 Series Vr5432 VR5500 and Vn10000 Series 31 23 22 4 3 0 9 4 19 Each bit of the Context register is described below PTEBase Base address of page table entry BadVPN2 Value of the page number of the virtual address whose TLB translation is invalid divided by 2 set by hardware when an exception occurs 0 This is reserved Write a zero here A zero will be returned when this area is read In the state of Figure 3 6 if the Context register and TLB table are set the table that is to be placed in the TLB entry can be referenced by referencing the contents of the Context register and its address when a TLB refill exception occurs ASID can be supported by creating a TLB entry table for each ASID and rewriting the PTEBase area of the Context register The information thus acquired to be written in the TLB entry is written in the TLB entry using the TLBWR instruction Application Note U10710EJ5VOAN 113 VOLUME 3 PROGRAMMING The following shows the program that performs table reference and rewriting This function
28. Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC do Brasil S A Electron Devices Division Guarulhos SP Brasil Tel 11 6462 6810 Fax 11 6462 6829 J01 2 Major Revisions in This Edition Throughout Addition and deletion of target devices Addition Vr4121 VR4122 Vr4181 VaA305 Vr4310 VR5000A Vn5432 VR5500 under development VR10000 VR12000 VR12000A Deletion Vr4100 Vr4200 Throughout Change addition and deletion of descriptions brought about by addition and deletion of target devices VOLUME 1 OUTLINE OF TOOLS p 17 VOLUME 2 Vr SERIES ARCHITECTURE VOLUME 2 Va SERIES ARCHITECTURE Change of composition of whole volume deletion of descriptions p 35 Addition and deletion of products in Table 1 3 Difference in Cache Depending on Processor pp 39 40 Addition of description in 1 3 2 1 Control Status register FCR31 pp 41 to 43 Change and addition of description in 2 1 Pipeline Stage pp 49 to 54 Addition of description in 3 1 Primary Cache p 50 Addition and deletion of products in Table 3 1 Primary Cache Size Line Size and Index pp 55 56 Addition of description in 3 2 Secondary Cache pp 57 to 59 pp 59 60 p 61 p 63 pp 64 to 70 Change of Table 3 3 Cache Instruction s Suboperation Code op for each product Addition of description in 3 3 Cache Instructions Addition and deletion of products in Table 4 1 Physical Address Space Deletion of description in 4 2 TLB Entri
29. Vr4100 Series Virtual address Physical address 0x0001 07FF Y Bag 0x0001 0000 1 K page x 2 0x0000 O7FF 0x0000 0000 b VR4300 Series Vr5000 Series Vr5432 VR5500 and Vn10000 Series Virtual address Physical address 0x0001 1FFFT gt 4K page x 2 0x0001 0000 0x0000 1FFF s y 0x0000 0000 Application Note U10710EJ5VOAN 109 VOLUME 3 PROGRAMMING 3 4 TLB Initialization Initializing the TLB invalidates all TLB entries and sets all virtual addresses within the entries to the TLB mapping invalid position This program sets all TLB entries to the Vr Series kernel mode 32 bit address ksegO a TLB mapping disabled area Note however that the initial value of the CPO registers used by the TLB is not guaranteed after a reset When using these registers set the values to the registers before use In the program shown below the CPO registers used by the tlbwrite function can be used as is because they are used after the values are set The following program initializes the TLB of the Vr Series This program uses the tlowrite function created as described in 3 2 Entry Write When linking this program link it together with the object file that contains the tlowrite function In this program all the TLB entries are set to the 32 bit kernel mode address ksegO a TLB mapping disabled area 1 TLB initialization 2 Initial setting 3 struct tlb 4 unsigned int Hi
30. address specified for cache block is not included and if the cache being used is the data cache and the block status is Dirty writeback to the main memory is performed Cache Barrier operation This operation spends time executing one instruction without affecting the cache contents Index Data operation This operation executes an instruction for the TagHi TagLo and ECC registers of the CPO For the detailed operations of each cache operation refer to the CACHE instructions in the CPU instruction set in the user s manual of each product 60 Application Note U10710EJ5VOAN CHAPTER 4 TLB In the MIPS architecture all the accesses from a program to the memory are performed in the virtual memory The TLB Translation Lookaside Buffer High speed translation buffer system translates virtual addresses to physical addresses Vr Series processors are provided with a memory management unit MMU that utilizes the TLB The memory management system increases the CPU s available address space by translating large virtual memory space into physical addresses The physical address spaces of each Vr Series product are as follows Table 4 1 Physical Address Space In 32 bit mode virtual addresses are 32 bits in width and the maximum user area is 2 GB 2 bytes The virtual address space is expanded according to the address space ID ASID Using ASID reduces the number of TLB flushes during context switching The ASID area is an 8 bit
31. an on chip TLB for translating virtual addresses into physical addresses This on chip TLB uses fully associative memory and each entry is mapped into even odd page pairs The size of these pages can be specified separately for each entry Figure 4 2 illustrates an example where each page occupies 4 KB Figure 4 2 TLB Translation Virtual address Physical address TLB translation PFN VPN2 EntryLo1 EntryHi PEN EntryLoO 2 pages Even page Application Note U10710EJ5VOAN 63 VOLUME 2 Vr SERIES ARCHITECTURE 4 3 TLB Entry Register This section describes the TLB entry registers in CPO used to manipulate the TLB 4 3 1 PageMask register Figure 4 3 PageMask Register a Vr4100 Series 19 18 13 b VR4300 Series Vr5000 Series Vr5432 Vn10000 Series 25 24 13 12 MASK 12 c VR5500 13 12 18 Each bit of the PageMask register is described below MASK This is a page comparison mask It determines the virtual page size of the corresponding entry 0 This is reserved Write a zero here A zero will be returned when this area is read 64 Application Note U10710EJ5VOAN CHAPTER 4 TLB The values shown in the table below can be set in the MASK area Table 4 2 Mask Values and Page Size a Vn4100 Series Page Size Cw loole pote pote po aw olololo olo 1 1 pee o o fo o 11 1 ka o ajai aea b VR4300 Series VR5000 Series Vr5432 VR10000 Series
32. before using the cache When changing the block size of the cache perform writeback to memory before changing If the block size is changed re initialize the cache For details of these registers refer to VOLUME 2 Figures 1 7 to 1 9 5 1 3 FPU CP1 registers x The Vn4300 Series VR5000 Series VR5432 VR5500 and Vr10000 Series include a Floating Point Unit coprocessor FPU The FPU includes one set of floating point registers FGR and two control registers Control Status register FCR31 Implementation Revision register FCRO Of these only the Control Status register requires initial setting The following shows an example of initializing the Control Status register as part of FPU initialization Initialization of FPU register Control Status register FS 0 C 0 Cause bit 0x00 Enable bit 0x00 Flag bit 0x00 RM 00 li S8 0x00000000 ctci1 o8 31 5 1 4 HALTimer shut down In the Vr4100 Series when HALTimer is not released by software within approx 4 seconds after RTC reset the reset status is restored Be sure to release HALTimer set the HALTIMERRST bit of the PMUCNTREG register to 1 when initialization has been correctly processed 5 1 5 Initialization of cache and TLB Separately from the CPU initialization it is necessary to individually initialize the cache and TLB For details refer to CHAPTER 2 CACHE and CHAPTER 3 TLB 122 Application Note U10710EJ5VOAN CHAPTER 5 CPU INITIALIZATION
33. change VR5000 Series only 1 Uses ECC register contents Exception occurrence due to cache parity error or ECC error VR5000 Series and Vn10000 Series only 1 Disable O gt Enable Application Note U10710EJ5VOAN CHAPTER 1 OUTLINE 1 2 2 Memory management 1 TLB Figure 1 10 shows the virtual memory address space for a Vn Series processor in 32 bit kernel mode operation Figure 1 10 Virtual Memory Address Space OxFFFF FFFF 0 5 GB with TLB mapping OxE000 0000 OxDFFF FFFF 0 5 GB with TLB mapping 0xC000 0000 OxBFFF FFFF 0 5 GB without TLB mapping OxA000 0000 Non cacheable Ox9FFF FFFF 0 5 GB without TLB mapping 0x8000 0000 Ox7FFF FFFF 2 GB with TLB mapping 0x0000 0000 Each segment is described below kuseg kuseg is accessed via the TLB ksegO ksegO is accessed without using the TLB Instead the address that is the virtual address minus 0x8000 0000 is selected as the physical address Cache usage and coherency are controlled by the KO area in the Config register kseg1 kseg1 is accessed without using the TLB Instead the address that is the virtual address minus OxA000 0000 is selected as the physical address This space is also accessed without using a cache The physical memory or the memory mapped l O device register is directly accessed ksseg ksseg is accessed via the TLB kseg3 kseg3 is accessed via the TLB The virtual address in the memory area that is accessed via the TLB
34. exception occurs Refer to VOLUME 2 Table 5 3 Status When Exception Occurs However soft reset and NMI cannot be discriminated only from the Status register in the Vr4300 Series VR5000 Series Vr5432 and Vr5500 To discriminate between soft reset and NMI information with which the CPU can determine NMI occurrence must be left by means of hardware In the Vr4100 Series soft reset does not occur Therefore manipulation for discrimination is not necessary In the VR10000 Series since the Status register contains an NMI bit soft reset and NMI occurrence can be discriminated by referencing this bit 1 Discrimination program The following shows a program that discriminates between cold resets and soft reset NMI exceptions set noreorder globl Reset ent Reset mfcO S26 12 li 27 0x0010 and 27 26 27 bne 27 0 NMI exception Add processing for cold reset exception 11 NMI exception 12 Add processing for soft reset NMI exception Allocate these to exception handler addresses by section specification etc Application Note U10710EJ5VOAN 115 VOLUME 3 PROGRAMMING 4 1 2 Other exceptions This section describes the method and program for discriminating between types of exceptions that utilize the exception vector OxBFCO 0380 Some of the exceptions utilizing the exception vector OxBFCO 0380 cannot be used depending on the CPU For details refer to VOLUME 2 CHAPTER 5 EXCEPTIONS To discriminat
35. incorporation of these circuits software and information in the design of customer s equipment shall be done under the full responsibility of customer NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC semiconductor products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to semiconductor products developed based on a customer designated quality assurance program for a specific application The recommended applications of a semiconductor product depend on its quality grade as indicated below Customers must check the quality grade of each semiconductor product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and
36. requires the contents of the Context register for argument 1 and the contents of the Random register for argument 2 In this case the Random register is specified for argument 2 because the tlowrite function created as described in 3 2 Entry Write is used However argument 2 is normally not required if it is changed to use TLBWR instruction TLB rewrite Initial setting struct tib unsigned int Hi EntryHi register unsigned int Lo0 EntryLo0 register unsigned int Lol EntryLol register 0 A U d W N F unsigned int Mask PageMask register struct tlb tlbwritel int struct tlb Ys void TLB swap unsigned int context unsigned int random struct tlb Tlb Pointer to structure Tib struct tlb context tlbwrite random Tib This method however requires a large memory to store TLB tables Therefore measures to save memory such as modifying the Context register are necessary Note A 4 MB memory space is required for one process ASID that uses kuseg only 114 Application Note U10710EJ5VOAN CHAPTER 4 EXCEPTIONS 4 1 Discriminating Between Exceptions This section describes methods for discriminating between exceptions when several exceptions are using the same exception vector 4 1 1 Cold reset soft reset and NMI exceptions Each cold reset soft reset and NMI exception can be discriminated by referring to the SR bit of the Status register that is set when an
37. the memory address is referred to and the cache line is determined The V bit is referred to for the validity of the cache line If the cache line is valid a physical address is created from the higher virtual address by TLB conversion and compared to the tag part in the cache line If the tag and the physical address match it becomes a cache hit Figure 3 1 Referencing Primary Cache Virtual address Physical Physical Cache memory Match check Application Note U10710EJ5VOAN 49 VOLUME 2 Vr SERIES ARCHITECTURE The following shows the capacity line block size and bits used in the index of the primary cache in the Vn Series Table 3 1 Primary Cache Size Line Size and Index x The format of the primary cache of each processor is shown below For the primary cache of the Vr10000 Series refer to VR10000 Series User s Manual 50 Application Note U10710EJ5VOAN CHAPTER 3 CACHE 3 1 1 Vn4100 Series The format of the Vr4100 Series on chip cache line is described below Figure 3 2 Vr4100 Series On Chip Cache Line a Instruction cache line Each bit of the cache line is described below V Valid bit W Writeback bit D Dirty bit PTag Physical tag bits 31 to 10 of the physical address Data Cache data Application Note U10710EJ5VOAN 51 VOLUME 2 Vr SERIES ARCHITECTURE 3 1 2 Vr4300 Series The format of the Vr4300 Series on chip cache line is described below
38. 0 TS 0 SR 0GH 0 GR 0DE 0 de ER FX 0 SX 07UX 07KSU 0 ERL 0 EXL 0 IE 0 mtco S8 12 WatchLo register li 8 0x00000000 set PAddr0 0 R 0 W 0 mtco 8 18 Compare register li Se ON EE mtco o8 SEL initialize TLB li 8 0xa0000000 base addr of VPN2 11 S9 32 number of TLB entries 11 S10 0x0800 VPN2 increment Application Note U10710EJ5VOAN 123 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 124 eg clear mtco addu mtco mtco mtco addiu mtco nop nop tlbwi bgtz nop 58 58 50 50 50 59 59 59 VOLUME 3 PROGRAMMING 10 8 2 3 SO 59 el 0 10 celp clear initialize cache mtco O i cache La 58 aL 59 cache clear cache 0x00 addiu 9 bgtz 9 addiu 8 d cache La 58 L 59 deache clear cache 0x09 addiu 9 bgtz 59 addiu 8 28 0x80000000 0x4000 8 S9 0x10 sicache Clear 8 0x10 0x80000000 0x2000 8 9 0x10 H H saCacne clear 8 Ox10 EntryHi EntryLoO EntryLol PageMask Index Write Indexed TLB Entry TagLo vaddr 1 cache size 16KB Index Invalidate increment of vaddr d cache size line size 8KB Index Store Tag K increment of line size initialize periph
39. 010000 parity or ECC to cause exceptions Index Invalidate I 0x0 0 0 Index Writeback Inv D 0x1 0 1 Index Writeback Inv S 0x3 0 3 Index Load Tag I 0x4 1 0 Index Load Tag D Ox5 1 1 Index Load Tag S Ox7 1 3 Index Store Tag I 0x8 2 0 Index Store Tag D Ox9 2 1 Index Store Tag S Oxb 2 3 Hit Invalidate I Ox10 4 0 Hit Invalidate D Ox11 4 1 Hit Invalidate S Ox13 4 3 Fill T Oxia 7 5 0 Hit Writeback Inv D Ox15 5 1 Hit Writeback Inv S Ox17 5 3 Index Load Data I 0x18 6 0 Index Load Data D 0x19 6 1 Index Load Data S Oxlb 6 3 Index Store Data I Oxlc 7 0 Index Store Data D 0x1d 7 1 Index Store Data S Ox1f 7 3 TagHi P PMod Neither Refill 0x20000000 Neither Refill or Written 8 RK EATER ck ke kc ck ke ce ck ck cce ck kc ck ck cce ck cec kc kc ck kc k AA Main program ok HE IE ck kc ck coke ke ck kc ck kc ck ck kc ck ccc ck kc ck cc ERA EEE kckck ck ckckck ck ckckckckok ck ckckck ck kck ck ck ck ck k kk i ESILE set noat Set noreorder globl init cache ent init cache init cache KK KK KK KK KK KARA kkk kkk RARA kkk kkk kkk kkk kkk kkk ck ck ck ckckck ck ck ck k Initialize L1 and L2 cache kk HE HERE kc ck coke ck ke ec ck coke ck ck cce ck cec ck cce ck cec ck kc I ck kc ck ckck ck ckckck SS A Status register setting mfcO 11 CO SR li 12 SR DE Or S13 12 SIL
40. 0A uPD30710A Vr4310 uPD30210 e VR5000 Series Note Under development Vr5000 uPD30500 VR5000A uPD30500A This manual is designed to be used as a handbook for developing application systems using the products listed above This manual consists of the following subjects e Outline of tools e Vn Series architecture e Programming It is assumed that the reader of this manual has general knowledge of microcontrollers the C programming language and assembler language The program source code shown in this manual is for reference only and is not intended for use in mass production design For the hardware functions of each product Refer to the Hardware User s Manual or User s Manual of each product For the instruction functions of each product Refer to the Instruction User s Manual Architecture User s Manual or User s Manual Application Note U10710EJ5VOAN 7 Conventions Related Documents Data significance Higher digits on the left and lower digits on the right Active low representation xxx after pin or signal name Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numerical representation Binary xxxx or xxxB Decimal xxxxx Hexadecimal Oxxxxx Suffix representing an exponent of 2 in address space or memory capacity K Kilo 2 1 024 M Mega 2 1 024 G Giga 2 1 024 T Tera 2 1 02
41. 1 24 23 22 21 20 19 18 17 16 o T TT Te T ce TE 1 1 1 1 1 1 1 1 1 b VR4122 24 23 22 21 20 19 18 17 16 9 9 w o sa o o c E 1 1 1 1 1 1 1 1 1 c Vr4300 Series 24 23 22 21 20 19 18 17 16 ms o j Sv T SR o om c E 1 1 1 1 1 1 1 1 1 d VR5000 Series 24 23 22 21 20 19 18 17 16 9 j o j 8v o sa o 0 c ce 1 1 1 1 1 1 1 1 1 e Vr5432 Vn5500 24 23 22 21 20 19 18 17 16 wwe o sw ts sa Je ce oe 1 1 1 1 1 1 1 1 1 f VR10000 24 23 22 21 20 19 18 17 16 OT Te Jos sa mu om ce oe 1 1 1 1 1 1 1 1 1 g Vr12000 Vr12000A 24 23 22 21 20 19 18 17 16 oso o ee s sa m cn ce oe 1 1 1 1 1 1 1 1 1 Application Note U10710EJ5VOAN 31 32 VOLUME 2 Vr SERIES ARCHITECTURE The following describes the bits especially important in the DS area BEV TS SR CH CE DE Specifies the base address of the TLB refill exception vector and general purpose exception vector 0 gt Normal 1 gt Boot strap Occurrence of TLB shut down O gt Does not occur 1 Occurs Occurrence of soft reset exception or NMI exception 1 Occurs O gt Does not occur e Vn4100 Series VR4300 Series VR5000 Series Vr5432 and VR5500 Condition bit of the CPO 1 True 0 gt False e VR10000 Series Hit of Hit Invalidate or Hit Writeback Invalidate operation for secondary cache processed last 1 gt Hit tag match valid status 0 gt Miss Cache check bit set
42. 13 add 15 0 0 amtel 0 SEL4 add 16 0 50 dmtcl 0 Sf15 add 17 0 0 dmtcal 0 Sf16 add 18 0 0 dicli 0 f17 add 19 0 0 dmtcl 0 Sf18 add 20 0 0 dmtcal 0 Sf19 add 21 0 0 dmtcal 0 Sf20 ada 9224 SO 50 dmeci 0 f21 add 23 507 50 ameci 0 SE22 add 24 0 0 dmtcal SO Sf23 add 25 0 0 dmtcl 0 Si24 add 26 0 0 dmtcl SO S 25 add 527 0 90 dmtcal 0 Sf26 add 28 0 50 amtel 0 927 add 29 0 0 dmtcal 0 Sf28 add 30 0 0 dmtcal SO Sf29 add 31 0 0 dmtcal 0 Sf30 dmtc1 0 St3l mult 1 2 for hi lo registers Application Note U10710EJ5VOAN 137 VOLUME 3 PROGRAMMING Change Prediction Mode to BP All Taken before using branches li 8 BP All Taken lt lt Diag BPModeShf EEES SS kkk kkk kkk kk kk kkk kk Initialize Branch Prediction Table using BPT line init E SS li 9 255 d number of lines to initialize in BPT loop SE 900 9 36 Gri 10 S50 Init BPT 00 or 10 8 MUCO 10 CO Diag bgtz 99 BPT loop addi 9 1 Ark kkkkkkkk kkk kkk kk kkk kkk kkk kkk kk kkk kkk kkk kkk kk kkk kkk kk kk kkk kkk k kkk kk Initialize TLB using tlbwi instruction all 64 entries invalid kk HE HERE kc ck ke coke ck kc ck ce ck ck kc ck kc EEE EEE E EEE RAEE EE EEA RAEE EE E ck eK kk li 8 63 Index register mte 0 00 Entry mtcO 0 CO EntryLoO mtcO 0 CO EntryLol tlb loop mtcO 8 CO Index nop tlbwi bne 8 90 tl
43. 2 Masks external normal interrupt Int 4 0 and external write request IM 1 0 Masks software interrupt e VR5432 IM7 Masks timer interrupt IM 6 2 Masks external normal interrupt Int 4 0 and external write request IM 1 0 Masks software interrupt e VR5500 IM7 Masks timer interrupt or external normal interrupt Int5 IM 6 2 Masks external normal interrupt Int 4 0 and external write request IM 1 0 Masks software interrupt Application Note U10710EJ5VOAN 29 30 VOLUME 2 Vr SERIES ARCHITECTURE e VR10000 Series IM7 Masks timer interrupt IM 6 2 Masks external normal interrupt external interrupt request IM 1 0 Masks software interrupt KX Enables 64 bit addressing in the kernel mode In the kernel mode 64 bit operation is always enabled 1 64 bits 0 gt 32 bits SX Enables 64 bit addressing and 64 bit operation in the supervisor mode 1 gt 64 bits 0 gt 32 bits UX Enables 64 bit addressing and 64 bit operation in the user mode 1 64 bits 0 gt 32 bits KSU Operating mode 10 gt User 01 gt Supervisor 00 gt Kernel ERL Error level 1 gt Error 0 gt Normal EXL Exception level 1 gt Exception 0 gt Normal IE Enables interrupt 1 gt Enable 0 gt Disable The details of the DS self diagnostic status area are shown below All bits except the TS bit can be read written Application Note U10710EJ5VOAN CHAPTER 1 OUTLINE Figure 1 9 Self Diagnostic Status DS Area a Vr4121 Vn418
44. 2 8 Loading Delay a Single way pipeline x oo we EX WB A Loading Y_ delay slot Instruction DC WB using target Loading delay b 2 way superscalar pipeline A Loading _Y delay slot Instruction using target Loading delay If an instruction using the data loaded during a loading delay is allocated the CPU detects this and stalls the pipeline until data loading is complete There is no need to be aware of loading delays that occur in the assembler because they are not treated as errors However from the viewpoint of performance enhancement it is recommended that instructions be scheduled taking loading delay in consideration Application Note U10710EJ5VOAN 47 L VOLUME 2 Vr SERIES ARCHITECTURE 2 4 Bypassing Data and conditions generated at the EX DC and WB stages of the pipeline are able to be used at the EX stage of the next instruction via a bypass data path If the pipeline is bypassed it is not necessary to wait for the data and conditions to be written to a register file when the WB stage is ended so the instruction of the EX stage can be continued For example the following assembler program is created lui 1 0x8000 ori S1 1 0x0000 Writing to register 1 in the first instruction is completed normally at the WB stage If the pipeline cannot be bypassed the RF stage of the second instruction must wait for the end o
45. 4 P Peta 2 1 024 E Exa 2 1 024 The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such e User s Manual e Data Sheet UuPD30121 Vr4121 Data Sheet U14691E uPD30122 Vn4122 Data Sheet To be prepared uPD30181 Vr4181 Data Sheet U14273E uPD30200 30210 VR4300 Vr4305 Vn4310 Data Sheet U10116E uPD30500 30500A Vr5000 VR5000A Data Sheet U12031E uPD30541 Vr5432 Data Sheet U13504E uPD30550 VR5500 Data Sheet To be prepared uPD30700 30710 VR10000 Vr12000 Data Sheet U12703E Application Note U10710EJ5VOAN CONTENTS VOLUME 1 OUTEINE OF TOO Simca 16 CHAPTER 1 PROGRAMMING TOOLS iciii nisiainriinininninacionacinnn nianacinnaanncnan iaia 17 VOLUME 2 VR SERIES ARCHITECTURE cirio 18 CHAPTER T OUTLINE aria 19 bi e CN GE 19 O e 19 Ne le sirio dra 20 EE ME Ted 22 tias e EE 24 1 2 ioleldolei l Liege 25 UNE SCIRE ETE UI 25 22 Memory E Le EE ER beo ECPN E 36 EE e EE 36 SDA Elba 37 Mow A RA rai 37 Ee E EN 37 CHAPTEH 2 PIPELINE ee 41 21 Pipeline e ua meets 41 2 2 e E ei 44 23 Della 46 Zion SBARCHI ASIAN AR RPS PPR OPR POE ee SERALI eer R E o CI 46 2302 koadng dolay R A AAA AR 47 KS MESI It A e E 48 GHAPTER 3 CACHE conidios 49 3 1 Primary Gace eR 49 SEE IOSEPH EE 51 e Ne430 Series ella 52 3 3 A A EE M 53 S YRS432 and EEN 54 Application Note U10710EJ5VOAN 9 32 Sec
46. 7 16 15 14 13 12 11 6 5 4 31 30 28 27 24 23 16 15 14 4 3 2 0 CIT EE 1 3 4 7 1 11 1 3 d VR5000 Series 31 30 2827 24 23 22 21 2019 18 17 12 11 ol ee es oo se ev EC e Vn5432 28 27 24 23 22 21 3 2 0 EEN 110110 SCH 110011011110 12 3 f VR5500 28 27 24 23 22 21 20 19 18 1716 15 3 2 0 fol ee Ten few ee 110011011110 12 3 Application Note U10710EJ5VOAN x X CHAPTER 1 OUTLINE Figure 1 7 Config Register 2 2 g Vr10000 29 28 26 25 1918 16 15 13 12 h Vr12000 Vr12000A 20 28 26 25 24 232221 19 18 16 15 13 12 Lx Teo re co se eee ee mene The following describes the bits especially important in the Config register IS Instruction streaming function setting Vr4122 only EP Transfer data pattern display Can be set by software only in the Vr4300 Series and Vr5432 M16 Display of MIPS16 ISA mode enable Vn4100 Series only BP Branch prediction setting Vn4122 only BE Endian display Can be set by software only in the Vr4300 Series IB Size of primary instruction cache line O gt 16 bytes Reserved in the Vr5000 Series 1 gt 32 bytes DB Size of primary data cache line O gt 16 bytes Reserved in the VR5000 Series 1 gt 32 bytes KO Coherency algorithm of ksegO In the Vr Series CPUs areas other than those described below have fixed values or are set with hardware after reset and become read only from software The following bits can be read written by software and be
47. AN CHAPTER 4 TLB 4 4 TLB Instructions TLB instructions are assembler instructions for the Vr Series processors that are used to control the TLB 1 TLBP Translation Lookaside Buffer Probe The TLB number that matches the EntryHi register is loaded to the Index register If the TLB entry does not match the highest bit in the Index register is set The operation of any load store instruction that comes immediately after the TLBP instruction is undefined The operation is also undefined when there is more than one matching TLB entry Figure 4 10 TLBP Instruction Retrieves entry PageMask Loads entry number EntryHi n Be EntryLo1 E nes EntryLoO 2 TLBR Translation Lookaside Buffer Read The contents of the TLB entry that is indicated by the Index register contents are written to the EntryHi EntryLoO EntryLo1 and PageMask registers Figure 4 11 TLBR Instruction Loads data PageMask Specifies entry EntryHi Index H TLB entry EntryLo1 EntryLoO Application Note U10710EJ5VOAN T1 VOLUME 2 Vr SERIES ARCHITECTURE 3 TLBWI Translation Lookaside Buffer Write Index The contents of the EntryHi EntryLo0 EntryLo1 and PageMask registers are written to the TLB entry that is indicated by the Index register contents Figure 4 12 TLBWI Instruction Stores data PageMask Specifies entry EntryHi Index n TLB entry
48. Application Note NEC VR Series 64 32 Bit Microprocessor Programming Guide Target Devices VR4100 Series VR4300 Series VR5000 Series VR5432 VR5500 VR10000 Series Document No U10710EJ5VOANOO 5th edition Date Published November 2001 N CP K NEC Corporation 1996 2001 Printed in Japan MEMO 2 Application Note U10710EJ5VOAN NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible t
49. C CPU General Cache Memory Cold reset feta E e 1 0 A e x x ee e e 09 Note Vr4300 Series and Vr10000 Series only Remarks 1 The Status register and ErrorEPC register are coprocessor 0 registers 2 0 A zero is set when an exception occurs 1 A one is set when an exception occurs The status prior to exception is saved A The address where exception occurred is saved x Undefined Application Note U10710EJ5VOAN 75 VOLUME 2 Vr SERIES ARCHITECTURE 5 4 2 General purpose exceptions In the Vr Series CPU more than one exception shares the same vector Of these general purpose exception vectors use the address OxBFCO 0380 BEV 1 or 0x8000 0180 BEV 0 To discriminate exceptions that utilize a general purpose exception vector refer to the exception code area ExcCode of the coprocessor 0 Cause register and perform processing for each exception according to the ExcCode value The following shows the contents of the Cause register Figure 5 1 Cause Register 31 30 29 28 27 1 5 2 Each bit of the Cause register is described below BD Indicates whether the exception that occurred last has been executed in the branching delay slot 1 gt In the delay slot 0 gt Normal CE Indicates the number of the coprocessor in which the coprocessor disable exception occurred When this exception has not occurred this bit becomes undefined IP Indicates the pending interrupt 1
50. CHAPTER 1 OUTLINE 1 3 FPU The floating point unit FPU of the Vn Series operates as a coprocessor and expands the CPU instruction set to execute the floating point The FPU complies with ANSI IEEE Standard 754 1985 IEEE Binary Floating Point Arithmetic Specifications An FPU is not provided in the VR4100 Series 1 3 1 Instructions All the FPU instructions are 32 bits in length and allocated to word boundaries FPU instructions are categorized as follows e Load store transfer instructions Load store transfer instructions perform data transfer between the general purpose registers of FPU and the CPU or memory e Conversion instructions Conversion instructions perform data conversion e Arithmetic instructions Arithmetic instructions execute operations for floating point values in the FPU register e Comparison instructions Comparison instructions perform comparison in the FPU register and set the result to the C CC bit of FCR31 e FPU conditional branch instructions FPU conditional branch instructions execute a branch to a specified target if the indicated coprocessor condition is true 1 3 2 Registers There are three methods to use the FPU general purpose registers 1 The thirty two general purpose registers are 32 bits in length if the FR bit of the CPO Status register is O and 64 bits in length if itis 1 The CPU accesses FGR with load store transfer instructions 2 If the FR bit of the Status register is O sixteen 64 bit r
51. EntryLol reg S5 5 PageMask reg 0 Index reg S10 EntryHi reg SO S25 ELD So as OX2000 init54 x 5 2 7 VR5500 noreorder init 55 init 55 init 55 lui r30 0x6401 Enable CP1 CP2 amp FR amp Disable Parity mtco F30 CD SR Set Status Register mtco r0 CO WatchLo Disable all Watch Exceptions mfcO D24 00 COntig I ES y 0xtOStrtrs and r3 f3 EL li r4 0x3 add r3 r3 r4 mtco ES CO Config tel CI SR Clear CP1 Status Register mtco ro CO TagLo mtco ro CO Tagli li rl 0x80003FE0 Initialize Index li r2 0x80000000 Define End Condition ICInvalLoop cache Index Store Tag l 0x0000 r1 cache Index Store Tag I 0x0001 r1 bne rl r2 ICInvalLoop addiu rl r1 0x0020 li rl 0x80003FE0 t Initialize Index li r2 0x80000000 Define End Condition DCInvalLoop 134 Application Note U10710EJ5VOAN CHAPTER 5 CPU INITIALIZATION cache Index Store Tag D 0x0000 r1 cache Index Store Tag D 0x0001 rl bne rl r2 DCInvalLoop addiu rl r1 0x0020 TLB initialize mtco CO PageMask Set Page size to 4K mtco CO EntryLoO Clear EntryLo G Bit in particular mtco CO EntryLol Clear EntryLo G Bit in particular by Ox2F Initialize Index La OXABC5E000 Initialize VPN TLBInvalLoop mtco CO Index dmtco CO EntryHi addiu r1 0x0001 addiu r2 0x2000 bgez TLBInvalLoop tlbwi end init55 5 2 8 Vn10000 Series define define define define define define
52. Figure 3 3 Vr4300 Series On Chip Cache Line a Instruction cache line Each bit of the cache line is described below V Valid bit D Dirty bit PTag Physical tag bits 31 to 12 of the physical address Data Cache data 52 Application Note U10710EJ5VOAN CHAPTER 3 CACHE 3 1 3 VR5000 Series The format of the VR5000 Series on chip cache line is described below Figure 3 4 VR5000 Series Primary Cache Line a Instruction cache line 30 29 28 27 24 23 0 31 PT F Poe coro 1 1 2 4 24 71 64 63 b Data cache line 27 26 25 24 23 0 Cele rsa m 2 24 Each bit of the cache line is described below P Even parity of PTag F Fill bit PState State of primary cache ICDEC Instruction cache predecode bit PTag Physical tag bits 31 to 12 of the physical address DataP Even parity of Data Data Cache data Application Note U10710EJ5VOAN 53 VOLUME 2 Vr SERIES ARCHITECTURE x 3 1 4 Vr5432 and Vn5500 The format of the Vr5432 and Vr5500 on chip cache lines is described below Figure 3 5 Vr5432 and VR5500 On Chip Cache Lines a Instruction cache line 27 4 3 2 1 0 A eso O 24 1 1 1 1 64 63 0 b Data cache line 27 4 3 2 1 0 A Tas 6363635 tivjeje 24 1 1 1 1 64 63 71 0 Each bit of the cache line is described below Tag DTag Physical tag bits 31 to 12 of the physical address L Lock bit V Valid bit U Unused bit D Dirt
53. Hi register 5 gt cp0 10 move S8 0 lw 59 055 mtco S8 10 structure to EntryLo0 register 5 4 gt cp0 2 move S8 SO lw 8 4 5 mtco 8 2 structure to EntryLol register 5 8 gt cp0 3 move S8 0 lw 8 8 95 mtco S8 3 structure to PageMask register 5 12 gt cp0 5 move S8 0 lw 8 12 5 mfcO 8 5 nop TLB entry to each TLB entry register of CPO tlbwi nop Restore Index register mtco S15 SU Create return value of function move 2 5 nop Ju Sra nop end tlbwrite Data can be written to the TLB entry when this function is called from a C language program The function s initial setting is made in lines 3 to 8 of this function In lines 9 to 11 the second argument specifying the entry number of the TLB that is passed to this function is copied to the Index register of the CPO register In lines 12 to 28 data is copied from the structure pointers passed by the first argument of the function to the each entry register In lines 30 and 31 data is written from the TLB entry registers EntryHi EntryLoO EntryLo1 and PageMask to the TLB entry indicated by the Index register with the TLBWI instruction The pointer to the structure is then set as the return value of the function 106 Application Note U10710EJ5VOAN CHAPTER 3 TLB 3 3 TLB Settings This section describes the creation in C language of a function to set the TLB using the functions created as described in 3 1
54. I instruction Although the Index area holds 6 bit information only the lower 5 bits are used in the Vr4100 Series and Vr4300 Series Figure 4 6 Index Register 68 Each bit of the Index register is described below P Indicates success failure of TLBP instruction O gt Success of probe instruction 1 gt Failure of probe instruction Index Specifies the index to the TLB entries that are the targets of the TLBR instruction and TLBWI instruction 0 This is reserved Write a zero here A zero will be returned when this area is read Application Note U10710EJ5VOAN CHAPTER 4 TLB 2 Random register The Random register is a read only register The lower 6 bits of this register are used for referencing TLB entries Although the Random area holds 6 bit information only the lower 5 bits are used in the Vr4100 Series and Vr4300 Series This register is decremented each time an instruction is executed The available value range of this register is as follows e The lower limit is indicated by the Wired register e The higher limit is the number of TLB entries 31 in the Vr4100 Series and Vr4300 Series 47 in the VR5000 Series Vr5432 and Vr5500 and 63 in the Vn10000 Series The Random register indicates the TLB entries that are the targets of the TLBWR instruction The Random register is set to the higher limit value upon cold reset It is also reset to the higher limit value when writing is performed to the Wired register Rando
55. Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Way 0 Way 1 Way 0 Way 1 Way 0 Way 1 Way 0 Way 1 Way 0 Way 1 Way 0 Way 1 Way 0 Way 1 Way 0 Way 1 Index Store Tag Way 0 Index Store Tag Way 1 HE E E UE UE UE EEE HH HH Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Index Store Data Application Note U10710EJ5VOAN _S _S _S _S _S S _S _S _S _S _S _S _S _S _S Way 0 Way 1 Way 0 Way 1 Way 0 Way 1 Way 0 Way 1 Way 0 Way 1 Way 0 Way 1 Way 0 Way 1 Way 0 Way 1 mfco 11 li 12 not 12 and 13 mtcO 13 VOLUME 3 PROGRAMMING CO SR SR DE 12 12 11 DE 0 CO SR end init cache x2 2 Cache Writeback The cache data writeback procedure is described below To writeback the data cache by software use the Hit Write Back operation or Index Write Back operation of the CACHE instruction The Hit Write Back operation is used to perform writeback for a specific area with the virtual address specified In the Hit Write Back ope
56. Index Store Tag TagLo TagHi PErr CACHE Hit OPS Cache line cache line Status CU Status KSU Status EXL Status ERL Coprocessor usability test Instruction fetch EntryHi ASID Status KSU Status EXL Status ERL Status RE Config KO Instruction fetch exception EPC Status Interrupt Cause IP Status IM Status IE Status EXL Status ERL Cause BadVAdar Context XContext B Load store EntryHi ASID Status KSU Status EXL Status ERL Status RE Config KO TLB Config AD Config EP WatchHi WatchLo Load store exception EPC Status Cause BadVaddr Context XContext Status TS 2 Instruction 4 Data E TLB shutdown 88 Application Note U10710EJ5VOAN CHAPTER 1 PIPELINE Table 1 2 CPO Hazards of Vn4300 Series Name Number of Name Number of Hazards Hazards TLBR Index TLB PageMask EntryHi EntryLoO EntryLo1 TLB 5 7 TLBWI Index or Random 5 8 TLBWR PageMask EntryHi EntryLoO EntryLo1 TLBP PageMask EntryHi Index ERET EPC or ErrorEPC Status Status EXL Status ERL n LLbit CACHE Index Store Tag TagLo TagHi ECC 7 2 Coprocessor usability test Status CU Status KSU Status EXL Status ERL Instruction fetch EntryHi ASID Status KSU Status EXL Status ERL Status HE Config KO E Instruction fetch exception EPC Status Cause BadVAddr Context Cause IP Status IM Status IE Status EXL Status ERL Interrupt Load store EntryHi A
57. OLUME 2 Vr SERIES ARCHITECTURE 5 5 Exception Processing This section briefly describes the flow of exception processing taking a general purpose exception as an example 5 5 1 Hardware processing The following shows the contents set by hardware after the exception cause occurs and until the processing moves to the exception vector 78 1 2 3 4 5 Setting register Performs setting of the register set for each exception WatchLo Hi registers etc and the Cause register Checking Status register EXL bit Checks the EXL bit in the Status register and if it is 1 moves to the processing in 4 without setting the EPC register Checking if exception has occurred in branching delay slot Checks whether the exception has occurred in the branching delay slot or not If the exception has occurred in the branching delay slot sets the BD bit of the Cause register and sets the value subtracting 4 from the address where the exception has occurred to the EPC register If the exception has occurred in other than the branching delay slot resets the BD bit of the Cause register and sets the value of the address where the exception occurred to the EPC register Setting Status register EXL bit Sets the EXL bit of the Status register This enables the operation mode of the processor to move to the kernel mode Checking Status register BEV bit Checks the BEV bit of the Status register If the BEV bit is 1 the exce
58. PO register In lines 13 and 14 the TLB entry indicated by the Index register is stored in the TLB entry registers EntryHi EntryLoO EntryLo1 and PageMask with the TLBR instruction In lines 15 onward each entry register is stored from the pointer to the structure passed by the first argument of this function to the structure The pointer to the structure is set as the return value of a function 3 2 Entry Write This section describes the creation of a C language type function tlowrite by the assembler for writing the contents of a TLB entry The following shows the specification of this function struct tlb unsigned int Hi EntryHi register unsigned int Lo0 EntryLo0 register unsigned int Lol EntryLol register unsigned int Mask PageMask register rs struct tlb tlbwritet int struct tib Application Note U10710EJ5VOAN 105 VOLUME 3 PROGRAMMING A function is created with the TLB entry number to be written and the pointer to the structure containing the contents to be written as arguments and the return value is the pointer to the above structure This function appears as follows when created by the assembler globl tlbwrite ent tlbwrite tlbwrite Initial setting assign 0 to the registers used move 8 0 move 15 0 Save index register cp0 0 gt cpu 15 mfco 515 90 nop ond OAO U RK UN F Argument 1 to Index register cpu 4 gt cp0 50 mtco S4 0 nop structure to Entry
59. SID Status KSU Status EXL Config KO Config DB TLB WatchHi WatchLo 4 5 Load store exception EPC Status Cause BadVaddr Context TLB shutdown Status TS J CO Ve Application Note U10710EJ5VOAN VOLUME 3 PROGRAMMING Table 1 3 Instruction Hazards of Vr5000 Series and Vn5432 TLBP PageMask EntryHi contents of TLB ERET EPC ErrorEPC Status L DIV DIVU DDIV DDIVU MULT HI LO MULTU DMULT DMULTU TOO MECO TOO MECO ET Note VR5000 Series only k Table 1 4 Instruction Hazards of Vn5500 Instruction fetch Instruction fetch at address translation address translation EmyHiASID TLB ss ASID TLB Instruction fetch at address error Status KSU Status EXL Status ERL Status KX Status SX detection Status UX Instruction decode at detection of Status XX Status CU Status KSU Status EXL Status ERL coprocessor enable and privileged Status KX Status SX Status UX instruction enable Note A change within the exception handler is surely reflected till the ERET instruction execution 90 Application Note U10710EJ5VOAN CHAPTER 1 PIPELINE 1 2 1 Calculation of CPO hazards The following shows how to calculate CPO hazards taking the Vr4300 Series as an example Example 1 When executing an FPU instruction after setting the CU1 bit of the Status register with the MTCO instruction Referring to the destination CPR rd column of the MTCO instruction the number of hazards is 7 For FP
60. U instructions refer to the coprocessor usability test column The number of hazards of the source Status CU is 2 This is calculated as follows 7 2 1 4 Therefore allocate instructions as follows mtco 12 1 d The value to be set to the Status register is placed in 1 nop nop nop nop cruel 31 2 The contents of 2 are transferred to the Control Status register of the FPU Example 2 When using the TLB entry newly set with the TLBWI instruction for address translation of data access Referring to the destination TLB column of the TLBWI instruction the number of hazards is 8 Refer to the load column for address translation The number of source TLB hazards is 4 This is calculated as follows 8 4 1 3 Therefore allocate instructions as follows 1 0x0 2 Address set to TLB is placed in 2 Example 3 When executing the ERET instruction after changing the EPC register with MTCO Referring to the destination CPR rd column of MTCO instruction the number of hazards is 7 Referring to the source EPC column of the ERET instruction the number of hazards is 4 This is calculated as follows 7 4 1 2 Therefore allocate instructions as follows ST 0x0 2 Address set to TLB is placed in 2 Application Note U10710EJ5VOAN 91 CHAPTER 2 CACHE This chapter describes the method of manipulating the cache of Vr Series processors 2 1 Cache Initialization The following describes the cache
61. U10710EJ5VOAN 3 Exporting this product or equipment that includes this product may require a governmental license from the U S A for some countries because this product utilizes technologies limited by the export control regulations of the U S A The information in this document is current as of October 2001 The information is subject to change without notice For actual design in refer to the latest publications of NEC s data sheets or data books etc for the most up to date specifications of NEC semiconductor products Not all products and or types are available in every country Please check with an NEC sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC NEC assumes no responsibility for any errors that may appear in this document NEC does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The
62. a 122 Initialization of exceptions 118 Weise zi AAA 86 TLB entry T 104 TLB entry replacement 111 EEN 105 TES MERTZ HO prora 110 TEB SCUING aaa 107 Programming tools eee 17 R Seier 69 Register GODIOCOSSOL uie S uta MU HU Mie REI 25 OFO ceana 25 122 p mU M RE 24 121 e 9 37 122 yir QE ERR 64 MOUNdINGIMOdE m 40 S Soft reset exception n 75 115 Status register 000000000 een 28 Self diagnostic status area 31 T TL Bre leticia 33 61 104 Initialization L i 110 122 Jee Le lla 71 Mn dtoducaatach 63 109 A E O 63 Page Zonan 65 pisc ME 104 TLS OIG EE 64 Replacement M T 111 vingt cc 107 BET EP ae etre 112 A a a 105 Translation of address nnoannenennneennnenneenreenr nnen 62 V Virtual addres sissi 34 62 W WIred Tegisterna dina 70 140 Application Note U10710EJ5VOAN Although NEC has taken all possible steps essag e to ensure thatthe documentation supplied to our customers is complete bug free and up to date we readily accept that From errors may occur Despite all the care and precautions we ve taken you may Name encounter problems in the documentation Please complete this form whenever Company T youd like to report errors or suggest
63. a 77 Table No Title Page 1 1 GPO Mazards Of E lOO Series alicell ico 88 1 2 CPO Pazards 0f AR TEE 89 1 3 Instruction Hazards of Vr5000 Series and VobA22 serere serere resur rere reru 90 1 4 Iistuetornlazards OF VRODOU asse Dele en ole ab EDI Mni ros AI en DI De E edo A 90 15 VOLUME 1 OUTLINE OF TOOLS Application Note U10710EJ5VOAN CHAPTER 1 PROGRAMMING TOOLS Tools that support development of Vr Series application programs are released by NEC and other companies e Principal programming tools MULTI Green Hills Software Inc GNU Red Hat Inc e Principal debugging tools PARTNER Kyoto Microcomputer Corporation RTE 1000 TP Midas Lab Co Ltd For details consult NEC sales representative Application Note U10710EJ5VOAN 17 VOLUME 2 Vr SERIES ARCHITECTURE Application Note U10710EJ5VOAN CHAPTER 1 OUTLINE 1 1 CPU The Vr4100 Series VR4300 Series VR5000 Series VR5432 Vr5500 and Vn10000 Series consist of high performance 64 bit microprocessors that adopt the RISC Reduced Instruction Set Computer architecture developed by MIPS The Vn Series instructions are upwardly compatible with the Vr3000 Series so existing applications can be utilized as is Note Under development 1 1 1 Outline The features of the Vr Series processors are shown below Table 1 1 Vr Series Processors Vn4100 Series Vn4121 Incorporates CPU and primary cache includes product sum operation and MIPS16 instruction set
64. ache hit write back unsigned int vaddr Cache block setting define Cache BLK 0x10 When cache block is 16 bytes Cache writeback function void Write Back cache unsigned int s vaddr unsigned int e vaddr for s vaddr lt e vaddr s vaddr Cache BLK cache hit write back s vaddr 2 Index Write Back operation The assembler source list of the function that performs the Index Write Back operation is shown below Cache writeback function Index Write Back operation Description Writeback the data cache block to the index specified by vaddr Format void cache index write back unsigned int vaddr Argument vaddr Cache block to be written back virtual address o NI O U B UN F Return value HE E S HH EEK None globl cache index write back Sent cache index write back cache index write back cache 0x1 0x0 54 Index writeback data cache jr S31 nop end cache index write back Application Note U10710EJ5VOAN 99 VOLUME 3 PROGRAMMING The C source list of the function that performs writeback for all the data on the data cache using the above function is shown below Cache writeback sample program 2 Description Writeback all data caches Format void Write Back cache all void Argument None Oo y O U B UN F Return value None ui External function extern void cache index write back unsigned int vaddr Cache size and block size setting
65. adopted differ depending on the product e Single way pipeline e 2 way superscalar pipeline e 4 way superscalar pipeline 1 Single way pipeline Reads and processes instructions one by one The pipeline of the Vr4100 Series and Vr4300 Series uses this method Figure 1 1 Outline of Single Way Pipeline 5 Stages and Instruction Execution PClock Ed gt a EX Pipeline 20 Application Note U10710EJ5VOAN CHAPTER 1 OUTLINE 2 2 way superscalar pipeline Reads two instructions simultaneously and processes them in parallel The pipeline of the VR5000 Series Vr5432 and Vr5500 uses this method In the VR5000 Series one of two pipelines is assigned to CPU instructions and the other is assigned to FPU instructions and one each of the CPU and FPU instructions are processed simultaneously In the VR5432 and Vr5500 this assignment does not occur and two instructions are processed simultaneously regardless of whether the instruction is from the CPU or FPU Figure 1 2 Outline of 2 Way Superscalar Pipeline 5 Stages and Instruction Execution Instruction Instruction EE passes pa EX DC WB Pipeline 3 4 way superscalar pipeline Reads four instructions simultaneously and processes them in parallel The pipeline of the VR10000 Series uses this method Figure 1 3 Outline of 4 Way Superscalar Pipeline 5 Stages and Instruction E
66. ay O0 cache Index Store Data T 0x25 Index Store Data Way 1 cache Index Store Data I 0x28 Index Store Data Way O0 cache Index Store Data I 0x29 Index Store Data Way 1 cache Index Store Data I 0x2c 9 9 9 9 9 9 9 cache Index Store Data I 0xd Index Store Data Way 0 cache Index Store Data I 0X2d Index Store Data Way 1 cache Index Store Data I 0x30 Index Store Data Way O0 cache Index Store Data I 0x31 Index Store Data Way 1 cache Index SLore Data 1 0x34 Index Store Data Way O0 cache Index Store Data T 0x35 Index Store Data Way 1 cache Index Store Data I 0x38 Index Store Data Way O0 cache index Store Data T 0x39 Index Store Data Way 1 cache Index Store Data I 0x3c Index Store Data Way O0 E ER HH K K E E E EE E HHH E E HH cache Index Store Data I 0x3d Index Store Data Way 1 addiu 9 9 0x40 bgtz 9 I CACHE addiu 8 8 0x40 initialize TagLo TagHi mtc0 0 C0 Taglo mtc0 0 CO TagHi li 12 TagHi_P_PMod Neither Refill mfcO 11 CO TagHi or 13 12 SII SM 01 mtco 13 CO TagHi initialize D cache lui 8 0x8000 Base li 9 0x4000 32KB 2 D CACHE 96 Application Note U10710EJ5VOAN CHAPTER 2 CACHE initialize TagLo TagHi initialize secondary cache S CACHE cache Index Store Tag D 0x00 58 cache Index Store Tag D 0x01 8 cache Index Store Data D 0x0 8 cache Index Store Da
67. b loop sub 8 1 J RK KK KK kkk kkk kkk kk kkk kkk kkk kkk kk kkk kkk kkk kkk kk kkk kkk k kkk kkk kkk k kkk k k Initialize Cache SS SA Enter the initialization program of the cache shown in page 94 here end init vr10000 138 Application Note U10710EJ5VOAN APPENDIX B BV DASSING M TN 48 C A 49 92 Filonide ai lea 100 WAG iena nana ata 50 Initialization no noninnons 92 122 EIERE Lele 50 EE EE ee 59 FINALY ACN arios aida 49 Secondary cache eee 55 SVI RARI 50 Tag OSPI ia 102 WVFIICDACK una 98 Cache instruction 200000 eee nn 57 Opera tas ii Aa 59 Suboperation code 57 58 59 Cache llri i e cete 51 52 53 54 55 56 viri 50 Cause register eee ener 76 Cold reset evcepton 75 115 CONTIG register nre estt e busque ies 26 Context register eee 113 Control Status regster eneee nnee 39 ENEE 25 Kiel 25 qi mem 25 Hazard A 36 87 88 89 91 Srel 25 122 CPU n cn de DOB Toro fur 19 INIMAliZatiori sai rindan 121 ASTUCION cad ES 22 A T li 24 121 D Debug interface sees 82 BIET CE 46 Branching delay 46 85 Loading delays iia ai 47 86 DS ea ida 31 E ENUM cilena 66 107 INDEX Enti yEO FOIS isaac 67 107 See Le 36 73 115 DiseniminNa ngisas 115 A Erer tees 118 A aio aio 74
68. bit O in the VR5432 VR5500 and Vn10000 Series is used to determine the way of the 2 way set cache Note CACHESIZE and BLOCKSIZE are the number of bits required to indicate the cache size and the cache block size For details refer to Table 3 1 e Hit operation This operation executes an instruction for a cache block that fully matches the address specified by the cache instruction The instruction is not executed if only the index matches e Invalidate operation This operation invalidates the specified cache block e Writeback operation This operation writes back the specified cache block If specified for a primary cache the writeback is to the main memory e Fill operation This operation fills the specified cache block with instruction data from the main memory Application Note U10710EJ5VOAN 59 VOLUME 2 Vr SERIES ARCHITECTURE Create_Dirty_Exclusive operation This operation sets the specified address to the cache block tag and makes the cache status Dirty If the address specified for the cache block is not included and if the block status is Dirty writeback to the main memory is performed Flash operation This operation flashes the entire tag array of the secondary cache Page Invalidate operation This operation invalidates the entire secondary cache block corresponding to the specified pages Fetch and Lock operation This operation sets the specified address to the cache block tag and locks the cache status If the
69. bss Compiler and linker specification Pass these along a path that includes the GHS tools directory CC ccmipel AS asmips LD Ix Program to be created MAIN S TARGET Link S TARGET reset o Add other required objects to part S LD o S TARGET S LFLAGS reset o S SECTION Assemble S AS S AFLAGS s Compile CC CFLAGS c 39 end makefile 120 Application Note U10710EJ5VOAN CHAPTER 5 CPU INITIALIZATION This chapter describes using sample programs the initialization to be performed by software for creating monitors etc 5 1 Initialization of CPU Once the CPU has been activated initialize first the registers incorporated in the CPU or coprocessor that are not set by hardware In the Vr Series most of the registers are undefined after reset It is necessary to correctly set the values when initializing 5 1 1 CPU registers Many of the CPU registers are general purpose registers At least the following registers of general purpose registers require initialization e Register 26 register 27 Used by OS monitor Can be used when designing OS monitors etc When calling C language functions the following registers also require initialization e GP register register 28 Required to be initialized when using small scale data area e SP register register 29 FP register register 30 e Register 4 register 5 register 6 register 7 Used as arguments for func
70. cile delli i csi ce i PECIA LEE 123 Dil Abu 125 So 9 NA oee a 128 Application Note U10710EJ5VOAN 11 52 ABASOO SOTIOS iuis RIESI TARE LIS ORTA OO ID ALSO OS P olt IP IP pe CI DP DE DE IET 130 5 25 NR5000 e M 4 laici 131 520 VESTIUM uM hte EID d RE M uud eM M MIL M ETE 133 520 a MA A ee 134 2 VRT0000 Series al 135 APPENDIX INDEX sa sodu EE 139 12 Application Note U10710EJ5VOAN LIST OF FIGURES 1 2 VOLUME 2 Vr SERIES ARCHITECTURE Figure No Title Page 1 1 Outline of Single Way Pipeline 5 Stages and Instruction Execution 2 eee een nn 20 1 2 Outline of 2 Way Superscalar Pipeline 5 Stages and Instruction Evecuton eee 21 1 3 Outline of 4 Way Superscalar Pipeline 5 Stages and Instruction Evecuton eee 21 1 4 Instructron Formalsi trail rt da 22 1 5 Example of R type ADD r14 r11 CIO E 23 1 6 Example of l type ADDI r14 r11 OXO TOO vans dt is ls opt he ete es 23 1 7 Conio REGISTON c ii ee cs 26 1 8 A A A MEA 28 1 9 sell Bliagnosticotatus DSY ABA ccm 31 1 10 Virtual Memory Address paesistico 33 1 11 Mapping of Virtual Address and Physical Address 34 1 12 Memory el E Ae PC aa 35 1 13 Elow OL Exception roces SINO aua i a dis ee lin 36 1 14 Pe UNA CO Se Siracusa ls 38 1 15 A o A ee ec ee E 39 1 16 Cause Ehable Flag Bito FORT aseado EH retten tune te tote nich ines Le me tute nitore aii 39 2 1 Operation of Single Way Pipeline 5 Stages sessi 42 2 2 Operatio
71. come undefined immediately after reset Initialize by software after reset VR4121 Vn4181 EP AD KO VR4122 IS EP AD BP IB KO Vr4300 Series EP BE CU KO EP and BE are conditional VR5000 Series SE KO VR5432 VR5500 EP EM except in Vr5432 s R43K mode KO EP and EM are conditional VR10000 Series KO The EP and BE bits in the Vr4300 Series and EP and EM bits in the Vr5432 and VR5500 can be changed only before the store instruction is executed upon the initialization of non cache area immediately after cold reset When the BE bit is changed with an MTCO instruction the load store instruction must be separated by two or more instructions before or after the MTCO instruction Application Note U10710EJ5VOAN 27 28 VOLUME 2 Vr SERIES ARCHITECTURE 2 Status register Status register can be read written and holds information such as the operating mode interrupt enable and the processor self diagnostic status The following shows the Status register of each CPU Figure 1 8 Status Register a Vr4100 Series 29 28 27 26 25 24 16 15 4 3 2 Mam om been b VR4300 Series 28 27 26 25 24 16 15 4 3 2 o emm I c VR5000 Series 28 27 26 25 24 16 15 4 3 2 ERREECHEN d VR5432 28 27 26 25 24 16 15 4 3 2 coso eme wes EECH e VR5500 28 27 26 25 24 16 15 4 3 2 m we olmo we lemas f VR10000 Series 28 27 26 25 24 16 15 4 3 2 m we jeme we eene o pneu
72. contents of entries if a TLB refill exception occurs This section describes the minimum processing required for the operation above Exception processing such as saving and restoring CPU and CPO registers is not described here For subjects related to exception processing refer to CHAPTER 4 EXCEPTIONS There are three types of TLB exceptions TLB refill exception e TLB invalid exception e TLB modification exception Of these the TLB refill exception requires TLB replacement The following shows the procedure to be performed after a TLB refill exception has occurred Figure 3 5 TLB Replacement Exception handler Judges exception Main program TLB refill exception occurs LW 10 0 11 Processes TLB refill Retrieves TLB entry in the memory Replaces TLB entry Restores registers Application Note U10710EJ5VOAN 111 VOLUME 3 PROGRAMMING The following method can be used as an example of Processes TLB refill in the figure above As the initial setting the TLB entry buffer placed in the memory is created in the following format Figure 3 6 Example of Creating Entry Table on Memory PageMask Create entries of 4K page x 2 from virtual memory OxFFFF DFFF EntryHi PageMask Create entries of 4K page x 2 from virtual memory Create the configuration similar 0x0000 2000 to the contents of TLB entry EntryHi PageMask Create entries of 4K page x 2 from virtual memory 0x0000 0000
73. d instead Figures 1 15 and 1 16 show the configuration of FCR31 Figure 1 15 FCR31 a Vn4300 Series 25 24 23 22 18 17 12 11 Cause Enable Flag EVZOU VZOU VZOU b VR5000 Series Vr5432 Vr5500 and Vn10000 Series 25 24 23 22 18 17 12 11 Cause Enable Flag C 7 1 Figure 1 16 Cause Enable Flag Bit of FCR31 Bit 17 si 11 d 6 Illegal Es Underflow Overflow Zero division Invalid operation Undefined operation Application Note U10710EJ5VOAN 39 VOLUME 2 Vr SERIES ARCHITECTURE The following describes the bits in FCR31 FS bit Bit to enable flushing of values that cannot be normalized C CC bit The result of the floating point comparison instruction is stored When the result of the comparison is true this bit is set to 1 When the result is false it is cleared to 0 Bit C CC is not affected by instructions other than the compare instruction and CTC1 instruction Cause bit Displays the status of the floating point arithmetic executed last Enable bit Enables the generation of floating point exceptions for each cause V Z O U and Flag bit Accumulates the result of floating point arithmetic after reset HM bit Rounding mode control bit For details refer to Table 1 4 Table 1 4 Rounding Mode Control Bit RMBR o Bit Mnemonic Description Rounds the result to the closest expressible value If the result is between two expressible values the result is rounded to the value whose lowe
74. e REIS o D T T ITEM 76 5 2 General Purpose Exception Processing by Hardware 79 5 3 General Purpose Exception Processing by Software e 80 6 1 Basic OMCN eebe att elt e ame a e ia io 83 VOLUME 3 PROGRAMMING Figure No Title Page 3 1 EntyAtRegister In 32 Bil MOG ot aida 107 3 2 EntryLoO Lo1 Register In 32 Bit Mode 107 3 3 BAIN e EE 107 3 4 RR SR d Ee acciai 109 3 5 BEST 111 3 6 Example of Creating Entry Table on Memory esses eene nnne nnne nnn nnn nnns 112 3 7 Context Register In 32 Bit MOd6 cpr A a A oct ta uo ets oce ee Posi ned 113 14 Application Note U10710EJ5VOAN LIST OF TABLES VOLUME 2 Vr SERIES ARCHITECTURE VOLUME 3 PROGRAMMING Application Note U10710EJ5VOAN Table No Title Page 1 1 VEN MES PIOCCSSOMS csi stan acai a e LO 19 1 2 e Oni celati 25 1 3 Difference in Cache Depending on Hroceseor eene nennen nennen nnn en nnn nnn nnn nnn 35 1 4 Rounding Mode Control E 40 2 1 N mber or Pipeline Stages In Ve SONGS A Eau Xe ob kan ak 41 3 1 Primary Cache Size Line Size and Index i 50 3 2 Cache Instruction s Suboperation Code op o 57 3 3 Cache Instruction s Suboperation Code Opa iii 57 4 1 Physical Address SPACE tide lieta elia eee Bo cse tU RSS edat 61 4 2 Mask values and e EE il ee lira 65 5 1 riders OPEXCO DIOS adele 74 5 2 EXCOPHON eege e TEE 75 5 3 Status When EE 75 5 4 Exception Code Area of Cause Register um
75. e between exceptions utilizing the exception vector OxBFCO 0380 refer to the exception code area in the Cause register of coprocessor 0 1 Discrimination program The following shows the program that discriminates between exceptions utilizing the exception vector OxBFCO 0380 In this example the CPU register is not restored or saved When actually creating an exception routine restore and save the CPU register used for exception processing globl OTHER exception ent OTHER exception OTHER exception Set Cause register to argument 1 mfcO 54 13 nop nop jal Check Exception nop end OTHER exception H 0 0 JO U SW N r The C language program shown below is called from the exception handler Hdefine Int Hdefine Mod Hdefine TLBL Hdefine TLBS define AdEL Hdefine AdES Hdefine IBE define DBE define define define define define Interrupt TLB modified TLB refill Load fetch TLB refill Store Address error Load fetch Address error Store Bus error Instruction fetch OO NI ON U RK UN F Bus error Data load store System call Breakpoint Reserved instruction ond OAO U K U NN F o HH VW Ho Coprocessor unusable LA N Operation overflow Hdefine JE Trap define Floating point define WATCH 23 Watch hop Ul W void Check Exception unsigned int Cause int ExcCode
76. e verification and program debugging can be performed simply by connecting a dedicated emulator with the device mounted on the target board on chip debug The Vn4122 Vr5432 and Vr5500 incorporate a debug interface compliant with N Wire specifications 6 1 Debug Interface Function The N Wire specification debug interface enables the following functions in each product 1 Vn4122 e Register access e Memory access e Single step execution Break from real time execution Instruction access break 2 points Data access break 2 points 2 VR5432 and Vn5500 e Register access e Memory access e Single step execution e Break from real time execution Instruction access break 1 point Data access break 1 point e Trace Outputs only branch condition 82 Application Note U10710EJ5VOAN CHAPTER 6 DEBUG INTERFACE 6 2 Debug System Configuration The basic configuration for on chip debugging using the N Wire specification debug interface is as follows Figure 6 1 Basic On Chip Debug Configuration Target system System on chip N Wire interface CPU S Debug unit N Wire emulator User logic Application Note U10710EJ5VOAN 83 84 VOLUME 3 PROGRAMMING Application Note U10710EJ5VOAN CHAPTER 1 PIPELINE This chapter describes points to be noted to smooth the flow of the pipeline when creating a program using an assembler and the CPO hazards when using coprocessor 0 in the assembler 1 1 Program Not Stopping Pipel
77. egisters FPR hold floating point data of single or double precision Each FPR register corresponds to FGR of the adjacent number as shown in Figure 1 14 3 If the FR bit of the Status register is 1 thirty two 64 bit registers FPR hold floating point data of single or double precision Each FPH register corresponds to FGR as shown in Figure 1 14 Application Note U10710EJ5VOAN 37 VOLUME 2 Vr SERIES ARCHITECTURE Figure 1 14 FPU Registers a FGR and FPR i When FPR bit 0 11 When FPR bit 1 Floating point register Floating point general Floating point register Floating point general FPR purpose register FGR FPR purpose register FGR 63 Lower FPRO Higher FPRI Lower FPR2 Higher FPR3 b FCR 1 Control Status register ii Implementation Revision register FCR31 FCRO 31 0 31 o ii The following describes the Control Status register which is especially important among these registers 38 Application Note U10710EJ5VOAN CHAPTER 1 OUTLINE 1 Control Status register FCR31 The Control Status register FCR31 can be read written and holds the control and status data FCR31 controls the rounding mode and enables the generation of floating point exceptions It shows the information of the exceptions that are generated in the instruction executed last and exceptions that have not become an exception due to masking and have been accumulate
78. eral Oxab000000 Add change the register settings in accordance with the hardware li 8 BCU etc 1 9 sh 9 Al 59 sh 9 E 59 sh 59 li 9 sh 9 li 59 sh 59 li 9 sh 9 L3 59 sh 59 PMU da 9 sh 9 T3 9 0x4000 0x0000 8 0x0000 0x0002 58 0x4000 0x0016 8 0x4000 Ox000a 8 0x0333 Ox000e 8 0x8039 Ox00la 8 0x0944 0x00le 8 0x0002 0Ox00a0 8 0x0003 H BCUCNTREGI lt BCUCNTREG2 lt BCUCNTREG3 lt BCUSPEEDREG lt BCURFCNTREG lt SDRAMMODEREG SDRAMCNTREG lt PMUINTREG lt Application Note U10710EJ5VOAN 0x4000 0x0000 0x4000 0x0336 0x0333 lt 0x8039 0x0944 0x0002 CHAPTER 5 CPU INITIALIZATION 9 0x00ac 8 4 PMUDIVREG lt 0x0003 9 0x0001 9 0x008c 8 MSYSINTIREG lt 0x0001 9 0x0000 9 0x0098 8 d NMIREG lt 0 NMI HH reset haltimer jal haltimerrst nop start user program T3 31 USER PROGRAM jr 531 nop i HALTIMER RESET globl haltimerrst ent haltimerrst haltimerrst lui 8 Oxab00 Shi PMUCNTREG lh 9 Ox00a2 8 S59 59 0x4 set HALTIMERRST sh 9 0x00a2 8 jr o3 haltimerrst 5 2 2 Vn4122 An example of an initialization program for an evaluation board from TANBAC Co Ltd TB0151 1 is shown below Add change initialization depending on the hardware BCU SDRAM etc in accordance with the system used The USER PROGRAM in the list indicates
79. es Addition of description in 4 3 TLB Entry Register pp 76 77 Addition of description in 5 4 2 General purpose exceptions pp 82 83 Addition of CHAPTER 6 DEBUG INTERFACE VOLUME 3 PROGRAMMING p 87 p 92 pp 93 to 98 pp 98 to 103 Addition of description in 1 2 Instruction Hazards Modification of description in 2 1 1 Cache initialization procedure Addition and change of description in 2 1 2 Example of cache initialization program Addition and change of examples of program in 2 2 Cache Writeback 2 3 Cache Fill and 2 4 Cache Tag Display p 108 pp 110 111 p 120 pp 121 122 pp 123 to 138 Change of example of program in 3 3 TLB Settings Change of example of program in 3 4 TLB Initialization Change of example of program in 4 2 Initialization of Exceptions Addition and deletion of description in 5 1 Initialization of CPU Addition and change of example of program in 5 2 Example of Initialization Program The mark x shows major revised points Application Note U10710EJ5VOAN Target Readers Purpose Organization How to Read This Manual INTRODUCTION This manual is intended for users who understand the functions of the following products and wish to design application systems using these products e Vn4100 Series e VR5432 uPD30541 VR4121 uPD30121 e VR5500 uPD30550 Vr4122 uPD30122 e VR10000 Series Vr4181 uPD30181 VR10000 uPD30700 e VR4300 Series VR12000 uPD30710 Vr4300 Vr4305 uPD30200 VR1200
80. es VR5432 Vr5500 and Vn10000 Series and the secondary cache of the Vr10000 Series adopt a 2 way set associative method Figure 1 12 shows the memory organization of the Vn Series In the logical memory hierarchy the cache is located between the CPU and main memory so that the access to the memory is speeded up from the user side As shown in Figure 1 12 the lower portions of the memory organization have greater capacity and longer access times than the upper portions Application Note U10710EJ5VOAN CHAPTER 1 OUTLINE Figure 1 12 Memory Hierarchy Vr Series CPU Register Register Register Instruction cache Data cache Primary cache Y Access time Storage capacity Secondary cache i is shorter is larger Main memory Disk CD ROM tape etc Peripheral device The VR Series is equipped with the following caches and controllers Table 1 3 Difference in Cache Depending on Processor we we jse k msn Jemen o Dwmmsem um ee 9 Remark O Available x Not available Application Note U10710EJ5VOAN 35 VOLUME 2 Vr SERIES ARCHITECTURE 1 2 3 Exceptions When an exception is generated the ordinary instruction stops execution The processor exits the current mode and enters the kernel mode The processor disables interrupts and hands the execution to the exception handler the exception routine processed by software and located in the specific address Save the process
81. ete Increment line size Set start virtual address Add cache size Set end virtual address cache 0x09 8 bne 68 S94 de Loop addu 28 DE PL3 jr 534 nop CACHE instruction Index Store Tag Is initialization of cache size complete Increment line size end initcache 2 VR10000 Series The C source list of the cache initialization program is shown below In this program initialization should be performed after specifying that the cache size of the secondary cache is 1 MB and the cache line size is 32 words define CO Index 0 define CO Random 1 define CO EntryLo0 2 define CO EntryLol 3 define CO Context 4 define CO PageMask 5 define CO Wired 6 define CO BadVAddr 8 define CO Count 9 define CO EntryHi 10 define CO Compare 11 define CO SR 12 define CO Cause 13 define CO EPC 14 define CO PRId 15 define define define define define define define define define define define define define 94 CO Config 16 CO LLAddr 17 CO WatchLo 18 CO WatchHi 19 CO XContext 20 CO FrameMask 21 CO Diag 22 CO Perr 225 CO ECC 26 CO CacheErr 27 CO TagLo 28 CO TagHi 29 CO ErrorEPC 30 Application Note U10710EJ5VOAN Hdefine define define define define define define define define define define define define define define define define define define define define define define CHAPTER 2 CACHE SR_DE 0x00
82. f the WB stage of the first instruction and smooth pipeline operation cannot be performed In the actual Vr Series however the pipeline can be bypassed and the data in register 1 can be used in the EX stage of the second instruction when the EX stage is ended Figure 2 9 Example of Bypassing a Single way pipeline WB 1 0x8000 DC 1 1 0x0000 1 0x8000 1 1 Ox0000 For bypassing in the Vn10000 Series refer to VR10000 Series User s Manual 48 Application Note U10710EJ5VOAN CHAPTER 3 CACHE 3 1 Primary Cache The primary cache in Vr Series products has the following states e Invalid The cache line does not contain valid information e Dirty exclusive The cache line contains valid information Information in the line differs from the main memory e Clean Exclusive The cache line contains valid information Information in the line is the same as the main memory e Shared The cache line contains valid information The same information is contained in other processors Dirty Exclusive and Clean Exclusive are also known jointly as valid state The primary cache is incorporated in the processor and its contents can therefore not be manipulated externally The primary cache of the Va Series refers to the cache with a part of the virtual address as the index The index is determined by the cache size and the cache line size When the cachable memory is accessed the index part of
83. field and in the CPO EntryHi register The global bit G is in the CPO s EntryLoO register and EntryLo1 register Application Note U10710EJ5VOAN 61 VOLUME 2 Vr SERIES ARCHITECTURE 4 1 Translation from Virtual Addresses to Physical Addresses The first step in translating from virtual addresses to physical addresses is comparing the virtual address received from the processor with all of the entries in the TLB A match occurs when the Virtual Page Number VPN of the virtual address is the same as the VPN area of the entry and when either of the following conditions is met The global bit G in the TLB is 1 The ASID area of the virtual address is the same as the ASID area of the TLB entry Such a match is called a TLB hit When no match occurs the processor generates an exception called a TLB refill When the TLB contains a matching virtual address the higher bits of physical address are read from the TLB and an offset is added The offset represents the address within the page frame space The offset portion does not pass through the TLB and the lower bit of the virtual address is output directly Figure 4 1 Translation from Virtual Address to Physical Address EntryHi register Virtual address ASID Offset Compare Entry in which ASID and VPN match Physical address 62 Application Note U10710EJ5VOAN CHAPTER 4 TLB 4 2 TLB Entries Vr Series processors have
84. g delays Therefore the number of instructions required to avoid a hazard must be managed on the program Data and status is not properly conveyed unless the number of CPO hazards is observed The number of instructions required between instruction A instruction placing the value in CPO and instruction B instruction which uses the same CPO register as instruction A as the source can be calculated with the following expression Number of hazards of instruction A destination number of hazards of instruction B source 1 In the Vr5000 Series VR5432 VR5500 and Vn10000 Series it is not necessary to take hazards into consideration since the CPU stalls the pipeline However according to the combination of instructions the result cannot be predicted when a specific system event occurs during execution in the Vr5000 Series VR5432 and VR5500 Caution Do not allocate a jump branch instruction in the delay slot of the jump branch instruction in the Vr Series Tables 1 1 to 1 4 show the instruction hazards of each CPU Application Note U10710EJ5VOAN 87 VOLUME 3 PROGRAMMING Table 1 1 CPO Hazards of Vn4100 Series Hazards Hazards Dm E we jee qo o oO TLBR Index TLB 2 PageMask EntryHi 5 EntryLo0 EntryLo1 TLBWI Index or Random 2 TLB 5 PageMask EntryHi EntryLoO EntryLo1 TLBWR PageMask EntryHi TLBP ERET EPC or ErrorEPC TLB Status CACHE Index Load Tag TagLo TagHi PErr n CACHE
85. gisters rewriting in the instructions fetched simultaneously are executed from wherever possible rather than in program order Hardware detects the dependency relationship of registers and delay due to load branch and resources are allocated so that no space remains in the pipeline and processed Note that the output of execution results such as writeback to memory is performed in program order Application Note U10710EJ5VOAN 19 VOLUME 2 Vr SERIES ARCHITECTURE 1 1 2 Pipeline In the Vr Series an instruction execution system called a pipeline is adopted In the pipeline instruction execution processing is delimited into several stages Instruction execution is complete when each stage is passed When processing of one instruction in one stage of the pipeline is complete the next instruction enters that stage When the pipeline is full it means that instructions equalling the number of pipeline stages are being executed simultaneously The pipeline clock is called the PClock Each cycle of the PClock is called a PCycle Instructions are read in synchronization with the PClock Each stage of the pipeline is executed in one PCycle Therefore executing an instruction requires as many PCycles as the number of pipeline stages When the required data has not been cached and must instead be fetched from the main memory the execution requires more cycles than the number of pipeline stages The Vr Series provides the following pipelines The methods
86. hat an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function VR10000 Series VR10000 Vn12000 VR12000A Vr3000 Series Vn4100 Series Vn4100 Vn4121 Vn4122 Vn4181 Vr4200 Vn4300 Series VR4300 Vn4305 Vn4310 VR5000 Series VR5000 VR5000A VR5432 Vr5500 and Vn Series are trademarks of NEC Corporation MIPS is a registered trademark of MIPS Technologies Inc in the United States MULTI is a trademark of Green Hills Software Inc Application Note
87. he execution of the user program 4 Restoring CPU registers Restore the contents of the CPU registers saved in 1 above 5 Restoring from exception processing Execute the ERET instruction and resume exception of the user program Figure 5 3 General Purpose Exception Processing by Software General purpose exception operation reference Saves CPU registers Checks Cause register Jumps to each routine Processes by each routine excludes exception cause As shown in Figure 5 2 if another exception occurs during the processing of an exception with EXL of the Status register 1 the EPC register will not be set If another exception occurs during the processing of an exception the exception processing cannot be properly ended To enable multiple interrupts exceptions refer to 5 5 3 Multiple interrupts 80 Application Note U10710EJ5VOAN CHAPTER 5 EXCEPTIONS 5 5 3 Multiple interrupts In the exception processing described above interrupts during the processing of exceptions including interrupts are not supported To enable multiple interrupts save CPO registers EPC register Status register etc used during the processing of exceptions and set the KSU ERL EXL and IE bits of the Status register to interrupt enabled To disable multiple interrupts after once enabling them change the Status register in the exception processing and then restore the contents of the register saved The exception processing
88. industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life Support systems and medical equipment for life support etc The quality grade of NEC semiconductor products is Standard unless otherwise expressly specified in NEC s data sheets or data books etc If customers wish to use NEC semiconductor products in applications not intended by NEC they must contact an NEC sales representative in advance to determine NEC s willingness to support a given application Note 1 NEC as used in this statement means NEC Corporation and also includes its majority owned subsidiaries 2 NEC semiconductor products means any semiconductor product developed or manufactured by or for NEC as defined above M8E 00 4 Application Note U10710EJ5VOAN Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify e Device availability e Ordering information e Product release schedule e Availability of related technical literature e Development enviro
89. ine There are two causes of pipeline stall slip branching delays and loading delays Allocating instructions on the program to prevent these causes smoothes the flow of the pipeline and allows full use of the CPU capability Remark Scheduling for branching or loading delays is not necessary in the VR10000 Series 1 1 1 Branching delay Instructions that generate branching delays include the following J BGEZAL BLTZ JAL BGEZALL BLTZAL JALR BGEZL BLTZALL JR BGTZ BLTZL BEQ BGTZL BNE BEQL BLEZ BNEL BGEZ BLEZL These are FPU branching instructions FPU instructions cannot be used in the Vr4100 Series BC1F BC1FL BC1T BC1TL When these instructions are used the instruction after this instruction is executed while the next address is being fetched after a jump is established However in branch likely instructions BEQL instruction etc if the branching condition is not established one instruction after the branching instruction is discarded The following shows an example of branching delay 1 2 3 4 5 6 7 8 9 Application Note U10710EJ5VOAN 85 VOLUME 3 PROGRAMMING These programs can optimize the allocation of instructions as follows 1 2 3 4 5 6 7 8 9 In the case above it looks as if the instruction addu 2 2 1 in line 9 is not executed when the condition is established However it is executed whether the condition is established or not because is in the branching delay slot of the BNEZ inst
90. initialization procedure 2 1 1 Cache initialization procedure What occurs in cache initialization differs somewhat between CPUs that have parity in their cache and CPUs that have no parity The cache with no parity can be initialized only by clearing the V bit of the cache line invalidating the cache line This is because a cache with no parity does not cause parity errors next time it is used even if the data portion is not initialized The cache can be initialized in the following procedure 1 Cache with no parity a Instruction cache 1 Invalidate the cache line using the Index_Invalidate operation of the CACHE instruction b Data cache 1 Initialize the TagLo register using the MTCO instruction 2 Write to the cache tag using the Index_Store_Tag operation of the CACHE instruction 2 Cache with parity a Instruction cache 1 OD n op Set the CE bit of the Status register to 0 Set the cache tag and determine the physical address managed by the cache Initialize the TagLo register using the MTCO instruction Write to the cache tag using the Index_Store_Tag operation of the CACHE instruction Initialize data block of the cache using the Fill operation of the CACHE instruction Invalidate the cache line using the Index Hit _Invalidate operation of the CACHE instruction b Data cache 1 2 3 4 Make the cache block Dirty Exclusive using the Create_Dirty_Exclusive operation of the CACHE v
91. instruction Trap Integer overflow Floating point arithmetic Address error Data access TLB refill Data access TLB invalid Data access TLB modified Data write Cache error Data access Watch Bus error Data access Interrupt except NMI Remark Some of the exceptions may not occur or the priority may differ depending on the CPU For details refer to the users manual of each product 74 Application Note U10710EJ5VOAN CHAPTER 5 EXCEPTIONS 5 3 Exception Vector Address When exceptions occur in Vr Series processors the processing branches to the addresses shown in Table 5 2 Note that the address differs depending on the contents of the BEV bit of the Status register Table 5 2 Exception Vector Address Type of Exception Vector Address BEV 0 Vector Address BEV 1 Cold reset soft reset NMI BEV bit is automatically set to 1 OxBFCO 0000 TLB refill EXL 0 0x8000 0000 OxBFCO 0200 XTLB refill EXL 0 0x8000 0080 OxBFCO 0280 Allocate the program of each exception processing to the address shown above using a section specification etc 5 4 Cautions Concerning Major Exceptions 5 4 1 Cold reset soft reset NMI exceptions The cold reset soft reset and NMI exceptions use the same exception vector OxBFCO 0000 The following shows the registers cache and memory whose status is guaranteed when these exceptions occur Table 5 3 Status When Exception Occurs Exception Status Register ErrorEP
92. int exception reserved instruction exception coprocessor unusable exception operation overflow exception Lrap exception floating point exception watch exception Application Note U10710EJ5VOAN 117 VOLUME 3 PROGRAMMING 4 2 Initialization of Exceptions This section describes the exception initial settings and program and the methods for allocating exceptions in the vector which are required when creating a monitor etc This program calls the program described in CHAPTER 5 CPU INITIALIZATION When linking this program link it with the required objects 1 set noreorder 2 i Cold reset soft reset NMI 3 globl Reset 4 ene Reset 5 OxbfcO 0000 6 Reset 7 MEGO 2649 SL 8 li 27 0x00100000 9 and 27 27 27 10 bne 27 0 NMI exception 11 Describe processing for cold reset exception 12 jal Check Processor 13 nop 14 j Reset 15 nop 16 NMI exception 17 Add processings for soft reset and NMI exception 18 jal Check Processor 19 nop 20 j Reset 21 nop 22 end Reset 23 24 TLB exception 25 align 0x200 26 globl TLB exception 27 ent TLB exception 28 OxbfcO 0200 29 TLB exception 30 Describe processing for TLB exception 31 32 j Reset 33 nop 34 end TLB exception 35 36 XTLB exception 37 align 0x280 38 globl XTLB excepti
93. is expanded to separate physical addresses according to the contents of the ASID area When accessing this area set the TLB first A TLB exception will be generated if this area is accessed without setting the TLB In virtual address space using the TLB cache usage and coherency are controlled by setting the C bit of TLB entries Figure 1 11 illustrates how the memory area that is accessed without using the TLB is translated to physical addresses Application Note U10710EJ5VOAN 33 34 2 VOLUME 2 Vr SERIES ARCHITECTURE Figure 1 11 Mapping of Virtual Address and Physical Address Virtual address 0 5 GB with TLB mapping Example of memory on an actual unit 0 5 GB with TLB mapping 0 5 GB without Pee mapping Ox1FFF FFFF Non cacheable 0 5 GB without i 0x1FCO 0000 PPINA Physical address 2 GB with TLB mapping 0x0 1FFF FFFF 0x0 0000 0000 In the figure above the ROM area on the actual unit is set from Ox1FCO 0000 This is because the reset exception vector is set from OxBFCO 0000 so that this area is to be specified for the ROM area In addition because the exception vectors for general use are set from 0x8000 0100 memory must be allocated to addresses from the physical address 0x0000 0000 Normally this area is set as RAM area Cache The cache of the Vn4100 Series and Vn4300 Series adopts the direct mapping method On the other hand the primary cache of the Vr5000 Seri
94. kk k kkk kkk k Initialization of CPO register kk cock ck kc ck ke ck ck kc ck kc ck ck cce RAEE EEE IE RAEE ccc ck SSA D 500200 add 8 0 50 li 8 SR XX SR CUL SR CUO SR FR MECO Se CO SR mtc0 0 CO TagLo meco 905 40 Tagli nto 0 CO ECC mtcO 0 CO PageMask 4k byte pages meso 0 C0 Index mnteo S0 CO Entry mtc0 0 CO EntryLhoO MUCO 0 C0 EntryLol mtcO 0 CO Cause mtc0 0 CO Wired also sets Random register to 63 J KK KKK KK KK kc ck eK eK KK RRA kkk kkk kkk kkk kkk kkk kkk kkk Initialize all registers After a power on or cold reset sequence all logical registers both in the integer and the floating point register files must be written before they can be read Failure to write any of these registers before reading from them will have unpredictable result HERE HE HE RE HE HERE EEE RAEE EEE E EHE E EEE RAEE EEE EEA EE E EHE RAEE EE E RAEE ERE ERA RA add SL 0 0 dmtcal SO SfO add 2 0 0 dmtc1 0 Sfl add 3 0 0 damtel 0 S f2 add 4 0 0 dmtcl 0 Sf3 136 Application Note U10710EJ5VOAN CHAPTER 5 CPU INITIALIZATION add 5 90 S0 amtel 0 Std add 6 0 0 dmtcal 0 S 5 add 7 0 0 dmtcl 0 SEe add 8 0 0 dmecil 0 5f7 add 9 0 0 dmtcal 0 S 8 ada S 107 0 0 dmtcl 0 S 9 ada 11 0 0 dmtcl SO Sf10 ada 12 90 0 dmtecil 0 SELL add 13 0 0 Geert 0 SEL2 add 14 0 0 dmtcal SO S
95. li 26 0x00000000 13 li 527 0x00000000 14 15 initialize CP0 Config register 16 mfcO 8 16 17 li 9 Oxf07f7ff8 clear EP AD BE KO bits 18 and 58 8 S9 19 Li 9 0x00000003 d set K0 3 20 or 59 584 DI 21 mtco S8 16 22 23 initialize CP0 Status register 24 li 8 Ox10000000 set CU0 1 RE 0 BEV 0 TS 0 25 SR 0 CH 0 CE 0 DE 0 26 E IM 0 KX 0 SX 0 UX 0 KSU 0 27 t ERL 0 EXL 0 IE 0 28 mtco S8 12 29 30 WatchLo register 31 li 8 0x00000000 set PAddr0 0 R 0 W 0 32 mtco 58 18 33 34 Compare register 35 li 8 Oxffffffff 36 mtco 58 4 SLL 37 38 initialize TLB 39 L3 8 0xa0000000 base addr of VPN2 40 li 9 32 number of TLB entries 41 li S10 0x0800 VPN2 increment 42 tlb clear 43 mtco S8 10 EntryHi 44 addu 985 985 S10 45 mtco S0 2 EntryLo0 46 mtco SO 3 EntryLol 47 mtco SO 5 PageMask 48 addiu 9 9 1 49 mtco S9 SO Index 50 nop 128 Application Note U10710EJ5VOAN 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 CHAPTER 5 CPU INITIALIZATION nop tlbwi K bgtz Soy EL clear nop initialize cache mtco SO 28 H i cache li 8 0x80000000 K La 9 Ox1000 icache clear cache 0x00 8 K addiu S9 9 0x10 bgtz o9 cache cledr addiu
96. line stages are being executed simultaneously The following shows the instruction status in each type of pipeline if the pipeline is full Application Note U10710EJ5VOAN 41 VOLUME 2 Vr SERIES ARCHITECTURE Figure 2 1 Operation of Single Way Pipeline 5 Stages 5 stages Current CPU cycle Figure 2 2 Operation of 2 Way Superscalar Pipeline 5 Stages 5 stages x 2 ways x U O SS UJ UJ d U O wo D D nn mim olj g ONO O Hit H ITI Ke m X JJ n JJ 2 Current CPU cycle 42 Application Note U10710EJ5VOAN CHAPTER 2 PIPELINE Figure 2 3 Operation of 4 Way Superscalar Pipeline 5 Stages 5 stages x 4 ways EX EX EX EX ala 5 0 m z 0 EA WB WB EX EX spe e Current CPU cycle Application Note U10710EJ5VOAN 43 VOLUME 2 Vr SERIES ARCHITECTURE 2 2 Interlock A pipeline s flow may be stopped upon a cache miss a cache status change the occurrence of an exception or detection of data dependencies Among these conditions that are processed by hardware such as cache misses are called interlocks On the other hand conditions that must be processed by software are called exceptions Interlocks and exceptions are collectively called faults as shown in Figure 2 4 The Vn4100 Series and Vr5000 Series have two types of interlocks
97. m entries can be updated with any TLB instruction Figure 4 7 Random Register 31 6 5 0 T 26 6 Each bit of the Random register is described below Random This is the TLB random index 0 This is reserved Write a zero here A zero will be returned when this area is read Application Note U10710EJ5VOAN 69 VOLUME 2 Vr SERIES ARCHITECTURE 3 Wired register The Wired register can be read written and indicates the lower limit of TLB random entries Although the Wired area holds 6 bit information only the lower 5 bits are used in the VR4100 Series and Vn4300 Series Wired entries cannot be updated with the TLBWR instruction but can be updated with the TLBWI instruction Figure 4 8 Locations Indicated by Wired Register Range indicated by Random register Value of Wired register Range of wired entries The Wired register is cleared to O upon cold reset The Random register is set to the higher limit value when writing is performed to the Wired register When TLB entries are replaced entries that are to be removed from the replacement targets are set as wired entries For example TLB entries related to the area used by the kernel are set Figure 4 9 Wired Register Each bit of the Wired register is described below Wired This specifies the TLB wired boundary O This is reserved Write a zero here A zero will be returned when this area is read 70 Application Note U10710EJ5VO
98. me loloj o lololo ole foo foo we lolo o ol olo o o o o Ji CO ON ol olo ON i RSR mem e s e s e s 5 Come O O r EN b p pb me es TTL c VR5500 reo s 2s or os os 0 s 5 amp m s 55 5 s me feoeo lelo lele eoleo le e e we ofo ofo ojofolofo ofo ojofelofe 1 64 KB o ojojojo ojo olojo o o o ot ix sexe 0 o o o o o o o ololojo 1 vis ea u ww olojojojo ojo o olo 1 1 1 vis e 1 fa emp olojojojo ojo o vjs e s e rr spa om o o o jojojoj i eya e ea e h ili ems olojojojs s ees e yae ea e eye e ir e sm olo sis aaa paa a pafafo euo arpa Application Note U10710EJ5VOAN 65 VOLUME 2 Vr SERIES ARCHITECTURE 4 3 2 EntryHi register The EntryHi register format in 32 birt mode is shown below Figure 4 4 EntryHi Register In 32 Bit Mode a Vr4100 Series 11 10 8 7 0 21 3 8 b VR4300 Series Vr5000 Series Vr5432 VR5500 Vn10000 Series 31 13 12 19 Each bit of the EntryHi register is described below VPN2 This is the virtual page number divided by two due to two page mapping ASID This is the address space ID area The 8 bit ASID area enables the TLB to be shared during multi processing The virtual addresses from each process are able to overlap 0 This is reserved Write a zero here A zero will be returned when this area is read 66 Application Note U10710EJ5VOAN CHAPTER 4 TLB 4 3 3 EntryLo0 Lo1 register The EntryLo register format in 32 bi
99. n of 2 Way Superscalar Pipeline 5 Gtagesl 4 4 0444 0000000ne0 rene rann 42 2 3 Operation of 4 Way Superscalar Pipeline 5 Gtagesl e 43 2 4 Relationship Betweem Interlocks Exceptions and Faute 44 2 5 Slate of Pipeline During Interlock Stall cid A er mer eene deco t es 45 2 6 State of Pipeline During Interlock Gi 45 2 7 Ey FUN tel ci meo A 46 2 8 Ll Ps rm tr SN 47 2 9 Example OF By pas aee P idas 48 3 1 Referencing Primary Cache r A A n kk o S boe 49 3 2 Vr4100 Series OnsChip Cache LIS iioi a ii 51 3 3 Vr4300 SeriesOn Ghip Cache E 52 3 4 VR5000 Series Primary Cache Une eee nne nnns nne KARR nnns nnns nens 53 3 5 Vr5432 and VR5500 On Chip Cache Lines 0000000000000 eee n P KKK KK KR A KKK PKR 54 3 6 VR5000 Series Secondary Cache me 55 3 7 VR TOODO Series Secondary Cache LING sees eden od an oet en ett ie eei ici 56 4 1 Translation from Virtual Address to Physical Address 62 4 2 A e EET DI DI 63 4 3 PageMask oli ge 64 4 4 EntryHi Register In 32 Bit Mode 66 4 5 EntryLoO Lo1 Register In 32 Bit Mode 67 4 6 It A el 68 4 7 Random ee ET CP C 69 Application Note U10710EJ5VOAN 13 LIST OF FIGURES 2 2 Figure No Title Page 4 8 Locations Indicated by Wired Register nennen nnn nennen nnne nnne nnne nans nna snas 70 4 9 Wired E E 70 4 10 RR G lle tee EE 71 4 11 MTEBP SIC OM EE 71 4 12 qui Sa HI de Te HON PCR TA ITE 72 4 13 TEBWR AST e de EE 72 5 1 Caus
100. nment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth e Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 3067 5800 Fax 01 3067 5899 NEC Electronics France S A Madrid Office Madrid Spain Tel 091 504 2787 Fax 091 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 Application Note U10710EJ5VOAN NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 253 8311 Fax 250 3583 NEC Electronics Taiwan Ltd
101. ntil the instruction fetch stage after the delay Figure 2 7 Branching Delay a Single way pipeline Jump branch IC EX DC WB A Branching Y delay slot RF DC WB Branching delay HF EX WB b 2 way superscalar pipeline Jump branch Branching delay slot ecs Branching delay When using an instruction for which a branching delay occurs in the assembler one delay slot is required In such cases note that the instruction within the delay slot is executed while the branching target instruction is being fetched from the memory Instructions that can be completed during that time are executed normally even when they are coded within a delay slot In the case of branch instructions the operation differs depending on the instruction for which a branching delay has not been established For branch likely instructions such as BNEL the instructions in the delay slots become invalid if the branch conditions are not established For other branch instructions the instructions in the delay slots are unconditionally executed 46 Application Note U10710EJ5VOAN CHAPTER 2 PIPELINE 2 3 2 Loading delay For the sake of pipeline optimization a one cycle loading delay occurs in the Vr Series processors For load instructions data loading is completed when the data fetch stage is ended but the data itself cannot be used until the EX stage following the delay Figure
102. on 39 ent XTLB exception 40 OxbfcO 0280 41 XTLB exception 42 d Describe processing for XTLB exception 43 44 j Reset 45 nop 46 end XTLB exception 47 48 Cache error exception 49 align 0x300 118 Application Note U10710EJ5VOAN CHAPTER 4 EXCEPTIONS globl Cache error ent Cache error OxbfcO 0300 Cache errors Describe processing for cache error exception j Reset nop end Cache error Other exceptions align 0x380 globi OTHER exception ent OTHER exception OxbfcO 0380 OTHER exception Set Cause register to argument 1 mfcO 4 13 nop nop jal Check Exception nop j Reset nop end OTHER exception Application Note U10710EJ5VOAN 119 VOLUME 3 PROGRAMMING When saving this program with the file name reset s the following shows a sample of the makefile to allocate this program to OxBFCO 0000 when the GHS tool is used OO NI nD U gd WYN F 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Specification of target to be created TARGET reset Modify according to target CPU CPU r4000 CFLAGS AFLAGS LFLAGS SECTION Specification of option to be passed to compiler ansi cpu S CPU G c Assembler option CPU Specification of option to be passed to linker e Reset Section specification sec text 0xbfc00000 data sbss 0xa0018000 sdata
103. ondary Cache 55 Seal MASODO SES ERE I LT 55 22 EIERE ad 56 39 Cache Ed Te de EE 57 CHAPTER TED aa 61 4 1 Translation from Virtual Addresses to Physical Addresses 62 42 TEBIENIOS IU I TIT M n Ob s l a 63 4 3 TLB Entry REGISTE unir ada 64 43 PAGEWIASK TEOISIOl sedo utu taa be eo desto ina 64 PC MEE e e imi i e O EI LED I 66 433 EnttyLoO BoT register soste A the tao he 67 404 du 68 AA HEET EE 71 CHAPTER S EXCEPTION Si cars hoc Bai A ete alana aw at 73 51 TY Le e iere 73 5 2 PRIORITY or EXCOpUON Sui Ai 74 5 3 Exception E ee 75 5 4 Cautions Concerning Major Exceptions cccccsssseecsesseeeeeeneeseesseeseenseeeseeaseesenseeeeensessnensenses 75 5 4 1 Gold reset soft reset TIR ele de 75 5 4 2 General purpose exceptions nennen nennen nnns PAKA PARK KARA sns sss aar rna nns 76 5 5 Exception PrOCES SING REN TTE 78 9 53 Hardware Process ne EE 78 5 5 2 Software DIOCESSING EE 80 2439 MU le TICS TT e E 81 XCHAPTEH 6 DEBUG INTERFACE deeg 82 6 1 Debug Interface FUNCHON eege EES 82 6 2 Debug System CONTIGUA ION inci ENEE ENEE ENEE eege 83 VOLUME 3 PROGRAMMING casi ido 84 CHAPTER A PIPELINE i cc 85 1 1 Program Not Stopping PipeliNe oooncconnccccnnniccccccccncccncncccnnncconnccnnnnnnnnnnnenannrnnnnrenannrnnanrrnnanennnns 85 er A O
104. operates with ultra low power consumption and is equipped with on chip peripheral units Vn4122 Incorporates CPU and primary cache includes product sum operation and MIPS16 instruction set operates with ultra low power consumption is equipped with on chip peripheral units and supports PCI bus subset Vn4181 Incorporates CPU and primary cache includes product sum operation and MIPS16 instruction set operates with ultra low power consumption and is equipped with on chip peripheral units Vn4300 Series Vn4300 Vn4305 Incorporates CPU FPU and primary cache and external bus is 32 bits VR4310 VR5000 Series VR5000 Vr5000A Adopts 2 way superscalar system for CPU incorporates FPU secondary cache interface and primary cache and external bus is 64 bits VR5432 Adopts 2 way superscalar system for CPU incorporates FPU primary cache and branch prediction unit and external bus is 32 bits native mode R43K mode selectable VR5500 Adopts 2 way superscalar out of order system for CPU incorporates FPU primary cache and branch prediction unit and external bus can be switched between 64 bits and 32 bits VR10000 Series VR10000 Vr12000 Adopts 4 way superscalar out of order system for CPU incorporates FPU Vr12000A secondary cache interface primary cache and branch prediction unit Notes 1 Under development 2 Out of order is an execution method in which instructions such as for performing operations or re
105. operation contents Table 3 3 Cache Instruction s Suboperation Code opa 1 3 a Vr4100 Series Vn4300 Series ee o nen tei ito T are O Le T oa Po meme 0 S oam 5 ae s i me O Application Note U10710EJ5VOAN 57 58 VOLUME 2 Vr SERIES ARCHITECTURE Table 3 3 Cache Instruction s Suboperation Code opa 2 3 b VR5000 Series C ee 5 ner ena a era o ao T mme O EE C o ae s i me c Va5432 ee 0 ae eci ie T r O T eee O a Jeepen 4 ww OTO 0 Cs a ewe 5 i remi OOOO d Vr5500 C eee o rr wita mas T rera 00 e o a ee 4 we meme S oam 5 om ET O 5 i ret nao OOOO Application Note U10710EJ5VOAN CHAPTER 3 CACHE Table 3 3 Cache Instructions Suboperation Code opa 3 3 e Vr10000 Series ee s t meme O s es mena O The cache operations are described below e Index operation In this operation an instruction is executed for the cache block that matches the index part of the address specified by the cache instruction The primary cache index is part of the virtual address vAddrcacuesize BLocksizE The secondary cache index is part of the physical address pAddrcacHssizE BLOCKSIZE In the Vr4100 Series and Vn4300 Series specification of an address smaller than the cache block does not have meaning Of the primary cache index addresses bit 14 in the Vr5000 Series or
106. or states such as the contents of the program counter current operating mode user or supervisor status and interrupt enable in the handler These states can be restored after processing the exception When an exception is generated the CPU loads the address to resume the execution after processing the exception to the EPC register Normally the address of the instruction that has generated the exception is loaded to the EPC register as the resume address However if the instruction that has generated the exception is being executed in the branching delay slot the address of the branch instruction immediately before the branching delay slot is loaded to the EPC register For a detailed description of the processing method for each exception refer to CHAPTER 5 EXCEPTIONS Figure 1 13 Flow of Exception Processing Main routine Exception handler Exception cause Resolves the exception cause in the exception handler 1 2 4 Hazards In Vr Series products other than the Vr10000 Series when executing the CPO CP1 instruction unlike the CPU instruction the pipeline is not interlocked Therefore the location of instructions must be managed when creating a program For the detailed description of CPO hazards refer to VOLUME 3 1 2 Instruction Hazards In the Vn10000 Series almost all the hazards related to the pipeline are detected It is therefore not necessary to manage instruction allocation 36 Application Note U10710EJ5VOAN
107. ption vector is set to OXBFCO 0380 and processing moves to this exception vector If the BEV bit is O the exception vector is set to 0x8000 0180 and processing moves to this exception vector Application Note U10710EJ5VOAN CHAPTER 5 EXCEPTIONS Figure 5 2 General Purpose Exception Processing by Hardware Setting Cause register ExcCode CE instruction in delay BD bit lt 1 BD bit 0 EPC lt PC 4 EPC lt PC EXL bit 1 1 boot strap O normal PC lt 0x8000 0000 180 PC lt OxBFCO 0200 180 To general purpose exception operation reference For the details refer to the chapter on exception processing in the user s manual of each CPU Application Note U10710EJ5VOAN 79 VOLUME 2 Vr SERIES ARCHITECTURE 5 5 2 Software processing The following shows the processing performed by software after the processing has moved to the exception vector 1 Saving CPU registers Save the contents of the CPU registers used in the exception processing routine Otherwise the processing cannot be continued when the processing is returned to the user program by the ERET instruction Especially when using the JAL and BAL instructions always save the contents of r31 2 Checking Cause register Check which exception has occurred referring to the Cause register of CPO 3 Excluding exception cause Process the cause of the exception checked in 2 above perform the setting so as not to interfere with t
108. ration note that the writeback is not performed if the cache holds tag contents that differ from the address specified To perform writeback for all data on the cache use the Index Write Back operation 2 2 1 Example of cache writeback program 1 Hit Write Back operation The assembler source list of the function that performs the Hit Write Back operation is shown below Cache writeback function Hit Write Back operation Description Writeback the data cache block specified by vaddr Format void cache hit write back unsigned int vaddr Argument Vaddr Cache block to be written back Return value virtual address ond HW U R UN HE HH E UE UE EEK None aALObL ent cache hit write back cache hit write back cache hit write back cache 0x19 0x0 4 Hit writeback data cache JE 531 nop end cache hit write back 98 Application Note U10710EJ5VOAN CHAPTER 2 CACHE The C source list of the function that specifies the start and end points of the virtual address and performs writeback using the above function is shown below Cache writeback sample program 1 Description Writeback the data cache between the points specified by s vaddr and e vaddr Format void Write Back cache unsigned int s vaddr unsigned int e vaddr Argument s vaddr Start address virtual address Oo yy AU R UN r e vaddr End address virtual address Return address None B External function extern void c
109. ruction 1 1 2 Loading delay Instructions that generate loading delays include the following LB LH LWL LBU LHU LWR LD LL LWU LDL LLD LDR LW These are FPU load instructions FPU instructions cannot be used in the Vr4100 Series LDC1 LWC1 In the Vr Series it is possible to describe instructions that include the register of the loading destination immediately after the load instruction However in that case interlocks are generated for the number of required cycles Therefore allocate instructions to reduce the generation of interlocks as much as possible in terms of both performance and compatibility with the VR3000 Series The following shows an example of loading delay lw 1 OxO 2 addiu o2 Sly LO andi 8 9 0x8 86 Application Note U10710EJ5VOAN CHAPTER 1 PIPELINE In this example a pipeline stall has been generated because the instruction addiu 2 1 10 which uses register 1 has been placed in the delay slot of the instruction Iw 1 0x0 2 in the third line In such a program the allocation of instructions can be optimized as follows As shown above placing an instruction that does not use register 1 in the delay slot of the instruction lw 1 0x0 2 in the third line smoothes the flow of the pipeline thus increasing the execution speed 1 2 Instruction Hazards When using the instructions of the Vr4100 Series and Vr4300 Series pipeline stalls are not generated unlike loadin
110. s arguments and the return value as the pointer to the above structure This function appears as follows when created by the assembler globl1 tlbread ent tlbread tlbread Initial setting assign 0 to the registers used move 8 SO Used as temporary move 15 0 Used for saving index register Save Index register cp0 0 gt cpu 15 m coO 215750 nop OO NI HD U RK UN F Argument 1 to Index register cpu 4 gt cp0 50 mtco S4 SO nop From TLB entry to TLB entry register of each cpO tlbr nop From EntryHi register to structure cp0 10 gt 5 move S8 0 mfcO 58 10 nop SW 8 O S5 From EntryLo0 register to structure cp0 2 544 move 58 0 mfcO 8 2 nop sw 8 4 5 K From EntryLol register to structure cp0 3 gt 5 8 move 8 0 mfcO 58 53 nop 104 Application Note U10710EJ5VOAN CHAPTER 3 TLB sw 58 8655 From PageMask register to structure cp0 5 gt 5 12 move 58 0 mfcO 8 5 nop sw 8 12 5 Restore Index register mec S15 e Create return value of function move 2 5 nop JE Sra nop end tlbread The contents of the TLB entry can be referenced when this function is called from a C language program The initial setting of the function is made in lines 3 to 8 of this function In lines 9 to 14 the second argument specifying the entry number of the TLB passed to this function is copied to the Index register of the C
111. st bit is O Rounds the result towards O The absolute value is the closest value in the range not exceeding the accurate result of the infinite precision 3 9o R Rounds the result towards The value becomes the actual result or more MEE 7 Rounds the result towards co The value becomes the actual result or less 40 Application Note U10710EJ5VOAN CHAPTER 2 PIPELINE 2 1 Pipeline Stage The following pipeline stages are provided in the Vr Series Instruction fetch IF IC etc Instruction decode ID IT etc Branch prediction BR VR5500 only Instruction queuing IQ VR5500 only Instruction issuance IS VR5500 and Vn10000 Series only Register renaming RN Vr5500 only Reservation stationing RS VR5500 only Register fetch RF etc Execution EX etc Data fetch DC DF etc Data align AL VR5500 only Writeback WB etc Commit CoR CoM Vr5500 only The number of pipeline stages is as follows depending on the products and operation mode Table 2 1 Number of Pipeline Stages in Vn Series Vn4121 MIPS III instruction mode Vr4122 MIPS III instruction mode Vn4181 Vr4300 Series Vr5000 Series Vr5432 AS Vr4121 MIPS16 instruction mode Vr4122 MIPS16 instruction mode 8 to 10 VR5500 When the processing of one instruction in one pipeline stage is complete the next instruction enters the stage If pipeline is full it means the instructions egualling the number of pipe
112. t mode is shown below Figure 4 5 EntryLo0 Lo1 Register In 32 Bit Mode a Vr4100 Series Each bit of the EntryLoO Lo1 register is described below PFN C D This is the page frame number It is the higher bits of the physical address This specifies the TLB s page attribute This stands for dirty When the value of this bit is 1 the page is marked as dirty which means it is write enabled Actually this bit functions as a Write protect bit that is used by the software to prevent modification of data This stands for valid When this bit is set to 1 it indicates that the TLB entry is valid If this entry is hit when the V bit has not been set a TLB invalid exception TLB or TLBS occurs This stands for global If the global bit of the both EntryLoO and Lo1 has been set the ASID is ignored when the TLB is referenced This is reserved Write a zero here A zero will be returned when this area is read Application Note U10710EJ5VOAN 67 VOLUME 2 Vr SERIES ARCHITECTURE 4 3 4 Others In addition to the registers described so far the following registers can be used for setting the TLB 1 Index register The Index register is a 32 bit register that can be read written The lower 6 bits of this register are used for the entry index The highest bit indicates the result success failure of the TLBP instruction This register indicates the TLB entries that are the targets of the TLBR instruction or TLBW
113. ta D 0x1 8 cache Index Store Data D 0x4 8 cache Index Store Data D 0x515 8 cache Index Store Data D 0x8 8 cache Index Store Data D 0x9 8 cache Index Store Data D 0x0c 8 cache Index Store Data D 0x0d 8 cache Index Store Data D 0x10 28 cache Index Store Data D 0x11 8 cache Index Store Data D 0x14 8 cache Index Store Data D OxX15 58 cache Index Store Data D 0x18 8 cache Index Store Data D 0x19 8 cache Index Store Data D 0xl1c 8 cache Index Store Data D 0x1d 8 addiu 9 9 0x20 bgtz 9 D CACHE addiu 8 8 0x20 mtc0 0 CO TagLo MECO 04 CO Tagua lui 8 0x8000 Base li 9 0x80000 1MB 2 cache Index Store Tag S 0x00 8 cache Index Store Tag S 0x01 8 cache Index Store Data S 0x00 8 cache Index Store Data S 0x01 8 cache Index Store Data S 0x10 8 cache Index Store Data S 0x11 8 cache Index Store Data S 0x20 8 cache Index Store Data S 0x21 8 cache Index Store Data S 0x30 8 cache Index Store Data S 0x31 8 cache Index Store Data S 0x40 8 cache Index Store Data S 0x41 8 cache Index Store Data S 0x50 8 cache Index Store Data S 0x51 8 cache Index Store Data S 0x60 8 cache Index Store Data S 0x61 8 cache Index Store Data S 0x70 8 cache Index Store Data S 0x71 8 addiu 9 9 0x80 H 32 word bgtz 9 S CACHE addiu 8 8 0x80 CE cb EK E HH EK H E UE Index Store Tag Way_ 0 Index Store Tag Way 1
114. ter and LL bit register cannot be operated by software 24 In addition the following functions are allocated to two general purpose registers rO and r31 rO This is the zero register lts contents are always zero and rO can be specified as the target register for an instruction when the result of the operation should be discarded This register can also be used as the source register when a value of zero is required r31 This is the return address register It is the link register used for the JAL instruction and JALR instruction It can also be used for other instructions but be careful not to duplicate use of data from operations by the JAL JALR instruction and other instructions Application Note U10710EJ5VOAN CHAPTER 1 OUTLINE 1 2 Coprocessors The CPU can be operated with up to four closely coupled coprocessors CPO to CP3 Coprocessor 1 CP1 is a floating point unit however this is reserved in the VR4100 Series Coprocessor 2 and coprocessor 3 are reserved for future use however in the Vr5432 the CP2 instruction code area is used for dedicated instructions Coprocessor 0 CPO is an on chip system control coprocessor and it supports the virtual memory system and exception processing 1 2 1 Registers The following describes the registers in CPO Table 1 2 CPO Registers Ae Used in memory management TLB De 1 Random Used in memory management TLB D Used in memory management TLB NE RN 8 Entro
115. the start address of the program that starts execution after initialization is complete FTE TE TE TE TE T T RARA RARA RRHH rr HH HH HH HH HH HH AHH EE HH HH HH HH HH HE HE EE EE EE EE EE EE EE EE E Initialization program sample VR4122 FTE TE TE TE T T T RARA RARA RRHH HAHAHA HH HH HH HH HH HH HH AHHH HH HH HH HH HH HH HE HE HE HE HE HE HH tt tt EE EE m m mm globl Initialize ent Initialize Initialize clear Hi Lo registers mthi SO mtlo SO clear k0 k1 registers li S26 0x00000000 li S27 0x00000000 initialize CP0 Config register mfco S8 16 l 9 0x707e7fd8 clear IS EP AD BP BE IB KO Sey 58 DI 9 0x00000003 d set IS 0 BP 0 IB 0 K0 3 587 584 59 8 S16 Application Note U10710EJ5VOAN 125 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 126 VOLUME 3 PROGRAMMING initialize CP0 Status register li 8 mtco S8 0x10000000 12 WatchLo register li mtco 58 58 0x00000000 18 Compare register li mtco 98 98 OXTEEETECE 11 HE initialize TLB den 8 LL 59 el SLO elb clear mtco 8 addu 8 mtco S0 mtco 50 mco O addiu 59 mtco 9 nop nop tlbwi bgtz 9 nop 0xa0000000 32 0x0800 10 8 10 2 3 5 DO xe 0 lb cleqE HH initialize cache
116. ther hea UMS 85 1112 e te q acia 86 10 Application Note U10710EJ5VOAN 12 Jet HAZANOS em 87 T2 Calculation or OPONAS candado dat 91 CHAPTER 2 CACHE eege 92 WR ET EEN d NEE 92 21 Cachelmitialization Procedures a a A aia Coda 92 2 1 2 Example of cache initialization program rachel tei ee teas 93 2 2 Gache Writeback 98 2 2 1 Example of cache writeback program 98 23 Gathe Wd eee DU Kt en 100 2 3 1 Example of cache fill program 101 2 4 Cache Tag RE E TE 102 2 4 1 Example of cache tag display program 102 CHAPTER 3 TEBE O a foo on o on o ao t 104 31 VALLI eet 104 3 2 ENUY e H 105 3 3 TEB E d cete 107 2 4 FEB Inniaiza ton EE 110 39 TCB EECHER ebe 111 CHAPTER 4 EXCEPTION Sinai 115 4 1 Discriminating Between Exceptions recess ee eee erre ener enne nnne nennen nns 115 4 1 1 Cold reset soft reset and NMI exceptions nennen nnns 115 he S MEN DINERO elc olea Su ee LE EQ ET 116 4 2 Inidlalizatron OF de d Le RE 118 CHAPTER 5 CPU INITIALIZATION cocos aos 121 51 ici rz nivel 121 ll GPU VEGQISICNS as de T m 121 Bile A A 122 ES e O TEOSE A 122 oO ded IHAL Me EI COW ice iaia 122 95 Initialization orGache and TEBS o ebe ds a tid esso ae ne OS todo 122 5 2 Example Of Initialization Programi ua lle iii 123 A
117. tions e RA register register 31 Used as returned address of a function Store desired values in the registers at initialization Assign an appropriate value to the multiply divide operation register incorporated in the CPU The uses of these registers differs depending on the compiler For details refer to the manual of each tool Application Note U10710EJ5VOAN 121 VOLUME 3 PROGRAMMING 5 1 2 CPO registers Coprocessor 0 has registers that specify the operation of CPU Therefore coprocessor 0 is the most important part of CPU initialization For a detailed description of the CPO registers refer to the user s manual of each product The following CPO registers require setting e Config register register 16 e Status register register 12 e WatchLo register register 18 In some cases a watch exception may occur unless this register is initialized before executing a load store instruction Omit this setting in the VR5000 Series since it does not have a watch register e Compare register register 11 If the value of the count register becomes equal to that of the Compare register before initialization a timer interrupt is generated e Wired register register 6 This register must be set before using the TLB e EntryHi register register 10 The ASID area must be initialized The Config register and Status register are particularly important registers since they specify CPU operations Initialize the Config register by software
118. to enable multiple interrupts is performed in the following procedure 1 2 3 4 5 6 7 Saving CPU registers Save the contents of the CPU registers used in the processing in 2 3 4 5 6 and 7 below to the memory Saving CPO registers Save the contents of the CPO registers and EPC register used in the processing in 3 4 and 5 below to the memory Setting Status register Set the Status register to enable multiple interrupts The following contents are set to the Status register KSU are 00 ERL bit 0 EXL bit 0 IE bit 1 Exception processing Perform processing to exclude the cause of the exception If the exception cause is the register to which the contents have been saved in 1 and 2 change the memory to which the contents have been saved otherwise it is reverted to the state before the exception in the restoration processing in 6 and 7 Setting Status register Restore the contents of the Status register in 2 and disable multiple interrupts Restoring CPO registers Restore the contents of the CPO registers saved in 2 Restoring CPU registers Restore the contents of the CPU registers saved in 1 Application Note U10710EJ5VOAN 81 CHAPTER 6 DEBUG INTERFACE Some products in the Vr Series incorporate debug interfaces that are compliant with the N Wire specifications In the products incorporating debug interfaces compliant with the N Wire specifications hardwar
119. x Format unsigned int cache index load tag unsigned int vaddr int type Argument vaddr Cache block from which the tag 1s to be read virtual address Oo yy ON U Ss UN PF type Cache type 0 Instruction cache 1 Data cache Return value Cache block TagLo register value H HHH globl cache index load tag ente cache index load tag cache index load tag bne 5 0 dcache nop icache cache 0x4 OxO S4 Instruction cache tag load J mfcO taglo nop cache 0x5 OxO S4 Data cache tag load nop mfc0 taglo mfco 52 28 K The TagLo register value is set as the return value jr 531 cache index load tag 102 Application Note U10710EJ5VOAN CHAPTER 2 CACHE The C source list of the function that displays the cache tag using the above function is shown below Oo NI O U B UN F A A AS A U U U U U U U U U UE NNN NNN NNN A FF FP FP K r r LA LA VO WN FPF O E OO X HD U K U NN FE o WO SI o U K U N E o WO O I HD U K U NN F O Cache tag display sample program 2 Description Displays all cache tags Format S void Print CahceTag void Argument None Return value None di External function extern unsigned int cache index load tag unsigned int vaddr Cache size and block size setting define ICache SIZE 0x8000 When define ICache BLK Ox10 When define DCache SIZE 0x4000 When define DCache BLK 0x10 When Start point of virtual address
120. x8 4 0x10 4 0x18 4 0x0 4 S4 0x20 55 A cache data create dirty exclusive index write back invalidate 0x80000000 0x80100000 ex L2cache 1MB 0x0 4 index store tag S4 0x20 2D eo cache S12 0x30 0xa0000000 2 2 EntryLo0 reg 3 3 EntryLol reg 5 S5 PageMask reg S2 1 SO 0 Index reg 10 10 EntryHi reg Application Note U10710EJ5VOAN CHAPTER 5 CPU INITIALIZATION S04 2 ELD 3 3 0x2000 init50 5 2 6 Vr5432 set noreorder text globl init54 ent init54 in1t54 CP0 1 reg mfco S2 16 16 Config reg li S3 OXfOfffff8 and Soia 553 92 li 4 0x3 add 3 3 4 mtco S3 16 EP 0x0 K0 0x3 li 5 Oxf0010000 mtco S5 12 E Sil2Q Status reg COUD3S 0 50xf DESOXL 7 mtco 0 13 13 Cause reg IP 1 0 0x0 mtco SO 18 18 WatchLo reg ctal S0 31 31 FPU Control Status reg cache mico 0 28 11 S4 0x80000000 11 S5 0x80004000 i Cache cache 0x8 OxO 4 index store tag way0 cache 0x8 Ox1 4 index store tag wayl addiu 4 4 0x20 bne 64 cb d cache nop li 4 0x80000000 d cache cache 0x9 0x0 4 index store tag way0 cache 0x9 Ox1 4 index store tag wayl addiu S4 4 0x20 bne Ss cache nop Application Note U10710EJ5VOAN 133 VOLUME 3 PROGRAMMING TLB 0x30 0xa0000000 2 2 EntryLo0 reg 53 3
121. xecution EE Tel 01 0 e ee EEE E EE e E E E e V e FF IS Pipeline Application Note U10710EJ5VOAN 21 VOLUME 2 Vr SERIES ARCHITECTURE 1 1 3 Instructions All the CPU instructions in the Vn Series except MIPS16 instructions are 32 bits in length The instructions are divided into three types according to their formats Figure 1 4 Instruction Formats 26 25 21 20 16 15 0 elisa e er we 31 26 25 0 J type jump target 26 25 21 20 16 15 11 10 Seen RECHERCHER They are further divided into seven types according to the function of the instruction 1 Load store Load store instructions perform data transfer between the memory and general purpose registers The format of load store instructions is type 2 Arithmetic Arithmetic instructions execute arithmetic operations logical arithmetic operations shift operations and multiply divide operations on the register value The format of arithmetic instructions is R type or I type 3 Jump branch Jump branch instructions change the control and flow of the program The jump instruction is either J type or R type The branch instruction is type The JAL instruction saves the return address to register 31 4 Coprocessor Coprocessor instructions execute coprocessor operations The load store instruction of the coprocessor is type The format of coprocessor arithmetic instructions differs depending on the coprocessor
122. y bit P Even parity of ITag DI ag DataP Even parity of Data Data Cache data 54 Application Note U10710EJ5VOAN CHAPTER 3 CACHE 3 2 Secondary Cache Since the VR5000 Series and the Vn10000 Series have an on chip secondary cache controller a secondary cache can be used simply by connecting SRAM The secondary cache can be accessed from both the processor and the system interface The secondary cache has the following two states e Invalid The cache line does not contain valid information e Dirty Exclusive The cache line contains valid information Information in the line differs from the main memory e Clean Exclusive The cache line contains valid information Information in the line is the same as the main memory e Shared The cache line contains valid information The same information is contained in other processors 3 2 1 VR5000 Series The format of the VR5000 Series secondary cache line is described below Figure 3 6 Vr5000 Series Secondary Cache Line 37 35 34 32 31 Each bit of the cache line is described below Vidx Primary cache index bits 14 to 12 of the virtual address SState State of secondary cache STag Secondary cache tag DataP Parity for Data Data Cache data Application Note U10710EJ5VOAN 55 VOLUME 2 Vr SERIES ARCHITECTURE x 3 2 2 Vr10000 Series The format of the VR10000 Series secondary cache line is shown below Figure 3 7 VR10000 Series Secondary Cache Line 137 136 128 127

VR Series 64-/32-Bit Microprocessor Programming Guide AN

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