4I24M PARALLEL PORT MANUAL
Contents
1. 1 C12 ART REV A J2 Page 8 4124M USER S MANUAL CONFIGURATION 5V ENABLE JUMPER Pin 49 on all of the 4124M I O connectors can either be grounded or connected to system 5V through a fuse 5V is provided on pin 49 to supply power to I O module racks This option is selected by the position of the shorting jumper on jumper block W5 When the jumper is in the left hand position fused 5V power is routed to pin 49 on the I O connectors When WS is in the right hand position pin 49 is used as an additional ground This is the default position of the 5 V enable jumper Note that the 5V fuse is rated at 1 Amp and can be replaced without soldering Replacement part number is LittleFuse PN 250001 PIN 1 OPTION JUMPERS Pin 1 is used by some 8 and 16 I O module racks as an additional 5V power source but is used as an I O bit by 24 module racks Jumper blocks W2 W3 and W14 allow pin 1 to be connected to either 5V or appropriate I O bit Jumper W3 selects the option for connector P1 jumper W2 selects the option for connector P2 and jumper W14 selects the option for connector When W2 W3 or W14 are in the left hand position power is routed to pin of the associated connector This is the appropriate setting for most 8 and 16 module I O racks Note that power to W2 W3 and VV 14 comes from power option jumper W5 which must be in the left hand p2. even pins connected to ground or open W4 option Page 14 4124M USER S MANUAL OPERATION P2 CONNECTOR PIN SIGNAL 1 A2 bit 0 or 5V fused power W2 option 3 A2 bit 1 5 A2 bit 2 T A2 bit 3 9 A2 bit 4 11 A2 bit 5 13 A2 bit 6 15 A2 bit 7 17 B2 bit 0 19 B2 bit 1 21 B2 bit 2 23 B2 bit 3 25 B2 bit 4 27 B2 bit 5 20 B2 bit 6 3l 80 bit 7 33 C2 bit 0 35 C2 bit 1 37 C2 bit 2 39 C2 bit 3 41 C2 bit 4 43 C2 bit 5 45 C2 bit 6 47 C2 bit 7 49 5V fused power GND W5 option All even pins connected to ground or open W15 option Page 15 4124 USER S MANUAL OPERATION 8255LOOP A simple test program is supplied with the 4124M for functional testing and verification This program is called 8255LOOP EXE 8255LOOP is what s called a loopback test program It works by sending rotating bit patterns out on all 24 bits of a8255 programmed for all outputs then checking to see that the same pattern has been received on a second 8255 programmed for all nputs After this is done 8255LOOP reverses the roles of the input and output chips and repeats the test The connection between the two 8255 s is done with an external cable a loopback cable 8255LOOP will detect most common I O port problems including stuck bits shorts and opens 8255LOOP is not very smart about major problems like incorrect port addresses missing loopback cables etc and will cheerfully report bit errors even if no 4124M card is present To u
3. WARRANTY Mesa Electronics warrants the products it manufactures to be free effects in material and workmanship under normal use and service for the period of 2 years from date of purchase This warranty shall not apply to products which have been subject to misuse neglect accident or abnormal conditions of operation In the event of failure of a product covered by this warranty Mesa Electronics will repair any product returned to Mesa Electronics within 2 years of original purchase provided the warrantor s examination discloses to its satisfaction that the product was defective The warrantor may at its option replace the product in lieu of repair With regard to any product returned within 2 years of purchase said repairs or replacement will be made without charge If the failure has been caused by misuse neglect accident or abnormal conditions of operation repairs will be billed at a nominal cost THE FOREGOING WARRANTY IS IN LIEU OF ALL OTHER WARRANTIES 55 OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTY OF MERCHANTABILITY FITNESS ADEQUACY FOR ANY PARTICULAR PURPOSE OR USE MESA ELECTRONICS SHALL NOT LIABLE FOR ANY SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES WHETHER IN CONTRACT TORT OR OTHERWISE If any failure occurs thefollowing steps should be taken 1 Notify Mesa Electronics giving full details of the difficulty On receipt of this information servic
4. chip the standard 8255 port names while the numeric suffix 0 1 or 2 refers to the specific chip The 82C55 ports are addressed as follows ADDRESS PORT CONNECTOR BASE 0 0 P3 1 BO P3 BASE 2 P3 BASE 3 Control0 BASE 4 Al Pl BASE 5 Bl Pl BASE 6 Cl Pl BASE 7 Control 1 BASE 8 A2 P2 BASE 9 B2 P2 BASE A C2 P2 BASE B Control2 BASE C XXX BASE D XXX BASE E XXX BASE F XXX Page 12 4124M USER S MANUAL OPERATION CONNECTOR PIN OUT The 4I24M 50 pin I O connector pinouts are as follows P3 CONNECTOR PIN SIGNAL 1 AO bit 0 or 5V fused power W14 option 3 AO bit 1 5 AO bit 2 7 AO bit 3 9 AO bit 4 11 AO bit 5 13 AO bit 6 15 AO bit 7 17 BO bit 0 19 BO bit 1 21 BO bit 2 23 BO bit 3 25 80 bit 4 27 BO bit 5 29 80 bit 6 3l 80 bit 7 33 bit 0 35 CO bit 1 37 bit 2 39 bit 3 41 bit 4 43 bit 5 45 bit 6 47 bit 7 49 5V fused power GND W5 option All even pins connected to ground or open W1 option Page 13 4124M USER S MANUAL OPERATION P1 CONNECTOR PIN SIGNAL 1 Al bit O0 5 fused power W3 option 3 A bit 1 5 A bit 2 7 Al bit 3 9 Al bit 4 11 Al bit 5 13 Al bit 6 15 Al bit 7 17 B1 bit 0 19 Bl bit 1 21 Bl bit 2 23 Bl bit 3 25 81 bit 4 27 Bl bit 5 20 81 bit 6 31 bit 7 33 Cl bit 0 35 Cl bit 1 37 Cl bit 2 39 bit 3 41 bit 4 43 CI bit 5 45 CI bit 6 47 Cl bit 7 49 5V fused power GND W5 option
5. 4124M PARALLEL PORT MANUAL Version 1 0 Copyright 1997 by MESA ELECTRONICS Richmond CA Printed in the United States of America rights reserved This document and the data disclosed herein is not to be reproduced used disclosed in whole or in part to anyone without the written permission of MESA ELECTRONICS Mesa Electronics 4175 Lakeside Drive Suite 100 Richmond CA 94806 1950 Tel 510 223 9272 Fax 510 223 9585 E Mail tech mesanet com Website www mesanet com 4124M USER S MANUAL TABLE OF CONTENTS HANDLING PRECAUTIONS Stati electricity de ces duit i INTRODUCTION _ 2222223 _ lt _ _ _____ _ _ _ __ CONFIGURATION General ose ed x D fault jumper set IBS NUR EDEN E BaseaddressselectiOn i ic oe pee embedded Em AU RA Aliased address selection cree Pease eee snd NS I OpowetOptOBS pesa INSTALLATION General z e ee eto UO OO EIER UU HE 1 connector orientation 0 11 OPERATION M 12 DO Nus Ue xU DU cus VE 13 90 3 a a 16 REFERENCE INFORMATION ee
6. 6 pin headers with ISO standard pinout 24 I O bits per 26 pin connector pin 2 GND pin 26 5V The 4124M has I O module rack compatible pinouts with three 50 pin connectors each having 24 I O bits with interleaved grounds 5V power on the I O connectors is fused on the 4124 4124 models can use 16 bit stack through type PC 104 bus architecture Four layer circuit card construction is used to minimize radiated EMI and provide optimum ground and power integrity All CMOS design keeps power consumption to a minimum The 4124 requires only 5V for operation The 4124 base address is set with jumpers and can be located anywhere in the 1024 byte I O address space of the PC 104 bus 4I24 cards use 16 contiguous I O address s but where multiple cards are used an aliased addressing capability allows up to four 4I24 cards to share the same 10 bit base address conserving I O address space A partially loaded 48 bit version of the 4124 and 41241 can be provided if needed contact MESA for availability Page 4 4124M USER S MANUAL CONFIGURATION GENERAL The 4I24M port address and I O power connection options are set with jumpers Each group of jumpers will be discussed separately by function In the following discussions when the words up down right and left are used it is assumed that the 4I24M I O card is oriented with its bus connectors J1 and J2 at the bottom edge of the card nearest the person doing the configuratio
7. e data or shipping instructions will be forwarded to you 2 On receipt of the shipping instructions forward the product in its original protective packaging transportation prepaid to Mesa Electronics Repairs will be made at Mesa Electronics and the product returned transportation prepaid Page 18 4124 USER S MANUAL REFERENCE INFORMATION SCHEMATICS Page 19
8. e que sutura E vus oi 17 M 18 Schematic e aevo epu qu sU Vel EEE qa eius 19 4124M USER S MANUAL HANDLING PRECAUTIONS STATIC ELECTRICITY The CMOS integrated circuits on the 4I24M can be damaged by exposure to electrostatic discharges The following precautions should be taken when handling the 4I24M to prevent possible damage A Leavethe 4I24M in its antistatic bag until needed B All work should be performed at an antistatic workstation C Ground equipment into which 4I24M will be installed D Ground handling personnel with conductive bracelet through 1 megohm resistor to ground E Avoid wearing synthetic fabrics particularly Nylon 4124M USER S MANUAL INTRODUCTION GENERAL The MESA 4124 series of cards are 96 bit parallel I O interfaces implemented the PC 104 bus The 4124 uses 4 4124 41241 or 3 4124M socketed 82C55 PIO chips to give for a total of 96 I O bits 4124 41241 or 72 I O bits 4I24M 3 3K Pullup resistors are provided on all ports to simplify interfacing to contact closure opto isolators etc The 4I24 includes three models with different I O connectors The standard 4I24 uses two 50 pin headers for I O connections The 50 pin connectors each have 48 I O bits ground and power The 41241 uses four 2
9. l L 65 5 02 u4 U 5 FI amp RNQ c7 5 NN wi2 5 5 P3 1 6 U7 47 9 Wn Wis V15 V14 C12 ART REV A 42 2 Page 10 4124M USER S MANUAL INSTALLATION GENERAL When the 4I24M has been properly configured for its application it can be inserted into a PC 104 stack The standoffs should then be tightened to secure the 4124M in its place When the 4124M is secured in the stack the 50 pin headers can be plugged in from the sides I O CONNECTOR ORIENTATION The 50 pin connectors on the 4I24M have their pin one ends marked with a white square on the circuit card This corresponds with the colored stripe on typical flat cable assemblies If more positive polarization is desired center polarized IDC header connectors should be used These connectors will not fully mate with the pins on the 4I24M if installed backwards A suggested center polarized 50 pin IDC header is AMP PN 1 746285 0 Page 11 4124M USER S MANUAL OPERATION PORT MAPPING The 4I24M has three 82C55 chips Each 82C55 chip occupies four contiguous locations in I O space for a total of twelve I O locations but the 4I24M decoding scheme actually uses sixteen I O locations per 4I24M card with the last four locations per card not used In the following table and I O connector pinout tables the letters A B and C refer to individual ports on a 8255
10. n DEFAULT JUMPER SETTINGS Factory default 4124M jumpering is as follows FUNCTION JUMPER S SETTING 4124M power option w5 I O conns pin 49 gnd 4124M ground option W1 W4 W15 T O even pins gnd 4124M bit AO option W2 W3 W14 conns pin 1 bit AO 4124 Base address W6 W7 W8 W9 0200H W10 W11 4124 Aliased address W12 W13 0000H Page 5 4124M USER S MANUAL CONFIGURATION DEFAULT JUMPER SETTINGS RN8 RN5 Cg C6 RNIO a 5 o RN7 Ong C12 ART REV A Q Page 6 4124M USER S MANUAL CONFIGURATION BASE ADDRESS SELECTION The I O addresses of the three 82C55 s on the 4I24M are selected by placing shorting jumpers on jumper blocks W6 through W11 Jumper blocks W6 through W11 have three pins and two valid shorting jumper locations up and down The position of jumpers on W6 through W11 is a binary representation of the 4I24M base address When a jumper is in the up position it matches a high address line The following table shows some example base address settings BASE ADDRESS W6 W7 W8 W9 A9 A8 A7 A6 A5 A4 0200H Defa
11. osition in order to supply power to module racks When W2 W3 W14 are in the right hand position pin 1 is an I O bit This is the appropriate setting for 24 module I O racks This is also the default position ofthe pin 1 option jumpers GROUND OPTION JUMPERS Normally all even pins of the 4I24M 50 pin I O connectors are grounded at the 4I24M In some circumstances this may cause ground noise to be conducted into the system ground I O ground lines can be disconnected at the 4I24M if desired Jumper blocks W1 W4 and W15 select whether or not the even I O pins are grounded Jumper W4 selects the option for connector P1 jumper VV 15 selects the option for connector P2 and jumper W1 selects the option for connector When W1 W4 or W15 are in the left hand position all even pins ofthe associated connector will be disconnected from ground When W1 W4 W15 right hand position all even pins ofthe associated connector will be grounded at the 4I24M This is default setting ofthe ground option jumpers Page 9 4124M USER S MANUAL CONFIGURATION POWER OPTION JUMPERS RN5 v RN mm Wa amp C1 u
12. se 8255LOOP you must have a 50 conductor flat cable with female headers on each end Because the 4I24M has three I O connectors you must run 8255LOOP with 2 different cable arrangements First connect P3 and P1 together with the flat cable Make sure that the cable is properly polarized pinl to pin 1 Then run 8255LOOP Next connect the loopback cable to P1 and P2 and run 8255LOOP again 8255LOOP is invoked with 2 hexadecimal addresses on the command line These are the addresses ofthe two 8255 s that will be tested If a 4124 is set to its default 0200H address and has a good loopback cable installed the following sequence of commands will do a fairly thorough test of the card Connect loopback cabletoP3 and P 1 8255LOOP 200 204 connect loopback cabletoP 1 and P2 8255LOOP 204 208 Page 16 4124 USER S MANUAL REFERENCE INFORMATION SPECIFICATIONS POWER SUPPLY Voltage Supply current BUS LOADING Input capacitance Input leakage current Output drive capability Output sink current I O PORT LOADING Input logic low Input logic high Output low Output high ENVIRONMENTAL Operating temperature range version C version Relative humidity MIN 4 5 3 2 0 3 0 Page 17 MAX 3 5 50 85 70 90 UNIT V mA no ext load pF uA pF 2 5 mA sink 2 5 mA source lt lt lt lt C C Percent Non condensing 4124 USER S MANUAL REFERENCE INFORMATION
13. ult up down down down down down 0290H up down up down down up 0360H up up down up up down ALIASED ADDRESS SELECTION If multiple 4124M s are used in a single system I O address space can be conserved by using aliased address s Aliased addresses are an artifact caused by the partial only 10 bit address decoding used by most PC bus cards 4124M cards actually decode A15 and A14 in addition to AO through A9 This makes it possible to have up to four 4124M s located at what appears to other cards in the system to be a single 16 byte block of I O addresses This is done by selecting the same base addresses on all cards but selecting differing high order aliased addresses The aliased address used by a 4I24M is selected via shorting jumpers W12 and W13 Note that aliased addressing only makes sense when using multiple 4I24M s in a single system and when all base address s used are the same The following table shows allfour ofthe possible aliased address settings ALIASED ADDRESS W12 W13 A15 A14 BASE 0000H Default down down BASE 4000H down up BASE 8000H up down BASE C000H up up Page 7 4124M USER S MANUAL CONFIGURATION BASE AND ALIASED ADDRESS JUMPERS RN3
Download Pdf Manuals
Related Search