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Xilinx ISE In-Depth Tutorial

1. Priority Figure 6 5 INPUT JITTER Constraint Value 7 ClickOK 96 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 g XILINX Using the Constraints Editor The period constraint is displayed in the constraint table at the top of the window The period cell is updated with the global clock period constraint that you just defined with a default 50 duty cycle In the Constraint Type tree view select the Inputs branch under Timing Constraints Double click the clk signal in the Global OFFSET IN Constraint table to bring up the Create Setup Time OFFSET IN wizard 10 Keep the default values on the first page of the screen and click Next Wil Create Setup Time OFFSET IN Interface type System Synchronous SDR Rising System synchronous PERIOD ns gt Source synchronous 4 M Hit re gt ___ ow rx Data rate Sas Single data rate SDR ere enone es Double data rate DDR Data XK r Rising Data X X Clock edge RISING VALID Center aligned Edge aligned Rising edge O Falling edge Both edges The System Synchronous Single Data Rate SDR Rising Edge interface captures one word data per clock cycle using the rising clock edge The clock in the System Synchronous interface is typically the same for both the transmitting and receiving device To properly analyze this interface the rising clock edge registers m
2. 22 RST IN gt 23 CLKFX OUT gt 24 CLKIN IBUFG OUT gt 25 CLKO OUT gt 26 LOCKED OUT gt 27 m 28 Figure 3 20 VHDL DCM Component Instantiation Select Edit gt Copy Place the cursor below the following line in the stopwatch vhd file Insert dcm1 instantiation here 12 Select Edit Paste to paste the instantiation template ISE In Depth Tutorial UG695 v14 1 April 24 2012 www xilinx com 31 Chapter 3 HDL Based Design XILINX 13 Make the necessary changes as shown in the following figure ID Insert demi instantiation here 142 Inst dcmi demi PORT MAP 143 CLKIN IN clk 144 RST IN gt reset 145 CLKFX OUT gt clk_26214k 146 CLKIN IBUFG OUT open 147 CLKO OUT open 148 LOCKED OUT locked 149 Ve Figure 3 21 VHDL Instantiation for dcm1 14 Select File gt Save to save the stopwatch vhd file The dcm1 module should now appear beneath the stopwatch module in the design hierarchy Instantiating the dcm1 Macro Verilog To instantiate the dcm1 macro for your Verilog design do the following 1 Inthe Hierarchy pane of the Project Navigator Design panel select dcm1 xaw 2 Inthe Processes pane double click View HDL Instantiation Template 3 From the newly opened HDL Instantiation Template dcm1 tfi copy the instantiation template shown below 4 Instantiate the module 5 demi instance name 6 CLKIN IN CLKIN IN 7
3. Figure 8 4 Edit Preferences 138 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Using Boundary Scan Configuration Mode Performing Boundary Scan Operations You can perform Boundary Scan operations on one device at a time The available Boundary Scan operations vary based on the device and the configuration file that was applied to the device To see a list of the available options right click on any device in the chain This brings up a window with all of the available options When you select a device and perform an operation on that device all other devices in the chain are automatically placed in BYPASS or HIGHZ depending on your iMPACT Preferences setting For more information about Preferences see Editing Preferences To perform an operation right click on a device and select one of the options In this section you will retrieve the device ID and run the programming option to verify the first device as follows 1 Right click on the XC35700A device and select Get Device ID E ISE iMPACT 0 40b C examples_O wave_gen_vhd_s6 auto_project_1 ipf Boundary Scan BAR la File Edit View Operations Output Debug Window Help DAR BEX naX BRO IMPACT Flows 8 F stopwatch bit TE stopwatch2 mcs E SystemACE TDI f Create PROM File PROM File Formatter H WebTalk Data xc3s700a xcfO4s stopwatch bit stopwatch2 mcs iMPACT Processes ensx
4. Note The completed directories contain the finished HDL source files Do not overwrite any files in the completed directories This tutorial assumes that the files are unzipped under c xilinx_tutorial but you can unzip the source files into any directory with read write permissions If you unzip the files into a different location substitute your project path in the procedures that follow 14 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Getting Started Starting the ISE Design Suite To start the ISE Design Suite double click the Project Navigator icon on your desktop or select Start gt All Programs gt Xilinx ISE Design Suite gt Xilinx Design Suite 14 gt ISE Design Tools gt Project Navigator Figure 3 1 Project Navigator Desktop Icon Creating a New Project To create a new project using the New Project Wizard do the following 1 From Project Navigator select File gt New Project The New Project Wizard appears New Project Wizard Create New Project Specify project location and type Enter a name locations and comment For the project Name wtut_vhd Location C xilinx_tutorial wtut_vhd Working Directory C xilinx_tutorial wtut_vhd Description Select the type of top level source For the project Top level source type Hor Figure 3 2 New Project Wizard Create New Project Page 2 Inthe Location field browse to c xilinx_tutorial or t
5. Reset Options Page 30f3 Next gt Generate Cancel Figure 3 14 CORE Generator Tool Distributed Memory Generator Customization GUI Page 3 The module is created and automatically added to the project library A number of files are added to the ipcore_dir sub directory of the project directory Following is a list of some of these files ISE In Depth Tutorial UG695 v14 1 April 24 2012 timer_preset vho or timer_preset veo These are the instantiation templates used to incorporate the CORE Generator tool module into your source HDL timer_preset vhd or timer_preset v These are HDL wrapper files for the core and are used only for simulation timer preset ngc This file is the netlist that is used during the Translate phase of implementation timer preset xco This file stores the configuration information for the timer preset module and is used as the project source in the ISE project timer preset mif This file provides the initialization values of the ROM for simulation www xilinx com 27 Chapter 3 HDL Based Design XILINX Instantiating the CORE Generator Tool Module in the HDL Code Next instantiate the CORE Generator tool module in the HDL code using either a VHDL flow or a Verilog flow After instantiation the core module appears beneath the stopwatch module in the hierarchy VHDL Flow To instantiate the CORE Generator tool module using a VHDL flow do the following 1 I
6. System Settings No Errors Programming File Generated No Errors 8 Warnings 3 new All Signals Completely Routed All Constraints Met 0 Timing Report ha timer inst time cnt time cnt arch time cnt vhd fhg timer state statmach behavior statmach vhd E stopwatch ucf 8 Bitaen Messages E All Implementation Messages Detailed Reports E Synthesis Report E Translation Report Map Report E Place and Route Report E Post PAR Static Timing Report L Power Report Total Number of 4 input LUTS E Bitgen Report Secondary Reports Number used as logic E ISIM Simulator Log Number used as a route thru Number of bonded 1065 Design Properties Enable Message Filtering Number of BUFGMUXs Number of DCMs Optional Design Summary Contents Average Fanout of Non Clock Nets Number of Slice Flip Flops 1 Number of 4 input LUTs 3 Number of occupied Slices 4 Number of Slices containing only related logic 288 100 Number of Slices containing unrelated logic 288 0 11 776 3 QQ No Processes Running Processes stopwatch stopwatch arch E Design Summary Reports Design Utilities User Constraints Synthesize XST Show Clock Report Show Failing Constraints Map Place amp Route Q Generate Programming File KP _ Configure Target Device Generate Target PROM A
7. Figure 7 14 Restart Simulation Icon 2 AttheSim Console command prompt enter run 2000 ns and hit the Enter key lun 2000 ns Figure 7 15 Entering the Run Command The simulation will run for 2000 ns The waveforms for the DCM should now be visible in the Simulation window Analyzing the Signals Now the DCM signals can be analyzed to verify that they are working as expected The CLKO must be 50 Mhz and the CLKFX should be approximately 26 Mhz The DCM signals should only be analyzed after the LOCKED signal has gone high Until the LOCKED signal is high the DCM outputs are not valid ISim has the capability to add cursors to carefully measure the distance between signals To measure the CLKO do the following 1 If necessary zoom in on the waveform using the local Zoom toolbar buttons 2 Inthelocal waveform viewer toolbar click the Snap to Transition toolbar button m Figure 7 16 Snap to Transition Toolbar Button 3 Click on the first rising edge transition on the CLKO signal after the LOCKED signal has gone high then drag the cursor to the right to the next rising edge transition of the CLKO signal Atthe bottom of the waveform window the start point time end point time and delta times are shown The delta should read 20 0 ns This converts to 50 Mhz which is www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Vi b fF OO y X Yo Ye m e Jeu H ISE In Depth Tutorial
8. Instantiated components with no entity or module declaration are displayed with a question mark Hierarchy wtut_vhd S EJ xc3s700a 4fg484 m v i stopwatch stopwatch arch stopwatch vhd ha clk divider clk div 262k divide clk div 262k vhd ha Icd_cntrl_inst led control led control arch Ied_control vhd 12 mode debounce debounce 12 strtstop_debounce debounce 12 lap load debounce debounce ha timer _inst time cnt time cnt arch time cnt vhd ha timer state statmach behavior statmach vhd Figure 3 4 Hierarchy Panel Showing Completed Design Correcting HDL Errors The syntactical correctness of the files is checked as the files are added to the project and also when they are saved Messages are posted in the Console and in the Parser Messages section of the Design Summary and indicate the success or failure as each of the files is parsed The time cnt module contains a syntax error that must be corrected An ERROR message in the Console indicates the failure and provides a summary and the line number of the syntax problem To display the error in the source file do the following 1 Inthe Console or Errors panel click the file name in the error message The source code appears in the Workspace with a yellow arrow icon next to the line with the error 2 Correct any errors in the HDL source file The comments above the error explain this simple fix 3 Select File
9. UG695 v14 1 April 24 2012 XILINX Outputs Design Description mode Toggles between clocking and timer modes This input is only functional while the clock or timer is not counting lap_load This is a dual function signal In clocking mode it displays the current clock value in the Lap display area In timer mode it will load the pre assigned values from the ROM to the timer display when the timer is not counting The following are outputs signals for the design Icd e lcd rs lcd rw These outputs are the control signals for the LCD display of the Spartan 3A demo board used to display the stopwatch times sf d 7 0 Provides the data values for the LCD display Functional Blocks The completed design consists of the following functional blocks Most of these blocks do not appear on the schematic sheet in the project until after you create and add them to the schematic during this tutorial The completed design consists of the following functional blocks ISE In Depth Tutorial UG695 v14 1 April 24 2012 clk div 262k Macro which divides a clock frequency by 262 144 Converts 26 2144 MHz clock into 100 Hz 50 6 duty cycle clock dcm1 Clocking Wizard macro with internal feedback frequency controlled output and duty cycle correction The CLKFX_OUT output converts the 50 MHz clock of the Spartan 3A demo board to 26 2144 MHz debounce Module implementing a simplistic debounce circuit for the str
10. mode debounce stristop o R CLR Inputs CLKIN IN sig in sg out dk sg in sg out dk clk div 262k div 262144 LOCKED OUT xm CLKFX OUT dk in CLKIN IBUFG OUT CLKO OUT statmach exem dk dien er e em ok lap trigger lap load d ee reset Icd control anso rst a rst conel eee am cik m s a time_cnt mode ED 3119 hundred tis 3 0 i orehe 0 EU B w ___ On rl aaan aman Ss load tenths 39 sec Isb 32 jones 3 0 sec msb 30 Itens 3 0 st d 7 0 min utes 30 timer preset R50 spo 192 Figure 4 2 Completed Stopwatch Schematic After the design is complete you will simulate the design to verify its functionality For more information about simulating your design see Chapter 5 Behavioral Simulation There are five external inputs and four external outputs in the completed design The following sections summarize the inputs and outputs and their respective functions The following are input signals for the tutorial stopwatch design e strtstop Starts and stops the stopwatch This is an active low signal which acts like the start stop button on a runner s stopwatch reset Puts the stopwatch in clocking mode and resets the time to 0 00 00 e clk Externally generated system clock 44 www xilinx com ISE In Depth Tutorial
11. 1 Withthe time cnt schematic sheet open select Tools Symbol Wizard 2 Inthe Symbol Wizard select Using Schematic and select time cnt 3 Click Next then Next then Next and then Finish to use the wizard defaults 4 View and then close the time cnt symbol 56 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry Placing the time_cnt Symbol Next place the symbol that represents the macro on the top level schematic stopwatch sch as follows 1 In the Hierarchy pane of the Design panel double click stopwatch sch to open the schematic Select Add gt Symbol or click the Add Symbol toolbar button D Figure 4 15 Add Symbol Toolbar Button In the Symbol Browser select the local symbols library c Nxilinx tutorial Wwtut sc and then select the newly created time cnt symbol Place the time cnt symbol in the schematic so that the output pins line up with the five buses driving inputs to the Icd control component This should be close to grid position 1612 1728 Grid position is shown at the bottom right corner of the Project Navigator window and is updated as the cursor is moved around the schematic Note Do not worry about connecting nets to the input pins of the time cnt symbol You will do this after adding other components to the stopwatch schematic Save the changes and close stopwatch sch Creating a CORE Generator Tool Module The CORE Gener
12. Timing Simulation Using Xilinx ISim the input frequency from the test bench which in turn should be the DCM CLKO output 11110101 X1 408 408 ps X2 388 408 ps f AX 20 000 ps lt Parra gt rae ees Figure 7 17 Waveform Viewer Displaying Time Between Transitions 4 Measure CLKFX using the same steps as above The measurement should read 38 5 ns this equals approximately 26 Mhz Your timing simulation is complete and you are ready to program your device by following Chapter 8 Configuration Using iMPACT www xilinx com 131 UG695 v14 1 April 24 2012 Chapter 7 Timing Simulation XILINX 132 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Chapter 6 Configuration Using iMPACT Overview of iMPACT This chapter takes you on a tour of iMPACT a file generation and device programming tool iMPACT enables you to program through several parallel cables including the Platform Cable USB iMPACT can create bitstream files System ACE solution files PROM files and SVF XSVF files The SVF XSVF files can be played backed without having to recreate the chain Device Support For information on supported devices refer to the Xilinx Design Tools Release Notes Guide UG631 available from the Xilinx website Download Cable Support The following cables are supported Parallel Cable IV The Parallel Cable connects to the parallel p
13. E Design Summary Reports Design Utilities User Constraints tH CIA Synthesize XST S Q9 Implement Design E CAA Translate CAA Map E Generate Post Map Static Timing Analyze Post Map Static Timing Manually Place amp Route FPGA Editor C Generate Post Map Simulation Model Place amp Route C Generate Programming File a g Configure Target Device a Update Bitstream with Processor Data Analyze Design Using Chipscope Figure 6 17 Post Map Static Timing Report Process Timing Analyzer automatically launches and displays the report 3 Inthe Report Navigation pane select the TS_inst_dem1_CLKFX_BUF timing constraint For EDIF flow select TS dcm inst CLKFX BUF ee Timing constraints S TS clk PERIOD TIMEGRP clk 7 ns HIGH 50 INPUT JITTER 0 06 ns amp Component switching limits TS inst dcm1 CLKFX BUF PERIOD TIMEGRP inst dcm1 CLKFX BUF TS d OFFSET IN 6 ns VALID 6 ns BEFORE COMP clk RISING OFFSET OUT 38 ns AFTER COMP clk 4 TIMEGRP display grp OFFSET OUT 32 ns AFTER COMP clk Derived Constraint Report Constraint compliance H Data sheet report Trace settings amp Figure 6 18 Selecting Post Map Static Timing Constraint The Workspace shows the report for the selected constraint At the top of this report you will find the selected period constraint and the minimum period obtained by the tools after mapping By default onl
14. Provides access to editing location and timing constraints e Synthesis Provides access to Check Syntax Synthesis View RTL or Technology Schematic and synthesis reports Available processes vary depending on the synthesis tools you use Implement Design Provides access to implementation tools and post implementation analysis tools Generate Programming File Provides access to bitstream generation e Configure Target Device Provides access to configuration tools for creating programming files and programming the device The Processes pane incorporates dependency management technology The tools keep track of which processes have been run and which processes need to be run Graphical status indicators display the state of the flow at any given time When you select a process in the flow the software automatically runs the processes necessary to get to the desired step For example when you run the Implement Design process Project Navigator also runs the Synthesis process because implementation is dependent on up to date synthesis results To view a running log of command line arguments used on the current project expand Design Utilities and select View Command Line Log File See Command Line Implementation in Chapter 6 for further details Files Panel ISE In Depth Tutorial The Files panel provides a flat sortable list of all the source files in the project Files can be sorted by any of the columns in the view Prope
15. Revision 0 01 File Created aly Additional Comments ZEE O eEeeeeEEeeeeEe teet 20 library IEEE 21 use IEEE STD LOGIC 1164 ALL 22 use IEEE STD LOGIC ARITH ALL 23 use IEEE STD LOGIC UNSIGNED ALL 24 25 Uncomment the following library declaration if instantiating 26 any Xilinx primitives in this code 2 library UNISIM 28 use UNISIM VComponents all 29 30 entity debounce is 31 Port sig in in STD LOGIC 32 clk in STD LOGIC dd sig out out STD LOGIC 34 end debounce 35 36 architecture Behavioral of debounce is 37 38 begin 39 40 41 end Behavioral aye Figure 3 7 VHDL File in ISE Text Editor ISE In Depth Tutorial www xilinx com 21 UG695 v14 1 April 24 2012 Chapter 3 HDL Based Design XILINX Following is an example Verilog file al timescale ins ips EMM g II M IIMgIgIMllMllytKE FTT MET M MY M ATLA AAA Aaa EL LLL 3 Company 4 Engineer 6 Create Date 14 12 53 03 15 2007 7 Design Name 8 Module Name debounce 9 Project Name 10 Target Devices 11 Tool versions 12 Description 0000 14 Dependencies ooo 16 Revision 317 Revision 0 01 File Created 18 Additional Comments oo M 20 21 module debounce sig_in clk sig out 22 input sig in 23
16. XILINX 3 Select the clk_26214k Clock net to see the fanout of the clock net Figure 6 22 Clock Net 4 To exit FPGA Editor select File gt Exit Evaluating Post Layout Timing After the design is placed and routed you can analyze the post Place and Route timing results to verify how the design performs against your specified timing goals There are multiple ways in which you can analyze timing e View the Post Place and Route Static Timing Report e Use the PlanAhead tool for post Place and Route timing analysis e Use hyperlinks in the Design Summary to analyze individual timing constraints Viewing the Post Place and Route Static Timing Report This report evaluates the logical block delays and the routing delays The net delays are reported as actual routing delays after the Place and Route process To display this report do the following 1 Inthe upper left pane of the Design Summary Report Viewer select Static Timing in the Design Overview section Note Alternatively you can run the Analyze Post Place amp Route Static Timing process from the Processes pane Expand Implement Design Place amp Route Generate Post Place amp Route Static Timing to access this process 110 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Evaluating Post Layout Timing The Timing Report opens in Timing Analyzer Following is a summary of the post Place and Route Static Timin
17. XST H C Implement Design H E3 Generate Programming File EC Configure Target Device iO Generate Target PROM ACE File v ks Manage Configuration Project iMPACT i Update Bitstream with Processor Data ap Processes Figure 8 1 Opening iMPACT from Project Navigator Opening iMPACT Standalone To open iMPACT without going through an ISE project use one of the following methods e PConly Click Start gt All Programs gt Xilinx ISE Design Suite gt ISE Design Tools gt Tools gt iMPACT e PCor Linux Type impact at a command prompt Note To run applications from the command line you must configure the system environment to point to the ISE Design Suite To do this run the appropriate settings32 csh bat or settings64 csh bat file from the lt XILINX installation directory gt For more information refer to the Xilinx Design Tools Installation and Licensing Guide UG798 available from the Xilinx website Using Boundary Scan Configuration Mode For this tutorial you will be using the Boundary Scan configuration mode Boundary Scan configuration mode enables you to perform Boundary Scan operations on any chain comprising JTAG compliant devices The chain can consist of both Xilinx and non Xilinx devices however limited operations will be available for non Xilinx devices To perform operations the cable must be connected and the JTAG pins TDI TCK TMS and TDO must be connected from the cable to the b
18. and run the simulation for the time specified Note The majority of this design runs at 100 Hz and would take a significant amount of time to simulate This is why the counter will seem like it is not working in a short simulation For the purpose of this tutorial only the DCM signals will be monitored to verify that they work correctly Adding Signals To view signals during the simulation you must add them to the Wave window The ISE Design Suite automatically adds all the top level ports to the Wave window Additional signals are displayed in the Signal window based on the selected structure in the Structure window There are two basic methods for adding signals to the Simulator Wave window e Drag and drop from the Signal Object window Highlight signals in the Signal Object window and then select Add gt Wave gt Selected Signals ISE In Depth Tutorial www xilinx com 121 UG695 v14 1 April 24 2012 Chapter 7 Timing Simulation XILINX The following procedure explains how to add additional signals in the design hierarchy In this tutorial you will be adding the DCM signals to the waveform Note f you are using ModelSim version 6 0 or higher all the windows are docked by default All windows can be undocked by clicking the Undock icon g Figure 7 3 Undock Icon 1 IntheStructure Instance window expand the UUT hierarchy The following figure shows the Structure Instance window for the Schematic f
19. then Finish to complete the project creation Stopping the Tutorial You may stop the tutorial at any time and save your work by selecting File gt Save All 16 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Description Design Description Inputs Outputs The design used in this tutorial is a hierarchical HDL based design which means that the top level design file is an HDL file that references several other lower level macros The lower level macros are either HDL modules or IP modules The design begins as an unfinished design Throughout the tutorial you will complete the design by generating some of the modules from scratch and by completing others from existing files When the design is complete you will simulate it to verify the design functionality In the runner s stopwatch design there are five external inputs and four external output buses The system clock is an externally generated signal The following list summarizes the input and output signals of the design The following are input signals for the tutorial stopwatch design e strtstop Starts and stops the stopwatch This is an active low signal which acts like the start stop button on a runner s stopwatch reset Puts the stopwatch in clocking mode and resets the time to 0 00 00 e clk Externally generated system clock mode Toggles between clocking and timer modes This input is only functional whi
20. 120 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Timing Simulation Using ModelSim The properties should appear as shown in the following figure Set the Simulation Run Time property to 2000 ns Process Properties Simulation Properties Category Display Properties Simulation Model Properties XPower Analyzer Properties Simulation Properties Switch Name Property Name Compiled Library Directory Ignore Pre Compiled Library Warning Check Generate Verbose Library Compilation Messages Use Custom Do File Custom Do File Use Automatic Do File Delay Values To Be Read from SDF Other VSIM Command Line Options Other VLOG Command Line Options Other VCOM Command Line Options Simulation Run Time Simulation Resolution VHDL Syntax Value XILINX language gt simulator gt F v v Setup Time 2000ns Default 1 ps 93 Lise Fynlicit Declarations Onke mil Property display level Advanced Y v Display switch names Figure 7 2 Simulation Properties 8 Click OK to close the Process Properties dialog box Performing Simulation To start the timing simulation double click Simulate Post Place and Route Model in the Processes pane The ISE Design Suite will run NetGen to create the timing simulation model The ISE Design Suite will then call ModelSim and create the working directory compile the source files load the design
21. 24 2012 XILINX Design Entry Repeat step 2 and then click successively on the nets connected to the TC output to add tc_out0 tc_out1 tc out2 tc_out3 and tc out4 to these nets Note Each of the wires with identical names are now electrically connected In this case the nets do not need to be physically connected on the schematic to make the logical connection Finally connect the input pins of the counters through net name association as follows 1 Select Add Wire or click the Add Wire toolbar button and add a hanging net to the four data pins of each of the five counters Select Add Net Name or click the Add Net Name toolbar button In the Add Net Name Options that appear in the Options panel enter q 0 in the Name field Select Increase the name The net name q 0 is now attached to the cursor Click successively on each of the nets connected to data inputs starting from the top so that the net named q 0 is attached to the DO pin of the top counter and the net named q 19 is attached to the D3 pin of the bottom counter See the following figure monere m cd4rled ISE In Depth Tutorial UG695 v14 1 April 24 2012 Figure 4 13 Completed time_cnt Schematic Note If the nets appear disconnected select View gt Refresh to refresh the screen www xilinx com 55 Chapter 4 Schematic Based Design X
22. File Save As and enter the desired file name Sections of the command line log file can also be copied from source name cmd log using either the copy and paste method or the drag and drop method into a text file For a complete listing of command line options for most Xilinx executables refer to the Command Line Tools User Guide UG628 Command line options are organized according to implementation tools Command line options can also be obtained by typing the executable name followed by the h option at a command prompt ISE In Depth Tutorial www xilinx com 115 UG695 v14 1 April 24 2012 Chapter 6 Design Implementation XILINX 116 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Chapter 7 Timing Simulation Overview of Timing Simulation Flow Timing simulation uses the block and routing delay information from a routed design to give a more accurate assessment of the behavior of the circuit under worst case conditions For this reason timing simulation is performed after the design has been placed and routed Timing post Place and Route simulation is a highly recommended part of the HDL design flow for Xilinx devices Timing simulation uses the detailed timing and design layout information that is available after Place and Route This enables simulation of the design which closely matches the actual device operation Performing a timing simulation in addition to a static timing a
23. Generator Project E User Document debounce File name Verilog Module Verilog Test Fixture Eh VHDL Module C xilinx_tutorial wtut_vhd VHDL Library P VHDL Package Ma VHDL Test Bench Qa Embedded Processor Location Add to project Figure 3 5 New Source Wizard Select Source Type Page Click Next In the Define Module page enter two input ports named sig in and clk and an output port named sig out for the debounce component as follows In the first three Port Name fields enter s g in clk and sig out b Setthe Direction field to input for sig in and clk and to output for sig out www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry c Leave the Bus designation boxes unchecked New Source Wizard Define Module Specify ports for module Entity name debounce Architecture name Behavioral f A Port Name Direction sig_in clk sig out aa DD DD DIL se lt 4 Figure 3 6 New Source Wizard Define Module Page 6 Click Next to view a description of the module 7 Click Finish to open the empty HDL file in the ISE Text Editor Following is an example VHDL file Module Name debounce Behavioral 8 Project Name 9 Target Devices ZUMEM Tool versions qup Description 12 13 Dependencies 14 DEN Revision 16
24. RISING does not clock any registered input components WARNING Timing 3225 Timing constraint OFFSET IN 6 ns VALID 6 ns BEFORE COMP clk RISING ignored during timing analysis INFO Timing 3386 Intersecting Constraints found and resolved TSI report Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report For more information see the E Map Report E Place and Route Report E Post PAR Static Timing Report Power Report Device speed data version PRODUCTION 1 41 2009 03 03 Bitgen Report S Secondary Reports E Post Map Static Timing Report Design Summary Report Number of External IOBs 16 out of 372 45 Number of External Input IOBs 5 Figure 6 19 Place and Route Report Using FPGA Editor to Verify the Place and Route Use the FPGA Editor to display and configure Field Programmable Gate Arrays FPGAs The FPGA Editor reads and writes Native Circuit Description NCD files macro files NMC and Physical Constraints Files PCF Use FPGA Editor to do the following Place and route critical components before running the automatic Place and Route tools Finish placement and routing if the routing program does not completely route your design Add probes to your design to examine the signal states of the targeted device Probes are used to route the value of internal nets to an IOB Input Output Block for analysis during debugging of a device Run
25. RST IN RST IN 8 CLKFX OUT CLKFX OUT 3 CLKIN IBUFG OUT CLKIN IBUFG OUT i0 CLKO OUT CLKO OUT 11 LOCKED OUT LOCKED OUT 12 Ve Figure 3 22 dcm1 Macro and Instantiation Templates 4 Paste the instantiation template into the following section in the stopwatch v file Insert dcm1 instantiation here 5 Make the necessary changes as shown in the following figure 83 Insert dcmi instantiation here 84 85 demi inst dcmi 86 CLKIN IN clk 87 RST IN reset 88 CLKFX OUT clk 26214k 89 CLKIN IBUFG OUT 90 CLKO OUT 91 LOCKED OUT locked Figure 3 23 Verilog Instantiation for dcm1 6 Select File gt Save to save the stopwatch v file The dcm1 module should now appear beneath the stopwatch module in the design hierarchy 32 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Synthesizing the Design Synthesizing the Design So far you have been using Xilinx Synthesis Technology XST for syntax checking Next you will synthesize the design using either XST Synplify Synplify Pro or Precision software The synthesis tool uses the design s HDL code and generates a supported netlist type EDIF or NGC for the Xilinx implementation tools The synthesis tool performs the following general steps although all synthesis tools further break down these general steps to create the netlist e Analyze Check Syntax Checks the syntax of the source code e Compi
26. Scan window and select Add Xilinx Device or Add Non Xilinx device An Add Device dialog box opens allowing you to select a configuration file 3 Select stopwatch bit and then click Open The device is added where the large cursor is positioned To add a device between existing devices click on the line between them and then add the new device Repeat steps 2 and 3 to add the stopwatch mcs file to the chain Note The Boundary Scan chain that you manually create in the software must match the chain on the board even if you intend to program only some of the devices All devices must be represented in the IMPACT window Writing to the SVF File The process of writing to an SVF file is identical to performing Boundary Scan operations with a cable You simply right click on a device and select an operation Any number of operations can be written to an SVF file In this section you will be writing the device ID to the programming file for the first device and performing further instructions for the second device 144 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Creating an SVF File To write the device ID do the following 1 Right click the first device XC3S700A and select Get Device ID TDO Get Device Signature Usercode Assign New Configuration File Set Programming Properties Set Erase Properties Figure 8 12 Selecting a Boundary Scan Operation The instructions th
27. Using Timing Analysis to Evaluate Block Delays After Mapping The following figure shows the Design Summary Report Viewer E Design Overview Summary Spree ME o E 108 Properties ro wtut vhd xise E Module Level Utilization a o 7 Timing Constraints Pin xc3s700a 4f9484 o 00 6 Warnings 6 new Ud Q static Timing Errors and Warnings i8 E Parser Messages f n Xilinx Default unlocked 0 B Synthesis Messages z E Translation Messages ERE E Map Messages Pla Bitaen es 8 All Impl tion Messages Number of Slice Flip Flops 229 11 776 1 Detailed Reports 8 Synthesis Report Number of 4 input LUTs 371 11 776 3 E Translation Report Number of occupied Slices 285 5 888 4 E Map Report E Place and Rout Number of Slices containing only related logic 285 285 100 Number of Slices containing unrelated logic 0 285 0 D Total Number of 4 input LUTs 443 11 776 3 O Bitgen Report Secondary Reports Number used as logic 371 E 151M Simulator Loa Number used as a route thru 72 Number of bonded 108s 16 372 4 Number of BUFGMUXs 3 24 12 Number of DCMs 1 8 12 Design Properties Average Fanout of Non Clock Nets 3 43 Enable Message Filtering Optional Design Summary Conten
28. bit i stopwatch2 mcs SystemACE l Create PROM File PROM File Formatter tH WebTalk Data xc3s700a xcf 4s st atch bit st atch2 iMPACT Processes enasx opwatc opwatch2 mcs Available Operations are mb Program mb Get Device ID Get Device Signature Usercode Read Device Status One Step SYF mb One Step XSVF Program Succeeded Boundary Scan value of MODE pin MO value of MODE pin M1 value of MODE pin M2 value of CFG RDY INIT B DONEIN input from Done Pin SYNC word not found INFO iMPACT 2219 Status register values INFO iMPACT 0001 1111 1000 1100 INFO iMPACT 579 1 Completed downloading bit file to device INFO iMPACT 188 1 Programming completed successfully LCK cycle NoWait LCK cycle NoWait A INFO iMPACT 1 Checking done pin done 1 Programmed successfully PROGRESS END End Operation Elapsed time 1 sec lt E Console iQ Errors Warnings Configuration Platform Cable USB 6 MHz usb hs Figure 8 9 Programming Operation Complete Your design has been programmed and has been verified The board should now be working and should allow you to start stop and reset the runner s stopwatch ISE In Depth Tutorial UG695 v14 1 April 24 2012 www xilinx com 141 Chapter 8 Configuration Using iMPACT XILINX Troubleshooting Boundary Scan Configuration 142 The following sections assist you with troubleshooting err
29. compared to the BIT file using the MSK file that was created earlier 4 Click OK to begin programming E Device Programming Properties Device 2 Programming Properties Device 1 FPGA xc3s700a Property Name Verify General CPLD And PROM Properties Erase The Entire Device Read Protect PROM CoolRunner II Usercode 8 Hex Digits PROM Specific Properties Load FPGA Oo Figure 8 7 Program Options for XC3S700A Device Note The options available in the Device Programming Properties dialog box vary based on the device you have selected 140 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Using Boundary Scan Configuration Mode 5 Right click on the XC3S700A device and select Program The Programming operation begins and an operation status window appears At the same time the log window reports all of the operations being performed E Configuration Operation Status Executing command ooo 75 Figure 8 8 Operation Status When the Program operation completes a large blue message appears showing that programming was successful as shown in the following figure This message disappears after a few seconds E ISE iMPACT 0 40b C examples_O wave_gen_vhd_s6 auto_project_1 ipf Boundary Scan File Edit View Operations Output Debug Window Help El X 6 X zs 223 22 IMPACT Flows 28 Boundary Scan enasax stopwatch
30. desired frequency of the design To enter synthesis options do the following 1 Inthe Hierarchy pane of the Project Navigator Design panel select stopwatch vhd or stopwatch v 2 Inthe Processes pane right click the Synthesize process and select Process Properties 3 Under the Synthesis Options tab set the Netlist Hierarchy property to a value of Rebuilt Note To use this property you must set the Property display level to Advanced 4 Click OK Synthesizing the Design Now you are ready to synthesize your design To take the HDL code and generate a compatible netlist do the following 1 Inthe Hierarchy pane select stopwatch vhd or stopwatch v 2 Inthe Processes pane double click the Synthesize process www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Synthesizing the Design Using the RTL Technology Viewer XST can generate a schematic representation of the HDL code that you have entered A schematic view of the code helps you analyze your design by displaying a graphical connection between the various components that XST has inferred Following are the two forms of schematic representation RTL View Pre optimization of the HDL code Technology View Post synthesis view of the HDL design mapped to the target technology To view a schematic representation of your HDL code do the following 1 ISE In Depth Tutorial UG695 v14 1 April 24 2012 In the Processes
31. detail in the following sections www xilinx com 7 UG695 v14 1 April 24 2012 Chapter 2 Overview of the ISE Design Suite The following figure shows the Project Navigator interface ISE Project Navigator 14 1 C xilinx_tutorial wtut_vhd wtut_vhd xise Design Summary Programming File Generated Edit View Project Source Process Tools Window Layout jx a Help AA BRPALDAl Bmmyiu E B rf 9 XILINX ensx view Implementation O f simulation Hierarchy al wtut_vhd Ej F xc3s700a 4fg484 Mh stopwatch stopwatch_arch stopwatch vhd t preset timer preset ipcore_dir timer_preset xco AX Inst dcmi 0001 ipcore dirldcmt xaw u clk divider clk div 262k divide clk div 262k vhd ho lcd cntrl inst lcd control lcd control arch Icd control vhd h mode debounce debounce Behavioral debounce vhd fhg strtstop debounce debounce Behavioral debounce vhd hs lap load debounce debounce Behavioral debounce vhd EH EE En E fa E F Design Overview Summary E IOB Properties E Module Level Utilization E Timing Constraints E Pinout Report E Clock Report static Timing Errors and Warnings E Parser Messages E Synthesis Messages Translation Messages E Map Messages E Place and Route Messages E Timing Messages wtut vhd xise stopwatch xc3s700a 4f9484 ISE 14 1 Balanced Xilinx Default unlocked
32. green arrow to activate the next section In the Add Storage Device s section click the Auto Select PROM checkbox In the Enter Data section enter an Output File Name of stopwatch1 Verify that the Checksum Fill Value is set to FF and the File Format is MCS NOU RB E PROM File Formatter Step i Select Storage Target Step 2 Add Storage Device s Step 3 Enter Data Storage Device Type uU Sap er General File Detail Value xiinx Flash PROM Ane EH Checksum Fil Non Volatile FPGA Device bits xcf 1s 1 M value FF Spartan3AM amp SPI le Add Storage Device Remove Storage Device Output File Name stopwatch1 Configure MultiBoot FPGA l Output File F BPI Fh HR Location e tempalbtalbit projtbft proji E Configure MultiBoot FPGA i lleled Pio labile TR Flash PROM File Property Value File Format MCS Enable Revisioning Yes Number Of Revisions Enable Compression no 4 Auto Select PROM Figure 6 27 PROM File Formatter Click OK to close the PROM File Formatter In the Add Device dialog box click OK and then select the stopwatch bit file 10 Click No when you are asked if you would like to add another design file to the datastream 11 Click OK to complete the process 12 Select the device graphic in the workspace area 13 In the iMPACT Processes view double click Generate File 114 www xilinx com ISE In Depth Tutorial UG695 v14 1 A
33. has been created you have the option of tapping this bus off to use each signal individually The next step is to create buses for each of the five outputs of the time cnt schematic The results can be found in the completed schematic www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry To add the buses hundredths 3 0 tenths 3 0 sec_Isb 3 0 sec msb 3 0 and minutes 3 0 to the schematic perform the following steps 1 Selectall of the output I O markers by drawing a box around them and then drag the group so that minutes 3 0 is below the Q3 output of the bottom counter block 2 Select Add Wire or click the Add Wire toolbar button 3 Click in the open space just above and to the right of the top cd4rled and then click again on the pin of the hundredths 3 0 I O marker The thick line should automatically be drawn to represent a bus with the name matching that of the I O marker cd4rled Figure 4 10 Adding a Bus 4 Repeat Steps 2 and 3 for the four remaining buses 5 After adding the five buses press Esc or right click at the end of the bus to exit the Add Wire mode Adding Bus Taps ISE In Depth Tutorial Next add nets to attach the appropriate pins from the cd4rled and ch4rled counters to the buses Use bus taps to tap off a single bit of a bus and connect it to another component Note Zooming in on the schematic enables greater precision when drawing the
34. here 170 Begin Cut here for INSTANTIATION Template INST T G 171 t_preset timer_preset 172 port map 173 a gt address 174 spo gt preset time ESL INST TAG END End INSTANTIATION Template Figure 3 16 VHDL Component Instantiation of CORE Generator Tool Module 10 The inserted code of timer preset vho contains several lines of commented text for instruction and legal documentation Delete these commented lines if desired 11 Save the design using File Save and close the ISE Text Editor 28 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry Verilog Flow To instantiate the CORE Generator tool module using a Verilog flow do the following 1 2 In Project Navigator double click stopwatch v to open the file in the ISE Text Editor Place the cursor after the following line Place the Coregen module instantiation for timer_preset her Select Edit gt Insert File and select ipcore_dir timer_preset veo The inserted code of timer preset veo contains several lines of commented text for instruction and legal documentation Delete these commented lines if desired Change the instance name from your instance name tot preset Edit this code to connect the signals in the stopwatch design to the ports of the CORE Generator tool module as shown below 36 Place the Coregen module instantiation for timer preset here
35. in the ModelSim installation directory is used ModelSim PE SE or DE If you are using ModelSim PE SE or DE refer to the Command Line Tools User Guide UG628 and use Compxlib to compile the libraries While compiling the libraries Compxlib also updates the modelsim ini file with the correct library mapping Open the modelsim ini file and make sure that the library mappings are correct For future projects you can copy the modelsim ini file to the working directory and make changes that are specific to that project or you can use the MODELSIM environment variable to point to the desired modelsim ini file ISim The modelsim ini file is not applicable to ISim ISE In Depth Tutorial www xilinx com 77 UG695 v14 1 April 24 2012 Chapter 5 Behavioral Simulation XILINX Adding an HDL Test Bench To add an HDL test bench to your design project you can either add a test bench file provided with this tutorial or create your own test bench file and add it to your project Adding the Tutorial Test Bench File This section demonstrates how to add an existing test bench file to the project A VHDL test bench and Verilog test fixture are provided with this tutorial Note To create your own test bench file in Project Navigator select Project gt New Source and select either VHDL Test Bench or Verilog Text Fixture in the New Source Wizard An empty stimulus file is added to your project You must define the test bench in a
36. in the following figure Module Name debounce Behavioral Project Name Target Devices Tool versions Description Dependencies Revision Revision 0 01 File Created Additional Comments library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL Uncomment the following library declaration if instantiating any Xilinx primitives in this code library UNISIM use UNISIM VComponents all entity debounce is Port sig in in STD LOGIC elk in STD LOGIC sig out out STD LOGIC end debounce architecture Behavioral of debounce is begin end Behavioral Figure 4 21 VHDL File in ISE Text Editor The Verilog HDL file is shown in the following figure 1 timescale ins ips 2 JI gMIIPPgSETPIPIg IMMIIIPgMIIMIIBgMNEMNIMIgNIIP Cg VIII EA EAE 3 Company 4 Engineer EE 6 Create Date 14 12 53 03 15 2007 7 Design Name 8 Module Name debounce 9 Project Name 10 Target Devices 11 Tool versions 12 Description 0000 14 Dependencies omen 16 Revision 1 Revision 0 01 File Created 18 Additional Comments 19 fi 20 CGC rail module debounce sig_in clk sig out 22 input sig_in 23 input clk 24 output sig_out 25 26 27 endmodule 28 Figure 4 22 Verilog File in ISE Text Editor ISE In Depth Tutorial UG695 v14 1 April 2
37. input clk 24 output sig_out 27 endmodule Figure 3 8 Verilog File in ISE Text Editor In the ISE Text Editor the ports are already declared in the HDL file and some of the basic file structure is already in place Keywords are displayed in blue comments in green and values are black The file is color coded to enhance readability and help you recognize typographical errors Using the Language Templates The ISE Language Templates include HDL constructs and synthesis templates which represent commonly used logic components such as counters D flip flops multiplexers and primitives You will use the Debounce Circuit template for this exercise Note You can add your own templates to the Language Templates for components or constructs that you use often To invoke the Language Templates and select the template for this tutorial do the following 1 From Project Navigator select Edit gt Language Templates Each HDL language in the Language Templates is divided into five sections Common Constructs Device Macro Instantiation Device Primitive Instantiation Simulation Constructs Synthesis Constructs and User Templates To expand the view of any of these sections click the plus symbol next to the section Click any of the listed templates to view the template contents in the right pane 2 Under either the VHDL or Verilog hierarchy expand Synthesis Constructs expand Coding Examples expand Misc and select the templat
38. it easier to differentiate the signals To add a divider called DCM Signals do the following 1 Right click anywhere in the signal section of the Wave window If necessary undock the window and maximize the window for a larger view of the waveform 2 Select Insert Divider 3 Enter DCM Signals in the Divider Name box 4 Click OK 5 Click and drag the newly created divider to above the CLKIN_IN signal After adding the DCM Signals divider the waveform will appear as shown in the following figure Istopwatch tb clk Istopwatch tb lap load stopwatch_tb mode Istopwatch tb reset Istopwatch tb strtstop Istopwatch tb lcd e Istopwatch tb lcd rs Istopwatch tbiled rw Ex stopwatch_tb sf_d DCM Signals stopwatch_tb uut dem_inst clkin_in Istopwatch tb uutidcm inst clk aut Istopwatch tb uut dcm inst clkfx out Istopwatch tb uut dem inst locked out Istopwatch tb uut dem inst rst in Figure 5 6 Waveform After Adding DCM Signals Divider The waveforms have not been drawn for any of the newly added signals This is because ModelSim did not record the data for these signals By default ModelSim records data only for the signals that are added to the Wave window while the simulation is running After new signals are added to the Wave window you must rerun the simulation for the desired amount of time Rerunning Simulation ISE In Depth Tutorial To rerun simulation in ModelSim do the following 1 Click the Resta
39. netlist file exists for the stopwatch design To continue with the HDL flow do either of the following e Go to Chapter 5 Behavioral Simulation to perform a pre synthesis simulation of this design e Proceed to Chapter 6 Design Implementation to place and route the design ISE In Depth Tutorial www xilinx com 39 UG695 v14 1 April 24 2012 Chapter 3 HDL Based Design 40 www xilinx com XILINX ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Chapter 4 Schematic Based Design Overview of Schematic Based Design This chapter guides you through a typical FPGA schematic based design procedure using the design of a runner s stopwatch The design example used in this tutorial demonstrates many device features software features and design flow practices that you can apply to your own designs The stopwatch design targets a Spartan 3A device however all of the principles and flows taught are applicable to any Xilinx device family unless otherwise noted This chapter is the first in the Schematic Design Flow In the first part of the tutorial you will use the ISE design entry tools to complete the design The design is composed of schematic elements CORE Generator tool components and HDL macros After the design is successfully entered in the Schematic Editor you will perform behavioral simulation Chapter 5 Behavioral Simulation run implementation with the Xilinx implementati
40. of each property click the Help button For this tutorial the default Simulation Model Properties are used Select the ISim Properties category These properties set the options the simulator uses to run the timing simulation For a description of each property click the Help button www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 g XILINX Timing Simulation Using Xilinx ISim The properties should appear as shown in the following figure Set the Simulation Run Time property to 2000 ns Process Properties ISim Properties Category Switch Name Property Name Isim Properties Use Custom Simulation Command File Simulation Model Properties XPower Analyzer Properties Custom Simulation Command File incremental Incremental Compilation nodebug Compile For HDL Debugging Use Custom Project File prj Custom Project Filename Run for Specified Time v Simulation Run Time 2bo0 ns Waveform Database Filename _vhdistopwatch_tb_isim_par wdb 23 Lise Custom Waveform Configuration File Custom Waveform Configuration File Generate SAIF File for Power Optimization Estimation SAIF File Name wtut_vhd xpower_time_sim saif Delay Values To Be Read from SDF Setup Time v Other Compiler Options rangecheck Value Range Check i Specify Search Directories For Include Ju l d Specify define Macro Name and Value Specify Top Level Instance Na
41. of the ISE Design Suite Software Overview The ISE Design Suite controls all aspects of the design flow Through the Project Navigator interface you can access all of the design entry and design implementation tools You can also access the files and documents associated with your project Project Navigator Interface ISE In Depth Tutorial By default the Project Navigator interface is divided into four panel sub windows as seen in Figure 2 1 On the top left are the Start Design Files and Libraries panels which include display and access to the source files in the project as well as access to running processes for the currently selected source The Start panel provides quick access to opening projects as well as frequently access reference material documentation and tutorials At the bottom of the Project Navigator are the Console Errors and Warnings panels which display status messages errors and warnings To the right is a multi document interface MDI window referred to as the Workspace The Workspace enables you to view design reports text files schematics and simulation waveforms Each window can be resized undocked from Project Navigator moved to a new location within the main Project Navigator window tiled layered or closed You can use the View gt Panels menu commands to open or close panels You can use the Layout gt Load Default Layout to restore the default window layout These windows are discussed in more
42. of the Limited Warranties which can be viewed at http www xilinx com warranty htm IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx Xilinx products are not designed or intended to be fail safe or for use in any application requiring fail safe performance you assume sole risk and liability for use of Xilinx products in Critical Applications http www xilinx com warranty htm critapps Copyright 2012 Xilinx Inc Xilinx the Xilinx logo Artix ISE Kintex Spartan Virtex Vivado Zynq and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 03 01 11 13 1 Changed tutorial directory to c xilinx_tutorial Updated CORE Generator tool graphics Updated third party synthesis tool versions 10 19 11 13 3 Revalidated for the 13 3 release Editorial updates only no technical content updates 01 18 12 13 4 Revalidated for the 13 4 release Editorial updates only no technical content updates 04 24 12 14 1 Revalidated for the 14 1 release Editorial updates only no technical content updates ISE In Depth Tutorial www xilinx com UG695 v14 1 April 24 2012 Table of Contents Beviston History ues ed vea ed he adn ea pa Roe en
43. pane expand Synthesize and double click View RTL Schematic or View Technology Schematic If the Set RTL Tech Viewer Startup Mode dialog appears select Start with the Explorer Wizard In the Create Schematic start page select the clk_divider and lap_load_debounce components from the Available Elements list and then click the Add button to move the selected items to the Selected Elements list Click Create Schematic Create RTL Schematic 1 Select items you want on the schematic from the Available Elements list and move them to the Selected Elements list Use the Filter control to filter the Available Elements list by name 2 Press the Create Schematic button to generate a schematic view using the items in the Selected Elements list Available Elements Selected Elements S gl stopwatch ck divider He LJ Primitives lap load debounce w LJ Signals J Top Level Ports GE a clk divider Remove al tH gh Inst demi 7 E lap load debounce iE led_cntrl_inst Hg mode debounce ic a strtstop_debounce tH gh timer inst Ez E timer state i Create Schematic Figure 3 25 Create RTL Schematic Start Page www xilinx com 35 Chapter 3 HDL Based Design XILINX 36 The schematic viewer allows you to select the portions of the design to display as schematics When the schematic is displayed double click on the symbol to push into the schemati
44. that the hardware is not set up correctly or the cable is not properly connected If the chain can be initialized try performing simple operations For example try getting the Device ID of every device in the chain If this can be done then the hardware is set up correctly and the cable is properly connected www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Creating an SVF File The debug chain can also be used to manually enter JTAG commands as shown in the following figure This can be used for testing commands and verifying that the chain is set up correctly To use this feature select Debug gt Enable Disable Debug Chain in iMPACT ISE iMPACT 0 40b C xilinx_tutorial wtut_sc stopwatch ipf Boundary Scan File Edit View Operations Output Debug Window Help zx RBIS TAN iMPACT Flows ensx SystemACE 0 E Create PROM File PROM File Formatter EX Run Tesuildie Select DR Scan 1 m 53 wshTalk Data iMPACT Processes eogx 1 Capture DR Capture IR Avallable Operations are Ow a ea 4 xc3s700a xcf 4s 90008 00 m Program J stopwatch bit stopwatch mcs SUME ERE SH m Get Device ID TDO a E 00 Get Device Sinnatirell kercade A Exitt DR H 60046 H IMPACT Boundary Scan Chain Debug eoex 9 io Non debug iMPACT oper
45. the BitGen program and download the resulting bitstream file to the targeted device View and change the nets connected to the capture units of an Integrated Logic Analyzer ILA core in your design 108 ISE In Depth Tutorial UG695 v14 1 April 24 2012 www xilinx com XILINX Using FPGA Editor to Verify the Place and Route To view the actual design layout of the FPGA do the following 1 Inthe Processes pane of the Project Navigator Design panel expand Place amp Route and double click View Edit Routed Design FPGA Editor E PAAA Synthesize XST E PAA Implement Design fH CIA Translate E nA Map Q Place amp Route E CIO Generate Post Place amp Route Static Timing Analyze Timing Floorplan Design Plan head View Edit Routed Design FPGA Editor im XPower Analyzer LA Canneska Dime Maka Figure 6 20 View Edit Routed Design FPGA Editor Process 2 In FPGA Editor change the List Window from All Components to All Nets This enables you to view all of the possible nets in the design Ss LM DORN AI Nets Placed Components Unplaced Components Component Groups All Hard Macros Placed Hard Macros Unplaced Hard Macros All Hard Macro External Pins addressc address lt 1 gt address lt 2 gt address lt 3 gt Figure 6 21 List Window in FPGA Editor ISE In Depth Tutorial www xilinx com 109 UG695 v14 1 April 24 2012 Chapter 6 Design Implementation
46. the inputs and outputs will be locked to specific pins in order to place and download the design to the Spartan 3A demo board Because the tutorial stopwatch design is simple and timing is not critical the example pin assignments will not adversely affect the ability of PAR to place and route the design Assign a LOC parameter to the output nets on the stopwatch schematic as follows 1 2 3 Right click on the clk net and select Object Properties In the Object Properties dialog box click the New button In the New Attribute dialog box enter LOC for the Attribute Name and E12 for the Attribute Value www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 g XILINX Design Entry 4 Click OK to return to the Object Properties dialog box amp Object Properties Net Attributes Category View and edit the attributes of the selected nets Enets Name Value Visible Name clk Edit Traits PortPolarity Input Loc E12 Delete Figure 4 30 Assigning Pin Locations 5 To make the LOC attribute visible select the Add button next to the LOC attribute 6 Inthe Net Attribute Visibility dialog box click on a location near the center of the displayed net and then click OK This will display the LOC attribute on the schematic above the clk net 7 Click OK to close the Object Properties dialog box The above procedure constrains clk to pin E12 Notice that the LOC pro
47. those data pins defined in the Pad Group 6 new Pad Group may be defined by selecting the Create New Pad Group Input register timegroup button i i Rising Constraint Parameters Falling edge constraints e The rising edge constraint applies to all rising edge registers and the clock and External setup time offset in data relationship is specified in reference to the rising clock edge Rising External Setup OFFSET IN is the time before the rising clock edge when Data valid duration E the rising data becomes valid e Rising VALID is the duration of the data valid window for the rising data Input register timegroup e The Input Register Group is used to limit the scope of the constraint to a subset of the rising edge registers v Figure 6 7 Offset In Constraint Page 2 14 In the Constraint Type tree view select the Outputs branch under Timing Constraints 15 In the Global OFFSET OUT Constraint table double click the clk signal 16 In the Create Clock to Pad OFFSET OUT dialog box enter a value of 38 ns in the External clock to pad offset out field This creates a Global OFFSET OUT constraint for the CLK signal 98 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Using the Constraints Editor 17 Click OK Create Clock to Pad OFFSET OUT Clock pad net and period SDR both edges DDR Output
48. to more easily see and understand each step During translation the NGDBuild program performs the following functions e Converts input design netlists and writes results to a single merged NGD netlist The merged netlist describes the logic in the design as well as any location and timing constraints e Performs timing specification and logical design rule checks e Adds constraints from the User Constraints File UCF to the merged netlist 94 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Using the Constraints Editor Using the Constraints Editor ISE In Depth Tutorial When you run the Create Timing Constraints process Translate is automatically run and the ISE Design Suite launches the Constraints Editor The Constraints Editor enables you to do the following e Edit constraints previously defined in a UCF file e Add new constraints to your design Following are input files to the Constraints Editor e NGD Native Generic Database File The NGD file serves as input to the mapper which then outputs the physical design database an NCD Native Circuit Description file e Corresponding UCF User Constraint File All UCF files that are part of the ISE project are passed to Constraints Editor Multiple UCF files are supported in ISE projects All constraint files in the project are read by the Constraints Editor and constraints that you edit are updated in the originating constraint f
49. x El WW stopwatch Nets 104 H E Primitives 29 S E clk divider div 262k Inst dernl derni 3i lap load debounce Crap p t E timer inst E timer state STATMACH 44K Properties fi 3 Properties Clock Regions 1 0 Ports A Name Direction Neg Diff Pair Sie Fixed Bank I O Std Vcco Vref Drive Strength Slew Type Pull Type pnm Al ports 16 H sf d 8 Output 2 default LYCMOS25 2 5 12 SLOW NONE iP Scalar ports 8 D ck Input 0 default LVCMOS25 12 SLOW NONE D lap load Input default LVCMOS25 12 SLOW NONE miia lasni E datant AERC OEY sacia sone Ed Td Console 1 Package Pins D 1 0 Ports Figure 6 12 PlanAhead Tool for I O Planning 4 IntheI O Ports tab expand the Scalar Ports tree under All ports You will now create pin assignments for the 1cd e 1cd rs and 1cd rw I O signals 5 Locate the lcd e output signal then click and drag it into the Package view and drop it on the AB4 pin location Place lcd e at AB4 Site Type IO L 6P 2 Bank 2 Figure 6 13 Assigning I O Pins by Dragging into Package View 6 Repeat the previous step to place the following additional output pins 102 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Mapping the Design e LCD_RS Y14 e LCD_RW W13 Alternatively you can type
50. 1 April 24 2012 g XILINX Design Description e Synthesis Tool XST VHDL Verilog e Simulator ISim VHDL Verilog e Preferred Language VHDL or Verilog depending on preference This will determine the default language for all processes that generate HDL files Other properties can be left at their default values 6 Click Next then Finish to complete the project creation Stopping the Tutorial If you need to stop the tutorial at any time save your work by selecting File gt Save All Design Description The design used in this tutorial is a hierarchical schematic based design which means that the top level design file is a schematic sheet that refers to several other lower level macros The lower level macros are a variety of different types of modules including schematic based modules a CORE Generator tool module an Architecture Wizard module and HDL modules The runner s stopwatch design begins as an unfinished design Throughout the tutorial you will complete the design by creating some of the modules and by completing others from existing files Through the course of this chapter you will create these modules instantiate them and then connect them The following figure shows a schematic of the completed stopwatch design ISE In Depth Tutorial www xilinx com 43 UG695 v14 1 April 24 2012 Chapter 4 Schematic Based Design XILINX debounce sig in sg out dk debounce
51. 2 Expand the UUT hierarchy ISE In Depth Tutorial www xilinx com 127 UG695 v14 1 April 24 2012 Chapter 7 Timing Simulation XILINX 3 Locate and select one of the following signals e For VHDL flow select inst dcm1 DCM SP INST e For Verilog flow select inst dcm1 DCM SP INST e For schematic flow select dcm inst DCM SP INST e For EDIF flow using stopwatch tb vhd select dem inst DCM INST DCM SP 4 Inthe Objects window right click the locked signal and select Add to Wave Window The following figure shows the Simulation Instances and Simulation Objects window for the VHDL flow The signal names and layout in the Simulation Instances window for a schematic or Verilog flow may be different ea File Edit view Simulation Window Layout Help Dg E LEkzaDBBx ve MK OFAN Aw AP BA Instances and Processes O amp X objects H dx I c cs Simulation Objects For Inst dcm1 D 2 8 aeaaaee A A L3 a 1B w es gt Instance and Process Name Design Unit Block Type M 1j sf d 4 oBuF x obuf x obu VHDL Entity Object Name Value J ij sf d 5 08 x obuf x obu VHDL Entity 1H cko o i sf d 6 OBUF x obuf x obu VHDL Entity 1E dkiso T ij sf d 7 oeur x obuf x obu VHDL Entity li dk270 o 9 i reset IBUF x buf x buf v VHDL Entity UB clk2x 1 i 1j lap load IBUF x buf x buf v VHDL Entity US dk2x180 il lcd rs OBUF x obuf x obu VHDL Entity
52. 37 Begin Cut here for INSTANTIATION Template INST_TAG 38 timer preset t preset 39 a address Bus 5 0 40 spo preset time Bus 19 0 41 42 INST T G END End INSTANTIATION Template Figure 3 17 Verilog Component Instantiation of the CORE Generator Tool Module 7 Save the design using File gt Save and close the ISE Text Editor Creating a DCM Module The Clocking Wizard a part of the Xilinx Architecture Wizard enables you to graphically select Digital Clock Manager DCM features that you want to use In this section you will create a basic DCM module with CLKO feedback and duty cycle correction Using the Clocking Wizard To create the dcm1 module do the following 1 2 ISE In Depth Tutorial UG695 v14 1 April 24 2012 In Project Navigator select Project gt New Source In the New Source Wizard select IP CoreGen amp Architecture Wizard source and enter dem1 for the file name Click Next www xilinx com 29 Chapter 3 HDL Based Design 4 11 12 13 14 15 16 30 XILINX In the Select IP dialog box select FPGA Features and Design gt Clocking gt Spartan 3E Spartan 3A gt Single DCM SP New Source Wizard Select IP Create Coregen or Architecture Wizard IP Core View by Function View by Name Name gt Version AxI AXI4 Stream AXI4 Lite Status License v tH Embedded Processing FPGA Features and Desig
53. 4 2012 www xilinx com 63 Chapter 4 Schematic Based Design XILINX In the ISE Text Editor the ports are already declared in the HDL file and some of the basic file structure is already in place Keywords are displayed in blue comments in green and values are black The file is color coded to enhance readability and help you recognize typographical errors Using the Language Templates The ISE Language Templates include HDL constructs and synthesis templates which represent commonly used logic components such as counters D flip flops multiplexers and primitives You will use the Debounce Circuit template for this exercise Note You can add your own templates to the Language Templates for components or constructs that you use often To invoke the Language Templates and select the template for this tutorial do the following 1 From Project Navigator select Edit gt Language Templates Each HDL language in the Language Templates is divided into the following sections Common Constructs Device Macro Instantiation Device Primitive Instantiation Simulation Constructs Synthesis Constructs and User Templates To expand the view of any of these sections click the plus symbol next to the section Click any of the listed templates to view the template contents in the right pane 2 Under either the VHDL or Verilog hierarchy expand Synthesis Constructs expand Coding Examples expand Misc and select the templa
54. ACT 0 40b Boundary Scan We File Edit per ing H xaeaxszsz ss xil iMPACT Flows 708 x E BE Boundary Scan SystemACE amp Create PROM File PROM File Formatter w WebTalk Data e xc3s700a xct04s bypass bypass Assign New Configuration File O C xilinx_tutorial wtut_sc Look in o o 369 4d My Computer O ngo F _xmsgs iMPACT Processes a howardp Available Operations are ipcore dir O iseconfig isim O wtut sc completed O xInx auto 0 xdb xst File name stopwatch bit Console Cancel Bypass PROGRESS END Ef files of type All Design Files bit rbt nky isc bsd Elapsed time BATCH CMD Console o Errors IA Warnings Cancel All Configuration Platform Cable USB 6 MHz usb hs Figure 8 3 Selecting a Configuration File Note If a configuration file is not available a Boundary Scan Description File BSDL or BSD file can be applied instead The BSDL file provides the software with the necessary Boundary Scan information that allows a subset of the Boundary Scan operations to be available for that device To have the ISE Design Suite automatically select a BSDL file for both Xilinx and non Xilinx devices select Bypass in the Assign New Configuration File dialog box When the software prompts you to select a configuration file for the second d
55. Allocates CLB and IOB resources for all basic logic elements in the design e Processes all location and timing constraints performs target device optimizations and runs a design rule check on the resulting mapped netlist ISE In Depth Tutorial www xilinx com 103 UG695 v14 1 April 24 2012 Chapter 6 Design Implementation XILINX Each step generates its own report as shown in the following table Table 6 2 Reports Generated by Translate and Map Report Translation Report Description Includes warning and error messages from the translation process Map Report Includes information about how the target device resources are allocated references to trimmed logic and device utilization All NGDBuild and Map Reports For detailed information on the Map reports refer to the Command Line Tools User Guide UG628 To view a report do the following 1 Inthe Processes pane of the Project Navigator Design panel double click Design Summary Reports Processes stopwatch stopwatch_arch Design Summary Reports H Design Utilities iE User Constraints E CAA Synthesize XST w C Implement Design T Generate Programming File a Configure Target Device Update Bitstream with Processor Data eu Analyze Design Using Chipscope Figure 6 15 Opening the Design Summary Reports 104 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX
56. CE File f Manage Configuration Project iMPACT Analyze Design Using ChipScope Show Warnings Show Errors 0 Setup 0 Hold 0 Component Switching Limit 0 All Signals Completely Routed All Constraints Met x Design Summary Programming File Generated 8 Pinout Report Clock Report gt Start IR Design Files D Libraries Console Started Generate Programming File Running bitgen Command Line bitgen intstyle ise f stopwatch ut stopwatch ncd 4 INFO PhysDesignRules 772 To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp Inst dcmi DCM SP INST consult the device Interactive Data Sheet Process Generate Programming File completed successfully lt E Console Errors Warnings Find in Files Results Figure 2 1 Project Navigator Design Panel The Design panel provides access to the View Hierarchy and Processes panes View Pane The View pane radio buttons enable you to view the source modules associated with the Implementation or Simulation Design View in the Hierarchy pane If you select Simulation you must select a simulation phase from the drop down list Hierarchy Pane The Hierarchy pane displays the project name the target device user documents and design source files associated with the selected Design View The View pane at the top of the Design pan
57. Distributed Memory Generator View Documents IP Symbol ax Distributed Memory Ue J lagi FF Generato r xilinx com ip dist mem gen 7 1 Input Options Non Registered O Registered Input Clock Enable Qualify WE with I CE 19 0 EA Dual Port Address dpo 19 0 Non Registered ipo 19 0 Output Options Non Registered Registered Common Output CLI Single Port Output CE Common Output CE Dual Port Output CE Pipelining Options jp Is il Pipeline Stages 0 Page2o0f3 Next Generate Cancel Help Figure 3 13 CORE Generator Tool Distributed Memory Generator Customization GUI Page 2 26 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry 10 To specify the Coefficients File click the Browse button and select definition1_times coe located in the project directory 11 Check that only the following pins are used used pins are highlighted on the symbol on the left side of the customization GUI a 5 0 spo 19 0 12 Click Generate Distributed Memory Generator View Documents IP Symbol ax Distributed Memory Generator xilinx cam ip dist mem gen 7 1 logi PE Load COE File If desired the initial memory content can be set by using a COE file This will be passed to the core as a Memory Initialisation File MIF Coefficients File hdefinition1 times coe Browse Show COE Options Default Data 0 Radix 16 v
58. Edit gt Preferences In the left pane of the Preferences dialog box expand ISE General and click Integrated Tools In the right pane under Model Tech Simulator browse to the location of modelsim exe file For example c modeltech_xe win32xoem modelsim exe In the Process Properties dialog box ensure that the Property display level is set to Advanced This global setting enables you to see all available properties Select the Simulation Model Properties category These properties set the options that NetGen uses when generating the simulation netlist For a description of each property click the Help button www xilinx com 119 Chapter 7 Timing Simulation XILINX The properties should appear as shown in the following figure For this tutorial the default Simulation Model Properties are used Process Properties Simulation Model Properties Category Switch Name Property Name Simulation Properties Simulation Model Target Display Properties f Simulation Model Properties XPower Analyzer Properties s Device Speed Grade Select ABS Minimum mhf Generate Multiple Hierarchical Netlist Files OOk o 5 fn Retain Hierarchy tp Bring Out Global Tristate Net as a Port Global Tristate Port Name gp Bring Out Global Set Reset Net as a Port Global Set Reset Port Name GSR_PORT TS PORT a tb Generate Testbench File 0 Rename Design Instance in Tes
59. HDL Package VHDL Package VHDL Package VHDL Package VHDL Package VHDL Package std_logic_textio VHDL Package std_logic_unsi components VHDL Package VHDL Package Figure 5 13 Instances and Processes Memory E Source Files Simulation Objects For a uu Object Name lb cdkin in W rst in cif out clin ibufg out ig ck out locked out li clkFb_in Ub cfx buf lig clin ibufg n clkO_buF Ue gnd_bit 5552 lt AE Default wcfg aj Adding Signals to the Simulation Waveform Notice that the waveforms have not been drawn for the newly added signals This is because ISim did not record the data for these signals By default ISim records data only for the signals that are added to the waveform window while the simulation is running Therefore when new signals are added to the waveform window you must rerun the simulation for the desired amount of time Rerunning Simulation To rerun the simulation in ISim do the following 1 Click the Restart Simulation icon Figure 5 14 Sim Restart Simulation Icon 2 At the ISim command prompt in the Console enter run 2000 ns and press Enter The simulation runs for 2000 ns The waveforms for the DCM are now visible in the Waveform window Analyzing the Signals Now the DCM signals can be analyzed to verify that they work as expected The CLKO_OUT must be 50 MHz and the CLKFX OUT should be approximately 26 MHz The DCM outputs are valid only after the LOC
60. ILINX Checking the Schematic The time_cnt schematic is now complete Verify that the schematic does not contain logical errors by running a design rule check DRC To do this select Tools gt Check Schematic The Console should report that no errors or warnings are detected If an error or warning is displayed fix the reported problem before proceeding Saving the Schematic Save the schematic as follows 1 Select File gt Save or click the Save toolbar button El Figure 4 14 Save Toolbar Button 2 Closethe time cnt schematic Creating and Placing the time cnt Symbol The next step is to create a symbol that represents the time cnt macro The symbol is an instantiation of the macro After you create a symbol for time cnt you will add the symbol to a top level schematic of the stopwatch design In the top level schematic the symbol of the time cnt macro will be connected to other components in a later section in this chapter Creating the time cnt Symbol You can create a symbol using either a Project Navigator process or a Tools menu command To create a symbol that represents the time cnt schematic using a Project Navigator process do the following 1 Inthe Hierarchy pane of the Design panel select time cnt sch 2 Inthe Processes pane expand Design Utilities and double click Create Schematic Symbol To create a symbol that represents the time cnt schematic using a Tools menu command do the following
61. ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX amp XILINX Notice of Disclaimer The information disclosed to you hereunder the Materials is provided solely for the selection and use of Xilinx products To the maximum extent permitted by applicable law 1 Materials are made available AS IS and with all faults Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS EXPRESS IMPLIED OR STATUTORY INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY NON INFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE and 2 Xilinx shall not be liable whether in contract or tort including negligence or under any other theory of liability for any loss or damage of any kind or nature related to arising under or in connection with the Materials including your use of the Materials including for any direct indirect special incidental or consequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a result of any action brought by a third party even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications You may not reproduce modify distribute or publicly display the Materials without prior written consent Certain products are subject to the terms and conditions
62. K 3 Repeat steps 1 and 2 to change the following symbol instance names e Name the statmach instance timer state e Name the top debounce instance lap load debounce e Name the middle debounce instance mode debounce e Name the bottom debounce instance strtstop debounce e Name the timer preset instance t preset e Name the time cnt instance timer cnt Using Hierarchy Push Pop First perform a hierarchy push down which enables you to focus in on a lower level of the schematic hierarchy to view the underlying file Push down into the time cnt macro which is a schematic based macro created earlier in this tutorial and examine its components To push down into time cnt from the top level stopwatch schematic do the following 1 Click the time cnt symbol in the schematic and select the Hierarchy Push toolbar button You can also right click the macro and select Symbol Push into Symbol LA Figure 4 27 Hierarchy Push Toolbar Button In the time cnt schematic you see five counter blocks Push into any of the counter blocks by selecting the block and clicking on the Hierarchy Push toolbar button This process may be repeated until the schematic page contains only Xilinx primitive components If you push into a symbol that has an underlying HDL or IP core file the appropriate text editor or customization GUI opens which enables you to edit the file 2 After examining the macro return to the top level schematic by sel
63. KED OUT signal is high therefore the DCM signals are analyzed only after the LOCKED OUT signal has gone high 88 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Behavioral Simulation Using ISim ISim can add markers to measure the distance between signals To measure the CLKO OUT do the following 1 If necessary zoom in on the waveform using the local Zoom toolbar buttons 2 Inthelocal waveform viewer toolbar click the Snap to Transition toolbar button Hl Figure 5 15 Snap to Transition Toolbar Button 3 Click on the first rising edge transition on the CLKO_OUT signal after the LOCKED_OUT signal has gone high then drag the cursor to the right to the next rising edge transition of the CLKO_OUT signal 4 At the bottom of the waveform window the start point time end point time and delta times are shown The delta should read 20 0 ns This converts to 50 MHz which is the input frequency from the test bench which in turn is the DCM CLKO output X1 390 000 ps x2 370 000 ps AX 20 000 ps i3 a Default wcfg mE kO wxtt Figure 5 16 Waveform Viewer Displaying Time Between Transitions 5 Measure CLKFX OUT using the same steps as above The measurement should read 38 5 ns This equals approximately 26 MHz Your behavioral simulation is complete To implement the design follow the steps in Chapter 6 Design Implementation ISE In Depth Tutorial www xilinx
64. L Test Bench in Chapter 5 if you do not already have a test bench in your project e Xilinx simulation libraries For timing simulation the SIMPRIM library is needed to simulate the design To perform timing simulation of Xilinx designs in any HDL simulator the SIMPRIM library must be set up correctly The timing simulation netlist created by Xilinx is composed entirely of instantiated primitives which are modeled in the SIMPRIM library If you completed Chapter 5 Behavioral Simulation the SIMPRIM library should already be compiled For more information on compiling and setting up Xilinx simulation libraries see Xilinx Simulation Libraries in Chapter 5 Specifying a Simulator To specify the simulator to simulate the stopwatch design do the following 1 Inthe Hierarchy pane of the Project Navigator Design panel right click the device line xc3s700A 4f 484 and select Design Properties 2 Inthe Design Properties dialog box set the Simulator field to ISim VHDL Verilog or ModelSim with the appropriate type and language Note ModelSim and Xilinx ISim are the only simulators that are integrated with Project Navigator Selecting a different simulator for example NC Sim or VCS will set the correct options for NetGen to create a simulation netlist for that simulator but Project Navigator will not directly open the simulator For additional information about simulation and for a list of other supported simulators see the Synt
65. TDO Available Operations are Program mb Get Device ID Get Device Signature Usercode mb Read Device Status mb One Step SVF One Step XSVF IE Boundary Scan Console BATCH CMD setMode bs Selected part xcf 04s BATCH CMD assignFile p 2 file C xilinx tutorial wtut sc stopwatch2 mcs 2 Loading file C xilinx tutorial wtut sc stopwatch2 mcs done BATCH CMD set ttribute position 2 attr packageName value Console o Errors A Warnings No Cable Connection NoFileOpen Figure 8 5 Available Boundary Scan Operations for XC3S700A Device The software accesses the IDCODE for this Spartan 3A device The result is displayed in the log window as shown in the following figure BATCH CMD ReadIdcode p 1 Maximum TCK operating frequency for this device chain 0 Validating chain Boundary scan chain validated successfully 1 IDCODE is 00000010011000101000000010010011 1 IDCODE is 02628093 in hex 1 Manufacturer s ID Xilinx xc3s700a Version 0 Figure 8 6 Log Window Showing Result of Get Device ID ISE In Depth Tutorial www xilinx com 139 UG695 v14 1 April 24 2012 Chapter 8 Configuration Using iMPACT XILINX 2 Right click on the XCF04S device and select Set Programming Properties The Device Programming Properties dialog box opens 3 Select the Verify option The Verify option enables the device to be read back and
66. Table 6 1 Required Tutorial Files File Name Description stopwatch edn stopwatch edf or Input netlist file EDIF stopwatch ngc timer preset ngc Timer netlist file NGC stopwatch ucf User Constraints File Note The completed directories contain the finished source files Do not overwrite any files in the completed directories This tutorial assumes that the files are unzipped under c xilinx_tutorial but you can unzip the source files into any directory with read write permissions If you unzip the files into a different location substitute your project path in the procedures that follow 1 Open the ISE Design Suite using one of the following methods e Ona workstation enter ise Ona PC select Start gt Programs gt Xilinx ISE Design Suite gt ISE Design Tools gt Project Navigator 2 Create a new project and add the EDIF netlist as follows a Select File gt New Project b Inthe Name field enter wtut_edif c Select EDIF for the Top Level Source Type and click Next d Select stopwatch edf or stopwatch edn for the Input Design file e Select stopwatch ucf for the Constraints file and click Next f Select the following values Family Spartan3A and Spartan3AN Device XC3S700A Package FG484 Speed 4 g Click Next then Finish to complete the project creation Note If the timer_preset ngc file is not in the project directory copy it from the extracted ZIP file www xili
67. The CORE Generator tool is a graphical interactive design tool that enables you to create high level modules such as memory elements math functions and communications and I O interface cores You can customize and pre optimize the modules to take advantage of the inherent architectural features of the Xilinx FPGA architectures such as Fast Carry Logic SRL16s and distributed and block RAM In this section you will create a CORE Generator tool module called timer_preset The module will be used to store a set of 64 values to load into the timer Creating the timer_preset CORE Generator Tool Module To create a CORE Generator tool module do the following 1 SIE SES OUS 2 24 In Project Navigator select Project New Source Select IP CORE Generator amp Architecture Wizard In the File Name field enter timer preset Click Next Expand the IP tree selector to locate Memories amp Storage Elements RAMs amp ROMs www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry 6 Select Distributed Memory Generator click Next and click Finish to open the Distributed Memory Generator customization GUI This customization GUI enables you to customize the memory to the design specifications New Source Wizard Select IP Create Coregen or Architecture Wizard IP Core view by Function View by Name Name Version AXI4 Ax14 Stream AXI4 Lite Status License Vendor Libra
68. a To review the Programming File Generation Report open the Bitgen Report in the Design Summary Report Viewer Verify that the specified options were used when creating the configuration data Creating a PROM File with iMPACT To program a single device using iMPACT all you need is a bitstream file To program several devices in a daisy chain configuration or to program your devices using a PROM you must use iMPACT to create a PROM file iMPACT accepts any number of bitstreams and creates one or more PROM files containing one or more daisy chain configurations In iMPACT a wizard enables you to do the following ISE In Depth Tutorial UG695 v14 1 April 24 2012 Create a PROM file Add additional bitstreams to the daisy chain Create additional daisy chains Remove the current bitstream and start over or immediately save the current PROM file configuration www xilinx com 113 Chapter 6 Design Implementation XILINX For this tutorial create a PROM file in iMPACT as follows 1 Inthe Processes pane expand Configure Target Device and double click Generate Target PROM ACE File 2 IniMPACT double click on Create PROM File PROM File Formatter in the iMPACT Flows window iMPACT Flows ensx Boundary Scan SystemACE Bf Create PROM File PROM File Formatter Figure 6 26 Create PROM File 3 Inthe PROM File Formatter window select Xilinx Flash PROM in the Select Storage Target section Click the
69. at are necessary to perform a Get Device ID operation are then written to the file ISE In Depth Tutorial www xilinx com 145 UG695 v14 1 April 24 2012 Chapter 8 Configuration Using iMPACT g XILINX 2 Tosee the results select View gt View SVF STAPL File The following figure shows the SVF file after the Get Device ID operation is performed Created using Xilinx iMPACT Software ISE 10 1 Date Mon May 19 21 44 00 2008 TRST OFF ENDIR IDLE ENDDR IDLE STATE RESET STATE IDLE FREQUENCY 1E6 HZ HIR TDR HDR TIR HIR 14 TDI 3fff SMASK 3fff HDR 2 TDI 00 SMASK 03 TDR O Loading device with idcode instruction SIR 6 TDI 09 SMASK 3f SDR 32 TDI 00000000 SMASK ffffffff TDO f2628093 MASK Ofbfffff TIR O HIR O TDR O HDR O TIR O HIR O TDR O HDR O TIR O Oo Oo Oo Oo TIR O HIR O TDR O HDR O TIR O HIR O TDR O HDR O TIR O HIR 14 TDI 3fff SMASK 3fff HDR 2 TDI 00 SMASK 03 TDR O Loading device with idcode instruction SIR 6 TDI 09 SDR 32 TDI 00000000 TDO f2628093 Loading device with idcode instruction SIR 6 TDI 09 SDR 32 TDI 00000000 TDO f2628093 TIR O HIR 14 TDI S3fff HDR 2 TDI 00 TDR O TIR O HIR O TDR O HDR O SIR 20 TDI Offfff SMASK Offfff SDR 3 TDI 00 SMASK 07 Figure 8 13 SVF File That Gets a Device ID from the First Devi
70. atic window can be undocked from the Project Navigator framework by selecting Window gt Float while the schematic is selected in the Workspace After being undocked the schematic window can be redocked by selecting Window gt Dock Creating a Schematic Based Macro A schematic based macro consists of a symbol and an underlying schematic You can create either the underlying schematic or the symbol first The corresponding symbol or schematic file can then be generated automatically In the following steps you will create a schematic based macro by using the New Source Wizard in Project Navigator An empty schematic file is then created and you can define the appropriate logic The created macro is then automatically added to the project library The macro you will create is called time_cnt This macro is a binary counter with five 4 bit outputs representing the digits of the stopwatch ISE In Depth Tutorial www xilinx com 47 UG695 v14 1 April 24 2012 Chapter 4 Schematic Based Design XILINX To create a schematic based macro do the following 1 In Project Navigator select Project gt New Source The New Source Wizard opens which displays a list of all of the available source types New Source Wizard Select Source Type Select source type file name and its location Pn BMM File ChipScope Definition and Connection File t Implementation Constraints File IP CORE Generator amp Architecture Wiza
71. ations are currently disabled Pause DR PauseR TDO and will be available when you exit the debug session o 1 0 1 To exit the debug session select Debug gt Enable Disable Chain LOY 60208 Exit24R 1 1 TOI 10 from the main menu Update DR Update IR sb v Ses ND Pulse TCK Test Logic Reset lt d EZ Boundary Scan E Console enex PLD file version 0012h PLD version 0012h PROGRESS END End Operation Elapsed time 1 sec Type 0x0004 ESN device is not available for this cable gt El Console 6 Errors d Warnings Configuration Platform Cable USB 6 MHz usb hs Figure 8 11 Debug Chain For help using iMPACT Boundary Scan Debug use the iMPACT Help accessible from Help gt Help Topics For help with troubleshooting file a WebCase on the Xilinx website Creating an SVF File This section is optional and assumes that you have followed the Using Boundary Scan Configuration Mode section and have successfully programmed to a board In this section all of the configuration information is written to the SVF file iMPACT supports the creation of device programming files in three formats SVF XSVF and STAPL If you are using third party programming solutions you may need to set up your Boundary Scan chain manually and then create a device programming file These programming files contain both programming instructions and configuration data an
72. ator tool is a graphical interactive design tool that enables you to create high level modules such as memory elements math functions communications and I O interface cores You can customize and pre optimize the modules to take advantage of the inherent architectural features of the Xilinx FPGA architectures such as Fast Carry Logic SRL 16s and distributed and block RAM In this section you will create a CORE Generator tool module called timer preset The module is used to store a set of 64 values to load into the timer Creating the timer preset CORE Generator Tool Module To create a CORE Generator tool module do the following 1 S aere R ISE In Depth Tutorial UG695 v14 1 April 24 2012 In Project Navigator select Project New Source Select IP Coregen amp Architecture Wizard In the File name field enter timer preset Click Next Double click Memories amp Storage Elements gt RAMs amp ROMs www xilinx com 57 Chapter 4 Schematic Based Design XILINX 6 Select Distributed Memory Generator then click Next and click Finish to open the Distributed Memory Generator customization GUI This customization GUI enables you to customize the memory to the design specifications New Source Wizard Select IP Create Coregen or Architecture Wizard IP Core View by Function View by Name Name Version AXI4 AxXI4 Stream AxI4 Lite Status License Vendor Library tH FIFOs t Bp Memory Interfac
73. ause the design then contains information needed for I O and clock related design rule checks performed by the PlanAhead tool Processes stopwatch stopwatch_arch E Design Summary Reports ic Design Utilities a User Constraints Create Timing Constraints T O Pin Planning Plan head Pre Synthesis T O Pin Planning Plandhead Post Synthesis Floorplan Area IO Logic PlanAhead CAA Synthesize XST w Q Implement Design T Generate Programming File e g Configure Target Device a Update Bitstream with Processor Data Analyze Design Using Chipscope Figure 6 11 VO Pin Planning Post Synthesis This process launches the PlanAhead tool If the design has not yet completed synthesis Project Navigator will first automatically run synthesis before launching the PlanAhead tool for I O pin planning The Welcome to PlanAhead tool screen provides links to detailed documentation tutorials and other training material to help you learn more about the PlanAhead tool The tutorials provide an overview of the use and capabilities of the PlanAhead tool www xilinx com 101 Chapter 6 Design Implementation XILINX 3 Click Close on the Welcome dialog to proceed in the PlanAhead tool G wtut _vhd C xilinx_tutorial wtut_vhd planAhead_run_1 wtut_vhd ppr PlanAhead 14 1 File Edit Tools Window Layout View Help Boo x diu Q KX 210 Planning X x 9 Synthesized Design 4 Netlist Pa Device
74. but that has mask data in place of configuration data This data is not used to configure the device but is used for verification If a mask bit is 0 the bit should be verified against the bit stream data If a mask bit is 1 the bit should not be verified This file is generated along with the BIT file These files are generated in Chapter 6 Design Implementation The tutorial project files are provided with the ISE Design Suite Tutorials available from the Xilinx website Download the project files for the VHDL Verilog or schematic design flow Connecting the Cable Prior to launching iMPACT connect the USB cable to one of your computer s USB ports and connect the other end to the USB port of the Spartan 3A Starter Kit demo board Be sure that the board is powered Starting the Software This section describes how to start the iMPACT software from the ISE Design Suite and how to run the iMPACT software standalone www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Using Boundary Scan Configuration Mode Opening iMPACT from Project Navigator To start iMPACT from Project Navigator double click Manage Configuration Project iMPACT in the Processes pane in the Design panel as shown in the following figure x Processes for stopwatch stopwatch_arch o Add Existing Source Create New Source View Design Summary eu tz Design Utilities User Constraints H CIA Synthesize
75. c and view the various design elements and connectivity Right click the schematic to view the various operations that can be performed in the schematic viewer X x E Figure 3 26 RTL Schematic You have completed XST synthesis An NGC file now exists for the stopwatch design To continue with the HDL flow do either of the following e Go to Chapter 5 Behavioral Simulation to perform a pre synthesis simulation of this design e Proceed to Chapter 6 Design Implementation to place and route the design Note For more information about XST constraints options reports or running XST from the command line see the XST User Guides Synthesizing the Design Using Synplify Synplify Pro Software Now that you have entered and analyzed the design the next step is to synthesize the design In this step the HDL files are translated into gates and optimized to the target architecture To access the Synplify software RTL viewer and constraints editor you must run the Synplify software outside of the ISE Design Suite Processes available for synthesis using the Synplify and Synplify Pro software are as follows e View Synthesis Report Lists the synthesis optimizations that were performed on the design and gives a brief timing and mapping report e View RTL Schematic Accessible from the Launch Tools hierarchy this process displays the Synplify or Synplify Pro software with a schematic view of your HDL code e View Technology Schemat
76. ce components and the lap load mode in and strtstop pin of the statmach macro Label the nets 11 debounced mode debounced and strtstop debounced See Drawing Wires and Adding Net Names 7 Addhanging wires to the dcm lock pin and the reset pin of the statmach macro Name them locked and reset respectively 72 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX 10 11 12 13 14 15 16 Design Entry Draw a hanging wire to the clken output of the statmach component and another hanging wire to the ce pin of the time cnt component Name both wires 1k_en_int Draw hanging wires from the rst output pin of the statmach macro and the clr pin of the time_cnt macro See Drawing Wires Label both wires rst_int Draw a wire from the bus output of the timer_preset to the q 19 0 input of the time_cnt macro See Drawing Wires Notice how the wire is automatically converted to a bus Draw a hanging bus on the input of the timer_preset macro and name the bus address 5 0 Draw wires from the lap_trigger and mode outputs of the statmach macro to the lap and mode inputs of the lcd control macro See Drawing Wires Name the nets lap and mode control respectively Draw hanging wires from the load output of the statmach macro and the load input of the time cnt macro See Drawing Wires Name both wires 1oad Draw a hanging wire to the up input time cnt macro See Drawing Wires Name the wire
77. ce in the Chain 146 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 g XILINX Creating an SVF File To write further instructions to the SVF for the second device do the following 1 Right click the second device XCF025 and select Program c TDI Eune Verify xc3s700a xcf04s stopwatch bit stopwatch2 mc Erase Blank Check Get Device ID Get Device Signature Usercode Assign New Configuration File Set Programming Properties Set Erase Properties Set Target Device TDO Figure 8 14 Available Boundary Scan Operations for XCF02S Device 2 Click OK in the Programming Properties window The instructions and configuration data needed to program the second device are added to the SVF file Stopping Writing to the SVF File After all the desired operations have been performed you must add an instruction to close the file from further instructions To stop writing to the programming file select Output gt SVF File gt Stop Writing to SVF File To add other operations in the future you can select Output gt SVF File gt Append to SVF File select the SVF file and click Save Playing Back the SVF or XSVF File To play back the SVF file that you created to verify the instructions do the following 1 Manually create a new chain 2 Assign the SVF file to the chain by right clicking and selecting Add Xilinx Device and selecting the SVF file in the search window 3 Right click
78. changes and do not result in an update to the project file Making a Copy of a Project ISE In Depth Tutorial You can create a copy of a project using File Copy Project to experiment with different source options and implementations Depending on your needs the design source files for the copied project and their location can vary as follows Design source files can be left in their existing location and the copied project points to these files e Design source files including generated files can be copied and placed in a specified directory e Design source files excluding generated files can be copied and placed in a specified directory www xilinx com 11 UG695 v14 1 April 24 2012 Chapter 2 Overview of the ISE Design Suite XILINX 12 Using the Project Browser The Project Browser accessible by selecting File gt Project Browser provides a convenient way to compare view and open projects as follows e Compare key characteristics between multiple projects e View Design Summary and Reports for a selected project before opening the full project e Compare detailed information for two selected projects e Open a selected project in the current Project Navigator session e Open a selected project in a new Project Navigator session Using Project Archives You can also archive the entire project into a single compressed file This allows for easier transfer over email and storage of numerous proj
79. ck the Browse button to browse to the project directory and select definitionl_times coe Check that only the following pins are used used pins are highlighted on the symbol on the left side of the customization GUI e a 5 0 e spo 19 0 Click Generate The module is created and automatically added to the project library A number of files are added to the ipcore dir sub directory of the project directory Following is a list of some of these files ISE In Depth Tutorial UG695 v14 1 April 24 2012 timer preset sym This file is a schematic symbol file timer preset vhd or timer preset v These are HDL wrapper files for the core and are used only for simulation timer preset ngc This file is the netlist that is used during the Translate phase of implementation www xilinx com 59 Chapter 4 Schematic Based Design XILINX e timer_preset xco This file stores the configuration information for the timer_preset module and is used as a project source e timer_preset mif This file provides the initialization values of the ROM for simulation Creating a DCM Module The Clocking Wizard a Xilinx Architecture Wizard enables you to graphically select Digital Clock Manager DCM features that you want to use In this section you will create a basic DCM module with CLKO feedback and duty cycle correction Using the Clocking Wizard Create the dcm1 module as follows 1 In Project Navigator select Proj
80. clkoa zT Uu lcd rw OBUF x obuf x obu VHDL Entity clkdv o 4 ij mode IBUF x buf x buf v VHDL Entity dx 1 2 i Inst dcmi CLKIM IBUFG INST x buf x buf v VHDL Entity clkfx180 0 L i Inst dcmi CLKO BUFG INST x bufgmux x VHDL Entity i Inst dcmi CLKO BUFG INST SINV x inv x inv v VHDL Entity iy Inst dcmi CLKO BUFG INST IO USED x buf x buf v VHDL Entity psdone status 7 0 10100 ig Inst dcmi CLKFX BUFG INST x bufgmux x VHDL Entity ckfb 1 Hn EF Inst dcmi CLKFX BUFG INST SINV x inv x inv v HDL Entity clkin 1 i Inst dcmi CLKFX BUFG INST IO U x buf x buf v VHDL Entity dssen Uu 1j dk divider div 262144 BUFG x bufgmux x VHDL Entity psclk iy clk divider div 262144 BUFG SINV x inv x inv v VHDL Entity psen o 4 dk divider div 262144 BUFG 10 US x buf x buf v VHDL Entity psincdec ij Inst dcmi DCM SP INST PSCLKINV x buf x buf v VHDL Entity rst o Inst dcmi DCM SP INST x dcm sp x VHDL Entity lo clkFb_ipd 1 iJ Inst demi DCM SP INST CLKFB BUF x buf x buf v VHDL Entity U clkin ipd 1 lt gt Up dssen_ipd U v E Instances and Processes Memory B Source Files lt i gt E Default wcfg amp Figure 7 12 Simulation Instances and Simulation Objects Windows VHDL Flow 128 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Timing Simulation Using Xilinx ISim 5 Click and drag the following Inst dcm1 DCM SP INST signals from the simulation hierarchy to the wavefo
81. clock pad net s f Okin ck L OFFSET OUT AFTER 9 Output clock period inFormation Clock Name clk Create Edit f REFERENCE PN Y p Skew gt Period 7 ns mis Duty Cycle 50 Output pad timegroup net Output pad timegroup v v External clock to pad offset oi Units 38 vl ns a Rising edge constraints Output skew reference pin Default v x Se Output Interface Detail The Single Data Rate and Dual Data Rate determine the output interface Output register timegroup type The Output clock Pad Net is the clock net used to trigger the outgoing data Rising edge comment The optional Output pad timegroup limits the scope of the OFFSET OUT constraint to only those data pins defined in the PAD timegroup Falling edge constraints External clock to pad offset oi Units 7 ns Rising Constraint Parameters 4 new Pad Group may be defined by selecting the Create New Pad Group button Output skew reference pin The optional Rising Clock to Output OFFSET OUT is the time from the rising clock Default edge at the input pin of the FPGA until data becomes valid at the output pin of the FPGA For source synchronous designs select lt Analyze Only from the pull down list For the OFFSET OUT value and only a skew report will be generated Output register timegroup a The Output Skew Reference Pin is the reference signal in which t
82. com 89 UG695 v14 1 April 24 2012 Chapter 5 Behavioral Simulation 90 www xilinx com XILINX ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Chapter 6 Design Implementation Overview of Design Implementation Design implementation is the process of translating mapping placing routing and generating a bitstream file for your design The design implementation tools are embedded in the Xilinx ISE Design Suite for easy access and project management This chapter is the first in the Implementation Only Flow and is a subsequent chapter for the HDL Design Flow and the Schematic Design Flow This chapter demonstrates the ISE Design Suite implementation flow The front end design has already been compiled in an EDA interface tool For details about compiling the design see Chapter 3 HDL Based Design or Chapter 4 Schematic Based Design In this chapter you will be passing a synthesized netlist EDN NGC from the front end tool to the back end design implementation tools and you will be incorporating placement constraints through a User Constraints File UCF You will also add timing constraints as well as additional placement constraints Getting Started The tutorial design emulates a runner s stopwatch with actual and lap times There are five inputs to the system CLK RESET LAP_LOAD MODE and SRTSTP This system generates a traditional stopwatch with lap times and a traditional timer on a
83. component and select Delete Drawing Wires You can draw wires also called nets to connect the components placed in the schematic Perform the following steps to draw a net between the AND2b1 and top cd4rled components on the time_cnt schematic 1 Select Add gt Wire or click the Add Wire toolbar button gt Figure 4 9 Add Wire Toolbar Button 2 Click the output pin of the AND2b1 and then click the destination pin CE on the cd4rled component The Schematic Editor draws a net between the two pins 3 Drawanetto connect the output of the AND5 component to the inverted input of the AND2b1 component Connect the other input of the AND2b1 to the ce input I O marker 4 Connectthe load up clk and clr input I O markers respectively to the L UP C and R pins of each of the five counter blocks and connect the CEO pin of the first four counters to the CE pin of the next counter as shown in Figure 4 8 To specify the shape of the net do the following 1 Move the mouse in the direction you want to draw the net 2 Click the mouse to create a 90 degree bend in the wire Note To draw a net between an already existing net and a pin click once on the component pin and once on the existing net A junction point is drawn on the existing net Adding Buses In the Schematic Editor a bus is simply a wire that has been given a multi bit name To add a bus use the methodology for adding wires and then add a multi bit name After a bus
84. d B debounce vhd Language Templates Figure 4 23 Language Templates 64 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry Adding a Language Template to a File You will now use Use in File method for adding templates to your HDL file Refer to Working with Language Templates in the ISE Help for additional usability options including drag and drop options To add the template to your HDL file do the following 1 10 ISE In Depth Tutorial UG695 v14 1 April 24 2012 With the debounce v or debounce vhd source file active position the cursor under the architecture begin statement in the VHDL file or under the module and pin declarations in the Verilog file Return to the Language Templates window right click on the Debounce Circuit template in the template index and select Use In File 73 Flip Flops else amp 9 Logical Shifters Ql lt GY Misc Q2 lt E 7 Segment Display Hex Conversior Q3 lt E Asynchronous Input Synchronizati end if T Barrel Shifter end if 7 Debounce circuit nd process IT Open Drain Output Open Drain Output amp E Output Clock Forw amp E Multiplexers a E RAM a E ROM amp E Shift Registers m 74 State Marhines OUT lt Q1 and if Use in File Figure 4 24 Selecting Language Template to Use in File Close the Language Templates window Open the debounce
85. d they are used by Automatic Test Equipment ATE machines and embedded controllers to perform Boundary Scan operations A cable normally does not need to be connected because no operations are being performed on devices ISE In Depth Tutorial www xilinx com 143 UG695 v14 1 April 24 2012 Chapter 8 Configuration Using iMPACT XILINX Setting Up the Boundary Scan Chain This section assumes that you are continuing from the previous sections of this chapter and already have the chain detected If not skip to Manually Setting Up the JTAG Chain for SVF Generation to define the chain manually Setting Up the JTAG Chain for SVF Generation To set up the JTAG chain do the following 1 Select Output gt SVF File gt Create SVF File to indicate that you are creating a programming file 2 Inthe Create New SVF File dialog box enter getid in the File Name field and click Save 3 Aninformational message appears stating that all device operations will be directed to the svf file Click OK Manually Setting Up the JTAG Chain for SVF Generation For this tutorial you may skip this section if you completed the Using Boundary Scan Configuration Mode section The Boundary Scan chain can be manually created or modified as well To do this do the following 1 Ensure that you are in Boundary Scan Mode by clicking the Boundary Scan tab You can now add one device at a time 2 Right click on an empty space in theiMPACT Boundary
86. d ISE General and click Integrated Tools Changing the design flow results in the deletion of implementation data You have not yet created any implementation data in this tutorial For projects that contain implementation ISE In Depth Tutorial www xilinx com 33 UG695 v14 1 April 24 2012 Chapter 3 HDL Based Design XILINX 34 data Xilinx recommends that you make a copy of the project using File gt Copy Project if you would like to make a backup of the project before continuing Synthesizing the Design Using XST Now that you have created and analyzed the design the next step is to synthesize the design During synthesis the HDL files are translated into gates and optimized for the target architecture Processes available for synthesis using XST are as follows e View RTL Schematic Generates a schematic view of your RTL netlist e View Technology Schematic Generates a schematic view of your technology netlist e Check Syntax Verifies that the HDL code is entered properly e Generate Post Synthesis Simulation Model Creates HDL simulation models based on the synthesis netlist Entering Synthesis Options Synthesis options enable you to modify the behavior of the synthesis tool to make optimizations according to the needs of the design One commonly used option is to control synthesis to make optimizations based on area or speed Other options include controlling the maximum fanout of a flip flop output or setting the
87. dication of how realistic your timing goals are evaluate the design after the map stage A rough guideline known as the 50 50 rule specifies that the block delays in any single path make up approximately 50 of the total path delay after the design is routed For example a path with 10 ns of block delay should meet a 20 ns timing constraint after it is placed and routed ISE In Depth Tutorial www xilinx com 105 UG695 v14 1 April 24 2012 Chapter 6 Design Implementation XILINX If your design is extremely dense the Post Map Static Timing Report provides a summary analysis of your timing constraints based on block delays and estimates of route delays This analysis can help to determine if your timing constraints are going to be met This report is produced after Map and prior to Place and Route PAR Reviewing the Post Map Static Timing Report Use the Post Map Static Timing Report to determine timing violations that may occur prior to running PAR Because you defined timing constraints for the stopwatch design the timing report will display the path for each of the timing constraints To view the Post Map Static Timing Report and review the PERIOD Constraints that were entered earlier do the following 1 Inthe Processes pane expand Map and double click Generate Post Map Static Timing 2 To open the Post Map Static Timing Report double click Analyze Post Map Static Timing Processes stopwatch stopwatch_arch
88. e Xilinx website To navigate to the Answer Record select the error or warning message right click the mouse and select Search for Answer Record from the right click menu The default Web browser opens and displays all Answer Records applicable to this message Workspace The Workspace is where design editors viewers and analysis tools open These include ISE Text Editor Schematic Editor Constraint Editor Design Summary Report Viewer RTL and Technology Viewers and Timing Analyzer Other tools such as the PlanAhead tool for I O planning and floorplanning ISim third party text editors XPower Analyzer and iMPACT open in separate windows outside the main Project Navigator environment when invoked Design Summary Report Viewer The Design Summary provides a summary of key design data as well as access to all of the messages and detailed reports from the synthesis and implementation tools The summary lists high level information about your project including overview information a device utilization summary performance data gathered from the Place and Route PAR report constraints information and summary information from all reports with links to the individual reports A link to the System Settings report provides information on www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Using Project Revision Management Features environment variables and tool settings used during the design imp
89. e Generators RAMs amp ROMs 4 Block Memory Generator 7 1 AXI4 Lite Production X Distributed Memory Generator 6 4 Production Distributed Memory Generator 7 tH 7 Standard Bus Interfaces lt xilinx com xilinx com i Production xilinx com v is Search IP Catalog Clear All IP versions C only IP compatible with chosen part Figure 4 16 New Source Wizard Select IP Page 7 Fillin the Distributed Memory Generator customization GUI with the following settings e Component Name timer preset defines the name of the module e Depth 64 defines the number of values to be stored e Data Width 20 defines the width of the output bus Memory Type ROM 8 Click Next 58 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry 9 Leave Input and Output options as Non Registered and click Next Distributed Memory Generator View Documents IP Symbol Bx Distributed Memory Gen e rato r xilinx com ip dist mem gen 7 1 lagi RE Options Depth 64 Range 16 65536 Data Width 20 Range 1 1024 Memory Type ROM Single Port RAM Q Dual Port RAM SRL16 based Memory Simple Dual Port RAM Datasheet lt Back Page 1of3 Next gt Generate Cancel Help Figure 4 17 CORE Generator Tool Distributed Memory Generator Customization 10 11 12 GUI To specify the Coefficients File cli
90. e Shift NONE e CLKIN Source External Single e Feedback Source Internal e Feedback Value 1X e Use Duty Cycle Correction Selected E Xilinx Clocking Wizard General Setup Input Clock Frequency 9 MHz ns CLKIN Source Extemal Internal Internal None Single Differential Feedback Value oo Figure 4 19 Xilinx Clocking Wizard General Setup 11 Click the Advanced button 12 Select the Wait for DCM Lock before DONE Signal goes high option 13 Click OK 14 Click Next and then Next again 15 Select Use output frequency and enter 26 2144 in the box and select MHz 26 2144Mhz 2 100Hz 16 Click Next and then click Finish The dcm1 xaw file is created and added to the list of project source files in the Hierarchy pane of the Design panel ISE In Depth Tutorial www xilinx com 61 UG695 v14 1 April 24 2012 Chapter 4 Schematic Based Design 62 Creating the dcm1 Symbol XILINX Next create a symbol representing the dcm1 macro This symbol will be added to the top level schematic stopwatch sch later in the tutorial 1 2 In Hierarchy pane of the Project Navigator Design panel select dcm1 xaw In the Processes pane double click Create Schematic Symbol Creating an HDL Based Module With the ISE Design Suite you can easily create modules from HDL code The HDL code is connected to your top level schemat
91. e called Debounce Circuit or One Shot Debounce Circuit Use the appropriate template for the language you are using 22 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry Upon selection the HDL code for a debounce circuit is displayed in the right pane amp Td w E ucF E Provides a one shot pulse from a non clock input wit 3 VHDL Insert the following between the architecture and X amp amp E Common Constructs begin keywords 1 amp 7 Device Macro Instantiation signal Q1 Q2 Q3 std logic w E Device Primitive Instantiation kd w 73 Simulation Constructs Insert the following after the begin keyword S Synthesis Constructs process lt clock gt w 7 Assertions amp Functions begin H E Attributes if lt clock gt event and lt clock gt 1 then amp 3 Coding Examples if lt reset gt 1 then w 7 Accumulators Qi ngis w E Arithmetic Q2 lt 0 w 7 Basic Gates Q3 lt rgis amp 9 Bi directional 1 0 else amp 7 Comparators Q1 lt D IN w E Counters Q2 lt Q1 a Decoders Q3 lt Q2 73 Encoders end if amp 7 Flip Flops end if w 73 Logical Shifters end process amp 3 Misc 7 Segment Display Hex Conversior Q OUT Q1 and Q2 and not Q3 Asynchronous Input Synchronizatii Barrel Shifter fa Debounce circuit T Open Drain Output bused reg Open Drain Outp
92. e dcm1 Macro VHDL Design Next you will instantiate the dcm1 macro for your VHDL or Verilog design To instantiate the 00001 macro for the VHDL design do the following 1 2 10 11 In the Hierarchy pane of the Project Navigator Design panel select dcm1 xaw In the Processes pane right click View HDL Instantiation Template and select Process Properties Choose VHDL for the HDL Instantiation Template Target Language value and click OK In the Processes pane double click View HDL Instantiation Template Highlight the component declaration template in the newly opened HDL Instantiation Template dcm1 vhi shown below 4 Notes 5 1 This instantiation template has been autc 8 std logic and std logic vector for the ports 7 2 To use this template to instantiate this 8 a8 COMPONENT dcmi 10 PORT 11 CLKIN IN IN std logic 12 RST IN IN std logic 13 CLKFX OUT OUT std logic 14 CLKIN IBUFG OUT OUT std logic 15 CLKO OUT OUT std logic 18 LOCKED OUT OUT std logic 17 Ve z 18 END COMPONENT Figure 3 19 VHDL DCM Component Declaration Select Edit gt Copy Place the cursor in the following section of the stopwatch vhd file Insert dcm1 component declaration here Select Edit Paste to paste the component declaration Highlight the instantiation template in the newly opened HDL Instantiation Template shown below 19 20 Inst dcmi dcmi PORT MAP 21 CLKIN IN gt
93. ect gt New Source 2 Inthe New Source Wizard select the IP Coregen amp Architecture Wizard source type and enter dem1 for the file name 3 Click Next In the Select IP dialog box select FPGA Features and Design gt Clocking gt Spartan 3E Spartan 3A gt Single DCM_SP New Source Wizard Select IP Create Coregen or Architecture Wizard IP Core View by Function View by Name Name Version AXI4 AXI4 Stream AxXI4 Lite Status License v W Embedded Processing FPGA Features and Design S clocking Mi Clocking Wizard E Spartan 3 Bp Spartan 3E Spartan 3A XX Board Deskew with an Internal Deskew DCM SP 13 1 Production X Cascading in Series with Two DCM SP 13 1 Production AX Clock Forwarding Board Deskew DCM SP 13 1 Production X Clock Switching with Two DCM SPs 13 1 Production Single DCM SP sh Production Ez B Mirtex 4 Virtex 5 5 77 IO Interfaces x gt Search IP Catalog All IP versions C only IP compatible with chosen part Figure 4 18 Selecting Single DCM Core Type 5 Click Next then click Finish The Clocking Wizard opens 6 Inthe Architecture Wizard Setup page select OK 7 Inthe General Setup page verify that RST CLKO and LOCKED ports are selected 60 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry 8 Select CLKFX port 9 Type 50 and select MHz for the Input Clock Frequency 10 Verify the following settings e Phas
94. ecting View Pop to Calling Schematic or select the Hierarchy Pop toolbar button when nothing in the schematic is selected You can also right click in an open space of the schematic and select Pop to Calling Schematic Figure 4 28 Hierarchy Pop Toolbar Button 68 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 g XILINX Design Entry Specifying Device Inputs Outputs You use I O markers to specify device I O on a schematic sheet All of the Schematic Editor schematics are netlisted to VHDL or Verilog and then synthesized by the synthesis tool of choice When the synthesis tool synthesizes the top level schematic HDL the I O markers are replaced with the appropriate pads and buffers Adding Input Pins Add five input pins to the stopwatch schematic reset clk lap_load mode and strtstop To add these components draw a hanging wire to the two inputs of dcm1 and to the sig_in pin of each debounce symbol Note Refer to Drawing Wires for detailed instructions Adding I O Markers and Net Names It is important to label nets and buses for the following reasons e Aids in debugging and simulation because you can more easily trace nets back to your original design For example any nets that remain unnamed in the design will be given generated names that will mean nothing to you later in the implementation process e Enhances readability and aids in documenting your design Label the five input nets
95. ectory 25 To close the Constraints Editor select File Close Assigning I O Locations Using the PlanAhead Tool Use the PlanAhead tool to add and edit the pin locations and area group constraints defined in the NGD file The PlanAhead tool writes the constraints to the project UCF file In the case of multiple UCF files in the project you will be asked to specify the constraint file in which to write new constraints If you modify existing constraints the constraints will be written to the constraint file in which they originated The PlanAhead tool also provides device specific design rule checks to aid you in pin planning and placement 100 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Assigning I O Locations Using the PlanAhead Tool The Translate step uses the design UCF file along with the design source netlists to produce a newer NGD file The NGD file incorporates the changes made in the design and the UCF file from the previous section To create IOB assignments for several signals 1 ISE In Depth Tutorial UG695 v14 1 April 24 2012 In the Hierarchy pane of the Project Navigator Design panel select the stopwatch module In the Processes pane expand User Constraints and double click I O Pin Planning PlanAhead Post Synthesis I O pin planning can be performed either pre or post synthesis Whenever possible it is recommended that the process be run post synthesis bec
96. ects in a limited space Creating an Archive To create an archive do the following 1 Select Project Archive 2 Inthe Project Archive dialog box enter the archive name and location 3 Click Save Note The archive contains all of the files in the project directory along with project settings Remote sources are included in the archive under a folder named remote sources For more information see the ISE Help Restoring an Archive You cannot restore an archived file directly into Project Navigator The compressed file can be extracted with any ZIP utility and you can then open the extracted file in Project Navigator www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Chapter 3 HDL Based Design Overview of HDL Based Design This chapter guides you through a typical HDL based design procedure using a design of a runner s stopwatch The design example used in this tutorial demonstrates many device features software features and design flow practices you can apply to your own design This design targets a Spartan 3A device however all of the principles and flows taught are applicable to any Xilinx device family unless otherwise noted The design is composed of HDL elements and two cores You can synthesize the design using Xilinx Synthesis Technology XST Synplity Synplify Pro or Precision software This chapter is the first chapter in the HDL Design Flow After the design is
97. el allows you to view only those source files associated with the selected Design View such as Implementation or Simulation Each file in the Hierarchy pane has an associated icon The icon indicates the file type HDL file schematic core or text file for example For a complete list of possible source ISE In Depth Tutorial UG695 v14 1 April 24 2012 8 www xilinx com XILINX Software Overview types and their associated icons see the Source File Types topic in the ISE Help From Project Navigator select Help gt Help Topics to view the ISE Help If a file contains lower levels of hierarchy the icon has a plus symbol to the left of the name You can expand the hierarchy by clicking the plus symbol You can open a file for editing by double clicking on the filename Processes Pane The Processes pane is context sensitive and it changes based upon the source type selected in the Sources pane and the top level source in your project From the Processes pane you can run the functions necessary to define run and analyze your design The Processes pane provides access to the following functions e Design Summary Reports Provides access to design reports messages and summary of results data Message filtering can also be performed e Design Utilities Provides access to symbol generation instantiation templates viewing command line history and simulation library compilation e User Constraints
98. er displays the libraries and their corresponding components Symbols ens Categories lt All Symbols gt lt C Xilinx 11 1 ISEs ISEexamples wtut_sc gt Arithmetic Buffer Carry_Logic Comparator Counter DDR Flip_Flop Decoder Flip_Flop General 10 IO FlipFlop IO Latch T v Symbols ch rled clk div 262k lcd control Figure 4 7 Symbol Browser Note The Options panel changes depending on the action you are performing in the schematic 2 The first component you will place is a cd4rled a 4 bit loadable bi directional BCD counter with clock enable and synchronous clear Select the cd4rled component using either of the following methods e Highlight the project directory category from the Symbol Browser dialog box and select the component cd4rled from the symbols list e Select All Symbols and enter cd4rled in the Symbol Name Filter at the bottom of the Symbol Browser 3 Move the mouse back into the schematic window You will notice that the cursor has changed to represent the cd4rled symbol 4 Move the symbol outline near the top and center of the sheet and click the left mouse button to place the object Note You can rotate new components being added to a schematic by selecting Ctrl R You can rotate existing components by selecting the component and then selecting Ctrl R 50 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Desig
99. erarchy this process displays the Precision software with a schematic view of the critical path of your HDL code mapped to the primitives associated with the target technology ISE In Depth Tutorial UG695 v14 1 April 24 2012 www xilinx com XILINX Synthesizing the Design Entering Synthesis Options and Synthesizing the Design Synthesis options enable you to modify the behavior of the synthesis tool to optimize according to the needs of the design For the tutorial the default property settings will be used To synthesize the design do the following 1 Inthe Hierarchy pane of the Project Navigator Design panel select stopwatch vhd or stopwatch v 2 Inthe Processes pane double click the Synthesize process Using the RTL Technology Viewer Precision Synthesis can generate a schematic representation of the HDL code that you have entered A schematic view of the code helps you analyze your design by seeing a graphical connection between the various components that Precision has inferred To launch the design in the RTL viewer double click the View RTL Schematic process The following figure displays the design in an RTL view stopwatch INTERF E Clocks H E Ports H E Nets H E Instances Transcript E Design Center Pg RTL Design Figure 3 28 Stopwatch Design in Precision Synthesis RTL Viewer You have now completed the design synthesis At this point an EDN
100. es contain models that are updated on a regular basis e XilinxCoreLib models are updated each time an IP Update is installed e All other models are updated each time a software update is installed When the models are updated you must recompile the libraries The compiled Xilinx simulation libraries are then available during the simulation of any design ModelSim PE SE or DE If you are using ModelSim PE SE or DE you must compile the simulation libraries with the updated models See the Synthesis and Simulation Design Guide UG626 Xilinx ISim Updated simulation libraries for ISim are precompiled and installed with ISE Design Suite installations Mapping Simulation Libraries in the modelsim ini File ModelSim uses the modelsim ini file to determine the location of the compiled libraries For example if you compiled the UNISIM library to c lib UNISI M the following mapping appears in the modelsim ini file UNISIM c lib UNISIM Note The modelsim ini is not applicable to ISim ModelSim searches for a modelsim ini file in the following locations until one is found e modelsim ini file pointed to by the MODELSIM environment variable e modelsim ini file in the current working directory e modelsim ini file in the directory where ModelSim is installed If the MODELSIM environment variable is not set and the modelsim ini file has not been copied to the working directory the modelsim ini file
101. et Mm debounce lcd control poe strtstop rst fan mode sg in Sig out ee contol 2 0 M me rr E FEF Ne l debounce SE BER Ge time cnt mode Ex dk a 190pundredths 40 B RE jhunsresths 0 i B load enhs 30 E MB E jentsi0 me up sec isb 30 E p oes60 m em eB ter 0 st d 7 0 au dk minutes 3 0 E eng Ejninutesi59 LT dr timer preset aro Se 00112 EO L a o WR f c TC a Figure 4 31 Completed Stopwatch Schematic To complete the schematic diagram do the following 1 Draw a hanging wire to the LOCKED OUT pin of dcm1 and name the wire locked See Drawing Wires and Adding Net Names 2 Draw a wire to connect the CLKFX_OUT pin of dcm1 to the CLK IN pin of clk_div_262k See Drawing Wires 3 Draw a hanging wire to the clk input of both the time cnt and statmach macros See Drawing Wires 4 Name both wires c1k_100 See Adding Net Names Note Remember that nets are logically connected if their names are the same even if the net is not physically drawn as a connection in the schematic This method is used to make the logical connection of clk_100 and several other signals 5 Draw a wire to connect the clk inputs of the three debounce macros and name the wire clk 100 6 Draw wires between the sig out pins of the deboun
102. evice XCF025 select the MCS file from your project working directory Click Open ISE In Depth Tutorial UG695 v14 1 April 24 2012 www xilinx com 137 Chapter 8 Configuration Using iMPACT g XILINX Saving the Project File After the chain has been fully described and configuration files are assigned you should save your iMPACT Project File IPF for later use To do this select File gt Save Project The Save As dialog box opens and you can browse and save your project file accordingly To restore the chain after reopening iMPACT select File gt Open Project and browse to the IPF Note Previous versions of the ISE Design Suite use Configuration Data Files CDF These files can still be opened and used in iMPACT iMPACT Project Files can also be exported to a CDF Editing Preferences To edit the preferences for the Boundary Scan configuration select Edit gt Preferences This selection opens the window shown in the following figure Click Help for a description of the preferences In this tutorial keep the default values and click OK E Preferences iMPACT General Options Category Set the general behavior of iMPACT Console XilinxNotify Proxy Settings Use iMPACT Main Wizard IMPACT Configuration Preferences Message Level Detailed v File Generation Controls Project Settings Controls Validate BSCAN Chain After Loading Project or CDF File WebTalk General Settings
103. ext create the schematic symbols for both the debounce and statmach HDL files as follows 1 Inthe Hierarchy pane of the Project Navigator Design panel select debounce vhd or debounce v 2 Inthe Processes panel expand Design Utilities and double click Create Schematic Symbol 3 Repeat this procedure for the statmach vhd file You are now ready to place the symbols on the stopwatch schematic Placing the statmach timer preset 00101 and debounce Symbols You can now place the statmach timer preset dcm1 and debounce symbols on the stopwatch schematic stopwatch sch To place the symbols do the following 1 In the Hierarchy pane of the Project Navigator Design panel double click stopwatch sch to open the schematic file in the Workspace Select Add Symbol or click the Add Symbol toolbar button gt Figure 4 25 Add Symbol Toolbar Button The Symbol Browser appears in the Options panel to the left of the schematic The Symbol Browser displays the libraries and their corresponding components View the list of available library components in the Symbol Browser Locate the project specific macros by selecting the project directory name in the Categories window Note The timer preset symbol is located in the ipcore_dir directory Select the appropriate symbol and add it to the stopwatch schematic in the approximate location as shown in Figure 4 26 Note Do not worry about drawing the wires
104. for the time specified The majority of this design runs at 100 Hz and would take a significant amount of time to simulate The first outputs to transition after RESET is released are the SF_D and LCD_E control signals at around 33 ms This is why the counter may seem like it is not working in a short simulation For the purpose of this tutorial only the DCM signals are monitored to verify that they work correctly Adding Signals ISE In Depth Tutorial To view internal signals during the simulation you must add them to the Wave window The ISE Design Suite automatically adds all the top level ports to the Wave window Additional signals are displayed in the Signal window based on the selected structure in the Structure window There are two basic methods for adding signals to the Simulator Wave window e Drag and drop from the Signal Object window Highlight signals in the Signal Object window and select Add gt To Wave gt Selected Signals The following procedure explains how to add additional signals in the design hierarchy In this tutorial you will be adding the DCM signals to the waveform If you are using ModelSim version 6 0 or higher all the windows are docked by default To undock the windows click the Undock icon g Figure 5 4 Undock Icon To add additional signals in the design hierarchy do the following 1 IntheStructure Instance window expand the uut hierarchy www xilinx com 81 UG695 v14 1 A
105. g Driven PAR PAR is run with the timing constraints specified in the input netlist the constraints file or both e Non Timing Driven PAR PAR is run ignoring all timing constraints Because you defined timing constraints earlier in this chapter the Place and Route PAR process performs timing driven placement and routing To run Place and Route do the following 1 Inthe Hierarchy pane of the Project Navigator Design panel select the stopwatch module 2 Inthe Processes pane expand Implement Design and double click Place amp Route The Place and Route process generates the reports shown in the following table Table 6 3 Reports Generated by PAR Report Description Provides a device utilization and delay summary Use Place and Route Report this report to verify that the design successfully routed and that all timing constraints were met Lists all nets in the design and the delays of all loads Asynchronous Delay Report onde nek For detailed information on the PAR reports refer to APAR REPONS the Command Line Tools User Guide UG628 Note Additional optional Place and Route reports can also be generated by enabling their creation in the Place and Route process properties When these reports are created they will appear in the Design Summary in the Secondary Reports section Note Timing warnings are generated for the offset in constraints on the clk signal The reason for these warnings i
106. g Report for the stopwatch design The minimum period value increased due to the actual routing delays The post Map timing report showed logic delays contributed to 80 to 90 of the minimum period attained The post layout report indicates that the logical delay value now equals between 30 and 40 of the period The total unplaced floors estimate changed as well The post layout result does not necessarily follow the 50 50 rule previously described because the worst case path primarily includes component delays For some hard to meet timing constraints the worst case path is mainly made up of logic delay Because total routing delay makes up only a small percentage of the total path delay spread out across two or three nets expecting the timing of these paths to be reduced any further is unrealistic In general you can reduce excessive block delays and improve design performance by decreasing the number of logic levels in the design Analyzing the Design using the PlanAhead Tool The PlanAhead tool can be used to perform post layout design analysis Graphical layout analysis and timing path viewing as well as floorplanning can be performed to both analyze design results as well as aid in design closure 1 ISE In Depth Tutorial UG695 v14 1 April 24 2012 In the Hierarchy pane of the Project Navigator Design panel select the stopwatch module In the Processes pane expand Implement Design expand Place amp Route and d
107. g edge on the CLKO OUT signal Br Figure 5 10 Find Next Transition Icon www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Behavioral Simulation Using ISim 5 Lookatthe bottom of the waveform for the distance between the two cursors The measurement should read 20000 ps This converts to 50 MHz which is the input frequency from the test bench which in turn should be the DCM CLKO output 6 Measure CLKFX OUT using the same steps as above The measurement should read 38462 ps This comes out to approximately 26 MHz Saving the Simulation The ModelSim simulator enables you to save the signals list in the Wave window after new signals or stimuli are added and after simulation is rerun The saved signals list can easily be opened each time the simulation is started To save the signals list do the following 1 Inthe Wave window select File Save Format 2 Inthe Save Format dialog box rename the file name from the default wave do to dcm signal do 3 Click Save After restarting the simulation select File Load in the Wave window to load this file Your behavioral simulation is complete To implement the design follow the steps in Chapter 6 Design Implementation Behavioral Simulation Using ISim Follow this section of the tutorial if you have skipped the previous section Behavioral Simulation Using ModelSim Now that you have a test bench in your project you can perform be
108. ge constraints Output skew reference pin lt Default gt Output Interface Detail The Single Data Rate and Dual Data Rate determine the output interface Output register timegroup type J 99e e The Output clock Pad Net is the clock net used to trigger the outgoing data Rising edge comment The optional Output pad timegroup limits the scope of the OFFSET OUT constraint to only those data pins defined in the PAD timegroup Falling edge constraints External clock to pad offset o Units Y ns Rising Constraint Parameters 4 new Pad Group may be defined by selecting the Create New Pad Group button Output skew reference pin The optional Rising Clock to Output OFFSET OUT is the time from the rising clock Defa edge at the input pin of the FPGA until data becomes valid at the output pin of the FPGA For source synchronous designs select lt Analyze Only from the pull Output register timegroup down list For the OFFSET OUT value and only a skew report will be generated The Output Skew Reference Pin is the reference signal in which the skew of all bits Falling edge comment in the bus will be reported against e The optional Output Register Timegroup is used to limit the scope of the constraint Figure 6 10 Clock to Pad Dialog Box 24 Select File Save in the Constraints Editor The changes are now saved in the stopwatch ucf file in your current working dir
109. gt Save to save the file The parsing message in the Console should now indicate that the file was checked successfully and is now free of errors Creating an HDL Based Module Next you will create a module from HDL code With the ISE Design Suite you can easily create modules from HDL code using the ISE Text Editor The HDL code is then connected to your top level HDL design through instantiation and is compiled with the rest of the design You will author a new HDL module This macro will be used to debounce the strtstop mode and lap_load inputs ISE In Depth Tutorial www xilinx com 19 UG695 v14 1 April 24 2012 Chapter 3 HDL Based Design 20 XILINX Using the New Source Wizard and ISE Text Editor In this section you create a file using the New Source wizard specifying the name and ports of the component The resulting HDL file is then modified in the ISE Text Editor To create the source file do the following 1 Select Project gt New Source The New Source Wizard opens in which you specify the type of source you want to In the Select Source Type page select VHDL Module or Verilog Module In the File Name field enter debounce New Source Wizard Select Source Type Select source type file name and its location y BMM File ChipScope Definition and Connection File I Implementation Constraints File 4 IP CORE Generator amp Architecture Wizard fal MEM File Schematic System
110. h tb and expand UUT The following figure shows the contents of the Instances and Processes panel for the VHDL flow The graphics and the layout of the window for a schematic or Verilog flow may be different Instance and Process Name Design Unit Block Type stopwatch tb VHDL Entity UUT stopwatch sto VHDL Entity ij t preset timer preset t VHDL Entity ij Inst dcmi demi behavio VHDL Entity ij dk divider clk div 262k VHDL Entity i lcd cntrl inst lcd control lcd VHDL Entity mode_debounce debounce beh VHDL Entity i strtstop debounce debounce beh VHDL Entity LU lap load debounce debounce beh VHDL Entity Uu timer inst time cnt time VHDL Entity timer_state statmach beh VHDL Entity C 252 stopwatch sto VHDL Process a 72 stopwatch tb VHDL Process CA 182 stopwatch tb VHDL Process ge std logic 1164 std logic 1164 VHDL Package 3 numeric std numeric std VHDL Package textio textio VHDL Package 9 vital timing vital timing VHDL Package e vital primitives vital primitives VHDL Package 00 std_logic_arith std_logic_arith VHDL Package std logic textio std logic textio VHDL Package 3 std logic unsigned std logic unsi VHDL Package CA vcomponents vcomponents VHDL Package M pa Instances and Processes Memory Source Files Figure 5 12 Simulation Hierarchy VHDL flow In the Instances and Processes panel select Inst dcm1 Click and drag CLKIN IN fr
111. hain Any supported Xilinx device will be recognized and labeled in iMPACT Any other device will be labeled as unknown The software will then highlight each device in the chain and prompt you to assign a configuration file or BSDL file Note f you were not prompted to select a configuration mode or automatic Boundary Scan mode right click in the iMPACT window and select Initialize Chain The software will identify the chain if the connections to the board are working Go to Troubleshooting Boundary Scan Configuration if you are having problems Assigning Configuration Files After initializing a chain the software prompts you for a configuration file see Figure 8 3 The configuration file is used to program the device There are several types of configuration files e Bitstream file bit rbt isc is used to configure an FPGA e JEDEC file jed isc is used to configure a CPLD e PROM file mcs hex is used to configure a PROM When the software prompts you to select a configuration file for the first device XC3S700A do the following 1 Select the BIT file from your project working directory 2 Click Open You should receive a warning stating that the startup clock has been changed to JtagClk www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Using Boundary Scan Configuration Mode 3 Click OK The following figure shows configuration file selection E ISE iMP
112. havioral simulation on the design using ISim The ISE Design Suite has full integration with ISim The ISE Design Suite enables ISim to create the work directory compile the source files load the design and perform simulation based on simulation properties To select ISim as your project simulator do the following 1 Inthe Hierarchy pane of the Project Navigator Design panel right click the device line xc3s700A 4f 484 and select Design Properties 2 Inthe Design Properties dialog box set the Simulator field to ISim VHDL Verilog Locating the Simulation Processes ISE In Depth Tutorial The simulation processes in Project Navigator enable you to run simulation on the design using ISim To locate the ISim processes do the following 1 Inthe View pane of the Project Navigator Design panel select Simulation and select Behavioral from the drop down list 2 Inthe Hierarchy pane select the test bench file stopwatch tr 3 In the Processes pane expand ISim Simulator to view the process hierarchy www xilinx com 85 UG695 v14 1 April 24 2012 Chapter 5 Behavioral Simulation XILINX The following simulation processes are available e Behavioral Check Syntax This process checks for syntax errors in the test bench e Simulate Behavioral Model This process starts the design simulation Specifying Simulation Properties You will perform a behavioral simulation on the stopwatch design after you set process pr
113. he skew of all bits Falling edge comment in the bus will be reported against e The optional Output Register Timegroup is used to limit the scope of the constraint Figure 6 8 Offset Out Constraint 18 In the Unconstrained Output Ports table select the sf d 0 through sf_d lt 7 gt signals using Shift Click to select multiple rows 19 Right click and select Create Time Group 20 In the Create Time Group dialog type display grp for the Time group name then click OK Create Time Group Time group name display arp Selected ports sf d 0 sf del sf d 2 sf_d lt 3 gt sf_d lt 4 gt sf de5 sf_d lt 6 gt sf de7 Figure 6 9 Creating a Time Group ISE In Depth Tutorial www xilinx com 99 UG695 v14 1 April 24 2012 Chapter 6 Design Implementation XILINX 21 When asked if you would like to create an offset constraint click OK 22 In the External clock to pad offset out field enter 32 ns 23 Click OK Create Clock to Pad OFFSET OUT Clock pad net and period SDR both edges DDR Output clock pad net Okin elk L orrseT OUT AFTER Output clock period information boc TxData Y X Clock Name clk Create Edit pN Skew gt Period 7 ns Duty Cycle 50 TxCik pee Output pad timegroup net Output pad timegroup display_orp vi External clock to pad offset o Units 32 v Ins lt Rising ed
114. hesis and Simulation Design Guide UG626 Timing Simulation Using ModelSim The Xilinx ISE Design Suite provides an integrated flow with the Mentor ModelSim simulator The ISE Design Suite enables you to create work directories compile source files initialize simulation and control simulation properties for ModelSim Note To simulate with ISim skip to Timing Simulation Using Xilinx ISim Whether you choose to use the ModelSim simulator or ISim for this tutorial the end result is the same 118 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Timing Simulation Using ModelSim Specifying Simulation Process Properties To set the simulation process properties do the following 1 ISE In Depth Tutorial UG695 v14 1 April 24 2012 In the View pane of the Project Navigator Design panel select Simulation and select Post Route from the drop down list In the Hierarchy pane select the test bench file stopwatch_tb In the Processes pane expand ModelSim Simulator right click Simulate Post Place amp Route Model and select Process Properties Note f the ModelSim Simulator processes do not appear ensure that you selected ModelSim in the Design Properties dialog box as described in Specifying a Simulator If this setting is correct and the ModelSim Simulator processes still do not appear ensure that Project Navigator can find the modelsim exe file To set the location for this file select
115. iat Chapter 1 Introduction About the In Depth Tutorial usus Tutorial Contents sees RR Tutorial Flows se esI Chapter 2 Overview of the ISE Design Suite Software Overview 1424 15 res pace vy de rcc e oU a do pa ee etie Using Project Revision Management Features Chapter 3 HDL Based Design Overview of HDL Based Design T tuus Getting Stared is ccce tesa ke bee e RC Rope ee Design Descriptif reut ba de ooa der hin o guten d Poche ion Qt eet e a Design Bitty i cite ki ree ER PERIERE RA ER ERE HE Ed Synthesizing the Design cocta sre rd em eie Re Chapter 4 Schematic Based Design Overview of Schematic Based Design 6 Getting Started si coctis He pe Eb bl e ee obtain Design Description iieceseeee roe eR ERE RRCCHERER ER C dS Design ENY NONEM NUM RHOD CU TTD HN E mnie OD Chapter 5 Behavioral Simulation Overview of Behavioral Simulation Flow ModelSim Setup i o n ze he Er I RRROHPERAORE CR e C dde E E ISim Sel p is sodes qu eed e bhedadeeppdee pd uad squad dark Getting Started iiie co Ca bcn DOCE OCIO S Adding an HDL Test Bench sssssessss Behavioral Simulation Using ModelSim Behavioral Simulation Using ISim Luuuuuuuuu Chapter 6 Design Implementation Overview of Design Implementation Luuuuue
116. ic Accessible from the Launch Tools hierarchy this process displays the Synplify or Synplify Pro software with a schematic view of your HDL code mapped to the primitives associated with the target technology www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Synthesizing the Design Entering Synthesis Options and Synthesizing the Design To synthesize the design set the global synthesis options as follows 1 Inthe Hierarchy pane of the Project Navigator Design panel select stopwatch vhd or stopwatch v In the Processes pane right click Synthesize and select Process Properties In the Synthesis Options dialog box select the Write Vendor Constraint File box Click OK to accept these values m ROI Double click the Synthesize process to run synthesis Note This step can also be done by selecting stopwatch vhd or stopwatch v clicking Synthesize in the Processes pane and selecting Process gt Run Examining Synthesis Results To view overall synthesis results double click View Synthesis Report under the Synthesize process The report consists of the following sections e Compiler Report e Mapper Report Timing Report e Resource Utilization Compiler Report The compiler report lists each HDL file that was compiled names which file is the top level and displays the syntax checking result for each file that was compiled The report also lists FSM extractions inferred memory warn
117. ic design through instantiation and compiled with the rest of the design You will author a new HDL module This macro will be used to debounce the strtstop mode and lap_load inputs Using the New Source Wizard and ISE Text Editor In this section you create a file using the New Source wizard specifying the name and ports of the component The resulting HDL file is then modified in the ISE Text Editor To create the source file do the following 1 Sm Hx Gee Select Project New Source Select VHDL Module or Verilog Module In the File Name field enter debounce Click Next Enter two input ports named sig in and clk and an output port named sig out for the debounce component as follows a Inthe first three Port Name fields enter sig in clk and sig out b Set the Direction field to input for sig in and clk and to output for sig out c Leave the Bus designation boxes unchecked New Source Wizard Define Module Specify ports for module Entity name debounce Architecture name Behavioral Port Name Direction sig in ck Sig out OOO s TRIR IRIRI n v Figure 4 20 New Source Wizard www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry 6 Click Next to view a description of the module 7 Click Finish to open the empty HDL file in the ISE Text Editor The VHDL file is shown
118. ierarchy pane select the test bench file stopwatch tr www xilinx com 79 UG695 v14 1 April 24 2012 Chapter 5 Behavioral Simulation 3 XILINX In the Processes pane expand ModelSim Simulator to view the process hierarchy The Simulate Behavioral Model process is available which starts the design simulation If ModelSim is installed but the processes are not available the Project Navigator preferences may not be set correctly To set the ModelSim location do the following 1 2 3 Select Edit Preferences In the Preferences dialog box expand ISE General and click Integrated Tools In the right pane under Model Tech Simulator browse to the location of the modelsim executable for example C modeltech_xe win32xoem modelsim exe Specifying Simulation Properties You will perform a behavioral simulation on the stopwatch design after you set process properties for simulation Project Navigator allows you to set several ModelSim simulator properties in addition to the simulation netlist properties To see the behavioral simulation properties and to modify the properties for this tutorial do the following 1 5 In the Hierarchy pane of the Project Navigator Design panel select the test bench file stopwatch tb In the Processes pane expand ModelSim Simulator right click Simulate Behavioral Model and select Process Properties In the Process Properties dialog box Figure 5 3 set the P
119. ign panel select the stopwatch module 2 Inthe Processes pane right click Generate Programming File and select Process Properties 3 Inthe Process Properties dialog box click the Startup Options category 112 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX 4 Creating Configuration Data Change the FPGA Start Up Clock property from CCLK to JTAG Clock S lt Process Properties Startup Options Category Switch Name Property Name Value General Options 19 StartUpClk FPGA Start Up Clock JTAG Clock Configuration Options Startup Options 14 DonePipe X Enable Internal Done Pipe Readback Options 9 DONE cycle Done Output Events Default 4 v 5 d wake Opti 1 uspend Wake Options 19 GTS_cycle Enable Outputs Output Events Default 5 v 19 GWE_cycle Release Write Enable Output Events Default 6 v l g LCK_cycle Wait for DLL Lock Output Events Default NoWait ai a DriveDone Drive Done Pin High L1 Property display level Advanced v Display switch names Cancel Apply Help Figure 6 25 Process Properties Startup Options Note You can use CCLK if you are configuring Select Map or Serial Slave Click OK In the Processes pane double click Generate Programming File to create a bitstream of this design The BitGen program creates the bitstream file in this tutorial the stopwatch bit file which contains the actual configuration dat
120. ile New constraints are written to the UCF file specified in Constraints Editor The Translate step NGDBuild uses the UCF file along with design source netlists to produce a newer NGD file which incorporates the changes made The Map program the next section in the design flow then reads the NGD In this design the stopwatch ngd and stopwatch ucf files are automatically read into the Constraints Editor In the following section a PERIOD Global OFFSET IN Global OFFSET OUT and TIMEGRP OFFSET IN constraint will be created and written in the UCF and used during implementation The Clock Domains branch of the Timing Constraints tab automatically displays all the clock nets in your design and enables you to define the associated period pad to setup and clock to pad values Note that many of the internal names will vary depending on the design flow and synthesis tool used www xilinx com 95 UG695 v14 1 April 24 2012 Chapter 6 Design Implementation XILINX The following figure shows the Constraints Editor File Edit View Project Source Process Tools Window Layout Help 3 PEASE x xoa i pP paraaan nal An E Lr Timing Constraints enex Create Timing Constraints for Clock Domains PERIOD Source Constraint File by direct entry or right click to open context menu topwatch ucf BEL e TIMESPEC Name Clock Time Name Clock Net Period Duty Cycle Edge Reference TIMESPEC Factor Phase Shift Input Jitter Sou
121. imary user interface for the ISE Design Suite Project Navigator and the synthesis tools available for your design Chapter 3 HDL Based Design guides you through a typical HDL based design procedure using a design of a runner s stopwatch This chapter also shows how to use ISE Design Suite accessories such as the CORE Generator tool and ISE Text Editor Chapter 4 Schematic Based Design explains many different facets of a schematic based ISE Design Suite design flow using a design of a runner s stopwatch This chapter also shows how to use ISE Design Suite accessories such as the CORE Generator tool and ISE Text Editor Chapter 5 Behavioral Simulation explains how to simulate a design before design implementation to verify that the logic that you have created is correct Chapter 6 Design Implementation describes how to Translate Map Place Route and generate a bitstream file for designs Chapter 7 Timing Simulation explains how to perform a timing simulation using the block and routing delay information from the routed design to give an accurate assessment of the behavior of the circuit under worst case conditions Chapter 8 Configuration Using iMPACT explains how to program a device with a newly created design using the IMPACT configuration tool www xilinx com 5 Chapter 1 Introduction Tutorial Flows XILINX This document contains three tutorial flows In this section the three tutorial flows are outl
122. ined and briefly described to help you determine which sequence of chapters applies to your needs The tutorial flows include the following HDL design flow Schematic design flow Implementation only flow HDL Design Flow The HDL design flow is as follows 1 2 Chapter 3 HDL Based Design Chapter 5 Behavioral Simulation Note Although behavioral simulation is optional it is strongly recommended in this tutorial flow Chapter 6 Design Implementation Chapter 7 Timing Simulation Note Although timing simulation is optional it is strongly recommended in this tutorial flow Chapter 8 Configuration Using iMPACT Schematic Design Flow The schematic design flow is as follows 1 2 Chapter 4 Schematic Based Design Chapter 5 Behavioral Simulation Note Although behavioral simulation is optional it is strongly recommended in this tutorial flow Chapter 6 Design Implementation Chapter 7 Timing Simulation Note Although timing simulation is optional it is strongly recommended in this tutorial flow Chapter 8 Configuration Using iMPACT Implementation Only Flow The implementation only flow is as follows 1 2 Chapter 6 Design Implementation Chapter 7 Timing Simulation Note Although timing simulation is optional it is strongly recommended in this tutorial flow Chapter 8 Configuration Using iMPACT www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Chapter 2 Overview
123. ings on latches unused ports and removal of redundant logic Note Black boxes modules not read into a design environment are always noted as unbound in the Synplify reports As long as the underlying netlist ngo ngc or edn for a black box exists in the project directory the implementation tools merge the netlist into the design during the Translate phase Mapper Report The mapper report lists the constraint files used the target technology and attributes set in the design The report lists the mapping results of flattened instances extracted counters optimized flip flops clock and buffered nets that were created and how FSMs were coded Timing Report The timing report section provides detailed information on the constraints that you entered and on delays on parts of the design that had no constraints The delay values are based on wireload models and are considered preliminary Consult the post Place and ISE In Depth Tutorial www xilinx com 37 UG695 v14 1 April 24 2012 Chapter 3 HDL Based Design XILINX Route timing reports discussed in Chapter 6 Design Implementation for the most accurate delay information Performance Summary 3 3 3 3 3 3 9 3 3 9 3 3 3 3 3 3 Worst slack in design 1 581 Starting Clock stopwatch clk divider clk 100 inferred clock stopwatch dcmi inst CLKFX BUF derived clock Requested Estimated Requested Estimated Freque
124. ion Library de i Simulation v work Adding files to project BBBNRERRRERRRRRRRRRRRRRRRRRENI o 1 fies 0 errors Figure 5 2 Adding Verilog Test Fixture Behavioral Simulation Using ModelSim Now that you have a test bench in your project you can perform behavioral simulation on the design using the ModelSim simulator The ISE Design Suite has full integration with the ModelSim simulator The ISE Design Suite enables ModelSim to create the work directory compile the source files load the design and perform simulation based on simulation properties To simulate with ISim skip to Behavioral Simulation Using ISim Whether you choose to use the ModelSim simulator or the ISim simulator for this tutorial the end result is the same To select ModelSim as your project simulator do the following 1 Inthe Hierarchy pane of the Project Navigator Design panel right click the device line xc3s700a 4f 484 and select Design Properties 2 Inthe Design Properties dialog box set the Simulator field to ModelSim with the appropriate type and language Locating the Simulation Processes ISE In Depth Tutorial The simulation processes in Project Navigator enable you to run simulation on the design using ModelSim To locate the ModelSim simulator processes do the following 1 Inthe View pane of the Project Navigator Design panel select Simulation and select Behavioral from the drop down list 2 Inthe H
125. ject Navigator Design panel select the stopwatch module 2 Inthe Processes pane expand User Constraints and double click Create Timing Constraints We C No Processes Running irl Processes stopwatch Design Summary Reports E m Design Utilities e User Constraints Create Timing Constraints T O Pin Planning PlanAhead Pre Synthesis a fel I O Pin Planning PlanAhead Post Synthesis fe Floorplan Area IO Logic Plan head amp A Synthesize XST amp C Implement Design Q Generate Programming File GT Configure Target Device qu Analyze Design Using ChipScope Figure 6 2 Create Timing Constraints Process This automatically runs the Translate step which is discussed in the following section Then the Constraints Editor opens Translating the Design The ISE Design Suite manages the files created during implementation The ISE design tools use the settings that you specified in the Process Properties dialog box This gives you complete control over how a design is processed Typically you set your properties first You then run through the entire flow by running the Implement Design process The Implement Design process includes the three sub processes Translate Map and Place and Route You can simply run the Implement Design process to automate the running of all three sub processes or you can run the sub processes individually In this tutorial you will run the sub processes individually
126. le Translates and optimizes the HDL code into a set of components that the synthesis tool can recognize Map Translates the components from the compile stage into the target technology s primitive components The synthesis tool can be changed at any time during the design flow To change the synthesis tool do the following 1 Inthe Hierarchy pane of the Project Navigator Design panel select the targeted part 2 Right click and select Design Properties 3 Inthe Design Properties dialog box click the Synthesis Tool value and use the pull down arrow to select the desired synthesis tool from the list Project Settings Property Name Value Top Level Source Type HDL w Evaluation Development Board None Specified v Product Category All sj Family Spartan3A and Spartan3AN v Device XC35700A Mj Package FG484 M Speed 4 v Synthesis Tool XST VYHDL Verilog v Simulator ISim VHDL Verilog v Preferred Language VHDL v Property Specification in Project File Store all values v Manual Compile Order VHDL Source Analysis Standard VHDL 93 v Enable Message Filtering L Figure 3 24 Specifying Synthesis Tool Note f you do not see your synthesis tool among the options in the list you may not have the software installed or may not have it configured in the ISE Design Suite The synthesis tools are configured in the Preferences dialog box Select Edit gt Preferences expan
127. le the clock or timer is not counting e lap_load This is a dual function signal In clocking mode it displays the current clock value in the Lap display area In timer mode it loads the pre assigned values from the ROM to the timer display when the timer is not counting The following are outputs signals for the design e 100 e lcd rs lcd rw These outputs are the control signals for the LCD display of the Spartan 3A demo board used to display the stopwatch times e sf d 7 0 Provides the data values for the LCD display Functional Blocks ISE In Depth Tutorial The completed design consists of the following functional blocks e clk_div_262k Macro that divides a clock frequency by 262 144 Converts 26 2144 MHz clock into 100 Hz 50 duty cycle clock www xilinx com 17 UG695 v14 1 April 24 2012 Design Entry 18 Chapter 3 HDL Based Design XILINX dcm1 Clocking Wizard macro with internal feedback frequency controlled output and duty cycle correction The CLKFX_OUT output converts the 50 MHz clock of the Spartan 3A demo board to 26 2144 MHz debounce Schematic module implementing a simplistic debounce circuit for the strtstop mode and lap_load input signals lcd control Module controlling the initialization of and output to the LCD display statmach State machine HDL module that controls the state of the stopwatch timer preset CORE Generator tool 64x20 ROM This macro contains 64 pre
128. lementation Messaging features such as message filtering tagging and incremental messaging are also available from this view Using Project Revision Management Features Project Navigator enables you to manage your project as follows Understanding the ISE Project File The ISE project file xise extension is an XML file that contains all source relevant data for the project as follows e ISE Design Suite version information e List of source files contained in the project e Source settings including design and process properties The ISE project file does not contain the following e Process status information e Command history e Constraints data Note A gise file also exists which contains generated data such as process status You should not need to directly interact with this file The ISE project file includes the following characteristics which are compatible with source control environments e Contains all of the necessary source settings and input data for the project e Can be opened in Project Navigator in a read only state Only updated or modified if a source level change is made to the project e Can be kept in a directory separate from the generated output directory working directory Note A source level change is a change to a property or the addition or removal of a source file Changes to the contents of a source file or changes to the state of an implementation run are not considered source level
129. ll that the associated library is work and click OK The Hierarchy pane in the Design panel displays all of the source files currently added to the project with the associated entity or module names Opening the Schematic File in the Xilinx Schematic Editor 46 The stopwatch schematic available in the wtut_sc project is incomplete In this tutorial you will update the schematic in the Schematic Editor After you create the project in Project Navigator and add the source files you can open the stopwatch sch file for editing To open the schematic file double click stopwatch sch in the Hierarchy pane of the Design panel The stopwatch schematic diagram opens in the Project Navigator Workspace You will see the unfinished design with elements in the lower right corner as shown in the following figure www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry clk 26214k clk_div_262k T v 262144 tg Icd control r t int s Dnro 20 E icd rsjod rwlod e dk 26214k ox Ls Er mose d rs oounti 3 0 MM EE EA 2 lcd rw count2 3 0 eee counti 3 0 ot count4 3 0 counts 3 0 Figure 4 3 Incomplete Stopwatch Schematic Manipulating the Window View The View menu commands enable you to manipulate how the schematic is displayed Select View gt Zoom gt In until you can comfortably view the schematic The schem
130. low The graphics and the layout of the Structure Instance window for a Verilog or VHDL flow may be different thal gbl GF stopwatch_tb stopwatch tb uut stopwatch Ld HASSIGNH218 stopwatch H ASSIGNH218 stopwatch Ly ASSIGNH218 stopwatch ww HASSIGNH2188 stopwatch sm Mcd cntrl inst L X AND2 sm Mcd cnt inst X AND2 if Mcd cnul inst L XV AND2 Mcd cnt insU L X AND2 Med cnt inst L X AND2 inst L X AND2 inst L X AND2 inst L X AND2 inst L X AND2 inst L X AND2 inst L X AND2 inst L X AND2 inst L X AND2 inst l AND2 inst l lcd cntrl lcd cntrl lcd cntrl lcd cntrl lcd cntrl icd cntrl icd cntr icd cntr icd cntr cd cntr ad ES E EST al Figure 7 4 Structure Instance Window Schematic Flow Click the Structure Instance window and select Edit gt Find Type X DcMin the search box and select Entity Module in the Field section After ModelSim locates X DCM select X DCM SP and click on the signals objects window All the signal names for the DCM will be listed Select the Signal Object window and select Edit Find Type CLKIN in the search box and select the Exact checkbox Click and drag CLKIN from the Signal Object window to the Wave window 122 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Timing Simulation Using ModelSim Click and d
131. m the default wave do to dcm signal tim do Imi Save Format ioj x dcm signal tim do Browse Save contents IV Waveform formats r OK Cancel Figure 7 10 Save Format Dialog Box 3 Click OK After restarting the simulation you can select File gt Load in the Wave window to reload this file Your timing simulation is complete and you are ready to program your device by following Chapter 8 Configuration Using iMPACT www xilinx com 125 UG695 v14 1 April 24 2012 Chapter 7 Timing Simulation XILINX Timing Simulation Using Xilinx ISim Follow this section of the tutorial if you have skipped the previous section Timing Simulation Using ModelSim 126 Specifying Simulation Process Properties To set the simulation process properties do the following 1 In the View pane of the Project Navigator Design panel select Simulation and select Post Route from the drop down list In the Hierarchy pane select the test bench file stopwatch_tb In the Processes pane expand ISim Simulator right click Simulate Post Place amp Route Model and select Process Properties In the Process Properties dialog box ensure that the Property display level is set to Advanced This global setting enables you to see all available properties Select the Simulation Model Properties category These properties set the options that NetGen uses when generating the simulation netlist For a description
132. mes work stopwatch_tb 1510 UUT Instance Name UUT Other Simulator Commands Property display level Advanced vj Display switch names Default Figure 7 11 Simulation Properties 7 Click OK to close the Process Properties dialog box Performing Simulation To start the timing simulation double click Simulate Post Place and Route Model in the Processes pane When a simulation process is run Project Navigator automatically runs NetGen to generate a timing simulation model from the placed and routed design The ISim then compiles the source files loads the design and runs the simulation for the time specified Note The majority of this design runs at 100 Hz and would take a significant amount of time to simulate This is why the counter will seem like it is not working in a short simulation For the purpose of this tutorial only the DCM signals will be monitored to verify that they work correctly Adding Signals To view signals during the simulation you must add them to the waveform window The ISE Design Suite automatically adds all the top level ports to the waveform window All available external top level ports and internal signals are displayed in the simulation hierarchy The following procedure explains how to add additional signals in the design hierarchy In this tutorial you will be adding the DCM signals to the waveform 1 Inthe Instances and Processes panel expand the stopwatch tb hierarchy
133. mode control Draw wires to connect the outputs of time cnt to the corresponding inputs of lcd control See Drawing Wires Save the design by selecting File Save You have now completed the schematic design To continue with the schematic flow do either of the following ISE In Depth Tutorial UG695 v14 1 April 24 2012 Go to Chapter 5 Behavioral Simulation to perform a pre synthesis simulation of this design Proceed to Chapter 6 Design Implementation to place and route the design www xilinx com 73 Chapter 4 Schematic Based Design 74 www xilinx com XILINX ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Chapter 5 Behavioral Simulation Overview of Behavioral Simulation Flow The Xilinx ISE Design Suite provides an integrated flow with the Mentor ModelSim simulator and the Xilinx ISim simulator that allows simulations to be run from the Xilinx Project Navigator The examples in this tutorial demonstrate how to use the integrated flow Whether you use the ModelSim simulator or the ISim simulator with this tutorial you will achieve the same simulation results For additional information about simulation and for a list of other supported simulators see the Synthesis and Simulation Design Guide UG626 This tutorial provides an introduction to the simulation flow within Project Navigator including highlights of features within the ModelSim and ISim simulators For more de
134. n Sf Clocking q Clocking Wizard Spartan 3 Bp Spartan 3E Spartan 3A XX Board Deskew with an Internal Deskew DCM SP AX Cascading in Series with Two DCM SP 13 AX Clock Forwarding Board Deskew DCM SP X Clock Switching with Two DCM SPs g Single DCM_SP amp B Virtex 4 Virtex 5 tH 1 IO Interfaces Production Production Production Production Production Search IP Catalog All IP versions C only IP compatible with chosen part Figure 3 18 Selecting Single DCM_SP IP Type Click Next and click Finish The Clocking Wizard is launched In the Architecture Wizard Setup page select OK In the General Setup page verify that RST CLKO and LOCKED ports are selected Select CLKFX port Enter 50 and select MHz for the Input Clock Frequency Verify the following settings e Phase Shift NONE e CLKIN Source External Single e Feedback Source Internal e Feedback Value 1X e Use Duty Cycle Correction Selected Click the Advanced button Select Wait for DCM lock before DONE Signal goes high Click OK Click Next and then click Next again Select Use output frequency and enter 26 2144 in the box and select MHz 26 2144Mhz 2 100Hz Click Next and then click Finish www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry The dcm1 xaw file is added to the list of project source files in the Hierarchy pane of the Design panel Instantiating th
135. n Entry 5 Place three more cd4rled symbols on the schematic by moving the cursor with attached symbol outline to the desired location and clicking the left mouse button See the following figure cd4rled ppe m cared i mcm gene E E gt 004060 oa xL al gt r1 ch4rled oe cd4rled a Figure 4 8 Partially Completed time_cnt Schematic 6 Follow the procedure outlined in steps 1 through 5 above to place the following components on the schematic sheet e AND2b1 e ch4rled e AND5 Refer to Figure 4 8 for placement locations 7 To exit the Symbols mode press the Esc key on the keyboard ISE In Depth Tutorial www xilinx com 51 UG695 v14 1 April 24 2012 Chapter 4 Schematic Based Design XILINX 52 For a detailed description of the functionality of Xilinx library components right click the component and select Symbol gt Symbol Info Symbol information is also available in the Libraries Guides Correcting Mistakes If you make a mistake when placing a component you can easily move or delete the component as follows e To move the component click the component and drag the mouse around the window e To delete a placed component use either of the following methods e Click the component and press the Delete key on your keyboard e Right click the
136. n LCD display Continuing from Design Entry ISE In Depth Tutorial If you have followed the tutorial using either the HDL design flow or the schematic design flow you have created a project completed source files and synthesized the design If you do not have a stopwatch ucf constraint file in your project create one as follows 1 Inthe Hierarchy pane of the Project Navigator Design panel select the top level source file stopwatch Select Project gt New Source Select Implementation Constraints File Enter stopwatch ucf as the file name Click Next Click Finish 9x 10 O9 2 With a UCF in the project you are now ready to begin this chapter Skip to the Specifying Options section www xilinx com 91 UG695 v14 1 April 24 2012 92 Chapter 6 Design Implementation XILINX Starting from Design Implementation The tutorial project files are provided with the ISE Design Suite Tutorials available from the Xilinx website Download the pre synthesized design files After you have downloaded the tutorial project files from the web unzip the tutorial projects into the c xilinx_tutorial directory replacing any existing files in that directory When you unzip the tutorial project files into c xxilinx tutorial the directory wtut edif is created within c xilinx_tutorial and the tutorial files are copied into the newly created directory The following table lists the locations of tutorial source files
137. n Project Navigator double click stopwatch vhd to open the file in ISE Text Editor 2 Place the cursor after the following line Insert CORE Generator ROM component declaration here 3 Select Edit gt Insert File then select ipcore dir timer preset vho and click Open The VHDL template file for the CORE Generator tool instantiation is inserted i5 Begin Cut here for COMPONENT Declaration COMP T G 122 component timer preset 123 port 124 a IN std logic VECTOR 5 downto 0 125 Spo OUT std logic VECTOR 19 downto 0 126 end component 127 i28 Synplicity black box declaration 129 attribute syn black box boolean 130 attribute syn_black_box of timer_preset component is true 131 IS COMP TAG END End COMPONENT Declaration Figure 3 15 VHDL Component Declaration for CORE Generator Tool Module 4 Highlight the inserted code from Begin Cut here for INSTANTIATION Template to INST TAG END END INSTANTIATION Template Select Edit gt Cut Place the cursor after the following line Insert CORE Generator ROM Instantiation here Select Edit Paste to place the core instantiation Change the instance name from your instance nametot preset Edit this instantiated code to connect the signals in the stopwatch design to the ports of the CORE Generator tool module as shown below Hie Sea Insert CORE Generator ROM instantiation
138. nalysis will help to uncover issues that cannot be found in a static timing analysis alone To verify the design the design should be analyzed both statically and dynamically In this chapter you will perform a timing simulation using either the ModelSim simulator or the Xilinx ISim simulator Getting Started The following sections outline the requirements to perform this part of the tutorial flow Required Software To simulate with ModelSim you must have the Xilinx ISE Design Suite and ModelSim simulator installed Refer to Chapter 5 Behavioral Simulation for information on installing and setting up ModelSim Simulating with ISim requires that the ISE Design Suite is installed ISE In Depth Tutorial www xilinx com 117 UG695 v14 1 April 24 2012 Chapter 7 Timing Simulation XILINX Required Files The timing simulation flow requires the following files Design files VHDL or Verilog This chapter assumes that you have completed Chapter 6 Design Implementation and thus have a placed and routed design The NetGen tool will be used in this chapter to create a simulation netlist from the placed and routed design which will be used to represent the design during the timing simulation e Test bench file VHDL or Verilog To simulate the design a test bench is needed to provide stimulus to the design You should use the same test bench that was used to perform the behavioral simulation Please refer to Adding an HD
139. ncy Frequency Period Period Slack 305 3 MHz 259 5 MHz 3 276 3 854 0 578 111 6 MHz 94 9 MHz 8 959 10 540 1 581 Figure 3 27 Synplify Estimated Timing Data Resource Utilization This section of the report lists all of the resources that the Synplify software uses for the given target technology You have now completed Synplify synthesis At this point a netlist EDN file exists for the stopwatch design To continue with the HDL flow do either of the following Go to Chapter 5 Behavioral Simulation to perform a pre synthesis simulation of this design Proceed to Chapter 6 Design Implementation to place and route the design Synthesizing the Design Using Precision Synthesis Now that you have entered and analyzed the design the next step is to synthesize the design In this step the HDL files are translated into gates and optimized to the target architecture Processes available for synthesis using the Precision software are as follows 38 Check Syntax Checks the syntax of the HDL code View RTL Schematic Accessible from the Launch Tools hierarchy this process displays the Precision software with a schematic view of your HDL code View Technology Schematic Accessible from the Launch Tools hierarchy this process displays the Precision software with a schematic view of your HDL code mapped to the primitives associated with the target technology View Critical Path Schematic Accessible from the Launch Tools hi
140. nets To tap off a single bit of each bus do the following 1 Select Add gt Bus Tap or click the Add Bus Tap toolbar button b Figure 4 11 Add Bus Tap Toolbar Button The cursor changes indicating that you are now in Draw Bus Tap mode 2 Inthe Add Bus Tap Options that appear in the Options panel choose the Right orientation for the bus tap www xilinx com 53 UG695 v14 1 April 24 2012 54 Chapter 4 Schematic Based Design XILINX 3 Click on the hundreths 3 0 bus with the left mouse button The Selected Bus Name and the Net Name values in the Options panel are now populated Note The indexes of the Net Name may be incremented or decremented by clicking the arrow buttons next to the Net Name box 4 With hundredths 3 as the Net Name value move the cursor so the tip of the attached tap touches the Q3 pin of the top cd4rled component Note Four selection squares appear around the pin when the cursor is in the correct position 5 Click once when the cursor is in the correct position A tap is connected to the hundredths 3 0 bus and a wire named hundreths 3 is drawn between the tap and the Q3 pin Click successively on pins Q2 O1 and Q0 to create taps for the remaining bits of the hundredths 3 0 bus 6 Repeat Steps 3 to 5 to tap off four bits from each of the remaining four buses Note It is the name of the wire that makes the electrical connection between the bus and the wire for exam
141. nst dcmi CLKFX BUF TS clk 0 52 HIGH 50 se Pathi Setup _0 487 lcd_cntrl_inst state F5M_FFd lcd_cntrl_instjcount_temp 26 12 815 5 676 55 7 a cik_26214k P Path2 Setup 0 487 lcd cntrl inst state FSM FFd7 lcd cntrl instjcount temp 27 12 815 5676 557 8k 26214k ck 26214k P Path3 Setup 0 487 lcd entr inst state FSM FFd7 lcd cntrl instjcount temp 28 12 815 5 676 55 7 8ck26214k 26214k P Path Setup 0 746 lcd cntrl inst state FSM FFd36 lcd cntrl instjcount temp 26 12 609 5572 558 Bck 26214k 26214k TRCE results 1 36 paths x Figure 6 24 Viewing Timing Path in PlanAhead Tool 4 Zoominon the path in the Device view by clicking and dragging a box around the area For a detailed tutorial on the full set of capabilities in the PlanAhead tool related to timing analysis and design closure select Help PlanAhead Tutorials and see the Design Analysis and Floorplanning Tutorial UG676 5 Toclose the PlanAhead tool select File Exit Creating Configuration Data After analyzing the design you need to create configuration data A configuration bitstream is created for downloading to a target device or for formatting into a PROM programming file In this tutorial you will create configuration data for a Xilinx Serial PROM To create a bitstream for the target device set the properties and run configuration as follows 1 Inthe Hierarchy pane of the Project Navigator Des
142. nx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Specifying Options Specifying Options This section describes how to set process properties for design implementation The implementation properties control how the software maps places routes and optimizes a design To set the implementation properties for this tutorial do the following 1 2 3 In the View pane of the Project Navigator Design panel select Implementation In the Hierarchy pane select the stopwatch top level file In the Processes pane right click the Implement Design process and select Process Properties The Process Properties dialog box provides access to the Translate Map Place and Route and Timing Report properties In the left pane of the dialog box you can click the different categories to set properties for each design implementation phase Ensure that you have set the Property display level to Advanced This global setting enables you to see all available properties Click the Place amp Route Properties category Change the Place amp Route Effort Level Overall to High This option increases the overall effort level of Place and Route during implementation Process Properties Place amp Route Properties Category Switch Name Property Name Value Translate Properties 4 P Place And Route Mode Normal Place and Route Map Properties Place amp Route Properties ol Place amp Route Effort Level O
143. o the directory in which you installed the project In the Name field enter wtut_whd or wtut ver Verify that HDL is selected as the Top Level Source Type and click Next ISE In Depth Tutorial www xilinx com 15 UG695 v14 1 April 24 2012 Chapter 3 HDL Based Design g XILINX The New Project Wizard Device Properties page appears New Project Wizard Project Settings Specify device and project properties Select the device and design flow For the project Property Name Evaluation Development Board Product Category Family Spartan3A and Spartan3AN Device XC35700A Package FG484 Speed 4 sI ESES EIES ES Top Level Source Type HDL Synthesis Tool XST vHDL Verilog Simulator ISim VHDLj Vverilog Preferred Language VHDL Property Specification in Project File Store all values Manual Compile Order Oo VHDL Source Analysis Standard VHDL 93 Figure 3 3 New Project Wizard Device Properties Page 5 Selectthe following values in the New Project Wizard Device Properties page e Product Category All e Family Spartan3A and Spartan3AN e Device XC3S700A e Package FG484 e Speed 4 e Synthesis Tool XST VHDL Verilog e Simulator ISim VHDL Verilog e Preferred Language VHDL or Verilog depending on preference This will determine the default language for all processes that generate HDL files Other properties can be left at their default values 6 Click Next
144. oard Specifying Boundary Scan Configuration Mode In iMPACT creating a new project includes specifying the configuration mode and the device to program To select Boundary Scan Mode do the following 1 Select File gt New Project 2 Inthe Automatically create and save a project dialog box select Yes 3 Inthe Welcome to iMPACT dialog box select Configure Devices using Boundary Scan JTAG 4 Ensure that Automatically connect to a cable and identify Boundary Scan chain is selected ISE In Depth Tutorial www xilinx com 135 UG695 v14 1 April 24 2012 Chapter 8 Configuration Using iMPACT g XILINX 136 Note The selection box also gives you the option to Enter a Boundary Scan Chain which enables you to manually add devices to create the chain This option enables you to generate an SVF XSVF programming file and is discussed in a later section in this chapter Automatically detecting and initializing the chain should be performed whenever possible 5 Click OK e Welcome to iMPACT Please select an action from the list below Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain v Prepare a PROM File Prepare a System ACE File Prepare a Boundary Scan File Cancel Figure 8 2 Selecting Automatic Boundary Scan Using iMPACT Wizard iMPACT will pass data through the devices and automatically identify the size and composition of the Boundary Scan c
145. ocii 133 Download Cable Support cerises ARR ER REERECEERR EE RE KE aha 133 Configuration Mode Support eese 133 Getting Statted iso sioe Food erre RA a p edes Pace qaa id adipe dps 134 Using Boundary Scan Configuration Mode Luuuuuuuuusueuusue 135 Troubleshooting Boundary Scan Configuration 05 142 Creating an SVF PH i ieibetbodus i eti Eee HE e ee eH da ita 143 Appendix A Additional Resources Xilinx Resources contests RU RR M Len mE IE Esp 149 ISE Design Suite Documentation ssessseseee eee 149 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Chapter 1 Introduction About the In Depth Tutorial This tutorial gives a description of the features and additions to the Xilinx ISE Design Suite The primary focus of this tutorial is to show the relationship among the design entry tools Xilinx and third party tools and the design implementation tools This guide is a learning tool for designers who are unfamiliar with the features of the ISE Design Suite or those wanting to refresh their skills and knowledge You may choose to follow one of the three tutorial flows available in this document For information about the tutorial flows see Tutorial Flows Tutorial Contents This guide covers the following topics ISE In Depth Tutorial UG695 v14 1 April 24 2012 Chapter 2 Overview of the ISE Design Suite introduces you to the pr
146. om the Simulation Objects window to the Waveform window 4 Select the following signals e RST IN e CLKFX OUT e CLK0O OUT e LOCK Lj D OUT Note To select multiple signals press the Ctrl key ISE In Depth Tutorial www xilinx com 87 UG695 v14 1 April 24 2012 Chapter 5 Behavioral Simulation Instances and Processes Instance and Process Name 1 stopwatch tb B ut 1j t preset 13 Inst dcmi ij dk divider ij led cntrl inst ij mode debounce 1j strtstop_debounce ij lap load debounce 1j timer inst 1 timer state Q 1252 e 72 Q 32 std logic 1164 numeric std textio vital timing vital primitives std logic arith std logic textio std logic unsigned S vcomponents XILINX 5 Drag all the selected signals to the waveform Note Alternatively right click on a selected signal and select Add to Wave Window Design Unit stopwatch tb stopwatch sto timer preset t dcmi behavio clk div 262k led controlled debounce beh debounce beh debounce beh time cnt time statmach beh stopwatch sto stopwatch tb stopwatch tb std logic 1164 numeric std textio vital timing vital primitives std logic arith D 8 X Objects enmnsx Block Type VHDL Entity VHDL Entity VHDL Entity VHDL Entity VHDL Entity VHDL Entity VHDL Entity VHDL Entity VHDL Entity VHDL Entity VHDL Entity VHDL Process VHDL Process VHDL Process V
147. on the SVF file in the Boundary Scan chain and select Execute XSVF SVF Your device programming is complete and you have successfully completed the ISE In Depth Tutorial UG695 ISE In Depth Tutorial www xilinx com 147 UG695 v14 1 April 24 2012 Chapter 8 Configuration Using iMPACT XILINX 148 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Appendix A Additional Resources Xilinx Resources e Xilinx Design Tools Installation and Licensing Guide UG798 http www xilinx com support documentation sw manuals xilinx14 1 iil pdf e Xilinx Design Tools Release Notes Guide UG631 http www xilinx com support documentation sw manuals xilinx14 1 irn pdf e Product Support and Documentation http www xilinx com support e Xilinx Glossary http www xilinx com company terms htm ISE Design Suite Documentation e Libraries Guides http www xilinx com support documentation dt ise14 1 librariesguides htm e ISE Design Suite Documents http www xilinx com support documentation dt ise14 1 htm Command Line Tools User Guide UG628 http www xilinx com support documentation sw manuals xilinx14 1 devref pdf ISim In Depth Tutorial UG682 http www xilinx com support documentation sw manuals xilinx14 1 ug682 pdf Synthesis and Simulation Design Guide UG626 http www xilinx com support documentation sw manuals xilinx14 1 sim pdf XST User Guide fo
148. on tools Chapter 6 Design Implementation perform timing simulation Chapter 7 Timing Simulation and configure and download to the Spartan 3A XC3S700A demo board see Chapter 8 Configuration Using iMPACT Getting Started The following sections describe the basic requirements for running the tutorial Required Software To perform this tutorial you must have Xilinx ISE Design Suite installed For this design you must install the Spartan 3A device libraries and device files This tutorial assumes that the software is installed in the default location at c xilinx release_number ISE_DS ISE If you installed the software in a different location substitute your installation path in the procedures that follow Note For detailed software installation instructions refer to the Xilinx Design Tools Installation and Licensing Guide UG798 available from the Xilinx website ISE In Depth Tutorial www xilinx com 41 UG695 v14 1 April 24 2012 Chapter 4 Schematic Based Design XILINX Installing the Tutorial Project Files The tutorial project files are provided with the ISE Design Suite Tutorials available from the Xilinx website Download the schematic design files wtut_sc zip The download contains the following directories e wtut sc Contains source files for the schematic tutorial The schematic tutorial project will be created in this directory e wtut scWNtut sc completed Contains the comple
149. operties for simulation Project Navigator allows you to set several ISim properties in addition to the simulation netlist properties To see the behavioral simulation properties and to modify the properties for this tutorial do the following 1 In the Hierarchy pane of the Project Navigator Design panel select the test bench file stopwatch_tb In the Processes pane expand ISim Simulator right click Simulate Behavioral Model and select Process Properties In the Process Properties dialog box set the Property display level to Advanced This global setting enables you to see all available properties Note For a detailed description of each property available in the Process Property dialog box click the Help button Change the Simulation Run Time to 2000 ns Click OK The following figure shows the properties for behavioral simulation Process Properties ISim Properties Switch Name Property Name Use Custom Simulation Command File Custom Simulation Command File incremental Incremental Compilation nodebug Compile For HDL Debugging Use Custom Project File prj Custom Project Filename Run for Specified Time v Simulation Run Time 2000 ns Waveform Database Filename stopwatch_tb_isim_beh wdb m Use Custom Waveform Configuration File Custom Waveform Configuration File Other Compiler Options rangecheck Value Range Check Property display level Ad
150. ors that may occur during Boundary Scan operations Verifying the Cable Connection When an error occurs during a Boundary Scan operation first verify that the cable connection is established and that the software auto detect function is working If a connection is still not established after plugging the cable into the board and into your machine right click in a blank portion of the iMPACT window and select either Cable Auto Connect or Cable Setup Cable Auto Connect will force the software to search every port for a connection Cable Setup enables you to select the cable and the port to which the cable is connected When a connection is found the bottom of the iMPACT window will display the type of cable connected the port attached to the cable and the cable speed as shown in the following figure Configuration Parallel IV SMHz LPT1 Figure 8 10 Cable Connection Successful Note f a cable is connected to the system and the cable autodetection fails refer to Xilinx Answer Record 15742 Verifying the Chain Setup When an error occurs during a Boundary Scan operation verify that the chain is set up correctly and verify that the software can communicate with the devices The easiest way to do this is to initialize the chain To do so right click in the iMPACT window and select Initialize Chain The software will identify the chain if the connections to the board are working If the chain cannot be initialized it is likely
151. ort of your computer and can be used to facilitate Boundary Scan functionality For more information see the Xilinx Parallel Cable IV Data Sheet available from the Xilinx website Platform Cable USB The Platform Cable connects to the USB port of your computer and can be used to facilitate Boundary Scan functionality For more information see the Platform Cable USB Data Sheet available from the Xilinx website Platform Cable USB II The Platform Cable connects to the USB port of your computer and can be used to facilitate Boundary Scan functionality For more information see the Platform Cable USB II Data Sheet available from the Xilinx website Configuration Mode Support iMPACT currently supports the Boundary Scan configuration mode for FPGAs CPLDs PROMs XCFxxS and XCFxxP and third party SPI BPI Flash devices ISE In Depth Tutorial www xilinx com 133 UG695 v14 1 April 24 2012 Getting Started 134 Chapter 8 Configuration Using iMPACT XILINX The following sections outline the requirements to perform this part of the tutorial flow Generating the Configuration Files To follow this chapter you must have the following files for the stopwatch design BIT file A binary file that contains proprietary header information as well as configuration data MCS file An ASCII file that contains PROM configuration information MSK file A binary file that contains the same configuration commands as a BIT file
152. orts To add the I O markers do the following 1 Select Tools gt Create I O Markers 2 Inthe Inputs field of the Create I O Markers dialog box enter q 19 0 10ad up ce clk clr 3 Inthe Outputs box enter hundredths 3 0 tenths 3 0 sec 1sb 3 0 sec msb 3 0 minutes 3 0 amp Create 1 0 Markers Inputs q 19 0 load up ce clk clr Quputs 3 0 tenths 3 0 sec_Isb 3 0 sec_msb 3 0 minutes 3 0 Bidirection p Figure 4 5 Create I O Markers Dialog Box 4 Click OK The eleven I O markers are added to the schematic sheet Note The Create I O Marker function is available only for an empty schematic sheet However I O markers can be added to nets at any time by selecting Add gt I O Marker and selecting the desired net Adding Schematic Components ISE In Depth Tutorial Components from the device and project libraries for the given project are available from the Symbol Browser and the component symbol can be placed on the schematic The available components listed in the Symbol Browser are arranged alphabetically within each library To add schematic components do the following 1 Select Add gt Symbol or click the Add Symbol toolbar button D Figure 4 6 Add Symbol Toolbar Button www xilinx com 49 UG695 v14 1 April 24 2012 Chapter 4 Schematic Based Design XILINX The Symbol Browser appears in the Options panel to the left of the schematic The Symbol Brows
153. ouble click Analyze Timing Floorplan Design PlanAhead The process is shown in the following figure amp CQ Synthesize XST amp PA Implement Design amp EIA Translate w CA Map Q Place amp Route w EQ Generate Post Place amp Route Static Timing a Analyze Timing Floorplan Design PlanAhead 2 View Edit Routed Design FPGA Editor XPower Analyzer Figure 6 23 Analyze Timing Floorplan Design PlanAhead Process www xilinx com 111 Chapter 6 Design Implementation XILINX 3 When the PlanAhead tool opens select one of the timing paths in the Timing Results tab You will be able to view the path graphically in the Device view and also view details of the path and the associated delays in the Properties tab G state_FSM_FFd1 FDRE G state FSM FFd2 FDRE G state_FSM_FFd3 FDRE G state_FSM_FFd4 FDRE G state FSM FFds FDRE G state_FSM_FFd6 FDRE tate_F5M_FFd7 FDRE F B netlist E Physical Constraints Timing Constraints Path Properties 00x ADEE p A P Path 1 Summary Path 1 Constraint TS Inst dcm1 CLKFX BUF PERIOD TIMEGRP Inst Slack 0 487 Requirement 13 461 Delay 12 815 wall E lt a lt gt General Report Instances Options Device x Package x 4 B Type Slade From To TotalDelay Logic Delay Net Stages Source Clock Destination Clock Constrained Paths 5 TS Inst dcm1 CLKFX BUF PERIOD TIMEGRP I
154. perty has already been added to the sf_d 7 0 bus The remaining pin location constraints will be added in Using the Constraints Editor and Assigning I O Locations Using the PlanAhead Tool of Chapter 6 Design Implementation Note To turn off the location constraint without deleting it select the loc attribute and click Edit Traits Select VHDL or Verilog and select Ignore this attribute Completing the Schematic Complete the schematic by wiring the components you have created and placed adding any additional necessary logic and labeling nets appropriately The following steps guide you through the process of completing the schematic You may also want to use the completed schematic shown below to complete the schematic Each of the actions referred ISE In Depth Tutorial www xilinx com 71 UG695 v14 1 April 24 2012 Chapter 4 Schematic Based Design XILINX to in this section has been discussed in detail in earlier sections of the tutorial Please see the earlier sections for detailed instructions i clk div 262k dkin div 262144 Sg se LOCKED_OUT CLKFX OUT CLKIN IBUFG OUT Cae CLKIN_IN CLKO_OUT statmach a dk dien eu debounce medom ek er ap loa M 5s in SQ out tap lead oo dk mode in i res
155. place of ISim e ModelSim SE PE DE 10 1a or above VHDL or Verilog This tutorial supports both VHDL and Verilog designs and applies to both designs simultaneously noting differences where applicable You will need to decide which HDL language you would like to work through for the tutorial and download the appropriate files for that language XST can synthesize a mixed language design However this tutorial does not cover the mixed language feature Installing the Tutorial Project Files The tutorial project files are provided with the ISE Design Suite Tutorials available from the Xilinx website Download either the VHDL or the Verilog design flow project files After you have downloaded the tutorial project files from the web unzip the tutorial projects into the c xilinx_tutorial directory replacing any existing files in that directory When you unzip the tutorial project files into c xilinx_tutorial1 the directory wtut_vhd fora VHDL design flow or wtut_ver for a Verilog design flow is created within c xilinx_tutorial and the tutorial files are copied into the newly created directory The following table lists the locations of tutorial source files Table 3 1 Tutorial Directories Directory Description wtut_vhd Incomplete VHDL Source Files wtut_ver Incomplete Verilog Source Files wtut_vhd wtut_vhd_completed Completed VHDL Source Files wtut_ver wtut_ver_completed Completed Verilog Source Files
156. ple sec msb 2 connects to the third bit of sec 3 0 The bus tap figure is for visual purposes only The following section shows additional electrical connections by name association Press Esc to exit the Add Bus Tap mode 8 Compare your time cnt schematic with Figure 4 13 to ensure that all connections are made properly Adding Net Names First add a hanging wire to each of the five inputs of the AND5 component and to the TC pin of each of the counter blocks Next add net names to the wires To add the net names do the following 1 Select Add Net Name or click the Add Net Name toolbar button abc Figure 4 12 Add Net Name Toolbar Button 2 Inthe Add Net Name Options that appear in the Options panel do the following a Inthe Name field enter tc outO b Select Increase the Name The net name tc out0 is now attached to the cursor 3 Click the net attached to the first input of the AND5 component The name is attached to the net The net name appears above the net if the name is placed on any point of the net other than an end point 4 Click on the remaining input nets of the AND5 to add tc out1 tc out2 tc out3 and tc out4 The Schematic Editor increments the net name as each name is placed on a net Note Alternatively name the first net tc out4 and select Decrease the name in the Add Net Names Options and nets are named from the bottom up www xilinx com ISE In Depth Tutorial UG695 v14 1 April
157. pril 24 2012 XILINX Command Line Implementation iMPACT displays the PROM associated with your bitstream file xcf 4s xc3s700a stopweatch bit Figure 6 28 PROM File 14 To close iMPACT select File Exit 15 When prompted to save the project select Yes then name the project file stopwatch impact ipf With the resulting stopwatch bit stopwatchl mcs and a MSK file generated along with the BIT file you are ready for programming your device using iMPACT For more information on programming a device see the iMPACT Help available from the iMPACT application by selecting Help Help Topics This completes the Design Implementation chapter of the tutorial For more information on this design flow and implementation methodologies see the ISE Help available from Project Navigator by selecting Help Help Topics Command Line Implementation The ISE Design Suite allows you to easily view and extract the command line arguments for the various steps of the implementation process This allows you to verify the options being used or to create a command batch file to replicate the design flow At any stage of the design flow you can look at the command line arguments for completed processes by double clicking View Command Line Log File under the Design Utilities process hierarchy in the Processes pane This process opens a file named source name cmd login read only mode To create an editable batch file select
158. pril 24 2012 Chapter 5 Behavioral Simulation XILINX The following figure shows the Structure Instance window for the VHDL flow The graphics and the layout of the Structure Instance window for a schematic or Verilog flow may be different Workspac Instance ix B vpko vital timing vital primitives BM vcomponents I textio stopwatch_tb BM timer state timer inst fi t preset 3 Bf sttstop debounce 6 mode debounce line 228 fi Icd cntrl inst Er lap load debounce dem inst ck divider line 83 line 73 std logic unsigned std logic textio std logic arith llf std logic 1164 Bl standard 4 zt EN Ali Library 3 si ES Figure 5 5 Structure Instance Window VHDL flow 2 Select dem_inst in the Structure Instance window The signals listed in the Signal Object window are updated Click and drag CLKIN_IN from the Signal Object window to the Wave window In the Signal Object window select the following signals e RST_IN e CLKFX OUT e CLK0 OUT LOCKED OUT Note To select multiple signals hold down the Ctrl key 82 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Behavioral Simulation Using ModelSim 5 Right click in the Signal Object window 6 Select Add gt To Wave gt Selected Signals Adding Dividers In ModelSim you can add dividers in the Wave window to make
159. r Virtex 4 Virtex 5 Spartan 3 and Newer CPLD Devices UG627 http www xilinx com support documentation sw manuals xilinx14 1 xst pdf XST User Guide for Virtex 6 Spartan 6 and 7 Series Devices UG687 http www xilinx com support documentation sw manuals xilinx14 1 xst v6s6 pdf ISE In Depth Tutorial www xilinx com 149 UG695 v14 1 April 24 2012 Appendix A Additional Resources XILINX 150 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012
160. rag the following signals from the Signal Object window to the Wave window e RST e CLKFX e CLKO LOCKED Note Multiple signals can be selected by holding down the Ctrl key In place of using the drag and drop method select Add to Wave Selected Signals Adding Dividers ModelSim has the capability to add dividers in the Wave window to make it easier to differentiate the signals To add a divider called DCM Signals do the following 1 roges pr W Right click anywhere in the signal section of the Wave window If necessary undock the window and maximize the window for a larger view of the waveform Select Insert Divider In the Divider Name box enter DCM Signals Click OK Click and drag the newly created divider to above the CLKIN signal Note Stretch the first column in the waveform to see the signals clearly The hierarchy in the signal name can also be turned off by selecting Tools Options Wave Preferences In the Display Signal Path box enter 2 and click OK After adding the DCM Signals divider the waveform appears as shown in the following figure stopwatch_tb mode stopwatch_tb reset 4 Ndem insUDCM INST DCM SP CLKIN 4 Ndem inst DCM INST DCM SPVRST 4 Mdem insUDCM INST DCM SPVCLKFX 4 Mem insUDCM INST DCM SPVCLKO 4 Mem ins DCM INST DCM SPVLOCKED Figure 7 5 Resulting Waveform The waveforms have not been drawn for the newly added signals This is because ModelSim did no
161. rce Show constraints from specified file only In Show constraints from all files Save New Constraints To File stopwatch uct vi Constraint Type UCF Constraints E Timing Constraints CRE Domains Validate Constraints Click Validate Constraints button after direct entry of any change Inputs Outputs 5 Exceptions Operating Conditions 8 Group Constraints Miscellaneous Unconstrained Clocks 1 ck 2 ck dividerdiv 2621441 Filter Find bs start ZB Timing i Design File P z Design Summary Translated a Timing Constraints ix Figure 6 3 Constraints Editor in Project Navigator Clock Domains In the Constraints Editor edit the constraints as follows 1 Double click the row containing the clk signal in the Unconstrained Clocks table 2 Inthe Clock Period dialog box verify that Specify Time is selected for the Clock Signal Definition This enables you to define an explicit period for the clock 3 Entera value of 7 0 in the Time field Verify that ns is selected from the Units drop down list Clock signal definition Specify time Time z Units ins Initial clock edge Rising HIGH Falling LOW Rising duty cycle 50 Units Figure 6 4 PERIOD Constraint Values 5 For the Input Jitter section enter a value of 60 in the Time field 6 Verify that ps is selected from the Units drop down list Input jitter en Units ps
162. rd MEM File Schematic System Generator Project amp User Document Verilog Module LW Verilog Test Fixture lig VHDL Module time cnt I VHDL Library P VHDL Package EN VHDL Test Bench C Vxilinx tutoriallwtut sc Qa Embedded Processor File name Location Add to project Figure 4 4 New Source Dialog Box Select Schematic as the source type In the File name field enter time cnt Click Next and click Finish A new schematic called time_cnt sch is created added to the project and opened for editing 5 Change the size of the schematic sheet by doing the following a Right click on the schematic page and select Object Properties b Click on the down arrow next to the sheet size value and select D 34 x 22 c Click OK Note Changing the sheet size cannot be undone with the Edit Undo option Defining the time cnt Schematic You have now created an empty schematic for time cnt The next step is to add the components that make up the time cnt macro You can then reference this macro symbol by placing it on a schematic sheet 48 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry Adding I O Markers I O markers are used to determine the ports on a macro or the top level schematic The name of each pin on the symbol must have a corresponding connector in the underlying schematic Add I O markers to the time_cnt schematic to determine the macro p
163. re the distance between signals To measure the CLKO do the following 1 Select Add Cursor twice to place two cursors on the wave view 2 Clickand drag the first cursor to the rising edge transition on the CLKO signal after the LOCKED signal has gone high www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX ISE In Depth Tutorial Timing Simulation Using ModelSim 3 Click and drag the second cursor to a position just right of the first cursor on the CLKO signal 4 Clickthe Find Next Transition icon twice to move the cursor to the next rising edge on the CLKO signal En Figure 7 9 Find Next Transition Icon Look at the bottom of the waveform to view the distance between the two cursors The measurement should read 20000 ps This converts to 50 Mhz which is the input frequency from the test bench which in turn should be the DCM CLKO output Measure CLKFX using the same steps as above The measurement should read 38462 ps This equals approximately 26 Mhz Saving the Simulation The ModelSim simulator provides the capability of saving the signals list in the Wave window Save the signals list after new signals or stimuli are added and after simulation is rerun The saved signals list can easily be loaded each time the simulation is started To save the signals list do the following 1 Inthe Wave window select File Save Format 2 Inthe Save Format dialog box rename the filename fro
164. rm window e RST e CLKFX e CLKO e CLKIN Note You can select multiple signals by pressing the Ctrl key Viewing Full Signal Names You can view signal names using either the complete hierarchical name or the short name which omits hierarchy information To change the signal name display do the following 1 Right click the desired signal in the waveform window 2 Select Name gt Long or Name gt Short Stretch the first column in the waveform to see the signals clearly The waveform should appear as shown in the following figure Objects epneax Simulation Objects for Inst dcm1 D Ca aaa 5 d Object Name Value lp clk ls lap_load i mode 11110101 psdone psen U 0 0 o rst T 1 uU l dssen_ipd ES jii J gt Fa Default wefg xf Figure 7 13 Resulting Waveform Notice that the waveforms have not been drawn for the newly added signals This is because ISim did not record the data for these signals ISim only records data for the signals that are added to the waveform window while the simulation is running Therefore after new signals are added to the waveform window you must rerun the simulation for the desired amount of time ISE In Depth Tutorial www xilinx com 129 UG695 v14 1 April 24 2012 130 Chapter 7 Timing Simulation XILINX Rerunning Simulation To restart and rerun the simulation do the following 1 Click the Restart Simulation toolbar button
165. roperty display level to Advanced This global setting enables you to see all available properties Change the Simulation Run Time to 2000 ns E Process Properties Simulation Properties EERE PR Switch Name Value Simulation Properties dir Display Properties Property Name Compiled Library Directory language simulator gt Ignore Pre Compiled Library Warning Check Generate Verbose Library Compilation Messages V Use Custom Do File Custom Do File Use Automatic Do File v Custom Compile File List Other VSIM Command Line Options Other VLOG Command Line Options Other VCOM Command Line Options Simulation Run Time 2000ns Defaut 1 ps VHDL Syntax 93 viv Simulation Resolution Default Property display level Advanced v v Display switch names Figure 5 3 Behavioral Simulation Process Properties Click OK Note For a detailed description of each property available in the Process Properties dialog box click the Help button in the dialog box 80 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Behavioral Simulation Using ModelSim Performing Simulation After the process properties have been set you are ready to run ModelSim To start the behavioral simulation double click Simulate Behavioral Model ModelSim creates the work directory compiles the source files loads the design and performs simulation
166. rt Simulation icon Figure 5 7 Restart Simulation Icon www xilinx com 83 UG695 v14 1 April 24 2012 84 Chapter 5 Behavioral Simulation XILINX 2 Inthe Restart dialog box click Restart RA Restart B E3 Keep I List Format M Wave Format v Breakpoints M Logged Signals v Virtual Definitions M Assertions M Cover Directives M TTY Format j Cancel Figure 5 8 Restart Dialog Box 3 Atthe ModelSim command prompt enter zun 2000 ns 4 Press Enter VSIM 5 run 2000 ns Figure 5 9 Entering the Run Command The simulation runs for 2000 ns The waveforms for the DCM are now visible in the Wave window Analyzing the Signals The DCM signals can be analyzed to verify that they work as expected The CLK0 OUT must be 50 MHz and the CLKFX_OUT should be approximately 26 MHz The DCM outputs are valid only after the LOCKED OUT signal is high therefore the DCM signals are analyzed only after the LOCKED OUT signal has gone high ModelSim enables you to add cursors to measure the distance between signals To measure the CLKO OUT do the following 1 Select Add To Wave Cursor twice to add two cursors 2 Click and drag one cursor to the first rising edge transition on the CLKO0 OUT signal after the LOCKED OUT signal has gone high Click and drag the second cursor just to the right of the first Click the Find Next Transition icon twice to move the cursor to the next risin
167. rties for each file can be viewed and modified by right clicking on the file and selecting Source Properties www xilinx com 9 UG695 v14 1 April 24 2012 10 Chapter 2 Overview of the ISE Design Suite XILINX Libraries Panel The Libraries panel enables you to manage HDL libraries and their associated HDL source files You can create view and edit libraries and their associated sources Console Panel The Console provides all standard output from processes run from Project Navigator It displays errors warnings and information messages Errors are signified by a red X next to the message while warnings have a yellow exclamation mark Errors Panel The Errors panel displays only error messages Other console messages are filtered out Warnings Panel The Warnings panel displays only warning messages Other console messages are filtered out Error Navigation to Source You can navigate from a synthesis error or warning message in the Console Errors or Warnings panel to the location of the error in a source HDL file To do so select the error or warning message right click the mouse and select Go to Source from the right click menu The HDL source file opens and the cursor moves to the line with the error Error Navigation to Answer Record You can navigate from an error or warning message in the Console Errors or Warnings panel to relevant Answer Records on the Product Support and Documentation page of th
168. ry FIFOs tH Memory Interface Generators RAMs amp ROMs 4 Block Memory Generator 74 AXI4 Lite Production xilinx com 4 Distributed Memory Generator 6 4 Production xilinx com Distributed Memory Generator Production xilinx com tH Standard Bus Interfaces Search IP Catalog E Clear All IP versions C only IP compatible with chosen part Figure 3 11 New Source Wizard Select IP Page 7 Fill in the Distributed Memory Generator customization GUI with the following settings e Component Name timer preset defines the name of the module e Depth 64 defines the number of values to be stored e Data Width 20 defines the width of the output bus Memory Type ROM ISE In Depth Tutorial www xilinx com 25 UG695 v14 1 April 24 2012 Chapter 3 HDL Based Design XILINX 8 Click Next Distributed Memory Generator View Documents IP Symbol Distributed Memory Generator xilinx com ip dist mem gen 7 1 0 Component Name timer_preset Options Depth 64 Range 16 65536 spo 19 0 Data Width 20 Range 1 1024 e Bu Memory Type ROM O Single Port RAM Dual Port RAM SRL16 based Memory Simple Dual Port RAM Back Page 1 of 3 Next gt Generate Cancel Help Figure 3 12 CORE Generator Tool Distributed Memory Generator Customization GUI Page 1 9 Leave Input and Output options as Non Registered and click Next
169. s that the clk signal does not directly drive any synchronous elements associated with the input pads www xilinx com 107 UG695 v14 1 April 24 2012 Chapter 6 Design Implementation XILINX To review the reports that are generated after the Place and Route process is completed do the following 1 In the Processes pane of the Project Navigator Design panel double click Design Summary Reports In the left pane of the Design Summary Report Viewer select the Place and Route Report in the Detailed Reports section The following figure shows the Place and Route Report in the Design Summary Report Viewer Gi Design Overview z E Summary ss useos 8 108 Properties E Module Level Utilization E Timing Constraints 8 Pinout Report 8 Clock Report S Static Timing 5 Errors and Warnings E Synthesis Messages E Translation Messages E Map Messages E Place and Route Messages E Timing Messages Bitgen Messages E All Current Messages S Detailed Reports E Synthesis Report E Translation Report Constraints file stopwatch pet stopwatch is an NCD version 3 2 device xc3s700a package 9484 speed 4 default Range 0 000 to 85 000 Celsius 1 140 to 1 260 Volts Initializing temperature to 65 000 Celsius Initializing voltage to 1 140 Volts default Range WARNING Timing 3224 The clock clk associated with OFFSET IN 6 ns VALID 6 ns BEFORE COMP clk
170. set times from 0 00 00 to 9 59 99 that can be loaded into the timer time cnt Up down counter module that counts between 0 00 00 to 9 59 99 decimal This macro has five 4 bit outputs which represent the digits of the stopwatch time For this hierarchical design you will examine HDL files correct syntax errors create an HDL macro and add a CORE Generator tool core and a clocking module You will create and use each type of design macro All procedures used in the tutorial can be used later for your own designs Adding Source Files HDL files must be added to the project before they can be synthesized You will add five source files to the project as follows 1 2 Select Project gt Add Source Select the following files vhd files for VHDL design entry or v files for Verilog design entry from the project directory and click Open e clk_div_262k e lcd_control e statmach e stopwatch e time_cnt In the Adding Source Files dialog box verify that the files are associated with All that the associated library is work and click OK The Hierarchy pane in the Design panel displays all of the source files currently added to the project with the associated entity or module names Each source design unit is represented in the Hierarchy pane using the following syntax instance name entity name architecture name file name www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry
171. sign or Chapter 4 Schematic Based Design After you have completed one of these chapters your design includes the required design files and is ready for simulation Test Bench File To simulate the design a test bench file is required to provide stimulus to the design VHDL and Verilog test bench files are available with the tutorial files You may also create your own test bench file Simulation Libraries Xilinx simulation libraries are required when a Xilinx primitive or IP core is instantiated in the design The design in this tutorial requires the use of simulation libraries because it contains instantiations of a digital clock manager DCM anda CORE Generator tool component For information on simulation libraries and how to compile them see the next section Xilinx Simulation Libraries Xilinx Simulation Libraries To simulate designs that contain instantiated Xilinx primitives CORE Generator tool components and other Xilinx IP cores you must use the Xilinx simulation libraries These libraries contain models for each component These models reflect the functions of each component and provide the simulator with the information required to perform simulation For a detailed description of each library see the Synthesis and Simulation Design Guide UG626 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Getting Started Updating the Xilinx Simulation Libraries The Xilinx simulation librari
172. successfully defined you will perform behavioral simulation Chapter 5 Behavioral Simulation run implementation with the Xilinx implementation tools Chapter 6 Design Implementation perform timing simulation Chapter 7 Timing Simulation and configure and download to the Spartan 3A device XC3S700A demo board Chapter 8 Configuration Using iMPACT Getting Started The following sections describe the basic requirements for running the tutorial Required Software To perform this tutorial you must have Xilinx ISE Design Suite installed This tutorial assumes that the software is installed in the default location c xilinx release_number ISE_DS ISE If you installed the software in a different location substitute your installation path in the procedures that follow Note For detailed software installation instructions refer to the Xilinx Design Tools Installation and Licensing Guide UG798 available from the Xilinx website Optional Software Requirements ISE In Depth Tutorial The following third party synthesis tools are incorporated into this tutorial and may be used in place of Xilinx Synthesis Technology XST e Synopsys Synplify Synplify Pro F 2012 03 SP1 or above e Mentor Precision Synthesis 2012a or above www xilinx com 13 UG695 v14 1 April 24 2012 Chapter 3 HDL Based Design XILINX The following third party simulation tool is optional for this tutorial and may be used in
173. t record the data for these signals By default ModelSim only records data for the signals that are added to the Wave window while the simulation is running Therefore after new signals are added to the Wave window you must rerun the simulation for the desired amount of time ISE In Depth Tutorial UG695 v14 1 April 24 2012 www xilinx com 123 124 Chapter 7 Timing Simulation XILINX Rerunning Simulation To restart and rerun the simulation do the following 1 Click the Restart Simulation icon Figure 7 6 Restart Simulation Icon The Restart dialog box opens Ral Restart B x Keep M List Format lV Wave Format v Breakpoints v Logged Signals MV Virtual Definitions M Assertions v Cover Directives M TTY Format i Cancel Figure 7 7 Restart Dialog Box 2 Click Restart 3 At the ModelSim command prompt enter run 2000 ns and hit the Enter key VSIM 5 run 2000 ns Figure 7 8 Entering the Run Command The simulation will run for 2000 ns The waveforms for the DCM should now be visible in the Wave window Analyzing the Signals Now the DCM signals can be analyzed to verify that it works as expected The CLKO must be 50 Mhz and the CLKFX should be approximately 26 Mhz The DCM signals should only be analyzed after the LOCKED signal has gone high Until the LOCKED signal is high the DCM outputs are not valid ModelSim has the capability to add cursors to carefully measu
174. tailed information about using these simulators see the ModelSim documentation available from the ModelSim website or the ISE Simulator ISim In Depth Tutorial UG682 provided with the ISE Design Suite Tutorials available from the Xilinx website ModelSim Setup To use this tutorial you must install ModelSim on your computer ModelSim PE ModelSim SE and ModelSim DE are full versions of ModelSim available for purchase directly from Mentor Graphics To simulate with the ISE Design Suite libraries use ModelSim 10 1a or newer Older versions may work but are not supported For more information about ModelSim PE SE and DE please contact Mentor Graphics ISim Setup ISim is automatically installed and set up with the ISE Design Suite installer on supported operating systems To see a list of operating systems supported by ISim please see the Xilinx Design Tools Release Notes Guide UG631 available from the Xilinx website ISE In Depth Tutorial www xilinx com 75 UG695 v14 1 April 24 2012 Chapter 5 Behavioral Simulation XILINX Getting Started 76 The following sections outline the requirements for performing behavioral simulation in this tutorial Required Files The behavioral simulation flow requires design files a test bench file and Xilinx simulation libraries Design Files VHDL Verilog or Schematic This chapter assumes that you have completed the design entry tutorial in either Chapter 3 HDL Based De
175. tbench File to insert_pp_buffers Insert Buffers to Prevent Pulse Swallowing Other NETGEN Command Line Options tm Rename Top Level Entity to stopwatch ar Rename Top Level Architecture To Structure f tpw Tristate On Configuration Pulse Width lo rpw Reset On Configuration Pulse Width 100 l a Generate Architecture Only No Entity Declaration Output Extended Identifiers tm Rename Top Level Module To ul Include uselib Directive in Verilog File sdf anno Include sdf annotate task in Verilog File sdf path Path Used in sdf annotate task Default ne Do Not Escape Signal and Instance Names in Netlist ism Include SIMPRIM Models in Verilog File insert glbl Automatically Insert glbl Module in the Netlist Property display level Advanced Display switch names Default Figure 7 1 Simulation Model Properties 6 Select the Display Properties category These properties give you control over the ModelSim simulation windows When timing simulation is launched from the ISE Design Suite three windows open by default the Signal window the Structure window and the Wave window For more details on ModelSim simulator windows refer to the ModelSim User Guide 7 Select the Simulation Properties category These properties set the options that ModelSim uses to run the timing simulation For a description of each property click the Help button
176. te called Debounce Circuit Use the appropriate template for the language you are using When the template is selected in the hierarchy the contents display in the right pane amp amp S3 Tel S 53 ucF a Provides a one shot pulse from a non clock input witl 3 VHDL Insert the following between the architecture and X w E Common Constructs begin keywords amp E Device Macro Instantiation signal Oi Q2 Q3 std logic H E Device Primitive Instantiation 4 E Simulation Constructs Insert the following after the begin keyword S amp Synthesis Constructs process lt clock gt w 7 Assertions amp Functions begin w 73 Attributes if lt clock gt event and clock 1 then Coding Examples if lt reset gt 1 then w E Accumulators Qi lt O w Arithmetic Q2 lt 0 w 71 Basic Gates Q3 lt 0 71 Bi directional 1 0 else w E Comparators Ql lt D IN H E Counters Q2 lt Q1 a 71 Decoders Q3 lt Q2 a 71 Encoders end if 73 Flip Flops end if E Logical Shifters jend process a amp Misc 7 Segment Display Hex Conversior Q OUT lt Q1 and Q2 and not Q3 Asynchronous Input Synchronizati Barrel Shifter fa Debounce circuit T Open Drain Output bused reg Open Drain Output single signal amp E Output Clock Forwarding Using DD a E Multiplexers w E RAM x lt lil 3 a gt Design Summary EB time cnt vh
177. ted design files for the schematic tutorial design including schematic HDL and state machine files Note Do not overwrite files under this directory The schematic tutorial files are copied into the directories when you unzip the files This tutorial assumes that the files are unzipped under c xilinx_tutorial but you can unzip the source files into any directory with read write permissions If you unzip the files into a different location substitute your project path in the procedures that follow Starting the ISE Design Suite To launch the ISE Design Suite double click the Project Navigator icon on your desktop or select Start gt All Programs gt Xilinx ISE Design Suite gt Xilinx Design Suite 14 gt ISE Design Tools gt Project Navigator wy amp jg 6193 ie 349 800 Figure 4 1 Project Navigator Desktop Icon Creating a New Project To create a new project using the New Project Wizard do the following 1 From Project Navigator select File gt New Project 2 Inthe Location field browse to c xilinx_tutorial or to the directory in which you installed the project In the Name field enter wtut_sc Select Schematic as the Top Level Source Type and then click Next 5 Select the following values in the New Project Wizard Device Properties page e Product Category All e Family Spartan3A and Spartan3AN e Device XC3S700A e Package FG484 e Speed 4 42 www xilinx com ISE In Depth Tutorial UG695 v14
178. text editor VHDL Simulation To add the tutorial VHDL test bench to the project do the following 1 In Project Navigator select Project gt Add Source 2 Select the test bench file stopwatch tb vhd 3 Click Open 4 Ensure that Simulation is selected for the file association type 5 Click OK Adding Source Files The following allows you to see the status of the source Files being added to the project It also allows you to specify the Design View association and For VHDL sources the library for sources which are successfully added to the project File Name Association Library s mulation v Adding files to project BRRRRRRRRRRRREERRRRRRRERRRRRRI of 1 fies 0 errors Figure 5 1 Adding VHDL Test Bench 78 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Behavioral Simulation Using ModelSim Verilog Simulation To add the tutorial Verilog test fixture to the project do the following 1 In Project Navigator select Project gt Add Source 2 Select the file stopwatch_tb v 3 Click Open 4 Ensure that Simulation is selected for the file association type 5 Click OK Adding Source Files The following allows you to see the status of the source Files being added to the project It also allows you to specify the Design View association and For VHDL sources the library For sources which are successfully added to the project File Name Associat
179. the location in the Site field in the I O Port Properties tab when the I O signal is selected led rw Direction Output Site wis v Package Pin 5 wis Instance lcd rw OBUF Net R ded rw Bank 5 I O Bank 2 Standard Tile E BIOIB x25Y0 Clock Region xivO General Configure Attributes Figure 6 14 Assigning I O Pins Using I O Port Properties 7 Using either the drag and drop or Port Properties method place the following input signals onto the appropriate I O pin locations e LAP_LOAD 116 e RESET U15 e MODE T14 e STRISTOF T15 8 After the pins are locked down select File gt Save Project The changes are saved in the stopwatch ucf file 9 To exit the PlanAhead tool select File gt Exit Mapping the Design Now that the implementation properties and constraints have been defined continue with the implementation of the design as follows 1 In the Hierarchy pane of the Project Navigator Design panel select the stopwatch module 2 Inthe Processes pane expand Implement Design and double click Map If the Translate process is not up to date Project Navigator automatically runs that process as well Note There is a warning from NGDBUILD because the Clock period created for the DCM does not match the newly created clock period for the overall design The design is mapped into CLBs and IOBs Map performs the following functions e
180. to connect the symbols You will connect components in the schematic later in the tutorial Save the schematic www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Design Entry The following figure shows the stopwatch schematic with placed symbols dcm1 RSTIN LOCKED OUT XILINX e ck div 262k cuex our dk 26214k dk 100 QXN sure our I e AKININ axo our e o ck cken a debounce sgn sig out ck debounce rst int dk 26214k time_cnt ok a 1909uncreatns 0 eto a leas manco count2 30 la count3 3 0 aks wc mago count4 30 a x minutes 0 ae elr timer_preset Taie Sop Watch Tutorial Namet Tutoral Date Thu Mar 22 11 15 09 2007 Smet of 1 Icd control ret control od rsJcd mk e Figure 4 26 Placing Design Macros ISE In Depth Tutorial UG695 v14 1 April 24 2012 www xilinx com 67 Chapter 4 Schematic Based Design XILINX Changing Instance Names When a symbol is placed on a schematic sheet it is given a unique instance name beginning with the prefix XLXI_ To help make the hierarchy more readable in the Project Navigator Hierarchy pane change the names of the added symbol instances as follows 1 Right click on the 00011 symbol instance and select Object Properties 2 Inthe Object Properties dialog box change the value of the InstName field to dcm inst and click O
181. ts Show Clock Report Show Failing Constraints Show Warnings e s Show Errors Synthesis Report Current 5 Warnings 5 new 4 Infos 4 new Translation Report Current Tue Mar 30 10 46 29 2010 0 1 Warning 1 new 1 Info 1 new W Map Report Current Tue Mar 30 10 46 41 2010 0 0 5 Infos 5 new Place and Route Report Power Report Post PAR Static Timing Report Bit Re t itgen Reporl Y E Design Summary Mapped x Figure 6 16 Design Summary Report Viewer 2 In the left pane of the Design Summary Report Viewer select a report such as the Translation Report or Map Report in the Detailed Reports section 3 Review the report The Design Summary also provides a summary of the design results and a list of all of the messages Errors Warnings Info generated by the implementation run Using Timing Analysis to Evaluate Block Delays After Mapping After the design is mapped evaluate the Logic Level details in the Post Map Static Timing Report to evaluate the logical paths in the design Evaluation verifies that block delays are reasonable given the design specifications Because the design is not yet placed and routed actual routing delay information is not available The timing report describes the logical block delays and estimated routing delays The net delays provided are based on an optimal distance between blocks also referred to as unplaced floors Estimating Timing Goals with the 50 50 Rule For a preliminary in
182. tstop mode and lap_load input signals Icd control Module controlling the initialization of and output to the LCD display statmach State machine module which controls the state of the stopwatch timer preset CORE Generator tool 64X20 ROM This macro contains 64 preset times from 0 00 00 to 9 59 99 which can be loaded into the timer time cnt Up down counter module which counts between 0 00 00 to 9 59 99 decimal This macro has five 4 bit outputs which represent the digits of the stopwatch time www xilinx com 45 Chapter 4 Schematic Based Design XILINX Design Entry In this hierarchical design you will create various types of macros including schematic based macros HDL based macros and CORE Generator tool macros You will learn the process for creating each of these types of macros and you will connect the macros together to create the completed stopwatch design All procedures used in the tutorial can be used later for your own designs Adding Source Files Source files must be added to the project before the design can be edited synthesized and implemented You will add six source files to the project as follows 1 Select Project gt Add Source 2 Select the following files from the project directory and click Open e cd4rled sch e ch4rled sch e clk div 262k vhd e lcd control vhd e stopwatch sch e statmach vhd 3 Inthe Adding Source Files dialog box verify that the files are associated with A
183. ust be constrained with a OFFSET IN constraint The preferred way to constrain this interface is to use the RISING keyword with the OFFSET IN constraint Figure 6 6 Offset In Constraint Page 1 11 In the External setup time offset in field enter 6 ns 12 In the Data valid duration field enter 6 ns This creates a Global OFFSET IN constraint for the CLK signal Note Timing warnings are generated for the offset in the constraint on the clk signal The reason for these warnings that the clk signal does not directly drive any synchronous elements associated with the input pads ISE In Depth Tutorial www xilinx com 97 UG695 v14 1 April 24 2012 Chapter 6 Design Implementation g XILINX 13 Click Finish Create Setup Time OFFSET IN Clock pad net and period Input clock pad net 0 09 9 L w System Synchronous SDR Rising Input clock period information Clock Name clk Create Edit Clock aS Period 7 ns i Duty Cycle 50 A RISING OFFSET IN RISING VALID Input pad timegroup net Input pad net x idk Rising edge constraints Input Pad Group External setup time offset in e The input Pad Group lists the defined timegroups which contain pad nets 6 e This input Pad Group is used to limit the scope of the rising and Falling Data valid duration constraints to only
184. ut single signal Output Clock Forwarding Using DD w Multiplexers H d RAM vi lt Ail gt lt gt x Design Summary B time cnt vhd B debounce vhd bs Language Templates Figure 3 9 Language Templates Adding a Language Template to a File You will now use the Use in File method for adding templates to your HDL file Refer to Working with Language Templates in the ISE Help for additional options including drag and drop options To add the template to your HDL file do the following 1 Withthe debounce v ordebounce vhd source file active position the cursor under the architecture begin statement in the VHDL file or under the module and pin declarations in the Verilog file 2 Return to the Language Templates window right click on the Debounce Circuit template in the template index and select Use In File E Flip Flops 73 Logical Shifters a 3 Misc 7 Segment Display Hex Conversior Asynchronous Input Synchronizati Barrel Shifter fa Debounce circuit Ir Open Drain Output Open Drain Output amp Output Clock Forw 3 Multiplexers a 19 RAM W ROM w 73 Shift Registers m 73 State Marhines else op ited Q2 lt Q3 lt end if end if nd process OUT lt Q1 and P Use in File Figure 3 10 Selecting Language Template to Use in File 3 Close the Language Templates window ISE In Depth Tutorial UG695 v14 1 April 24 2012 www xilin
185. uues Getting Startede oe EHE RAMIS adeo ted be akti dos Specifying Options c c Leg Roe RO Rn Ra e GRO Ru Cn ATUS Creating Timing Constraints 0 000 cece eee eee ISE In Depth Tutorial www xilinx com UG695 v14 1 April 24 2012 XILINX Translating the Design 2s osos Roe a sps uote eoe Rl de Kao dedi 94 Using the Constraints Editor 2 or red FR RRr ER RRE RE EVER MEIN A d Ia r rnn 95 Assigning I O Locations Using the PlanAhead Tool 100 Mapping the Design iesse regi erebe te RH RH roe PEORES bei doen 103 Using Timing Analysis to Evaluate Block Delays After Mapping 105 Placing and Routing the Design usuusueussessse ees eese 107 Using FPGA Editor to Verify the Place and Route 108 Evaluating Post Layout Timing susseseeeesseee eese 110 Creating Configuration Data ssss ee eios e 9 er a a ra 112 Command Line Implementation usse esee eese 115 Chapter 7 Timing Simulation Overview of Timing Simulation Flow u suus 117 Getting Started or eer CIR CER RRA e 117 Timing Simulation Using ModelSim 0 0 0 cece eee 118 Timing Simulation Using Xilinx ISim ut tuurtuusssssesse 126 Chapter 8 Configuration Using iMPACT Overview or iMPACT oissedodh exa EXE TESEC EXPE erernu ereer rreren 133 D vice SUDDOEE eere ce RCE rt bere p Ete se EXER DERE pa EA yes s
186. v or debounce vhd source file to verify that the Language Template was properly inserted Verilog only Complete the Verilog module by doing the following a Remove the reset logic not used in this design by deleting the three lines beginning with if and ending with else b Change reg name to q in all six locations c Change clock to clk input to sig in and output to sig out Note You can select Edit Find amp Replace to facilitate this The Find fields appear at the bottom of the Text Editor VHDL only Complete the VHDL module by doing the following a Move the line beginning with the word signal so that it is between the architecture and begin keywords b Remove the reset logic not used in this design by deleting the five lines beginning with if lt reset gt and ending with else and delete one of the end if lines IN to sig_in and Q OUT to sig out c Change clock to clk D Note You can select Edit Find amp Replace to facilitate this The Find fields appear at the bottom of the Text Editor Save the file by selecting File Save Select one of the debounce instances in the Hierarchy pane In the Processes pane double click Check Syntax Verify that the syntax check passes successfully Correct any errors as necessary Close the ISE Text Editor www xilinx com 65 66 Chapter 4 Schematic Based Design XILINX Creating Schematic Symbols for HDL Modules N
187. vanced v v Display switch names Default Figure 5 11 Behavioral Simulation Process Properties Performing Simulation After the process properties have been set you are ready to run ISim to simulate the design To start the behavioral simulation double click Simulate Behavioral Model ISim 86 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Behavioral Simulation Using ISim creates the work directory compiles the source files loads the design and performs simulation for the time specified The majority of this design runs at 100 Hz and would take a significant amount of time to simulate The first outputs to transition after RESET is released are SF_D and LCD_E at around 33 ms This is why the counter may seem like it is not working in a short simulation For the purpose of this tutorial only the DCM signals are monitored to verify that they work correctly Adding Signals To view signals during the simulation you must add them to the Waveform window The ISE Design Suite automatically adds all the top level ports to the Waveform window Additional signals are displayed in the Instances and Processes panel The following procedure explains how to add additional signals in the design hierarchy For the purpose of this tutorial add the DCM signals to the waveform To add additional signals in the design hierarchy do the following 1 Inthe Instances and Processes panel expand stopwatc
188. verall Post Map Static Timing Report Prop pl Placer Effort Level Overrides Overall Level None Post Place amp Route Static Timing Re f Simulation Model Properties rl Router Effort Level Overrides Overall Level None xe Extra Effort Highest PAR level only None t Starting Placer Cost Table 1 100 x Ignore User Timing Constraints ntd Timing Mode erformance Evaluation Generate Asynchronous Delay Report Generate Clock Region Report Generate Post Place amp Route Simulation Model Generate Post Place amp Route Power Report power Power Reduction activityfile Power Activity File Other Place amp Route Command Line Options Property display level Advanced Display switch names Default Figure 6 1 Place and Route Properties 7 Click OK to exit the Process Properties dialog box ISE In Depth Tutorial UG695 v14 1 April 24 2012 www xilinx com 93 Chapter 6 Design Implementation XILINX Creating Timing Constraints The User Constraints File UCF is a text file and can be edited directly with a text editor To facilitate editing of this file graphical tools are provided to create and edit constraints The Constraints Editor and PlanAhead tool are graphical tools that enable you to enter timing and I O and placement constraints To launch the Constraints Editor do the following 1 Inthe Hierarchy pane of the Pro
189. x com 23 Chapter 3 HDL Based Design XILINX Open the debounce v or debounce vhd source file to verify that the Language Template was properly inserted Verilog only Complete the Verilog module by doing the following a Remove the reset logic not used in this design by deleting the three lines beginning with if and ending with else b Change lt reg_name gt to qin all six locations c Change clock to clk input to sig in and output to sig out Note You can select Edit Find amp Replace to facilitate this The Find fields appear at the bottom of the Text Editor VHDL only Complete the VHDL module by doing the following a Move the line beginning with the word signal so that it is between the architecture and begin keywords b Remove the reset logic not used in this design by deleting the five lines beginning with if lt reset gt and ending with else and delete one of the end if lines c Change clock to clk D_IN to sig_in and Q_OUT to sig out Note You can select Edit gt Find amp Replace to facilitate this The Find fields appear at the bottom of the Text Editor Save the file by selecting File gt Save Select one of the debounce instances in the Hierarchy pane In the Processes pane double click Check Syntax Verify that the syntax check passes successfully Correct any errors as necessary 10 Close the ISE Text Editor Creating a CORE Generator Tool Module
190. y three paths per timing constraint are shown Selecting one of the three paths allows you to see a breakdown of the path which contains the component and routing delays 106 www xilinx com ISE In Depth Tutorial UG695 v14 1 April 24 2012 XILINX Placing and Routing the Design Notice that the report displays the percentage of logic versus the percentage of routing at the end of each path e g 88 0 logic 12 0 route The unplaced floors listed are estimates indicated by the letter e next to the net delay based on optimal placement of blocks 4 After viewing the report close the Timing Analyzer by selecting File gt Close Note Even if you do not generate a timing report PAR still processes a design based on the relationship between the block delays floors and timing specifications for the design For example if a PERIOD constraint of 8 ns is specified for a path and there are block delays of 7 ns and unplaced floor net delays of 3 ns PAR stops and generates an error message In this example PAR fails because it determines that the total delay 10 ns is greater than the constraint placed on the design 8 ns The Post Map Static Timing Report will list any pre PAR timing violations Placing and Routing the Design ISE In Depth Tutorial After the mapped design is evaluated the design can be placed and routed One of two place and route algorithms is performed during the Place and Route PAR process e Timin
191. you just drew Refer to the completed schematic below To label the reset net do the following 1 Select Add gt Net Name 2 Inthe Add Net Name Options that appear in the Options panel enter reset in the Name box The net name is now attached to the cursor 3 Place the name on the leftmost end of the net as shown in Figure 4 29 Repeat Steps 1 through 3 for the clk lap_load mode and strtstop pins After all of the nets have been labeled add the I O marker 5 Select Add gt I O Marker ISE In Depth Tutorial www xilinx com 69 UG695 v14 1 April 24 2012 Chapter 4 Schematic Based Design 70 XILINX 6 Click and drag a box around the name of the five labeled nets to place an input port on each net as shown in the following figure dk dcm1 RST N LOOXED OUT arx our 26214 CLKIN_SLUFG_OUT QXN IN CiK0 OUT debounce lap load San st ox 1 e a debounce moiset fan moj ox debounce ssop fan sgo jx Figure 4 29 Adding I O Markers to Labeled Nets Assigning Pin Locations Xilinx recommends that you let the automatic Place and Route PAR program define the pinout of your design Pre assigning locations to the pins can sometimes degrade the performance of the Place and Route tools However it may be necessary at some point to lock the pinout of a design so that it can be integrated into a Printed Circuit Board PCB For this tutorial

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