What is a Bus?
Contents
1. c Discuss the iCOMP TM INDEX c Discuss System Buses c Describe a simple Microprocessor System c Describe the System Board amp Peripheral chips c Discuss Microprocessor Buses amp simple bus cycles c Discuss fetching of initial instructions after CPU is reset t C PC Architecture For Technicians Level 1 ins THE iCOMP INDEX Intel Family Comparison Intel iCOMP Index 1386 DX 25 486 5 25 DX2 66 DX4 100 g Pentium 60 Pentium 66 Pentium 90 Pentium 100 0 200 400 600 800 1000 Examples Pentium 510 60 735 90 815 100 PC Architecture For Technicians Level 1 Ge THE iCOMP V INDEX c A NEW WAY TO COMPARE CPU PERFORMANCE c iCOMP Intel COmparative Microprocessor Performance c The iCOMP index is a simple numerical index of relative performance for making straightforward comparisons of Intel CPU power It provides consumers with useful information when they make a PC purchase It is intended to supplement not replace benchmarks c The iCOMP formula was designed to reflect the full capabilities of a CPU those which are executed not only by today s desktop systems and software applications but the software expected to be in use throughout the three to five year average life of a system bought today c It is an index that reflects the relative performance of one Intel microprocessor to another not system performance anf C PC Architecture For Technicians Level 1 ins THE iCOMP T2. he Bee bit Burst Write hack 4 O o O 2 D 2 o o o 2 lt O lt Oo 5 z 2 2 lt O lt 5 a o 2 lt O lt O 5 z 2 O 2 UU O o mi lt 5 2 2 pc Architecture For Technicians Level 1 ASARES PETENS EN PUPPI Ps GENERIC DECODE LOGIC c The system board contains some logic to decode the BUS CYCLE DEFINITIONS of the CPU c The BUS CYCLE DEFINITIONS from the CPU are VALID when ADS is asserted Logic 0 c The drawing shows an example of logic that could be used to decode the BUS CYCLE DEFINITIONS c The signals generated by the GENERIC DECODE LOGIC would be used by the System Board to generate signals such as I O chip selects and DRAM amp PROM output enables C PC Architecture For Technicians Level 1 ins GENERIC DECODE LOGIC WIO p 1 D C 1 4 ADS e g WR Addr 43H PC Architecture For Technicians Level 1 INTA 486 P5 SPECIAL IOR 486 P5 INVALID MEMR MEMW amp pc Microprocessor Single Bus Cycle MEMORY WRITE amp READ WITH WAIT STATES T1 T2 T2 Ti T1 T2 T2 T2 Ti CLK ADS I I WAIT IDLE WAIT WAIT IDLE STATE STATE STATE ST
3. lt SYSTEM UNIT ee SS KEYBOARD ED C PC Architecture For Technicians Level 1 ins oystem Board Overview c The emphasis in this course is an Intel system board c The Intel system board is compatible with the original 8 MHz IBM PC AT c We will use the term PC AT to refer to a generic computer when we are not discussing specific implementations The following items define a PC AT system board containing an Intel 80286 80386 80486 or Pentium microprocessor plus peripheral chips compatible with the original IBM PC AT The used an Intel 8088 e System board adapter card slots ISA compatible with those on the original IBM PC AT e Disk drives providing IBM PC AT compatibility diskette and fixed disks etd C PC Architecture For Technicians Level 1 inside P oystem Board Overview c The following items define a PC AT Cont power supply 5v 5v 12v 12v eA compatible keyboard eA display adapter and monitor The basic types are monochrome CGA and e The system board must contain an IBM PC AT compatible BIOS Examples are AMI Award and Phoenix BIOS Many applications directly access low level hardware and BIOS functions This leads to requirement that the board must contain an IBM PC AT compatible BIOS e n addition to connecting the above components PC AT must be able to run MS DOS or
4. CONTROL C PC Architecture For Technicians Level 1 ins MICROPROCESSOR BUSES c he microprocessor uses several buses to communicate with memory and I O c n general there are three buses e Address e Data e Control C PC Architecture For Technicians Level 1 ins MICROPROCESSOR BUSES c Address bus microprocessor provides an address to the memory amp I O chips e The number of address lines determines the amount of memory supported by the processor eA31 A3 Address bus lines determines where in the 4GB memory space or 64K IO space the CPU is accessing eBE7 BEO outputs Byte enable lines to enable each of the 8 bytes in the 64 bit data path effect a decode of the address lines 2 0 which the Pentium does not generate Which lines go active depends on the address and whether the cycle requires a byte word double word or quad word pc PC Architecture ForTechnicians Level 1 inside P Bus Description FFFFFFFFH Physical Memory PHYSICAL Space MEMORY 00000007H FFFFFFFFH FFFFFFF8H 00000007H 00000000H 7 BE6 BE5 BEA BE3 BE2 BE1 BEO 64 BIT Wide Memory Organization a C PC Architecture For Technicians Level 1 ins Bus Description c Address Space is limited to 64 Kbytes 0000H FFFFH c This limit is imposed by a 16 bit CPU Register 16 bit register can store up to FFFFH 1111 1111 1111 1111 y Not Accessible 0000FFFFH 0000F
5. the VL Bus can only support 2 add in cards at 33MHz and none at 50MHz Memory Slots EISA or ISA Bus O Keyboard Disks Other Elements i C PC Architecture For Technicians Level 1 ins ISA or EISA Expansion Slots Introduction Bus Standards PCI Bus Like the VL Bus PCI will improve graphics performance but will support other components as well network hard drive etc Since it is not directly connected to the CPU it sheds the electrical limitations of the VL bus and will accept multiple PCl bus add in cards Memory fe E PCI Slots Disk Network EISA or ISA Bus etc T ISA or EISA Keyboard DISKS Expansion Slots Other Elements mc PC Architecture For Technicians Level 1 ins Simple Microprocessor oystems Simple Microprocessor Systems KEYBOARD CONSOLE DISK PRINTER DISPLAY C PC Architecture For Technicians Level 1 ins Simple Microprocessor Systems What are the needs of a simple microprocessor system c microprocessor c Memory for program and data storage e RAM Random Access Memory comes in two main types DRAM dynamic RAM needs periodic refreshing STATIC fast expensive needs no refreshing e RAM does not retain the stored code and data when the computer is turned off RAM is used to store the operating system and user programs t C PC Architecture For Technicians Level 1 ins Simple
6. 0 is an indication of the failure elf everything is OK POST gives control to a Bootstrap Loader to load an Operating System via INT 19H c The majority of failures will occur before POST has completed and gives control to a Bootstrap Loader v C PC Architecture For Technicians Level 1 ins SUMMARY WE HAVE DISCUSSED THE FOLLOWING c THE iCOMP TM INDEX c System Buses c Simple Microprocessor Systems c he System Board amp Peripheral chips c Microprocessor Buses amp simple bus cycles c Fetching instructions after CPU is reset t C PC Architecture For Technicians Level 1 ins
7. ATE STATE A31 A3 ADDR ADDR Ee i W R CACHE BRDY D63 DO FROM CPU TO CPU C PC Architecture For Technicians Level 1 ins BRDY D63 D0 Basic Burst Read Cycle CYCLE CYCLE CYCLE CYCLE 1 2 3 4 IDLE STATE IDLE IDLE STATE STATE TO TO TO TO CPU CPU CPU CPU PC Architecture For Technicians Level 1 inside Fetching the Initial Instructions F F F F F 0 31 30 29 2827 26 25 24 2322212019181716 1514131211109 8 76 54 32 1 j U NON VOLATILE MEMORY Flash 27 BIOS FFFFFFFO From OOOFFFFO Mem Code Read Bus Cycle Definition gt _ 1 Shad d Disable ROM Chip Select SHADOW BIOS C PC Architecture For Technicians Level 1 ins ACCESSING THE FLASH BIOS c The Chip Select for the BIOS is the result of decoding the Reset Vector CPU Address at Reset is the Reset Vector Address FFFFFFFO physical physical address is the output on the CPU address bus e The Upper AND GATE will generate a for address FFFFXXXXp c The Mem Code Read bus cycle definition causes the Flash BIOS Output Enable eThe first bus cycle definition is a Code Fetch Memory Code Read t C PC Architecture For Technicians Level 1 ins Fetching the Initial Instructions c The CPU is forced into a known condition at RESET e The address is set to the Reset
8. FFCH 00000000H 00000003H I O Space 45 PC Architecture For Technicians Level 1 P MICROPROCESSOR BUSES Data bus The data bus provides a path for data to flow c The data can flow to from the microprocessor during a memory or I O operation eProvides the propagation path in both directions c D63 DO bi directional The 64 bit data path to or from the processor e The signal W R distinguishes direction c Parity DP7 DPO bi directional Pentium uses EVEN parity bits on a per byte basis eParity signals Output on writes Input on reads lt Not supported on all systems C PC Architecture For Technicians Level 1 ins MICROPROCESSOR BUSES Control bus The control bus is used by the microprocessor to tell the memory and chips what the microprocessor 15 doing Typical control bus signals are these eM IO Z output Defines if the bus cycle is a Memory access or an Port access e D C output Defines if the bus cycle is Data or Code for Memory access eW R output Indicates if bus cycle is a Write or a Read operation eCache output Processor indication of internal cacheability Cache and Ken are used together to determine if a read will be turned into a linefill Burst cycle C PC Architecture For Technicians Level 1 ins MICROPROCESSOR BUSES c CONTROL BUS Cont c ADS output Signals that the processor is beginning a bus cycle eFrom power on th
9. M INDEX The base processor for the index is the 25 MHz Intel486 SX microprocessor which has been assigned a value of 100 All other rated CPUs will have a number that is either above 100 meaning a faster CPU or below meaning slower c The size of the disparity between any two indices provides a relative measure of how much more powerful one CPU is than any other c However to using the analogy of the EPA s highway and city mileage rating the actual performance the user sees in the system depends on the individual car system and driving habits specific types of software of the user as well as on the CPU t C PC Architecture For Technicians Level 1 ins Typical System Buses The following pages describe the numerous bus standards implemented in today s Personal Computers What is a Bus A bus is an electrical conduit in a computer that connects various components so they can communicate with each other A bus standard is a set of rules that govern how the communications will take place think of it as grammar for a computer And different bus standards will have different grammatical rules that affect how quickly they can communicate t C PC Architecture For Technicians Level 1 ins Typical System Buses X Bridges isolate buses electrically and logically X Higher performance functions on PCI bus X Low performance functions on ISA or EISA bus X86 CPU Cache Memory Subsystem
10. Microprocessor Systems What are the needs of a simple microprocessor system Cont c ROM Read only memory available in many main types PROMS cannot reprogrammed but are cheaper EPROMS can be erased and reprogrammed UV EEPROMS can be erased and reprogrammed byte at a time FLASH can be erased and reprogrammed all cells at once e ROM retains the stored code and data when the computer is turned off ROM usually contains the following POST Power On Self Test BIOS Basic Input Output System Low level interface to devices Low level I O drivers and services C PC Architecture For Technicians Level 1 ins simple Microprocessor Systems What are the needs of a simple microprocessor system Cont devices to provide user interaction with the computer Typical I O devices are these ekeyboard edisplay unit efile storage floppy and hard disks e printer emodems C PC Architecture For Technicians Level 1 ins Statistical Comparison PCAT Compatibility Standard 8088 80286 80386 80486 Pentium MEM SIZE 4 GIG 4GIG 4GIG VIRTUAL 64 TERA 64 TERA 64 TERA SIZE REG SIZE CPU SEG REGS On Ohi BUS SPEED MHz 50 60 66 ON CHIP CACHE Protected Mode PC Architecture Technicians Level 1 inside System Board Overview PC AT System Board Overview ADAPTER CARDS POWER SUPPLY DISKS m mm
11. PC Architecture for Technicians Level 1 p C J ins Systems Manufacturing Training amp Employee Development Copyright 1996 Intel Corp PC Architecture For Technicians Level D DRE e PM de P C E S S O R Chapter 1 Introduction PC Architecture for Technicians Level 1 Systems Manufacturing Training and Employee Development Copyright 1996 Intel Corp t C PC Architecture For Technicians Level 1 ins Trademark notice e he following are trademarks of Intel Corporation lt iCOMP R IntelDX4 1386 i486 IntelDX2 Intel386 Intel486 i486 Pentium R 8088 8086 80286 80386 80486 82288 8042 8259 8254 8327 A e he following are trademarks of International Business Machines Corporation IBM PC PS 2 Micro Channel VGA CGA EGA MDA PC DOS and OS 2 e MS DOS R and Windows are trademarks of Microsoft Corporation e UNIXis a registered trademark of UNIX Systems Laboratories e TRISTATE is a trademark of National Semiconductor Corporation e All other product names not listed here but mentioned in this material may be trademarks and or registered trademarks of their respective companies a C PC Architecture For Technicians Level 1 ins Where to get more information c The Indispensable PC Hardware Book Messmer e Addison Wesley ISBN 0 201 87697 3 c ISA System Architecture Shanley am
12. PC DOS applications a C PC Architecture For Technicians Level 1 ins oystem Board Overview c Add on products typically come with software drivers and adapter cards Examples include ePrinters eDiskette and fixed disk controllers and drives eCommunications RS232 LANS GPIB Modems eMice c NOTE IBM has published Technical References for the IBM PC PC XT and PC AT The references include circuit diagrams and BIOS listings and provide the information necessary for the PC industry to produce imitations references were not complete as they didn t adequately define the ISA bus signals vf C PC Architecture For Technicians Level 1 ins THE SYSTEM BOARD IN DETAIL c MICROPROCESSOR eThe original PC AT contained the following chips which formed the heart of the system board lt an Intel 80286 microprocessor 6 then 8 MHz Intel 82284 clock reset and ready chip Intel 82288 bus controller chip socket for the Intel 80287 math coprocessor eCurrent Intel boards have contain a microprocessor and a ChipSet which incorporates the functions of the the Bus amp Memory Controllers as well as most of the peripheral chips a C PC Architecture For Technicians Level 1 ins THE SYSTEM BOARD IN DETAIL c BUSES eOn the original PC AT several buses were created from the local 286 bus Each bus including the 286 local bus has three parts address data control eCurrent Intel
13. PCI Bridge DRAM Subsystem 4 Controller PCI Add in Slots ISA Bus Bridge ISA Add in Slots a C PC Architecture For Technicians Level 1 ins Introduction Bus Standards ISA When the PC was introduced in the early 1980 s the Industry otandard Architecture ISA bus was used As the PC s popularity spread and clones appeared the ISA bus was always used for compatibility It is 16 bits wide at 8MHz and is fully compatible with all PC software An ISA system will accept ISA add in cards It is found in most PCs Keyboard Disks Slots Other Elements ISA Bus Standard System PC Architecture For Technicians Level 1 p Introduction Bus Standards EISA The Enhanced ISA or EISA bus is faster than ISA 32 bits 8MHz and is fully compatible with ISA and all PC software An EISA bus will give better overall performance to a computer system and will accept ISA amp EISA cards It is typically used in servers workstations and high end PCs EISA Keyboard Disks Slots Other Elements EISA Bus Improved overall performance t C PC Architecture For Technicians Level 1 ins Introduction Bus Standards VL VESA Local Bus 1992 the VL Local Bus began to appear and was mainly used to increase the graphics performance It is used in conjunction with an ISA bus Since the VL Bus is attached directly to the CPU both must run at the same speed For electrical reasons
14. Vector FFFFFFFO physical internal registers generate this address eThe first bus cycle definition is a Code Fetch c The CPU will FETCH the first instructions from the BIOS eT he ROM BIOS is chip selected as a result of the Reset Vector address FFFFFFFO e The Flash BIOS output enable results from the Mem Code Head bus cycle definition e The ROM data is accepted by the CPU when BRDY is asserted t C PC Architecture For Technicians Level 1 ins Fetching the Initial Instructions c The CPU DECODES the ROM BIOS instructions e The HEX BYTES machine code stored in the BIOS are decoded by the CPU into instructions c The first instruction decoded is a FAR JUMP to 000 5 e The FOOOOp FFFFFp range is the 1 MB COMPATIBLE PC AT address range accessed in REAL MODE e BIOS Chip Select now results from decoding 000FEOS5Bp e The Lower AND GATE will generate for an address the 000FXXXXp range 000F0000p 000FFFFFp c POST will now EXECUTE in the FOOOOp FFFFFp etd C PC Architecture For Technicians Level 1 inside P Fetching the Initial Instructions c The CPU executes the Code fetched from the ROM and the POST Power On Self Test is executed e POST detects checks amp initializes installed components on the system board e POST writes a CODE to 1 0 Port 80 at the start of each new POST test ePOST normally stops on critical Failures LAST POST CODE written to Port 8
15. boards have buses that contain the three basic parts address data control c SYSTEM BOARD RAM MEMORY eThe system board of the IBM PC AT contained up to 512K bytes of dynamic RAM Adapters could be added to bring the memory to 640K bytes and above eCurrent Intel boards contain upwards of 128M on the system board using SIMM or DIMM modules t C PC Architecture For Technicians Level 1 ins XT AT System Board Peripherals Today s Personal Computers are COMPATIBLE with the PC XT AT cpu 8088 80286 80386 80486 amp Pentium MATH 8087 80287 80387 8253 8254 pit pMA 8237 2 8237s INTERRUPTS 8259 2 8259s pic DIGITAL LOGIC 8255 8042 Micro controller 48 64K 128 REAL TIME CLOCK CHIP W CMOS RAM BATTERY BACKUP CLOCK ntel PC Architecture For Technicians Level 1 inside pc XT AT System Board Peripherals c SYSTEM BOARD PERIPHERAL CHIPS These will be described in detail in this course e An Intel 8254 Programmable Interval Timers PIT e Two Intel 8259A Programmable Interrupt Controller chips PIC e An Intel 8042 8742 MICROCONTROLLER to provide digital I O and to interface with the keyboard e A real time clock chip that provides time and 64 bytes of CMOS RAM for configuration information The clock chip is backed up with a battery e Two Intel 8237 5 DMA Controller chips e 7415612 latch to provide page information during DMA tra
16. e ADS signal should be asserted periodically when bus cycles are running c BRDY input This signal ends the current bus cycle low and is used to extend bus cycles high to allow slow devices extra time elf LOW this signal ends the current bus cycle and the next bus cycle can begin elf HIGH the Pentium is prevented from continuing processing and wait states are added to allow slow devices extra time t C PC Architecture For Technicians Level 1 ins Ready Logic State Machine Example ISA Bus Read Access EPR Microprocessor Bus Cycles c A BUS CYCLE begins with the Processor driving an address and control signals and asserting ADS c A BUS CYCLE ends when the last BRDY is returned to the Processor c A BUS CYCLE may have 1 or 4 data transfers eA SINGLE Cycle transfer is 64 bits maximum 8 bytes eA BURST Cycle transfer is 256 bits 4 64 32 bytes c The following table lists all the bus cycles that will be generated by the Pentium microprocessor e From Table 6 10 in Pentium manual t C PC Architecture For Technicians Level 1 ins Bus Cycle Definition M lO 0 W R Ken Cvcle Description No of Transfers Interruot Acknowledae 1 transfer each cycle 2 locked le 1 1 Read 32 bits or less 1 Code Read 256 bit burst 4 Ter Reserved will not be n a driven bv the Pentium DIO e O Memorv Read 64 bit or less 1 256 bit bursrt 4 ine
17. nsfers e A DRAM Refresh Controller c Remaining system board features not covered in this course e Two 82510 or compatible UARTS providing two COM ports e Circuitry to support a parallel printer port e A speaker for beeping C PC Architecture For Technicians Level 1 ins System Board Component Layout PCI ARBITER PAL T 4 VID override CPU Fan conn LOTS NOISNVdX VSI LOTS NOISNVdX VSI 10715 NOISNVdXd IOd 10715 NOISNVdX IOd O IS NOISNVdXd IOd LOTS NOISNVdX Od gt gt 2 A 2 nN JoMOd PCIIDE Connector PCI IDE Connector Front panel connector e M C PC Architecture For Technicians Level 1 ins REOS E DEFICIUNT INE Microprocessor Buses amp Simple Bus Cycles CPU Signals Required for operation Pentium CPU Address Bus A31 A3 Byte Enables BE7 Pentium up C PC Architecture For Technicians Level 1 ins CPU Signals Required for operation c Power and Ground signals on multiple pins e5 0v for P5 3 3v for P54C c Processor RESET input c Processor CLOCK input Often 50 60 or 66 MHz depending on design c AHOLD input not active Used to disable the address bus for alternate bus master e g DMA cache snooping a C PC Architecture For Technicians Level 1 ins Microprocessor Buses MEMORY MEM RD MEM WR RD lO WR
18. p Anderson eMindshare ISBN 0 201 40996 8 c The Personal Computer from the Inside Out e Addison Wesley ISBN 0 201 62646 2 c The Peter Norton PC Programmer s Bible eMicrosoft Press ISBN 1 55615 555 7 c The Indispensable Pentium Book Messmer e Addison Wesley ISBN 0 201 87727 9 c Pentium Processor System Architecture eMindshare ISBN 1 881609 07 3 t C PC Architecture For Technicians Level 1 ins Where to get more information c Pentium Processor User s Manual e ntel Order Number 241428 c Pentium Architecture amp Programming Manual e ntel Order Number 241430 c PCI Local Bus Specification PCI SIG ePCI Special Interest Group CC Mail PCI SIG c PCI System Architecture Shanley amp Anderson eMindshare ISBN 0 201 40993 3 c PCI Hardware and Software Solari amp Willse eAnnabooks ISBN 0 929392 28 0 t C PC Architecture For Technicians Level 1 ins This chapter provides an overview of concepts which will be covered in more detail throughout the course c The PC based on the Pentium is processor is compatible with entire installed base of applications for MS DOS OS 2 and UNIX c You will learn about PC architecture signals and key bus cycles c The knowledge acquired here will serve a foundation for the boards based on Intel processors t C PC Architecture For Technicians Level 1 ins VDVJEVULIIVES At tne ena or inis section the student will be able to do the following
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