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TS2068 Technical Manual - Unofficial Timex Sinclair 2068 Site

1. 24 ect KEYBOARD 1pk DRIVER SWITCH Lat EER COL COL cs TT 1000pF 78540 E i SWITCHING VOLTAGE i REGULATOR ss PARE H SUP E c R9 z Lad 62K 0 7 3 B Lour y E vee 8 CR24 9 5V DC RR 45 1 5 R14 N4148 sprAken 1 50 E 3 32K 1 10K 680K 51 4 51 he cas 84 aT Se i De p 2002 E 20pF 14 112 R48 R15 R50 YI MHZ TER i 47K 1 2000 srraxene 5 n 2 wan R49 R60 6 50 Aa 100K 10K PIA 33 SOUND R72 pF 22 390K VIT AR sta as R REFERENCE DESIGNATIONS 4 LAST USED USED EA 078 dni R73 winced LAST USED NOT USED 0014F 1 120 L o tury CR26 62K 27 04224 leron MAS 1 3 5 C1 13 26 PIB 28 J4 35 CE 25 027 6 32 27 44 2 S ema CR28 MAS 2 gum C72 c10 4148 G G CR 12 001 6 120 L 0474F 2o et 5 85 gam SL chs aah at 148 a 194 148 55 as R16 10K t ola C60 x V C67 lt 45 kn 12 Tarr 0 als SYNC WHT OPT 2 22uF LEVEL u EE 5 211 2 C54 p PIB 17 J4 3 _ 2 1 PIB 18 J4 30 23 27 PIB 39 J4 28 21 26 nb PIB 20 J4 26 24 22 WREG PIB 21 J4 24 25 19 07 4 14 6 PIB 4 25 3 18 06 10 24 11 meyer oT PIB 23 J4 27 4 1
2. 1BH 1CH 1DH 20H 21H 22H 23H 78 DESCRI PTI ON Reserved Returns Memory Selection Low Active in C for Bank 2 in B Returns Bank in A for Address in HL Reserved Process Keyboard nput See Section 4 1 1 Generates DE 1 Cycles of a Tone having the Period 884236 to 88 246 T States HL N See 4 4 BEEP Comma n d processes parameters on Calculator Stack Exits via PARP See 4 4 COPY Command Dump Primary Display File to Printer See 4 1 3 Char Output to Screen Printer Character Code in See 4 1 2 Set Print Position to value in BC B Line 0 23 C Column No 0 31 Set Attribute Byte for Display File Adrs in HL using ATTR T MASK T and P FLAG Per manent Attribute Info to Temporary Attribute Variables Cl ear Lower Screen Pri mary Display File Cl ear Entire Screen Pri Display File Print Clear Print Buffer See 4 1 3 SERVI CE DESLUG K NEW INIT INCH SELECT NSERT RESET CLOSE CLCHAN OPEN OPCHAN TABLE 3 3 4 2 TS 2068 FUNCTION DISPATCHER SERVI CES SERVICE CODE 37 38 39 40 41 42 43 44 45 46 47 25H 26H 27H 28H 29H 2 AH 2BH 208 208 218 2FH continued 79 DESCRIPTION 3 pytes co rinter Pixel Data Address in HL Number of Scans remaining in B 21 8 See
3. R ATT3 SCRL SCRMBL SEARCH SELECT SEL HL SENDCH 9ENDTV SEPRMT SETCUR SETTVC SET AT SHIFT SIN SKIP SKIPIT SL CER SMINIT SOUND SRCHSC STBOOL STDE S STDE U STKUSN STK_O STK_A STK EC STK_M STOP STRITO STTVCU SUB SUBLIN SUBLN 1 SUMSLD SVNERR SYNTAX TAN TEMG TEMP38 TEMP39 TERM TESTO TIMES TOKENS TO THE TRUNC TVFUL TV COL USRRET WRCH XEV X CALC X T HL 12CA 1354 1ECA 1 FD4 2 R 3768 2065 2454 11 68 0338 0939 2603 1268 1230 1248 11ED 0500 3C39 0914 0914 oSB2 339C 1028 2569 ZE10 11 1 2128 1 374 3926 314c 314A 3059 1C51 ZOES 30E9 3773 1C59 220F 5 33CE 16 ICAT S503 0790 23BB 2 1 3282 0010 3100 134 156 3 EDIT EDIT SYNTaX SYNTaX EXPRN CALC FUNCTS SYNTWO CHANS TOL 10_1 GRAPHS EDIT EDIT EDIT EDIT IG_1 TAPEMSG I_1 10 1 10 1 SUMS FUNCTS SYNTAX SVNTWO I DENT EDIT SYNTAX EDIT CALC NCILIT NOUT SYNTAX NOUT INOUT CALC SYNTAX SVNTWO IQ_1 SUMS LIST LIST SUMS SYNTAX SYNTAX FUNCTS BASIC SYNTAX SYNTaX SYNTAX SYNTAX SYNTaX SYNTWO CALC SUMS BASIC FUNCT SUMS IO 1 SYNTWO K SCAN CALC BASIC INCLIT EDIT EDIT PROGRAM BLOCK 4000 BYTES ENTRY LINK 1 7 LOAD MODULE XBASIC INIT CHNG VID PASSING BS GLOBAL AKEY BLDSCT CALL B CHNG V CLDF IL EXINIT GOTO B LOA
4. EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU TOKO EQU RNDTOK EQU EQU PIt EQU _ EQU PNT TK1 EQU SCRNTKt EQU EQU EQU TOK_FN EQU EQU VALSTK EQU LO MON EQU BIN_TK EQU LINETK EQU THEN EQU TOt EQU STEP EQU EQU MIN_KWs EQU EQU FORMTK EQU EQU DEL_TK EQU OPN_TKs EQU OEH OFH 10H 19H ene 7 7 54 gt 27 7 7 ud Ad 4 SFH 80H 90H TOKENS OASH OASH OA6H OQ7H OAGH OASH OAAH OABH OACH FN_TK OADH OREH OAF H OC4H OCSH OCAH OCBH OCCH OCDH OCEH DEF TK OCFH ODOH OD1H OD2H OD3H QU EQU VFY_TKs EQU EQU ARC TKt EQU EQU EQU QOUT TKt EQU LPR TK EQU EQU STOPTK EQU READTK EQU DATATK EQU RESTTKs EQU NEXTOK EQU DUMPTK EQU BORDPT EQU ODSH OD6H OD7H OD9H 4 5 ODFH OEOH OE 1H OE2H OE 3H OE 4H OE SH OF 3H OFFH OFEH 49 o we 9 dO 9 44 9 e 8 CAPS SHIFT LOCK TOGGLE TOKEN MODE ORAPHICS MODE FOREGROUND BLACK BACKGROUND BLACK STRING QUOTE DOLLAR SIGN PRESTEL CODE FOR 7 1
5. Bit can be thought of as an envelope enable bit i e when 0 the envelope is not used and when M l the envelope is enabled Figure 2 1 6 6 illustrates all combination of the 5 bit Amplitude Control FIGURE 2 1 6 6 AMPLITUDE CONTROL REGISTERS AMPLITUDE CONTROL REGISTER CHANNEL R8 A R9 B RI 0 N PM Amplitude Control NOT USED M 13 1211 output 0 0 0 0 0 0 0 0 0 The amplitude D ou DAY 41020400 is fixed at 1 of 0 v Xu 16 levels as e determined by 0 L3 LO 0 1 1 1 1 1 X X X X E3 E2 El EO The amplitude is variable at 16 X Don t Care levels as deter ned by the output of the Envelope Gen The all zeros code is used to turn a channel off 26 2 1 6 4 conti nued Figure 2 1 6 7 graphically illustrates a selection of variable level envelope controlled amplitude where the 16 levels directly reflect the output of the Envelope Generator A fixed level amplitude would correspond to only one of the levels shown with the level directly determined by the decimal equivalent of Bits 13 10 FIGURE 2 1 6 7 VARIABLE AMPLITUDE CONTROL 5 GRAPHIC REPRESENTATION Of CHANNEL 13 THE DECIMAL VALUES OF THE 3 MAXIMUM 12 AMPLITUDE CONTROL OUTPUT AMPLITUDE CHANNE EP E EP eee od 186 Ve 2 1 6 5 Envelope Generator Control Registers RII R12 R13 To accomplish the generation of fairly complex envelope pa
6. FIGURE 5 1 3 EPROM CARTRIDGE BOARD SOLDER SIDE ARTWORK 115 FIGURE 5 1 4 EPROM CARTRIDGE BOARD SOLDER MASK 4 gt gv 1 SOLDER MASK SK 2000 8 1 116 5 2 Advanced Video Modes The following sections describe the various video modes available on the TS 2068 and the major software supoort functions necessary See Sections 3 2 2 3 and 3 2 2 4 for details on using the Video Mode Change Service Appendix contains descriptions and code listings for a number of software packages developed by Timex that support various screen modes and applications Reference to these packages should aid in gaining an understanding of the software techniques needed to support the video mode hardware The TS 2068 video mode hardware works out of two areas of RAM the primary display file at 4000H and the second display file at 6000H Each area consists of 5912 1B00H bytes used for pixel and or attribute data based on the mode selected via bits 0 5 of Port FFH The pixel data area divides into three blocks each supporting 8 contiguous lines on the screen See Section 2 1 10 for details on organization of the display RAM Because the two display files occupy the same relative positions within their respective 8K Chunks by setting clearing Address Bit 13 a software routine can address the corresponding location in each file Address B it 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 DF 4000 5AFFH Bit 13 0 Address Bit 1
7. p o 4260 12 Stet INC DE 4 EE 13 INC DE amp 2EF 7 67 ANTI A LAG EUSA se GRC HL DE amp 2C 2 ER 549 DE HL 62T 2 DDD J OCCO 70 LO Ix O 4207 001 571 ADD Ix DE 6209 D1 72 POF 620 8 pur gt 573 LD SP IX ezcc 74 CALL SAVE STATUS 62 F cs 57 PLISH BC e2pDo Q FF 76 LD 6202 CEASA 577 CALL G T_ TATLE G amp F F 7 Lf B al 7 7 Ln 420 ANT OF H ODA L c A CD9 64 2 CALL RANK ARE C1 333 POF RC amp 20 2 78 RII LD HL FRAMES INON INCREMENT FRAME COUNTER 62E2 23 SES INC HL amp 2E 227250 5 6 LD FRAMES HL amp 2E A 7 57 LD amp 2 7 see OR L 2ER 2003 339 JR NZ2 LIT3 GZ2EA FD3440 590 INC 1 2 62ET cs 91 LIT3 PUSH BC 6ZEE r 92 PUSH DE amp 2 CDE 102 593 CALL UPD K 2 2 ni 394 POF amp 2F 3 C1 7 POP RC S96 PHLAF1 t JUMP HERE TO POP HL POP ENABLE INTERRLFTS RETURN amp 2FA nfiz 10000 597 LD Ix 0 e2Fe puas Sve ADD SP tora 4 5 CALL RESTORE STATUS e 2FD DLi23 eoo INC IX 62FF Dif 601 LD IX 6301 UDE 1 602 POP IX 6303 E1 403 POP HL 304 F1 604 POF 6305 FER 605 E1 6206 c9 606 RET 607 eoe THERE TO SERVICE NON MASEARLE INTERRUPT 609 tIF NMIADD O THEN RETURNS STRAIGHT AWAY 610 ELSE JUMFS TO NMIADD WITH HL ON TOF AF RETN ADDR ON amp 11 THE STACK 207 FS 612 WMI PUSH AF 6308
8. 13 TABLE 3 3 4 0 SERVICE ROUTINES LABEL SERVICE COOE LOCATI ON DESCRI PTI ON Deci mal H H GET WORD 6316 FADO Returns in HL the word from the address in HL in the bank specified in B PUT WORD 6336 FAFB Wites the word in DE to the address in HL in the bank specified in B GET STATUS 14 6405 FBC5 Returns current memory selection Horizontal Select byte low active in C for the bank specified in B Preserves Bank in B for Home Ext or Dock GET CHUNK 6440 FCOD Returns a single byte mask in A with all bits 0 except the one corresponding to the chunk for the address in HL GET NUMBER 13 645E FCI E Returns in Reg A the bank number currently controlling the address in HL BANK ENABLE 6499 FC59 Enables the me mor y selected Hori zontal Select byte low active in the specified bank Bank in B Mem Sel in GOTO BANK 6572 F032 Transfers control to the specified address after enabling the me mor y selected in the specified bank Parameters passed on stack by pushing target address then Bank Sel ect prior to calling GOTO BANK Return address is discarded CALL BANK 65D0 FD90 Li ke GOTO BANK except saves current hankstatus calls target address and restores status prior to returning to user Two additional parameters are passed on stack prior to doing call to CALL BANK These are PRM OUT 16 bits following by PRM IN 16 bits as described for the Function Dispatc
9. 15 Address Bus Bit 15 Buffered NMI Non Maskable Int Active Low 14 Address Bus Bit 14 Buffered HALT CPU HALT Indicator Active Low A13B Address Bus Bit 13 Buffered MREQB Memory Request Active Low Bfrd 2 Address Bus Bit 12 TORQB I O Request Active Low Bfrd All Mdress Bus Bit 11 RDB Read Active Low Buffered 10 Mdrees Bus Bit 10 WRB Write AcLive Low Buffered A9 Mdress Bus Bit 9 BUSAK Bus Acknowledge Active Low A8 Mdress Bus Bit 8 WAIT CPU WAIT Active Low 7 Mdresa Bus Bit 7 BUSRQ Bus Request Active Low A6 Address Bus Bit 6 RESET CPU Reset Active Low 5 Address Bus Bit 5 1 Ml State Active Low A4 Address Bus Bit 4 RFSHB Refresh Active Low Buffered DZOUT Daisy Out Not Connected EXROM Extension ROM Enable Active Low H Color Signal Red ROSCS ROS Chip Select Active Low Dock Bank Enable Color Signal Green BE Bank Enable Active Low B Color Signal Blue IOA5 BUSISO SOUND Analog Sound Signal Output 0 5V VIDEO Composite Video Signal Output GND Signal Ground GND Signal Ground NOTE All A Pins are on component side of board All B Pins are on non component soldering side of board 55 TABLE 2 4 1 2 PI SIGNAL ELECTRICAL CHARACTERISTICS s ss OUTPUTS FROM TS2068 INPUTS TO TS2068 CAPACITIVE NPUT LOADI NG V OL LOAD V 0H VIL V 1H IN CAPACITIVE MAX MAX MAX MIN MAX MIN LOADI NG MNE MONI C
10. D 1 ON HOME GN_EXIT NO EXP BANKS I SEARCH ALL EXP BANKS FOUND THE CHUNK SO EXIT LOOP NOT IN EXP BANKS SO CHECK DOCK TIF CHUNK gt 1 THEM CAN T BE IN EXT CHECK IF EXT NOT IN EXT TIN EXT BANK 50 RETURN 244 TIN HOME BANK 50 RETURN 255 GN EXTT GN EXIT A B DE BC TFOUND CHUNK DOCK SO RETURN RETURN EXP BANK NUMBER RESTORE REGS HORIZONTAL SELECT C FRSA x t SAVE REGISTERS amp 4 2E 4A1 83452 4A4 6442 4 448 4 4AE 4BO 4461 4B2 LARS 4 884 6487 AMES LARA 4 FC 4BE amp 4 2 55404 AALT ALALA 4068 4ACF 440 44012 2 3 04 485 40 4 05 AACA ALE EARE EET AEA 4E 44C aE E 4EF AGF U AFT KAF 3 SAF LAF 64FC LAFE ro amp s02 14 amp CM 4 17 509 AME eto 5 12 6514 4 1 eA D ASID 361563 A7 311 1580 1 Eoo 63 1640 Fe 7 F SF F1 Cp ce3 CF4 LIU DEFF DEF 4 Ceo 4 FEFF 2E lt CME 4 5 1440 7 2F 3 1 C1 F1 g r 1 DAFF 7 Oz UEF a D07700 pr23 341743 47 2600 47 a CORAS 920 921 922 23 924 22 9 24 927 92 930 931 932 924 735
11. REGISTERS SET UP FOR ROUTINE ADDRESS TO HL CALL CHGVID WITH DESIRED VIDEO MODE IN A ADDRESS TO HL SAVE VIDEO MODE COMPENSATE FOR BUG IN CHNG VID RTN WHICH SETS VI DMOD 0 INSTEAD OF 80 WHEN BOTH DISPLAY FILES ARE OPEN TEST VIDEO MODE TEST IF 80 SET VI DMOD 80H GET PREV HOR SEL RESTORE READ PORT FF TURN OFF RCM SEL SAVE SEL PORT MASK INTERRUPTIONS PRESERVE REG A EXT ROM SELECT BIT SEL EXT ROM HORI ZONTAL SELECT FCR DOCK EXT SAVE SELECT CHUNK 0 IN EXT ROM RESTORE REG A EXECUTE TARGET RETURN TO CALLER CF ROUTINE AND FRTN 3 9 RAM Organization and Services 3 3 1 System Variables RAM beginning at 23552 5C00H is dedicated to the BASIC System Variables as defined in Appendix D of the TS 2068 User Manual and in Appendix B of this document The area from the end of the defined variables STRMNM 23755 5 to 24297 5EE9H is reserved for expansion of the System Variables but is not used by the Operating System in the current TS 2068 3 3 2 System Configuration Table The area from 24298 5EEAH to 24575 5FFFH is reserved for the System Configuration Table SYSCON This table is built at system initialization time and is comprised of an 8 byte entry for AROS a 4 byte entry for LROS followed by eleven 24 byte entries for proposed expansion banks and an End of Table marker In the original TS 2068 the actual usage of this table is limi
12. VOLTS MA VOLTS VOLTS VOLTS uA MAX PF A158 30 0 5 1 9 2 4 0 8 2 0 1800 10 148 30 0 5 1 8 2 4 0 8 2 0 1800 40 A13B 0 5 1 8 2 4 0 8 2 0 1800 40 A12 30 0 4 1 8 2 4 0 8 2 0 1800 14 30 0 4 1 8 24 0 8 2 0 1800 74 A10 30 0 4 1 8 24 0 8 2 0 1800 14 A9 30 0 4 1 8 2 4 0 8 2 0 1800 76 A8 30 0 4 1 8 2 4 0 8 2 0 1800 16 30 0 4 1 8 2 4 0 8 2 0 1800 12 A6 30 0 4 1 8 2 4 0 8 2 0 1800 72 A5 30 0 4 1 8 2 4 0 8 2 0 1800 12 M 30 0 5 1 8 2 4 0 8 2 0 1800 12 A3 0 4 1 8 2 4 0 8 2 0 1800 12 A2 30 0 4 1 8 2 4 0 8 2 0 1800 72 Al 30 0 4 1 8 2 4 0 8 2 0 1800 12 A0 30 0 4 1 8 2 4 0 8 2 0 1800 98 30 0 5 0 35 2 1 0 8 2 0 120 30 0 5 12 2 4 0 8 2 0 20 10 WRB 30 0 5 12 2 4 0 8 2 0 20 10 RFSHB 30 0 5 12 2 4 0 8 2 0 20 10 EXROM 30 0 5 12 2 4 S ROSCS 0 5 12 2 4 EN MREQB 30 0 5 12 2 4 0 8 2 0 20 10 RDB 30 0 5 12 2 4 0 8 2 0 20 10 MI 30 0 4 1 8 2 4 0 8 2 0 20 10 BE 0 8 2 0 10 12 BUSAK 30 0 4 1 8 2 4 Een WAIT 2 REN n 0 8 2 0 10 HALT 30 0 4 1 8 2 4 0 8 2 0 10 NMI 0 8 2 0 10 E sn OPEN COLLECTOR With PULL UP wa RT ERES ERE E sss R 50 0 4 1 8 2 4 C 50 0 4 1 9 2 4 ds RN B 50 0 4 1 8 2 4 nm VIDEO 0 40 75 ohm COAX ee LL L LLL L L L LL L L L ee DO 30 0 4 1 8 2 4 0 8 2 0 20 120 DI 30 mas 1 8 2 4 D2 30 0 4 1 8 2 4 03 30 1 8 2 4 0 8 2 0 120 04 30 4 1 D5 30 LILI 14 14 2 0 Q1 06 30 0
13. 041 OZE 0301 0437 O1CE 0053 0300 MODULE FUNGTS SUMS I DENT I DENT FUNGTS AROS GALG ARNS ARNS FUNCTS FUNGTS 17 1 KSCAN SYNTWO SYNTAX SYNTWO KSCAN EDIT SYNTAX GRAPHS CHANS SYNTAX EDIT IO 1 CHANS 10 2 SYNTAX TOU 19 1 SYNTWO SYNTWO SYNTAX FUNCTS LIST CALC 136 LEL T YM DEL DE DEL C DESLUG DE HL DIGIT DIM DIVIDE DRAW DRAWLN CORAWL DUMPPR DYADIC ECHO EDIT K END ENDSTT ENDTEM ERASE ERR2 ERR4 ERRS ERR6 ERRB ERRH ERR E x CUTE EXP EXPRN FIND L FIND_N FIX_U FI X_ily FLOAT FOR FORMAT FP2A FPZRC F ATTR F INKY F PI F FNT F ZCRN GETAL GET LN GET XY GU se HIFLZH NGH ININT INIT INPUT INST INSA INSERT INT INTOIV 1 22 1 1750 1740 0000 1563 op ZFCO SSAE 2913 2310 OAZ3 1 BDC OAS 1844 154A zaps 1891 1 FC F 07171 BSAC 1F29 227 1230 1 ALIS ZARF z s4 1604 2670 1F23 1F1E 1 60D 3654 1C 3 25CC 3193 2160 23D7 OF 2ES 2624 222E 17CF 2D 54 1224 2440 FY 238C 2410 11 1 OF 00 31 2228 1289 7 12BB ZARB SYNTAX SYNTAX LIST 10 2 LIST 10 2 10 2 LIST I NOUT I DENT SUMS GRAPHS GRAPHS GRAPHS 1022 SYNTAX 15 2 10 2 SYNTWO SYNTAX SYNTAX I5_1 SIMS SYNTAX SYNTWO EDIT SYNTAX FUNCTS EXPRN LIST DENT SYNTAX SY
14. Full explanation of the following Calculator Routines is beyond the scope of this document SUB 113 71H Subtract floating point format numbers HL minus DE DFE assumed to be HL 5 87 TABLE 3 3 3 2 TS 2068 FUNCTION DISPATCHER SERVICES continued SERVI CE SERVICE CODE DESCRIPTION ADD 114 72H Add HL DE See SUB MULT 115 73H Integer multiply HL DE Returns C if overflow TIMES 116 74H Floating Point Multiply HL DE DIVIDE 117 75H Floating Point Divide HL DE TRUNC 118 76H Truncates a floating point number HL towards zero to an integer Assumes DE HL 5 FLOAT 119 77H Converts number HL to floating point format Assumes HL points to an integer in 5 byte format INTDIV 120 78H Repl aces top two numbers on Calculator Stack X and Y by X Mod Y and the integer quotient INT Returns with DE and Calc Stack Pointers NT 121 79H Replaces the top of the Calculator Stack by its integer part Returns with HL top of Calc Stack and DE next free space EXP 122 Replaces the top of the Calculator Stack X by EXP X Returns with DE and HL Calc Stack Pointers LN 123 Replaces the top of the Calculator Stack by its natrual logarithm Returns DE and HL Calc Stack Pointers ANGLE 124 Replaces the top of the Calculator Stack X by Y where Y is greater than or equal to 1 and less than or equal to and the SIN
15. Interruption Handler with your own code if you will be using the Video Mode service Your branch instruction at 62 however will be copied unmodified to location FA6EH in Chunk 7 and vice versa Note that this technique cannot be used if you are using BASIC since then you must have Chunk 0 enabled in the Home Bank Italso cannot be used from a cartridge because the memory selection hardware Port OF4H is common to the Dock and Extension ROM Banks and can only enable one of them at a given time as selected by Bit 7 of Port OFFH AROS Variables Inorder to use pre defined arrays and or other BASIC variables store them in the cartridge possibly in the lower half of the addressable space which is not usable for BASIC program and branch to a machine code routine via the USR function at the beginning of your BASIC AROS program Use this routine to do the necessary memory selection and copy your data fromthe cartridge to the RAM address in VARS Adjust the System Variables E LINE WORKSP STKBOT and STKEND to all point to the first free memory following your BASIC variables Of course all BASIC variables must conform to the format expected by the BASIC Interpreter In addition to BASIC structures you can also store screen images and machine code variables in the cartridge for transfer to the RAM under your control Consider using the XFER_ BYTES service in the 05 RAM 125 6 0 Known BUGS and Corrections This section desc
16. 1 EF F 1 DUTECH DOF 17401 DOLGE OL 0066 7 7 CIC e 1 SF e 1 CORC ez EF DUE Dish t Fo AF DL 160000 DD 2 C4442 gt 1322 1323 1 24 132 132 GQ gt VOS tar deg D our Oy 44S ur t 94 bad MOR aN C 0 076 er ca gt Q as s p pb 4 w ap OP sv ss a wa a tet fi a 9 3400 1401 1402 140 1404 1405 140 1407 1405 14019 1410 1411 1412 1413 1414 141 1416 1417 1418 1419 1420 1421 1422 X8 DIFF_ BAMKS XB DO MOVE XB REVERSE XB OVERLAP XE XE_LAST MOVE XELEXIT LD LD CALL LD LD CALL LD LD LD LD LD LD LD RLCA RRCA UDIR R LDLR AR LD PUSH CALL LD ANU SEC LD ant ALM NC ANLE SBC LE UEC Ex 1NC LD LD LD LD LD AND Shc A lt CALL ADD CALL Lo Lit LD ADU CALL 148 C A B O HL Q HL SP HL BC HL HL SP MAX_BANF 2 HL Ix 1 POINTS TO LOCATION SAVE SF IX SAVE _ STATIS ix 1X POINTS TO FARM H Q T Ye RI CREATE_BITMAP SRC BITMAP AF SAVE ON STACK TEMPORARILY L IX DEST ADOR H CI
17. 256 EP 10 10 10 10 Where fE Desired envelope frequency fCLOCK Input clock frequency EP Decimal equivalent of the Envelope 10 Period bits EPI5 EPO CT Deci mal equivalent of the Coarse 10 Tune register bits B7 BO EP15 EP8 FT Decimal equivalent of the Fine 10 Tune register bits 87 80 7 From the above equation it can be seen that the envelope frequency can range from a low of fCL0CK 16 766 960 wherein EP 65 535 10 10 10 to a high of fCLOCK 256 wherein EP l Using 1 76475 MHz clock 10 10 for example would produce a range of envelope frequencies from 0 105 Hz to 6893 6 Hz 28 To calculate the values for the contents of the Envelope Period Coarse and Fine Tune registers given the input clock and the desired envelope frequencies we rearrange the above equations yielding a EP fCLOCK b CT FT EP 10 256 10 10 10 Exampl e fE 0 5 Hz fCLOCK 1 76475 MHz 6 EP 1 76475 x 10 13787 10 256 0 5 Substituting this result into equation hb CT FT 13787 53 219 10 1 0 25 6 256 256 CT 53 00110101 87 80 10 219 11011011 7 0 10 2 1 6 5 2 Envelope Shape Cycle Control Register R13 The Envelope Generator further counts down the envelope frequency by 16 producing 16 state per cycle envelope pattern as defined by its 4 bit counter output E3 EO The particular shape and cycle pattern of any desired envelope is accomplished by controlli
18. 4290 HELLEN ECU HS 431 ENA EOU 20H 43 HZL BNA 433 ARN EQU COACH 434 HSF AEN H REG ADDR 4 5 sTALL RBN 426 CMD ECA QC OH 437 STA 6 EQU CAD 438 LOWNYB EQU tRESET NYBBLE STEERING LOGIC CMD 437 FREE_BYTES EQU 32 440 PRM OUT EQU a 441 HOR SEL EGU 19 442 BANK EQU 11 443 PDO EQU OZE1H 444 44 446 447 GLOBAL DISPATCH INT NMI FUT WORD GET WORD 445 GLOBAL WRITE BS REG READ BS REO GET_STATLIS GET NUMBER 449 GLOBAL GET CHUNK BANK ENABLE GOTO_ BANK CALL BANK 450 GLOBAL _ BS_MAX_BANK BS_3P 471 GLOBAL CREATE BITMAP MOVE BYTES 452 23 f DISPATCH SVC CODEt PASSED ON STACK 4 4 4 3 SVC CODE 15 16 BIT QUANTITY 15 IS USED AS A JUMP FLAG IF 4 amp SET THE DISFATCHER WILL 00 GOTO BANK TO THE SPECIFIED ROUTINE 457 t OTHERWISE IT WILL DO A CALL BANK 459 1 4 9 1 4 0 461 MFTRL EQU 1FFFH 4 2 LASTLEXT SVC EQU 13 4423 LAST RAM sVcC ECU 2 464 T 4 01 4 4 t 6200 447 ARG 4 2004 445 200 DU210000 42 DISPATCH LU Ix o 6204 7035 470 IX 5F f AZO CT 471 PUTH F DRELERVE WORT CN THE STALK F 472 Fr TH AF NERS 472 PERH ELM 620 05 474 PUSH 4200 ES 475 HL 620B DO EO2 475 LD E IX 2 520E DD0 5503 477 Lo D 1X3 SVC_CODE amp 211 AF 473 XOR A 6212 CHA 479 SLA E 5214 CB12 430 RL D 2 DG amp 216 17 421 RLA JUMP FLAG 4217 210000 482 LD HL LAST_EXT_sve 621A C
19. EQU EQU EQU EQU EQU EQU EQU PRBUFF L LEN 8 QN KSTATE 8 LAST K 1 REPDEL 1 REPPER 1 DEFADD 2 K_DATA 1 TVDATA 2 3 3 m 1 0 1 2 3 STRMS HIDSTR 16 2 1 gt CHARS 2 FART 1 PIP 1 Y ERR_NR 1 Q N O LAGS 1 Q pb OQ O n v OC TVFLAG 1 ERR SF 2 LISTSP 2 MODE 1 NEWPPC 2 NSPPC 1 PPC 2 SUBPPC 1 BORDCR 1 E_PPC 2 VARS 2 DEST 2 CHANS_ 2 CURCHL 2 105 NXTLINz EQU PROG 2 ws 4 de we 90 s 4 o we lt we 49 d 49 ve SEE KB DOCUMENTATION BYTE IS A CHAR KEY PRESSED IS TIME TILL COUNTS AS RELEASED IS TIME FRAMES TILL REPEAT 4TH IS CODE WHEN REPEATS STH 8TH ARE A SECOND SET OF 1ST FOUR NEWLY PRESSED KEY DELAY BEFORE 1ST REPEAT INITIALIZED TO 35 DELAY BEFORE SUBSEQUENT REPEATS INITIALIZED TO 5 2 CHAR AFTER IN FORMAL PARAMETER LIST MUST BE O WHEN NO USER DEFINED FN BEING EVALUATED DATA BYTE IN COMPOSITE CHAR FROM KEYBOARD USED FOR STORING BYTES IN COMPOSITE CHARACTERS TVDATA KEY BYTE 1 1ST DATA BYTE FOR OR TAB STREAM DATA POINTERS OFFSETS FROM CHANS 1 TO CHANNELS O STREAM NOT OPEN NO STREAMS HIDDEN FROM USER THESE ARE TIED UNALTERABLY TO SPECIFIC CHANNELS KEYBOARD TV UPPER HALF OF SCREEN INSERTION IN RAM STREAM FOR COMMANDS STREAM FOR INPUT
20. Processes parameter on Calculator Stack to BC then waits BC frames or until key is depressed Uses HALT instructiion SO interruptions must be enabled Reads BREAK key Returns NC if it is pressed and ON ERROR is not active Define Function LPRINT Selects Channel 3 and processes tems n LPRI NT statement for output via WRCH PRINT Selects Channel 2 and processes t ems in PRI NT Statement for output via WRCH same code used for LPR Code used by K LPR and K PRIN to process output data and controls in BASIC statement address in CH ADD INPUT command Selects Channel 1 and processes 110 for Keyboard Lower Screen using buffer at WORKSP for input TABLE 3 3 3 2 TS 2068 FUNCTION DISPATCHER SERVICES continued SERVI CE SERVICE CODE DESCRI PTI ON SE 03 53H Code used by INPUT to process input items and controls in BASIC statement address in CH ADD NOTKB 84 54H Returns Z if current channel is Keyboard Lower Screen device specificationz K COLOR 85 55H Adjusts system variables ATTR T MASK T and P FLAG for color code in D 0 9 Enter with C set to set Ink or NC set to set Paper Error K if Dis invalid HI FLSH 86 56H Adjusts system variables ATTR T and MASK for Flash Bright code in D 0 1 or 0 else Error K Enter with C for Flash or NC for Bright SCRMBL 87 57H Returns in HL the primary display file address for the pixel with coordinates in BC B Y CzX
21. S430 630 AASE amp amp 3F 4440 4 6 44 54 47 A649 2 5 4 C 4 64 452 4454 6459 AASA 665B 4630 AARE LASF E443 64 66 5 AA 6 Q 64 65 666D COLE amp amp amp F 670 674 6477 4679 667 amp 67E EAEI amp amp amp 2 ect ec ec eene 6 CET eeap 6426 6655F amp amp Uu 64573 6696 6697 64 93 6 69R eet amp amp A1 E42 F9 Dr21060000 0613 pr4coa 004443 4F 3001 E DRO us DDE 1 CU1E6 00210000 039 DD4EOA DOC460R 0924 4 F1 01 CDE 1 1 DDE 1 CORCES FS cs US E DOUZACE4 GD48 OO Chics p4 600 EI DD22CE 5 DI 2100009 06 37 Ug 21 4F 3001 114 0003 Does Ei 704845 LOES EB DD2ACE EEOSE DUD 0 4 2 00 DOs gt DPSSCE 4 ct DUE 1 E1 01 C F1 pnt Cv ES ps Ct 45 DA 4 09 CD7v64 42 4F DOTE OC DOSC 1 0 6 027 1122 1123 1124 112 1126 1127 1128 112 1130 1131 1122 1123 1124 113 1134 1137 1129 117 1140 1141 1142 1143 1144 1145 1145 1147 1142 114 1190 1151 1152 1153 1174 1155 11 1157 1152 1159 1140 1161 1142 1143 1144 1145 1144 1147 1143 11 1170 1171 1172 1173 1174 1175 1174 1177 117 1174 11 0 1161 112 11 amp 3 1164 1123 1164 1127 1186 142 11 0 1191 1195 1192 1194 119 1126 1197 119E 1155 1200 1201 1202 12012 1204 20
22. Signal Definitions 2 4 2 2 4 Signal Electrical Characteristics 2 4 4 Joystick Connector Signal Assignment 3 2 2 Inputs to Video Mode Change Service 3 3 4 1 05 RAM Service Routines 3 3 4 2 Function Dispatcher Services 1 0 INTRODUCTION This manual provides detailed technical information on the Ti mex Sinclair 2068 Personal Color Computer Inconjunction with the TS2068 User Manual it is intended to assist the reader in understanding the architecture hardware and software features programming techniques and 1 0 techniques pertaining to the 752068 1 1 752068 Overview 1 1 1 Hardware Overview Figure 1 1 1 is a block diagram of the TS2068 showing the maj or functional components and their logical connections These components are Control Logic SCLD Standard Cell Logic Device CPU 1804 Microprocessor RA 48K Random Access Memory ROM 24K System Read Only Memory 16K plus 8K Extension System Bus Connector Cartridge Connector Sound Generator Speaker Video Circuits Cassette READ WRITE Joystick Connectors The 752009 Cartridge Connector provides for the plug in of cartridges containing programmed ROMs with up to 64K of addressable memory The full 64K is not normally utilized e g due to need for access to RAM for the machine stack See Section 5 1 for details Figure 1 1 2 shows the standard 752008 memory configuration comprised of the Home Bank the ROM Extension Bank and the Dock Cart
23. active and when INT is active at the rising edge of the last clock of any instruction a maskable interruption occurs during the subsequent MI cycle as illustrated in Figure 2 1 3 5 FIGURE 2 1 3 5 NTERRUPT REQUEST ACKNOWLEDGE CYCLE A15 MREO DATA BUS WAIT Last M Cycle of instruction Last T State In Interruption Mode 0 the interrupting 1 0 device places any instruction on the data bus during the TORQ activation and the CPU executes that instruction The RESTART instruction is commonly used for this purpose RESET will automatically set Interruption Mode 0 In Interruption Mode 1 the CPU executes a RESTART to Location 0038H This is the mode normally used by the TS 2068 software In Interruption Mode 2 the CPU concatenates the 8 bit argument which must be a E byte boundary address with the 8 bit Register contents to form a 16 bit pointer to a memory table entry containing the 16 bit service routine address first byte in the table 13 Mode O being the low order portion of the address Once the interrupting device supplies the lower portion of the pointer for concatenation the CPU automatically pushes the PC onto the stack obtains the starting address from the table and does a jump to that address 19 clock periods are required to complete this sequence 2 1 3 8 Non Maskable Interruption NM A pulse on the NMI input to the Z80 sets the internal latch which is tested by
24. is undone This is one reason the Video Mode Change Service and some of the bank switching routines such as BANK ENABLE cannot be meaningfully accessed via the Function Dispatcher CALL BANK Does not correctly retrieve the stack entry designating the count of parameters being passed Memory is overwritten in the case where this count is not zero This is corrected by setting Location 6610H 9 POKE 26128 9 You only need to apply the correction once it will be duplicated in Chunk 7 if the code is relocated 130 LOCATION OBJ CODE HEX 6405 6406 6407 6408 640A 6400 640E 6410 6411 6413 6430 6432 6434 6436 6438 643A 643C 643E 6440 6442 6444 6445 6447 6449 644A 6448 644 The asterisks mark the locations modified corresponding POKE s F5 D5 18 2824 FEFF 2837 2821 OEFF DBFF E680 2812 1808 OEFF DBFF E680 2008 DBF4 2 1802 DBF 4 4F F1 C9 FIGURE 6 5 1 GET STATUS CORRECTI ONS SOURCE STATEMENT COMMENTS Input Bank in B Output Bank 2 in B Bank Status if Exp Bank Memory Selection in C Low Active Format GET STATUS PUSH AF Save Regs PUSH DE LD B Get Bank CP OFEH Test if Ext 254 JR 1 65 EXT OFFH Test if Home 255 JR 1 65 HOME AND A Test if Dock 0 JR 1 65 DOCK Code for Expansion Banks not applicable GS EXT ID C OFFH Assume none IN Test if selected AND 80H JR Z 65 XT1 Not active JR
25. supported via Channel 1 0 4 1 1 Keyboard The low level routines supporting keyboard input executed every 60 of a second out of the Interruption Handler Location 56 38H The controlling routine is labelled UPD K This routine calls K SCAN to determine if any key s are currently being depressed controls the debouncing and repeat algorithms calls K BASE to determine the Base Code calls CHCODE to translate the Base Code based on Mode e g 6 E Mode and finally stores the resultant keystroke code in LAST K and sets the flag KEYHI T Figure 4 1 1 1 illustrates the mode control variable and associated flags and Figure 4 1 1 2 contains flowcharts of the keyboard support routines The character input routine associated with Device Spec is labeled INK The entry address is obtained using the pointer in CURCHL when Channel 1 has been Selected and the Character 1 0 Input routines RDCH INCH are executed The IN K routine tests the KEYHIT flag to detect the presence of input from the keyboard When the KEYHIT flagzl the contents of LAST K are returned to the requestor 93 FIGURE 4 1 1 1 TS 2068 MODE CONTROLS System Variable Location Description MODE 23617 5CA1H K or L Mode E Mode G Mode 23611 5C3BH If MODE O then Bit 3 0 for K Mode for L Mode FLAGS2 23658 5C6AH If in L Mode then Bit 3 O CAPS Lock Off CAPS Lock On UPOATE KEYBOARD STATE Calted
26. 0 device The addressed memory or device should use this signal to gate the requested data onto the CPU data bus WR Memory Write Tri state output active low This signal indicates that the CPU data bus holds valid data to be stored in the addressed memory or 1 0 device RI SH Refresh output active low This signal indicates that the lower 7 bits of the Address Bus contain a refresh address for dynamic memories and the current 7 signal should be used to do a refresh read to all dynamic memories A7 is a logic zero and the upper 8 bits of the Address Bus contain the contents of the Register 15 TABLE 2 1 180 CONTROL SIGNALS continued ACRONYM DEFINITION CPU CONTROL HALT Halt State Output active low This signal indicates that the CPU has executed a HALT instruction CPU operations are suspended until a Non Maskable or a Maskable Interruption with the mask enabled occurs While halted the CPU executes NOP s to maintain memory refresh WAIT Wait Input active lou This signal Tndicates to the CPU that the addressed memory or I O device is not ready for data transfer The CPU will continue to enter wait states as long as this signal is active This allows for synchronization of the CPU to external devices of varying speeds TNT Interrupt Request Input active low This signal 1 generated by external devices and is honored at the end of the current instruction if the interrupt is not masked by th
27. 126 Machine Code AROS 126 BASIC AROS 127 Video Mode Change ves 127 0S General RAM Routines 134 APPENDICES Appendix System ROM 05 RAM Module 136 Appendix B System Variables Definition File 150 Appendix Application Development Library 158 64 Column Mode 80 Column Mode 40 Column Mode Dual Screen Mode Sprites ec ec e UGY Appendix D 288 752068 PCB Assembly Drawing 2 TS2068 Parts List 3 TS2068 Schematic Diagram J Appendix E Expansion Buss Comparisons 95 Appendix Modifications for EPROMs 296 LIST OF FIGURES FIGURE NO TITLE TS 2068 Block Diagram Memory Configuration RAM Mapping System Initialization Flowchart a pa gt N L CPU Ti mi ng 0p Code Fetch Ti mi ng Memory Read Mrite Ti mi ng 110 Read Write Timing Interrupt Request Ack Cycle Rework for EPROM PSG Register Block Diagram Tone Period Registers Noise Period Register Mixer Control 1 0 Enable Reg D A Converter Signal Generation Amplitude Control Registers Variable Amplitude Control Envelope Period Registers Envelope Shape Cycle Control Reg Envelope Generator Output Envelope Generator Output Detail Joystick Port Operation Bank Selection Logic Video RAM Address Generation Keyboard Schematic c I lt O C gt F F uoi nr IO NI NJ NJ NJ NJ RY
28. 2 J Use a 27128 16K EPROM for Ul6 8 Use a 2764 8K EPROM for U20 296 Proposed TS2068 Home ROM Corrections MMI fix J050 2301 AH Z 20 7QH DELETE detay timing 9551 2182103 LD 9354 aB DEC BC 8355 73 LD H C 9555 Ba OR B 2357 290FB JR HZ 0354H 9359 F1 POP AF 935A 1862 JR 32 EH Optional turn an message Last character add 80H 1118 Property of Bob 1128 Orrfelt T0 39 b dcm os eh 1138 INT 65536 etc errors 33Fl1 F5 PLUSH AF S3F2 3C INC R 33F3 OR E 3324 D 3S33FS 2 435 JF NZ 35E4H 33F8 C3EF35 AP 35EFH 35E2 181A JR 35FEH 35E4 F1 POP AF 35E5 77 LD HLJ A 35E6 23 INC 35E7 73 LO 35E8 23 INC HL 35E9 72 LD CHLI D 35EA 2B DEC HL 35EB 2B DEC HL 35EC 2B DEC HL 35ED Dl POP CE 35EE C9 RET F1 POP 35FO 2B DEC 35 1 3691 LD HL 1 lH 35F3 23 INC 3SF4 3638 LD HL 1 Sore 3c INC H 35F7 18ED JR 35EsSH 35F9 bla rk s JSF 297 WSR chunk selection 3adF E689 AND 3ani 2818 JR 2 D543 SUB R 40H Jano FHB 33 21 iM 38B7 H Fix tar Oliaer EPROM programar s 85 zuyncuare page 141 34 DB OAC 3 DB a 022020 3B DB 2 DB 92 DB ror EPROM praarammer Ex 3 59 212508 LD MWe BH 85 ADO ALL 37BD SF L D L H 37BE LD HL 37BF 2535 LD 372104 Exx 3 2 C ORF x pn 3753529 3704 Oct
29. 223 224 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 ERR LN1 _ ERR St ERR Tt SYSCON1 _ EQU SYSCON 2 CURCBN EQU MAX BANK 1 EQU EQU EQU EQU ADDITIONAL 2 ERR LN 2 ERR_C 2 ERR S 1 EQU _ 1 1 TO ON ERROR LINE NUMBER FOR A GO TO I STORE LINE NUMBER IN WHICH ERROR OCCURRED _ 8 5 STATEMENT NUMBER IN WHICH ERROR OCCURRED STORE FOR ERROR TYPE AFTER A ON ERR SYSTEM CONFIGURATION TABLE SLARGEST BANK NUMBER ASSIGNED BANK NUMBER OF THE CURRENT CHANNEL MSTBOT EQU CURCBN 1 tADDRESS OF LOCATION ABOVE MACHINE STACK VIDMOD EGU MSTBOT 2 i NOTE UNUSED BYTE AFTER VIDMOD P a ARSBUF s EQU VIDMOD 2 sPOINTER TO AROS BUFFER ARSFLG EQU ARSBUF 2 tAROS FLAG BIT 7 SET INDICATES AROS PRESENT 4 SET INDICATES NXTLIN POINTING TO AROS BIT SET INDICATES DATADD POINTING TO AROS t THESE BITS BECOME IMPORTANT FOR THE INSERT ROUTINE 3 POINTERS POINTING TO AROS SHOULD NOT BE UPDATED IFOR AN INSERTION INTO RAM ADATLN EQU ARSFLG 1 TO THE START OF THE CURRENT DATA LINE f AROS ONLY DTLNLN EQU ADATLN 2 LENGTH OF THE CURRENT DATA LINE AROS ONLY STRMNM EQU DTLNL N 2 CURRENT STREAM NUMBER USED FOR BUS EXPANSION 3 UNIT DEVICES MSTACK EQU 6200H LOCATION ABOVE MACHINE STACK DRIVES EQU 6840H ISTART OF DRIVES A
30. 4 1 3 Remove Number Slugs from Edit Line Buffer Address in HL NEW command See Fig 1 1 4 Initialize DE Maxi mum RAM Address A 0 for Power On 1 FFH for NEW See Fig l l 4 nput Character to A from currently Selected Channel Returns NC if no input Select Channel Stream in See 4 1 Insert BC Bytes before byte whose address is in HL Copies up all from HL to STKEND and updates affected system variables Returns BC 0 DE adrs of last byte of inserted space HLzadrs of byte before first Reset Calculator Stack Sets STKEND STKBOT and MEM ZMEMBOT 5C92H CLOSE Command Channel on Calculator Stack Close Channel BC Value from STRMS Index into CHANS OPEN Command Channel an4 Device Spec on Calculator Stack Open Channel Device Spec on Cal cul ator Stack DEzpoi nter into STRMS based on See 4 1 for more info on OPEN and CLOSE SERVI CE ERASE FORMAT MOVE FLASHA FIND L SUBL IN TABLE 3 3 4 2 TS 2068 FUNCTION DISPATCHER SERVICES SERVICE CODE CM 48 304 CAT Command Not Applicable 49 50 51 52 53 54 36H 31H 32H 33H 34H 35H continued 8 0 DESCRIPTION ERASE Comnand Not Applicable FORMAT Command Not Applicable MOVE Command Not Applicable Flash Char in A to Screen Calls SENDTV assumes Lower Screen selected Used to Flash Cursor Find BASIC Program Line with the number in H
31. 4 2 0 07 30 0 2 NEN REN 014 10 1 OUT 500 0 5 0 04 0 3 0 5 Jos asi nrc m EAR 15 1 6 2 4 1 3 5 0 SOUND 100 0 2 5 0 3 5 0 me m yl amp T ee TE 0 8 2 0 10 M E TUF 220K PULL UP 0A5 M uu s 56 2 4 1 1 Attachment of an RGB Monitor The TS 2068 provides via the P rear edge connector the ability to attach an RGB monitor for excellent picture clarity and resolution The TTL level logic signals appear directly on the rear edge connector of the TS 20698 the necessary synch signals can be derived from the simple synch stripper separator circuit described here The Schematic of Figure 2 4 1 3 shows the required connections and electronics Attachment is via the 64 pin keyed Pl connector Shielding should not normally be required but ferrite beads are recommended on each wire to minimize EM TVI etc Circuit Operation and the base emitter junction of operate as DC restoration circuit with current flowing only when the composite video input signal from connector pin B31 is at the synch level With the charge maintained on Cl Ql conducts only during the synch pulse interval not during the color burst time During this conduction interval the composite synch signal appears in inverted form on the collector of Ql The Q2 stage simply re inverts the signal providing at its co
32. 57 R2 R13 68 R74 R11 33 34 35 36 38 42 62 R41 R29 30 R52 R22 R32 R61 R53 R69 R31 RI 6 40 60 70 R26 27 R44 45 R9 73 R15 49 R43 QTY PER ASSY N3 m3 nO BO RO FO BO qu lA WM 2U 844 COMMENTS TEMP 15020 05 GMV 20 or GMV TEMP Z5U 20 80 TEMP 250 or GMV DESCRIPTION DI DIODE Schottky 821 or equi valent IC UA 78540 NPC Switching Regulator IC SCLD IC LM1889N Video Modulator 74152440 IC TMS4416 15 150NS MOS Dynamic RAM IC UA 78L12 Regulator IC 1115245 74LS157N TM 4416 20 20005 MOS Dynamic RAM IC AY 3 8912 Sound Gen and 1 0 Port 1 23128 Mask ROM 16K X 8 IC CPU Z80A IC 2364 Mask ROM 8K X 8 IC 741500 TRAN PNP D43Cl TRAN PNP 2N2907 TRAN PNP 283904 TRAN PNP 282222 APPENDIX D T 2068 PARTS LIST conti nued COMPONENT DESI GNATI ON 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 R1 Ul u3 u4 u9 15 10 11 012 13 17 18 114 U16 119 120 121 0 03 07 8 4 2 292 QTY PER ASSY 25 COMMENTS APPENDIX D 752008 PARTS LIST continued COMPONENT QTY DESCRI PTI ON DESIGNATION PER ASSY COMMENTS Filter Bifiler 2m Inductor 230 uh L2 Inductor 33uh Axial L3 4 2 Inductor 12uh L6 7 2 Crystal Oscillator 14 112 MHz 1
33. 9v 1 Ov Do Ov 0 0 A De A 10 D A L D A 2 0 IORQGE 3I INT Ov 4 NMI Video SI HALT SI v 1 ioREQ u Sl BUSRO 31 WR RESET o 2 EE 2 v A 10 A 4 ROMCS 4 RFSH BUSAK amp XI A 1 A A 295 SIDE A SIDE B ZX Bl BOTTOM TOP D 9v KAMCS Ov Do Ov D CLK D A 0 A D A b A D lt q As d NT u A rd NMI 2 Au Sd A e 4 MREO A i Ao RD A WR A MH BUSAK A A WAIT j BUSRO A 4 RESET MI ROMCS 4 RFSH APPENDIX E August 1985 Bob Orrfelt TS2068 MODIFICATIONS FOR EPROMS There are a number of errors in the TS2068 Home ROM and the Extension ROM The errors can be corrected by using EPROMs The following modifications are necessary U20 Extension ROM 27 2 2 x Home cut 26 3 27 2 ROM Face Non comnonent side of the pch O Remove ROMs 1 Cut the trace between 020 26 and 020 27 2 Jumper pins 1 to 28 to 27 on each socket Sus Y 7 U 6 pr 2 Trace A wy Wg wx Oe 7 U 21 c D Component side of pcb Removethe two zero ohm resistors Wl and W2 4 Cut the trace just above and to the left of hole A 5 jumper from hole A to the trace This connects MREQ EO 22 6 Add jumper from hole to hole B This connects ROMCS to Ud pri 2
34. A CBZF Tee SRA A 4724 77 72 LD ML A IRITE MSN OF DATA pito E7 724 LD A 7 RESTORE zOtND REGS 27 O2F 5 725 rT SAQDPT A229 76 726 uD A B 4 1 727 QUT SDATPT A oo a SN 729 LD TE DFS 72 OUT SADDPT A A 7 7 77 Ln C A1 D 3F 731 QUT SDATPT F1 772 77 722 LD HL IRESTOFE HL ELAS Fi 724 FOP AF ATAA 2200 O 7 4 LD LOWNYB A RESTORE OE OOH E1 775 Fre HL TRESTORE REGISTERS 5744 C1 737 fup BC ATAN F1 774 UM NL 7 9 740 1 741 fF 742 PTC ADLES REL LIN Abl b E Pee Bata CI 744 y FY 74 READ PEL FLSH AF SAVE REGISTER AE 74 PRISH Bc 767 HL k Hi 420 742 LU H D DELW 74 lt LU HL MEMORY O LOWNYE f SAVE TBC FE 7 1 F 7 752 Lo A HL SAVE IHL RR FE 7 2 SE 3EC7 7 4 Lf 7 BE er E 7955 CUT CCADDFTO ISAVE VALUES OF Siu REGS 7 AND E 2END DRE 754 N A DATPT amp PHF 47 7 7 LD E ARTO SE OE 794 Lt A OEH amp 7C 7 9 CUT SADDFTO 4204 DEF 760 IN A SDATPT e Q A 4F 741 LL C amp 377 cs 762 FLISH BC CEO 782 Lo A 7 SET JOA CHANNEL TO CHITEEIT Ea CSF 764 QUT SADDPT amp utu SE AO 74 4 LL A 40H CURT 76 4 GUT SDATP
35. CH ADD skipping over Spaces and control characters except End of Line ODHZENTER 65 32 NXT_IS Like IGN SP but returns in A the Next Significant Character 40 CALCTR gt Entry to Calculator Routines 48 COPYUP Make room for BC Bytes of temporary workspace just before address in System Variable STKBOT by copying up memory between there and the address in STKEND adjusting affected pointers Returns DE Ist Byte of Space HLzLast Location 56 38H is the entry to service the hardware generated interruption which occurs approximately every 1 60 of a second 16 67 ms 160 Int Mode 1 is used This interruption is used to scan the keyboard call to routine UPD K see Section 4 1 1 It is also used to update the Frame Counter 3 bytes pointed to by the System Variable FRAMES used by the RANDOMI ZE instruction Location 102 66H is the entry point for the NMI interruption but this interruption is not used in the TS2068 design See Section 2 1 3 8 NMI Interruption 3 2 1 2 BASIC AROS Support BASIC Application Cartridges are supported by special code in the Home ROM program line is copied from the cartridge to a buffer in the Home RAM ARSBUF and is then executed from there by the BASIC Interpreter When a READ command is executed the line containing the appropriate DATA statement is also copied from the cartridge to the RAM The cartridge memory is enabled only fur search and copy operations for both
36. CLEAR command specifying an address no greater than 63255 F717H prior to invoking the Video Mode Change Service This reserves space between RAMTOP and the end of memory of 2280 bytes 8E8H utilized as 168 bytes User Defined Graphics 21 X 8 2112 bytes 840H Machine Stack and OS Routines 2280 SESH Exampl e RAMTOP 63255 Reserved Area 2280 65535 TFFFH The software packages in Appendix C are written assuming that RAMTOP is set to 57343 DFFFH or lower to protect the machine code which is loaded beginning at 57344 NEW Command If youhave used the Video Mode Change Service to open the second display file and now wish to execute the NEW command you should first return the computer to normal mode by calling the video mode service with A zero This returns the User Defined Graphics and other RAM structures to their normal locations Ifyou don t do this the UDG area will remain in the alternate location and if you have not corrected RAMTOP as explained above part or all of your UDG area could he cleared to zeros by the NEW command VIDMOD When Mode 128 80H is designated for activating the Primary Display File inDual Screen Mode the System Variable VI DMOD at 23746 5CC2H is set to zero instead of to 128 This creates a potential problem if the 17 ms interruption occurs before VIDMOD can be corrected since the interruption fielder will branch to Chunk 3 instead of to
37. COMPOSITE OIF 58 js 84444481111444444 COLOR 307 R34 ly d g g 4 2 2 10V R67 lt C64 Z a C65 s VIDEO Q 1K us NONCOMPONENT SIDE 5 MONITOR 75 P iH OUT 120pF 120pF PI EXPANSION PIB 32 C63 J8 nes C45 14 L3 120pF 7 TIMEX RF OUT 1 COMPUTER CORPORATION 560 oo01ur 33 33 Hy WATERBURY CONN 06720 R66 C29 C28 NAME 2241 TS2000 SYSTEM SCHEMATIC DIAGRAM DWG NO 2F NSE PUN SIZE amp TOL j es PHY SPH FIRST SUPERSEDES SCALE NONE SUP RSE DEI BY 335 870500 USED UN M2068
38. Chunk 7 and Chunk 3 is now in use for the second display file This problem is corrected by disabling the interruption prior to calling the Video Mode Change Service and setting VI DMOD to the correct value prior to re enabling it These corrections are included in the Extension ROM Interface Routine in Figure 3 2 2 2 128 NOTE On an initial access changing video mode from normal to Mode 128 the interruption is re enabled within the Video Mode Change Service itself after copying the stack and other Chunk 3 data to Chunk 7 This cannot be corrected but has not proven to present a problem in actual use At the point where the interruption is first enabled the Chunk 3 code is still intact allowing for correct processing of one interruption and the path length from there to the point of correcting VIDMOD is apparently less than 17 ms The interruption is also re enabled within the Video Mode Change Service if you have applied the patches for the BANK ENABLE and RESTORE STATUS routines Section 6 5 4 which are executed in connection with inserting space into the RAM to open the second display file Again this has not proven to be a problem in actual use 6 4 4 Interruption Inhibit By setting Bit 6 of Port to a 1 the normal 17 ms interruption generated from the SCLD to the Z80A CPU will be inhibited When Port OFFH is written to by the Video Mode Change Service Bit 6 is forced to zero If youwish to inhibit the normal i
39. During the INinstruction address bits AO A7zFEH select the Keyboard 1 0 port while bits A8 A15 select the particular 5 keys to be sampled during the particular INinstruction execution For example an INinstruction directed at the keyboard 1 0 port with address bit low and A9 A15 high will supply O s on KBO KBl KB2 KB3 and or KB4 if the CAP SHIFT Z X C and or V keys are respectively denressed Note that when reading the 1 0 port FEH data bits 05 07 are not part of the keyboard information Section 2 4 7 details the connection of the keyboard to the main P C board 2 1 10 16K Video Display RAM The 16K byte video display RAM composed of two 4416 s is isolated from the Z80A CPU by the SCLD control logic and buffers to allow the video display processor to access pixel and attribute data from the display files independent of the CPU see Section 2 1 8 3 The Video Display RAM is located in Chunks 2 and 3 of the Home Bank beginning at 400DH and 600DH respectively Figure 2 1 10 1 illustrates the organization of the Primary Display File located at 4000H The second display file utilizes the same organization Based on the video mode set via Port FFH the video hardware accesses the RAM for pixel data and attribute control information 44 Flgure 2 1 9 KEYBOARD SCHEMATIC En a A RIFY I IN Q RESET A DATA X B1 OF VAL LEN USA SPACE BAR A8 A 15 ADORESS BLIS ZB
40. ET 613 PUSH HL 6305 2AROS5C 14 LD HL NMIADD 6200 7C 15 LD 6200 616 OR L OE 2001 617 NZ LNI3 tIF NO USER SUPPLIEI SERVICE ROUTINE 6310 E 6186 JP HL 140 amp 1 6117 315 amp 3417 ARLE amp 31F AD A 5223 8726 5327 ASAE al29 eset 4 3201 Gace DER ARIO amp 231 6 2 amp 333 8724 5337 4328 339 43238 F1 EDAT Ft C pE 5 4 F I 47 CUOTAS r lt 04044 F 42 60994 ni C1 F1 C9 FS CUTECA FS FS CS ES 52 2 00 FS 7E FS SEO DFS DEFA 47 3 OE D3F 5 DBF 4F 3 07 DSF 3E40 4 3EOE D3F5 D3F6 7 77 CEZF 3 696 497 499 700 701 702 763 704 705 704 707 70 709 710 711 712 713 718 715 715 717 718 719 f POF HL POF RETN LI RS MAX RANK GET WORO ADIR HL GET WORT 1 1 8 w a FUSH CA L IT CALL C ALL CFL un LU CALL to IN LD pec EX LD CALL POP POP POP RET FIT WORD WORD DE UT WORE WHITE _BS_REG WRITE _BS_REG PUSH PUSH CALL PUSH LD LD CALL PUSH CALL CPL LD LD CALL LD INC LD DEC POP PCP CALL Foe POP RET REG_AUDR D PEG DATA FLUSH PUSH PUSH LD LD PUSH LD FUSH LD QUT IN LD LO QUT IN LD OUT LD OUT LD OUT XOR OUT
41. LD LD LD LD SRA 141 FANY EF ADDR HL 1 THI RC GE Y NUMBE AF H B A GET 3TATU S EC GE T IC HUNE B D BANK ENABLE E HL HL D HL HL HL BC p BANK ENABLE PC OF AF Bc GET NUHBPER AF D B B GET STATUS BC GET CHUNK B D C A EANK ENABLE AL E HL HL D BANK ENARLE BC AF AF Be HL H D L O LOWNYB AF HL AF A 7 SADDPT A A SDATPT R A SAOUPT SDATPT C A A 7 SADDPT 40H SDATPT SADDPT SDATPT A 2 LOWNYB E HL WORT HL BANK t I A COPY OF MAX RAN f SAVE REGS IGFT RANK OF 1 STATUS WF OWNER rr AL t SET HS FOR GETTING CFT IN ACTIVE LOW FORMAT f ENABLE IFEAD THE WORD tREENABLE OWNER tRESTORE REOS B 1 SAVE REGS BANK 6 OF OWNER CF ADDR STATUS OF OWNER ISET HS FOR GETTING ADDR TPUT IM ACTIVE LOW FORMAT ENABLE ADDR tWRITE THE WORD I OWNER ADDR E ISAVE REGISTERS MEMORY MAPFED ADCR 1 SAVE OEOOOH ISAVE HL 1 SAVE VALUES SOUND REGS 7 ANCI IOA CHANNEL TO OUTPUT NYBBLE STEERING LOGIC WRITE LEN OF DATA E amp 3E CRZF 720 SRA A Av CRZF 721 SRA
42. MASK Pt EQU ATTR T EQU MASK T EQU EQU XOR CH EQU INV_CH EQU F CB EQU B CF EQU EQU NMIADD EQU RAMTOP EQU P RAMT EQU ATTR_P 1 MASK P 1 ATTR_T 1 _ 1 2 4 P FLAG 1 MEMBOT 30 NMIADD 2 RAMTOP 2 4 48 4 B t 9 el gt TERMINATOR OF LAST DATA ITEM gt LINE BEING EDITED gt CURRENT CHAR IN INPUT BUFFER gt CURRENT CHAR WHEN SYNTAX CHECKING gt 1ST CHAR NOT SYNTACTICALLY OK O IF ALL OK ALSO STORES CHADD DURING READ amp INPUT gt TEMPORARY WORK SPACE gt BOTTOM OF CALCULATOR STACK gt NEXT FREE PLACE ON CALCULATOR STACK ALTERNATIVE NAME KEEPS VALUE OF CALCULATOR B REGISTER gt AREA USED BY CALCTR INSTRS MEMORY amp COPY MORE FLAGS AUTOMATIC LISTING ON SCREEN PRINTER BUFFER NOT EMPTY INSIDE STRING WHEN DOING KB MODE IN LISTCH CAPITALS SHIFT LOCK QN RETYPE POSSIBLE AFTER SYNTAX ERROR DELETE KEY REPEAT KEY HELD DOWN LINES IN 2ND HALF OF SCREEN INC SEP G BLANK LINE LINE IN PROGRAM OF TOP LINE ON SCREEN LINE OF E G INTERRUPTED STMT OLD SUB PPC STATEMENT NO WITHIN LINE FOR OLDPPC FLAGS ASSOCIATED WITH ASSIGNMENT FLEXIBLE LENGTH ASSIGNMENT REQUIRED DESTINATION OF ASSIGNMENT NOT FOUND REG INPUT VALUE RATHER THAN LINE PROGRAM REQD TYPE IS NUMERIC LINPUT INPUT LINE RATHER THAN STRAIGHT INFUT LENGTH OF DESTINATION W
43. PSG by combining the contents of the relative Coarse and Fine Tune registers as illustrated by Figure 2 1 6 2 Note that the 12 bit value programed in the combined Coarse and Fine Tune registers is a period value the higher the value in the registers the lower the resultant tone frequency Note also that due to the design technique used in the Tone Period countdown the lowest period value is 000000000001 divide by 1 and the highest period value is 111111111111 divide by 4095 19 FIGURE 2 1 6 PSG REGISTER BLOCK DIAGRAM REGISTER BIT DEC HEX OCT B7 B6 B5 B4 B3 B2 BO Z Rl Rl RI Tone Period 4 Bit Coarse Tune R R Channel R3 R3 R3 Tone Period 11 1 R R R Channel C 5 R5 85 R5 Tone Period 4 Bit Coarse Tune R6 RG u R7 R7 R7 Enable R8 R8 RIO Ch A Amplitude M L3 L2 rij 10 R9 89 Rll Ch B Amplitudd M R10 RA RI2 Ch C Amplitude 1 V M L2 L1 L0 4 Bit Coarse Tune Rll RB R13 Envelope 8 Bit Fine Tune E R12 RC RI4 Period OBit Coarse Tune E Envelope R13 RD R15 Shape Cycle CONT ATT lALT HOLD 1 0 Port R14 RE RI6 Data Store 8 Bit Parallel I O on Port A FIGURE 2 1 6 2 12 TONE PERIOD TP TO TONE GENERATOR COARSE TUNE FINE TUNE REGISTER CHANNEL REGISTER RI A RO R3 B R R5 C R4 _B7
44. RY BY NJ NJ NJ BRO NJ NJ NJ RY NJ NJ NJ NJ N gt CO c c c c c c c o 9 F w w w 99 ne m 0 Video RAM Data Organization 1 1 Composite Video Signal 2 4 1 1 P Mating Connector Mechanical Requirements 2 4 1 2 Pl Signal Layout 2 4 1 3 RGB Monitor Connection Schematic 2 4 2 4 Mating Connector Mechanical Requirements 2 4 2 2 J4 Signal Layout 2 4 4 Joystick Connector 2 4 8 1 AC Adapter Plug 3 2 2 Ext ROM Interruption Fielder 3 2 2 2 Ext ROM Interface Routine 1 1 1 1 Keyboard Mode Control 4 1 1 2 Keyboard Support Routines Flowcharts 1 1 2 1 Standard Character Table Locations 4 1 2 2 Screen Row Column Designations 4 2 Tape Header Formats 4 3 Joystick Data Format LIST OF FIGURES conti nued FIGURE NO TITLE a EPROM Cartridge Board Schematic Ctdg Bd Component Side Artwork Ctdg Bd Solder Side Artwork EPROM Cartridge Bd Solder Mask o 6 5 STATUS Corrections 6 5 2 WORD Corrections 6 5 3 BANK ENABLE and RESTORE STATUS Corrections LIST OF TABLES TABLE NO TI TLE 2 280A Control Signals 2 1 6 1 PSG 1 0 Enable Truth Table 2 1 6 2 PSG 1 0 Port Truth Table 2 1 8 1 SCLD 1 0 Pin Function Definitions 2 1 13 1 110 Port Map 2 4 1 1 PI Signal Definitions 2 4 1 2 PI Signal Electrical Characteristics 2 4 2 J
45. The HSR at port Fih has a 1 in the bit selected by a decode of Address bits A13 A15 and C BE is high causing activation of ROSCS ROS Chip Select 35 2 The EXROM bank is selected on amemory access with a Port FF bit 7 1 b The HSR at port F4H has a 1 in the bit nnn by a decode of Address bits Al3 A15 C BE is hi gh EL the activation of EXROM Ext ROM Enable 3 The Home Bank is selected on a memory access wi th The HSR at Port HH has a 0 in the bit selected by a decode of Address bits Al3 A15 b r is high causing the activation of the appropriate enable signal as detailed below Tounderstand the details of the schematic of Section 2 2 Appendix D 1 SELECT CARTRIDGE of Figure 2 1 8 1 involves activating ROSCS to its low active state 2 SELECT EXROMof Figure 2 1 8 1 involves activating EXROM to its low active state 3 SELECT HOME BANK of Figure 2 1 8 1 involves Activating ROMCS to its low active state when 15 0 and CAST to its low active state when 15 0 and TAS to its low active state when Al5 z1 and Acti vati n CAS3 to its low active state when Al5 1 and 36 FIGURE 2 1 8 1 BANK SELECTION LOGIC 32K RAM a T d s mo m a y gt p GEHE HORIZONTAL ae uu p SELECT REGISTER 7 Lane d e K see pez POSEEN 16K RAM m P Setect CARTRID
46. X SIN PI 2 Y 88 TABLE 3 3 3 2 TS 2068 FUNCTION DISPATCHER SERVICES continued SERVI CE SERVICE CODE DESCRI PTI ON COS 125 7 Replaces the top of the Calculator Stack by its COSINE SIN 126 Replaces the top of the Calculator Stack by its SINE TAN 127 Replaces the top of the Calculator Stack by its TANGENT ATN 128 80H Replaces the top of the Calculator Stack by its inverse TANGENT ASN 129 81H Replaces the top of the Calculator Stack by its inverse SINE ACS 130 82H Replaces the top of the Calculator Stack by its inverse COSINE ROOT 131 83H Replaces the top of the Calculator Stack by its Square Root TO THE 132 84H Replaces the top two numbers on the Calculator Stack X Y by y RDCH 133 85H Wait for character from currently selected channel calls INCH Returns character code in See 4 1 1 SENDCH 134 86H Write character whose code is in A to currently selected output channel See 41 1 2 WR CH 135 87H See 3 2 1 1 RESTART 16 K SCAN 136 88H Keyboard Scan See 4 1 1 89 SERVI CE P LFT PUT MES CLS SCRL F PNT DRAWLN LN TABLE 3 3 3 2 TS 2068 FUNCTION DISPATCHER SERVI CES continued SERVICE CODE 137 89H 138 139 8BH 140 8CH 141 8DH 142 8EH 143 8FH 144 90H 145 91H 90 DESCRI PTI ON Backspace Sets current column position back 1 for selected device System Variable updat
47. aces 09 Reverved gataer 908 GC s1 6994 821 600024 906 GRAPHS 58957 GRTSC 64 GTCHL 92 CCa e 34 5T1Cn23 69 6 948 GTC 1 19 7 610432 969 GTC ms 6946 GTCHs 983 GTCn6 0930 G 1 0 Reserved t t everves 2 LOPOSN ETL Ince 2096 45 erac Reserved 689 MA SASF scoe 217 69 secas 0318 SETSPR 6904 P Reserved STPQSN E90 dG UPDATT et 406 uP0412 412 09 lt 9 604 vLOMQO SCC 903 0 6443 EET t4C0 9C4 Easoa WACHLS APE 2 008 7114257 2196 WRCHI eoet cera to 50 orrore detested APPENDIX D TS2068 PCB Assembly and Schematic Diagram The following Appendix contains the PCB Assembly Drawing the PCB Parts List end PCP Schematic Diagram a fold out page located just inside the back cover The Table below contains some corrections to the Schematic Diagram w AP562066 BCE Schematic Diagram Corrections Page 34 of the Technical Manual shows pin 9 of the joystick ports grounded as it should be The traces were left off the TSZ068 PCB VRL 33 22 goes Gor VEI 04 Connect base to R55 R54 Solder dots on horizontal lines below keyboard U12 4 to U3 65 WR 012 5 to 03 66 MREQ 12 U5 2 to 03 38 not Pls PILE HELIS uot 1 53 uz 2 00 R44 C gt 12 Ue o
48. an AROS 6 2 Machine Code AROS When setting the AROS Overhead parameter requesting RAM space for machine code variables 21 n bytes 15H n must be requested where n is the number of bytes needed The machine language variables area then starts at 69558 immediately following the 21 byte CHANS area See Section 5 1 2 3 NOTE This does not apply to an AROS that contains both BASIC and machine code 126 6 3 BASIC AROS 6 3 1 USR Function When testing the USR address against the Cartridge Memory Selection byte to determine if the address is in the Home Bank or the Dock Bank the wrong nibble is tested in the register thus a valid cartridge address could be erroneously processed as a Home Bank address Since the ROM code cannot be corrected the machine code in the cartridge would have to be movedto an address that does not cause a problem 6 3 2 FOR NEXT Ifthe limit of the FOR statement has already been passed on its initial execution FOR 1 TO 10 and has been set to 12 control is passed to the statement following the corresponding NEXT Inthe AROS support code the address of this statement is lost giving unpredictable results Since the ROM code cannot be corrected care must be taken not to use this technique in an AROS Cartridge Normal usage of FOR NEXT loops is not affected 6 3 3 Advanced Video Modes Because the BASIC AROS support code interfaces directly to the Bank Switching code in Chunk 3 does
49. attributes are fixed at 0 and the Border is fixed to match the paper color The Attribute Files in RAM at 5800H 5AFFH primary display file and 7800H 7AFFH second display file are not utilized in this mode 123 9 2 Software supporting this mode must set up the display file address for character insertion based on the column position evenzDFl oddzDF2 When scrolling the screen or a portion of it any line of text on the screen requires the same operation to be done at the corresponding locations in each display file This is also true to clear the screen or a portion of it To save a Screen on tape you must save two Code files one for each display file The SAVE filename SCREENS will work for the Primary Display File only You will have to specifically SAVE the second display file via a SAVE filename CODE 24576 6144 Note also that because the Border color is fixed by the video mode you will not see the usual stripes during a tape operation Code to support an 80 column mode screen was developed utilizing the 64 column hardware mode and redefining the character size to a 6 X 8 pixel group there is really room for 84 characters if the full 256 pixel width is used Since individual characters now can span the two display files e g 2 pixels in DFI and 4 in DF2 insertion of data into the display files involves masking the 6 bit character or portion thereof with the 8 bits of data read written from to the display fi
50. be accomplished by writing all zeroes into the corresponding Amplitude Control register R8 R9 or RIO refer to Paragraph 2 1 6 4 2 1 6 4 Amplitude Control Registers R8 R9 RIO The amplitudes of the signals generated by each of the three D A Converters one each for Channels A B and is determined by the contents of the lower 5 bits 84 80 of Registers R8 R9 and RIO as illustrated by Figure 2 1 6 5 FIGURE 2 1 6 5 D A CONVERTER SIGNAL GENERATION AMPLITUDE CONTROL REGISTER CHANNEL R8 R9 B RIO C B B6 B5 B4 B3 B2 bi BO NOT USED Amplitude 4 Bit Fixed Mode Amplitude Level 25 2 1 6 4 continued The amplitude mode Bit selects either fixed level amplitude M 0 or variable level amplitude Mzl It follows then that Bits 13 10 defining the value of a fixed level amplitude are only active when Mz0 When fixed level amplitude is selected it is fixed only in the sense that the amplitude level is under the direct control of the system processor via bits 13 10 Varying the amplitude when in this fixed amplitude mode requires in each instance the direct intervention of the system processor via an address latch write data sequence to modify the L3 LO data When M select variable level amplitudes the amplitude of each channel is determined by the envelope pattern as defined by the Envelope Generator s 4 bit output E3 EO refer to Paragraph 2 1 6 5 The amplitude
51. beginning program execution The AROS buffer ARSBUF begins immediately following this reserved area see Fig 1 1 3 Note that this area is part of the RAM that gets relocated if the second display file is opened Therefore access to your machine code and or variables should he conditional on the video mode rather than direct if you are going to be using the advanced video modes This reserved area begins at 31488 7B00H when the second display file is open Remember use of the second display file and execution of BASIC program from the cartridge are mutually exclusive The standard technique of reserving space for machine code by modifying RAMTOP could also be used to place machine code variables at the top of the Home Bank If you place code above RAMTOP which is to be accessed via the BASIC USR function the affected memory chunk s cannot be marked as in use in the cartridge in the AROS Memory Selection Specification 2 Machine Code AROS A machine code AROS is similar to an LROS with the exception that it is dependent on the System ROM for interruption handling if the interruption is enabled This implies that Chunks 0 3 are enabled in the Home Sank 111 The Autostart parameter should be set to 1 since if it is Zero control will be passed to the BASIC Interpreter as if the cartridge were not present There is no BASIC command to directly start execution of a Machine Code AROS Because of a bug in
52. for each 8 X l pixel group thus giving 32 X 192 positions within each of which two colors plus Bright and Flash can be defined Each byte of pixel data entered into the primary display file has 120 its own Attribute byte in the corresponding location in the second display file e g the byte written to Location 4000H has its Attribute byte at Location 6000H the byte at 47FFH last byte of last scan row in Line 7 has its Attribute byte at Location 67FFH the byte at 57FFH last byte of last scan row in Line 23 has its Attribute byte at Location 77FFH The routine writing data to the screen would therefore enter the pixel data to the desired location and then set Address Bit 13 of the Primary Display File address and write the desired attribute control byte to the resultant location If normal characters are being written to the screen in this mode eight Attribute bytes must also be written one for each of the bytes defining the character The same technique would be used for writing to both display files i e for each of the seven bytes entered after the first the display file address would be incremented by 256 100 The System ROM graphics commands PLOT DRAW and CIRCLE place data into the Primary Display File and update the Attribute File associated with the standard video mode 5800H 5AFFH In High Resolution Graphics Mode the hardware does not access this area for attribute control therefore its contents have no visible e
53. hold at that count 30 To further describe the above functions numerous charts of the binary count sequence of E3 EO could be used showing each combination of Hold Alternate Attack and Continue However since these outputs are used when selected by the Amplitude Control registers to amplitude modulate the output of the Mixers a better understanding of their effect can be accomplished via a graphic representation of their value for each condition selected as illustrated in Figures 2 1 6 10 and 2 1 6 11 FIGURE 2 1 6 10 ENVELOPE GENERATOR OUTPUT R13 83 B2 51 A C L 0 T A Y Y R I vi N w Al al GAAPHIC REPRESENTATION ul t L OF ENVELOPE GENERATOR K E 0 OUTPUT 62 1 EO Q 0 0 t 9 REFER ro figure 2 1 6 11 9 FOR OETAIL 0 t t EP IS THE ENVELOPE PERIOO OURATION OF OIE CYCLE S4 FIGURE 2 1 6 11 DETAIL OF TWO CYCLES OF FIGURE 2 1 6 10 2 1 6 6 1 0 Port Data Store Register R14 Register R14 functions as an intermediate data storage register between the PSG CPU data bus DA7 DA0 and the 1 0 Port 10A7 1040 This port is available for reading the joysticks Using register R14 for the transfer of 1 0 data has no effect at all on sound generation To output data from the CPU bus to a peripheral device connected to 1 0 Port A would require the following steps 1 Latch address R7 select Enable register 2 Write data to PSG setting R7 B
54. not access based on its relocatability the second display file cannot be open when executing BASIC program from an AROS 6 4 Video Mode Change Service 6 4 1 Available Memory Test When the size of memory needed is calculated by adding the size of the second display file 6912 bytes or 18008 to the memory now in use address in System Variable STKEND the code fails to check for overflow Thus if the address in STKEND is greater than 58623 E4FFH the fact that there is not enough free memory to open the second display file will not be detected and the systen will crash If your BASIC program and or variables area are large you may want to make this test yourself prior to invoking the Video Mode Change Service in order to avoid this problem The size of memory needed is subsequently tested against the contents of RAMTOP and if there is not sufficient space value in RAMTOP is less than size needed you will get Error 4 Out of Me mor y 127 6 4 2 RAMTOP When the machine stack and OS RAM code is 6 6 4 4 3 4 moved to Chunk 7 the User Defined Graphics area is moved down in RAM by 2112 bytes 840H to make room for the stack and OS RAM routines at the top of memory The pointer in UDG is updated however the value in RAMTOP is not modified to insure that the relocated UDG area as well as the OS code and stack are protected from expansion of the BASIC program You can avoid problems by setting RAMTOP via a
55. of the Edit Line with the C or E cursor display of ROM data or multiple scrolls Stick to single key responses and you won t have any problems When DELETE Cap Shift 0 is held down to do deletion of characters in the Edit Line sometimes it outputs the DELETE Keyword instead it should not do this in auto repeat mode This is especially noticeable when the input line is long Since the ROM code cannot be corrected you must try releasing and pressing the DELETE key at differing frequencies and you will be able to get past this Bug 135 LINK 1 7 LOAD MAP MODULE BLOCK BASIC KSCAN IO 1 IO 2 EDIT CHANS LIST AROS SYNTAX SYNTWO GRAPHS EXPRN IDENT INOUT SUMS CALC FUNCTS TAPEMSG CH SET GLOBAL ALS ACL ALNIM ALPHA ANGLE ARIS ARRAY AR_LN AR NXT ASN ATN ATTBYT BEEP BORDER BREAK CAT CHCOLDE CHK 52 CIRCLE CL CHAN CLEAR CL EL CLLHS CLOSE GLPR BC CLS CLS R COL TM CUL CILIR CONT GP EC CTRO APPENDIX A HOME ROM MAP ORIGIN LENGTH 0000 0227 0500 0402 ODID 139F 14E1 17R5 1745 214 2603 2354 2070 2059 S354 SABB 3089 S000 ADDRESS SCSE 3303 2044 3045 SEE 1276 27035 17EA 17FF 3BFD 0710 0434 2436 2009 AS 0371 11 1F BR 2479 1 3BE 1F34 133F OSA 139F Cm35 1F39 Q97F 224 23DE 1EE4 3BCS 15 371A 0000 9227 0209 0802 O31B 0622 0142 2 4 0120 OSOA 9484 0251
56. test the value in the System Variable VI DMOD at location 23746 5CC2H A zero indicates that the second display file is not in use and that the OS RAM routines are therefore in Chunk 3 any non zero value indicates that the routines are in Chunk 7 YOTE This design implies that Chunks 2 3 and 7 are always enabled in the Home Bank RAM whenever the System ROM and or RAM routines are being used The OS RAM routines are contained in Module Dispatch which ts included in Appendix A 3 3 4 1 RAM Interruption Handler Chunk 3 Entry 62 Chunk 7 Entry FA6EH The user must enter with bank status and 780 registers intact with address from point of interruption on the stack The RAM interruption handler saves state including memory selection enables the Home Bank updates the Frame Counter calls the keyboard scan routine in the Home ROM restores state and returns to the interrupted process The RAM Interruption handler is used whenever the interruption occurs while the Extension ROM is enabled See Figure 3 2 2 1 Extension ROM Interruption Fielder This same technique can he used for interruption processing in another bank e g if an LROS wanted to use the standard system ROM keyboard scanning routines 3 3 4 2 RAM Service Routines Table 3 3 4 1 lists the RAM service routines which are designed to facilitate communi cation between memory banks Those with Service Codes are accessible via the Function Dispatcher
57. the Home Bank ROM Extension and Dock This results in switching out of either the Home Bank or the Dock when status is restored This affects use of the Function Dispatcher and GET WORD routines and any other code using GET STATUS Figure 6 5 1 shows the patches and additions necessary to correct this routine PUT WORD Write data passed in Reg Pair DE is overwritten prior to use Figure 6 5 2 shows corrections BANK ENABLE and RESTORE STATUS Ifthe 17 ms interruption occurs during update of the memory selection hardware it can cause the system to hang and RAM to be overwritten This occurs when the interruption happens in an interval when Port FF Bit 7 is zero thus selecting the Dock Bank and Port F4 Bit 0 is one thus enabling Chunk in the Dock Bank and there is no memory in Chunk 0 of the Dock Bank This can be true when there is no cartridge installed or if the cartridge installed is an AROS This problem is corrected by disabling or masking the interruption while updating the memory selection hardware Figure 6 5 3 shows one implementation of this correction SAVE STATUS and RESTORE STATUS The value of Port FFH which includes video mode and interruption inhibit as well as Ext ROM Dock Select is saved and restored as a full 8 bits Therefore any modification of this port by code accessed between execution of SAVE STATUS and subsequent execution of RESTORE STATUS erg via CALL BANK or use of the Function Dispatcher
58. the Initialization code handling a Machine Code AROS the parameter specifying the number of bytes to be reserved for machine code variables must be adjusted by adding 21 15H to the actual number of bytes needed This preserves the 21 byte CHANS area starting at 26688 6840H The reserved area then starts at 26709 6855H or 31488 7B15H when the second display file is open Access to the variables should be conditional based on the video mode rather than direct if you plan to use the advanced video modes If yudo not plan to utilize any of the system software you can disregard the above and do your own thing with the RAM See Section 6 0 for known corrections when using System SIW 5 1 3 EPROM Cartridge Board Application Figure 5 1 1 provides the logic diagram for a pluggable EPROM cartridge board capable of configuring up to four 16K byte 128K bit EPROM s of the 27128 type The artwork for the PC board implementing that logic diagram is provided in Figures 5 1 2 5 1 3 and 5 1 4 for the Component Side art the Solder Side art and the Solder Mask one common mask for both sides respectively See Section 2 4 2 for mechanical details of the connector portion of the PCB 112 FIGURE 5 1 1 PLUGGABLE EPROM CARTRIDGE BOARD LOGIC DIAGRAM Vcc A14B iib 130 A158 16 3 5 ROSES 5 15 7415155 113 FIGURE 5 1 2 EPROM CARTRIDGE BOARD COMPONENT SIDE ARTWORK COMPONENT SIDE 4 5 2000 81
59. the requesting device that the CPU has set its address data and control bus signals to a high impedance state in response to Figure 2 1 4 1 REWORK TO REPLACE ROM s with EPROM s Legend Omm ADO lt lt lt CUT 17 2 1 4 ROM The system includes both a 16K byte ROM and an 8K byte ROM mapped into the address space as shown below 3FFFh U16 16K ROM lFFFh 020 8K ROM 0000h OOOOh HOME BANK EXPANSION BANK Section 2 1 8 1 describes the selection of the Home Bank and Expansion Bank via the control logic The devices involved are a 23128 and a 2364 for the 16K byte 128K bit and the 8K byte 64K bit ROMs respectively Direct replacement of these devices with 27128 and 2764 EPROM s is not possible since pins 1 and 27 must be maintained in the high state for those devices see schematic in Section 2 2 To replace 016 and U20 with 27128 and 2764 EPROM s requires the rework shown in Figure 2 1 4 1 1 Cut input to pin 27 on each chi p 2 Wire 5V to pins 1 and 27 on each chip to pull high If 020 is to be a 27128 then replace the RD input to pin 26 with address Al3 from pin 26 on U16 2 1 5 32K RAM Address 8000 FFFFH The upper 32K of RAM is composed of four 200ns 4416 s 16K x 4 dynamic RAMs 18 2 1 6 Sound Generator The Programmable Sound Generator GI 8912 is accessed via Ports OF5H Address and OF6H Data The basic registers in the PSG which produce the programmed sounds include T
60. to Port OF5H address to Programmable Sound Generator and the second parameter load data to Port OF6H data to PSG The program line is scanned for multiple parameter pairs and continues writing address data pairs to the PSG until the end of the statement is reached See Section 2 1 6 for details on the hardware of the PSG 105 5 0 Advanced Concepts 5 1 Cartridge Software Hardware 5 1 1 LROS An LROS is identified by the following overhead bytes Location Description 0000 Not Used 0001 Cartridge Type 01 LROS 0002 0003 Starting Address LSB Address to be jumped to after Operating System initialization is complete Order of bytes is as for a JP instruction 0004 Memory Chunk Specification Bits 0 7 represent Chunks 0 7 respectively in the Dock Bank in low active format 0 if in use 1 if not in use NOTE When writing to the Horizontal Select Register Port HH the Chunk Specification is High Active The Memory Chunk Specification is used to enable the specified chunks in the Dock Bank prior to jumping to the address specified in Location 2 and 3 Control is transferred from the Initialization code in the Extension ROM via the GOTO BANK routine in Home Bank RAM Chunk 3 therefore Bit 3 of the Memory Chunk Specification must be set to 1 in order for the transfer to be accomplished as designed Chunk 3 also contains the Machine Stack CAUTI ON IfChunk 3 is marked for use in the Dock Bank then when the Memo
61. to Port OFFH Bits 0 5 and the System Variable VIDMOD 5CC2H is updated The second display file is cleared to zeros on initial access for Dual Screen Mode and High Resolution Graphics Mode this results in a black screen since 0 yields attributes of black ink on black paper Ifthere is not enough free memory to do the necessary remapping Error 4 Out of Memory is given Access to this service via the Function Dispatcher cannot be made consistently for various reasons An Interface Routine is given in Section 3 2 2 4 to be executed from the Home RAM which provides access to the Vi deo Mode Change Service as well as other Extension ROM routines See Sections 4 1 2 and 5 2 for discussion of video screen support software See Section 6 4 for details on known problems and corrections related to the Video Mode Change Service 68 128 80H 14 OEH 22 16H 30 EH 38 26H 46 2EH 54 36H 62 TABLE 3 2 2 INPUT TO VIDEO MODE CHANGE SERVICE VIDEO MODE Normal Dual Screen Dual Screen High Resolution Graphics 64 Col umn nk Paper Black White Blue Yellow Red Cyan Magenta Green Green Magenta Cyan Red Yellow Blue White Bl ack The areas of memory DESCRIPTION Primary Display File 2nd Display File if Open Onl y Close Two Display Files Available Primary Display File Active at Screen Two Display Files Available Second Display File Active at Scr
62. 0 16 10H 18 12H 30 1EH 32 20H 34 22H 46 2EH TABLE 5CC2H the second display file LSB MSB Line 17 address of 5020H 17H col umns of 11 OBH 20 43 40 40 20H 20H EO 40 00 48 20 48 20H 20H 48 00 50 20 50 20H 20H 0 50 Column 4800H 5000H 23 11H 17H 5037H second display file was to be used address would yield 7037H because the column is odd Bit the starting line column address by 2 shift in each display file address display file address address character 100H between incrementing containing simplified version DE contains that Reg character address of desired each write the the address illustrating this process address of the desired table and that HL contains the Pair in the character upp you can determine whether to set Bit because you are in an or simply because you are using of er 0 screen mode Line 0 Top of Screen Line 1 Line 2 Line 7 End of Upper Block Line 8 Top of Middle Block Line 9 Line 15 End of Middle Block Line 16 Top of Bottom Block Line 17 Line 23 End of Bottom Block would yield a display right 7102BH this The the 0 1 getting 7020H If VIDMOD indicated the setting Bit 13 of the If wewere using 64 column mode we would set Bit 13 of then divide the 1 since there are only 32 This would give us an off
63. 0 8 2 0 15 120 D5 30 0 4 1 8 2 4 0 8 2 0 15 120 D6 30 0 4 1 8 2 4 0 8 2 0 15 120 D7 30 0 4 1 8 2 4 0 8 2 0 15 120 Vcc 5 5 25 300 4 75 GND s 61 2 2 4 4 4 Cassette 1 0 The and MICconnectors provided on the rear of the T 2068 are 118 mi ni phone jacks requiring 118 plugs as mating connectors MIC output is filtered by a low pass filter with a breakpoint of 2 5KHz and provides a signal output of 0 15 to 0 67 V p p The EAR input is filtered by a low pass filter with a breakpoi nt of 23 KHz Input voltaqes should be between 4 0 and 10 0 V p p Joystick The joystick input connectors one on each side of the 752068 case are standard D pin D type connectors for use with 5 switch type joysticks Connector layout and the function of each pin is given in Figure 2 4 4 1 and Table 2 4 4 1 respectively FIGURE 2 4 4 JOYSTICK CONNECTOR 5 4 9 9 9 62 TABLE 2 4 4 JOYSTICK CONNECTOR SIGNAL ASSIGNMENT SIGNAL NAME 1 0 PORT BIT FUNCTI ON STI CK UP STICK DOWN STICK LEFT STICK RIGHT not used PUSH BUTTON 9 VOLT POWER READ STROBE ADDRESS BIT 8 OR 9 GND POWER GROUND When Address Bit 8 is high the READ strobe to the left joystick is driven low When address Bit 9 is high the READ strobe to the right joystick is driven low 2 4 3 Adapter Power Plug The AC Adapter provided with the TS 2068 provides unregul
64. 03H BASIC AROS Addrs of First Program Line Machine Code AROS Addrs of First 280 Instruction 32112 Memory Chunk Specification 8004H Bits 0 7 represent Chunks 0 7 respectively in the Dock Bank in low active format as follows 0 if in use l if not in use NOTE Bits 0 3 must he set to 1 for proper execution 32113 Autostart Specification 8005H 0 No Autostart 1 Autostart 327741 32775 Number of bytes of RAM to be 8006 8007H Reserved for Machine Code Variables LSB MSB 0100 1 byte Reserved 0002H 512 bytes Reserved 3 1 2 1 BASIC AROS A BASIC AROS is supported by special code in the System ROM Section 3 2 1 2 The portion of the cartridge containing BASIC program lines is restricted to the upper half of the memory space beginning at location 32776 8008H the Dock Bank Support for User Defined Functions which requires searching for 109 the definition parameters within the program is not implemented Also because the support code interfaces directly to the bank switching code RAM Chunk 3 does not allow for it to be relocated to Chunk 7 a BASIC AROS cannot utilize the advanced video modes and also execute BASIC program statements If the cartridge contained machine code supporting advanced video modes the TS 2068 would have to be returned to Normal video mode with the RAM mapped accordingly see Figure 1 1 3 if control were to be returned to the BASIC Interpreter USR code Since ex
65. 1 you will want to clear Sample routine GETJOY LD A OEH Load A 14 OUT A 0F5H Address the joystick port LD B playerno LD 0F6H Data Port address to IN Joystick data to A CPL Compl ement to High Active AND 8FH Get significant bits The data read is LOW ACTIVE i e all bits 1 byte FFH when the stick is at center and the button is not depressed Figure 4 3 shows the interpretation of the data byte FIGURE 4 3 JOYSTICK DATA 3 2 Bit 0 1 L STICK UP STICK DOWN 0 x LSTICK LEFT STICK RIGHT NOT USED Always 1 BUTTON DEPRESSED 4 4 S W Generated Sound The BEEP command produces sound using the speaker by toggling Bit 4 of 1 0 Port to generate a signal of a calculated frequency and duration based on the command parameters It uses the routine PARP which takes as input two parameters one defining the period of the signal HL and the other defining the number of cycles to be generated DE and outputs 0 1 cycles of a tone having the period 8 236 to 88 2246 T States where HL N Both the BEEP and PARP routines are in the K SCAN module of the Home ROY The PARP routine is also used to generate the keyboard click and the raspberry which can be varied by modifying the values in the system variables PIP 23609 5C39H and RASP 23608 5C38H 4 5 Sound Chip SOUND The SOUND command writes the first parameter register number
66. 14 25429 43 Input PUT WORD mark the locations Data in DE Address in HL Bank in B PUSH AF Save Regs PUSH BC CALL GET NUMBER Bank of Owner PUSH DE Save Data LD D B Save Target Bank LD Bank of Owner CALL GET STATUS Get Bank Status PUSH BC Save It CALL GET CHUNK Get Bit Map CPL Set High Active LD B D Target Bank to B LD C A Memory Select Byte CALL BANK ENABLE Enhl Target Mem POP BC Saved Bank Status POP DE Saved Data LD HL E Write LSB INC HL Increment Adrs LD HL D Write MSB DEC HL Restore HL CALL BANK ENABLE Restore Bank St POP BC Restore Regs POP AF RET Return modified corrections to GET STATUS and BANK ENABLE are also required 133 FIGURE 0 5 3 BANK ENABLE AND RESTORE STATUS CORRECTI ONS From BASIC BANK ENABLE Location Object Code POKE Address Value 6499H 00 NOP 25153 0 649DH F3 DI 25757 243 651 CH FB El 25884 251 RESTORE STATUS 654AH F3 DI 25930 243 6570H F B EI 25968 25 In both cases theDisable Interrupt and Enable Interrupt are being done by deleting the preservation of the AF Registers PUSH AF POP If your code requires AF to be saved you must do it prior to calling either of these routines or any other system routines that use them Note also that if you already have the interruption masked when these routines are entered it will be enabled when they are exitted If this proves to be a problem replace the Enable Interruption ED instruction wi
67. 26 1038 11 4 ic 1 1n4o 104 2 1044 1045 1045 104A 146 104E DEO ADS 1054 1 4 1 LTA 10500 1PSE 1040 ipe 104 4 1 4 4 1014 5 10 A 1Der 1 D70 1072 10 74 1074 1 I73 107 A Ez4 65 565 SEAS 3042 T0 65 644 CEES ETAS 2465 EDAS FOE 1 4 6 zb ee SAAG 4746 Ot 6644 724 O GALL COEL F Li 0 67 067 4F 7 T0467 067 7647 7067 472 7 1267 4 7 AY 70 73 100 101 102 HANK ENABLE 1 DEFW BANI ENABLE 7 SH ENABLE 7DH UEFW SAVE STATUS 1 4H SAVE STATUS 1CH DEF W RESTORE STATUS 1 ZH DEFW RE TORE STATUS 1 CH DEF W BS DEFW GOTO_BANK 13H CALL BANK 3H DEFW CALL BANK 1 DH LE FW CALL BANK 29H DEFW CALL BANK 4EH DEF W CALL BANK 5DH CALL BANK amp DEFW CALL BANK 7 2H CALL BANK 80H DEFW CALL BANK 96H CALL _ BANK 0A2H DEF W CALL BANK ORGOH D FW MOVE RYTES DEFW MOVE _ CREATE_BI TMAP 1 SH DEF W CREATE_BI TMAP 1 BH DEF W XFER_BYTES CEH DEF W XFER BYTES 2DH DEFW 2 DEF W XFER BYTES 38H DEFW XFER_BYTES 54H DEF W XFER_BYTES SEH XFER_BYTES 85H DEFW XFER BYTES OBAH DEFW XFER BYTES OCIH DEFW XFER_BYTES OD4H O THIS I THE TABLE TERMINATOR APPENDIX B Syst
68. 279 ADOR Loe 1279 JP IK 103903 Vers o dg So FALL EAN ADUR BANK HORIZONTAL SELECT FRM OUT FRM IN 193303 ALL INFUT PARAMETERS ARE PUSHED ON THE STACK 2941 t q CLOBRERS IX 1 9 4087 1 IOAN g SETS UP THE BANK AND MAKES JUMP WITH KETURN ADDKESS TO ADDRESS 109 1 IN BANK 1191104 19914 ATIE 107 BS STACK DEFS amp 4 LE 1073 BS SP DEFS 2 1276 129 1 1996 CALL BANK EX SP HL RET ADDR e t 01 DD 2ACESS 1097 LD IX BS SP 09 DDZR 1098 CEC IX ATO 007400 1099 IX H UA OZB 1100 LEC IX ODO Siu 1101 LD tx L FUSH HL ON BS_STACK E1 1102 FOP HL 1103 EX SP HL PRM IN X UD2B 1104 DEC 1 DE3 007400 1105 LD IX H 5E6 CULE 1106 Dec iX ATEZ 007900 1107 CIR L PUSH PRM IN ON 5 2 ATER DDUZZCE4T 1108 LD BS SP IX BSSP amp 05 1109 PUSH 1 SAVE REOS s 1116 FUSH BC OTF 1 F3 1111 PUSH AF 2 210000 1112 LD HL O SF 39 1113 ADD HL SP IHL P 5F 4 1114 LD amp 5F7 111 LD E L SSF 3 181545 1114 ES_MAX_BANK ASFB 4F 1117 LD C A amp SF C 1113 LU B O e5FE 1112 INC ec e7FF ea 1126 BC MAX c EAN A7 1121 AND A 145 4601 46093 e404 4 403 4404 4406 460E amp 11 5613 4414 amp 15 4447 amp 61 e51D 441D 4 4 20 6424 5526 429 AAC bA gE 6430 E631 A 22 4433 46 3 e637 6639
69. 3 a T e DC VJ C di 5 gt i 3 jJ lt p gt i 3 Z gt gt nj s HE lt gt I lt gt 9 2 o 5 nc LAS LAS AIA 7417117 ra a G TOQ OO UC OL C3 4 3 4 5 7 R49 2 1 556 E C R RY 37 6 85 Sw RG8 R c D D D C i C42 S4c 782068 PC BOARD COMPONENT LAYOUT 289 555 852901 05 TIMEX TS 2008 APPENDIX D 752008 PARTS LIST COMPONENT QTY DESCRI PTI ON DESI GNATI ON PER ASSY COMMENTS Fabrication and Artwork REV 3A CAP 0 1 uf Ceramic Axial C2 7 9 16 24 30 2 3 20 80 or GMV 31 34 35 37 39 43 TEMP 275 44 48 49 50 51 52 53 54 55 56 57 CAP 0 01 uf Ceramic Axial C11 12 14 33 61 8 20 80 or GMV 62 68 69 TEMP 75 0 001 uf Ceramic Axial 8 45 46 47 4 20 80 GMV TEMP 275 0 047 uf Ceramic Axial 10 15 74 75 4 20 80 GMV TEMP 75 20pf Ceramic Axial 23 20 80 or GMV TEMP Z5U CAP 39pf Ceramic Axial c20 NPO 43pf Ceramic Axial 19 1 NPO 56pf Ceramic Axial 25 1 NPO CAP 75pf Ceramic Axial 32 1 NPO CAP 120pf Ceramic Disc 59 63 64 65 72 6 20 80 73 TEMP 75 470uf 25V AL Electro 1 lytic Axial 1 uf 16V MINAL Electro c21 lytic Axial CAP 47 uf 16V MINAL Elec 41 1 trolytic Axial or Radial 1000 uf 12V M
70. 5 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 V V V V Y V v V V DF2 6000 7AFFH Bit13 1 Inorder to display a character on the screen 8 bytes of pixel data must be entered into the display file one for each scan row For a particular character position the scan rows are 100H bytes apart E g the 8 bytes of pixel data for position Line O Column 0 are located at 4000H 4100H 1200 47008 Since this is the first character position on the screen its Attribute byte in Normal Mode is the first byte in the Attribute File which starts at 5800H The 768 300H Attribute Bytes are in sequential order starting at position 0 0 through 0 31 1 0 through 1 31 and so forth ending with 23 0 through 23 31 One method of determining the starting display file address for a particular line column position is to build a table containing the starting address of each of the 24 lines 2 bytes per entry Then construct an algorithm that takes the 117 LINE lt gt 15 16 17 line number and forms an index by multiplying it by 2 shift add the index to the base address of the table The column position is By testing left 1 read out the display file address added to this address then simply an offset VIDMOD 23746 13 for odd column in 64 column mode the second display file in dual The following example illustrates this method entries are in Hex NDEX 4 14
71. 6 1 3 Latch address R14 select 10 register 4 Write data to PSG data to be output on 1 0 Port A To input data from 1 0 Port to the CPU bus would require the following 1 Latch address R7 select Enable register 2 Write data to PSG setting R7 6 0 3 Latch address R14 select 10 register 4 Read data from PSG data from 1 0 Port Note that once loaded with data in the output mode the data will remain on the 1 0 port until changed either by loading different data by applying a reset grounding the Reset pin or by switching to the input mode 32 Note also that when in the input mode the contents of register R14 will follow the signals applied to the 1 0 port However transfer of this data to the CPU bus requires read operation as described above 2 1 7 Joystick Port Operation The joystick port Register 14 of the Sound Chip Section 2 1 6 6 is read via an IN instruction directed at port F6H with selection of activating data from the left player 1 or right player 2 determined by Address bits 8 and 9 as shown in Figure 2 1 7 1 In order to address Register 14 a OEH must be written to port F5H Sound Generator Address prior to reading joystick data Section 4 4 describes the software sequence necessary to control this hardware In the example of Figure 2 1 7 1 the joystick shown schematically in the lower left of the drawing is composed of a movable center stick which is pushed up to
72. 7 05 PiA 11 44 13 24 J4 29 5 16 D4 13 44 17 PIB 25 6 15 D3 PIA 12 J4 15 PIB 13 14 14 7 33 02 PIA 9 J4 9 PIB 4 12 8 1 D1 PIA 8 44 7 VT AR7B PIA 3 1124 10 9 11 D PIA 7 J4 5 C68 15 SOUND TANK 10 04 8 10 OIF uu 2364 BKx8 16 unoMA SUPPLY MAGK ROM 250N6 EXER 5 JOYSTICK J6 JOYSTICK PIA 27 44 34 a lt J4 CARTRIDGE lt lt lt lt p lt x a 9 Q o COMPONENT it Y 7 8 2 E 2 ag ee J SL as S S 1 lt e S z LM1889N 9 lt lt x amp v CHB TANK yy 2 4 8 B 10 12 14 16 18 20 22 24 26 28 30 32 34 36 5 4 3 2 1 3 2 1 1 3 5 7 9 1113 15 17 19 21 23 25 27 29 31 33 35 c 968 7 6 c B 7 6 56 240 o t 8 TOPE FCEE 4B BE S216 gt zl la u I 12 750 xd a 5 NONCOMPONENT 57 24001 l l12uHyT 75PF SIDE TS 1000 COMPATIBLE TIMING 1 DIFFERENT 9 CHROMA OCS OUT INA148x10 5 COMPONENT SIDE Y2 TDK BEAD SN S ul 5 z s R44 m t E e Z y A9 8 o pu TME TE LUMBER SKFEREERREREEELLELLELLCLUPLELPEREE 2N3904 A V CHROMA LAG 1 2 3 4 5 6 7 8 9 101112 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 BA 2 3 4 5 6 7 8 1011 VA OM QNO E A RAR PIB 31 CHROMA LEAD gt gt of m qi a b m 2 of al oj
73. 7 80 10 10 Example 2 fT 100 Hz fCLOCK 1 76475 MHz 6 TP 1 76475 10 10 2 1103 16 1x10 Substituting this result into equation b CT FT 1103 10 10 4 79 256 256 205 resulting in CT 4 0100 83 80 10 10 79 01001111 87 80 10 10 FT 22 2 1 6 2 Noise Generator Control Register R6 The frequency of the noise source is obtained in the PSG by first counting down the input clock by 16 then by further counting down the result by the programmed 5 bit Noise Period value This 5 bit value consists of the lower 5 bits B4 BO of Register RO as illustrated by Figure 2 1 6 3 FIGURE 2 1 6 3 NOISE PERIOD REGISTER R6 B6 Bd B4 B3 B2 BO NOT USED 9 BIT NOISE PERIOD NP TO NOISE GENERATOR Note that the 5 bit value in R6 is a period value the higher the value in the register the lower the resultant noise frequency Note also that as with the Tone Period the lowest period value is 00001 divide by 1 the highest period value 15 11111 divide by 31 10 The noise frequency equation is fN fCLOCK 16 NP 10 Where fN Desired noise frequency fCLOCK Input clock frequency NP Decimal equivalent of the 10 Noise Period register bits 84 80 From the above equation it seen that the noise frequency can range from a low of fCLOCK 496 wherein NP 31 10 10 to a high of fCLOCK 16 wherein 1 Using a 1 76475 MHz 10 clock for example would produce a ra
74. 71 272 273 274 275 276 277 278 277 246 247 228 249 230 231 232 233 234 2395 236 237 238 239 240 241 242 243 244 245 246 247 248 249 291 253 254 255 256 297 298 299 260 261 262 263 264 265 266 267 RUB CCt CR_CC NL t SLUG FORECC STY_KCt FSH KCt LOL KC1 HIL KC NLV_KCs INV KC CSL_KC TM_KC GRM_KCr BG SPACEt QUOTE DOLLAR COLON COMMA KET ERROR WRCH t IGN SP NXT IS CALCTRt COP YUP 1 NOSIZE DIGIT LETTER DEBDEL1 COM CC EDT CC BS_CC CRT CCt1 CD CC CU CC RUB_CC CRCC NL SLUG FORECC ATCC _ STY KCt FSH KCt LOL KC NLV LKC INV KCt EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQUI EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 49 CONTROL O0 p GQ N OEH OFH 10H 19H 4 ene 7 26 we RESTARTS 16 24 32 48 0 y 1 L RUBOUT CARRIAGE RETURN NEWLINE PRECEDES 5 BYTES OF SLUG FOREGROUND THE CONTROL CHARS FOR FORE BACK FLASH BRIGHT INVERT amp OVER ARE CONSECUTIVE IN THAT ARDEP PRINT AT PRINT TAB CHARACTERS RECEIVED FROM KEYBOARD STEADY FLASH LOWL IGHT HIGHLIGHT NORMAL VIDEO INVERSE VIDEO CAPS SHIFT LOCK TOOGLE TO
75. 85 120 1207 208 1209 1210 1211 1212 1213 1214 121 1214 1217 1216 121 1220 1221 m CB_NC 1 CR NCZ2 t t CALLS t DIRECTION RLF LENGTH DES T ADDR SKC _ADLIR DEST_BAN ERC JEANI ADD ADD LD JR INC ADD pec CALL FUH LLR Ex INC LU LD Lo INC LE INC Lt PLUSH POF POF FET EOL EU EQUI EGLI EQU EQU SP 1X Ix DE FARR IX FRMLOUT B 1 _ 14 A C CB NCI B DE IX SAVE_STATUS IX O Ix SP IX HOR SEL IX BANK BANK ENABLE AF BC LE HL IX IX 1X MP IX OF BC DE HL IX BS SP C IX Ix B 1X 1 BS_SP IX 1 0 Ix 8 a cC C NC CB NC2 B 1 BC IX HL RES PORE STAES 1 DE HL HL SF HL Ix C IX RS SF IX EC IX HL DE Bc 1 HERE ARE SOME EQUATES WHICH ARE USED ODDS BHC PUE HL NOW CONTAIN DEST RL t POINTERS FOR BLOCK MOVE DC _ 14 MAKE ROOM FOR BANK STATIS tix DE PARMS FOR BANK ENABLE TENABLE DESTINATION BANK RESTORE REGS t TRASH PARMS CALL_BANK AND GET ADER CALL ADDRESS IN IX 1 SAVE REGS PRM IN OFF BS STACK UPDATE BS SPF PRM IN 3 JIX a PRMLIN 3 IHL ERC FOOINTER FoR oc MWE TRESTORE S
76. 93 937 938 939 240 941 42 243 744 94 946 47 742 24 951 ona ot3 254 ett a lt 7 7 2 1 4 2 Vea ect 7 67 ses 70 971 ore lt gt 974 476 97 77 97A 67 ee 922 ce o24 ORS CRI gt 50 91 e92 54 697 oon cc 160600 1601 10602 1002 1004 1 6o0 1007 x 36011 1012 1017 1014 017 1016 1037 1018 1019 1020 1021 _ _ NTDOCK EC NTEXT BE HOME BE_EXIT SAVE ETATU LOOF LD AND LD LD CALL LD P USH LD CFL LD CALL LD AND LD JR IN RES OUT Ln CPL OUT Lp IM KLA RR PRA BIT RES IN SECT CHIT CFL LU LI CF OR CFL CHIT KIT AK 1 RES CRIT IN RES CHIT LI N LL Li CALL LD WC CPL LD CALL FOF FOF POF POP FISH IN LI IN LD INC Lf LD LD CALL 144 OBS MAXLBANKO LARGEST BANK NUMBER A 2 BE SKIP D BNA O WRITE BS REG D HSP NO EXP BANKS WRITE BS REO OFF APPROPRIATE BITS OF f ALL EXP BANKS A B NI BE NTDOCK A C OFFH 1 BE EXT OK HR XPT 7 HREXPT A C THERE FOR DOCK DKHSPT A TEN
77. ABLE DOCK BE EXIT A B OF EH 1 BE NTEXT HREIPT t CHECK IF EXT FOR EXT A 7 HZ A TIwHSPT a fu HEFT EC EX1T Irrt _ DPT tDISARLE ICKY E UDKHSFTO 1 EFE_CH HOME A HREXPT HREXPT Dr HSf T o OF FH 7 BE_EXIT D RNA B WRITE Rt REG HE A C DISARLE EXT IF HOME 11 HOME SO DONE WRITE NEW EXP STATUS WRITE BS REG HL RESTORE REGISTERS RAR SAVE BAM STATHUSES STATUSLADDRI IX PUSHES THE STATUS CF ALL BANKS ON THE STACK 1 SAVE REGS tSAVE EXT STATI LEAVE FITS 0 4 ALONE NOES FUT IN TG FEEF ADDRS THE SAME t X tx fi DKHSPT TOET DOCK BAW STATUS IX A Ix A BS MAX BAME 1OET NUMBER OF BANE S 1 SSe EXIT E SET UF COUNTER E B t BANK NUMBER INTO E OET STATUS STATUS OF amp 2C 207100 1022 Lt Ix C eS zf 1023 INC 1 4 41 43 1074 LD etr 1 OF 4 102 UNZ LOOP 100 FOR ALL 2544 DD2R 1026 SS LEXIT CEC 1 e 544 Ci 1027 FOF te RESTORE REGS 69347 C1 1028 FOP BC e 4 amp F1 1029 or OF 4349 C9 1030 1931 t 1022 t 1033 1 RESTORE BANK STATUSES STATUS ADUR IX 1034 t 1035 RESTORES BANK STATUS TO ALL BANK
78. B2s 483 SLA L 6210 CR14 484 RL H tH 24H SOIE A7 42 AND A amp 21F EDS 426 SBC HL DE I COMPARE HL AND DE 4221 301 497 JR NC D EXT DE lt HL 4223 211200 4en HL LAST_RAN_SVC ELTA CRZS 429 SLA L 622 Bi 4 49C RL H AZZA A 491 AND A 228 EDS2 492 SBC HL DE 6220 493 JR cC D HOME amp 22F OAFF 494 LD 255 HERE FOR RAM BASED SERVICES amp 231 CRSA 495 CALL GET STATUS STATUS OF HOME BANK 6234 AFF 496 LD B 25 BC HOME BANK HORIZ SELECT 236 19804 497 JR D SAVE 6238 OAFE 428 D EXT LD B 254 I HERE FOR EXT ROM BASED SERVICES 622A DEFE LD OFEM 423C 1304 JR D SAVE 422E OAFF 01 D_ HOME LD 255 1 SET PANK ENABLE PAKMS FOR HOME 6240 102 LD cC 0 6242 FS 503 D SAVE PUSH AF 4243 PUSH BC I SAVE JUMP FLAG AND BANK_ENABLE PARMS 4244 21FF1F sos LD HL CALC ADDR OF TABLE ENTRY 6247 37 504 SCF 4282 0152 507 SRC HL DE 4244 OSFE 508 LD B 254 624 CD1663 so CALL WORE TREAN TABLE ENTRY amp 24F EB 510 EX DE HL amp 250 C1 511 BC 6251 F1 512 AF tRESTORE JUMP FLAG ETC 5252 513 AND 6253 2281F 514 R 1 D_CALL 2254 DO71FE 51 LD 1 2 BANK AND HOR SEL ON STACK 6253 DO7OFF 515 IX 1 B OLE OG S17 L IX t AVE RET ADDR 62E 065401 518 LD IX 1 6261 207403 Si LD 1 3 H ADOR RACY OM STACK 139 2664 007302 52 IX 2 L 24 7 DL 201 gt Lo Ix 1 D tZET STA
79. B6 B5 B4 B3 B2 B1 BO Ar n NOT USED d TELL TEILO TES TP7 6 5 TP4 2 TPO 20 2 1 6 1 continued The equations describing the relationship between the desired output tone frequency and the input clock frequency and Tone Period value are a fT fCLOCK b TP 256CT FT 16 10 10 10 Where fT Desired tone frequency fCLOCK Input clock frequency TP Decimal equivalent of the Tone Period 10 bits TPII to CT Decimal equivalent of the Coarse Tune 10 register bits B3 to BO TPI to FT Decimal equivalent of the Fine Tune 10 register bits B7 to BO TP7 to TPO From the above equations it can be seen that the tone frequency can range from a low of fCLOCK 65520 wherein TP 4095 10 10 to a high of fCLOCK 16 wherein TP ES 10 The TS 2068 uses a 1 76475 MHZ input clock so it can produce a range of 26 9 Hz to 110 kHz 21 2 1 6 1 conti nued To calculate the values for the contents of the Tone Period Coarse and Fine Tune registers given the input clock and the desired output tone frequencies we simply rearrange the above equations yielding a TP fCLOCK b CT FT TP 10 T6 f 10 10 10 256 256 Example 1 fT 1 kHZ fCLOCK 1 76475 MHz 6 TP 1 76475x 10 10 3 16 1x10 110 3 Substituting this result into equation 0 CT FT 110 3 10 10 10 resulting in CT 0 0000 83 80 10 110 01101110 8
80. BSV EQU CONST EQU MINUS1 EQU COPY EQU MEMORY EQU OPL LTK EQU HI MON EQU MONOP EQU LONOMO EQU HINOMO EQU LIST ON SGN 1 t ABSOLUTE T gt NTN 5 1 gt PEEK PEEK 1 IT gt IN T IN 1 gt USR T USR 1 gt STR T STR 1 IT gt CHR CHR 1 tT gt BOOLEAN T O NOT NOT 1 t DUPLICATE gt T DUP 1 t INTEGER DIVISION S T gt S MOD T INT S T INTDIV 1 I PROGRAMME CONTROL RELATIVE JUMP BY FOLLOWING BYTE JUMP 1 I STACKS FOLLOWING NUMBER LITERAL 1 ILIKE ZILOG DJNZ LOOP 1 tT BOOLEAN T lt O MINUS 1 tT gt BOOLEAN T gt O PLUS 1 I RETURNS CONTROL TO 280 QUIT 1 T Y WHERE 1 lt Y lt 1 amp SIN T SIN PI 2 Y t MEMORY O t TRUE IF T IN 2ND OR 3RD QUADRANT ANGLE 1 TRUNCATE T gt INTEGER TRUNCATION OF T TOWARDS TRUNC 1 EXECUTES BREG AS A CALCULATOR INSTRUCTION XEQTB 1 gt S 10H8T XEY 1 T FORCED INTO FLOATING POINT FORM THE FOLLOWING COMMANDS HAVE ADDED TO THEM AN GPERAND N 80H t SUMS N TERMS OF CHEBYSHEV SERIES SEE 5 CBSV 20H 9 CONSTANT T gt NTH CALCULATOR CONSTANT CONST 6 CALCTR CONSTANT EQUAL TO i CONST 20H gt Tt T COPIED TO NTH CALCULATOR MEMORY COPY 20H gt CONTENTS OF NTH CALCULATOR MEMORY LO_MON LO_MON TOKEN FOR OPTR C IS OP_TK C OP TK CHR TOKEN FOR LAST MONADIC OPTR EXCEPTING LO_MON OR OCOH t OPERATION CODE FOR LO_MON TOP 2 BITS SET OP_TK SIN TOKE
81. CE Display Enhancement FF 255 11111111 R W 2 1 10 2 1 13 1 Control 2 2 7 2 54 Keyboard Tape 1 0 FE 254 11111110 R W 21 9 22151222 2 4 3 4 1 1 4 2 Reserved FD 253 11111101 Reserved FC 252 11111100 TS 2040 Printer FB 51 11111011 RW 2 1 13 3 4 1 3 Sound Chip amp Joystick Data F6 246 11110110 RAW 21505 eleh 2 4 4 4 3 4 Sound Chip Address F5 245 11110101 W Same Horizontal Select F4 244 11110100 RW 2 1 8 1 Register 2 1 13 2 Keyboard Tape 1 0 Port FER Port FEH is used to input Keyboard and Tape data and to output Border color Tape data and Sound BEEP tones READ IN 07 D6 DS D II le d KEYBOARD INPUT DATA See 2 1 9 I NPUT See 4 2 Used Set to 0 50 WRITE OUT D D D3 r nr o NOT USED BORDER COLOR 000 Black 001 Blue 010 Red 011 Magenta 100 Green 101 Cyan TAPE 110 Yellow OUTPUT 111 White See 4 2 SOUND BEEP OUT 2 1 13 3 TS 2040 Printer Port 1XXXX0XX The TS 2040 Printer peripheral is written to and status read from via OUT and INinstructions with Bit 7 1 and Bit 2 0 other bits are not decoded by the printer READ IN NOT USED Ready for Next Pi Printer Not Configured Start of Paper WRITE OUT L wor USED otor Speed Select 0 Fast Slow Motor ON OFF 0 ON OFF Pixel to Print 0 None Bl ack 2 1 13 4 Sound Chip amp Joystick Ports and F6H Ports F5H and F6H a
82. CH THE ADDRESS OF AN INPUT ROUTINE FOR INCH 1 BYTE CODE FOR THE DEVICE amp WHERE APPROPRIATE FILE NAME ADDITIONAL DATA amp BUFFER DATA FOR CURRENT CHANNEL BASIC PROGRAM 2 gt gt gt 2 NEXT LINE OF SOURCE CODE 151 106 107 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 131 132 133 134 151 DATADD E_LINE K CUR CH_ADD X_PTR EQU EQU EQU EQU EQU WORKSP t STKBOT t STKNXT STKEND EQU EQU EQU EQU MEM FLAGSZ ALOS EQU PRLEFT EQU L STR EQU CAPS L EQU RETPOS1EQU DELREP EQU DF SZ EQU 5 EQU OLDPPC EQU OSPPC EQU FLAGXs EQU FLEX EQU UNFND EQU INPLN EQU NO EQU LINPLN EQU STRLEN EQU T ADDR EQU SEED EQU FRAMES EQU FRAME2 EQU UDG EQU COORDS EQU EQU EQU P_POSN _ EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU OREENt BLUEB EQU NXTLIN 2 DATADD 2 E_LINE 2 K_CUR 2 CH_ADD 2 X_PTR 2 WORKSP 2 STKBOT 2 STKNXT STKEND Z BREG 1 MEM 2 N b FLAGS2 1 5741 S TOP 2 OLDPPC 2 OSPPC 1 NO tle FLAGX 1 STRLEN 2 T ADDR 2 SEED 2 FRAMES 2 2 1 UDG 2 COORDS 2 P_POSN 1 PR_CC 2 ECHO_E 2 DF CC 2 DFCCL 2 S POSN 2 SPOSNL 2 SCR_CT 1 1 EQU 2 3 EQU 3 REDBt EQU 4 GREENB EQU 5 HILITE EQU 5 FLASHt EQU 7
83. CK OOTEL RANK 62 40 007 300 La Ix ON STACK 23 Fine tRE TORE REG F Dt 52 pe esc c1 m ror LGH F1 row Ar amp z7 07145 27 BANK HERE IF JUMP FLAG NOT SET 274 Det oo DLCALL Lt t IX EET UF STACI FOR CALL 27 2 uf H CIXNS1 IN PROFER LOC E278 7 4 21 Lf L 1 4 27E ONAN un H 1x45 ezti Dr FE LD Ix 2 L C234 DN74FF 524 Lr IX 1 H 297 DUE 04 25 Lo L TPUT PRM OUT IN PRPER Lo 220 DOGO 534 1 0 H IX 7 amp 2er s27 1 L LIPO 007401 SR LU 1x 1 H 2 017102 lt Lt C tFUT BANI HE ON tT6C 6276 07003 540 LD 1 43 R amp 297 007304 41 1 4 ADDR ON STACI 0067205 542 LD IX 5 Pad TAS POF HL Dpp o 544 LE IX amp L 007407 Tas LD 1x7 H 46 HL RESTORE REGS za D1 47 POP DE C1 548 POP BC 2 F1 49 AF 62AA 5 SSO CALL CALL HERE IF JUMP FLAG NOT SET SZAL 4 41 552 t 3 554 IRST 56 HERE TO SERVICE INTERRUPT BY READING KEYROARD StS AE F S54 INT PUSH 5 S357 PUSH HL DDES s PUSH ATE 210000 SSS LD HL 2E 3 ADD HL SP ELBE DS 561 DE 6257 381563 5 2 LD RV MAX BAN 2RA SF 5 3 LD E A 2 1600 S64
84. Crystal Oscillator 3 579545 MHz Switch SPDT Rocker S 2 Switch Channel Select S W1 1 SPDT Slide Video Jack Insulation Pad 1 Under J Jack Right Angle RCA Video J7 Monitor Jack Jack Mini Phone EAR amp MIC 2 3 Jack COAX DC Power 2 1 2 JI MM Pin Jack Phono J8 Assembled to Shield R F Connector Cartridge 2 X 18 J4 Key between Pin 0 1 Space Contact 486 Connector Flex Cable 14 Pin J 9 Keyboard Connector Joystick 9 Pin Male J5 6 2 Joysticks 0 Type Shield R F Button Shield R F Top Heat Sink Heat Sink Insulation Pad 293 DESCRIPTION ocket n Socket 1 40 Pin Speaker 45 OHM Mylar Cone Jumper Wire Ferrite Bead PC Board Assembl y Daughter APPENDIX D 752008 PARTS LIST continued COMPONENT TY DESIGNATION COMMENTS 2 50 j L5 8 294 APPENDIX E Expansion Buss Comparison of TS2068 Sinclair Spectrum and ZX81 TS 2068 BOTTOM TOP GND GND SPKR TAPE 4 EAR 15 ATR D N C N C PWR GND D PWR GND D CLK 9 D A p A b 2 D A 3 D A B INT AB SI NMI A B SH HALT A Z1 MREQB A 54 ROB A ROB A E24 WRB A BUSAK 24 A 4 BUSRQ 25 RESET A lt 4 MI N 4 RFSHB RGB Red 4 EXROM RGB Grn amp ROSCS RGB Blu BE IO VIDEO 24 SOUND GND SPECTRUM BOTTOM TOP As 5v D
85. D MERGE OPDF IL PASSIN RD BIT RESSCT R EDGE R_ TAPE SAVE SLVM W_BORD W_ TAPE EXTENSION ROM MAP ORIGIN LENGTH 0000 0063 O8E7 ODBO OF 43 OF 8A ADDRESS O9F4 OF 99 OESE 27 08 7 OF9A 95 O6ES ODBO OF43 0189 0130 OOFC 0851 O1AB OOES 0068 0068 037F 4 9 0193 0047 QO1E MODULE TAPE INIT BS CHNG_VID CHNG_VID INIT BS TAPE TAPE CHNG VID PASSING TAPE INIT TAPE TAPE PROGRAM 1000 BYTES ENTRY DISPATCH GLOBAL BANK E BS MAX BS SP CALL B CREATE DISPAT GET CH GET NU GET ST GET WO GOTO B GOTO E INT 1000 ADDRESS 6499 6315 65CE 65D0 66E8 6200 _ 6440 645 6405 6316 6572 6815 62 0624 MODULE DISPATCH DISPATCH DISPATCH DISPATCH DISPATCH DISPATCH DISPATCH DISPATCH DISPATCH DISPATCH DISPATCH DISPATCH DISPATCH ORIGIN TABLES FIXTBL 1000 JMPTBL LEDC UNUSED 1624 1D7C 138 THIS MODULE IS COPIED TO RAM 6200 space reserved 6200 683FH Relocated to RAM F9CO FFFFH when second Display File is used LENGTH 007C 0124 06DC 0160 LOC OR CODE zTMT SOURCE STATEMENT 6 9 4 0 eLIST ON 4 1 LIST CN 4 22 INCLIIDE NEW 5 YSVARTLS 423 1 HERE ARE NEW s STEM VARIABLE LEF INIT IONS 422 1 42 426 STIKS EOU OH 4 SADDPT EDU OF SH SOLUNDAN CHIP ADDR FuRT 42 amp DATPT OF AH t OUND CHIP FORT 42 HS ENI 40H
86. DATA STREAM FOR PRINT STREAM FOR LPRINT 8 20H BYTES BEFORE CHARACTER SET NO CYCLES OF ERROR NOISE 2 SVES BELOW MIDDLE C NO CYCLES OF KEYEGARD NOISE 3 8VES ABOVE MIDDLE C VALUE ALWAYS HELD IN IY TIME ERROR 1 1 VARIOUS FLAGS SUPPRESS SPACE BEFORE TOKENS PRINTING TO PRINTER NOT TV L MODE NOT K AT CURRENT CHARACTER L MODE NOT K AT CURSOR KEYHIT FOUND EXPRESSION 15 NUMERICAL STRING REQ INTERPRET RATHER THAN CHECK SYNTAX FLAGS ASSOCIATED WITH THE TV PRINTING TO LOWER HALF OF SCREEN OUTPUTTING LINE FOR EDIT OR NO FOR STRING ECHO REQUESTED IF INPUTTING FROM KEYBOARD OUTPUTTING AN AUTOMATIC LISTING CLEAR LOWER HALF WHEN KEY PRESSED 1ST 2ND 3RD gt BOTTOM ITEM ON MACHINE STACK 2 RETURN ADDRESS FROM AUTOMATIC LISTING O 1 F 2 OG LINE BE JUMPED TO SUBLINE TO BE JUMPED TO BIT 7 OFF FORCES JUMP LINE OF INSTR BEING INTERPRETED NO WITHIN LINE OF INSTR BEING INTERPRETED BORDER COLOUR SHIFTED LEFT BACKG BITS WITH OS IN BITS 0 2 amp 6 7 LINE OF CURRENT LINE IN LISTING THE VARIABLES FROM VARS UP TO amp INCLUDING STKEND ARE MOVABLE IN THE SENSE THAT THEY ARE ADJUSTED BY REMGSZ IN MODULE EDIT WHENEVER STUFF IS INSERTED IN OR DELETED FROM RAM 1ST RECORD FOR VARIABLE LAST IS 1 BYTE 80H VAR MATCHED BY TEMPL CODE 1 OR 4 TEXT OR RECORD CHANNEL DATA INCLUDING FLOPPY BUFFERS EACH ITEM COMPRISES THE ADDRESS OF AN OUTPUT ROUTINE FOR WR
87. De d B L 2 CH_NE1 Z B CB_NB2 B XFER_BYTES LENGTH CALCULATE ENT ADDR PIF lt O sGET END CHUNI BIT SET START HIT SHERE IF START AND ENC CcHUNE SI ARE THE ZAME SFT START AND RITE TOGETHER FILL IN THEM WITH ZEROES NEXT OTHERWISE FOUND FIRTT ZERG NEXT tFOUND LAST ZERO OTHERWISE UPDATE BITMAP RETURN DEST ALOR SRC_AUUR LEST BANK FASZED ON STACK IN ORDER CHOWN STATUS COLE AF BC HL HL HL SP DE 10 HL DE UE HL A BS_mAX 147 ALL PARAMETERS ON STACK HAVE OFFSETS DEFINED AROVE f TAVE REGS POINTS TO START OF FARMS BANt 470 8 c 765 e7po CTOs 714 47017 70 amp 7 08 67 LE A7E 7 1 7 2 AFE 47E6 lt 7 amp 7EC 7ELD 67EE e7EF 7F lt 7FS 4F GO CO 2l0000 re A Eras 28 ak E COE 1 LOLESAS ODE 1 CUES FS D 06E04 54 4F F1 47 DD7EO9 00 4503 BA 2005 78 A1 47 1898 74 R1 FEFF 2020 a 42 CD v64 004569 48 CD9944 DOSE O4 006407 04 007605 DD4EOQO2 004603 OD7EOO 07 OF 3204 EDBO 1252 EL R 134 217044 gt CAFF C01543 C1 110002 a7 EDS2 142000 19 SAHM 13 A7 EDS 3604 TEE
88. E HL L CIX BUF H CIX BUF_PTR 1 HL DE IHL PTR BUE 52 F r SRESTORE STACY FOINTER 4 RETURN CODE FOR SUCCESSFUL COMPLET LUN 1 O IX SF RESTORE STATUS 4 STATE AND RETURN ZERO COLE 67F amp 7FA 67 7Ft FE 6804 GRO e coa amp amp GA e coc ELE 6510 612 E14 6817 4216 681A 661C amp S1E 520 522 223 Lec 1D60 ipo 1102 1004 100004 1Doz 1 COA 1 LCC IDOE 1010 3812 10 4 1114 10412 1 Jl dC 1020 tuz 10 4 30126 1 CLE IDE j DL 23 DODF Iu C1 F1 Dre 1 DLE 5 DDE 1 UDE 3 DDE 1 2 DDOE 1 LLE OPE 1 DUE 2 FS DEFF CBFF D3FF 3 01 DFA Fi ES 1423 1424 1425 142 1427 1426 1429 1430 1431 14 2 1433 1434 1435 1436 1437 1436 1439 1440 1441 1442 1443 1444 144 1446 1447 1446 144 1450 1451 1452 1453 1454 GB CODE M STMT c 404 2 726r ABAZ BS 2 CD42 DIAZ FR 1 244 ZAG ut h D 9 ee v MR e s t GOTOLEKTLINIT t t AN CAE T FIXTBL SOURCE STATEMENT LMI FATIH INT GET WORD FIAT GET GET NUMBER ENABLE SAVE TATLU RESTORE STATIS R STALE BL GOTO BANE CALL BANE MOVE BYTES CREATE _
89. E IF 25 6430 A7 1 411 soir 6184 JR 2 tIF RAN 41 1420 815 Ln D BNA HERE IF EXP BANK CRIS e 814 LT E E 6416 COSCE 817 CALL WRITE_BS_REG 41 7 1646 Ln D HO_LLSN At ft 1E 81 LD HS MSN 142 411 HAD 44 422 6423 EATS 6427 642A 42R 4 D 6452 4428 6 42 AARE amp amp xz 64 4420 6 4 gt 64 F 440 lt 441 6 443 6444 5444 4447 4 442 4444 4 448 LAAL 448 amp A4F 471 6453 45 4 4 5 4457 4 9 443A 545 A E LASF 54 0 4463 464 5457 4444 46B amp 44C 6470 6472 5474 6476 5477 1478 647A 4478 5470 amp 47F 481 4482 4434 6436 4427 498 494 40 4 ag 4490 4492 4 423 5495 5426 4497 Kage 6499 4434 442B amp 43C 49D CAL 1 CIRD 2 43 1D 0160000 1 DEF 4 2t 4 OE KO 1810 DEF F E 2f 07 47 DEF 4 2F Eany P 47 OF n C is 1 BF 10 C aC 47 27 17 1 0 C1 Ds C DALA 291563 A 22089 47 CDO364 Al 2923 19F7 UBF 4 oF Al 2818 4011 DBFF 7 UPF 4 ESO gt 2304 j 02 3EFF 1304 1 01 73 D1 Ci FS c5 ES Ae Gt EXT i 1 T LCHUNI GC SHIFT GC ROLL GET _NUMEER GN CHECK GN RD DOCK GN HOME LD N Dir GN EXP GN EXIT BANK ENABLE DE To n
90. GE AE n F4h Port FF bit 7 Reese NND Select EXROM N Select HOME BANK 37 SYMBOL 0 Al Al 3 A15 00 07 KBO MA7 TS OCPU TABLE 2 1 8 1 SCLD I O PIN FUNCTION DEFINITIONS NAME Address Bus Data Bus Keyboard Outputs A7 Refresh Adrs Bus Tri State Display Memory Ctl Clock to CPU Read Direction Control to SCLD Home ROM Chip Select Row Address Strobe 1 DIRECTION OF SCLD I N OUT In n Out In out out out out out out out 38 FUNCTION Address Bus lines Input from Z80A from to inputs U6 and U7 Data Bus inputs outputs Z80A through 09 7415245 or from display RAM 16K Inputs from 5 lines of keyboard matrix goes low at one of 8 address line active ow sequences on 1 0 Request To refresh and address 8th bit address line input of RAM memory not display of 32K of 4416 RAM Home Bank 8000H to FFFFH Display memory muxed address bus and refresh Tri State control for address and data buffers when CPU is address ing display memory at same ti me display controller is addressing the display memory Clock to Z80A CPU which is interrupted to stop CPU when CPU wants to address display RAM at same time as display controller To control read write direction of 7415245 Data Bus Buffer be tween CPU and SCLD To activate the 16K Home ROM first 16K when memo
91. GETHS Get Hor Select GS DOCK LD C OFFH Assume none IN A OFFH Test if selected AND 80H JR NZ GS XT1 Not active GETHS IN 0F4H Get Hor Select Reg CPL Invert to Low Active JR GS 0 Exit GS HOME IN 0FAH All bits set are not active in Home Bank GS 0 LD C Memory Select to GS XT1 POP DE Restore Regs POP AF RET Return for BASIC 131 See next page for list of FIGURE 6 5 1 GET STATUS CORRECTI ONS continued From BASIC POKE 25610 40 25611 36 25614 40 POKE 25615 55 POKE 25617 40 POKE 25618 39 POKE 25648 14 POKE 25649 255 POKE 25650 219 POKE 25651 255 POKE 25652 230 POKE 25653 128 25654 40 POKE 25655 18 POKE 25656 24 POKE 25657 8 POKE 25658 14 POKE 25659 255 POKE 25660 219 POKE 25661 255 POKE 25662 230 POKE 25663 128 POKE 25664 32 POKE 25665 8 POKE 25666 219 POKE 25667 244 POKE 25668 47 POKE 25669 24 POKE 25670 2 POKE 25671 219 POKE 25672 244 POKE 25673 79 132 Location 640AH Location 640EH Location 6411H Location 6430H xoxo FIGURE 0 5 2 PUT WORD CORRECTI ONS LOCATION lL SOURCE STATEMENT COMMENTS HEX 6338 633C 633D 6340 6341 6342 6343 6346 6347 634A 0348 634C 634D 6350 6351 6352 6353 6354 6355 6356 6359 635A 6358 The asterisks From BASIC NOTE POKE POKE POKE POKE POKE POKE POKE The 25408 213 25424 193 25425 209 25426 115 25427 35 25428 1
92. HEN STRING TYPE gt NEXT BYTE IN TEMPLATE LAST RANDOM BEFORE SCALING 6 2 BYTES 3 BYTE FRAME COUNTER MS BYTE OF 3 BYTE FRAME COUNTER gt 1ST USER DEFINED GRAPHIC COORDINATES OF LAST PLOT 1 COORDS 1 Y COORD COLUMN NO OF PRINTER POSN LS BYTE OF ADDRESS OF NEXT CHAR FOR PRINTER COORDS IN LOWER HALF OF END OF KEYBOARD INFUT BUFFER gt SCREEN CHAR UNDER PRINT CURSOR LIKE DF CC FOR LOWER HALF SCREEN POSN COL amp LINE OF NEXT CHAR TO BE OUTPUT LIKE S POSN FOR LOWER HALF SCROLL COUNT DECREMENTED FOR EACH SCROLL CURRENT PERMANENT PRINTING ATTRIBUTES LS BIT OF FOREGROUND COLOUR COORDS X COORD LS BIT OF BACKGROUND COLOUR PAPER BRIGHT FLASH CURRENT PERMANENT PRINTING ATTRIBUTES MASK O FOR NEW 1 FOR OLD CURRENT TEMP PRINTING ATTRIBUTES BITS AS ATTR P CURRENT TEMPORARY PRINTING ATTRIBUTES MASK ADDITIONAL FLAGS FOR PRINTING TEMPORARY FLAGS IN EVEN BITS PERMANENT FLAGS IN ODD BITS NEW CHARS XOR D INTO OLD RATHER THAN BEING LOADED NEW CHARS INVERTED FOREGROUND COMPLEMENT OF BACKGROUND BACKGROUND COMPLEMENT OF FOREGROUND BOTTOM OF CALCULATOR MEMORY 6 NUMBERS gt USER S NMI SERVICE ROUTINE LAST ADDRESS OF BASIC SYSTEM AREA gt LAST BYTE OF PHYSICAL RAM 152 177 178 179 180 181 182 183 184 185 186 137 188 189 190 191 192 193 194 195 196 197 199 200 201 202 203 205 206 207 210 211 212 214 215 216 217 218 219 221
93. IN AL c40 1 LOW ESR Electrolytic Axial CAP 1000 pf 50V MIN FILM C36 tl 20 MYLAR CAP 100 uf 10V MINAL Elec C58 67 2 trolytic Axial CAP 6 50 pf TRIMMER C5 18 2 NPO CAP 0 47 uf Ceramic Axial C60 20 80 or GMV TEMP 75 CAP 33 uf TANTALUM 71 1 20 290 DESCRIPTION 68 pf Ceramic Axial CAP CAP RES 300 OHM RES 200 OHM RES 100 OHM RES 240 OHM RES 68 OHM RES 680 OHM RES 390 OHM RES 1K OHM RES 1 5K OHM RES 1 8K OHM RES 620 OHM RES 2K OHM RES 3K OHM RES 2 2 OHM RES 110 OHM RES 510 OHM RES 5 1 OHM RES 10K OHM RES 13K OHM RES 20K OHM RES 62K OHM RES OOK OHM RES 220K OHM RES 75 OHM RES 1 10K OHM RES 3 32K OHM RES 10K OHM VARIABLE RES 330 OHM 0 5 0 RES 56 OHM 1 4W RES 0 110 OHM Wire Wound RES 20 OHM 1 4W RES 82 OHM 1 4W RES 22 OHM 1 4W RES 680K OHM 1 4W RES 47K OHM 1 4W RES 390K OHM 1 4W l RES 6 8K OHM 1 4W I 1 4W E a 8 oun clc KL gt H n B g E E SS 24 pf Ceramic Axial 47 pf Ceramic Axial 5 5 5 5 CF CF CF CF CF CF CF CF APPENDIX D 752008 PARTS LIST continued COMPONENT DESIGNATION c o c29 27 C28 R23 R19 50 54 55 R58 R24 28 56
94. KEN MODE GRAPHICS MODE FOREGROUND BLACK BACKGROUND BLACK STRING QUOTE DOLLAR SIGN OF BYTES IN FLOATING POINT NUMBER DIGIT N IS CODE FOR DIGIT N LETTER ALPHA IS CODE FOR LETTER ALPHA NO CONSECUTIVE TIMES KB SWITCH FOUND OPEN BEFORE KEY RECKONED RELEASED CONTROL CHARACTERS APPEARING CIN STREAM OAH OBH OCH CR CC OEH 10H 16H 17H we we lt CONTROL gt a x lt PRINT COMMA EDIT BACKSPACE CURSOR LEFT CURSOR RIGHT CURSOR DOWN CURSOR UP RUBOUT CARRIAGE RETURN NEWLINE PRECEDES 5 BYTES OF SLUG FOREGROUND THE CONTROL CHARS FOR FORE BACK FLASH BRIGHT INVERT amp OVER ARE CONSECUTIVE IN THAT ORDER PRINT AT PRINT TAB CHARACTERS RECEIVED FROM KEYBOARD STEADY FLASH LOWLIGHT HIGHLIGHT NORMAL VIDEO INVERSE VIDEO 154 268 269 270 271 272 273 274 275 276 277 278 27 280 231 282 283 284 285 287 289 290 291 293 294 295 296 297 298 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 322 323 324 325 326 327 328 330 331 332 333 334 335 336 337 338 339 340 CSL KCt EQU EQU GRM KCt EQU FG_KC Eau BG_KC EQU SPACE t QUOTE DOLLAR COLON COMMA KET BRA GT MINUS EQUAL EQU PLUS EQU STROKE EQU EQU POINT EQU SHARP EQU STD_GR EQU
95. L If Line found returns Z and Address of Line in HL else returns NZ and HL contains either address of line with next larger line number or points to the Variables area if there is no larger line number Requested Line No returned in BC and Address of Preceding Line in DE DEzHL if no preceding line Finds either the D th statement D Statement 0 or lst Statement whose keyword token matches E D 0 in a line pointed to by HL Ifthe D th Statement is found returns Z and HL and CH ADD both point to 1 byte before statement If i ne contains exactly 0 1 statements then the next line counts as the D th If match on E is found then returns NZ NC and both HL and CH ADD point to keyword D is decremented by the number of statements looked at e g D 2 if two statements If no match on E then returns NZ C with both HL and CH ADD pointing to End of Line byte 0DH SERVICE DELREC PUT BC SYNTAX EXCUTE FOR STOP NEXT READ DATA RESTBC RAND TABLE 3 3 4 2 TS 2068 FUNCTION DISPATCHER SERVICES conti nued SERVICE CODE 55 3 H 56 57 98 99 60 61 62 63 64 65 66 38H 39H 3BH 3CH 40H 41H 42H 81 DESCRIPTION Returns in BC the length of the record pointed to by HL Sets DE to HL BC The record can be a program line or a string or numeric variable or array Delete record pointed to byHL
96. MS amp PRINTER BUFFER CLEAR SCREEN amp OUTPUT OS RAM CODE TO CHUNK 3 t s P EXTENSION ROM SET MAX ADDRESS 64K witch to Home Rom To LROS Start ADAS To Basic interpreter To BASIC AROS Support Code J Switch to Extension 1 1 3 Cartridge Software Overview The TS2068 supports two basic types of Cartridge or ROM Oriented Software designated as LROS Language ROM Oriented Software and AROS Application ROM Oriented Software which pluq into the cartridge connector They are identified via overhead bytes at Location 0 for an LROS or 32768 8000H for AROS The fundamental difference is that an LROS contains 280 machine code in memory chunk 0 and is in total control of the 752068 hardware i ncl udi ng the RESTART implementation and Interruption Mode setting and handling while an AROS is dependent on the System ROM or an LROS for these functions if needed An AROS written in BASIC which may also include machine code accessed via the USR function is supported from the System ROM BASIC Interpreter and is mapped beginning in memory chunk 4 An AROS may also be written entirely in Z80 machine code An AROS written in any other high level language would require an LROS supporting that language and would have to be integrated with the LROS in a single cartridge See Sections 3 2 1 2 BASIC AROS Support and 5 1 Cartridge Hardware for addi
97. N FOR 1ST NUMBER NUMBER OPTR AFTER OP_TK USR TOKEN FOR LAST NUMBER NUMBER OPTR 157 APPENDIX C The entirety of Appendix C pages 158 to 287 has been excluded primarily because of its length and because of the poor print quality My OCR software would not accept it and including these pages as images would unacceptably expand the girth of this file Appendix C 1 Assembly source to support the 64 column mode Appendix C 2 Assembly source to support 80 columns in the 64 column mode Appendix C 3 Assembly source to support 40 columns in the 32 column mode Appendix C 4 Assembly source to support the dual screen mode Appendix C 5 Assembly source for sprite graphics in the 32 column mode Much of this software is still bugged Appendix C 5 was debugged and eventually released as Sprites 2068 by a third party Timex of Portugal also released Basic 64 which supported 64 80 128 column text and BASIC graphics commands CIRCLE DRAW etc in the 64 column mode though written for the TC2048 and therefore must be run using a Spectrum emulator on the TS2068 A third party released OS64 on cartridge an expansion to BASIC that allowed it to operate in the 64 column mode TOLON CR182711 version 13 36 16 T Way cM4 151910 Lew level 1 3 module 10 0 SRC a Reserved atrerr 534 AYTTR amp tec ATTRIP 90 5 Rotor ved Reserved 414 CALCA1 6422 CALCPO agar CHARSET 3c 90 Cure 190 CONVPM 990 CURPCS 899 0 Reserved O
98. NS 1 Each entry has the following format Output Routine Address 2 Bytes Input Routine Address 2 Bytes Device Specification 1 Byte This table is copied from CHINIT in module EDIT of the Home ROM The last byte of the table contains an 80H which will immediately precede the first line of the BASIC Program PROG Whenever an 1 0 operation is performed the appropriate Channel is selected i e its number is used as an index into STRMS to obtain the offset into the CHANS table This offset is added to 92 CHANS 1 and the resultant pointer is loaded into the System Variable CURCHL for use by the next character 1 0 operation WRCH RDCH device specification from CHANS is used to find and execute the initilization routine in SELTAB C SELTAB The Select Table is located in the EDIT module of the Home ROM and contains offsets to device dependent initialization routines for the standard devices S and P D SPEC T The Specification Table is located in the CHANS module of the Home ROM and contains offsets to device dependent OPEN routines for the standard devices 5 and It is accessed whenever an OPEN is executed E CL TAB The Close Table is located in the CHANS module of the Home ROM and contains offsets to device dependent CLOSE routines for the standard system devices K S and It is accessed whenever a CLOSE is executed The following sections describe the standard system 1 0 devices
99. NTAX LIST SLMS SYNTAX SYNTWO NOUT I NOLUIT EXPRN EXPRN EXPRN GRAPHS EXPRN AROS I DENT EDIT GRAPHS SYNTAX SYNTWO SYNTWO EDIT I NCIUT EDIT SYNTWO EDIT ID 2 EDIT FUNCTS FUNCTS IN_K SEQ JUMP K_ BASE K CLS Kao DOMP K LIST K LLST KNEW Kk PRIN K SCAN LCU2 LDDE LOMES LDTVCU LE3 LED18 LED4 LET LINENG LIST LN LPO 54 ET22 MOVE MULT NEW NEWDEV NEXT NEXTCH NEXT L NOTKB NXT HL OPCHAN OPEN OPTNO OUTPUT FAEDCB PARP PASSEM PALISE PHLAF PLOT PLOTBC PLUG IN PGPSTR PRSCAN FR CUR PR TV2 PSHSTR PUT FUTDIG PUTMES PUT BC PUT LN PUT SR P NL _ RAND ROCH READ RECLEN 2259 EH 1EF1 OTSE amp QA02 1545 1541 21 5 0010 2159 OZRO 1 22D 3130 3CA3 OOIT OEZF OESD ZERD 1768 14E1 2R2E 1 1 44 1 ADO 3468 0077 2220 0032 2402 105 0074 1658 2250 ath 1465 142A 1249 2101 2 74 2 9 1FEB OQAF 26 35 263E 0000 ZFAF 1620 0776 2E70 15C9 11 7 1788 1795 15041 0566 09 94 217 277 1 ED4 11 1097 1720 EXPRN 10 2 SYNT SYNTAX K SCAN Im IG_2 LIST LIST SYNTWO EDIT SVNTWG KSCaN EDIT NWIT TAPEMSIG 1021 BASIC EDIT EDIT DENT LIST LIST FUNCTS LIST SYNTaX SYNTaX SYNTWO SUMS BASIC CALC EDIT SYNTWU SYNTAX 1527 REMGSZ RESET HESTBC RETURN RND ROOM ROOT RSET
100. OA 19 B EN Out Data PORT D7 ADORESS 04 Z D E 3 a 06 07 DATA BU S lt P gt lt a 45 FIG 2 1 10 1 DISPLAY FILE ORGANIZATION NORMAL MODE 32 BYTES 32 BYTES 32 BYTES LINE 0 k LINE 1 N E 1000 200T 401F 4020 FF T AOEOTAOET F n 411F 4120 as SS AMET 4201 421 F 4220 42 0 42 1 42F F 4301 431 F 4320 433 Fl 43E0 43El 43F F 4401 441 F 4420 A4EO AMET 44F F 4501 451 F 4520 45E0 45E1 45F F 4501 46 F 4620 46E0 46 1 46F F 4701 47 F 4720 47 0 47 1 47F F CHAR CHAR CHAR TAR CHAR HAR POS POS POS POS POS POS 0 0 0 1 0 31 7 0 7 1 7 31 32 BYTES 32 BYTES 32 RYTFC 5 scan L 1 4901 0 2 4A01 C 3 4B01 K 4 5 1 6 7 POS POS POS POS POS POS 8 0 8 1 8 31 15 0 15 1 15 31 32 BYTES 32 BYTES 32 BYTES LINE 7 oe 511 5120 5201 521F 5220 5301 TE 9901 4 4 TE 55 0 55 1 9601 56E0 56 1 57E0 57E CHAR CHAR POS POS POS POS POS POS 16 0 16 1 16 31 23 0 23 1 23 31 46 2 1 11 Video Generation 2 1 11 1 Composite Vi deo The U V and Y siqnals from the SCLD are supplied to the LM1889 and associated circuitry to produce composite video and modulated RF T
101. P2BC Error B if number out of range CLEAR 711 47H CLEAR command Processes parameter on Calculator Stack to value in BC for CLR CLR BC 72 48H Value in BC is new RAMTOP Deletes Variables clears screen and Calculator Stack etc 60 SUB 13 49H GO SUB command Inserts a 3 byte 60 508 Block into the machine stack above the 2 most recent entries The Block consists of current Line No 2 bytes and Statement No 1 byte to be used when RETURN is executed Then calls JUMP to process GO SUB parameter and returns At return to caller machine stack consists of top of stack at point GO SUB was called followed by 3 byte entry Line MSB Line No LSB Statement No 82 SERVI CE TABLE 3 3 3 1 TS 2068 FUNCTION DISPATCHER SERVICES SERVICE CODE continued DESCRIPTION 57 H Checks if room for BU 89 50H RETURN PAUSE BREAK DEF K LPR K PRIN P SEQ NPUT 15 16 11 18 19 80 81 82 4CH 4DH 50H 51H 52H 83 bytes between STKEND RAMTOP Addition of 80 bytes is left over from Spectrum to guarantee minimum machine stack Where the stack was at the top of RAM Error 4 if not enough room RETURN command Retrieves most recent GO SUB Block from Machine Stack SP 4 loads data to NEWPPC and NSPPC and returns Error 7 if MSB Line 3EH End of Stack Marker PAUSE command
102. R TAPE routine Register DE must contain the length of the block to be read DE 17 for the Header and DE HDLEN for Data See Fig 4 2 1 for a definition Or HDLEN 103 PROGRAM FIGURE 4 2 1 TAPE HEADER FORMATS TT wowane io 1DADL ADV Ak 0 up to 10 Length of Starting Length of Pro ASCII Chars Program Line No gram Offset Variables or 8000H to Variables LINE E G VARS PROG PROG 0500 Line 5 or 0080H if no Line No NO ARRAY Length LSB 00 A 0 Field from ID Data 0 Structure 100 x xs ASCII 60H CHAR ARRAY 2 E Length LSB 00 N A 0 Field from MSB Array ID Data 0 Structure LIO a we se Y ASCII 60H CODE BINARY 3 Length Address N A 0 Specified Specified in SAVE in SAVE 4 3 Joysticks The two joysticks are controlled via Register 14 1 0 Port A of the Programmable Sound Generator Chip see Sections 2 1 6 and Il Address and data are passed via Ports OF5H and OF6H respectively The joysticks are read by first addressing Register 14 in the PSG by writing a 14 OEH to Port OF5H The data is then read by executing an IN from Port OF6H having the port address in 280 Register C and the joystick player number in Register B number 1 or 2 Note that PSG Register 7 Bit 5 is assumed to be zero enabling 1 0 Port for input If you ever use 1 0 Port A for output Bit 6 prior to any input operation 7 6
103. REA BANK ENABLE EQU 6499H CALL BANK EQU 6 5DOH 62 EQU DRIVES 6000H DESTZ EQU OFFFFH MOVE SZ 1 FIX EQU DEST7 6000H CALL _VBANK EQU CALL BANK F I X GOTO BANK EQU 6572H ADDRESS OF GO TO BANK BANK SWITCHING AWARD XFER_BYTES EQU 6722H s INDIRECT DATA TRANSFER BETWEEN BANKS GOTOLEXT EQU 6815H 1 INITIALIZATION CODE HOME BANK f EXTENTION SLUM EQU O1LABH SADDRESS OF TAPE ROUTINES FOR SAVE LOAD t VERIFY AND MERGE COMMANDS BLDSCT EQU O9F 4H ADDRESS OF INITIALIZATION ROUTINE BUILD THE SYSTEM CONFIGURATION TABLE RESSCT EQU OCACH 3ADDRESS OF RESET ROUTINE ADD DEVICES PASSING EQU OF OPH ADDRESS OF ROUTINE TO PUSH PARAMETERS 4 THE BEU ROUTINES ONTO THE MACHINE STACK 9 2 2 2 3 GTHER EQUATES sRESTARTS ERROR EQU 6 WRCHt EQU 16 IGN SP EQU 24 1 EQU 32 CALCTR EQU 40 COPYUP EQU 48 NOSIZE EQU 5 OF BYTES IN A FLOATING POINT NUMBER DIGIT EQU 707 t DIGITAN IS CODE FOR DIGITN LETTER EQU f LETTER ALPHA IS CODE FOR LETTER ALPHA DEBDEL EQU 5 NO CONSECUTIVE TIMES KB SWITCH FOUND OPEN BEFORE KEY RECKONED RELEASED CONTROL CHARACTERS APPEARING ON STREAM COM CCt EQU 6 PRINT COMMA EQU 7 EDIT BS cC EQU 8 BACKSPACE CURSOR LEFT _ EQU 9 CURSOR RIGHT CD CC EQU OAH CURSOR DOWN EQU OBH CURSOR UP 153 290 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 2
104. Returns in the bit no 0 7 where O lefthand or most significant bit Error B if Y is greater than 175 PLOT 88 58H PLOT command Processes X Y parameters on the Calculator Stack to BC for plotting of pixel via PLOTBC PLOTBC 09 59H Deals with pixel for coordi nates in BC B Y 5K Processes using P FLAG for Inverse and Over attributes Updates Attribute File and sets COORDSzBC GET XY 90 Converts a pair of numbers from the Calculator Stack to 2 single byte numbers Top number goes to B and second to D sign of B and 5 of C 4l or 1 Used by PLOT and other routines a4 TABLE 3 3 3 2 TS 2068 FUNCTION DISPATCHER SERVICES continued SERVI CE SERVICE CODE DESCRI PTI ON CIRCLE 91 CIRCLE command Calculates Successive plot positions from the parameters in the BASIC statement DRAW 92 5CH DRAW command Calculates successive plot positions from the parameters in the BASIC statement DRAW L 93 5DH Plots a straight line from current position COORDS based on parameters from Calculator Stack X Y EXPRN 94 5EH Evaluates expression in BASIC program line CH ADD putting value on Calculator Stack F SCRN 95 5FH SCREENS function Matches screen line col position parameters on Calculator Stack against standard ASCII character set Returns BC O if no find BC and DE points to Char Code byte if match found F ATTR 96 60H ATTR function Returns att
105. S 1036 3 1037 LDAA FS 1038 RESTORE STATUS PUSH AF 6548 cs 1039 PUSH TAC 1 1040 PUSH DE 64 DOZE 1041 LD 1 EXT ROM STATUS eT usr 1642 43 2 0023 1043 INC 1 6554 Dt 7EO00 1044 LE IX tGET DOCK BANK STATUS 6 37 USF 4 1043 OUT DKHSPT ESTY Dri23 104 inc Ix 3 B 381543 1047 LD BS_MAX BANKIIGET NUMEER OF SE A 1046 ANI 45 2606 1049 JR 1 RS EXIT 361 47 1050 Ln P A t T UWF COUNTER 656 DDAEOO 10 51 00 0 1X 654 5 CD 764 t052 CALL tWRITE BAN STATUS CF 6566 DD23 1053 INC Ix eSen 10F 102 4 lt OCP FOR ALL ESOC ODITE 1035 RS EXIT DEC 1X eet pi POF DE RESTORE REGS EF C 1057 POF BC 6 70 F1 1017 AF 573 C 1057 RET 060 a 1062 1 FAN HORIZONTALL ELECT 6 GN 1680 gt 1041 JO amp 4 4 SETS IE THE DESTINATION ANU OMNES WITHA GE TUN Yur ALB ME C7 1044 IN BANI 1014 7 t 10 2 CST CCS cnim 1069 BANE Lt 1 f To iF 74 DD 22 12720 ALD Ix 4T75 07109 071 LL Jx t SAVE AND TRAacH KET ALF e t tB t 72001 1072 L Ix 1 R QE 107 Lo yel FARM FOR BANK _ ENABLE 64274 D4403 1074 L 1 5 4 C 744 14174 5 A L BANK ENABLE 6527 C1 16024 POP RC tRESTORE AS m DLC 1 1077 1 tTRAZM FARMS TO OCTO LEAN ODE 1 1
106. SEE OR OR 1 fS T gt NUMERICAL S AND T SEE NOAND AND 4 5 gt NUMERICAL S gt T 3 NUMERIC COMPARISON OPERATIONS HAVE NOT BEEN GIVEN MNEMONICS S T gt S T WHERE IS lt m gt gt gt OR 1 SEE CMPRSN AND 7 5 gt S T ADD 1 5 gt S ANDS T SEE STGAND 36 STRING COMPARISON OPERATIONS WITHOUT MNEMONICS STGAND 7 1S T gt 5 6 T ORDINARY OPERATIONS WITHOUT STKDWN CONCAT 1 8 1 USRS 1 INKEY 1 NEGATE 1 CODE CODE 1 VAL 1 LEN 1 SIM 1 COS 1 1 ASN 1 ACS 1 1 LN 1 EXP 1 INT 1 ROOT 1 gt 1T gt VALS T T gt ADDRESS BIT PATTERN FOR CORRESPONDING USER DEF INED GRAPHIC T gt INKEYS 2 T 57 gt CODE T OPERATION CODE FOR LO MON T gt VAL T ITS gt LEN T IT gt SIN T cos T TAN T ARCSIN T ARCCOS T ARCTAN T T gt 7 gt gt T gt T gt LN T gt EXP T INTEGER PART T gt INT T gt SQUARE ROOT OF T IT gt SON T 156 413 414 415 416 417 418 419 420 421 422 424 425 426 427 428 429 430 A31 432 433 434 435 436 437 438 440 441 442 443 444 445 446 447 448 449 450 ABS EQU EQU IN EQU USR EQU STR EQU CHR EQU NOT EQU ZERO EQU DUP t EQU INTDIV EQU JUMP 1 EQU LITERAL EQU LOOP1 EQU MINUS EQU PLUS EQU QUIT EQU ANGLE EQU TRUNC EQU XEQTB EQU XEY EQU FLOAT EQU C
107. ST STANDARD GRAPHIC 1ST USER DEFINED GRAPHIC 1ST TOKEN RND INKEYS PI FN POINT SCREENS ATTRT AT 1ST TOKEN TO REQUIRE A SPACE AFTER TAB VALS TOKEN FOR 1ST MONADIC OPTR AFTER VALS CODE BIN OR NB THE TOKENS FOR OR AND CONSECUIIVE IN THAT ORDER LINE THEN r TO STEP DEF 1ST TOKEN THAT IS A KEYWORD RATHER THAN _ OPERATOR FORMAT MOVE DELETE OPEN CLOSE MERGE VERIFY BEEP ARC FOREGROUND NB THE TOKENS FOR FORE BACK FLASH BRIGHT INVERT amp OVER ARE CONSECUTIVE IN THAT lt gt lt gt ORDER 7 INVERT QUT LPRINT LLIST STOP READ RESTORE NEXT COP Y OUTPUT PORT FOR SETTING BORDER COLOUR 155 341 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 387 388 389 390 391 392 393 394 395 396 397 398 399 401 402 403 405 407 408 409 410 411 412 PR IN EQU PR_OUT EQU EQU O PORT EQU I PORT EQU EQU DKHSPT EQU BDATPT EQU BCMDPT EQU HREXPT EQU _ EQU CHAN_S EQU CHAN_R EQU CHAN_P EQU CH SET EQU EJECT IFJUMP EQU EXCH EQU LOSE t EQU SUB EQU TIMES EQU DI
108. T 747 Lo A OEH ADI CRFS 762 SADDPT amp 3D4 AF 749 XCIR A LADS 770 SDATPT TENDI 771 Lr A 2 SIE SANTO 772 LD LOWNYB A RESET NYBBLE STEERING LOGIC 7 773 LE HL READ LSN OF DATA 472000 tr OF 774 AND OFH aL 4F 77 LD C ATEO ea 77 LD H E 4 361 7E 777 L T HL IREAL MSN CF DATA e 3E 2 27 772 SLA amp EA CED 77E ELA A amp 4 CRZ7 TRO SLA A ETET 27 721 SLA A LEA Ei on OR C SF TE x LI E RETURN BYTE IN E C1 7 4 POP BC e ZE U SEC 785 LD A 7 RESTORE SOUND REGS n zF 784 SADDFT A AEF 1 75 7 7 LI ERFT rear A FRE CHIT SDATFT A PEt LU UEH f Care 7 Cult SADDPT A 7 7 1 LU A amp zF D 3F 4 792 SDATFT A r1 792 For AF C AFF 7 774 LE RESTORE HL ATE F1 79 AF ATE 200CO Tt Li 440 7727 For HL tRESTORE REGISTERS 6402 C1 PFR PUF BC 4405 Fj 729 POF 4 4018 C ENI O2 1 GET RANE E TATUS STATUS t HORIZONTAL SELECT BOG 1 20 t GANE FF GET STATUIS PUSH AF SAVE SAVE REGS 404 ps pe 4607 7t eo LU A 64 EN OF EH 6404 2 57E 10 JR 7 lt tIF 254 64 Fr FEFF 11 CF OFFH 640E TEJD 12 JR 2 GZ HOM
109. TAT Or ALL LANE SDE DELP ppi TOEALLOC ATE FOR CETATII TRE TORE SF RET ALIR CHF ESLSTACI FUFDATE F SF sRESTOFE REGS RET ALIR ON ETALK BY THE INES 11 MOVE BYTES RYTES TO MOVE DE DIRECTION A MOVE BYTES PUSH L Li CALL LU LU LU LD LD LL 146 HL DE C B B IXeSRC FAN ENABLE R D C E IX BUF FTR f SAVE REGISTERS SELECT SAE BANI MOVE FROM SKC TO STALE IX BUF FTR 1 L COIX SRCLAIDR H CIX SRCLADER 1 444 6 645 ec A e 4 05 eA GAAF amp amp RO 6452 ec p e65R amp S4E9 ee RA amp 5 GARE e 6RF 6 2 64073 6604 6607 64604 46C0 bbl enp1 ect 6 24 6604 66017 amp eDB 6606 6DE amp amp 1 amp amp E 4 GEE amp 6 t 5E7 Tt AT 57 4 572 672 67 2 672 720 LTE 72F Q7 Seis E EG ty 1809 7 ED42 pp 007407 C1 E1 ES 0 460 4 44 40 DD58 04 DDS4A05 DODGE oo 00466501 SERS 1308 A7 Era 00794 Dn74o C1 1 E1 4 CDAEGZ 04403 D 7E QC Q7 CF 3803 CS geo2 Eas Cr A D7 4 Fr 47 EE DF gt 6 6 LI e 47 OE 7 7 11 5 us ES 210000 3 j Lee
110. TION 4 b a geen L umaka ie VE c b IHE HHEIRRET a zd Lu M E Jl BI dL o a 7 27 73 NOTES 2 54 1 Circuit Board Material FLGFN C62 C1 1A2A 94V 0 Copper 1 or 2 sides 2 Contact Fingers Min 10 millionth MIL G 45204 Gold over 00005 to 00010 inch low stress nickel 3 Contact Fingers 2 and 36 should be longer than other fingers to latch up when inserted with power on FIGURE 2 4 2 2 J4 SIGNAL LAYOUT View from Front gt a t IS iis bloia i i ijoicici si i i 7i li 22 lt lt COMP gt e n SIDE 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 34 io E 7 9 LL 1738 17 19 22 22 25 27 29 3L 335 JJ d NON COMP i ioilaialaiaiaeiaijizZliziisi i i i iialjc 59 TABLE 2 4 2 4 CONNECTOR SIGNAL DEFINITIONS SIGNAL NAME DESCRIPTION Address Bus Bit 14 Buffered 5 volts DC Address Bus Bit 12 Address Bus Bit 13 Buffered Data Bus Bit 0 Data Bus Bit 7 Data Bus Bit 1 Address Bus Bit O Data Bus Bit 2 Address Bus Bit 1 Data Bus Bit 6 Address Bus Bit 2 Data Bus Bit 5 Address Bus Bit 3 Data Bus Bit 3 Address Bus Bit 15 Buffered Data Bus Bit 4 Memory Request Active Low Bfrd I O Request Active Low Buffered Refresh Address B
111. TS2068 Technical Manual This is the second edition of the manual published by Time Designs Magazine now defunct It is based on the original blue manual released by Timex Computer Corp shortly before it folded Aside from a page renumbering and some sections that were added in the second edition there is not a lot of difference between the two This doc was captured using Adobe Acrobat 3 0 the only software could find that did a half decent job There are still numerous errors where Acrobat got confused but I m too lazy to fix them Alvin 05 10 98 aralbrec concentric net TIMEX SINCLAIR 2068 PERSONAL COLOR COMPUTER TECHNICAL REFERENCE MANUAL Prepared by V C Corcoran and H Branigin TIMEX COMPUTER CORPORATI ON Waterbury CT 06720 May 1984 Second Edition Printing Published Exclusively by TIME DESIGNS MAGAZINE CO COLTON OREGON 97017 JANUARY 1986 PREFACE This manual is dedicated to the many individuals associated with the Timex Computer Corporation in the development and production of the TS2068 Our special thanks to Nan Parsons who prepared the TS2068 Schematic and other drawings used in this manual While every effort has been made to make this document complete and accurate use of the technical Tlntormetron contained herein is at user s sole risk The Timex Corp or its affiliates and Time Designs Magazine Company assume no responsibility or liability for the safety performance of any
112. V EQU POWER EQU OR EQU AND EQu EQU APD EQU STOAND EQU CONCAT EQU VALSt EQU USRS1 EQU INKEY EQU NEGATE EQU CODE t EQU LO MON EQU VAL 1 EQU LEN EQU SIN EQU COS EQU EQU ASN EQU ACSt EQU ATNE EQU LN EQU EXP EQU INTs EQU ROOT EQu SGN EQU OF BH FOR INPUT FROM PRINTER OF BH FOR OUTPUT TO PRINTER OF EH INPUT PORT FOR READING KEYBOARD OFEH f OUTPUT PORT FOR TAPE OFEH INPUT PORT FOR 6 TAPE INPUT BIT IN I PORT 494 ADDITIONAL OF 4H DOCK HORIZONTAL SELECT PORT OF CH EXPANSION BANK DATA PORT OF tH EXPANSION BANK COMMAND FORT OFFH HOME ROM EXPANSION RANK PORT pues OFFSETS FROM CHANS OF PERMANENT CHANNELS 0 KEYBOARD 5 TV SCREEN UPPER HALF 10 RAM INSERTION 15 ZX PRINTER 4000H 96 8 ADDRESS OF CHARACTER SET STARTING WITH SPACE i CALCULATOR COMMANDS IN THE DESCRIPTIONS T k S STAND FOR THE TOP amp SECOND FROM TOP ON THE CALCULATOR STACK WHERE NECESSARY FULLER DESCRIPTIONS CAN BE FOUND AT THE CODE FOR THE RELEVANT ROUTINES FOLLOWING COMMANDS HAVE THE STACK POINTERS HL amp DE BUT STKNXT DECREMENTED FOR THEM BY CALCTR BEFORE THEY ARE CALLED STKDWN 55 gt St RELATIVE JUMP CONDITIONAL ON VALUE OF T IF JUMP 1 EXCHANGE S T gt T S EXCH 1 S T gt S LOSE 1 SUBTRACT S T gt S T SUB 1 S T gt S T TIMES 1 DIVIDE S T gt S T DIV 1 IS T gt Se T POWER 1 S T gt S OR T
113. Vector U out Color vector level for quadrature B Y input to video modulator GND Ground In Ground return of SCLD 0 Buffered Clock out Buffered CPU clock to outside J connector R Red Color Output Out Produce color signals to RGB monitor TTL level C Green Color out Produce color signals to RGB output monitor TTL level B Blue Color out Produce color signals to RGB output monitor TTL level 41 2 1 8 2 2 1 8 3 2 80 Clock Generation The oscillator circuit utilizes an AT cut quartz crystal at 14 112 MHz This oscillator feeds a divide by 4 chain to generate the 3 528 MHz clock for the CPU 0 CPU This clock runs continuously except when the CPU addresses the 16K bytes of RAM containing the video display file at the same time the video display processor logic requires access to that same RAM For this contention case the CPU clock is stopped in the high state until the video display processor access has been completed then the CPU clock continues in its normal manner Display File H W Control and Timing The 14 112 MHz oscillator is also used to drive the counter chain deriving video ti ming By dividing the 14 112 MHz signal by 896 a 15 75 KHz horizontal sweep frequency is generated The 15 75 KHz signal feeds a 9 stage counter which counts from 0 to 106H 262 deci mal developing the 60 1145 Hz vertical sync See Figure 2 1 8 2 During each horizontal scan the video display processor accesses in the standard vide
114. X DEST ADDR 1 1 SAVE S STATUS CREATE BI TMAP DEST BITMAP C A DEST BITMAP AF B B SRC BITMAP A IX SRC_BANK D IX DEST BANK D COMPARE SRC AND DEST BANK NUMBER XB_DIFF_ BANKS e B IF BANK NUMBERS ARE DIFFERENT B A B UNION OR SRC AND DEST BITMAFS XB 0O_MOVE A B CHECK FOR OVERLAP BETWEEN SRC ANU C DEST CHUNKS OF FH 1 XB OVERLAP E B THERE IF NO OVERLAP O BANK ENABLE f SELECT DEST BANK IX SRC BANK C E BANK ENABLE I SELECT SRC BANK L IX SRC ADOR CIX SRCLADDRe1 CIX DEST ADDR D IX DEST ADDR 1 CIX tCIX LENOTH 1 CIX DIRECTION C XB REVERSE lt O HL MSTROT BC 255 WORD BC DE STKSZ HL DE DE FFEE_HYTE S HL DE Le Ht HL 1 HL SP IHL lt U DE Ur MEARE TF IMI Cr EW HL DE NC XELSFACE SIF SF OLI SF NEW Z 1 TRETURN ERROR CODE XE EXx11 DE SP HL t SET SF TC SP NEW EBLE 57 f HL FU 1 _ L SAVE ON STAC CIX BLE __PTF 1 H L 2X LENGTH H IX LENGTH 1 AGURESS STACH LIMIT SP LEFT Te ME HL DE tDE BYTES TC MOVE THIS TIME XE LAST MCOVE TIF LESS THAN BUF_S2 RYTES LEFT MOVE BYTES 1 COOP HL DE DE HL MOVE PYTES D
115. XFER RYTES HERE IS THE FIXUF TABLE FOR THE VIDEU MODE CHANGER INC LU POP F OF POF FOF POF EX POF EX POP EX POF POF EX RET EU EHI EC Em e goi EDL EQUI Eau Ix SF IX t 1X F FX SF Ix SF IX ix IX SPs JX HL gt 1y AF HREXFT 7 HREXPT 1 DKHSPT A HL 4 HIF AEH 4 z1 LH amp 2 38H 40H amp 4 amp 4 H amp S1EH 653EH 6 4 EH 657 2H 0H 646 5 CH 6E amp H 6722H TRESTORE REGS CLEAN UF TIRASH EL IT DEFINE THE LOCATIONS IN RAM WHICH MUST BE UPDATED WHEN MOVED FROM CHUNI 2 T CHUN 7 OR V CE VERSA FIXTEL ORG DEFW DEFW DEFW DEFW DEFW DEFW DEFW DEFW DEFW DEFW UEFW LEFW LEF W LEFW LE FW LEFW LEF W LiF W 149 U SPAT CH 22H D ISPATCH 4DH DISFATCH 7 2H D ISPATCH OAEH INT GAH INT 1FH INT Z 5H INT 2EH INT 4L H GE T_WORLI 4H GET WORD OAH GET WORD OEH GET WORD 14H WORDI 1F H FUT ACRI 3H FIT MORI 9H FUT WORD UH FIAT WIDRUI 1 3H FLIT WORD 1CH zTATLIEIS 1 ZH GET 17H DET ez ZH LE 1 LNUPNECR 2H tok F AIMEE Fe 7H CPET MUJ Fes CH ag THE AULRESSES IN THE TABLE ARE DEFINED AS 3 ADDRESSES 10
116. ance per depressed CR10 A13B CRIT A8 CRI 2 A14B CR13 A158 replacement of the keyboard supplied must resistance less than 200 ohms Bounce less than 10 ms line less than 20 br 0 or 1 key less than 40 pF more than 1 key depressed 64 3 0 SYSTEM SOFTWARE GUIDE 3 1 3 2 Identifier Location 13 13H of the Home Bank ROM is used to identify the revision level of the System Software The initial version is identified by this location having a value of 255 Any subsequent versions will decrement this value by 1 e g the first revision would be identified by a value of 254 This identifier should be used to conditionally apply patches or execute work arounds identified as necessary with a particular version of the System Software ROM Organization and Services 3 2 1 Home ROM 3 2 1 1 Fixed Entry Points Home ROM Location 0 is the entry to the system initialization code upon power up Ref Figure 1 1 4 Locations 8 through 48 8H through 30H are the Z80 RESTART entry points for the following functions RESTART FUNCTI ON 5 ERROR Error exit from BASIC Address on Stack points to Error Number 15 WRCH Write Character Code in to Current Output Channel as established by SELECT Address of output routine pointed to by System Variable CURCHL See Section 1 0 24 IGN SP Return in A the current Significant character in the Program Line Address in System Variable
117. ated DC to the unit as described in Section 2 1 1 Mechanical details of the plug which mates to the TS 2068 are shown below AR MINI POWER PLUG 315 r gp STRAIN DETAIL p 250 315 O97 DC RETURN GND 63 2 2 2 4 4 4 6 Composite Monitor Output The MONITOR output on the rear of the TS2068 provides a 1 V 20 composite color video signal output to an phono jack which is mated by a standard phono plug into a 75 ohm coax cable Section 2 1 11 1 RF Output The TV output on the modulated color video signal J as selected by the channel select switch on the bottom of the unit Connection to the phono jack output should be via a standard phono plug and 75 ohm coax rear of the TS2068 provides a on VHF Channel 2 or Channel cable See Section 2 1 11 2 Channel frequencies provided are Channel 2 55 250 100 KHz Channel 3 61 250 100 KHz Output levels are less than 3 milliwatts as limited by the Federal Communications Commission 8 Keyboard Interface 9 Connector Located on the PCB inside the TS 2068 is a 14 pin single in line flex cable connector AMP TRI 0 MATE P N 1 520315 4 or equivalent Signals are as listed below SI GNAL GND KBO KBI KB2 KB3 KB4 CR6 All CR7 A10 CR8 A9 CR9 A12 4 a w N gt Any modification to or the following consider 1 2 3 Contact Capacit
118. ating Attribute File address would be substituted for the method used in the example if not working in High Resolution Graphics mode Inaddition to data insertion two major screen support functions are scrolling and clearing the screen Scrolling is done in the System ROM by copying the entire display file data and attribute controls up one line position Line 1 to Line 0 Line 2 to Line 1 etc andinserting a blank line at the bottom Numerous more elaborate scrolling techniques can be implemented using various directions up down left 119 5 503 2 right and smaller areas or windows of the screen Similarly clearing the screen which consists of writing zeros to the data file and updating the attribute bytes to a uniform value can be implemented on smaller sections of the screen The software packages in Appendix C contain examples of such implementations Dual Screen Mode In this mode the second display file is used to provide a second independent screen having the same data and attribute organization as the orimary display file By writing to Port FFH with Bits 0 5 1 Bit 0 set the second display file is activated at the video screen Appendix C contains a software package supporting Dual Screen Mode The software package uses the system variable VIDMOD to determine which display file is the target of the current operation Special values for VI DMOD have been defined to permit building of one display file w
119. back cover and Appendix D Unit Absolute Ratings 53 Interfaces and Connectors 53 System Bus Connector Pl Cartridge Connector 4 Cassette 1 0 Joystick Composite Monitor Output RF Output Keyboard Interface Connector J AC Adapter Power Plug INO NJ MJ RO NJ NJ NJ PN gt gt N SYSTEM SOFTWARE GUIDE 65 Identifier 65 3 3 aAa gt 2 3 UW RI TABLE OF CONTENTS continued ROM Organization and Services 65 3 2 1 Home ROM 3 4 151 Fixed Entry Points 3 21 27 BASIC AROS Support 25402 12 General 3 2 1 Extension ROM 3 2 2 1 Fixed Entry Points jede General 3 2 2 3 Video Mode Change Service 3 2 2 4 Extension ROM Interface Routine RAM Organization and Services 72 3 3 1 System Variables 3 3 System Configuration Table 3 3 3 Machine Stack 3 3 4 05 RAM Routines 3 3 4 1 RAM Interruption Handler 3 3 4 1 RAM Service Routines 3 3 4 3 Function Dispatcher SYSTEM 1 0 GUIDE 91 I O Channels 91 Keyboard Video Screen 2040 Dot Matrix Printer gt 1 1 1 N gt Cassette Tape 102 Joysticks 104 Software Generated Sound BEEP 105 Programmable Sound Chip SOUND 105 ADVANCED CONCEPTS 106 Cartridge Software Hardware 106 Advanced Video Modes 117 Other 125 TABLE OF CONTENTS conti nued KNOWN BUGS AND CORRECTI ONS 126 LROS and Machine Code AROS
120. ble Extension ROM Select 5 Volt Power Interrupt to CPU ROS Chip Select Speaker and Tape Output Clock Bus Direction to Sound Chip Bus Control to Sound Chip continued DI RECTION OF SCLD In In In out In out out out out out out 40 FUNCTI ON CPU is generating a refresh address to refresh dynamic s Magnetic tape signal input When active low indicates that i nter nal memory 1 disabled Home Extension and Dock Banks and an external memory is in use Active low chip select signal for Extension ROM Power 5V input to SCLD Interrupts CPU to handle keyboard strobing and timer for PAUSE com mand Open drain N channel with internal pull up ROM Oriented Software Cartridge Bank Chip Select Digital output to magnetic tape and to sound amplifier for speaker output Clock for sound chip 81 764 MHz A bus direction control signal to the PSG When high the sound chip either receives a write to PSG or latches addresses from the data bus A bus control signal to the PSG When high the sound chip either is read to data bus or latches addresses from the data bus TABLE 2 1 8 1 SCLD I O PIN FUNCTI ON DEFI NI TI ONS continued DI RECTI ON OF SCLD SYMBOL NAME OUT FUNCTI ON out oscillator Out out Xtal Oscillator amplifier output to drive crystal OSC In Oscillator In In Xtal Oscillator amplifier input to sense crystal signal Chroma
121. buffer This flag is used when exit is made from a program to print any unprinted data prior to program termination As the pixel data for a particular character is entered into the buffer the buffer address is incremented by 32 20H the sequential data in the buffer therefore represents 8 complete scan lines of 32 characters When the Print Buffer is full or upon processing an End of Line ODH or at program termination the contents of the buffer are written to the Printer the buffer is cleared and the PRLEFT Flag is set to zero Printer 1 0 is done via Port OFBH but the Printer responds to any 1 0 Read Write with Address Bit 7 1 and Address Bit 2 0 Therefore any Port providing this combination e g Ports OFA through OF8 and Ports OF3 through OFO as well as others will interface to the Printer See Section 2 1 13 3 for the bit definitions for Printer 1 0 The pixel data is written to the device by the routine PRSCAN in module 10 2 of the Home ROM which outputs 1 scan line 32 bytes one bit at a ti me on each call to the routine There are two controlling routines for output to the printer DUMPPR is called from SENDTV based on buffer full or End of Line control This routine will call PRSCAN 8 times to output the 256 bytes of the Print Buffer 8 scan lines The other routine is K DUMP which implements the COPY command This routine calls PRSCAN 176 times to write the contents of the primary display file for the main screen to
122. ce Routine listed in Figure 3 2 2 2 The general flow required to write a header and data block is Call with 0 IX contains the address of the header and DE contains the length 2 Delay loop approximately 1 second j Call W TAPE with A FFH IX contains the address of the data block and DE contains the length 102 The R TAPE routine performs either a LOAD transfers data from tape to memory or VERIFY compare data from tape against data in memory operation based on the status at entry Carry Set for Load and No Carry if Verify As for the Write A Block Type 0 for Header and 1 FFH for Data Block IX contains the memory address The tape routines return 1 for successful completion and Carry for error or Break Key detected Roth W TAPE and R TAPE exit via the routine W BORD which restores the Border color based on bits 3 5 of the system variable BORDCR If the Break Key is detected during this exit routine a RESTART 8 ERROR is executed NOTE The write to Port OFEH in the exit routine restoring the Border Color has hit 3 0 This creates a final transition on the tape followina a write ooeration This transition is necessary in order to successfully read back the final data bit from some tape recording devices If yuare calling the W TAPE routine so as to bypass the normal exit path you must perform this final write to Port OFEH with Bit 3 0 within a similar timeframe Addendum to
123. d RD signals used as in the fetch cycle During a write cycle the WR signal is activated when the write data is stable on the data bus The address and data bus contents remain stable for one half T state after the WR signal goes active Figure 2 1 3 3 illustrates FIGURE 2 1 3 2 INSTRUCTION OP CODE FETCH Mt Cycle T3 T Ti T2 d H P A0 A15 __fernesnaoon RD WAIT ET ES MI FIGURE 2 1 3 3 MEMORY READ OR WRITE CYCLES Memory Read Cycle Memory Write Cycle a T3 d T2 T3 0 15 MEMORYADOR j MEMORYADOR MREG GR ee DATA BUS C D 72 00 07 wm L H Ur LLLI 2 1 3 6 1 0 READ WRITE During 1 0 operations TORQ and RD WR are activated on the leading edge of the T2 clock and a single Wait state is automatically inserted as illustrated in Figure 2 1 3 4 The and WR signals are used to enable data from the addressed port onto the data bus and to on the rising edge of WR clock data to the 1 0 port respectively Note that external 1 0 may stretch the activation period of the WAIT line to extend the 1 0 cycles FIGURE 2 1 3 4 I OR OUTPUT CYCLES DATA 805 r 3 WAIT wR DATA BUS 2 Ta T3 T PORT 55 J Cycle Insertedby 280 CPU 2 1 3 7 Maskable Interruption When enabled by software when BUSRO is not
124. dress Bus Output from the 7 80 16 0115 of address information AQ A15 which are high active tri state signals and address for memory data and 1 0 device exchanges MEE Data Bus These input output signals from the 7 80 00 D7 constitute an 8 bi t bi directional high active tri state data bus used for data exchanges with memory and 1 0 devices 2 1 3 3 Control Bus Associated with the Z 80 are 13 control lines which are provided by or used by the Z 80 to control system operation These signals are detailed in Table 2 1 2 1 3 4 Op Code Fetch The timing during an cycle 09 Code Fetch is shown in Figure 2 1 3 2 the beginning of the cycle the PC Program Counter is placed onto the address bus then one half clock ti me later the MREQ signal goes active indicating that the memory address is stable The RD signal is activated to indicate that memory read data should be gated onto the data bus the rising clock edge during the T3 state the CPU samples the data on the data bus and deactivates the RD and MEQ signals During the T3 and T4 states the CPU decodes and executes the fetched instruction and the CPU places on the lower 7 bits of the address bus a memory refresh address and activates the RFSH signal indicating a refresh read is to begin when MEQ iS activated 2 1 3 5 Memory READ WRITE Memory read or write cycles other than Op Code Fetches are 3 clock periods long with the MREQ an
125. e software and if the BUSRQ signal is not active When the CPU accepts the interruption an acknowledge signal is sent out at the beginning of the next instruction cycle TORQ at MI ti There are three interruption modes selectable by the software RMI Non Maskable Interruption Input negative edge triggered This signal has a higher priority than INT and is always recognized at the end of the current instruction cannot be masked The CPU is forced to restart to location 0066H with the program counter saved in the external stack NOTE The NM is not used in the 752068 ROM software design 16 TABLE 2 1 180 CONTROL SI GNALS continued ACRONYM DEFINITION RESET Reset Input active low This signal forces the program counter to zero and initializes the CPU Address and data buses go to their high impedance state and control output signals to their inactive state No refresh occurs Initialization includes Disable the interrupt enable flip flop and set Register Register and the Interrupt Mode all to Zero CPU BUS CONTROL BUSRQ Bus Request Input active low This signal IS used to request the CPU address bus data bus and tri state output control signals to qo to a high impedance state permitting other devices to control these buses The CPU sets these buses to a high impedance state at the termination of the current Machine cycle BUSAK Bus Acknowledge Output active low This signal is used to indicate to
126. ecution of the cartridge BASIC program is done by copying program lines to a buffer in the Home Bank RAM ARSBUF the most efficient cartridge execution is obtained by making program lines as large as possible 1 making use of the multi statement feature of the TS 2068 The reverse is true concerning execution of READ commands An entire DATA statement is copied to the Home Rank RAM but only the current item is accessed It therefore will be more efficient to not make DATA statements excessively long The BASIC program lines appear in the cartridge in exactly the same format used in the RAM i e Line Number 2 bytes Length 2 bytes Command Token etc terminated by an Enter 0ODH Numerical constants appearing in a program line are followed by the CHR OEH byte and 5 byte floating point format described in the User Manual see Appendix C of the TS 2068 User Manual The Variables area is built in the RAM address in VARS exactly as though the program were in the RAM All variables including arrays are built at the time of program execution there is no provision for copying or accessing ore defined variables from the cartridge however see Section 5 3 2 The last program line must be followed by a terminator byte having the Most Significant Bit set e g 80H otherwise the Interpreter cannot detect the end of the program A BASIC AROS may contain machine code accessed via the USR function If the machine code address is w
127. ed is S POSN SPOSNL or P POSN for Screen Lower Screen or Printer respectively Outputs a space to currently selected device End of Li ne Sets current position to start of next line if screen or outputs printer buffer if printer output message to currently selected device DE points to base of message table which contains variable length ASCII coded messages The first byte of the table and the last byte of each message must have the most significant bit set Register A contains the message number numbered from 0 upwards CLS command Executes both CLS and CLLHS Scrolls entire screen pri mary display file up 1 line POINT function Processes parameters from Calculator Stack to BC Returns unsigned integer value 0 or 1 on Calculator Stack reflecting state of pixel at coordinates X Y Same as DRAW L but enter with BC register containing coordi nates B Y and C X Output Line Number as 4 digits right aligned and space filled to currently Selected output channel HL points to MSB of Z byte Line Number 4 0 SYSTEM I O GUIDE 4 1 I O Channels The TS 2068 software architecture supports up to 19 1 0 Channels or Streams numbered from 3 through 15 Those numbered less than 0 are hidden or reserved for system use Channels 0 through 15 are available for assignment via the OPEN command which has the following format OPEN n s where n is the Channel number 0 15 and s is the Device Spec
128. een Primary Display File contains data for 256X192 pixels Second Display File contains 6144 Attribute Bytes each one controlling 8X1 pixels NOTE 1 The two display files are com bined to provide a 64 column X 24 line screen Even columns are derived from data in the Primary Display File and odd columns from the 2nd Display File Bits 3 5 of the mode select the ink color which determines the complementary paper color The Flash and Bright Attributes are fixed at 0 the Border is fixed at the paper color NOTE 1 normally used for Attribute Bytes are not accessed by the video hardware in this mode 35 2 24 Extension ROM Interface Routine The Extension ROM routines W TAPE Write from RAM to Tape R TAPE Read from Tape to RAM see Section 4 2 and CHNG VID see Section 3 2 2 2 may be of interest to the machine code programmer Because of a conflict with the use of the IX Register the tape routines cannot be successfully accessed via the Function Dispatcher Because the Change Video Mode Service may involve relocating the OS RAM routines including the Function Dispatcher and for other reasons it also cannot be consistently accessed using the Function Dispatcher Figure 3 2 2 2 gives a sample routine to be executed from the Home RAM which can be used to bank switch to the Extension ROM and call directly to the desired service Appendix A contains an Extension ROM Map giving the addresses of these and
129. em Variables Definition File 2068 HOME ROM 152000 HOME ROM BASIC LOC ORJ CODE M STMT SOURCE STATEMENT ASN 5 9 13 EJECT 14 INCL SYSVAR 15 PAGESIZE 54 16 17 RST MACRO ROUT 18 RST ROUT 19 ENDM 20 21 ASSERT MACRO COND 22 COND COND 23 ERROR IN ASSERTION COND 24 ENDC 25 26 27 1 SYSTEM VARIABLES 23 29 L_LEN EQU 32 CHARS PER LINE ON THE DISPLAY 30 TV LNS EQU 24 NO OF LINES TV SCREEN 31 D FILE EQU 4000H ADDRESS OF DISPLAY FILE 32 ATTRS EQU D FILE L LEN TV LNS 8 SCREEN ATTRIBUTES 33 PRBUFF EQU ATTRS TV_LNS L_LEN PRINTER BUFFER 34 ASSERT PRBUFF AND OFFH O COND NOT PRBUFF AND OFFH 0 ERROR IN ASSERTION PRBUFF AND OFFH O ENDC 150 100 101 102 103 104 KSTATEs KSLA KS Ct KS B KS Dt LAST REPDEL 1 REPPERt DEFADD K_DATAS TVDATA STRMSt EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU HIDSTR EQU HID Kt EQU HID S EQU _ EQU ST INP ST EQU _ EQU LPR STt EQU CHARS FART PIP FLA65 SPCt PR EQU EQU EQU EQU EQU EQU EQU EQU L MODE 1 EQU L MODE 1 EQU KEYHIT EQU NO TVFLAG LHS EDIT EQU EQU EQU EQU EQU ECHREQ EQU LIST CL HS ERR SP LISTSP MODE NEWPPC NSPPC PPC SUBPPC 1 BORDCR E_PPC VARS DEST CHANS CURCHL PROG EQU EQU EQU EQU EQU EQU EQU EQU EQU
130. ffect If before or immediately following execution of the BASIC graphics operation you update the attribute control information in the second display file you could possibly take advantage of the System ROM graphics capability Admittedly this is not a simple operation in the case of circles or drawing diagonal lines and it will be more efficient to develop code specifically to support this video mode The following sample routine takes as input two single byte binary digits representing the X and Y coordinates of a pixel position on the screen It formulates the display file address of the byte containing the pixel creates a pattern or mask byte for the specified bit position sets the bit in the display file and updates the attribute byte High Resolution Graphics Mode assumed This represents a simplified version of the approach used in the System ROM graphics support routines PLOTBC and SCRMBL The two inputs are assumed to be as follows Reg C X Coordinate 0 255 0 FFH going left to right across the screen Y Coordinate 0 191 0 BFH going from bottom to top of the screen Reg D NOTE This covers the full vertical range of 192 positions Y Bit SCREEN LINE NO SCAN ROW BLOCK WITHIN WITHIN 0 2 BLOCK LINE 0 7 0 7 PLOTXY The Y Coordinate is checked for valid range and reversed directionally so that 0 represents the top of the screen and 191 represents the bottom After this reversal t
131. having length BC from Program or Variables me mor y Updates affected system variables Converts number in BC from binary to ASCll and outputs to currently selected channel If BC less than 0 outputs a O Check syntax of command or program line in Edit Line Buffer E LINE ERR NR 1 if no errors otherwisecontains Error Number l Execute command s from Edit Line buffer FOR command STOP command Does RESTART 8 with Error No 9 NEXT command READ command DATA statement RESTORE command Line No in BC RANDomi ze command Sets seed for Random Number Generator based on Parameter Calculator Stack Ifparameter is non zero value is loaded to SEED if zero value in FRAMES is loaded to SEED TABLE 3 3 3 2 TS 2068 FUNCTION DISPATCHER SERVICES continued SERVI CE SERVICE CODE DESCRIPTION CON T 61 43H CONT command Loads values from OLDPPC and OSPPC to NEWPPC and NSPPC and returns Inside the BASIC Interpreter this results in executing from Line No in NEWPPC Statement No in NSPPC J UMP 68 44H Jump to Line Loads Line Number from Calculator Stack to NEWPPC and sets NSPPC to 0 and returns FI X Ul 69 45H Converts Floating Point number on Calculator Stack to a single byte unsigned binary value in uses FP2A Does RESTART 8 for Error B if number out of range FIX U 70 46H Converts Floating Point number on Calculator Stack to a 2 byte unsigned binary value in BC uses F
132. he two coordinates represent the following values Bit17 6 5 4 3 2 0 COLUMN 0 31 0 1 0 1 We first formulate the MSB of the display file address using the Block and Scan Line information in the Y Coordi nate PUSH SAVECO BC 191 B C ERROR B A 0COH HA 0 40 Save coordinates Test Y within range Y coordinate beyond range Y Coordinate now 0 Get Block No 0 2 Shift Bits to Pos 3 amp 4 Save Block Bits Y Coordi nate Get Scan Row Bits Combine Block and Scan Row Base Address of DF 4000H H MSB of DF Address Next we formulate the LSB of the display file address using the Line information from the Y Coordinate and the Column information from the X Coordi nate LD RLCA RLCA RLCA AND LD LD AND OR RLCA RLCA LD A 0C7H L A L L 122 Get X Coordinate Align to Pick Up Line Bits from Y A 2 LS Bits Column XXX 3 MS Bits Column Clear Bits 3 5 Save A in L Get Y Coordi nate Get Line Bits Combine with Col Bits Shift to Final Position A Line Column L LSB Display File Addrs 5 2 Next we get the pixel position within the byte by taking the last 3 bits of the X Coordinate and create a mask byte having all bits zero except the addressed pixel This mask is then used to set the bit in the Display File address is set to Display File 2 to update the Attribute File High Res Graphic
133. her 74 LABEL XFER NOTE TABLE 3 3 4 1 05 RAM SERVICE ROUTINES continued SERVICE CODE LOCATION Deci ma BYTES 6722 See Appendix for listing of these routines known corrections to the routines 75 DESCRIPTION Copies n byte s from specified source to specified destination in either ascending or descending order Source and destination can be in the same or different banks and can be in shadowing chunks but neither source nor destination can pass a chunk 8K boundary since only the chunks containing the starting source and destination addresses are explicitly enabled stack by Parameters passed on pushing Source Bank Dest Bank Source Address Dest Address Length 0 Direction O Asscending Descending See Section 6 0 for 3 3 4 3 Function Dispatcher Chunk 3 Entry 6200H Chunk 7 Entry F9COH The Function Dispatcher provides a common interface to a number of system routines via a Service Code and Jump Flag parameter passed on the machine stack Table 3 3 4 2 lists the routines in Service Code order Codes for routines that are known to not be successfully accessible via the Function Dispatcher have been deleted marked Reserved However there is no guarantee that those on the list can be accessed without problems Some ROM routines require data in a particular format e g BASIC floating point number s both standard and special integer format
134. hile the other is active at the screen so that a complete screen image is ready when the hardware mode is changed Copy and Exchange routines have been provided to move data within and between the two display files This enables the BASIC graphics commands like PLOT CIRCLE and DRAW which work only in the primary display file to be used to create screens which are then moved into the second display file Because the System ROM works only in the primary display file you can come up with some unusual situations when you have the second display file active at the screen and you are executing BASIC or using the System ROM routines Ifan error occurs for example the error message will be placed into the primary display file and the ROM will be waiting for input from the keyboard to direct the next action but all of this is invisible since you have the other display file active The machine will appear to be hung but it is only doing its normal thing Be prepared to enter a OUT 255 0 to an invisible command line in order to switch the display back to the standard file Don t forget to also set VI DMOD POKE 23746 128 to keep things consistent inside the dual screen support code High Resolution Graphics Hode This mode is set by writing to Port with Bits 0 5 2 Bit 1 set Inthis mode also called Extended Color Mode the second display file is used to expand the number of Attribute bytes from one for each 8 X 8 pixel group to one
135. his circuitry produces color vectors at approximately the following angles PHASE TS 2068 NTSC STANDARD Degrees Degrees Blue 350 350 Magenta 64 62 Red 116 112 Green 242 240 Cyan 284 284 Yellow 170 170 Reference 224 180 The Front Porch Sync Pulse Back Porch and Color Burst portions of the composite video signal are illustrated in Figure 2 1 11 1 Inproper adjustment the following Should be observed 40 2 IRE units 35 to 45 IRE units 3 579545 70 Hz Sync Pulse Color Burst Color Burst Freq The following three facts may aid in understanding problems with certain monitors 1 color burst is not synchronous with the waveform since it is generated from the 3 579545 MHz crystal and the waveform is derived from the 14 112 MHz crystal The result is observed ripples at color boundaries e g green to magenta The color burst duration is 8 cycles while standard TV broadcast stations provide 9 cycles This short burst is a problem for some monitors 3 The color burst starts 6 4 microseconds from the leading edge of sync Many monitors are designed to expect this start as early as 5 3 microseconds thus these monitors may not produce color when attached to the TS 2068 47 FIGURE 2 1 11 1 COMPOSITE VIDEO SIGNALS DETAIL 6 4 CYCLES usec 2 1 11 2 RF Modulator The composite video information is used to AM modulate the selected channel frequency via the LM1889 and assoc
136. iated Channel 213 tank circuitry The modulated output is filtered through the output filter network to reduce harmonic generation to compl y with FCC requirements The RF circuitry is physically contained inside the RF can at the rear left corner of the PCB at the RF output jack 75 ohms is the output impedance 48 2 1 12 Cassette 1 0 See Sections 2 1 13 2 2 4 3 and 4 2 2 1 13 Port Map Table 2 1 13 1 summarizes the 1 0 addressing of ports utilized by the TS 2068 Details of the data bits of each of these ports is provided by the following sections 2 1 13 1 Display Enhancement Control Port FFH The display enhancement control register within the SCLD controls a Selection of Enhanced Video Modes b Ink selection for 64 Column Mode c Enable Inhibit the 17 ms interruption to the 780 d Selection of Extension ROM or Cartridge see Section 2 1 8 1 64 Col umn Mode Video Mode Ink Paper Selection Selection 000 Black White 000 Normal Primary 001 Blue Yellow Display File 010 Red Cyan 001 Second Display File 011 gt Magenta Green 010 High Res Graphics 100 Green Magenta 110 64 Column Mode 101 Cyan Red 110 Yellow Bl ue Other combinations may 11 White Black produce unpredictable results Inhibit 17 ms Interruption 0 to Enable EXROM Cartridge Select See 2 1 8 1 49 TABLE 2 1 13 1 1 0 PORT PORT ADDRESS FUNCTION HEXS DECIMAL BINARY OPERATION REFEREN
137. ification e g keyboard 5 screen or printer Channels 0 through 3 are initialized at power on or execution of a NEW command to support the standard system devices and character I O functions as shown in Figure 4 1 1 Channels 4 15 are considered Closed You can re assign the standard 1 0 e g OPEN 2 P will direct all PRINT and LIST commands to the 2040 Printer instead of the screen You can also assign Channels 4 15 and then direct 1 0 by including the Channel number or a variable equated to the channel number in the I Ostatement e g PRINT n Support for other than the standard system devices descri bed above is not implemented in the original version of the TS 2068 and attempts to OPEN Channels or Streams using other than the standard device specifications K S or P will result in error message One possibility for adding BASIC support for new devices is to intercept the I Oerror on OPEN and other commands such as CAT and FORMAT via ON ERR and interpret the BASIC program line using your own machine code routines Channel Device Stream Specification Command Function 3 Keyboard Lower Screen RESERVED Main Screen RAM Write not used 0 Ue Output to Lower Screen NPUT command 2 E n PRINT LIST commands 3 p LPRINT LLIST commands FIGURE 4 1 1 91 STRMS CHANS The Channel architecture is implemented by a number of tables located in b
138. is supplied for regulation through a bi filar torroidal inductor which reduces conducted line emanation for FCC compliance and through the power ON OFF switch located on the left side of the 152068 This switch voltage is supplied to the System Bus Connector see Section 2 4 and for regulation to the 12 V regulator and the 5 V regulator Characteristics are as follows SUPPLY VOLTAGE RANGE CURRENT RANGE 5V 4 75 5 25V 200ma 1 0 A 12v 11 5 12 5V 20ma 00 120v mna E ZW REGULATOR 112v GND The 12V regulator is a 78112 series regulator while the 5V regulator is a switching supply utilizing the 78540 circuit 2 1 3 2 80 CPU The Z 80A CPU of the TS2068 operates at a clock frequency of 3 53 MHz Primary features of this CPU are 158 instructions Dual register set Two index registers On chip refresh logic The Z 80 CPU executes instructions by proceeding through a sequence of operations that include a instruction Op code fetching b READ or WRITE memory c READ or WRITE 1 0 d Acknowledge an interruption The basic clock period is referred to as a T time or state and three or more T states make up a machine cycl e In the 752068 each T time is approximately 283 nanoseconds 2 83 X 10 7 seconds Figure 2 1 3 1 illustrates the basic timing FIGURE 2 1 3 1 BASIC CPU TIMING EXAMPLE Machine C ycte M1 M2 M3 OP Code Fetch Memory Read IMemory Write instruction Cycle 2 1 3 1 Ad
139. it 7 Buffered Read Active Low Buffered CPU State Active Low Write Active Low Buffered Address Bus Bit 8 Address Bus Bit 7 Address Bus Bit 9 Address Bus Bit 6 Address Bus Bit 10 Address Bus Bit 5 Address Bus Bit 11 Address Bus Bit 4 Refresh Active Low Buffered Bank Enable Active Low Extension ROM Enable Active Low ROS Chip Select Active Low Dock Bank Enable Ground 6 0 TABLE 2 4 2 2 J4 SIGNAL ELECTRICAL CHARACTERISTICS S Z S sss OUTPUTS FROM TS2068 s ss s sss ss INPUTS TO 152068 SE CAPACI TI VE NPUT LOADING V 0L I LOAD V 0H I LOAD V IL V IH IN MAX CAPACITIVE MAX MAX MAX MIN LOADI NG MNEMONI C PF VOLTS VOLTS uA VOLTS VOLTS uA MAX PF A15B 30 0 5 1 8 2 4 10 A14B 30 0 5 1 8 2 4 10 A13B 30 0 5 1 8 2 4 10 Al 2 30 0 4 1 8 2 4 10 Al 0 4 1 8 2 4 10 A10 30 0 4 1 8 2 4 10 A9 30 0 4 1 8 2 4 10 A8 30 0 4 1 8 2 4 10 Al 30 0 4 1 8 2 4 10 A6 30 0 4 1 8 2 4 10 A5 30 0 4 1 8 2 4 10 A4 30 0 4 1 8 2 4 10 30 0 4 1 8 2 4 10 A2 30 0 4 1 8 2 4 10 Al 30 0 4 1 8 2 4 10 A0 30 0 4 1 8 2 4 A7RB 30 0 5 0 35 2 1 ROSCS 30 0 4 1 8 2 4 10 MREQB 0 5 1 8 2 4 10 RDB 30 0 5 1 8 2 4 10 ORQB 30 0 5 12 2 4 10 WRB 30 0 5 12 2 4 10 RFSHB 0 5 12 2 4 10 EXROM 30 0 5 12 2 4 10 ili 30 0 5 12 2 4 10 00 30 0 4 1 8 2 0 15 120 01 30 0 4 1 8 2 4 0 8 2 0 15 120 02 30 0 4 1 8 2 4 0 8 2 0 15 120 D3 30 0 4 1 8 2 4 0 8 2 0 15 120 D4 30 0 4 1 8 2 4
140. ithin the memory designated by the AROS Memory Select Specification as in use the Dock Bank will be enabled otherwise the machine code address is assumed to be in the Home Bank See Section 6 0 for details on known problems in this area of the code Obviously once control is transferred to the machine code in the AROS the ball is now in your court You could have additional machine code residing in the lower half of the Dock Bank memory space which you can now switch in You only have to know what you re about If and when you are ready to go back to 110 5 1 executing your BASIC program you must enable Chunks 0 3 in the Home Bank and have the stack and other Home Bank RAM in the proper state for return to the USR function code in the BASICInterpreter i e what it was when the USR function passed control to you The Autostart feature begins execution out of the BASIC AROS immediately after system initialization If the Autostart parameter is zero control will go to the BASIC Interpreter as if there were no cartridge installed although internal flags have been set noting that a BASIC AROS is present The cartridge will be started when you execute a RUN or GOTO Line Number command The final parameter in the overhead bytes allows you to reserve RAM beginning in Chunk 3 at Location 26688 6840H f or machi ne code and or machine code variables The designated number of bytes are reserved by the AROS support code prior to
141. le Appendix C contains descriptions and code listings of software packages supporting 64 and 80 Column modes Ot her Appendix C also contains software packages supporting the following video screen features 40 Column utilizes the 6 X 8 character set defined for 80 Colum Mode in normal mode May be combined with the Dual Screen package B Sprites supports movement of software defined objects and multi directional screen scrolling services in the Primary Display File You must create the actual bit map defining the shape of your sprite s but this package does the rest 5 3 Other Advanced Concepts 9 3 2 BASIC Interruption Fielding For a machine code program executing in the Home RAM you can intercept the 17 ms interruption for your own purposes by permanently enabling Chunk 0 in the Extension ROM Bank write a 1 to Port OF4H and always have Bit 7 of Port OFFH 1 and inserting at Location 25262 62AE Hex a branch to your own interruption handler Or if VIDMOD is not zero insert your branch instruction at Location 64110 FA6EH By doing this you are forcing the interruption to branch to the RAM and then bypassing the 05 RAM Interruption Handler see Sections 3 77 33 1 and 3 3 3 1 Because the Video Mode Change Service automatically updates internal branch addresses in the 08 RAM code when it is relocated between Chunk 3 and Chunk 7 you probably do not want to directly overlay the 05 RAM
142. llector a composite synch signal for the connected monitor To provide a separated Vertical synch pulse R5 and C3 filter the output of Ql to partially eliminate the Horizontal synch pulses which are shorter than the Vertical synch pulses The partially filtered inverted signal is re inverted by Q3 then R6 and C4 complete the elimination of the Horizontal synch pulses so that a separate Vertical synch pulse is supplied for the attached monitor Signals R G and B from connector pins 827 828 and B29 can be supplied directly to the attached monitor FIGURE 2 4 1 3 01 03 2 2907 EQUAL svDc 02 2N2222 OR EOUAL COMPUTER COMPOSITE SYNCH COMPOSITE TO MONITOR 831 o GNO TO MONITOR A30 432 SIGNAL GND B30 832 VERTICAL SYNCH TO MONITOR 027 828 0 9 G TO MONITOR 829 B 57 2 4 Cartridge Connector 4 The 152068 provides a 2 X 18 pin connector designated 4 on the schematic under the door at the front right of the console The table and figures listed below detail the mechanical functional and electrical requirements and limits of the J4 Cartridge Connector FI GURE TABLE TITLE Figure 2 4 2 1 J4 Mating PCB Mechanical Requirements Figure 2 4 2 2 J Signal Layout Table 2 4 2 1 4 Signal Definition Table 2 4 2 2 J Signal Electrical Characteristics 58 FIGURE 2 4 2 MATING PCB MECHANICAL REQUIREMENTS TOP VIEW WORKING POSI
143. meric or string arrays STKUSN 106 Stack Unsigned Number inputs a a6 floating point number onto the Calculator Stack from a series of ASCllcharacters addressed by CH ADD The first character is already in Reg A either deci mal point binary token or digit TABLE 3 3 3 2 TS 2068 FUNCTION DISPATCHER SERVICES continued SERVI CE SERVICE CODE DESCRIPTION STK A 107 I byte unsigned integer in A to top of Calculator Stack binary to floating point Loads 0 to B and A to C then executes STK BC STK BC 108 6CH 2 byte unsigned integer in BC to top of Calculator Stack binary to floating point NI NT 109 6DH Converts a series of ASCII digits pointed to by CH ADD into an unsigned floating point integer on the Calculator Stack First character is in A on entry Terminates when non digit found FP2BC 110 Pops top of Calculator Stack floating point number and puts in BC rounded to nearest integer Returns NZ if value is negative Returns C if number exceeded maximum 2 byte value 65535 Range 65535 to 165535 FP2A 111 6FH Pops top of Calculator Stack floating point number and puts in A rounded to nearest i nteger Returns NZ if value is negative Returns C if number exceeded maximum l byte value 255 Range 255 to 255 OUTPUT 112 70H outputs number on top of Cal cul ator Stack to currently selected channel via WRCH Converts from floating point to ASCII
144. n 1 141 3 MB RV2 ME Ur 2 t t CREATE_BITMAF ADDR t t CREATE_BI TMAF CE SUI CE TELNE CR NGL CB EXIT 3 1 3 t X 5 RRA LDIF 44 LEDR AND SBC Li Lo PCF POF PUSH PUSH LG CAL L LD Lo LD LD LD RLCA RRCA JR LDIR ADU JR LDODK AND SEC LD LU POP POF POP RET LD LL LD LU RL CA RRCA JR APD ft SKE CALL CFL LD EX CALL CFL Lp XUR A LL ANT LL Lf LE KL AR L RL ANO AR XOR L i JR LI RET SRI _ RANK 1 PUSH PISH LD ADD LD AUD EX LD C ME KVI HL DC Mi LUE HU BC 1x SRC_ADDR L ACO s INCREMENT FAINTER 1 DECREMENT FOINTER f STOKE NEW FOINTER VALUE IX SRCCADDER 1 H BC HL HL BC E CIX DEST RAN Boh ENABLE SELECT DEST RAN FROM STACI TC DEST C L IX DEST ADDR D IX DEST ADDR 1 L COIX BUF PTR H CIXeBUF PTR 1 MB RV2 HL RC MB UP2 HL RC IX DEST ADDR L tiF A lt O INCREMENT POINTER t DECREMENT POINTER STORE NEW POINTER VALUE CIX DEST ADDR 120 H RC HL BITMAF D H L sRESTORE REGISTERS z 1 SAVE START ADIR I X LENGTH B CIX LENGTH CO X DIRECTION CRP SUE HL CE_CONT HL EC GE T CHEIN B HL GE T CHUONI A Et 2
145. n Olego CA 92123 8 382 0 508 330 2 020 FOR 1 675 062 BOARD EE 6 12 oz per contact pair using a 1 575 062 flat test dimensions are in millimeters dimensione shown XX X are in inches FIGURE 2 4 1 2 P1 CONNECTOR SIGNAL LAYOUT COMPONENT SIDE TS1000 COMPATIBLE p t e 4 q SLOT een ee DZIS cone 106 am 1 n 11 2 WY 1 V 8 10 i 0 n 8 M 3 V Mw s 08 00 516 9 gt gt SPKR TAPE OUT 15y NOT USED SLOT A158 148 38 M 11 10 VIDEO SIG GND 5 F NOT USED NON COMPONENT SIDE VIEW FROM FRONT OF COMPUTER 54 TABLE 2 4 1 1 PI SIGNAL DEFINITION PIN SIGNAL NAME DESCRIPTION GND Signal Ground GND Signal Ground EAR EAR Input SPKR TAPE OUT Speaker Tape Output A7RB Refresh Address Bit 7 Buffered 157 15 Volts DC D7 Data Bus Bit 7 5 5 Volts DZIN Daisy In Not Connected Not Used Slot Slot DO Data Bus Bit 0 GND Power Ground D1 Data Bus Bit 1 GND Power Ground D2 Data Bus Bit 2 0 CPU Clock Inverted D6 Data Bus Bit 60 0 Address Bus Bit 0 DS Data Bus Bit 5 Al Address Bus Bit 1 D3 Data Bus Bit 3 A2 Address Bus Bit 2 D4 Data Bus Bit 4 Mdress Bus Bit 3 INT Interrupt Bequest Active Low
146. ng the count pattern count up count down of the 4 bit counter and by defining asingle cycle or repeat cycle pattern This envelope shape cycle control is contained in the lower 4 bits 83 80 of register R13 Each of these 4 bits controls a function in the envelope generator as illustrated in Figure 2 1 6 9 29 FIGURE 2 1 6 9 ENVELOPE SHAPE CYCLE CONTROL REGISTER R13 B7 B6 B5 B4 B3 B2 BO Function AN NOT USED y HOLD gt ALTERNATE To Envelope E TS gt ATTACK Generator gt CONTI NUE Z The definition of each function is as follows When set to logic 1 limits the envelope to one cycle holding HOLD ALTERNATE ATTACK CONTI NUE the last count of the envelope counter E3 EO either 0000 or 1111 depending on whether the envelope counter was in countdown or countup mode respectively When set to logic 1 the envelope counter reverses count direction up down after each cycle NOTE When both the Hold bit and the Alternate bit are ones the envelope counter is reset to its initial count before holding When set to logic 1 the envelope counter will count up attack from E3 EO 0000 to E3 EO 1111 when set to logic 0 the envelope counter will count down decay from 1111 to 0000 When set to logic 1 the cycle pattern will be as defined by the Hold bit when set to logic 0 the envelope generator will reset to 0000 after one cycle and
147. nge of noise frequencies from 3 6 kHz to 110 3 khz To calculate the value for the contents of the Noise Period register given the input clock and the desired output noise frequencies we simply rearrange the above equation yielding NP fCLOCK I6fN 10 Lr Cc CO Cc e 2 1 6 3 Mixer Control 1 0 Enable Register R7 Register 7 is a multi function Enable register which controls the three Noise Tone Mixers and the two general purpose 1 0 ports The Mixers as previously described combine the noise and tone frequencies for each of the three channels The determination of combining neither either both noise and tone frequencies on each channel is made by the state of bits B5 thru BO of R7 The direction input or output of the two general purpose 1 0 ports 10A and IOB is determined by the state of bits B7 and B6 of R7 Note that in the TS 2068 there is no second 1 0 Port B These functions are illustrated by Figure 2 1 6 4 and Tables 2 1 6 1 and 2 1 6 2 below FIGURE 2 1 6 4 MIXER CONTROL 1 0 ENABLE REGISTER R7 TABLE 2 1 6 1 110 ENABLE TRUTH TABLE NABLE TRUTH TABLE TONE ENABLE TRUTH Noise one tnabl ec B5 B4 B3 on Channel B2 Bl BO on Channel o gt gt gt gt 24 TABLE 2 1 6 2 0 PORT TRUTH TABLE R BITS 1 0 Port Status NOTE Disabling noise and tone does not turn off a channel Turning a channel off can only
148. nterruption via this mechanism and also plan to use the Video Mode Change Service it is recommended that you first invoke the service to remap the RAM and open the second display file then set Bit 6 of Port OFFH to inhibit the normal interruption and write your own routine s for subsequent changing of the video mode setting that do not involve remapping the RAM Inthis way you can maintain the value in Bit 6 6 5 OS RAM Routines Inpatching the 05 RAM routines care must be taken not to relocate CALL and JP instructions since this affects the modification of the code when it is moved between Chunks 3 and 7 All of the code containing actual addresses must be modified to reflect the relocation and this is done using a table in the Extension Since the table cannot be changed none of these instructions can be moved Also any CALL or JP instructions added must be modified by you when the code is relocated 6 5 1 Function Dispatcher For a variety of reasons such as conflict with use of the IX Register incorrect entries in the ROM Function Dispatcher Jump Table etc some Service Codes have been deleted from the Function Dispatcher table Table 3 3 4 2 n addition the following correction to the GET STATUS routine is required in order to successfully utilize the Function Dispatcher from a cartridge 129 6 5 2 GET STATUS Returns invalid memory selection status 6 6 6 6 5 5 5 5 4 5 for
149. o mode 32 bytes of pixel data plus 32 bytes of attributes by 32 memory accesses reading 2 bytes per access in RAM page mode i e the low order address bits are provided to the RAM once via RAS activation then the data byte is read during the first activation of CAS and the attribute byte is read during the second activation of CAS The page mode operation is completed by deactivating RAS See Fiq 2 1 8 2 The accessed pixel data is serially shifted out to the video generation circuitry at a rate of 1 bit each 142 nanoseconds 7 056 MHz resulting in the need to fetch a new data attribute pair each 1 134 microseconds during the horizontal scan time The shifted out pixel information is used to control the selection of the 3 paper color pixel 0 or 3 ink color pixelz1 bits to be qated out as the R G and B signals When FLASH is enabled by the attribute byte the INK and PAPER field information is swapped at the 1 879 Hz flash rate The R and B signals control the D to A converter which generates the proper U V and Y outputs for use by the 1889 to create composite video The address information provided to the RAM duri nq RAS and CAS times is as shown in Figure 2 1 8 2 This address generation logic explains the non sequential nature of the video display as described in Section 2 1 10 42 FIGURE 2 1 8 2 VI DEO DISPLAY PROCESSOR RAM ADDRESS GENERATI ON Normal Video Mode DISPLAY PIXEL DATA ADDRESS Address Bi
150. ober 1985 Bob Orrfelt anq Improvements NOTES 298 BRUNING 44 131 22870 3 5 1 0 AMP C44 USE OF THE TECHNICAL INFORMATION CONTAINED HEREIN IS AT USER S SOLE RISK WHILE THE INFORMATION WAS BELIEVED BE CORRECT AT ae Po wes THE TIME IT WAS PREPARED TIMEX COMPUTER CORPORATION OR ITS e CR11 N 8 gt IN4148 x 8 ICTU ke CR8 n CORE TDK UA78L12 EE 132 AFFILIATES ASSUME NO RESPONSIBILITY OR LIABILITY FOR THE SAFETY 12V OR PERFORMANCE OF ANY PRODUCT MANUFACTURED RELYING ON THE Q L2 1000 uF TECHNICAL DATA CONTAINED HEREIN OR ANY LIABILITY LOSS DAMAGE OPERATION 230 CR1 IN5821 SIGNAL OR EXPENSE SUSTAINED BY REASON OF ANY CLAIM THAT SUCH PRODUCTS T3v GND INFRINGE ANY PATENT OR OTHER INDUSTRIAL PROPERTY RIGHT H C56 RFSHB PIA 26 J4 32 MREQB PIA 17 44 18 IORQB 18 J4 19 WRB PiA 20 J4 23 RDB PlA 19 J4 21 A138 16 J4 4 PIB 15 44 7 11 A158 PIB 14 J4 16 7415245 20 NOTES UNLESS OTHERWISE SPECIFIED 1 ALL RESISTORS ARE 1 4 W 5 RATED IN OHMS 2 ALL CAPACITORS ARE RATED IN MICROFARADS 3 FOR 028128 INSERT W1 amp W2 FOR INSERT W3 amp W4 NOT USED CHANGES NEUE Cf ats NO N EF SHELL esce
151. ode 1 Bank Switching Data Transfer Services Function Dispatcher provides access to selected system routines via a Service Code input Inaddition portions of the Home Bank RAM are used for the machine stack the BASIC system variables the Printer Buffer and the Display Files Figure 1 1 3 shows the standard mapping of the Home Bank RAM and the mapping necessary when the second display file is to be used with the BASIC interpreter still functional The Video Mode Change Service routine makes these memory modifications Note that there is no direct support of the second display file via BASIC or in the system ROM 1 0 routines Figure 1 1 4 is a Flowchart of the System Initialization process P RAMT RAMTOP FIGURE 1 1 3 STANDARD MAPPING OF HOME BANK RAM UDG MACHIME COO VARIABLES OS RAM RESIDENT CODE MACHINE STACK SYSTEM VARIABLES PRINTER BUFFER A 1 Display File OS RAM RESIDENT CODE MACHINE STACK MACHINE CODE VARIABLES SYSTEM VARIABLES B 2 Display File P RAMT F7 COH RAMTOP FIGURE 1 1 4 SYSTEM INITIALIZATION POWER ON HOME ROM SET MAX 64K ADORESS SET MAX ADDRESS z RAMTOP Y NE W SET NEW FLAG N SAVE P RAMT INITIALIZE P RAMPT UOG PIP amp UDG PIP amp amp RASP RASP INITIALIZE SYSTEM RESTORE P RAMT VARIABLES UDG PIP amp RASP INITIALIZE MACHINE STACK INITIALIZE CHANS STREA
152. odes Location Standard 96 32 127 Home 20 7FH 3000 Address 100H in CHARS Std Graphics 16 128 143 Dynamically 80 Generated by Software Defined 11 144 164 Home RAM Graphics 90 Address in UDG 98 The screen output routine SENDTV is in Module 10 1 of the Home This routine is used for output to both the screen upper and lower and the dot matrix printer The following sequence illustrates the major operations involved in executing a PRINT A statement 1 Channel 2 is Selected normal assignment assumed loads CURCHL with pointer into CHANS area for Channel 2 first 2 bytes are address of Output Routine SENDTV clears printer and lower screen flags sets T to values based ATTR P current permanent attribute values are nsferred to the system variable used by the screen output routine If the PRINT statement contained temporary attribute controls they woul d override the settings established via Select The character code for A 65 41H is placed in Register and a RESTART 16 10H is executed WRCH This jumps to SENDCH in module EDIT of the Home ROM which oasses control to the SENDTV routine based on CURCHL 3 The registers are loaded from the System Variables with the current Column position S POSN and Display File address DF CC for the main screen 4 The character code is determined to be from the Standard charac
153. ommands They are lim ted to the 22 lines of the upper screen 256 X 176 pixels Figure 4 1 2 2 shows the internal representation used to designate row line and column positions See Section 2 1 10 for details on the organization of the Display Pixel and Attribute Files See Section 5 2 for details on software support necessary for the advanced video modes FIGURE 4 1 2 DISPLAY FILE ROW COLUMN NOTATION BASIC Parameters Internal Representation Line Row 0 24 18H 23 17H UPPER SCREEN SCREEN 100 4 1 3 2040 Dot Matrix Printer Character output to the 2040 Printer is handled by the same routine used for the screen SENDTV When the Printer Flagzl set by initialization for device P the pixel data is written into the Print Buffer instead of into the Display File There is no Attribute Byte The attributes OVER and INVERSE which are software controlled can be active Since the Print Buffer is always precleared to zeros OVER has no effect NVERSE works exactly as it does for the screen i e INK pixels are zero and PAPER pixels are 1 The Print Buffer is located at 23296 5B00H and is 256 OOH bytes long the data needed to print one line of 32 characters each character comprised of 8 bytes 8 X 8 pi xel s character The buffer is cleared to zeros and the flag PRLEFT set to zero at power on time or execution of a NEW command PRLEFT flag is set to 1 whenever pixel data is written to the
154. omplete NZ Set DzCHAR KEY D 16n 24 D 27h 39 D FF 1 lt swaP BEE D NEW KEY Bit Found E PREV KEY Symbol Shift amp CAP Shift amp No Keys FF or PREV One Other Key One Other Key Or One Key KEY D Z Set 2 Set 7 Set D 18h D 18h O 27h D FFh ds dpc SYM Shit CAP Shift E Key ELSE SET Z E Key E KEY Z SYM Shift amp One Character Or Just One Character D FF Or SYM Shift E CHAR Code NZ tf Two CHAR Keys 96 K BASE Find BASE Code For Key Key Code SYM SHIFT ONE CHAR or Jus One Char Key Code YM SHIFTY w No Chat RE TURN O NC Key Code gt 27h Cz O NC GET XLATE BYTE ADDRESSED BY HL ED cz A CODE K lt 30h 39n lt K lt gt lt gt lt gt or L K or L KTAB4 HL KTABBe HL M KTAB2 HL KTABS HL A 4Fh A lt KTAB4 gt HL KTAB3 HL LCC34 FETCH XLATE VALUE FROM AtAS5Sh CONVERT TO KEYWORD DIGIT 1 8 Cin G Mode HL A A A 86h A 20h A CONVERT TO CONVERT CONVERT TO TO SET SYMBOL M MOSAICS FG COLOR A 20h A RETURN CONVERT TO LOWER CASE BRIGHT OR NBRIGHT RETURN Others A FEh A CONVERT TO FLASH OR UNFLASH CONVERT TO INVERSE RETURN 97 4 1 2 Video Screen The TS 2068 system software supports I O in the pri mary display file onl
155. on the Calculator Stack which is located between STKBOT and STKEND see Appendix C of the TS 2068 User Manual An effort has been made to include information on register usage and functionality but some of the ROM routines are so tightly tied to the BASIC Interpreter that they would require analysis which is beyond the scope of this document These have been flagged with an Asterisk but included in the list for documentation purposes only Most of the routines which are directly implementing a BASIC command or function have two different action sequences based on the INTPT Flag Bit 7 of FLAGS which distinguishes syntax checking Flagz0 from actual execution Flag l Inorder to use the Function Dispatcher first set up any memory and stack both machine and or calculator locations as if invoking the desired service directly Then push the parameter s for the Dispatcher on the machine stack in the order outlined below Fi nal ly set up the registers as if invoking the desired service directly and call the Dispatcher based on its current location Chunk 3 if VI DMODzO or Chunk 7 if VIDMOD has a non zero value PRM OUT 16 bits Number of bytes of parameter data being passed on the stack to the specified Service number of stack pushes 2 Zero if no parameters being passed E g to pass 4 bytes 76 LD HL 4 PUSH HL This parameter is passed to the Dispatcher only if the Jump Flag SVC CODE Bit 15 is n
156. once every 1 60th of a second ADDRESS LABEL USE RETURN 5 00 KSTATE DEBOUNCE CNT O LUK2 co1 REPEAT CNT O sco2 CHARACTER O s 5 04 kstater LE 5cos5 7 CNT 1 scoe REPEAT CNT 1 CREHENT DE N 5 07 CHARACTER 1 OEBOUNCE CNT scos INITIAL DEBOUNCE DEBOUNCE 9 Yes FFh KSTATE LUK3 FIGURE 4 1 1 2 CID DE RESULT OF K SCAN Y os FLOWCHARTS KT means 4 K BASE CHAR TS 2068 KEYBOARD ROUTINES Pd C or NC NC 0 RETURN 94 Sht 2 RESET REPEAT DELETION FLAG d X 1 5 DEBOUNCE X One Keystore X21 Location le Empty DECREMENT No LUKS REPEAT CNT X 8 Neither Key OzK STATE 5COO Yes M Empty KEY 1 STATE 4 5CO4 RETURN No REPEAT CNT 5 DEBOUNCE CNT X 5CO1 or 5COS Not Time x g To Repeat y RETURN Yes SETUP FOR CH CODE REPPER REPEAT CNT X E Keystroke tS KEY BEING HELO DELETE OELAY LOOP No LUK57 KEYSTROKE LAST K From 5C03 or 5C07 SET KEY HIT T ZFh A Position Code DE FEFE A7 0 FE 15 8 zREGB INVERT DATA FOR 5 BITS Produces Low Active Date Bits For Keys Pressed In Row Addressed M S MJ Low Active Address Bit L 1 L Next Row lt gt RETURN ds Too Many Keys Scan C
157. one Generators Produce the basic square wave tone frequencies for each channel A B C Noise Generator Produces a frequency modulated pseudo random pu se width square wave output Mixers Combine the outputs of the Tone Generators and the Noise Generator One for each channel A B Amplitude Control Provides the D A Converters with either a fixed or variable amplitude pattern The fixed amplitude is under direct CPU control the variable amplitude is accomplished by using the output of the Envelope Generator Envelope Generator Produces an envelope pattern which can be used to amplitude modulate the output of each Mixer D A Converters The three D A Converters each produce up to a 16 1 output signal as determined by the Amplitude Control An additional register is shown in the PSG Block Diagram Figure 2 1 6 1 which has nothing directly to do with the production of sound this is the 1 0 Port A Data to from the CPU may be read written to from the 8 bit 1 0 Port without affecting any other function of the PSG The TS 2068 uses the 1 0 Port to access the joysticks 2 1 6 1 Tone Generator Control Registers 10 19 The frequency of each square wave generated by the three Tone Generators one each for Channels A B and is obtained in the PSG by first counting down the input clock by 16 then by further counting down the result by the programed 12 bit Tone Period val ue Each 12 bit value is obtained in the
158. ot set NOTE This parameter refers to machine Stack entries only not to the Calculator Stack PRM IN 16 bits Number of bytes of parameter data to be passed back from the specified Service number of stack pushes 2 Zero if no parameters to be passed back This parameter is passed to the Dispatcher only if the Jump Flag SVC CODE Bit 15 is not set NOTE This parameter refers to machine stack entries only not to the Calculator Stack SVC CODE 16 bits Bits 0 14 identify the Service to be invoked Bit 15 Jump Flag is set if no return is desired jump to Service rather than call Bit 15 is zero if return is desired E g to call K SCAN using Service Code 136 LD 136 or LD HL 88H PUSH HL PUSH HL Addendum To TS 2068 Function Dispatcher Services On page 84 COLOR and HIFLSH service codes 85 and 86 cannot always be accessed through the Function Dis patcher due to resetting of the carry flag by the FD COLOR may be accessed by setting the registers as de scribed in the manual and then coding CALL 23DE HIFLSH can be accessed similarly by coding CALL 2410 77 SERVI CE GET STATUS GET NUMBER UPD K PARP BEEP DUMP SENDTV SETAT ATTBYT ATTS CLLHS CLS DUMPPR TABLE 3 3 4 2 TS 2068 FUNCTION DISPATCHER SERVICES SERVICE CODE 1 14 15 16 24 10 18H 25 26 27 28 29 30 31 32 33 34 35 13 1 009 0EH 0FH 19H
159. oth ROM and RAM STRMS is a 38 byte table 2 bytes for each of the 19 channel s located in the System Variables area beginning at 23568 5C10H It is initialized at power on or NEW to the following values LOCATION VALUE 5Cl0 0100 Channel 3 5c12 0600 Channel 2 Copied from 5c14 0600 Channel 1 SMINIT in 5 16 0100 Channel 0 module EDIT 5018 0100 Channel 1 of the Home 5CIA 0600 Channel 2 ROM 5CIC 1000 Channel 3 5CIE 0000 Channel 4 5634 0000 Channel 15 This table is accessed using Ch 2 16H as an index added to 5C00H The 2 byte value in the table is an index into the CHANS area of memory which contains the addresses of the 1 0 routines for the selected channel If the 2 byte value is zero the Channel is closed The STRMS table is modified via the OPEN and CLOSE commands When a Channel is OPENed the device specification is used to obtain the 2 byte value to be inserted This value is taken from the table STRMINIT in module EDIT of the Home ROM When Channels 0 through 3 are CLOSEed the values are restored to those used at power on ti me All others are cleared to zero The CHANS System Variable at 23631 5C4FH contains the address of a 2l hbyte table initialized at power on or execution of a NEW command to support stream 1 0 to the four standard system devices K S and P J Each table entry is 5 bytes long and is indexed by the value obtained from the STRMS table added to CHA
160. other routines 70 0000 UO 0006 0008 000B 000E 0010 IE 0014 0017 0018 00111 0016 OOlF 0022 0024 0026 0028 002A 0023 002C 0020 002 002F QUSS 0033 0035 0937 0034 003C 0035 0933F OOFC 0068 OE8E 5CC2 21 18 21 18 2 F5 CD Fl FE 20 22 JA 03 08 CB 03 FB c9 00 F3 F5 08 CB 03 D8 22 03 F1 9 00 0020 17 0068 0020 OF 0020 FF FF FF F4 002C F4 EXTENSION ROM o N OC A uo N au FIGURE 3 2 2 2 R W CHNG VID VI DMOD se READTP WRITTP t CHGVI D EXIT HSSAVE IFRIN INTERFACE ROUTINE LO CALL JR LO CALL LD CALL 11 E QU OOFCH E QU 0068H E QU OE8EH EQU 5CC2H HL R TAPE FRTN EXIT HL W_TAPE If RTN EXIT HL CHNG VID AF FQTN AF 80H NZ EXIT VIDMOD A A HSSAVE OF4H A OFFH A AF A OFFH 1 HSSAVE A A 1 OF4H A AF HL x lt m EXTENSION ROM INTERFACE ROUTINE READ TAPE ROUTINE WRITE TAPE ROUTINE CHANGE VIDEO MODE ROUTINE VIDEO MODE SYSTEM VARI ABLE CALL READTP WITH REGISTERS SET UP FOR R TAPE ROUTINE ADDRESS TO HL ENABLE EXT EXECUTE QTN RESTORE HOME BANK AND RETURN CALL WRITETP
161. ovides a 2 X 32 pin connector which is designated as Pl at the right rear corner of the console The mechanical functional and electrical requirements of the system buss connector are detailed in the following tables and figures FI GURE TABLE TITLE Figure 2 4 1 1 Pl Mating Connector Mechanical Requirements Figure 2 4 1 2 Pl Signal Layout Table 2 4 1 1 M Signal Definition Table 2 4 1 2 PI Signal Electrical Characteristics FIGURE 2 4 1 1 P MATING CONNECTOR MECHANICAL REQUI REMENTS 64 PIN CONNECTOR L MOLDED IN KEY 1 SCALE NONE JA 636 025 SQUARE Section X X 53 16 GND 516 GNO SPECIFICATIONS tjerssQae INSULATOR MATERIAL Insulator body shall be 30 525 0 127 375 005 glese filled polyester and shell meet UL94V O requirements 2 CONTACT MATERIAL Contact material shall be phosphor bronze 13 97 20 284 650 4 0 10 CONTACT FINISH Contacts shall be selectively plated with gold 2 54 100 0 00038 000015 thick over niche on contact surfaces 3 EQUAL vlde e AT INSERTION FORCE insertion forces shali be 170 1 283 5 grams 2 64 100 78 74 3 100 6 10 oz per contact pair using a 1 575 062 test blade WITHDRAWAL FORCE Withdrawal forces shall be 226 8 340 2 grams NORMAL FORCE Normal force shall be 85 05 grams 3 ox minimum when mated with a 1 37 054 thick test board PURCHASE FROM Diego Microtronics INC Sa
162. ow BAN ENABLE CALL CFL LD LD Ln CALL L LD IN CPL Ln LD IN AND CFL RL CA LU IN CFL ANT CIF UI LE FOF Fer KFT ADER MLI Lo LD IRL TNZ INC LD XOR SCF RLA DUN POP RET PLUSH PUSH CALL LD LD AND JR LD LD CALL AND JR DJNZ IN CPL AND AR DEC AR IN AND LO IN AND RRCA AND R LD JR FFH IR X UR LD FOP FOP BANKS PUSH PUSH PUSH PUSH LD 143 READ_BC_REG C D STALL STA G READ BS REGQ B E GS EXIT BC O GS EXIT DKHSPT R 4 C 05 A HREXFT R 2 A A H SHIFT BC BC DE GET CHUN READ HE SREAD STATUS NYBBLES RETURN O FOR HOME BANI STATUS 1 RETURN DOCK STATUS CLEAR ALL BITS EXCEPT 7 PUT ACTIVE LOW BIT IN BIT URES TORO n ALE F THONE NUMBER BITS UF t H G SHIFT H RIGHT BIT CREATE ROLLING 1 t LEFT CHR NUMEERe1 TIMES THE 1 COMES FROM THE CARRY 1 FLAG RESTORE GET BANK NUMBER ADDR HL BANK NUMBERS A t ZAVE REGS BSL LMAX LARGEST BANK NUMBER A Z ON RD DOCK B E B GET STATUS 2 GN_CHECK DKHSPT 2 GN DOCK 2 GN_HOME A HREXPT A DKHSPT 1
163. product manufactured relying on the technical data contained herein Of any Da t so Loss damage or expense sustained by reason of any claim that such products infringe any patent or other industrial property right The Second Edrtron or this Technical Manual has been re edited by Tim Woods Special thanks to Bob Orrfelt and Dave Clifford for technical assistance If you would like to receive information on a magazine and other publications for the Timex Sinclair 2068 direct your inquiry to Time Designs Magazine Company 29722 Hult Rd COLEG B 97017 Timex Sinclair 2068 Technical Manual 2nd Edition Copyright 1986 by the Time Designs Magazine Company Reproduction of this document in whole or in part by any means without expressed written permission from Tlme Designs Is prohibited by law This manual was printed by Toad Litho Printing and Composition Oregon City OR 97045 1 0 2 0 2 1 2 2 2 3 2 4 3 0 3 1 TARLE OF CONTENTS INTRODUCTION TS 2068 Overview 1 1 1 1 Hardware Overview 112 System Software Overview ld Cartridge Software Overview HARDWARE GUIDE 7 Major Hardware Functions 7 252124 Adapter 2 1 2 Voltage Regulation 2 1 3 280A CPU 2 1 4 ROM 2 1 5 32K RAM 2 1 6 Programmable Sound Generator 2 1 7 Joystick Port 2 1 8 Control Logic 2 1 9 Keyboard 2 1 10 16K Video Display RAM 25111 Video Generation 2 1 12 Cassette 1 0 2 1 13 Port Map Schematic see inside
164. program lines and DATA statements and when executing a USR function otherwise the entire Home Bank is enabled while executing in the BASIC Interpreter There is no support for User Defined Functions which insert the expanded definition parameters directly into the program and then require search of the program area to find these parameters whenever a function is invoked See Section 5 1 Cartridge Software Hardware for additional details on BASIC AROS 66 3 2 1 3 3 2 2 Extension 3528244 General The balance of the Home ROM contains the BASIC Interpreter and standard 1 0 routines with the exception of the cassette 1 0 which is in the Extension ROM The bit map table for the standard character set is located at the end of the Home ROM from location 15616 to 16383 3D00H to 3FFFH The address of this table minus 256 100 is contained in the System Variable CHARS 3C00H The Home ROM routines accessible via the Function Dispatcher are described in Table 3 3 4 2 See Appendix A for the ROM Maps giving the ROM addresses of these routines ROM Fixed Entry Points Extension ROM Location 0 contains code to pass control to the initialization code in the Home ROM Figure 1 1 4 Extension ROM Location 56 38H is the interruption fielder Control is passed to the System RAM code See Section 3 3 3 to bank switch to the Home Bank and call the interruption service routines after which the state of the machine i
165. re used to control and access the Sound Generator and the Joysticks Details of the registers available via these ports is contained f n Sections 2 1 6 and 2 1 7 2 1 13 5 Horizontal Select Register Port HSR addressed via Port is used in the control of the Bank Switching logic as detailed fn Section 2 1 8 Each bit when set enables the corresponding 8K memory chunk in either the Dock Bank Port FF Bit 7 0 or the Extension ROM Bank Port FF Bit 7 1 The HSR must be set to all zeroes in order to enable the entf re Home Bank 2 2 Schematic Diagram Appendfx D contains adetailed schematic diagram of the TS 2068 2 3 Unit Absolute Ratings FUNCTI ON DESCRI PTI ON MIN MAX T Storage Temperature 40 650 VAC AC Line Voltage 105v 130v Ta Operating Ambient Temp 0 4 0c Vf n Voltage on any Logic 0 3v 5 3v Pin Vfn EAR EAR input Peak AC 2 0v 5 0v Vdc IN Input DC Voltage 14 75V 26V 2 4 Interfaces and Connectors The TS2068 has a number of specialized interfaces that are accessible vi a the following connectors CONNECTOR TYPE LOCATI ON System Bus 2X32 Card Edge Right Rear Cartridge 2X18 Card Edge Under TCC door MI C 1 8 Mini Phone Rear EAR 1 8 Mini Phone Rear Player 1 Joystick 9 pin D Left Side Player 2 Joystick 9 pin D Right Side Moni tor RCA Phono Rear TV RCA Phono Rear Keyboard 14 pi n SIP Inside Left Rear AC Adapter Rear 52 2 4 1 System Bus Connector Pl The TS2068 pr
166. ribes the known problems in the TS 2068 System Software and gives corrections or work arounds where these have been defined 6 1 LROS and Autostart Machine Code AROS 6 1 1 If youwill be using the System ROM Keyboard routines and accessing the input character code from system variable LAST K 5C08H you must initialize the TS 2068 to L mode by setting the system variable MODE at 23617 5C41H to zero and setting Bit 3 of FLAGS 23611 563BH to 1 The TS 2068 is in mode when control is passed from System Initialization to the Cartridge Keyword Token codes will be placed in LAST K instead of character codes 6 1 2 If you will be using the System ROM Calculator routines RESTART 40 28H or any ROM routines that invoke them you must initialize the System Variable YEM by doing the following LD 5C92H Set HL MEMBOT LD 5C68H HL Initialize MEM 6 1 3 Chunk 3 must not be designated as in use by the Cartridge Memory Selection Specification byte This will cause deselection of the bank switching code prior to completion of the transfer of control to the cartridge starting address Once control has been transferred the cartridge code may then enable Chunk 3 in the Dock Bank if desired See Section 5 1 6 1 4 No entry is made in the System Configuration Table for an RROS if an LROS is present This means that an LROS designed to support either RAM based or cartridge based applications must include code for detection of
167. ribute byte value controlling screen pixel position based on parameters on Calculator Stack X Y RND 97 61H RND function Uses value in SEED to generate a pseudo random number which is placed on the Calculator Stack Floating Point number F PI 98 62H Plfunction Places value of PI on Calculator Stack 85 TABLE 3 3 3 2 TS2068 FUNCTION DISPATCHER SERVICES continued SERVI CE SERVICE CODE DESCRI PTI ON F INKY 99 63H INKEY function cans keyboard and puts character code byte in WORKSP if key detected In any case pushes Regs AEDCB onto Calculator Stack BC 0 if no input if char code stored DE address of char code byte FIND N 100 64H Find Variable Searches Variables area for match against identifier pointed to by CH ADD Adjusts bit NO of FLAGS Bit 6 for type l numeric Ozsstring Al so used to find f or mal parameters for User Defined Functions PSHSTR 101 65H Push String Clears bit NO of FLAGS and pushes Regs AEDCB onto Cal cul ator Stack adjusting STKNXT upwards DE contains address of string BC contains length PAEDCB 102 66H Same code as for PSHSTR but preserves state of bit NO of FLAGS Bit 6 LET 103 67H LET command Processes existing or creates new variables POPSTR 104 68H Pop String Pops end of Cal cul ator Stack STKNXT 1 through STKNXT 5 to Regs BCDEA adjusting STKNXT downwards DIM 105 69H DIM statement Creates initializes nu
168. ridge Bank This memory is selectable as eight 8K chunks with the Home Bank being enabled by default i e any chunk not selected in the Extension or Dock Bank is automatically enabled in the Home Bank Memory selection and 1 0 are controlled via the 1 0 ports These topics are covered in detail in later sections FIGURE 1 1 1 TS 2068 SYSTEM BLOCK DIAGRAM 12V VOLTAGE oo eee ur GND 16K 8K Data Data k Hr lA spill lt gt lt gt Address Address eese gro Tq CT SLE TRI Control Control 3 579546 MHZ T MER ATOR Ao OC JOYSTICKS CRYSTAL FIGURE l i 2 TS 2068 STANDARD MEMORY CONFI GURATI ON CHUNK ADDRE FFFFH 7 E960 6 CO96H 5 09e UP TO 64K 8 Ful 64K ddr s amp ng space not normally utilized 3 6000H See Section 5 1 2 4000H 1 2900H OOOH HOME BANK EXTENSION BANK BANK 255 BANK 254 BANK 1 1 2 System Software Overview The TS2068 System Software resides in the Home ROM the Extension ROM and dedicated It supports the following functions System Initialization BASIC Interpreter including BASIC cartridge support BASIC 1 0 for Standard Peripherals keyboard video screen 2040 32 col dot matrix printer cassette tape joysticks Software generated sound BEEP oprogrammable sound chip SOUND o O O O O O Video Mode Change Service Interruption Servicing Z80 Int M
169. rmation With Ag A7 F6h During in inetruction 34 2 1 8 Control Logic The control logic of the TS2068 is primarily a Standard Cell Logic Device in a 68 pin JEDEC leaded carrier package and includes the following major functions SECTI ON FUNCTI ON 2 1 8 1 Bank Selection Logic 1 80 Clock Generation 2 1 8 3 Display Ti mi ng Display File Access Attribute Control and Pixel Data Serial Shift 2 1 8 4 Interruption Generation Output See Section 2 1 13 2 CASSETTE 1 0 See Section 2 1 12 Additionally Table 2 1 8 1 provides a description of the function of each SCLD 1 0 pin See the System Schematic in Appendix D for pin numbering 2 1 8 1 Bank Selection Logic 152068 is 7 80 based computer therefore it can directly address only 64K bytes of memory via its 16 bit address Additionally since the Z 80 has no relocation or indirection capability the conventional technique of extending the memory space available to the Z 80 is bank switching The TS2068 provides extended bank switching by allowing selection of memory in 8K chunks which are identified by bank number and chunk number as illustrated in Figure 2 1 8 1 for the internal bank selection logic The externally sourced BE Bank Enable signal can be used by external logic to disable the internally controlled memories As shown in Figure 2 1 8 1 1 The cartridge is selected on a memory access with a Port FF bit 7 0 b
170. ry Chunk Spec is written to Port by the Sank Enable code execution will continue from that point in Chunk 3 in the Dock Bank with the Stack Pointer addressing ROM An LROS is Z80 machine code and is in complete control of the TS 2068 hardware after transfer to the starting address has been made It can directly implement an application or it 106 can support multiple applications by implementing a language other than BASIC An AR0S dependent on such an LROS would have to be part of the same cartridge since there is only one cartridge connector Interruption Mode 1 has been set hy the TS 2068 and interruptions are enahled prior to passing control to the LROS starting address therefore the LROS must contain appropriate code at location 56 38H to cover the case where the interruption occurs after Chunk 0 in the Dock Bank has been enabled hut before any action by the software cartridge to disable the interruption has been taken Once control is transferred the LROS may then disable the standard TS 2068 interruption by setting hit 6 of Port FFH mask the interruption by executing a Dl instruction or set a different Interruption Mode It may change the location of the Machine Stack It may also change the memory selection hy writing to Port OF4H with each bit set to 1 for the corresponding chunk to he enabled in the Dock Bank high active format or 0 to he enabled in the Home Bank Thus an LROS may contain code in Chunk 3 hu
171. ry selection is set to Home Bank To activate row address strobe for display memory only during memory read write refresh and display read TABLE 2 1 8 1 SCLD 1 0 PIN FUNCTI ON DEFINITIONS continued DI RECTI ON OF SCLD SYMBOL NAME N OUT FUNCTI ON CASI Column Address out To activate column address strobe Strobe for display memory only 2nd 16K during me mor y read write and display read CASZ Column Address out To activate column address strobe Strobe 2 for Home Bank RAM 3rd 16K CAS3 Column Address out To activate column address strobe Strobe 3 for Home Bank RAM 4th 16K DRAMWE Dynamic RAM out When active low enables a write Write Enable into the display RAM only MUX Mux Control of out Mux control to 74L5157 amp UII RAM Address to multiplex the row and column addresses to all dynamic RAM s V Chroma Vector V out Color vector level for quadrature R Y input to video modulator Y Lumi nance Y out Lumi nance brightness control evel RD Read to CPU In CPU is reading from a memory or I O location WR Write from CPU In CPU is writing to a memory or 1 0 location MREQ Memory Request In CPU is requesting access to a memory location to read or write TORO 1 0 Request In CPU is requesting access to an 1 0 location to read or write 39 SYMBOL RFSH Tape n ROSCS SPKR TAPE OUT BDI R BCI TABLE 2 1 8 1 SCLD 1 0 PIN FUNCTION DEFI NI TI ONS NAME Refresh Tape Input Bank Ena
172. s Mode is assumed to be active and the routine is finished The memory locations defined as ATTR and SAVECO are for illustration purposes only LD Get Pixel Position AND O Leftmost MSB 7 Rightmost LSB LD B A Use as Control Count INC B B 8 LD 000000018 Bit Mask LOOP RRCA Rotate Mask Bit 0 LOOP to Proper Position OR HL OR Bit into DF LD A 20H OR H Set Bit 13 for DF2 LD H A HL Attribute File LD ATTR Get Attribute Byte LD HL Update Attribute File POP BC Original X Y to BC Regs RET Repetitive calls to this routine with the appropriate X Y Coordinate values will draw on the screen The System ROM routines for drawing lines and circles calculate the successive X Y Coordinate values and use common low level routines similar to the above to place each pixel in the display file 64 Column Mode Inthis mode set by writing to Port OFFH with Bits 0 2 6 Bits and 2 set and Bits 3 5 selecting ink color 0 7 the pixel data portions of the two display files are merged by the hardware on an alternating column basis to produce 64 columns across the screen All even columns 0 2 4 62 are derived from the primary display file and all odd columns 63 derived from the second display file There are still 24 lines vertically from top to bottom The attributes are controlled by bits 3 5 written to Port FFH selecting one of eight ink paper combi nati ons The Bright and Flash
173. s restored and control returns to the interrupted process Figure 3 2 2 shows the Extension ROM Interruption Fielder code 3 2 2 2 General The balance of the Extension ROM contains the following major components Final Phase of System Initialization See Figure 1 1 4 Cassette tape 1 0 see Section 4 2 Change Video Mode Service 05 RAM routines including the Function Dispatcher copied to RAM at System Initialization see Section 3 3 3 Function Dispatcher Jump Table 67 FIGURE 3 2 2 1 Extension ROM Interruption Fielder LOCAT ION OBJECT CODE SOURCE CODE COMMENTS 0038 F5 PUSH AF Save AF 0039 F3 DI Disable Ints 003A 3AC25C LD A VIDMOD Test Vidmod 003D A7 AND 003E 00 NOP 003F 2804 JR Z CHK3 Vi dmo d 0 0041 FI POP AF Restore AF 0042 C36EFA JP INT7 Chunk 7 if Vidmod not 0 0045 CHK3 POP AF Restore AF 0046 C3AE62 JP INT3 Chunk 3 if Vidmod 0 3 2 2 3 Video Mode Change Service The routine CHNG VID takes as input a single byte in Register3 which designates the desired video mode as shown in Table 3 2 2 1 Al non zero values involve access to the second display file located at 6000H 7AFFH When the mode change requires remapping of the RAM see Figure 1 1 3 the necessary relocation BASIC program machine stack 0S RAM code UDG area etc and modifications system variables RAM code internal addresses stack pointer etc are done by this service The desired video mode is written
174. set which added to the starting address results in a Having the display file we now insert the 8 bytes of pixel data for incrementing the display file address by is easily done by simply register of the register following routine is the desired position in the display file 118 The table lt assumes LD 8 Set Scan Count LOOP LD A Dd Get pixel pattern LD HL A Write to Display File INC DE Next pixel Pattern byte INC H Next DF Position 100H 0 NZ LOOP Continue for 8 Scan Rows Finally we must update the Attribute Byte controlling the updated character position The following sample algorithm will formulate the Attribute File address given the address of any of the scan rows of the character position We will assume we have saved off the starting display file address and now have it in Register Pair HL GETATT LD A H MSB of DF Address RRCA Shift right circular RRCA to get Bits 3 amp 4 Block RRCA to positions 00 AND 3 Clear other bits OR 58H OR in Attr File Base Adrs LD H Update MSB NOTE The LSB is the same as for the pixel data Using our first example with a Display File address of 5037H the Attribute File address would be 5437H The second example was using 64 Column Mode which does not require attribute file update attributes determined by video mode setting See Section 5 2 2 for a sample algorithm to formulate the display file address for X Y pixel coordinates The above routine for calcul
175. t 15 14 13 12 11 10 9 8 6 5 4 3 2 1 J Range Bg 1 gf R Q M L 0 N I H G F D 4000H eS ee 57FFH CASIA R S DISPLAY ATTRI BUTE ADDRESS Address Bit 15 14 13 12 11 I 8 6 5 4 j 2 7 Range 8 1 g 1 1 8 R 0 0 N I H G F D 5800H 222 SAFFH CAS 1B RAS VIDEO TIMING COUNTER CHAIN MSB LSB Y PIXEL LINE LINE 8Bit Group COLUMN s R Q P 0 N M T K J E 1V1de by cC WV Dy J1vide by IC 1 764 Counter Counter k 60 1145 Hz 15 75 KHz 14 112 Vert Sync Horiz Sweep MHz 8 43 2 1 8 4 Interruption Generation 17 ms During the vertical blanking interval once each 15 635 ms the SCLD if enabled by the INTEN bit Bit 6 of 1 0 Port FFH activates the INT signal which directly connects to the INT input to the 280 A CPU maskable interruption can then occur as described in Section 2 1 3 7 if enabled 2 1 9 Keyboard The keyboard for the TS 2068 has forty two 42 hard keys typewriter style wi th tactile f eel utilizing an over dead center type of rubber spring pad and a carbon pill that hits the P C board just under the keyboard to short out pair of closely placed precious metal contacts The read out matrix is an eight by five cross point switching as shown in Figure 2 1 9 1 Each switch closure connects one of the eight high order address lines by going low through a diode to one of the five input lines to the SCLD through KB4 Scanning is by software algorithm as described in Section 4 1 1
176. t it should be enabled after the OS RAM code has finished execution Now that your LROS is in the driver s seat you are on your own Some important points to remember when mapping your Dock Bank memory and doing bank switching are The Display RAM is in Home Bank Chunk 2 for the primary display file and Chunk 3 for the second display file This memory is accessed independently by the video hardware The software only needs to enable it when actually reading or writing it 2 Dock Bank and Extension ROM Bank are mutually exclusive since they share the Horizontal Select Register in Port F4H You will need a routine in the Home Bank RAM to do any switching between the two You must also be careful to have the appropriate Home Bank Chunks enabled which are referenced by the Extension ROM code e g the System Variables in Chunk 2 or possibly the bank switching code in Chunk 3 Some interesting switching routines can be constructed by having parallel code in shadowing chunks of memory to take advantage of the instant switch in execution from one hank to another when the memory selection is made E g aroutine in the Dock Bank ROM in Chunk 6 could push a Home Bank address on the stack write to Port F4H enabling Chunk 6 and any other desired chunks in the Home Bank by deselecting them in the Dock and have code at the next sequential instruction address in Home Bank RAM Chunk 6 to continue the path A Return 107 instruc
177. ted to the 12 bytes for software cartridge identification see Section 5 1 for details of the LROS and AROS Overhead Bytes 3 3 3 Machine Stack The TS 2068 reserves 512 200H bytes of RAM for the Machine Stack The Machine Stack pointer is initialized to a value of 6200H value also in System Variable MSTBOT the pointer is decremented as items are pushed onto the stack the pointer may also be modified directly by software While the area reserved for the stack extends to 6000H there is no actual check made to enforce this limit Note that the Machine Stack is located in the same memory area as the second display file The CHNG VID routine relocates the stack to the memory area from OF7COH to OFBBFH and modifies the Stack Pointer and MSTBOT OF8COH as well as other affected system variables when initializing the second display file See Section 3 252535 3 3 4 05 RAM Routi nes The code for the following Operating System functions is copied from the Extension ROM to Chunk 3 of the RAM at System initialization time Since this is in the same memory area as the second display file this code must be relocated along with the machine stack if the second display file is to be used The CHNG VID routine does the necessary relocation and modifications Section 3 2 2 3 12 Because this code is not in a fixed location access to the 05 RAM routines is conditional on the current video mode The standard technique employed is to
178. ter set so the registers are loaded with the address from CHARS and the offset to the pixel pattern for A is calculated using the character code X 8 shift left 3 places 2 The first pixel row 8X1 from the character table is copied to the display file The character table address is incremented by 1 and the display file address is incremented by 256 1 00H The next pixel row 8X1 is copied to the display file This process is repeated until the 8 pixel rows have been copied Masking of the data going into the display file is done based on the flags from P FLAG thus controlling the OVER and INVERSE attributes 6 The attribute byte controlling the character position just written is updated based on the value in ATTR T and other flags 99 1 variables S POSN and DF CC are updated to reflect the nexfscreen position and return is made from the WRCH operation Inthe above sequence if the print position for the had started a new line following the 22 lines of the main screen the SCROLL prompt would have been outputted to the lower screen and assuming a positive response the upper screen would be scrolled up 1 line a blank line inserted at the bottom of the upper screen and the printed at the start of the new line Graphics 1 0 using pixel coordinates is supported in the primary display file by the PLOT DRAW and CIRCLE commands The Home ROM module GRAPHS contains the major routines which implement these c
179. th a NOP and do the enable at a more appropriate place in your own code 6 5 6 GET NUMBER Always returns the Dock Bank for any memory enabled in the ROM Extension Unlikely to be a problem because of limited use of the ROM Extension 6 5 7 XFR BYTES Improperly passes memory select byte for the case where source and destination are in the same bank This is corrected by setting Location 676AH 26474 951 6 6 GENERAL 6 6 1 Pressing ENTER multiple times with an invalid tape command on the edit line syntax error causes the system to reset This is due to overflowing the Bank Status Stack in RAM Chunk 3 7 due to the multiple calls to and from the Extension ROM via the Call Bank code without normal termination the error causes a RESTART to be executed out of Home ROM code called from the ROM Extension Itshoul dn t take anybody that many tries to get a tape command right so this is not a real problem but you may want to keep it in mind For any call made through the OS RAM services you should have a corresponding return to keep the structures clean 134 6 6 2 ON ERR GOTO Ifa non existent line number is 6 6 6 6 6 6 CJ Specified followed by an error the system will hang The ROM code is in an endless loop trying to report the absence of a valid error handler to the non existent error handler On some errors you will get an unexpected 0 OK termination showing the line n
180. the CPU at the end of each instruction The NM has priority over the maskable interruption and its reponse is identical to the maskable interruption Mode 1 except that the call location is 0066H instead of 0038H NOTES 1 The NMI is not used by the T 2068 Comments in the ROM listing claiming to mask the via the DI Instruction are incorrect The DI instruction masks onl y the maskable interruption TABLE 2 1 2 80 CONTROL SIGNALS ACRONYM DEFINITI ON SYSTEM CONTROL MT Machine Cycle 1 Output active low This siqnal indicates that the current machine cycle is the OP code fetch cycle During execution of instructions having a 2 byte OP code this signal is generated as each OP code byte is fetched is also used with TORQ to indicate an interrupt acknowledge cycle MREQ Memory Request Tri state output active low This signal indicates that the Address Bus holds a valid address for a memory read or write operation TORO 1 0 Request Tri state output active low This signal indicates that the lower half of the Address Bus holds a valid I O address for 1 0 read or write operation This signal is also used with MT in connection with acknowledging an interruption indicating that an interrupt response vector can be placed on the data bus I O operations never occur during MT time RD Memory Read Tri state output active low his signal indicates that the CPU wants to read data from memory or an 1
181. the printer 8 X 22 All of the low level print routines are in module 10 2 of the Home ROM wet 4 2 Cassette Tape 1 0 is done via Port 1 0 read of Port OFEH pulls in the cassette input on Bit 6 An 1 0 write of Port Bit 3 controls the tape output with Bit 3 1 genrating a high output and Bit 3 0 generating a low output Data is written to the tape under software control creating the following frequencies and format Sync Pattern of 4032 cycles at 806 5 Hz 5 sec Header 17 bytes of data identifying the following data block as either Program Number Array Character Array or Binary Code and containing other control information The header is written as Data i e the Most Significant Bit first in each byte 1 cycle at 2040 Hz for a Zero and 1 cycle at 1020 Hz for a One The first byte is zero identifying the header The f i nal byte is a Checksum calculated by XOR of all preceding data bytes Software delay of approximately 835 milliseconds Sync Pattern of 1612 cycles at 806 5 Hz 2 secs Transition Pattern of 1 cycle at 2400 Hz Data Block Written as Data see above with first byte 1 FFH and a final Checksum byte Figure 4 2 1 shows the header formats for the various types of data The routines used to actually write and read the tape W TAPE and R TAPE are in the TAPE Module of the Extension ROM see map in Appendix A They are accessible via the Extension ROM Interfa
182. tion for example would pass control to the address on the stack Code to switch memory back to the Dock Bank could be mapped in a similar way If you plan to use any of the System software routines unless you know otherwise it is probably necessary to maintain the contents of Home Bank Chunks 2 and 3 intact and Chunk 7 if the OS RAM routines have been relocated The system routines rely heavily on the System Variables and assume that any pointers in them are pointing to the Home Bank See Section 3 3 4 1 for details on using the RAM Interruption Handler and Section 6 0 for known corrections when using System S W If you desi gn an LROS implementing a higher level language and want to support an AROS application you must design your own initialization code to detect the presence of such an AROS The TS 2068 will not look for the presence of an AROS if an LROS is present therefore there will be no entry for the AROS in the System Configuration Table Note that since there is only one cartridge connector such an AROS would also have to be integrated with the supporting LROS in a single cartridge or cartridge board 108 9 1 2 AROS An AROS is identified by the following overhead bytes Location Description 32768 Language 8000H BASIC and machine code Machine code only Any other value will result in Error S Missing LROS 32 69 Cartridge Type 8001H 2 AROS 32770132771 Starting Address LSB MSB 8002 80
183. tional details 2 0 HARDWARE GUI DE 2 1 Description of Major Hardware Functions Figure 1 1 1 shows a simplified block diagram of the TS2068 The following functional units are described in the following sections SECTI ON FUNCTIONAL UNIT AC Adapter Voltage Regulation Z 80A CPU Address Bus Data Bus Control Signals OP Code Fetch Memory READ WRITE 110 READ WRITE Maskable Interruption Non Maskable Interruption NMI ROM 32K RAM Sound Generator Joystick Port Control Logic Bank Selection Logic 280 Clock Generator Display File Access Interruption Generation Keyboard 16K Video Display RAM Video Generation Composite Video 11 2 RF Modulator Cassette 1 0 Port Map lt Un amp n gt co co oo SID UI B UJ UJ U CO CO U w WY F7 UC N FL e e a gt o INI NJ RO RO RO NJ RY NJ NJ NJ RI NJ PRY NJ NJ BRI NJ NJ NJ NJ NJ NJ NJ RY PY N F lt 2 25151 Adapter The AC Adapter transforms 117V AC Nominal to filtered DC via a step down transformer full wave bridge rectifier and filter capacitor to supply from 14 to 25 volts at 1 amp over the AC voltage variation range of 105 to 130 V Transformer isolation exceeds 1500 volts 117v AC 60H 14 to 25v T DC 2 1 2 Voltage Regulation 14 to DC Unregulated DC from the AC Adapter
184. touch the up contact and therefore electronically connects pin 8 to pin l Inthis state a read of port F6H with address bit A8 high causes actions as follows 1 Address A8 high turns on transistor Q8 2 08 drives cable pin 8 low 3 The movable center stick of the joystick in contact with the up contact results in a conductive path from cable pin 8 to cable pin l 4 Pin I low results in a 0 in bit position 0 of the TO register via the isolation diode The various positions of the stick similarly result in various bits being read from the I Oregister Note that 5 volts and ground are available on the connector so 5V logic could be attached to the joystick port 33 FIGURE 2 1 7 I JOYSTICK PORT OPERATI ON m lt E Th A gt 2 m gt gt E M LEFT Player 1 RIGHT Player 2 JOYSTICK CONNECTOR CONNECTOR aes S D G EEI edeedey V 4 r z a z it i 4 N CN CN N N S 4 x Pp py Tf tL 7 6 5 4 3 2 10 15 14 13 12 1 109 68 1 0 Register Addressed Via in instruction 7 80 Address Bus 8 15 info
185. tterns two independent methods of control are provided in the PSG first it is possible to vary the frequency of the envelope using registers and R12 and second the relative shape and cycle pattern of the envelope can be varied using register R13 The following paragraphs explain the details of the envelope control functions describing first the envelope period control and then the envelope shape cycle control 2 1 6 5 1 Envelope Period Control Registers RII R12 The frequency of the envelope is obtained in the PSG by first counting down the input clock by 256 then by further counting down the result by the programed 16 bit Envelope Period value This 16 bit value is obtained in the PSG by combining the contents of the Envelope Coarse and Fine Tune registers as illustrated by Figure 2 1 6 8 27 FIGURE 2 1 6 8 16 BIT ENVELOPE PERIOD EP TO ENVELOPE GENERATOR ENVELOPE ENVELOPE COARSE TUNE FINE TUNE REGISTER R12 REGI STER RII i at 4 p p 2 4 b LJ OF a 2t Note that the 16 bit value programmed in the combined Coarse and Fine Tune registers is a period value the higher the value in the registers the lower the resultant envelope frequency Note also that as with the Tone Period the lowest period value is 000000000000001 divide by 1 the highest p value is 1111111111111111 divide by 65 535 10 envelope frequency equations a fE fCLOCK b EP 256 CT FT
186. umber of your Error Handler This is because some ROM routines temporarily clear the INTPT Flag Bit 7 of FLAGS This flag is set to 0 when checking syntax and set to 1 when executing if an error is detected while the Flag 0 the error handler code is branched to but is not executed Parameters to the SOUND command are not fully validated therefore you can specify a number beyond the valid range for a given operation and not get an error for example you can write a value greater than 63 to the Enable Register Reg 7 possibly changing the 1 0 Port used for reading the joysticks from input to output If you specify a number larger than 255 FFH only the least significant byte will be actually written to the Programmable Sound Generator Access to PSG Reg 14 10 A used for the Joysticks is also not precluded via the SOUND command If you experience difficulty in reading the joystick s do a write to PSG Reg 7 clearing Bit 6 to 0 to guarantee that the joystick path is enabled for input see Section 4 3 This write can be done by executing a SOUND 7 63 or any value less than 63 The I NTEGER function for 65536 gives an incorrect result of 1 and for other cases where the result should be 65536 it gives 38 Since the ROM code cannot be changed there is no correction If yourespond to the SCROLL message using multiple keys such as Cap Shift Z or Cap Shift Symbol Shift you will get strange results like dumping
187. y See Section 2 1 10 for the display file organization The screen which is 32 columns X 24 lines is partitioned into two parts the main or upper screen 22 linesl and the lower screen 2 lines The lower portion of the screen is used for output of system messages and to echo input from the keyboard of BASIC commands BASIC program lines or data The lower screen expands as needed for multi line input scrolling the entire screen upwards The variable DF SZ reflects the number of lines in the lower screen defaultz2 Character output to the screen is done using the Channel 1 0 described in Section 4 1 using device specification for the lower screen and 5 for the upper screen Each character is defined by an 8 X 8 group of pixels The 8 bytes needed for each of the 133 characters supported by the TS 2068 are located as shown in Figure 4 1 2 1 Note that by constructing your own pixel data and placing base address IOOH into CHARS you can define your own character set Associated with each character position is an Attribute Byte controlling the background PAPER color the foreground INK color the intensity BRIGHT and whether the position is constant or alternates between true and inverse video FLASH Two other attributes OVER and INVERSE are implemented by software at the time the character s are placed into the display file FIGURE 4 1 2 1 TS 2068 STANDARD CHARACTER TABLES Character Set No of Chars Char C

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