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MF 604 - Humusoft

1. vc O10 401 OUT3 our2 O 2 391 GATE 2 our 3 OUT4 GATE 1 14 370 OUT5 x1 05 36 GATE3 x2 6 35 GATE4 FOUT 7 1 GATES 8 331 SOURCE 1 WR 321 SOURCE 2 O 10 31 SOURCE 3 Ro 30 1 SOURCE 4 DO 12 29 1 SOURCE 5 D1 13 28 D 15 D2 14 27 D 14 D3 15 26 D 13 16 25 1 GATE 5A D12 D5 17 24 1 GATE 4A D11 06 18 23 1 GATE 010 D7 19 22 1 GATE 2A D9 GATE 1A D8 20 21 1 vss Figure 2 CTS9513 DIP 40 Package Pinouts PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp RevC November 97 Celeritous Technical Services Corp PO Box 65600 1200 806 783 0904 FAX 806 783 0905 CTS9513 Lubbock Texas 79464 5600 http www celeritous com 5 Chan 16 bit Counter Timer PLCC 44 Package Pinouts Extended Function Pins Pin Signal Pin Signal Pin Signal Pin Signal 1 VCC 23 D8 1 Vcc 51 Vcc 2 OUT2 24 VSS 2 DO 52 NC 3 NC 25 09 3 D2 53 NC 4 OUT1 26 D10 4 D4 54 NC 5 GATE1 27 D11 5 D6 55 NC 6 x1 28 D12 6 D8 56 NC 7 2 29 D13 r D10 57 NC 8 FOUT 30 D14 8 D12 58 NC 9 NC 31 D15 9 D14 59 NC 10 C
2. OUTPUT INHIBIT i INT CLEAR N B sa 4 gt TCOUT INTMODE OUTPUT SET COUNTER TC _ OUTPUT ee OUTPUT CLEAR TC TOGGLE COMPARATOR ALARM EN OUTPUT POL OUTPUT LOW TRISTATE CNTL Figure 7 CTS9513 Counter Output Logic Block Diagram PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp 13 RevC November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 806 783 0904 FAX 806 783 0905 http www celeritous com CTS9513 5 Chan 16 bit 50MHz Counter Timer 4BITS 4BITS 4BITS 4BITS 4BITS CLKIN l 4BITS 1 1 1 L FREQUENCY Fi F2 F4 F5 F6 F7 BCD SCALING BINARY SCALING CLKIN CLKIN CLK 10 CLK 16 CLK 100 CLK 256 CLK 1000 CLK 4096 CLK 10000 CLK 65536 CLK 100000 CLK 1048576 CLK 1000000 CLK 16777216 Figure 8 CTS9513 Counter Internal Prescaler Block Diagram output waveform are shown in each waveform For waveforms which disarm automatically on TC the software ARM command is shown in conjunction with a Write pulse Repetitive waveforms do not show the write pulse or ARM command The letters L and H are used in t
3. Wu Eu PUR Yam TC OUTPUT p TOGGLE OUTPUT Y Y COUNTER MODE J WAVEFORMS Figure 19 CTS9513 Counter Mode J Representative Waveforms Mope I HARDWARE TRIGGERED DELAYED PULSE STROBE Mode I is similar to Mode G with the exception that the counter is active only after receipt of an ARM command and a valid Gate Edge As illustrated in Figure 18 the counter will count to TC reload from the Hold Register count to TC then disarm itself Once a valid Gate edge has been received the gate line has no further action on the counter J VARIABLE Duty CycLE RATE GENER ATOR WITH No HARDWARE GATING This mode is used primarily for generation of variable duty cycle waveforms Once armed the counter will count repeatedly until disarmed The counter will count to the first TC reload automatically from the Hold register count to the next TC reload automati cally from the Load register and repeat the cycle If the toggle output mode is selected the output will have an on or off time equal to the load count and off on time equal to the hold count As shown in Figure 19 PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp RevC November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 806 783 0904 FAX 806 783 0905 http www celeritous com CTS9513 5 C
4. OUTPUT TOGGLE OUTPUT COUNTER MODE B WAVEFORMS Figure 11 CTS9513 Counter Mode B Representative Waveforms Mops A SOFTWARE TRIGGERED STROBE WITH NO GATING As shown in Figure 10 The counter is only active after receipt of an ARM command On reaching TC the counter automatically reloads from the Load register and disarms awaiting the next software ARM command SOFTWARE TRIGGERED STROBE WITH LEVEL GATING In Mode B illustrated in Figure 11 the counter is only active when both an ARM command has been re ceived and the selected Gate line is active The counter will halt counting when the gate line is de asserted and resume counting when the gate line is re asserted until the counter reaches TC When the counter reaches TC the timer will reload from the load register and disarm automatically until a new ARM command is received PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp 16 RevC November 97 806 783 0904 FAX 806 783 0905 http www celeritous com Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 CTS9513 5 Chan 16 bit 50MHz Counter Timer source V _ LI VS NJ D TC OUTPUT TOGGLE OUTPUT COUNTER MODE C WAVEFORMS Figure 12 CTS9513 Counter Mode C Representative Waveforms source AOP A A dXX WR
5. TESIT COMMAND REGISTER BUS MUX w BUS CONTROL each counter Level asserted interrupt lines must be cleared with an extended set software command OUTEN Output Enable PQFP 100 pkg only The Output enable line is an active low hardware override to place all timer outputs in a high impedance state Acting directly on the counter out puts this line allows the user to inhibit the outputs while the counters remain active FUNCTIONAL DESCRIPTION SvsrEM LEVEL The CTS9513 is addressed by the external system as two address locations Counter and command data are written to individual counters through a sequence of indirectly addressing the internal command or data register through the command port address followed by a write to the data port address which points to the indirectly addressed register location Data is trans ferred through either two 8 bit transfers or a single 16 bit transfer Pointer sequencing for 8 bit transfers is automatic and is transferred as least significant byte first most significant byte second Rapid programming of the CTS9513 may be accom plished by use of the auto increment feature of the data pointer This feature is enabled by setting Mas ter Mode Register bit 14 MM14 When enabled the data pointer may be sequenced through a single counter group all counter group registers all counter group Hold registers only or just the control group regist
6. DATA care NRA TC OUTPUT TOGGLE OUTPUT m ua X X COUNTER MODE D WAVEFORMS Figure 18 CTS9513 Counter Mode D Representative Waveforms C HARDWARE TRIGGERED STROBE In Mode C as shown in Figure 12 the counter is active only after receipt of an ARM command and the application of a Gate edge to the selected gate line Once a Gate edge is sensed the counter will count until it reaches TC Subsequent gate actions have no further effect on the counter action The counter will remain inactive until receipt of a new ARM command and Gate Mops D RATE GENERATOR WITH NO HARD WARE GATING Mode D illustrated in Figure 13 is commonly used as a programmable frequency source as it continues to count repetitively until receipt of a DISARM com mand Once ARMed the counter counts to TC automatically reloads the counter from the Load register and begins counting again The waveform produced can be a square wave if the Toggle output mode is specified The Gate line has no effect on the counter action PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp RevC November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 806 783 0904 FAX 806 783 0905
7. CTS9513 5 Chan 16 bit 50MHz Counter Timer Figure 1 CTS9513 DIP 40 Package CTS9513 OVERVIEW For two decades the most flexible counter timer pe ripheral device available was the Advanced Micro Devices AM9513 Counter Timer Until discontinued in 1995 the AM9513 was a leading device in indus trial and scientific timing controllers Its only limita tion was its 7 Mh maximum clock speed until now Building on two decades of successful use as the most flexible programmable counter timer device the CTS9513 breaks the old limitations of the AM9513 in a new technology device with over 5 times the performance of the venerable 9513 with 16 bit coun ters Sporting up to a 50 MHz Maximum Input clock the CTS9513 allows timing resolutions of 20 ns and gate pulses as short as 10nS This opens up a whole new range of capabilities and applications for this device The CTS9513 is fully Hardware and Software com patible with the AM9513 allowing use of your present Software drivers The CTS9513 5 Also features an extended set of instructions for additional prescaling of the input clock and internal interrupt generation circuitry Standard Packaging for the CTS9513 is the DIP 40 PLCC 44 PQFP 100 Package Extended 1 0 is available in the PQFP 100 package only Both Commercial and Industrial temperature ranges are available in plastic packaging CTS95130 Also in the works is a full 5 x 32 bit implementation of
8. Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 806 783 0904 FAX 806 783 0905 http www celeritous com CTS9513 5 Chan 16 bit 50MHz Counter Timer Auxiliary Counter Mode Register The Auxiliary Counter Mode Register has been added to accommodate extended feature program ming The primary Counter Mode Register remains the same as in the 9513 for software compatibility At power on and at reset both Counter Mode regis ters are reset to all zeros If no subsequent writes are made to the auxiliary Counter Mode register there is no difference in operation from the9513 as extended features will not be enabled Status Register The Status register has been extended to 16 bits to accommodate monitoring of the status of the com parators interrupt outputs and the hardware output inhibit line The lower 8 bits remain the same as in the9513 to preserve software compatibility 24 bit Extended Internal Prescaling The original 9513 was limited to a maximum of 16 bits of prescaling 10 000 BCD 65 536 Binary With a 50 MHz clock this would provide limited prescaling to 5kHz in BCD mode or 763 Hz in Binary mode The CTS9513 extends the internal prescaling counter to 24 bits 1M BCD 16 77M Binary adding two additional prescaler outputs These two new outputs may be programmed as count sources for any of the five counters as well as the FOUT dividers FOUT Prescaler The FOUT counter has been exte
9. MF 604 MULTIFUNCTION I O CARD USER S MANUAL 1999 COPYRIGHT 1999 by HUMUSOFT s r o All rights reserved No part of this publication may be reproduced or distributed in any form or by any means or stored in a database or retrieval system without the prior written consent of HUMUSOFT s r o Limited Warranty HUMUSOFT s r o disclaims all liability for any direct or indirect damages caused by use or misuse of the MF 604 device or this documentation HUMUSOFT is a registered trademark of HUMUSOFT s r o Other brand and product names are trademarks or registered trademarks of their respective holders Printed in Czech Republic Table of Contents 1 Introduction 1 1 General Description 1 2 Features List 1 3 Specifications mL ERRASSE 1 3 1 A D Converter 1 3 2 D A Converter 1 3 3 Digital Inputs 1 3 4 Digital Outputs 1 3 5 Quadrature Encoder Inputs 1 3 6 Counters Timers 2 Hardware Installation 2 1 DIP Switch Settings 2 2 Installation rie BOO t mere 3 Programming Guide 3 1 VO PO MAP ee entente 3 2 A D Converter oori es ee oe ge EE TS 3 3 D A Converters Digital Oi RUM 3 5 Quadrature Encoder Inputs 3 6 Timer Co
10. rising source edges The timing specifications are the same for 1000 ns N falling edge counting 17 This parameter applies to the hardware retrigger save modes 8 This parameter applies to edge gating CM15 CM13 110 or N O Q R and X CM7 1 and CM15 CM13 lt gt 000 This 111 and gating when both CM7 1 and CM15 CM137000 This parameter ensures that the gating pulse initiates a hardware parameter represents the minimum GATE pulse width needed retrigger save operation to ensure that the pulse initiates counting or counter reloading 18 This parameter applies to hardware load source select modes 9 This parameter applies to both edge and level gating CM15 S and V CM7 1 and CM15 CM13 000 This parameter CM13 001 through 111 and CM7 0 This parameter repre sents the minimum setup or hold times to ensure that the Gate input is seen at the intended level on the active source edge and represents the minimum hold time to ensure that the GATE input selects the correct load source on the active source edge Copyright 1997 Celeritous Technical Services Corp PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Rev C November 97 Celeritous Technical Services Corp 806 783 0904 PO Box 65600 1200 FAX 806 783 0905 CTS9513 Lubbock Texas 79464 5600 http www celeritous com 5 Chan 16 bit 50MHz Counter Timer Param Description X2 Low Pulse Width Count Source Pulse Duration High Tehfv Count Sou
11. 00 to all Counter Mode registers does not reset counter values outp BASE 1 OxFF master reset outp BASE 1 0x5F resets all counters loading 0x0000 from Load registers Programming Guide write 0x0B22 to Counter 1 Mode register to select binary mode counting down without gating output toggle on terminal count repeat mode using F1 clock source 20 MHz outp BASE 1 0x01 select Counter 1 Mode reg outp BASE 0x22 write Counter 1 Mode reg LO outp BASE OxOB write Counter 1 Mode reg HI write 10000 0x2710 to Counter 1 Load register will cause counter owerflow and output toggle every 0 5 ms and produce 1 kHz squre wave on timer counter 1 output after arming the counter outp BASE 1 0x09 select Counter 1 Load reg outp BASE 0x10 write Counter 1 Load reg LO outp BASE 0x27 write Counter 1 Load reg HI outp BASE 1 0x61 loads and arms counter 1 3 7 IRQEN Register MF 604 is capable of generating system interrupt on interrupt lines 2 3 5 10 11 12 and 15 After power on or hardware reset all interrupts are disabled Interruprs can be enabled or disabled using IRQEN 5 5 register Writing 1 to corresponding bit in IRQEN enables interrupt from timer 5 output not from the timer 5 INT output 0 disables interrupt For bit assignment of IRQEN register see Table 14 Do not set more than one bit of IRQEN register t
12. 16BITCOMPARATOR SOURCE FREQ GATE wr wr SET CONTROL 16 BIT HOLD REGISTER ENT COUNTER CONTROL 1 MODE CONTROL 16BIT COUNTER OUTPUT OUT CNTL TERM COUNT 16 BIT LOAD REGISTER Figure 5 CTS9513 Counter Groups 1 amp 2 Counter Groups All of the counter groups have a 16 bit counter and four programmable registers The primary and auxil iary counter mode register controls the count source gating and counting modes input and output polari ties binary or BCD counting and other parameters Load Register The Load register is the primary register used for storing count up or count down values which may be automatically reloaded into the counter for repetitive counting Hold Register The Hold register may be used for storing the instan taneous count value without disturbing the count process for reading by the host system It may also be used in certain count modes for storing alternate count values and alternately counting the load and hold register values to generate complex waveforms Counter Outputs Each of the counters has a single dedicated output pin which is programmable for polarity tri state low Z to ground and a variety of output modes as described later In addition to the output pin the CTS9513 adds an additional dedicated interrupt out put pin This allows the timer output to produce an interrupt sign
13. Default factory setting of base address is 300H 2 2 Installation Once you have properly set all switches you can install the MF 604 card in any free ISA expansion slot of your computer Follow the steps outlined below Turn off the power to the computer system and unplug the power cord Disconnect all cables connected to the computer system Using a screwdriver or nut driver remove the cover mounting screws that screws are at the rear side of the PC Remove the computer system s cover Find an empty expansion slot for your computer for MF 604 card If the slot still has the metal expansion slot cover attached remove the cover with a screwdriver Save the screw to install the MF 604 Hold the MF 604 firmly at the top of the board and press the gold edge connector into an empty expansion slot Using screwdriver or nut driver screw the retaining bracket tightly against the rear plate of the computer system case of using also quadrature encoder inputs or timer counters install also the aditional connector with metal slot cover to neighbouring slot Otherwise you can disconnect the aditional connector from the board and save it for future use Replace the cover of the computer and plug in the power cord Reconnect all cables that were previously attached to the rear of the computer 10 Programming Guide 3 Programming Guide 3 1 I O Port Map I O space of MF 604 card consists of
14. RESERVED Table 10 CTS9513 Counter Mode and Auxiliary Counter Mode Register Bit Assignments The output may be disabled by either placing it in a high impedance state or in a low impedance state to ground The outputs may also be hardware inhibited with the line In the Terminal count mode the output may be programmed to output an active high or active low pulse which is equal to one count source clock period In the output toggle mode the output changes state whenever the counter reaches a terminal count The output state may be initialized with the SET and CLEAR counter commands ron GATE INPUT MUX GATE 1 GATE AND POLARITY GATE 1 SELEGT GATE EN Count Control Bits CM3 7 Whenever the counter reaches a TC the counter automatically reloads the counter from the Load or Hold Register Which register the counter loads from whether the counter counts repeatedly or once whether the counter counts binary or BCD and whether the counter is under hardware control is controlled by the Count control Bit CM3 controls whether the counter counts in Binary or BCD fashion Bit CM4 determines whether the counter counts up or down Bit CM5 determines whether the counter counts once and disarms itself or will continue counting and reloading the counter COUNTER MODE REGISTER EDGE AND LEVEL GATE CONTROL COUNTER Figure 9 CTS9513 Counter Gating Input Logic Block Diagram PRE
15. Corp PO Box 65600 1200 Lubbock Texas 79464 5600 806 783 0904 FAX 806 783 0905 http www celeritous com FUNCTIONS Five 16 bit programmable up down counters Programmable Pulse Generation Programmable Delay Generator Pulse Measurement Event Counting Freguency Measurement System Synchronization Real Time Clock APPLICATIONS e Computer System Timing Real Time Clock with Alarm Watchdog Timer Programmable System Bus Clock Wait State Generation e Data Acguisition Programmable Converter Clock Pulse Measurement Freguency Counter Event Counter ATE Programmable Stimulus Generator Timing Extremes Generator Laser Systems Timing Sequencer Programmable Delay Generator External Equipment Synchronization Burst Mode Generator Industrial Process Control Pulse Frequency Sensor conversion System Timing Synchronization ExTENDED 9513 FEATURES 5 Device Up to 50 MHz Maximum input frequency Extended Pre scaling Internal Interrupt Generation Master Output Inhibit Extended Count Source Selection STANDARD AM9513 FEATURES Five independent 16 bit counters Up Down Binary BCD Counting Internal Binary BCD Prescaling One Shot Continuous Outputs Software External triggering Tri state Outputs Programmable output polarities Programmable gate polarities edges Time of Day Alarm Functions Programmable Internal External Counter Source Fully AM9513 Hardware Software Compatible Dual count registers on each counter
16. P 4 X axis programmable input to operate either as direct reset XCNTR or count enable disable gate or synchronous reset XCNTR The synchronous reset XCNTR mode is intended for interfacing with the encoder Index output in quadrature clock mode In direct reset XCNTR mode a logic low level is the active level at this input whereas in synchronous reset XCNTR mode the active level can be pro grammed to be either a logic low or a logic high Both quarter cycle and half cycle index signals are supported by this input in the indexed reset CNTR mode The synchronous function must be disabled in non quadrature count mode See description of IDR on P 4 In count enable disable mode a logic high at this input enables the counter and a logic low level disables the counter X axis programmable output to operate either as XCARRY Active low or XCOMPARE generated when XPR XCNTR Active low or XIDX XFLAG bit 6 or XCARRY XBORROW Active low X axis programmable output to operate as either XBORROW Active low or XU D XFLAG bit 5 or XE XFLAG bit 4 All the X axis inputs outputs are duplicated for the Y axis with similar functionalities YA Pin 25 YB Pin 24 YLCNTR YLOL Pin 1 YRCNTR YABG Pin 28 YFLG1 Pin 27 YFLG2 Pin 26 COMMON l Os WR Pin 14 RD Pin 16 CS Pin 15 C D Pin 13 DO D7 Pins 4 11 FCK Pin 2 XY Pin 17 VDD Pin 3 Vas Pin 121 Write input Control data bytes are written at the trailing ed
17. and 2 When enabled additional counter logic is enabled to allow the two counters to operate as a 24 hour clock Counters 1 and two must be programmed for BCD counting To initialize the time appropriate values are loaded in the Counter Load registers To read the time a SAVE command is issued to Counters 1 and 2 and the values read from the Hold registers Table 9 illustrates the Time of day storage configura tion In short Counter 2 bits 8 15 form a two digit BCD Hours counter Bits 0 7 form a two digit BCD Minutes counter Counter 1 bits Bits 8 15 form a two digit BCD seconds counter Bits 4 7 form a tenth second counter and Bits 0 3 form a division factor for the input source for divide by 5 6 or 10 Comparator Enable Bits MM2 3 The two 16 bit comparators on counters 1 and 2 may be used in any mode When enabled the output of parison between the counter and alarm register con tents are true It will remain asserted as long as the counter and alarm register remain the same In the Time of Day mode the comparators operate in conjunction such that the output of the counter 2 comparator is asserted only when both comparators 1 and 2 are true the comparator 1 output will continue to operate normally FOUT Source Bits MM4 7 Fifteen different sources may be routed to the input of the FOUT divider including the five SOURCE inputs five GATE inputs and five of the internal divided frequencies derived from the X1 input Addi
18. and CS are low Release starts when either RD or CS is terminated 3 1 t1 t2 where n PSC 0 to FFH 4 gt 2t3 5 gt 4t3 QA 1 8ts Q2 t3 idx gt lt t3 X AXIS l Os XA Pin 20 XB Pin 21 XLCNTR XLOL Pin 19 XRCNTR XABG Pin 18 XFLG1 Pin 22 XFLG2 Pin 23 Y AXIS INPUTS OUTPUTS X axis count input A Either quadrature encoded clocks or non quadrature clocks can be applied X axis count input B to XA and XB In quadrature mode XA and XB are digitally filtered and decoded for UP DN clock In non quadrature mode the filter and the decoder circuits are by passed Also in non quadrature mode XA serves as the count input and XB as the UP DOWN direction control input with XB 1 selecting Up Count mode and XB 0 selecting Down Count mode X axis programmable input to operate as either direct load XCNTR or direct load XOL or synchronous load XCNTR or synchronous load XOL The synchronous load mode is intended for interfacing with the encoder Index output in quadrature clock mode In direct load mode a logic low level is the active level at this input In synchronous load mode the active level can be programmed to be either logic low or logic high Both quarter cycle and half cycle Index signals are supported by this input in the in dexed Load mode The synchronous function must be disabled in non quadrature count mode See description of IDR on
19. associated BP is automatically incremented to address the next byte Flag Register XFLAG and YFLAG The FLAG registers hold the status information of the CNTRs and can be read out on the data bus The E bit of a FLAG register is set to 1 when the noise pulses at the quadrature inputs are wide enough to be validated by the input filter circuits E 1 indicates excessive noise at the inputs but not a definite count error Once set E can only be reset via the RLD FLAG 7 6 5 4 3 2 Borrow Toggle flip flop Toggles every time CNTR underflows Carry toggle flip flop Toggles every time CNTR overflows CPT Compare toggle flip flop Toggles every time PR equals CNTR S Sign flag Set to1 when CNTR underflows Reset to 0 when CNTR overflows E Error flag Set to 1 when excessive noise is present at the count inputs in quadrature mode Irrelevant in non quadrature mode U D Up Down flag Set to 1 when counting up and reset to 0 when counting down IDX Index Set to 1 when selected index input is at active level 0 Notused Always reset to 0 Filter Clock Prescalers XPSC and YPSC Each PSC is an 8 bit programmable modulo N down counter driven by the FCK clock The factor N is down load ed into a PSC from the associated PR low byte register PRO The PSCs provide the ability to generate in dependent filter clock frequencies for each channel Fina
20. byte during conversion cycle will abort current conversion and start a new conversion cycle Table 6 A D Status Byte Format 14 Programming Guide Table 7 A D Data Registers Format The output data format is binary in unipolar mode and twos complement binary in bipolar mode When reading ADLO the lower eight bits are read When reading ADHI the upper four MSBs are available and the output data bits D4 D7 are either set O in unipolar mode or set to the value of MSB in bipolar mode as described in Table 7 converter voltage reference can be adjusted by R11 Sample code for A D conversion unsigned short BASE int ch short ad char Gain 8 start conversion on channel ch outp BASE 6 ch Gain ch 3 0x40 wait until conversion completed while ISBITI inp BASE 8 0x80 read data ad inpw BASE 6 convert to bipolar range ad Gain ch amp Ox1 0 0x800 convert to double return ad double 1 lt lt 11 15 Programming Guide 3 3 D A Converters D A converters are accessed through eight data input latch registers DAOLO DAOHI DA1LO DA1HI DA2LO DA2HI DA3LO D A converters do not require any initialization Analog outputs are updated when the high byte is written to D A register Therefore low byte must be written first for correct operation Table 8 D A Data Registers Format Output voltage ranges of D A converters are 1
21. use these pins this register can be used to enable disable A and B inputs only Programming Guide Bee EHE deel E E Disable A and B inputs COCO s Table 12 Command register bit assignments for access Index Control Register IDR allows programming of index operation Index input is connected to RCNTR ABG pin and bit 2 of IDR must be set to 1 for correct index operation aT 6 5 4 s 2 Command register vit LLL gb t fol Disable index CL Erse index L o Nesie index poa Positive index polarity Table 13 Command register bit assignments for IDR access Sample code for IRC operation initialize IRC for 1 0 i IRC INPUTS i BASE 0x11 2 1i 0x01 reset BP outp BASE 0x10 2 i 0 PRO 0 20 outp BASE 0x11 2 i 0x18 outp BASE 0x11 2 i 0x01 outp BASE 0x10 2 i 0x00 outp BASE 0x10 2 i 0x00 outp 5 0 10 2 1 0x00 BASE 0x11 2 i 0x08 outp 5 0 11 2 1 0x38 outp BASE 0x111 2 1 0x41 outp BASE 0x111 2 1 0x65 read IRC ad BASE 0x10 2 ch outp ad 1 0x11 irc inp ad irc inp ad lt lt 8 irc inp lt lt 16 return irc Programming Guide PRO gt PSC reset BP reset PR PR CNTR CMR IOR IDR CNTR gt OL reset BP 3 6 Timer Counter MF 604 c
22. which source is used as an input to the counter There are 20 possible CTS9513 5 Chan 16 bit 50MHz Counter Timer count sources 16 of which may be selected with bits CM8 12 Additional Count sources may be specified with the extended registers Figure 8 illustrates the internal 24 bit prescaler whose outputs may be used as count sources Gating Control Bits CM13 15 Gating control determines whether the counter is hardware gated or not When gating is disabled the counter will continue as long as the counter is armed If any gating mode is enabled the counter action is determined by some hardware gate condition Gating of the counter may be controlled from the gate line associated with the counter or gate lines associated with adjacent counters Gating on the line associated with the counter may be programmed for edge or level sensitive active high or active low The counter may also be gated by the TC output of the previous counter The gating control logic is outlined in Figure 7 COUNTER MODES Counter modes continue as in the 9513 to retain their mode designations A X with modes M P T U and V reserved Tables 11 12 summarize the counter modes and the associated settings of the counter mode bits CM5 7 and CM13 15 Figures 10 through 28 illustrate the counter modes All representative waveforms assume counting down on rising source edges A TC mode and Toggled
23. 0V After power on or hardware reset the output voltage is set to OV Digital input Output Voltage OxFFF 9 9951 V 0x800 0 0000 V Ox7FF 0 0049 V 0x000 10 0000 V Table 9 D A Outputs 16 Programming Guide 3 4 Digital MF 604 contains one 8 bit digital input port and one 8 bit digital output port Digital input port can be accessed directly by read from DIN register BASE 4 Inputs are TTL compatible Digital output port can be accessed by write to DOUT register BASE 4 Outputs are TTL compatible After power on or hardware reset digital outputs are set to 0 3 5 Quadrature Encoder Inputs MF 604 contains four quadrature encoder inputs with single ended or differential interface and index puls inputs Inputs are differential TTL compatible with Schmitt triggers Two LS7266R1 chips with 20 MHz clock are used first for channels IRCO and IRCI second for IRC2 and IRC3 For detail low level documentation please refer to LS7266R1 documentation in Appendix of this User s Manual Each IRC channel has one data register and one command register allowing you to access all internal data and control structures As internal counters are 24 bit wide Byte Pointers BP with autoincrement function are used to address 3 bytes sequentially Each counter can be loaded from Preset Register PR and latched to Output Latch OL The Read and Write operations on an OL or PR always accesses one byte at a time The byte that is accessed is
24. 32 registers immediately following the base address selected by SW1 9513A Command read lI 1 DIN Digital input register ADLO A D data low byte ADHI A D data high byte 05 5755 ADSTAT A D status reg 11 Programming Guide Table 2 I O Port Map 3 2 A D Converter functions of A D converter are accessible through four registers A D control register ADCTRL is used to select input channel input range and to start conversion For ADCTRL bit assignment see table 3 D7 5 DI DO MSB LSB Fe 0 pt o mo a M 12 Programming Guide NAME DESCRIPTION T TES 3 neant 1 r ram Table 4 Input Range Selection 13 Programming Guide T T T PI PTT TT TT ETSI I II ET LET was Table 5 Input Channel Selection Conversion is initiated with a write operation to ADCTRL register located at address BASE 6 which also selects the input multiplexer channel and input range When the conversion is complete bit 7 in A D status register ADSTAT BASE 8 is set to zero Then the data is ready and can be read from ADLO and ADHI registers BASE 6 BASE 7 The read operation of ADLO and ADHI registers sets the conversion complete bit in ADSTAT register back to one Writing a new control
25. 4 bits Counter modes binary BCD Index input programmable Inputs differential with Schmitt triggers Input noise filter digital programmable 0 2 50 us Introduction Input frequency max 2 MHZ Quadrature modes X1 X2 X4 1 3 6 Counters Timers Counter chip CTS9513A Number of channels 5 4 of them available on I O connector Resolution 16 bits cascadable up to 80 bits Clock frequency 20 MHZ Conter modes up down binary BCD Triggering software external Clock source internal prescalers external Inputs TTL Schmitt triggers Outputs TTL SW1 1 b b lo Jo o 2 Hardware Installation 2 1 DIP Switch Settings SW1 2 SW1 3 SW1 4 lo Z 2 2 Z lo mou o 2 a a 2 2 2 o S o o o Z Z tH 2 Z Z 2 m Table 1 I O Address setting using SW1 switch Hardware Installation address Hardware Installation The bank of four switches SW1 on the MF 604 specifies the base address of I O ports on the card MF 604 occupies 32 consequent addresses in PC s I O address space Possible settings of DIP switches are listed in table 1 According to this table selecting I O address 300H means that switch 1 should be switched OFF while all other switches should be ON
26. D 32 NC 10 NC 60 NC 11 WR 33 SOURCES5 11 NC 61 IRD 12 cs 34 SOURCE4 12 NC 62 ICS 13 RD 35 SOURCE3 13 NC 63 NC 14 NC 36 SOURCE2 14 NC 64 NC 15 DO 37 SOURCE1 15 NC 65 NC 16 D1 38 GATE5 16 NC 66 NC 17 D2 39 GATE4 17 NC 67 NC 18 D3 40 GATE3 18 C D 68 NC 19 D4 41 OUT5 19 NC 69 NC 20 D5 42 OUT4 20 IWR 70 NC 21 D6 43 GATE2 21 NC 71 NC 22 D7 44 OUT3 22 NC 72 D15 Table 2 PLCC 44 Pinouts 23 NC 73 D13 24 NC 74 D11 U 25 NC 75 D9 1 o 26 NC 76 D7 e on 27 NC 77 D5 i i 28 NC 78 03 CTSC9513ADI 5 29 Nc jm 1 30 Vss 80 Vss 1 i 31 Vss 81 Vss i il 32 NC 82 NC D 33 NC 83 xi n Pes 34 NC 84 NC 35 NC 85 2 36 NC 86 NC 37 NC 87 SOURCE 1 Figure 3 PLCC 44 Outline 38 INT 5 88 SOURCE2 gt lt 39 INT 4 89 SOURCE 3 40 INT 3 90 SOURCE 4 41 INT 2 91 SOURCE 5 42 INT 1 92 NC 43 OUT 5 93 GATE 1 44 OUT 4 94 GATE 2 45 OUT 3 95 GATE 3 46 OUT 2 96 GATE 4 47 OUT 1 97 GATE 5 48 NC 98 NC 49 FOUT 99 IOUTEN 50 Vec 100 Vcc Figure 4 PQFP Package Outline Table 3 PQFP 100 Package Pinouts New Signal PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp 4 Rev November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 806 783 0904 FAX 806 783 0905 http www celeritous com CTS9513 5 Chan 16 bit 50MHz Counter Timer ORIGINAL SiGNALS The following signal names and description confor
27. DE CM7 SPECIAL GAT CM6 RELOAD SOU 5 REPITITION CM13 15 GATE CO Countto TC Once Countto TC Twice Countto TC repeatedly Gate Input Inactive Count while gate active E RCE TROL Count once on gate edge Count twice on gate edge No Hardware retriggering Reload from Load on C Alternate Load Hold on TC Gate Controlled Load Hold Gate Retrigger Counter 806 783 0904 FAX 806 783 0905 http www celeritous com M N 0 P Q R 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 000 LVL EDG 000 LVL X X X X X X X X X X X X X X X X Table 12 Counter Modes M X CTS9513 5 Chan 16 bit 50MHz Counter Timer LVL V W X 1 1 1 1 1 1 1 1 1 000 LVL EDG X X PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp 15 Rev November 97 Celeritous Technical Services Corp 806 783 0904 PO Box 65600 1200 FAX 806 783 0905 Lubbock Texas 79464 5600 http mww celeritous com CTS9513 5 Chan 16 bit 50MHz Counter Timer source f X JU Gd N Z D DATA GATE OUTPUT TOGGLE OUTPUT count vatue a Vs tos Var anam um X COUNTER MODE A WAVEFORMS Figure 10 CTS9513 Counter Mode A Representative Waveforms joue dox XC WR DATA GATE FA V j f FA f FA arm commano OM k 5 COUNT VALUE ua ox odes a Xa X
28. ENCY SHIFT KEYING Mode V is similar to mode S in that the Gate line act to select which register the counter is reloaded from but counts continuously once armed If the Toggled output is used the output may be used to switch between two frequencies determined by the Load and Hold Count values and the state of the Gate line as shown in Figure 27 This is used in Frequency Shift Keying FSK applications PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp Rev November 97 806 783 0904 FAX 806 783 0905 http www celeritous com Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 FA FA FA pA Vf sure V N AYN NJ NJ NT NI CTS9513 5 Chan 16 bit 50MHz Counter Timer AUF JA Wi ko Z DATA y A ARM COMMAND care WWWWWWWWWWWWW WWW ME a X OA feu WP es ru Ke TC OUTPUT TOGGLE OUTPUT HOLD REG L X COUNTER MODE X WAVEFORMS Figure 28 CTS9513 Counter Mode X Representative Waveforms X HARDWARE SAVE Mode X is a hardware edge triggered strobe counter with the capability of reading the counter value with out interrupting the count As shown in Figure 28 once the counter is ARMed a valid gate edge starts the counter Once triggered the counter will count to TC r
29. Figure 24 CTS9513 Counter Mode Q Representative Waveforms source V V V kr A A VV VV VV LI AO AO N LI care 777 XN XXX couwr VALUE ia Y Y we Y ua J Y a Lu Y xa e TC OUTPUT NA COUNTER MODE R WAVEFORMS Figure 25 CTS9513 Counter Mode R Representative Waveforms Mope Q RATE GENERATOR WITH SYNCHRO NIZATION Mode Q provides a continuous rate generator which may be externally gated or synchronized to an exter nal event via the Gate input As shown in Figure 24 once an ARM command is received the counter will continuously count to TC reload the Load register and repeat as long as the Gate line is asserted While the Gate line is deasserted the counter is inhibited On the active going edge of the gate signal the counter is reloaded from the Load register reset ting the counter and resume counting on the second valid source edge following the Gate edge Mope RETRIGGERABLE ONE SHOT Mode R as shown in Figure 25 begins counting only after receipt of an ARM command and a valid active Gate edge The counter will count once to TC and stop The counter will remain inactive until re ceipt of a subsequent valid Gate edge If a valid Gate Edge is received prior to the counter reaching TC the counter value will be saved in the Hold register and the counter reloaded from the Load register retriggering or resetting the counter The counter in insensitive to the Gate level and gate actions do no inh
30. ICE Copyright 1997 Celeritous Technical Services Corp RevC November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 806 783 0904 FAX 806 783 0905 http www celeritous com SAVE Command The SAVE command is used to save the contents of the counter while counting continues This allows the counter value to be read without interfering with the counter Subsequent SAVE commands will overwrite any previous contents of the Hold register CLEAR Command The CLEAR command is used to reset the counter output toggle to initialize it to a low state This command is only active if the output toggle is pro grammed It is inactive if a Terminal Count output is specified SET Command The SET command is used to set the counter output toggle to initialize it to a high state This command is only active if the output toggle is programmed It is inactive if a Terminal Count output is specified STEP Command The STEP Command increments of decrements the selected counter by one depending on the operating mode Master Mode Commands A number of commands directly affect the Master Mode Register without having to write to it directly These commands affect primarily the modes of the data path data pointer sequencing enabling the divided FOUT output clocks and clearing of latched interrupt outputs from the counters Table 6 summa rizes thes commands REGISTER DEFINITIONS STATUS REGISTER The 16 bit S
31. ION B AND GATE ABG INPUTS IN NON QUADRATURE MODE A B to CY CNTR DISABLED gt J de t BW CNTR DISABLED t CNTR DISABLED CNTR 999998 999999 0 1 2 1 0 999999 0 999999 N N 1 2 CNTRENABLED RCNTR t CNTR ENABLED k tn CNTR ENABLED LCNTR t11 FIGURE 7 NON RECYCLE NON QUADRATURE BCD MODE A B UP DOWN 1 2 0 1 2 1 0 3 2 1 0 3 V2 K te COMP BW FIGURE 8 MODULO N NON QUADRATURE Shown with 3 A x Ya m DOWN AEO CNTR 0 1 2 3 4 CNTRFROZEN 3 2 1 0 CNTR FROZEN 1 2 COMP BW FIGURE 9 RANGE LIMIT NON QUADRATURE Shown with 4 8 WRITE NPUTREG SBYTEO SBYTE2 SBYTE1 SBYTEO FCK PRESCALER FOK DIRECTION COMPARATOR COUNT CLOCK A CLOCK DIRECTION GEN FILTER B SBYTE2 SBYTE1 SBYTEO INTERNAL BUS READ WRITE VO BUF DATA BUS ISA BUS LS7266R1 DO TE D1 L M iow D2 WR 16 D3 RD IOR 04 cp 18 M 06 XN 17 1 D7 tsb 15 AEN A9 AB d x A7 ADDRESS P DECODER 4 1 0 IOR IOW FIGURE 11A LS7266R1 INTERFACE EXAMPLES ADDRESS 68 ATHAS DECODE MC68000 A1 gt C D MC68010 A2 gt XY MC68HC000 DO D7 lt gt 00 07 wW i C RD LS7266R1 LDS OQ WR DTACK O i Ke FIGURE 11B LS7266R1 INTERFACE EXAMPLES Celeritous Technical Services
32. LIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp 12 Rev November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 806 783 0904 FAX 806 783 0905 http www celeritous com until commanded to disarm Bit CM6 determines the source from which the counter will be reloaded The actions of CM6 depend on the gating control settings If CM6 is cleared the counter reloads from the Load Register at TC If CM6 is set the counter may reload from either the Load or the hold register depending on the gating mode It may alternate with the Load register or be controlled from the gate to reload from the load or hold register Bit CM7 controls whether hardware retriggering of the counter is enabled Its actions depend on the settings of CM5 CM6 and the gating controls If some type of gating is enabled and 7 is cleared hardware retriggering is disabled When CM7 is set hardware retriggering is enabled and the counter is retriggered any time an active gate edge is received When retriggered the counter value is saved in the Hold register and the counter reloaded from the Load register If no gating is enabled and CM7 is cleared the gate input has no effect on counting If CM7 is set then the Gate input controls whether the counter is reloaded from the Load or Hold Register Count Source Bits CM8 12 The count source determines
33. Lj 1 0 Write to YIDR 1 1 1 1 Ta spe x 0 Write to both XIDR and YIDR x x x 0 0 1 0 0 Read XOL byte segment addressed by XBP Note 3 X X X 0 0 1 1 0 Read YOL byte segment addressed by YBP Note 3 x x x 1 0 1 0 0 Read XFLAG X X X 1 0 1 1 0 Read YFLAG X Don t Care Note 3 Relevant BP is automatically incremented at the trailing edge of RD or WR pulse Absolute Maximum Ratings Parameter Symbol Values Unit Voltage at any input VIN Vss 3 to VDD 3 V Supply Voltage VDD 7 0 V Operating Temperature TA 25 to 80 Storage Temperature TSTG 65 to 150 DC Electrical Characteristics TA 25 C to 80 C VDD 4 5V to 5 5V Parameter Symbol Min Value Max Value Unit Remarks Supply Voltage VDD 4 5 5 5 V Supply Current IDD 800 All clocks off Input Logic Low VIL E 0 8 V Input Logic High VIH 2 0 V Output Low Voltage VOL 0 5 V IOSNK 5mA Output High Voltage VOH VDD 5 V losRc 1mA Input Leakage Current 30 Data Bus Leakage Current IDLK 60 nA Data bus off Output Source Current IOSRC 1 0 mA Vo VDD 5V Output Sink Current IOSNK 5 0 mA Vo 0 5V 7266R1 111196 5 Transient Characteristics TA 25 C to 80 C VDD 4 5V to 5 5V Parameter Symbol Read Cycle See Fig 1 RD Pulse Width ri CS Set up Time r2 CS Hold Time 13 C D Set up Time r4 C D Hold Time r5 X Y Set up Time r6 X Y Hold Time 17 Data Bus Access Time r8 Data Bus Release Time r9 Back to Back Read delay r10 Write Cy
34. Load count This is the more common use of this mode of operation Mope H Sortware TRIGGERED DELAYED PULSE ONE SHOT wirH HARDWARE GATING Mode H is similar to Mode G with the exception that the counter is active only after receipt of an ARM command and a valid Gate input As shown in Figure 17 the counter counts only as long as the Gate line is asserted and suspended while the Gate line is de asserted Tas in Mode G the counter counts to TC using the Load register value reloads from the hold register and counts to a second TC Once the counter reaches the second TC the counter disarms itself and awaits another ARM command This mode allows extension of either the initial delay or the delayed pulse width by use of the Gate PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp Rev November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 http www celeritous com 806 783 0904 FAX 806 783 0905 CTS9513 5 Chan 16 bit 50MHz Counter Timer source PNP A Jf y y y N D GATE PU LE rom Dr OUTPUT fe Kx CA CE YR TT TOGGLE OUTPUT COUNTER MODE I WAVEFORMS Figure 18 CTS9513 Counter Mode Representative Waveforms some _ f f V V ZI A LJ
35. Outputs 0 1 5 are associated with individual coun ters Outputs are tri state and may be pro grammed by the counter for output polarity initialized to a given state and programmed for pulse square wave or complex duty cycle waveforms Counter outputs may also be driven into tri state by the OUTEN line available in PQFP Package only D0 15 Data Bus D0 15 form a bi directional 16 bit data bus for exchanging programming and status informa tion with a host processor or system These lines act as inputs to the counter when CS and WR are asserted and as outputs when RD and CS are asserted While CS is de asserted these lines are placed in a high impedance state On power up the data bus is configured for 8 bit transfers The data bus may be reconfig ured for 16 bit by programming Master Mode register Bit 13 If D8 15 are not used they should be pulled up CS Chip Select Input The chip select line is an active low I O con trol signal used to enable the device for read and write operations IWR Write Input The write line is an active low I O control sig nal which is used to transfer information from the data bus to one of the internal command or data registers RD Read Input The read line is an active low control sig nal which is used to transfer information from one of the internal data or command registers to the data bus C D Control Data Port Select Input The C D line is used in conjunction w
36. RD N N Trhwl Twwh Twhwi Ran T i r y WR N N OH Tha U j The Twhdx DATA lt i gt mE L Twhyy OUT I Figure 30 Bus Timing Diagram Teheh Le Teleh 4 COUNT SOURCE N ow Tehgv M die GATE IB FOUT X K OUT X F C Tehh eee vec Reg T Tehd FN T n 1 Figure 31 Counter Timing Diagram PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp 26 RevC November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 806 783 0904 FAX 806 783 0905 http www celeritous com CTS9513 5 Chan 16 bit 50MHz Counter Timer Param Description Figure Min Typ Units Tavi CD valid to Read Low L jJ 9 hs Tawh C D Vald to Write High L 2 9 Tdwh _ Data In Valid to Write High 24 5 Tehi Count Source High to Read setup time Note 2 7 94 ns Tehwh Count Source High to Write High setup time Note 3 7 ns Tg Gate valid to Write High Note 3 10 ns Trhax Read High to C D don t Care 2 o nS Trheh Read High to Count Source High Note 47 2 o hs Tm Read High to Data Out Invalid nS Trhaz Read H
37. T NOTICE Copyright 1997 Celeritous Technical Services Corp 11 RevC November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 806 783 0904 FAX 806 783 0905 http www celeritous com CTS9513 5 Chan 16 bit 50MHz Counter Timer CM31 CM30 CM29 CM28 CM27 CM26 CM25 CM24 CM23 CM22 CM21 CM20 CM19 18 CM17 CM16 RESERVED IPOL IMODE SRC1 16 Interrupt Interrupt Polarity Mode O Low 0 l High l Latch COUNTER MODE REGISTER LOW WORD 15 14 CM13 12 CM10 CM9 CM8 CM7 CM6 CM5 CM4 CM3 CM2 CM1 CMO GCTL3 GCTL2 GCTL1 EDGE SRC1 8 SRC1 4 SRC1 2 SRC1 1 RELOAD REPEAT COUNT DIR OUT4 OUT2 01 11 Gate Control Edge Count Source Selection With CM16 Gate Reload Repeat Count Count Output Control 000 No Gating Mode 00000 TC N 1 Mode Mode Mode Mode Direction 000 Inactive Output Low 001 Active High TC N 1 0 00001 Source 1 0 0ff 0zLoad 0 0 0 Down 001 Active High on TC Rising Binary 010 Active High Level GateN 41 00010 Source 2 1 0 1 Both 1 1 BCD 1 Up 010 TC Toggled Falling repeat 011 Active High Level GateN 1 00011 2 Source 3 011 lt Illegal ctive High Level GateN 100 Inactive Output High Z ctive Low Level GateN 101 lt Active Low on TC ctive High Edge GateN 110 Illegal 111 Active Low Edge GateN 111 Illegal 10011 FOUT 2 10100 11111
38. addressed by BP BP is autoincremented at the end of every Read or Write cycle on OL or PR 17 Programming Guide lower bytes are accessed first BP can be reset by Reset and Load Decoder RLD Each counter has a Filter Clock Prescaler PSC which is a programmable modulo N 8 bit counter driven by chip clock 20 MHz The divider N can be downloaded to PSC from PR low byte register using Reset and Load Decoder RLD Filter clock frequency 2x107 n 1 where n PSC 0 to RLD allows tranfer PR to CNTR transfer CNTR to OL reset CNTR BP and FLAG 5 Command register it 0 0 pop ses _ fi fof Reset Boron Compare sign tias lesom C 117 CEP EE nemo ee ieee Table 10 Command register bit assignments for RLD access 18 Programming Guide Conter Mode Register CMR allows programming of counter operational mode a ES RE spp zs JE EET E E E EE FERE Ec 8 Non recycle count Table 11 Command register bit assignments for CMR access 3 2 For detail description of Range Limit Non Recycle and Modulo N modes refer to LS7266R1 documentation Input Output Control Register IOR controls programmable input and output pins As MF 604 does not
39. al and a complex output waveform simultaneously The Interrupt output pin may be programmed for either polarity and for a pulsed or latched level output It is asserted each time the counter reaches TC The level interrupt output is cleared by software control upon acknowledging the interrupt This flexibility allows operation in a variety of bus and processor architectures Source Inputs Each counter group may be programmed for a vari ety of count sources including any of the five source input lines any of the internal prescaler outputs or the output of the previous counter allowing counter concatenation and FOUT divided outputs CTS9513 5 Chan 16 bit 50MHz Counter Timer FREQ 7 put mux Nr ie arr hoi Hraisren ire i CONTER oureur eur MODE CONTROL 16 BIT LOAD REGISTER TERM COUNT 7 Figure 6 CTS9513 Counter Groups 3 5 Gate Inputs Gate inputs are used for external hardware triggering or synchronization of the counters Each counter may be programmed to be gated from its own gate line or the gate lines from the previous or next counter The gate lines may also be programmed to be level or edge sensitive and respond to active high or low signals The gate line may be used to either initiate one or more count sequences or used as a count enable line allowing the counter to count only while the gate line is held active Another mode allow
40. as the Index input at a time and hence only one type of in dexing function can be performed in any given set up The index function must be disabled in non quadrature count mode IDR 7 6 5 4 3 2 1 o L 1 1 o Disable Index Enable Index Negative Index Polarity Positive Index Polarity LCNTRILOL pin is indexed See Note 1 RONTR ABG pin is indexed See Note 2 o Not used Select IDR 0 Select IDR addressed by XIY input 1 Select both XIDR and YIDR Note D7 1 overrides X Y input Note 1 Function selected for this pin via IOR becomes the operating INDEX function Note 2 RCNTR ABG input must also be initialized as the reset CNTR input via IOR REGISTER ADDRESSING MODES RD WR XY 07 06 05 cs FUNCTION X X x x x x x 1 Disable both axes for Read Write x x x 0 0 0 Write to byte segment addressed by XBP Note 3 X X X 0 1 1 0 Write to YPR byte segment addressed by YBP Note 3 0 0 0 1 1 L 0 0 Write to XRLD 0 0 0 1 1 1 0 Write to YRLD 1 0 0 1 1 L x 0 Write to both XRLD and YRLD 0 0 1 1 1 LI 0 0 Write to XCMR 0 0 1 1 1 1 0 Write to YCMR 1 0 1 1 1 x 0 Write to both XCMR and YCMR 0 1 0 1 1 Tale 0 0 Write to XIOR 0 1 0 1 1 1 0 Write to YIOR 1 1 0 1 1 x 0 Write to both XIOR and YIOR 0 1 1 1 1 0 0 Write to XIDR 0 1 1 1 1
41. ata Pointer Sequencing enabled 8 Frequency scaling Binary C7 C6 C5 C4 C3 C2 C1 CO Command Register Bit S Status of the counter interrupt outputs 1 1 H o o lo o 0 iar MM14 Enable Data Pointer Sequencing 1 1 1 0 fO 1 1 0 Clear MM12 FOUT Gate On When reporting the status of the counter output the T H 1 lo 1 TH 1 clear M13 Enable 8 bit Bus Mode Z 11111 0 1 10 O 0 SetMM14 Disable Data Pointer Sequencing C5 63162 co Command Register Bit I ITT 0 FOUT O Sueneg 55 54 53 52 51 51 5 Counter Group Select 1 1 1 0 1 1 1 SetMM13 Enable 16 bit Bus Mode 1 1 1 1 0 0 0 0 Originally Reserved 0 0 1 55 54 53 52 51 Arm Selected Counters 1 1 1 1 1 1 0 Originally Reserved 0 1 0 55154 53 52 51 Load Selected Counters i o 1 1 5 54 53 52 51 Load and Arm Selected Counters ips pravo erc Clear AN nemis 0g Reserved 1 o 0 155 54 53 52 51 Disarm and Save Selected Counters 0 0s Enable Write 1 0 1 55 54 53 52 51 Save selected counters to Hold Registers 1 1 1 1 1 0 0 1 Disable Write Pre Fetch 1 l 0 55 54 53 52 51 Disarm Selected Counters 1 1 1 1 O 1 0 Clear Counter 1 Interrupt Orig Reserved 1 1 1 1 1 0 1 Clea
42. cle See Fig 2 WR Pulse Width Wi CS Set up Time w2 CS Hold Time W3 C D Set up Time WA C D Hold Time W5 Set up Time W6 X Y Hold Time W7 Data Bus Set up Time W8 Data Bus Hold Time w9 Back to Back Write Delay twio Quadrature Mode See Fig 3 5 FCK High Pulse Width 1 FCK Low Pulse Width 2 FCK Frequency FCK Mod n Filter Clock FCKn Period 3 FCKn frequency FCKn Quadrature Separation 4 Quadrature Clock Pulse Width 5 Quadrature Clock frequency QA Quadrature Clock to Count Delay toi X1 X2 X4 Count Clock Pulse Width 102 Index Input Pulse Width idx Index Skew from A Ai Carry Borrow Compare Output Width Q3 Non Quadrature Mode See Fig 6 7 Clock A High Pulse Width 6 Clock A Low Pulse Width 7 Direction Input B Set up Time 85 Direction Input B Hold Time 8H Gate Input ABG Set up Time GS Gate Input ABG Hold Time GH Clock Frequency non Mod N A Clock Frequency Mod N AN Clock to Carry or Borrow Out Delay 9 Carry or Borrow Out Pulse Width 10 Load CNTR Reset CNTR and Load OL Pulse Width 11 Clock to Compare Out Delay 12 Min Value 50 50 0 50 10 50 10 50 60 30 30 30 10 30 10 30 10 60 14 14 28 115 20 50 Max Value 35 35 4 3 6ts 28 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz ns ns MHz ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns Remarks Access starts when both RD
43. dress 0x00 will write data to the Counter mode register 2 If the 8 bit transfer mode is selected the next write to the Primary Data Port Ad dress will expect the least significant word of the register value followed by a write of the most significant word to the data port The internal word pointer is automatically incremented 3 automatic sequence command has been given the data pointer will automati cally be sequenced to the next register READING REGISTERS Reading from a device register follows the write sequence very closely requiring a write to the com mand register to set the appropriate data pointer followed by a read or reads from the data port Several items should be noted when reading from the device registers 1 The data pointer should always be reloaded before reading from the data port if the prior command was anything but a LOAD DATA POINTER command in order to update the Read data pre fetch latch 2 ALOAD DATA POINTER command Should be issued to the device prior to reading a HOLD register following a hardware triggered SAVE of the counter contents to the HOLD register COMMANDS COUNTER COMMANDS Counter commands are divided into two main groups Those commands which directly affect counter operation often shortcuts to programming specific register functions and those associated with indirectly addressing the countersinternal registers Counter control commands can be further subdivided in
44. e Hold register at terminal count or alternately loaded from the Load and Hold register at terminal count Alarm Register Counters 1 and 2 contain an additional 16 bit Alarm register and corresponding 16 bit comparator When the value in the counter matches the value stored in the Alarm register the output pin for the counter goes true The output remains true as long as the counter value matches the Alarm register value The output may be programmed for active high or active low by the counter mode register COUNTER REGISTER Each counter group contains a mode control register which controls the counter behavior gating and out put active states and polarities and counter source The counter mode register is initialized at power up to all zeroes This translates to an initial counter mode of Output Low impedance to Ground Count Down Count Binary Count Once Load Register Selected No Retriggering F1 source selected Positive true input polarity No Gating O1 The Counter Mode Register must be loaded while the counter is disarmed Table 10 summarizes the Counter Mode Register bit assignments Output Control Bits CMO 2 The counter output may be configured to be disabled programmed to follow the counter terminal count or to toggle its state at each terminal count The output logic for each counter is shown in Figure 8 PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOU
45. e and reliable However LSI Computer Systems Inc assumes no responsibilities for inaccuracies nor for any infringements of patent rights of others which may result from its use Input Output Control Register XIOR and YIOR The functional modes of the programmable input and output pins are written into the IORs IOR 314 3 21 m 0 Disable inputs A and 1 Enable inputs A and B 0 LCNTR LOL pin is Load CNTR input 1 LONTR LOL pin is Load OL input 0 RONTR ABG pin is Reset CNTR input 1 RCNTR ABG pin is A and B Enable gate ol FLG1 pin is CARRY output FLG2 pin is BORROW output 4 X FLG1 pin is COMPARE output FLG2 pin is BORROW output 0 E N FLG1 pin is Carry Borrow output and FLG2 pin is U D FLAG register bit 5 J 15 1 FLG1 is IDX FLAG register bit 6 FLG2 is E FLAG register bit 4 0 Select IOR rie 0 Select IOR addressed by X Y input 1 Select both XIOR and YIOR together Note D7 1 overrides X Y input INDEX CONTROL REGISTERS XIDR and YIDR Either the LCNTR LOL or the RCNTR ABG inputs can be initialized to operate as an index input When initialized as such the index signal from the encoder applied to one of these inputs performs either the Reset CNTR or the Load CNTR or the Load OL operation synchronously with the quadrature clocks Note that only one of these inputs can be selected
46. egardless of the state of the Gate line Gate edges received prior to TC will store the current count in the Hold register Once the counter has reached TC the counter will stop until a subsequent gate edge is received Gate edges ap plied to an unarmed counter have no effect Specification TTL Input LOW Level TTL Input HIGH Level X2 Input LOW Level X2 Input HIGH Level Vo Output LOW Level o 4mA 0 4 Volts V Output HIGH Level o 4mA 24 Volts 12 Input Leakage Current 10 10 pp Supply Current No Load F osc 7MHz 20 mA pps IDD Static 10 uA Cw Pin Capacitance 10 pF Table 12 CTS9513 Electrical Characteristics PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp 25 Rev November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 806 783 0904 FAX 806 783 0905 http www celeritous com CTS9513 5 Chan 16 bit 50MHz Counter Timer Teta Trheh n Tehwh Twheh 7 EE 1 H countsourceE Xi Tovwh b Twhgv 1 1 N GATE X X Trhsh Hi Twhsh m B 11 Tslwh 1 cs iq v9 NET ts on 1 Trhax a m Twhax iD cD X X PET 1 n I H I
47. errides all software commands to place the outputs in a high impedance state This allows external hardware interlock control over the counter outputs An extension to the Status register allows software monitoring of the state of this line FEATURE EXTENSIONS Output Polarities Pd asd ane Haan Auxiliary Master Mode Register his 1 ds olarities An auxiliary Master Mode Register has been added Software nota serie to accommodate programming of new features The U gi triggering primary Master Mode Register remain the same as in z BCD eine al eee the 9513 for software compatibility At power on and Real ti y S d at reset both Master Mode registers are reset to all Aa s Sout regis in ne zeros If no subsequent writes are made to the osn P On 5 auxiliary Master Mode register or as long as all writes sp 9 ble i q y k li are zero filled in the high word there is no difference rogrammable internal clock pre scaling in operation from the 9513 as extended features will not be enabled Symbol Description Min Max Units V pp DC Supply Voltage 0 3 7 Volts Vin Input Voltage at Any Pin 0 3 Volts op Operating Temperature AxC Axl 0 40 70 85 C Storage Temperature 55 150 Table 1 Absolute Maximum Ratings PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp RevC November 97
48. ers INTERNAL CONFIGURATION d INT COUNTER 5 ours Figure 4 CTS9513 Counter Block Diagram Overview A simplified block diagram of the CTS9513 is shown in Figure 4 This diagram shows the major device elements consisting of the five counter groups inter nal frequency prescaler which divides down the pri mary external clock source from clock input X1 the external FOUT clock prescalers which provide prescaled or divided outputs from a variety of Sources the Bus interface Master mode register and the status register Not shown are the extended set registers power on reset circuitry or internal control lines The counter group block diagrams are shown in Figures 5 and 6 Counter groups 1 and 2 as shown in Figure 5 have an additional programmable alarm register and 16 bit comparator for implementation of time of day and alarm functions cs RD WR Dx 1 X X X High Impedance 0 0 1 0 Read Data 0 0 1 1 Read Command 0 1 0 0 Write Data 0 1 0 1 Write Command 0 0 0 X Illegal Table 3 CTS9513 Bus Control Line States PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp RevC November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 806 783 0904 FAX 806 783 0905 Attp www celeritous com 16 BIT ALARM REGISTER
49. ference between these signals will manifest itself by operation initiated by the write and the counter may be off by causing counters using two different F signals to count at one count different times on nominally simultaneous transitions in the F 4 Any input transition that occurs after this minimum hold time is signals F1 X2 guaranteed to not influence the contents read from the status 12 This timing specification assumes that CS is active whenever register on the current read operation RD or WR are active CS may be held active indefinitely 5 Any input transition that occurs after this minimum hold time is 18 This parameter assumes X2 is driven from an external gate guaranteed to be seen by the counter as occurring after the with a square wave he action initiated by the write operation and the counter may be off 14 This parameter assumes that the write operation is to the by one count command register 6 This parameter applies to cases where the write operation 15 This timing specification applies to single action commands causes a change in the output bit only e g LOAD ARM SAVE etc For double action com 7 The enabled count source is one of F1 F5 TCN 1 SRC1 SRC5 mands such as LOAD AND ARM and DISARM AND SAVE or GATE1 GATE 5 as selected in the applicable Counter Mode TWHEH minimum 700ns register The timing diagram assumes the counter counts on 16 In short data write mode TWHRL TWHWL minimum
50. filter 0 2 50 us Introduction Quadrature input frequency up to 2 MHz Software selectable index pulse operation 9513A 5 channel timer counter with 50 ns resolution 8 bit TTL compatible digital input port 8 bit TTL compatible digital output port switch selectable I O port base address Software selectable interrupt Requires 16 bit ISA slot and optional second slot for second connector Power consumption 400 mA Q 45V 50 mA 12V 50 mA 12V Operating temperature 0 to 70 1 3 Specifications 1 3 1 A D Converter Resolution 12 bits Number of channels 8 single ended Conversion time 10 us Input ranges 10V 5V 0 10V 0 5V software selectable Input protection 16 5 Input impedance gt 10 1 3 2 D A Converter Resolution 12 bit Number of channels 4 Settling time max 10 us 1 2 LSB Slew Rate 10 V us Introduction Output current min 5 mA Short circuit current 30 mA DC output impedance 010 Load capacitance max 500 pF Differential nonlinearity 1 LSB Gain drift typ 5 ppm K Zero drift typ 5 ppmFSR K 1 3 3 Digital Inputs Number of bits 8 Input signal levels TIL Logic 0 0 8 V max Logic 1 2 0 V min 1 3 4 Digital Outputs Number of bits 8 Output signal levels TTL Logic 0 0 5 V max 24 mA sink Logic 1 2 0 V min 15 mA source 1 3 5 Quadrature Encoder Inputs Number of axes 4 independent Resolution 2
51. ge of low level pulse applied to this input Read input A low level applied to this input enables the FLAGs and OLs to be read on the data bus Chip select input A low level applied to this input enables the chip for Read and Write Control Data input This input selects between a control register or a data register for Read Write When low a data register is selected When high a control register is selected Data Bus input output The 8 bit three state data bus is the I O port through which all data transfers take place between the LS7266R1 and the host processor Filter clock input in quadrature mode The FCK is divided down internally by two 8 bit programmable prescalers one for each channel Selects between X and Y axes for Read or Write X Y 0 selects X axis and X Y 1 selects Y axis X Y is overridden by D7 1 in Control Write Mode C D 1 5VDC GND tri trio RD tr2 4 4 cs tra 15 gt c D tre gt t7 tro IL LLL BB ME ge gt ymma X 7771 FIGURE 1 READ CYCLE twi tw10 4 tw2 CS 4 tw3 lt tw5 C D twe tw gt XY lt two gt DB INPUT DATA INPUT DATA FIGURE 2 WRITE CYCLE st t2 FCK t3 FCKn Note 4 t5 gt A t4 t4 a t4 4 B t5 FIGURE 3 FILTER CLOCK FCK AND GUADRATURE CLOCKS A AND B Note 4 FCK is the final modulo n internal filter clock arbitraril
52. han 16 bit 50MHz Counter Timer source J y FAX FAX D C care EO J COUNT VALUE La TC OUTPUT Y a Yue Y TOGGLE OUTPUT X X COUNTER MODE K WAVEFORMS Figure 20 CTS9513 Counter Mode K Representative Waveforms sse f X w TC OUTPUT TOGGLE OUTPUT COUNTER MODE L WAVEFORMS Figure 21 CTS9513 Counter Mode L Representative Waveforms K VARIABLE CycLE RATE GENER ATOR WITH LEVEL GATING Mode K is similar to Mode J with the exception that the counter is enabled only after being ARMed and when the selected Gate line is asserted When the Gate line is deasserted the counter stops This allows the gate to modulate the duty cycle of either state as illustrated in Figure 20 Mope L HARDWARE TRIGGERED DELAYED PULSE ONE SHOT Mode L is used often as an externally triggered delayed pulse generator where the delay and pulse width are both programmable Like Modes J and K the counter cycles through the load count reloads from the hold at the first TC and counts to the second TC Unlike Modes J and K however the counter is only active after being ARMed and after a valid gate edge is received As shown in Figure 21 the gate edge initiates one count cycle and is disregarded for the rest of the cycle After one count cycle Load and Hold the counter stops u
53. he figures to denote Load and Hold register values and the letters K and N to denote arbitrary counter values In all cases the counter begins counting on the first count source edge following the Write pulse in soft ware triggered modes and the first source edge following a valid gate edge in hardware triggered or enabled modes In gate controlled modes which inhibit counting the counter is suspended for any valid source edges that occur after de assertion of the gate line OPERATING MODE CM7 SPECIAL GATE CM6 RELOAD SOURCE CM5 REPITITION CM13 15 GATE CONTROL 000 Count to TC Once X Countto TC Twice Countto TC repeatedly Gate Input Inactive x Count while gate active x Count once on gate edge Count twice on gate edge No Hardware retriggering x x Reload from Load on TC x x Alternate Load Hold on TC Gate Controlled Load Hold Gate Retrigger Counter gt P lt lt lt x ce e ceo lt 000 room LVL 6 H 0 0 1 1 0 0 000 LVL X X x x X x x x Table 11 Counter Modes A L oro EGD F2 F3 F4 F5 F6 F7 000 K L 0 0 1 1 1 1 LVL X X x x x x x x PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp 14 Rev C November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 OPERATING MO
54. http www celeritous com CTS9513 5 Chan 16 bit 50MHz Counter Timer source V NV f NV f Nf Nf WR COUNT VALUE m GATE Ce Y Y x Ye d x TC OUTPUT TOGGLE OUTPUT COUNTER MODE E WAVEFORMS Figure 14 CTS9513 Counter Mode E Representative Waveforms source V N V NV Vf m DATA GATE COUNT VALUE ti TC OUTPUT TOGGLE OUTPUT COUNTER MODE F WAVEFORMS Figure 15 CTS9513 Counter Mode F Representative Waveforms Mope E RATE GENERATOR WITH LEVEL GAT ING Mode E is similar to Mode D in that the counter will count repetitively after being ARMed and as long as the selected Gate line is asserted As shown in Figure 14 this allows gating of the pulse train or square wave on and off from an external source via the gate line Mope Non RETRIGGERABLE ONE SHOT Mode F is similar to Mode C with the exception that the counter may be retriggered without receipt of a new ARM Command As shown in Figure 15 Once the counter has been ARMed and a valid Gate edge has been received the counter will count once to TC and reload the counter from the Load register It will remain inactive until receipt of another Gate edge While counting subsequent gate edges are disre garded PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Co
55. ibit the counter as in Mode Q PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp RevC November 97 23 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 806 783 0904 FAX 806 783 0905 http www celeritous com CTS9513 5 Chan 16 bit 50MHz Counter Timer SOURCE WR ARM COMMAND GATE COUNT VALUE m v2 2 TC OUTPUT TOGGLE OUTPUT COUNTER MODE 5 WAVEFORMS Figure 26 CTS9513 Counter Mode S Representative Waveforms SOURCE Xf LIVIN HER RTE TR OU HN WWWW GATE U COUNT VALUE H 1 TC OUTPUT TOGGLE OUTPUT Y COUNTER MODE V WAVEFORMS Figure 27 CTS9513 Counter Mode V Representative Waveforms Mope S GATE CONTROLLED STROBE In Mode S once ARMed the counter will count to TC twice and disarm During this time the State of the Gate line determines whether the counter is loaded from the Load or Hold Register The Gate line does not affect or initiate the counter in this Mode Its only action is a level sensitive selection of the Load or Hold Register as a counter reload source As shown in Figure 26 at each TC in the cycle if the Gate line is high the counter will be reloaded from the Hold Register If it is Low the counter is reloaded from the Load Register Mone V FREQU
56. igh to Data Out Bus Release Time 2 ses Tri Read High to Read Low Read Recovery Time ns Trhsh ReadHighto CS High Note 12 nS Tw High to Wite Low Read Recovery Time nS Tiv Read Low to Data Out Valid 2 156 Trig Read Low to Data Bus Driven Bus Drive Time 24 ds Read Low to Read High Read Pulse Duration Note i2 2 12 Tsin CSLowtoReadLow Note 12 L jJ 9 Tswh CS Low to Write High Note 12 nS Twhax ite High to C D Dont Care 2 Wite High to Data In Dont Care nS Twheh Write High to Count Source High Note 5 7 14 15 2 20 nS Twhg Miite High to Gate valid Note 5 10 14 2 20 nS Twhd High to Read Low Wite Recovery Time Note 16 ns Twhsh High to CS High Note 12 nS Twhw Wite High to Wite Low Wite Recovery Time Note 16 nS Table 14 Bus Timing Specifications NOTES the counter may be off by one count 1 10 This parameter assumes that the GATENA input is unused 2 Any Input transition that occurs before this minimum setup 16 bit bus mode or is tied high In cases where the GATENA requirement will be reflected in the contents read from the input is used this timing specification must be met by both the status register GATE and GATENA inputs 3 Any Input transition that occurs before this minimum setup 11 Signals F1 F5 cannot be directly monitored by the user The requirement will act on the counter before the execution of the phase dif
57. it In range limit count mode an upper and a lower limit is set mimicking limit switches in the me chanical counterpart The upper limit is set by the content of the PR and the lower limit is set to be 0 The CNTR freezes at CNTR PR when counting up and at CNTR 0 when counting down At either of these limits the counting is resumed only when the count direction is reversed Non Recycle In non recycle count mode the CNTR is disabled whenever a count overflow or underflow takes place The end of cycle is marked by the generation of a Carry in Up Count or a Borrow in Down Count The CNTR is re enabled when a reset or load operation is performed on the CNTR Modulo N In modulo N count mode a count boundary is set between 0 and the content of PR When counting up at CNTR PR the CNTR is reset to 0 and the up count is continued from that point When counting down at CNTR 0 the CNTR is loaded with the content of PR and down count is continued from that point The modulo N is true bidirectional in that the divide by N output frequency is generated in both up and down di rection of counting for same N and does not require the complement of N in the UP instance In frequency di vider application the modulo N output frequency can be obtained at either the Compare FLG1 or the Borrow FLG2 output Modulo N output frequency fN fi N 1 where fi Input count frequency and N PR The information included herein is believed to be accurat
58. ith each X and Y axis All X axis registers have the name prefix X whereas all Y axis registers have the prefix Y Selection of a specific register for Read Write is made from the decode of the three most significant bits D7 D5 of the data bus CS input enables the IC for Read Write C D input selects between control and data information for Read Write Following is a complete list of LS7266R1 registers Preset Registers XPR and YPR Each of these PRs are 24 bit wide 24 bit data can be written into a PR one byte at a time in a sequence of three data wri les te cycles 7 0 7 07 0 BYTE LO BYTE PR2 PR1 PRO Counters XCNTR and YCNTR Each of these CNTRs are 24 bit synchronous Up Down counters The count clocks for each CNTR is derived from its associated A B inputs Each CNTR can be loaded with the content of its associated PR Output Latches XOL and YOL Each OL is 24 bits wide In effect the OLs are the output ports for the CNTRs Data from each CNTR can be loaded into its associated OL and then read back on the data bus one byte at a time in a sequence of three data Read cycles OL 7 07 0 7 0 HI BYTE MIDBYTE LO BYTE 0L2 OL1 OLO Byte Pointers XBP and YBP The Read and Write operations on an OL or a PR always accesses one byte at a time The byte that is accessed is addressed by one of the BPs At the end of every data Read or Write cycle on an OL or a PR the
59. ith the CS RD and WR to select which internal command or data register is being written to or read from The C D line selects between the command and data register sets as sum marized in Table 3 EXTENDED I O SIGNALS The following signals are extensions to the original AM9513 device and are available only in the PQFP 100 package The DIP 40 and PLCC 44 packaged devices will operate normally in their absence INT 1 5 Interrupt Outputs PQFP 100 pkg only The interrupt lines are associated with individual counter outputs and may be used to generate system interrupts on the terminal count of a counter The interrupt lines are asserted as either a pulse or level on the terminal count of a counter Output polarity of the interrupt may be individually programmed for PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp Rev November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 806 783 0904 FAX 806 783 0905 http mww celeritous com SOURCE 1 5 CTS9513 5 Chan 16 bit 50MHz Counter Timer GATE 1 5 osc CLK IN 24 BIT PRESCALER ints COUNTER 1 our surrer BTDWDER Le 16 BIT STATUS INT 2 COUNTER 2 gt OUT2 REGISTER INT 3 COUNTER 3 2 OUTS INT 4 COUNTER 4 OUT 4 BT MASTER MODE REGISTER
60. l filter clock frequency frckn 1 where n PSC 0 to FFH Reset and Load Signal Decoders XRLD and YRLD Following functions can be performed by writing a control byte into an RLD Transfer PR to CNTR Transfer CNTR to OL reset CNTR reset FLAG and reset BP RLD 7 6 5 4 3 2 1 0 0 NOP 1 Reset BP 4 04 o 14 Reset CNTR 0 04 Reset BT CT 5 1 ts 1 Reset E NOP Transfer PR to CNTR p Note All 24 bits are transferred in parallel Transfer CNTR to OL ad Note All 24 bits are transferred in parallel Transfer PRO to PSC Select RLD 1 0 Select the RLD addressed by X Y input 1 Select both XRLD and YRLD together Note D7 1 overrides X Y input Counter Mode Registers XCMR and YCMR The CNTR operational mode is programmed by writing into the CMRs CMR z el sl al sl al 1 o 0 Binary count 1 BCD count Normal count Range Limit Non recycle count Modulo N Non quadrature 0 1 Quadrature X1 gd 4 0 Quadrature X2 e 11 Quadrature 13 17 Select CMR 0 Select CMR addressed by X Y input 1 Select both XCMR and YCMR together Note D7 1 overrides X Y input DEFINITIONS OF COUNT MODES Range Lim
61. m to the original AM9513 device vcc 5 Volt Power Supply VSS Ground X1 External Crystal Crystal should be parallel resonant fundamental mode type When driven from an external source X1 should be left open X2 External Crystal If driven from an external Source X2 should be connected to a TTL source and pulled up to VCC FOUT Frequency Divider Outputs The FOUT line is generated by internally pro grammable counters The clock source for these counters may be any of the external GATE or SOURCE inputs as well as any of the internally prescaled clock outputs SOURCE1 5 Count Source Inputs Source inputs 1 5 provide external clock Source lines which may be routed to any of the internal counters or the FOUT divider The active count edge for the source is pro grammed at the counter GATE1 5 Counter Gate Inputs Gate inputs are used to control counter be havior Any gate may be routed to one of three internal counters They may also be used as clock or count input sources for the internal counters or FOUT divider The GATE lines may be programmed for use as counter enables counter triggers or inhibits and to switch between two different frequencies In dividual counters may be programmed for active polarity as well as to be level or edge sensitive to the GATE line In the CTS9513 the auxiliary GATEN A lines which were originally multiplexed with Data lines D8 12 in the AM9513 are not implemented OUT1 5 Counter
62. n effectively retriggering the counter as shown in Figure 22 One application of this mode is to measure the delay between two successive gate edges by reading the remainder count value from the hold register Mops O SOFTWARE TRIGGERED STROBE WITH EDGE GATING AND HARDWARE RETRIGGERING Mode O is similar to Mode N in that the counter must be ARMed and a valid Gate edge must be received to start the counter Unlike most other modes however each time a valid gate edge is received prior to the counter reaching TC will cause the counter to be retriggered by reloading the counter from the load register on the first valid source edge following a valid gate edge If the counter is allowed to reach TC is automatically reloads from the Load register and disarms itself The counter is insensitive to gate edges while dis armed and while counting The counter is sensitive only to a valid gate edge while counting PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp RevC November 97 806 783 0904 FAX 806 783 0905 http www celeritous com Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 CTS9513 5 Chan 16 bit 50MHz Counter Timer source Wm WR care ARMAR 0 count VALUE Xv Y Yna y u BTE Y Xe fef OUTPUT TOGGLE OUTPUT y
63. nally Reserved Alarm Register 1 Control Cycle Counter 2 Aux Mode Originally Reserved Counter 1 Load Register Counter 2 Load Register Counter 3 Load Register Counter 4 Load Register Counter 5 Load Register Counter 3 Aux Mode Originally Reserved Alarm Register 2 Control Cycle Counter 4 Aux Mode Originally Reserved Counter 1 Hold Register Counter 2 Hold Register Counter 3 Hold Register Counter 4 Hold Register Counter 5 Hold Register Counter 5 Aux Mode Originally Reserved Master Mode Register Control Cycle Aux Master Mode Originally Reserved Hold Register Cycle Hold Register Cycle Hold Register Cycle Hold Register Cycle Hold Register Cycle Originally Reserved Status Register ererererererererererererererererererererererejererepereyererere mpEgmpmsspmpmpmmrmszsmmgmperesrersrisrtrerirrerirese 444 444 lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt 4 s as EEE 4 4 lt ES EEE SEE Table 4 CTS9513 Data Pointer Commands PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOT
64. nded to 6 bits The FOUT counter may now be programmed for divide by 1 to 63 inclusive The original four bit Master Mode register counter program controls the least significant four bits of FOUT to provide maximum backwards compatibility The auxiliary Master Mode register contains the program bits for the additional divider Command Registers The command register remains the same as the 9513 with only the lower 8 bits used Previously unused commands in the 9513 are utilized for the extended features such as Interrupt output control and auxiliary register addressing This preserves the original two port address access for the timer INTERFACE SicNALS PACKAGING Figure 2 illustrates the DIP 40 Package pinout of the device which conforms to the original AM9513 pinouts Table 2 summarizes the pinouts of the PLCC 44 package illustrated in Figure 3 which conform to the original AM9513 pinouts Table 3 summarizes the CTS9513 device pinouts and signal names for the QFP 100 package illus trated in Figure 4 Pinouts are optimized for ease of layout CTSC9513A x Package Plastic DIP 40 Plastic PLCC 44 J Plastic PQFP 100 Q Temperature Range Commercial 0 70 C Industrial 40 85 C I Maximum Clock Speed 20 MHz 2 50 MHz 5 Table 2 CTS9513 Ordering Information
65. ntil another gate edge is received PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp Rev November 97 806 783 0904 FAX 806 783 0905 http www celeritous com Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 FAFAFAFAFAFAFAJ SOURCE CTS9513 5 Chan 16 bit 50MHz Counter Timer w cave OUTPUT TOGGLE OUTPUT COUNTER MODE N WAVEFROMS Figure 22 CTS9513 Counter Mode Representative Waveforms source GATE COUNT VALUE TC OUTPUT TOGGLE OUTPUT COUNTER MODE 0 WAVEFORMS Figure 23 CTS9513 Counter Mode O Representative Waveforms Sortware TRIGGERED STROBE WITH LEVEL GATING AND HARDWARE RETRIGGERING In Mode N once ARMed the counter is active only as long at the selected Gate line is asserted Counting begins only after the gate line is asserted after the counter is ARMed If the Gate line remains asserted the counter will count to TC reload automatically from the load register and disarm itself until receipt of anew ARM command If the gate is deasserted prior to the counter reaching TC the counter will halt When the Gate line is reasserted on a halted counter the count value is transferred to the Hold register and the next valid count source edge will cause the counter to reload from the Load register and begin counting agai
66. o 1 otherwise more than one interrupt will be enabled 23 Programming Guide Table 14 IRQEN Register Bit Assignment 24 I O Signals 4 I O Signals 4 1 Output Connector Signal Description The MF 604 multifunction I O card is equipped with an on board 37 pin D type female connector X1 and with an aditional 37 pin D type female connector X2 on cable extender For pin assignment refer to Tables 15 and 16 TB 620 Terminal Board can be connected to both connectors ADO AD7 Analog inputs DAO DA3 Analog outputs DINO DIN7 TTL compatible digital inputs DOUTO0 DOUT7 TTL compatible digital outputs IRCO IRC3 Quadrature encoder A B and Index inputs TOIN T3IN Timer counter gate and clock inputs TOOUT T3OUT Timer counter outputs 12V 12V power supply 12V 12V power supply 5V 5V power supply AGND Analog ground GND Digital ground 25 1 0 Signals e phe asi m a s e m 7 m ES Him pem bw f 37 DOUT7 Table 15 X1 Connector Pin Assignement DIN2 26 1 0 Signals 20 IRCOA mee EE mer up mex fe af mew 37 T3OUT Table 16 X2 Connector Pin Assignement 27 Contact Address Contact address HUMUSOFT s r o Nov kovych 6 180 00 Praha 8 Czech Republic tel 420 2 66315767 tel fax 420 2 6844174 E mail info humusoft cz Homepage http www humusoft cz 28 LSI CSI 187266 1 m E 151 Comp
67. ontains CTS9513 timer counter chip with 20 MHz input clock The first four timers are accessible through external connector X2 while the fifth timer can generate system interrupt if enabled by IRQEN register or can be used as a clock source for other timers or for similar internal functions Gate and clock inputs are connected together and sharing the same input pin TxIN on I O connector Therefore this pin can be used either as a clock source or as a gate source Inputs and outputs are TTL compatible Schmitt triggers are at all inputs to improve noise immunity CTS9513 timer is connected as 8 bit device Do not 21 Programming Guide program it to 16 bit mode CTS9513 is a powerfull counter timer chip offering wide range of operation modes allowing up down binary BCD counting internal or external clock and gate sources binary BCD prescaling one shot continuous outputs software external triggering programmable gate and output polarities time of day and alarm functions pulse counting frequency measurement pulse generation including PWM programmable clock source For detail low level documentation describing all modes of operation please refer to CTS9513 documentation in Appendix of this User s Manual Sample code for programming timer 1 as 1 kHz frequency generator master reset disables all counters timers loads 22 0x0000 to Master Mode register and all Load and Hold registers loads 0 0
68. r Counter 2 Interrupt Orig Reserved N4 N2 NI N1 4 Counter Group Select 001 N 1 1 1 1 1 1 0 0 clear Counter 3 Interrupt Orig Reserved 101 1 1 1 1 1 1 0 1 Clear Counter 4 Interrupt Orig Reserved 1 1 1 0 N4 N2 Ni Clear Selected Counter Toggle Out 1 1 l 1 0 Clear Counter 5 Interrupt Orig Reserved 1 l 1 j0 1 N2 NI SetSelected Counter Toggle Out 1 1 1 1 fl 1 1 1 MasterReset 1 1 1 n TNT Cten Calartad Counter inldewn hu Table 5 Counter Action Related Commands Table 6 Device Level Commands PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp Rev November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 806 783 0904 FAX 806 783 0905 Attp www celeritous com CTS9513 5 Chan 16 bit 50MHz Counter Timer 515 514 513 512 511 510 59 58 87 56 S5 S4 53 52 51 50 RSVD RSVD OUTEN 5 INT4 INT3 INT2 CMP2 CMP1 OUT5 OUT4 OUT3 OUT2 OUT1 WP RESERVED Output Interrupt Status Comparator Counter Output Status Byte Enable Reflects actual state of Interrupt Output Status Reflects Actual State of Output Prior to Pointer Status Tri State Buffer Table 7 Status Register Time of Day Bits 0 1 Bits and 1 control the Time of day functions for counters 1
69. rce high to FOUT Valid Count Source High to Out Valid eleh Prescaler Clock Skew Level Gating Setup Time Note 1 Gate Pulse Duration Note 2 Table 15 Counter Timing Specifications To Accompany Figure 31 Notes 1 This parameter applies to both level and edge gating representing the minimum setup or hold times to ensure that the Gate input is seen at the intended level on the active source edge or the counter may be off one count 2 This parameter applies to both level and edge gating representing the minimum gate pulse width needed to ensure the pulse initiates counter gating or reloading PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp 28 RevC November 97
70. red the external data bus is set to 8 bits and registers are loaded 8 bits at a time least significant word first Data Pointer Sequencing Bit MM14 When cleared this bit enables automatic sequencing of the data pointer as defined by the data pointer commands When set the data pointer contents may only be changed by command Scaling Bit MM15 This bit determines whether the internal frequency prescaler operates as a BCD or Binary Divider Figure 6 illustrates the internal 24 bit prescaler and its outputs COUNTER REGISTERS Load Register The load register is a read write counter register used to store the counter initial value The load register value can be transferred into the counter each time the counter reaches a terminal count A terminal count is defined as that period of time the counter value would have been zero if an external value had not been transferred into the counter In all operating modes the value in either the load or hold register is transferred into the counter when the counter reaches terminal count Hold Register The hold register is a read write dual purpose regis ter In some operating modes the hold register may be used to store counter instantaneous values on command without disturbing the counter action for readout by the host Other operating modes allow the hold register to be used as storage for counter values in a fashion similar to the Load register The counter may be loaded from th
71. rp 18 RevC November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 http www celeritous com 806 783 0904 FAX 806 783 0905 CTS9513 5 Chan 16 bit 50MHz Counter Timer source GATE TC OUTPUT TOGGLE OUTPUT DATA countvaue fus Y Y Y Y nz us Y xa L ra FA NA Figure 16 CTS9513 Counter Mode G Representative Waveforms SOURCE xd X X Li VJ P SI VSS OWNER D Y Ann Y care RA v WWW COUNT VALUE ii 2 Xa TC OUTPUT TOGGLE OUTPUT COUNTER MODE H WAVEFORMS Figure 17 CTS9513 Counter Mode H Representative Waveforms Mope G SOFTWARE TRIGGERED DELAYED Purse ONE SHOT In Mode G once the counter has been ARMed the counter will 1 Count to TC with the Load register value 2 Reload itself automatically from the Hold Register 3 Count to TC with the Hold Register Value 4 Disarm itself and reload the counter with the Load register Value This produces a waveform as illustrated in Figure 16 in which the counter can in TC mode produce a pair of pulses with the first pulse delay controlled by the Load count value and the delay between the pulses determined by the Hold register count If the Toggle Output mode is selected the output produced is a pulse width determined by the Hold count and an initial delay determined by the
72. s the counter to be reloaded from the load or hold register depend ing on the state of the gate line allowing dual frequency generation for FSK applications or similar functions PROGRAMMING REGISTER PROGRAMMING Data Bus Operation Table 3 summarizes the I O control signal and data status during bus reads and writes to the CTS9513 The interface control logic assumes that e RD and WR are never active simultaneously RD WR C D are ignored unless CS is asserted Register Programming Accessing and writing to a specific data or com mand register from the data port is as follows Set Data Pointer 1 Select the appropriate data pointer value to access the desired register example Counter group 1 Mode register 0x01 2 Write LOAD DATA POINTER command to primary command address write 0x0001 to device address 0x01 to set data pointer to Counter Group 1 Mode register This points the data port to the Group 1 mode register and set the word pointer to 1 indicating a least significant word is expected PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp RevC November 97 806 783 0904 FAX 806 783 0905 http www celeritous com Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 WRITING To REGISTERS Write Data to Register 1 If the 16 bit transfer mode is selected the next write to the Primary Data Port Device Ad
73. tatus Register indicates the 1 Status of the internal word pointer 2 Status of the counter outputs CTS9513 5 Chan 16 bit 50MHz Counter Timer status bit reflects the exact state of the output pin regardless of how the output pin state or toggle is programmed When an output low impedance to ground output is programmed the Status bit reflects and Active High status When the output is programmed for a high impedance output or is externally inhibited the status register reflects an active low output Table 7 sum marizes the status register bit assignments Master Mode Commands The Master Mode registers are 16 bit read Write registers used to set counter parameters not associ ated with individual counters These parameters in clude setting the data bus width prescaling factors Time of day functions and data pointer sequencing The primary Master Mode Register is identical in function to the original 9513 device The auxiliary Master Mode Register is used to program extended features of the CTS9513 If the auxiliary register is not programmed the device behaves as an original 9513 device Table 8 summarizes the primary and auxiliary Master Mode Register bit assignments On Power up the Master Mode register is cleared to all zeros resulting in the following default conditions 1 Time of Day disabled 2 Alarm Comparators Disabled 3 FOUT source is F1 4 FOUT divider set for divide by 16 5 FOUT enabled 6 Data Bus 8 bits 7 D
74. the 9513 capable of 33 Mhz clock speeds Imagine counter dynamic ranges of 30 nS to over 2 minutes in a single counter The 33 Mhz clock speed and full 32 bit data path make this a perfect PCI bus compati ble peripheral device PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp Rev November 97 Celeritous Technical Services Corp PO Box 65600 1200 Lubbock Texas 79464 5600 DEVICE DESCRIPTION The CTS9513 is a custom high speed gate array implementation and extension of the AMD AM9513 System Timing Controller The 9513 has long been the most versatile counter timer peripheral device featuring far more flexibility than competing timing devices such as the Intel 8253 8254 Motorola 6840 or others A large installed base of devices and software drivers already exists 806 783 0904 FAX 806 783 0905 http www celeritous com The principal limitation of the AM9513 was its maxi mum frequency limitation of 7 Mhz imposed by its late 19708 NMOS LSI design The CTS9513 shat ters this barrier with a 50 MHz maximum clock speed The CTS9513 Counter Timer is capable of a wide variety of applications including but not limited to Event Counting Event Sequencing Programmable pulse generation Programmable delay generation Frequency counting Frequency synthesis Real Time Clock Alarm Clock Functions Watchdog Timing Retriggerable Pulse Generation Non Re
75. tional Sources may be programmed using the ex tended Master mode register functions FOUT1 Divider Bits MM8 11 FOUT may be divided by 1 to 256 Master mode bits 8 11 allow programming of the FOUT divider from 1 to 16 inclusive Higher order division factors are programmed through the extended Master Mode the comparators are routed to the output of the register functions counter The output will be asserted when the com 15 14 AMM13 12 AMMII 10 9 AMM8 AMM7 AMM6 5 4 AMM3 AMM2 AMMI AMMO RSRVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD DIVI 32 DIVI 16 FOUTI 16 Ext FOUT Source and Divider Bits 15 14 13 MM12 11 10 MM9 MM8 MM7 MM6 MM5 MM4 MM3 MM2 MM1 MMO SCALE POINT BUS FGATE1 DIVI 8 DIV1 4 DIV1 2 DIV1 1 FOUTI 8 FOUT1 4 FOUT1 2 FOUTI 1 COMP2 COMP1 1002 1001 Scale Data Data Bus FOUT FOUT Divider Including AMM1 2 FOUT Source Select With AMMO Comparator Time of Day Mode Mode Pointer Width Mode Mode 0 Binary 0 Enable 0 8 0 0 000000 Divide by 16 00000 F1 00 Disabled 00 00 Disabled 1 BCD 1 Dis 1 16 1 0ff 000001 Divide by 1 00001 Source 1 01 Comparator 1 01 TOD Enabled 5 able 000010 Divide by 2 00010 Source 2 10 gt Comparator 2 10 TOD Enabled 6 000011 Divide by 3 00011 Source 3 11 Both On 11 TOD Enabled 10 000100 Divide by 4 000101 Divide b
76. to those commands which affect individual counter operation and those which affect the overall device operation Table 4 Lists the commands associated with indirect addressing of the counter internal registers These commands point the data port to the appropriate internal register in order to read or write to them CTS9513 5 Chan 16 bit 50MHz Counter Timer Table 5 Lists the commands associated with control ling the actions of individual counters They are made up basically of the ARM DISARM LOAD SAVE CLEAR SET and STEP commands ARM Command A counter must be ARMed before it can commence counting Once ARMed a counter may be pro grammed to begin counting immediately or to await a hardware trigger to initiate counting DISARM Command The DISARM command halts and disables any fur ther counting regardless of any hardware gating or triggering While DISARMed a counter may be reloaded SAVEd or incremented or decremented using the STEP Command LOAD Command The LOAD command is used to load the counter with he value stored in either the associated Load or Hold register It may also serve as an automatic retrigger of the counter once the counter is loaded Command Register Bit Load Data Pointer Commands 61 4 Group Pointer E1 2 Element Pointer Originally Reserved Counter 1 Mode Register Counter 2 Mode Register Counter 3 Mode Register Counter 4 Mode Register Counter 5 Mode Register Counter 1 Aux Mode Origi
77. triggerable Pulse Generation Frequency Shift Keying Baud Rate Clock Waveform Analysis Interrupt Generation Pulse burst generation The user has total software control over key features Such as CTS9513 5 Chan 16 bit 50MHz Counter Timer EXTENDED FEATURES BACKWARDS COMPATIBLE The CTS9513 maintains full backwards compatibility with the AM9513 allowing continued use of your existing software drivers Data may be transferred in 8 or 16 bit increments All internal data paths in the CTS9513 are 16 bit All 9513 commands registers and modes are supported Timer commands are still 8 bit with extended features making use of previ ously unused commands DEVIATIONS FROM THE 9513 The primary hardware feature NOT implemented in the CTS9513 is the GATE1A GATE5A input lines shared with the upper 8 bit data bus lines due to their limited utility EXxTENDED I O Interrupt Outputs PQFP 100 Pkg only Five separate interrupt output lines are provided in the CTS9513 PQFP 100 package only driven by the terminal count pulse of each counter These lines may be programmed to assert a pulse or a latched level reset by software for use in a variety of proces sor and bus systems Timer Output Inhibit POFP 100 Pkg only In addition to the software programmable output inhibit or tri state command the CTS9513 PQFP 100 package only provides a hardware output inhibit signal which ov
78. unter 3 7 IRQEN Register 4 Signals 4 1 Output Connector Signal Description Table of Contents Table of Contents Introduction 1 Introduction 1 1 General Description The MF 604 multifunction I O card is designed for the need of connecting PC compatible computers to real world signals The MF 604 contains a 100 kHz throughput 12 bit A D converter with sample hold circuit four software selectable input ranges and 8 channel input multiplexer 4 independent 12 bit D A converters 8 bit digital input port and 8 bit digital output port 4 quadrature encoder inputs with single ended or differential interface and 5 timers counters The card is designed for standard data acquisition and control applications and optimized for use with Real Time Toolbox for MATLAB Because of the small size and low power consumption MF 604 can be used not only in desktop computers but also in portable computers and notebooks 1 2 Features List The MF 604 offers following features 10 us 12 bit A D converter with sample amp hold circuit 8 channel single ended fault protected input multiplexer Software selectable input ranges 10V 5V 0 10V 0 5V Internal clock amp voltage reference 4 D A converters with 12 bit resolution and 10V output range 4 quadrature encoder inputs with single ended or differential interface Software selectable digital input noise
79. uter Systems Inc 1235 Walt Whitman Road Melville NY 11747 516 271 0400 FAX 516 271 0405 24 BIT DUAL AXIS QUADRATURE COUNTER January 1998 PIN ASSIGNMENT TOP VIEW FEATURES 28 Pin Package 30 MHz count frequency in non quadrature mode 17MHz in X4 quadrature mode dai Dual 24 bit counters to support X and Y axes in YLCHTRIYLOL 1 i YRONTRIYABG motion control applications FCK 2 27 YFLG1 Dual 24 bit comparators VDD 5V 3 be 2 Digital filtering of the input guadrature clocks p s a Programmable 8 bit separate filter clock prescalers Ej YA for each axis bi 5 24 YB Error flags for noise exceeding filter band width D2 6 b3 Programmable Index Input and other programmable 1 7 bz Independent mode programmability for each axis p3 v Miet Programmable count modes 04 8 RI 21 XB Quadrature X1 X2 X4 Non quadrature ps 9 3 bo Normal Modulo N Range Limit Non Recycle ee pe 19 19 XLCNTR XLOL 8 bit 3 State data bus 1 18 XRCNTR XABG 5V operation VDD VSS vss GND 12 hz xv TTL CMOS compatible I Os Hel Ab 28 Pin SOIC 28 PDIP 300mil 600mil ep WR 14 15 cs LS7266R1 Registers LS7266R1 has a set of registers associated w
80. y 5 111110 Divide by 62 111111 Divide by 63 00100 Source 4 00101 Source 5 00110 Gate 1 00111 Gate 2 01000 Gate 3 01001 Gate 4 01010 Gate 5 01011 F1 01100 F2 01101 F3 01110 F4 01111 F5 10000 F6 10001 F7 10010 FOUT 2 10011 11111 Reserved Table 8 Master and Auxiliary Master Mode Register Definitions PRELIMINARY INFORMATION SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 1997 Celeritous Technical Services Corp 10 RevC November 97 Celeritous Technical Services Corp 806 783 0904 PO Box 65600 1200 FAX 806 783 0905 CTS9513 Lubbock Texas 79464 5600 http www celeritous com 5 Chan 16 bit 50 2 Counter Timer 2 15 C2 14 C2 13 C2 12 C2 11 C2 10 C29 C28 C2 7 C26 C2 5 C24 C23 C22 C24 C2 0 0 s Hours Hours 10 s Minutes Minutes BCD DATA 0 23 Hours BCD DATA 0 59 Minutes 1 15 C1 14 C1 13 C1 12 C1 10 19 C1 8 7 16 C15 C14 C12 C1 1 C1 0 10 s Seconds Seconds 10th Seconds Division Factor 5 6 10 BCD DATA 0 0 59 9 Seconds Table 9 CTS9513 Time of Day Data Format FOUT Enable Bit MM12 The FOUT output may be enabled or disabled and placed in a low impedance state to ground under software control Bus Width Bit MM13 When set this bit places the device into a 16 bit external data bus mode When clea
81. y shown here as modulo 1 UP x DOWN tai INDEXI Note 5 X1 CLOCK Note 6 X2 CLOCK Note 6 X4 CLOCK Note 6 4 tidx gt IDX Note 7 FIGURE 4 QUADRATURE CLOCK A B AND INDEX INPUT Note 5 Shown here is positive index with solid line depicting 1 4 cycle index and dotted line depicting 1 2 cycle index Either LCNTR LOL or RONTR ABG input can be used as the INDEX input Note 6 X1 X2 and X4 clocks are the final internal Up Down count clocks derived from filtered and decoded Quadrature Clock inputs A and B Note 7 IDX is the synchronized internal load OL or CNTR or reset CNTR signal based on LCNTR LOL or RCNTR ABG input being selected as the INDEX input respectively This signal is identical with FLAG register bit 6 UP 1 DOWN B X4 CLOCK Internal tae CNTR FFFFFD FFFFFE FFFFFF 0 1 2 3 2 1 0 FFFFFF FFFFFE dk BW sa t tas COMPARE 9 ik Note 8 CT FLAG B1 BT FLAG BO CPT FLAG B2 FIGURE 5 CARRY BORROW COMPARE CARRY TOGGLE BORROW TOGGLE AND COMPARE TOGGLE IN X4 QUADRATURE NORMAL BINARY COUNT MODE Note 8 COMPARE is generated when PR CNTR In this timing diagram it is arbitrarily assumed that PR 1 DOWN UP DOWN DIRECTION B 185 4 COUNT IN A 65 TS tGH GATE ABG COUNT DISABLE T44 COUNT ENABLE FIGURE 6 COUNT A DIRECT

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