TB-FMCH-12GSDI Hardware User Manual
Contents
1. M23554G Ex Xalarm Chi DIR Reclocker Cable Driver Chi SDI M23145G M23428G Xalarm TX Chl Xalarm TX Ch1 CS RCLKR CH CS DRVR N SPI MOSI SCLK MISO CH1 RF HDBNC LL CS RCVR CH Switch pae 7 52 42520 Equalizer Reclocker Ex Chi SDO p n Chi SDO p n M23554G Channel 1 Ex Xalarm _ Ex Ch2 DIR DIR Reclocker Cable Driver 2 SDI 2 SDI M23145G M23428G Ex Xalarm TX Ch2 Xalarm TX Ch2 CS RCLKR CH2 cs DRVR SPDT SPI MOSI SCLK MISO CH2 CS RCVR CH2 Switch Y 42520 Equalizer Reclocker Ex Ch2 SDO p n Ch2 SDO p n 4 M23554G Channel 2 Ex Xalarm RX Ch2 Xalarm RX Ch2 E Ex Ch3 DIR Ch3 DIR Bg Od Reclocker Cable Driver 2 M23145G M23428G a f Doc 55 Ex Kalam Cono qu TA in 5 5 CS CH3 A miso SPDT RF ot CS RCVR CH3 Switch na 2 amp 4 E PE42520 ity 01 1 Equalizer Reclocker 5 Ch3 SDO p n z Ch3_SDO_p n M23554G Channel 3 02 Xalarm RX iz Ch32. 1 00 Figure 4 1 TB FMCH 12GSDI Block ELECTRON DEVICE LIMITED Sync Separator LMH1981 9 Fin Vin Hin o aa SYNC IN INIT No_Ref No_Align No_Lock Fout1 Fout2 Fouts Video Fout4 Clock N Clkout1_p n Generator Clkout4 p n LMH1983 t 2 Repeater ace epeater PCA9517 PCA9517 lt VCXO 27 0MHz Extender 2 provided only Clkout2 p n for LMH1983 power down CIk0 Ck E out3 p n Crosspoint Switch MGT_Clk1 Osc 148 5MHz SCL Osc 148 35165MHz EM Note single ended GPIO signals A connected to the FMC are voltage MOSI CH 0 3 level shifted to VADJ SCLK CH 0 3 All high speed differential signals are SPI MISO SPI MISO AC coupled EX SPI SO SPI 50 SPI MISO CH 0 3 EX SPI 61 BRUST Multiplexers 5 RCLKR EX SPI CS1 Ej SN74LV4052A x3 CS DRVR 0 3 EX 52 SPI CS2 Cr 0 3 M SPI CS3 SPI CS3 CS RCVR CH 0 3 Diagram 10 TB FMCH 12GSDI Hardware User Manual 5 External View of the Board ET iiim in n ii a EE r 7 Ami MS i 1g Meer nente rhe LIT TI d y E He 7 LLLI P Yawa
3. 15 Usage Example An FPGA demonstration load is available on the inrevium website ELECTRON DEVICE LIMITED inreviun 16 Appendix 2 Contents The following table describes the contents of the EEPROM as programmed at the factory Table 16 1 2 EEPROM Contents NOT CURRENTLY AVAILABLE ELECTRON DEVICE LIMITED TOKYO ELECTRON DEVICE E m PLD Solution Dept PLD Division URL http solutions inrevium com E mail psd support 2teldevice co jp HEAD Quarter Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa Japan 221 0056 TEL 81 45 443 4016 FAX 81 45 443 4058 Rev 1 00 TOKYO ELECTRON DEVICE LIMITED 29
4. TB FMCH 12GSDI Hardware User Manual 1 00 Rev 1 00 TOKYO ELECTRON DEVICE LIMITED 1 Revision History Rev 1 00 2015 03 17 Initial release Rev 1 00 TOKYO ELECTRON DEVICE LIMITED 2 1 BFelaled Documents and AGG88S0rI6G8 7 Deci eee 7 J 8 jJ DOC PD U 9 o Me Board 11 6 12 7 Supplying Power to the 002 2200000 2 0 nennen nnne nsns naar nnns 13 B GO 210 9 12 eos mU I MM M E 13 8 1 HPC Connector to Main Board 13 8 2 Connector for the Extender TB FMCH 12GSDI 19 89 BBNGO COE IOS I 21 22 10 SPI uuu __ 23 Tis FPMO 20 EEPROM E 24 24 J 25 14 Test Points and LEDS a a 26 15 Usage 27 16 Appendix FMC 2 EEPROM 28 List of Figures Figure 3 1 HPC Connector Pin Layout from VITA 57 1
5. ni J ot del s s LI Bel H TT LIES n 2 Ao HORA iki BEN 3 ee cu EIN E ET 1 LE a LA L D yr eem TR i TA ud E Lm Figure 5 1 External View of TB FMCH 12GSDI Component Side dU TY ahea ada a Whe OS Et dm 1 NS a L p e a s a uu LLL EM M 1 c aS a e E T B o5 IN Ll ug M ft 4 4 Sh 10079 01 P vom T TIT E 4 i MIT 1 NL a a a LI es NEN 4 softs 2 5 dert T oer E won aa Blisa ul ILLI 8 2 41 y ie LELI LJ a eitis ne 685 seers XL une I ws Figur
6. 8 Figure 4 1 TB FMCH 12GSDI Block 9 10 Figure 5 1 External View of TB FMCH 12GSDI Component Side 11 Figure 5 2 External View of TB FMCH 12GSDI Solder Side 11 Figure 6 1 TB FMCH 12GSDI Board Dimensions 12 Figure 8 1 TB FMCH 12GSDI Front Edge HDBNC Coaxial Connectors 21 Figure 10 1 SPI Multiplexer 1 23 Figure 13 1 Video Clock Generation 25 Figure 14 1 Test Point and LED Locations HDBNC Connector 5 26 List of Tables Table 8 1 HPC Main Board Connector Pin Assignment 14 Table 8 2 Extender Board Connector Pin Assignment 19 Table 9 1 SDI Channel Major 22 Tae 23 Table 14 1 Test S 26 Table 16 1 126 EEPROM 28 1 00 ELECTRON DEVICE LIMITED 3 Introduction Thank you for purchasing the TB FMCH 12GSDI board Before using the product be sure to carefully read this user manual and fully understand how to corr
7. CS RCLKR CS RCLKR CH2 CS RCLKR CS DRVHR De CS DRVR CH2 DRVR SPI S0 ____5 _51 5 CS ae CS CH2 To From J10 FMC CS connector via voltage translators SN74LV4052A Dual 4 Channel Multiplexers MOSI CHO U17 SCLK CHO MISO CHO M23145G U18 M23428G Driver CS DRVR CHO M23554G Equalizer CS 501 Channel 0 Connections shown The other three channels are similar Figure 10 1 SPI Multiplexer Connections ELECTRON DEVICE LIMITED Rev 1 00 11 122 EEPROM EEPROM 24 02 is provided for FMC identification as described section 5 5 of 57 1 It is at 2 address 0b1010000x and is connected to the FMC dedicated pins at J10 C30 SCL and J10 C31 SDA The pull up resistors to 3V3 AUX are populated R163 and R164 The EEPROM is permanently enabled for writing The FMC identification EEPROM for the extender card is connected to J10 C22 LA18 CC P for SCL and J10 C23 LA18 N for SDA These signals are connected to J11 C30 SCL and J11 C31 SDA via a PCA9517 I2C bus repeater The FMC identification EEPROM is programmed at the factory to enable automated identification verification and configuration of Main Board parameters The contents of the EEPROM are displayed in Appendix A
8. 1 42520 G30 F CH1 DIR LA29 P In LVCMOS VADJ CTRL CH 2 PE42520 G33 F CH2 DIR LA31 P In LVCMOS VADJ CTRL CH 3 PE42520 C18 F CH3 DIR LA14 P In LVCMOS VADJ a Rev 1 00 TOKYO ELECTRON DEVICE LIMITED 10 m Schematic Signal VITA 57 1 Name Type Description Direction 016 F INIT LA12 N w LVCMOS VADJ LMH1983 INIT LUIS NIT F NO REF LAO2 P LVCMOS VADJ NO REF LMH1983 H8 F NO ALIGN LAO2 N Out LVCMOS VADJ NO ALIGN LMH1983 H10 F NO LOCK 04 P LVCMOS VADJ LOCK rama a s Noteomecies nowa ramo Ou nowa _ me Ou GN _ me Wacmemd n D omero mwm n mems ow Ou TAG Bypassed_ m Du Noteomecies m SS ue Noteomecies Ou _ _ 1 00 ELECTRON DEVICE LIMITED 10 EE FMC M Schematic Signal Name VITA 57 1 Name Description Pin Direction Extender SDI Differential Pairs SDI P DP4 C2M P In LVDS Channel 0 Output EX CHO SDI N DP4 C2M N EX CH1 SDI P DP5 C2M P In LVDS Channel 1 Output EX CH1 SDI N DP5 C2M N EX CH2 SDI P DP6 C2M P In LVDS Channel 2 Output EX 2 SDI DP6 C2M N EX CH3 SDI P D
9. is to enable SDI connectivity To accomplish this there are 5 HDBNC connectors SDI channel 0 consists of two HDBNC connectors 1 dedicated input and 1 dedicated output SDI channels 1 2 and 3 are each provisioned with a single HDBNC connector An SPDT switch located at each connector on channels 1 2 and 3 determines the desired functionality i e input or output The system block diagram at the beginning of this document depicts the key components that are present on each channel Table 9 1 SDI Channel Major Components Transmit System MACOM M23145G Multi Rate Digital Re Clocker MACOM M23428G Low Jitter Cable Driver SPDT RF Switch 9KHz to 13GHz 50 ohm Each device in the table above is programmable via Each RF switch direction is controlled by the signal CHx DIR 0 input to FMC 1 output from Although the switch is absorptive and offers good isolation it is recommended that any transmit circuitry be disabled when operating in receive mode Note Exceeding the maximum input level or connecting multiple outputs together can cause irreparable damage to the TB FMCH 12GSDI FMC Always confirm your Tx Rx switch configurations prior to enabling outputs or driving inputs Note All SDI inputs outputs are AC coupled Note Maximum input levels Peregrine Semiconductor PE42520 RF Switch Frequency dependent refer to PE42520 datasheet and remember to consider that this is a 50 ohm specifi
10. Note The user must be cognizant that the 122 EEPROM is always write enabled As it contains critical information required for correct operation one must never overwrite the factory settings 12 Sync Input The Sync input on the FB FMCH 12GSDI FMC allows the user to synchronize the FPGA FMC system to an external video system The Sync input on HDBNC 9 is first terminated with 75 ohms to ground and then coupled before entering the LMH1981 video sync separator The LMH1981 will accept a wide variety of video signals up to 1080p The odd even field horizontal and vertical sync outputs are connected to the carrier board connector The LMH1981 automatically detects the video format and accepts video signals up to 1 2Vpp Please see the LMH1981 data sheet for complete details on its operation Note Exceeding the maximum input level on the Sync input can cause irreparable damage to the TB FMCH 12GSDI FMC Do not exceed 1 2Vpp and OV DC 1 00 ELECTRON DEVICE LIMITED 24 13 Video Clock Generation Figure 13 1 shows the video clock generation circuit It basically consists of the LMH1983 video clock generator and the DS10CP154 crosspoint switch The LMH1983 is very versatile and can generate almost any required SDI video clocks The LMH1983 and the crosspoint switch are controlled an 126 bus Two oscillators feed the crosspoint switch to supply common video clock frequencies The L
11. Video Clocks CLKOUT1 CLKO M2C P LMH1983 Out LVDS CLKOUT4 CLKO M2C N CLKOUT1 CLK1 P LMH1983 Out LVDS F CLK1 M2C CLKOUT4 F CLKOUT2 GBTCLKO M2C P DS10CP154A Out LVDS F CLKOUT2 GBTCLKO M2C N OUTO F CLKOUT3 GBTCLK1 M2C P DS10CP154A Out LVDS F CLKOUT3 GBTCLK1 M2C N OUTI F FOUT LA12 P LVCMOS VADJ LMH1981 OEOUT F VOUT 08 LVCMOS VADJ LMH1981 VSOUT F HOUT LAO8 N LVCMOS VADJ LMH1981 HSOUT F FIN LA20 P LVCMOS LMH1983 FIN F VIN LA16 P LVCMOS LMH1983 VIN F HIN LA16 N L VCMOS VADJ LMH1983 HIN FOUT LAO3 P LVCMOS VADJ LMH1983 FOUT1 2 00 CC P LVCMOS VADJ LMH1983 FOUT2 N LVCMOS VADJ LMH1983 FOUT3 FOUT4 LAO3 N LVCMOS VADJ LMH1983 FOUT4 Control and Miscellaneous Signals CH 0 M23145G C10 F XALARM TX CHO LAO6 P Out LVCMOS VADJ CH 1 M23145G C11 F XALARM TX LA06_N Out LVCMOS xALARM CH 2 M23145G C14 F XALARM TX 2 LA10_P Out LVCMOS xALARM CH 3 M23145G C15 F XALARM TX CH3 LA10 Out LVCMOS VADJ 0 235540 16 F XALARM RX CHO 11 P Out LVCMOS VADJ CH 1 M23554G H17 XALARM 11 Out LVCMOS VADJ CH 2 M23554G H19 F XALARM 2 LA15 P Out LVCMOS VADJ 3 235540 20 F XALARM LA15 N Out LVCMOS VADJ
12. data rate up to 11 88 Gbps It also has a video sync input for a video sync separator chip All video signal connections are via 75 ohm HDBNC jacks A video clock generator can also produce common video timing signals from oscillators or from HVF sync signals from the host FPGA The TB FMCH 12GSDI uses Samtec s FMC HPC connector for connection with a platform board having High Pin Count connectors It is a single width air cooled FMC that is compatible with the ANSI VITA 57 1 FPGA Mezzanine Card FMC Standard A second FMC HPC connector allows a second TB FMCH 12GSDI to be stacked to double the number of SDI inputs and outputs Note Even if your target carrier card supports a single TB FMCH 12GSDI there is no guarantee that stacking will be supported typically due to limited gigabit transceiver connectivity If stacking is a critical feature for you please contact your sales representative to confirm operation prior to ordering stacking The TB FMCH 12GSDI supports SD HD 3G 6G 12G SDI rates to enable next generation UHDTV 4k 60fps video over a single coaxial cable 1 00 ELECTRON DEVICE LIMITED 7 inreviun 3 Features SDI Video Reclocker MACOM M23145G SDI Cable Driver MACOM M23428G SDI Cable Equalizer Reclocker MACOM M23554G FMC Main Connector Samtec ASP 134488 01 FMC Extender Connector Samtec ASP 134486 01 SDI Connectors Samtec HDBNC J P GN RA BH2 FPGA GPIO Signal Level 1 2V through 3 3V using voltage
13. sales personnel for repair If an unpleasant smell or smoking occurs disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately After verifying that there is no smoking contact our sales personnel for repair Do not disassemble repair or modify the product Otherwise a fire or electric shock may occur due to a short circuit or heat generation For inspection modification or repair contact our sales personnel Do not touch a cooling fan As a cooling fan rotates at high speed do not put your hand close to it Otherwise it may cause injury to persons Never touch a rotating cooling fan Do not place the product on unstable locations Otherwise it may drop or fall resulting in injury to persons or failure If the product is dropped or damaged do not use it as is Otherwise a fire or electric shock may occur Do not touch the product with a metallic object Otherwise a fire or electric shock may occur Do not place the product in dusty or humid locations or where water may splash Otherwise a fire or electric shock may occur Do not get the product wet or touch it with a wet hand Otherwise the product may break down or it may cause a fire smoking or electric shock Do not touch a connector on the product gold plated portion Otherwise the surface of a connector may be contaminated with sweat or skin oil resulting in contact failure of a con
14. 5165 2 AV J OUT3N 1 3 531BC000110DG OSC Figure 13 1 Video Clock Generation Circuit Rev 1 00 TOKYO ELECTRON DEVICE LIMITED 14 Test Points and LEDs There are 11 test points accessible on the side of the card on which the HDBNC connectors are mounted This includes four through hole ground test points and seven test point pads for voltage rails Table 14 1 lists all the test points and Figure 14 1 shows the locations of the test points Note that TP7 does not exist There are three LEDs on the side of the card on which the HDBNC connectors are mounted The LEDs are on the LMH1983 video clock generator status outputs D2 is on the NO REF output D3 is on the NO ALIGN output and D4 is on the NO LOCK output There are no LEDs for any voltage rail Table 14 1 Test Points T5 8 _____ FETED 5 Pa 77 x 14 SSSS 2 2 os we T 18 VR WHEELS eue 1 c L 5 er Y 5 in Ie a 3 did EE SU 1 E NA LE MEE 255 Be UE CO emit SS 4 amp 44 YN Figure 14 1 Test Point and LED Locations HDBNC Connector Side 1 00 ELECTRON DEVICE LIMITED 26
15. CMOS VADJ xALARM CH 1 M23554G 024 EX XALARM LA23 N Out LVCMOS VADJ xALARM CH 2 M23554G 026 EX XALARM CH2 LA26 P Out LVCMOS VADJ xALARM CH 3 M23554G 027 EX XALARM CH3 LA26 N Out LVCMOS VADJ xALARM CH 1 PE42520 G31 EX_CH1_DIR LA29 N In LVCMOS VADJ CTRL CH 2 PE42520 G34 EX_CH2_DIR LA31_N In LVCMOS VADJ CTRL CH 3 PE42520 C19 EX_CH3_DIR LA14 N LVCMOS VADJ ow weil Notcomnestes VREFBMIG Ou _ or Notcomnectes m _ Fi pGMec Ow Wa EXPRENT PRENLMeGN Ow m 00 Notcomnestes m os Waemems wo ms m msn m ue Notcomestes vosme of Notcomnectes vosme Ow 1 00 ELECTRON DEVICE LIMITED 8 2 Connector for the Extender TB FMCH 12GSDI The FMC connector High Pin Count connecting to the extender FMC uses Samtec ASP 134486 01 Table 8 2 shows the FMC extender connector pin assignment Table 8 2 HPC FMC Extender Board Connector Pin Assignment J11 FMC Schematic Signal Name VITA 57 1 Description Pin Direction SDI Differential Pairs EX CHO SDI P DPO C2M P In LVDS Channel 0 Output EX CHO SDI N DPO C2M N EX CH1 SDI P DP1 C2M P In LVDS Channel 1 Outp
16. M23145G xALARM Channel 3 C15 EX XALARM TX CH3 LA10 N Out LVCMOS M23145G xALARM Channel 0 H16 EX XALARM RX CHO LA11 P Out LVCMOS M23554G xALARM Channel 1 H17 XALARM LA11 N Out LVCMOS M23554G xALARM Channel 2 H19 EX XALARM RX CH2 LA15 P Out LVCMOS VADJ M23554G xALARM Channel 3 H20 EX XALARM RX CH3 LA15 N Out LVCMOS M23554G xALARM Channel 1 PE42520 G30 EX CH1 DIR LA29 P In LVCMOS CTRL Channel 2 PE42520 G33 EX CH2 DIR LA31 P In LVCMOS CTRL Channel 3 PE42520 C18 EX CH3 DIR LA14 P LVCMOS EN e Noteomecies vereme Ou or Neteomnecies m me Pri Ou me Netcomecies m o 00 w m 7 oomoo om Wacwemd m Du Noteomecies m Sid ue Noteomecies Ou Ou 1 00 ELECTRON DEVICE LIMITED inreviun 8 3 HDBNC Connectors The SDI connectors use Samtec coaxial High Density BNC HDBNC HDBNC J P GN RA BH2 connectors Figure 8 1 shows the positions and assignments for each front edge connector Figure 8 1 TB FMCH 12GSDI Front Edge HDBNC Coaxial Connectors 1 00 ELECTRON DEVICE LIMITED 9 501 Channels The main function of the TB FMCH 12GSDI
17. MH1983 FIN and VIN clocks can also be supplied from the LMH1981 sync separator through the FPGA so the SDI channels can be synchronized with an external video source G19 3 LA16 N HIN G18 4 LA16 P p VIN G21 SN74AVC4T245 5 LA20 P 9 FIN G16 6 LA12 gt INIT G9 37 LAO3 P 4 FOUTI G6 30 LAOO CC P 4 FOUT G7 SN74AVC8T245 22 LAO CC N 4 FOUT3 G10 17 LAO3 FOUT4 H10 11 LAO4 P lt 4 LOCK H8 12 LAO2 4 ALIGN H7 SN74AVC47T245 13 LAO2 P 44 lt REF H4 36 M2C P lt 55 CLKOUTI CLKO M2C N CLKOUT1 N G2 15 M2C P 4 CLKOUT4 N CLK1 M2C N is CLKOUTA 40 ulis 8 gt P C MP7711MK LAO7 p e SDA 7 14 PCA9517 9 34 27 0MHz LAO7 lt e SCL XOIN P t AV HPC HOST SDA 36 LMH1983 VIDEO 357LB31027M0000 CARRIER 37 CLOCK VCXO CONNECTOR J10 SCL lt GENERATOR D4 29 1 28 GBTCLKO M2C N N CLKOUT2 N B20 27 4 23 M2C N lt q OUT1 N IN1 N lt CLKOUT3 N 24 6 OUT2 P IN2 P a N C 23 7 148 5MHz AV OUT2N IN2 Ne p DS10CP154 531BC148M500 OSC CROSSPOINT SWITCH 22 9 4 P IN3 P t N C 21 10 148 3
18. P7 C2M P In LVDS Channel 3 Output EX CH3 SDI N DP7 C2M N EX CHO SDO P M2C P Out LVDS Channel 0 Input EX CHO SDO N DP4 M2C N EX CH1 SDO P DP5 M2C P Out LVDS Channel 1 Input EX 00 N DP5 M2C N EX 2 SDO P DP6 M2C P Out LVDS Channel 2 Input EX CH SDO DP6 M2C EX CH3 SDO P DP7 M2C P Out LVDS Channel 3 Input EX CH3 SDO N DP7 M2C N Extender SPI and 2 Signals LINE 7 NENE GNOME 11 73 Chip Select EX SPI 51 LA24 N LVCMOS VADJ for M23145G SPI Chip Select H28 EX SPI CS2 LA24 P In LVCMOS VADJ for M23428G SPI Chip Select H26 EX SPI CS3 LA21 N In LVCMOS VADJ for M23554G LVCMOS OD C26 2 SCL LA27 P In Control 2 Clock VADJ LVCMOS OD C27 2 SDA LA27 BI DIR Control 2 Data VADJ LVCMOS OD FMC ID EEPROM C22 EX SCL LA18 CC P In VADJ 2 Clock LVCMOS OD FMC ID EEPROM C23 EX SDA LA18 CC N BI DIR VADJ 2 Data 1 00 ELECTRON DEVICE LIMITED 10 EE FMC M Schematic Signal Name VITA 57 1 Name Description Pin Direction Extender Control and Miscellaneous Signals CH 0 M23145G G24 EX XALARM TX CHO LA22 P Out LVCMOS VADJ ALARM CH1 M23145G G25 EX XALARM TX LA22 N Out LVCMOS VADJ xALARM CH 2 M23145G G27 EX_XALARM_TX_CH2 LA25 P Out LVCMOS VADJ xALARM CH 3 M23145G G28 EX XALARM TX CH3 LA25 N Out LVCMOS VADJ xALARM CH 0 M23554G 023 EX XALARM RX CHO LA23 P Out LV
19. devices Tokyo Electron Device Limited assumes no responsibility or liability for 1 Erasure or corruption of data arising from use of this product 2 Any consequences or other abnormalities arising from use of this product or 3 Damage of this product not due to our responsibility or failure due to modification This product has been developed by assuming its use for research testing or evaluation It is not authorized for use in any system or application that requires high reliability Repair of this product is carried out by replacing it on chargeable basis not repairing the faulty devices However non chargeable replacement is offered for initial failure if such notification is received within two weeks after delivery of the product The specification of this product is subject to change without prior notice The product is subject to discontinuation without prior notice 1 00 ELECTRON DEVICE LIMITED 6 1 Related Documents and Accessories All documents relating to this board can be downloaded from the TED Support Web at address http ppg teldevice co jp eng index htm Board accessories HDBNC BNC Cable Belden 1694A 12cm x2 spacer set AS 2610 2 5 2625 2 B 2606 S1N x6 5 2610 4 2 Overview TB FMCH 12GSDI has dedicated SDI input a dedicated SDI output and three SDI channels that are either input or output Each SDI channel supports a
20. e 5 2 External View of TB FMCH 12GSDI Solder Side Rev 1 00 TOKYO ELECTRON DEVICE LIMITED 6 Board Specification The following shows the TB FMCH 12GSDI board physical specifications External Dimensions Number of Layers Board Thickness Material SDI Connectors FMC Main Connector FMC Extender Connector Figure 6 1 TB FMCH 12GSDI Board Dimensions mm Rev 1 00 84 00 mm long x 69 00 mm wide 16 layers 1 6 mm Megtron 6 Samtec HDBNC J P GN RA BH2 Samtec ASP 134488 01 Samtec ASP 134486 01 His pal _ d adio TI 1 L X Tut quum i d SE n m UM aes tai I di 84 00 ELECTRON DEVICE LIMITED 12 69 00 7 Supplying Power the Board The power structure of the TB FMCH 12GSDI is relatively simple The total power dissipation is under 5 watts There is one switching power regulator 562130 to produce 2 5 volts from the 12 rail 12 0 The MACOM ICs and the SPI multiplexers use only the 2 5 volt rail All the other ICs except for the voltage translators and the 2 repeaters use the 3 3 volt rail 3P3V The voltage translators and repeaters use the FMC VADJ voltage which can be range between 1 2 volts to 3 3 volts voltage
21. ectly use the product First read through this manual and then always keep it handy SAFETY PRECAUTIONS Observe the precautions listed below to prevent injuries to you or other personnel or damage to property e Before using the product read these safety precautions carefully to assure correct use e These precautions contain serious safety instructions that must be observed e After reading through this manual be sure to always keep it handy The following conventions are used to indicate the possibility of injury damage and classify precautions if the product is handled incorrectly Indicates the high possibility of serious injury or death if the product is handled Danger incorrectly Indicates the possibility of serious injury or death if the product is handled Warning incorrectly Indicates the possibility of injury or physical damage in connection with houses or Caution household goods if the product is handled incorrectly The following graphical symbols are used to indicate and classify precautions in this manual Examples Turn off the power switch Do not disassemble the product Do not attempt this 1 00 ELECTRON DEVICE LIMITED 4 TB FMCH 12GSDI Hardware User Manual inreviun ag Rev 1 00 A Warning In the event of a failure disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately and contact our
22. ed part operating in a 75 ohm system M23554G Adaptive Cable Equalizer 880mVpp Note The PE42520 is a 50 ohm switch Signal integrity assessments have confirmed that this part will work as required in this 75 ohm system Rev 1 00 TOKYO ELECTRON DEVICE LIMITED 22 10 Multiplexed SPI Busses MACOM devices M23145G M23428G 235540 are configured controlled four wire busses As there are 12 MACOM devices per TB FMCH 12GSDI there would be many FPGA pins required for just the SPI busses To reduce the number of FMC signal connections to something more desirable at the expense of complexity the busses are multiplexed Structurally each of the four SDI channels has a separate bus Table 10 1 shows the connections and signals for the SPI busses Three dual SN74LV4052 multiplexer chips are controlled with two signals 50 SPI 51 to select which of the four SPI busses is connected to the FPGA The maximum SPI bus clock frequency is 20MHz The following table show which SPI bus is active based on the state of the multiplexer selection signals and which chip select signal corresponds with which MACOM device Table 10 1 SPI Decoding Oo L9 74 4 4 __ _ 2 O MOSI CH1 MOSI CH2 MOSI CH3 SPI MOSI 50 SS T _ 1 SCLK CH1 SCLK CH2 SCLK MISO CH1 MISO CH2 MISO A SPI 51
23. is used only by the EEPROM and a single 2 repeater The current draw from the 12 voltage is less than 300 mA The current draw from the 3P3V rail is about 500 mA worst case There is no over current or over voltage protection on the 3P3V or 12 rails although both are LC filtered 8 Connectors There are a total of eight connectors on the FMC One HPC FMC connector is for the main board J10 and another HPC connector J11 is for a second TB FMCH 12GSDI to provide double the SDI channels if required The six HDBNC SDI channel connector are located in a row on the front edge of the card Note Only stack FMCs that are identical i e same part number and same revision Do not attempt to stack different FMCs Stacking FMCs of different types or revisions could cause damage 8 1 HPC FMC Connector to Main Board The FMC connector High Pin Count connecting to the main board uses Samtec ASP 134488 01 Table 8 1 shows the connector pin assignment In this table the C2M direction means carrier to mezzanine which is an input to the FMC The M2C direction means mezzanine to carrier which is an output from the FMC BI DIR means bi directional so the signal direction could be either an input or an output Pins not included in the table are unconnected including all HA 0 23 and HB 0 21 signals 1 00 ELECTRON DEVICE LIMITED 13 Table 8 1 Main Board C
24. level translators or AC coupling Video Sync Separator Texas Instruments LMH1981 Video Clock Generator Texas Instruments LMH1983 25 ad H G F D B a h co C2M GND 021 M2C P 2L 8 Ghd M2C N J c 4 CLK2 BIDIR P GND CLKO M COND wae N 3 aw ure e J S gt 1 Connector LPC Connector LPC Connector LPC Connector Figure 3 1 FMC HPC Connector Pin Layout from VITA 57 1 Rev 1 00 TOKYO ELECTRON DEVICE LIMITED 8 4 Block Diagram Figure 4 1 shows the TB FMCH 12GSDI block diagram The FMC HPC main connector is mounted on the component side of the board The FMC HPC extender connector is mounted coincident with the main connector on the opposite side of the board Voltage level translators are not shown in the block diagram Rev 1 00 TOKYO ELECTRON DEVICE LIMITED inreviun E Reclocker Cable Driver n 501 p n SDI p n 4231456 M23428G 7 T Xalarm TX Xalarm TX uA SDXHD ity TI Acs_DRVR_CHO CS RCLKR CHO CS RCVR SPI MOSI SCLK MISO CHO Equalizer Reclocker Ex 0 SDO p n SDO p n
25. nector or it may cause a malfunction fire or electric shock due to static electricity ELECTRON DEVICE LIMITED 5 Caution Do not use or place the product in the following locations e Humid and dusty locations Airless locations such as closet or bookshelf Locations which receive oily smoke or steam Locations exposed to direct sunlight Locations close to heating equipment Closed inside of a car where the temperature becomes high otatic prone locations Locations close to water or chemicals Otherwise a fire electric shock accident or deformation may occur due to a short circuit or heat generation B Disclaimer This product is an SDI interface for Xilinx FPGA evaluation boards Tokyo Electron Device Limited assumes no responsibility for any damages resulting from the use of this product for purposes other than those stated Even if the product is used properly Tokyo Electron Device Limited assumes no responsibility for any damages caused by 1 Earthquake thunder natural disaster or fire resulting from the use beyond our responsibility acts by a third party or other accidents the customer s willful or accidental misuse or use under other abnormal conditions 2 Secondary impact arising from use of this product or its unusable state business interruption or others 3 Use of this product against the instructions given in this manual 4 Malfunctions due to connection to other
26. onnector Pin Assignment J10 EE FMC M Schematic Signal Name VITA 57 1 Name l Type Description Pin Direction SDI Differential Pairs CHO SDI P DPO In LVDS Channel 0 Output CHO SDI N DPO C2M CH1 SDI P P In LVDS Channel 1 Output CH1 SDI N 1_ 2 CH2 SDI P DP2 C2M P In LVDS Channel 2 Output CH2 SDI N DP2 C2M N CH3 SDI P DP3 C2M P In LVDS Channel 3 Output CH3 SDI N DP3 C2M N CHO SDO P DPO M2C P Out LVDS Channel 0 Input CHO SDO N DPO M2C N CH1 SDO P DP1 M2C P Out LVDS Channel 1 Input CH1 DP1 M2C N CH2 SDO P DP2 M2C P Out LVDS Channel 2 Input CH2 SDO DP2 M2C N CH3 SDO P DP3 M2C P Out LVDS Channel 3 Input CH3 SDO N DP3 M2C N SPI and 2 Signals i SPI Mux Selecto rss T masma sr SPI Chip Select D15 F SPI CS1 LAO9 N LVCMOS for M23145G SPI Chip Select D14 F SPI CS2 LAO9 In LVCMOS for M23428G SPI Chip Select D12 F SPI 53 LAO5 In LVCMOS for M23554G LVCMOS OD H13 F SCL LAO7 P In Control I2C Clock VADJ LVCMOS OD H14 F CTL I2C SDA LAO7 N BI DIR Control I2C Data VADJ FMC ID EEPROM C30 none SCL In LVCMOS 2 Clock FMC ID EEPROM C31 none SDA BI DIR LVCMOS mm vemos 2 Data 1 00 ELECTRON DEVICE LIMITED 10 EE FMC M Schematic Signal Name VITA 57 1 Name Description Pin Direction
27. ut EX CH1 SDI N DP1 C2M EX CH2 SDI P DP2 C2M P In LVDS Channel 2 Output EX CH2 SDI N DP2 C2M EX CH3 SDI P DP3 C2M P In LVDS Channel 3 Output EX CH3 SDI N DP3 C2M N EX CHO SDO P DPO M2C P Out LVDS Channel 0 Input EX CHO SDO N DPO M2C N EX CH1 SDO P M2C P Out LVDS Channel 1 Input EX CH1 SDO N M2C EX 2 SDO P DP2 M2C P Out LVDS Channel 2 Input EX CH SDO DP2 M2C EX CH3 SDO P DP3 M2C P Out LVDS Channel 3 Input EX CH3 SDO N DP3 M2C N SPI and 2 Signals on exserso i IVMOSQVAD SPI Mux Selecto HELME A mr Us SPI Chip Select for D15 EX SPI CS1 LAO9 N LVCMOS VADJ M23145G SPI Chip Select for D14 EX SPI CS2 09 LVCMOS VADJ M23428G SPI Chip Select for D12 EX SPI CS3 LAO5 N LVCMOS VADJ M23554G H13 CTL SCL LAO7 P LVCMOS OD Control I2C Clock 2 SDA LAO7 N BIDIR LVCMOS OD V Control I2C Data FMC ID EEPROM EX 2 SCL LVCMOS 2 Clock FMC ID EEPROM C31 EX 2 SDA SDA BI DIR LVCMOS 2 Data Rev 1 00 TOKYO ELECTRON DEVICE LIMITED 11 Schematic Signal Name VITA 57 1 Name BAN Type Description Pin Direction Control and Miscellaneous Signals Channel 0 C10 EX XALARM TX CHO LAO6 Out LVCMOS M23145G xALARM Channel 1 C11 EX XALARM TX 1 LAO6 Out LVCMOS M23145G xALARM Channel 2 C14 EX XALARM TX CH2 LA10 P Out LVCMOS
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