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AXM-A75 User`s Manual

1. GROUND SHIELD ON CABLE CONNECTS TO P1 amp P2 SHIELDED BACKSHELL P2 PI EH H gt E i H gt i cH jH 2 METERS gt P2 78 72 INCHES 4 0 0 0 INCHES P1 z ON f 55 Da 7 N Ay a PIN PIN34 PIN 68 PIN 34 33 68 n ge 33 C 53 PIN1 PIN 35 ER PIN1 a PIN35 FRONT VIEW U gt MODEL 5028 420 ULTRA SCSI VHDCI TO SCHEMATIC SCSI 3 68 PIN CABLE ASSEMBLY SHIELDED 4502 153A JI 1 2 3 4 5 6 7 8 9 101112 13 1415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 5960 61 62 63 64 65 66 67 68 TB1 1 23 4 5 6 7 8 9 10111213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
2. MODEL 5025 288 TERMINATION PANEL SCHEMATIC cita ARE TIED TO J1 METAL HOUSING A PIN 68 o Ji E H H TB2 12 3 40 86 36 PLACE MODEL SERIAL TBI LABEL HERE 0000900000900 000060000000000000000 E 00000000000000000000000000000090 Y L m SIDE VIEW lt 180 34 TOP VIEW NOTE 1 23 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 DIMENSIONS ARE IN INCHES emo on 1d a MILLIMETERS 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 gt TERMINATION 27 Y DODO DD ODO DO ODO ODO ODO DDD DO ODO MARKINGS 68 58 FRONT VIEW 4501 920 32 AXM A75 User s Manual Multifunction I O Mezzanine Board 33
3. Designed to comply with IEC61000 4 3 class A Surge IMMUNItY Not required for signal I O per European Norm EN61000 6 1 Electric Fast Transient IMmunity Designed to comply with IEC61000 4 4 class A Radiated Emissions Designed to comply with CISPR 16 2 3 class A Electrostatic Discharge Designed to comply with IEC6100 4 2 Level 2 Conducted Radio Frequency Interference Designed to comply with IEC6100 4 6 class A 26 AXM A75 User s Manual Multifunction I O Mezzanine Board Power Requirements 3 3 Volts 15 39 MA typical 50 mA maximum 5 Volts 15 54 mA typical 65 mA maximum IN O 103 mA typical 115 mA maximum 12V 15 92 MA typical 115 mA maximum ANALOG INPUTS AS tia ADI AD7686 Input Channels 16 differential Input Signal Type Voltage Non isolated Input Ranges 10 24 5 12 2 56 and 1 28 V Input Overvoltage Protection 31V with power on 19 V with power off Input Resistance 5 300 GQ typical differential Input Bias Current s es 5 nA typical 40 nA maximum Common Mode Rejection Ratio 98 dB typical 60 Hz Input Channel to Input Channel Rejection Ratio 41 dB typical 100 kHz Output Channel to Input Channel Rejection Ratio 85 dB typical 1 kHz ACCUFACV ici Gain Full Scale 25 C Full Scale O 70 C 1 0 011 0 026 2 0 013 0 029 4 0 015
4. ADC3offset 8228 822C ADcadata 8237 8238 ADC4offset 8238 823C __ ADC5data 8240 8247 8244 8248 ADCSoffst_ 8248 824C __ ADC6data 8250 8257 ADC6gaimcorrection 8254 8258 ADC6offset 8258 825C __ ADCIAAta 8260 8267 8264 8268_ ADC7Offset_ 8268 826C 8273 ADc8data 8270 8277 8274 8278 ADc8offset 8278 827F 827C 8283 ADCIdata 8280 8287 8284 8288_ ADCSOffset_ 8288 828F 828C PAC data 8290 10 AXM A75 User s Manual Multifunction I O Mezzanine Board PCIBar2 PCIBar2 Hex D31 D16 D15 DOO Hex 8297 ADC 10 gain correction 8294 ADC 10 offset 8298 829C ADC 11 data 82A0 8247 82A4 82AB ADCitoffset_ 8208 82AC 883 ADci2data 8280 8287 8284 82BB8 ADCI2Offset 8288 828F 82BC 82c3_ ADci3data 82C0 82C7 8204 82cB ADci3offset 82c8 82CF 82CC __ ADciIAdta 8200 82D7 82D4 8208_ ADCI4Offset 8208 82DC __ ADciSdaa 82E7 828 gt ADCISOfiset 8268 82EC __ ADCi6data 82F7 ADC 16 gain correction 82FB 3535 ADCIGOffset 82F8 82FC DAC 1 data 8300 829B DAC 1 fine gain 8308 DAC 1 offset 830C 8310 DAC 2 coarse gain 8314 DAC 2 fine gain 8318 DAC 2 DAC 3 coarse gain 11 AXM A75 User s Manual Multifunction I O Mezzanine Board PCIBar2 PCIBar2 DAC 3 fine DAC 3 DACAdata DAC 4 coarse 8337 gain DAC 4 fine DAC 4 Dac5data 8340 DAC 5 coarse 8347 gain
5. 0 033 8 0 018 0 040 Programmable Gain Instrumentation Amplifier Device ante ADI AD8251 PGA Linearity Error 0 005 maximum 3 27 LSB Offset Error RUM lasci 1 0 mV typical 2 5 mV maximum Offset vs Temperature 0 6 1 5 G uV C typical G 1 2 4 8 1 2 5 G uV C maximum Gain Error all gains 0 01 typical 0 1 maximum 1 Input channel to input channel rejection ratio was measured with a 100 KHz 1V pk pk sine wave input on an adjacent channel The output channel to input channel rejection ratio was measured with all output channels driving a 10k ohm load outputting a 1 kHz 20 V pk pk sine wave Load resistors were located on a termination panel connected to a 2 meter cable 27 AXM A75 User s Manual Multifunction I O Mezzanine Board Gain vs Temperature 3 ppm C typical 10 pm C maximum Difference Amplifier DEVICE iii TI INA159 Gain Errori raga 0 005 typical 0 024 maximum Gain Error vs Temperature 1 ppm C typical Offset Error 100 uV typical 500 uV maximum Offset Voltage vs Temperature 1 5 uV C typical Reference Divider Accuracy 0 002 typical 0 024 maximum Voltage Reference REF3240 DEVICE TI REF3240 ACCUFACY A na 0 01 typical 0 2 maximum Output Voltage Temperature Drift 4 ppm C typical 7 ppm C maximum Thermal HysteresiS 100 p
6. 8344 DAC 5 fine DAC 5 DAC6data DAC 6coarse 8357 gain DAC 6 fine DAC 6 Dac7data 8360 DAC 7 coarse 8367 gain 8364 DAC 7 fine DAC 7 8373 DAC8dataregister 8370 DAC 8 coarse 8377 gain 8374 DAC 8 fine 837B gain 8378 DAC 8 837F offset 837C 8383 8380 y Reserved for base PMC Module y 1FFFFF 1FFFFC 12 AXM A75 User s Manual Multifunction I O Mezzanine Board FLASH Data Format Factory calibration constants are stored in FLASH memory The FLASH memory device is a Numonyx M25P10 Error Reference source not ound shows the memory map of the FLASH contents All numeric constants are 32 bit values stored in little endian byte order Table 3 2 FLASH Memory Map Addr D31 D16 D15 Doo Addr 0007 FLASH ID AXM A75 null terminated 0000 character string 000B 10 24 Volt Range Channel 1 Offset 0008 10 24 Volt Range Channel 2 Offset 000C 0013 10 24 Volt Range Channel 3 Offset 0010 0047 0044 0048 0048 004C 0087 0084 0088 0088 008F 008c 0090 00C7 00c4 00CB ooc8 00CF 00cc 00D0 0107 0104 0108 0108 010F 010C 0113 0110 0147 0144 0148 0148 014F 014C 0153 0150 13 AXM A75 User s Manual Multifunction I O Mezzanine Board 0188 018F 0193 01C7 01C4 01CB 01C8 01CF o1cc 01D3 01D0 0207 0208 0208 020C 0213 0210 0227 0247 0248 0248 024C 0267 DAC Gain Channel 8 Board Status and Reset Register Read Write PCIBar2 8000H This read
7. e a A BE A A aie de aa 27 ANALOGINPUTS o abs 27 Programmable Gain Instrumentation Amplifier i 27 Difference Ampli nei ai ari 28 Voltage Reference REF3240 i 28 Analogito DigitalConverteri iia rare o andai co rear 28 ANALOG OUTPUTS 0 A RARE Iain 29 Digital to Analog Converter iii 29 APRENDO Diada at Ad aa 30 CABLE MODEL 5028 420 Ultra SCSI VHDCI male to SCSI 3 male Round Shielded 30 TERMINATION PANEL MODEL 5025 288 31 DRAWINGS ASE A ae 32 AXM A75 User s Manual Multifunction I O Mezzanine Board The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involve
8. fine gain correction and offset correction The data register is a 16 bit write read register Reading this register will retrieve the last value that was loaded into the DAC 19 AXM A75 User s Manual Multifunction I O Mezzanine Board register for that channel Each of the D A channels will apply a gain and offset correction to each output word The addition and multiplication operations are done in each DAC device The gain and offset registers are set to one and zero respectively upon reset to pass uncorrected DAC values to the outputs Typical start up operation would include reading factory calibration constants from AXM A75 on board FLASH memory and writing the appropriate correction values for the currently selected full scale range to the coarse gain fine gain and offset registers for each channel 20 AXM A75 User s Manual DAC Data Register DAC Coarse Gain Register DAC Fine Gain Register Multifunction I O Mezzanine Board The DAC data format is 16 bit offset binary The ideal output from the DAC for some select output codes is shown in Table 3 13 The full scale range FSR is controlled by the coarse gain selection register for each channel See Table 3 4 The FSR choices are 10 10 2564 and 10 5263 Volts Table 3 13 DAC Data Format DIGITAL OUTPUT FFFF 8001 8000 7FFF 0000 The coarse gain register is a two bit register that allows the selection of one of three Full Scale Ranges 10 10 256
9. 4 and 10 5263 Volts as shown in Table 3 14 There is a separate coarse gain register for each channel Table 3 14 DAC Coarse Gain Selections FSR Volts Register Value a 10 2568 10 5265 The fine gain register is a six bit register that allows the user to adjust the gain of each DAC by 32 LSBs to 31 LSBs in 1 LSB steps as shown in Table 3 15 Table 3 15 DAC Fine Gain Selections 21 AXM A75 User s Manual DAC Offset Register Updating DAC outputs Multifunction I O Mezzanine Board The offset register is an eight bit register that allows the user to adjust the offset of each DAC by 16 LSBs to 15 875 LSBs in steps of one eighth LSB as shown in Table 3 16 Table 3 16 DAC Offset Correction om ors OF OFA OFS OFZ OFT OF CS EEE ss Joa aaa prpo Nosdwsment of o ofo o ofoo EACH AA AA CR CR A A A E EE asas fajo psss jajo Note the LDAC bit in the control register must be written to trigger a transfer from the DAC data registers to the DAC offset register The values written to the DAC data registers are not immediately applied to the DAC outputs The LDAC bit in the control register must be written to trigger a transfer from the DAC data registers to the DAC outputs see Table 3 4 The transfer from the data register to DAC outputs occurs simultaneously for all DAC channels 22 AXM A75 User s Manual 4 0 THEORY OF OPERATION Field I O Connections The field I O interface to the A
10. Acromag kd THE LEADER IN INDUSTRIAL 1 0 AXM A75 Multifunction I O Mezzanine Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 0310 Fax 248 624 9234 Copyright 2013 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 927 A13A000 AXM A75 User s Manual Multifunction I O Mezzanine Board 1 0 2 0 3 0 4 0 GENERAL INFORMATION cos oes seks E aides A dt 5 KEY FEATURES os 5 ENGINEERING DESIGN KIT 3A AT E AEA EAER AASEN EAE SATE EEEE 6 BOARD CONTROL SOFPTWARE sess lE aii 6 PREPARA TION FOR USE Cuit E OA alate 6 UNPACKING AND INSPECTION lee cene ce ce cc 6 CARD CAGE CONSIDERATIONS 3 3 iii a e iniettate 6 Front Panel Field I O Connector J1 nono nono nnnnanno nn nc nn cnnnnnnonn nn nana cnnannnn nes 8 Analog Inputs Noise and Grounding ConsiderationS 9 None Isolation Considerations a inerenti 9 PROGRAMMING INFORMATION 9 AXM A75 Memoryv Map accasa a A A a A a irrita 9 FLASH Data Format ie E E i ai ian 13 Board Status and Reset Register Read Write PCIBar2 8000H i 14 Control Register Read Write PCIBar2 8100H 15 Status Register O Read Write PCIBar2 8104H 15 Status Register 1 Read Write PCIBar2 8108H i 16 Digital I O Read Wri
11. EI Dia 3 oo 37 os 4 oe 38 io 5 p 39 Dios 6 oo 4 bio 8 Dos 4 Don 9 Dios 4 vino 26 vns 60 via 32 vns 66 vini 34 vne 6_ The sixteen differential analog input channels are labeled VINx and VINx where x is the channel number 1 to 16 Analog outputs are labeled VOUTx where x is the channel number 1 to 8 Digital input output signals are labeled DIOx where x is bit 0 to 15 Signal returns are labeled GND AXM A75 User s Manual Multifunction I O Mezzanine Board Analog Inputs Noise and Grounding Considerations Non Isolation Considerations Differential inputs require two leads and per channel and provide rejection of common mode voltages This allows the desired signal to be accurately measured However the signal being measured cannot be floating It must be referenced to analog common on the AXM module and be within the normal input voltage range Shielded cable of the shortest length possible is strongly recommended The board is non isolated since there is electrical continuity between the logic and field I O grounds As such the field I O connections are not isolated from the system Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections 3 0 PROGRAMMING INFORMATION AXM A75 Memory Map This Section provides the specific information necessa
12. SB maximum Bipolar Zero Error 2 mV maximum Internal Reference 4 995 V minimum 5 005 V maximum Short Circuit Current 10 MA typical Load Current 1 mA maximum for specified performance Capacitive Load Stability 200 pF maximum with Rioap 1000 pF maximum with Rroap 10K Q DC Output Impedance 0 3 Q maximum Gain Dri inicias 2 ppm full scale range C Bipolar Zero Drift 2 ppm full scale range C AcCUr Vainas i 0 015 full scale 25 C 0 029 full scale 0 70 C 29 AXM A75 User s Manual Multifunction I O Mezzanine Board 7 0 APPENDIX CABLE MODEL 5028 420 Ultra SCSI VHDCI male to SCSI 3 male Round Shielded Type Round shielded cable 34 wire pairs Ultra SCSI VHDCI male and SCSI 3 male connectors The cable length is 2 meters 6 56 feet This shielded cable is recommended for all I O applications both digital I O and precision analog I O Application Used to connect Model 5025 288 termination panel to the board Length 2 meters 6 56 feet Cable 34 wire pairs 28 AWG foil braided shield inside a PVC jacket Connectors Ultra SCSI VHDCI and SCSI 3 68 pin male connectors with backshell Keying The connectors have a D Shell Schematic and Physical Attributes See Drawing 4502 153 Electrical Specifications 30 VAC per UL and CSA SCSI 3 connec
13. XM A75 is provided through connector P1 refer to Table 2 1 Field I O signals are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops see Section 2 0 for connection recommendations Ignoring this effect may cause operation errors and with extreme abuse possible circuit damage Multifunction I O Mezzanine Board FIELD 1 0 P1 tk Y o 16 28 bit o 16 o Digital I O o e I il CONVERTI AN y 16 bit SCLK1 A D A2D_DATA1 i e 16 channels o CONVERT16 Anas 16 bit SCL eda o _ __ _ __ A D A2D_DATA16 AOUT1 AOUT2 16 bit e AOUT4 D2A_DATA1 D A e AQUIS 16 bit lo SCK2 AOUT7 Quad AOUT8 D A 4 D2A_DATA2 gt TO FPGA Figure 1 AXM A75 Block Diagram 23 AXM A75 User s Manual Digital I O Multifunction I O Mezzanine Board A block diagram of a single digital I O channel is shown in Figure 2 Digital I O This structure is replicated 16 times on the AXM A75 The signal DIG_OUT_STROBE is activated upon a write to the Digital I O register The level of DIG_IO_n is returned upon a read of the Digital I O register The signal DIG_OUT_DIR_STROBE is activated upon a write to the Digital I O Direction Register When the DIG_OUT_DIR_n signal is logic high the contents of the DIG_OUT_n flip flop will be driven onto the DIG_IO_n si
14. d It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility AXM A75 User s Manual Multifunction I O Mezzanine Board 1 0 GENERAL INFORMATION The AXM A75 is a high speed analog input output mezzanine board compatible with Acromag s line of re configurable PMC and XMC FPGA modules The AXM A75 has 16 differential analog inputs 8 analog outputs and 16 digital inputs outputs KEY FEATURES High Speed Analog Input sixteen independent 16 bit Analog to Digital Converter ADC channels provide simultaneous sampling at a maximum rate of 500 KHz The digitized output of each ADC is simultaneously input to the Field Programmable Gate Array FPGA for data collection and processing Programmable Input Voltage Range four gain selections are available that allow a bipolar input voltage range from 1 28 Volts to 10 24 Volts Analog Output eight 16 bit Digital to Analog Converter DAC channels provide simultaneous update with a maximum rate of 100 KHz Programmable Output Voltage Range three gain selections are available that allow a bipolar output voltage range from 10 Volts to 10 5263 Volts Calibration Constants factory calibration constants used to correct gain and offset errors are stored in on board FLASH memory Correction constants are stored for each channel and gain selection combination Gain and offset corr
15. ddress returns the data read from a previous write read serial transfer WARNING Factory calibration data is stored in FLASH Writing to FLASH could result in loss of factory calibration data See Error eference source not found Table 3 9 FLASH Data Register 8114H FUNCTION 8 FLASH data Digital I O Direction Register Read Write PCIBar2 8118H The Digital I O Direction provides an output enable for each of the 16 digital I O lines Write a 1 to a bit to enable the output Table 3 10 Digital I O 8118CH FUNCTION 31 16 me Pes I O Direction 15 0 ADC Channels There are three registers associated with each of the sixteen ADC channels data gain correction and offset correction The data register is a 16 bit read only register Reading this register will retrieve the oldest value from the FIFO associated with that channel Each of the ADC channels will apply a gain and offset correction to each sample prior to writing the result to a FIFO The addition and multiplication operations are done in FPGA hardware using one of the FPGA s DSP blocks for each channel The gain and offset registers are set to one and zero respectively upon reset to pass uncorrected ADC values to the FIFOs Typical start up operation would include reading factory calibration constants from AXM A75 on board FLASH memory and writing the appropriate correction values for the currently selected full scale range to the gain and offset
16. ducts sold separately facilitate the product interface in the following operating systems Windows DLL VxWorks and Linux Refer to the PMC XMC base board s manual for further information 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Y CAUTION SENSITIVE ELECTRON DEVICES DD MIT site On STORE NEAR ETADAD CARD CAGE CONSIDERATIONS Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment It is recommended that the board be visually inspected for evidence of mishandling prior to applying power The board utilizes static sensitive components and should only be handled at a static safe workstation Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommoda
17. ection are supported for both analog input and analog output General Purpose Digital Input or Output sixteen general purpose I O signals are provided The outputs are pulled high via pull up resistors Example Design the example VHDL design provided in the base board EDK provides the following features e Control of ADC sample rate and gain selection e Gain and offset error correction is applied in FPGA hardware for analog inputs and on chip for analog outputs e Each ADC channel includes a FIFO capable of storing 2050 samples e All enabled ADC channels are sampled simultaneously ADC sample rate can range from 1 34 Hz to 500 KHz e Control of DAC gain selection AXM A75 User s Manual ENGINEERING DESIGN KIT BOARD CONTROL SOFTWARE Multifunction I O Mezzanine Board Analog Input FIFO Status Interrupts Interrupts can be generated when an input channel s FIFO half full condition is reached or when a FIFO overflow occurs Acromag does not provide an engineering design kit specifically for the AXM A75 module However an example design is included in the Engineering Design Kit of the PMC XMC base board Refer to the PMC XMC base board s manual for further information on the available Engineering Design Kit Acromag does not provide board control software specifically for the AXM A75 series board However the AXM A75 module can be accessed via the control software for the base PMC or XMC module These pro
18. gnal The level translator is a NXP GTL2010 FPGA on XMC PMC DB_OUT n DIG_OUT_STROBE CLK_125MHZ DB_OUT_n DIG_OUT_DIR_STROBE CLK_125MHZ Analog Outputs Analog Inputs Bi 4 75K DIG OUT n directional DIG_IO_n Level Translator DIG_OUT_DIR_n Figure 2 Digital I O Two Analog Devices AD5764R quad bipolar voltage output DACs are used to provide the eight analog output channels Each DAC uses its own on chip reference as its reference source Although each DAC has separate clock sync load and serial I O signals connected to the FPGA the firmware as delivered with the EDK provides access to only a single quad DAC at a time The CLR BIN2SCOMP and RESET signals are common to both DACS Each of the analog input channels consists of a differential low pass filter followed by an instrumentation amplifier a difference amplifier and an ADC 24 AXM A75 User s Manual Multifunction I O Mezzanine Board The differential low pass RC filter is intended to reduce RF interference The 3db cutoff frequency of the filter is 421 kHz differential 8 84 MHz common mode An Analog Devices AD8251 Programmable Gain Instrumentation Amplifier PGA takes as input the channel s and inputs and outputs a single ended voltage proportional to it The gain can be 1 2 4 or 8 and is selected through the gain selection bits in the control register The gain selection affects all channels The output from the PGA is input to a Te
19. pm first cycle 25 ppm additional cycles NOISE cio 78 UV RMS typical AD Conin ai ADI AD7686 A D Resolution 16 bits Data Format ui straight binary No Missing Codes no missing codes 15 bits A D Integral Linearity Error 0 6 LSB typical 2 LSB maximum Offset ENOR cirpas e iae 0 1 mV typical 10 V range 1 6 mV maximum Gain Error Temperature Drift 0 3 ppm C typical Offset Temperature Drift 0 3 ppm C typical Full Scale Error 0 5 maximum A D Conversion Time 2 uS maximum Conversion Rate 500 kHz maximum Input NOISE 2 LSB rms typical 3 ai a dui Software calibration eliminates these error components i Acromag does not temperature cycle this product before shipping to customers If the product is operated at the extremes of its temperature range the voltage reference could drift by the amount specified for first cycle 28 AXM A75 User s Manual Multifunction I O Mezzanine Board ANALOG OUTPUTS Digital to Analog Converter DEVICE ia ADI AD5764RB Resolution ia 16 bits Output Ranges 10 10 2564 and 10 5263 V Settling TIME ii 8 uS typical full scale step to 1 LSB 10 uS maximum Slew Rate in 5 V usS typical Integral Nonlinearity 2 LSB maximum Differential Nonlinearity 1 L
20. range 5 12 Volts 10 Gain 4 full scale input range 2 56 Volts 11 Gain 8 full scale input range 1 28 Volts FLASH Select This bit is connected directly to the select input of the serial FLASH device LDAC transfer DAC data from data registers to output registers all channels write only read zero CLR clear DAC data registers to 0x00 all channels write only read zero 24 16 15 0 Convert channel 16 1 each channel can be individually controlled O channel stopped 1 enable continuous conversion Status Register 0 Read Write PCIBar2 8104H Status Register 0 provides access to the FIFO overflow and half full status bits for each channel Table 3 5 Status Register 0 8104H BIT FUNCTION 15 AXM A75 User s Manual Multifunction I O Mezzanine Board BIT FUNCTION FIFO overflow interrupt pending clear channel 16 1 A 1 indicates that at least one A D sample was lost due to an attempted write to a full FIFO Write a 1 to clear the bit FIFO half full interrupt pending channel 16 1 A 1 indicates that there are at least 1024 samples in the FIFO Status Register 1 Read Write PCIBar2 8108H Status Register 1 provides access to the FIFO empty status bits for each channel Table 3 6 Status Register 1 8108H BIT FUNCTION 31 16 15 0 FIFO empty channel 16 1 A 1 indicates that the FIFO is empty Digital I O Read Wri
21. registers for each channel ADC Data Format The output from the ADC is offset binary format as shown in Table 3 11 The full scale range 10 24 5 12 2 56 1 28 is controlled by the gain selection in the control register See Table 3 4 17 AXM A75 User s Manual Multifunction I O Mezzanine Board Table 3 11 ADC Data Format DESCRIPTION DIGITAL OUTPUT Full Scale FFFF Midscale zero 8000 1 LSB Below Midscale 7FFF Full Scale 0000 ADC Offset Register The offset register contains a 16 bit two s complement value that is added to the value output from the ADC to correct offset errors There is a separate offset register for each channel ADC Gain Register The gain register is a 17 bit fixed point positive fractional number ranging from 0 to 1 999984 weighted as shown in Table 3 12 The 17 bit fixed point number is least significant bit justified in a 32 bit register This number is multiplied by the offset corrected ADC value to correct for gain errors There is a separate gain register for each channel Table 3 12 Gain Register Number Format 16 15 ia E E Ti 10 7 Uncalibrated ADC Performance The uncalibrated analog input channel performance is affected by four error sources These are the instrumentation amplifier difference amplifier ADC reference and the ADC Each of these 18 AXM A75 User s Manual Multifunction I O Mezzanine Board devices can contribute to the offset and gain e
22. rror of the system These errors can be corrected by calibration Analog Input Channel Calibration Procedure Accurate calibration of the analog input channel digitized values can be accomplished by applying external precision calibration voltages The calibration voltages are used to find two points that determine the straight line characteristic of the analog channel Factory calibration constants are calculated using the following equations Gain 1 2 40r 8 FullScaleR ullScaleRange ui 10 24 IdealZero Gain 216 IdealSl Zn i FullScaleRange CountCALHI CountCALLO VoltsCALHI VoltsCALLO ActualIntercept CountCALHI ActualSlope VoltsCALHI ActualSlope Offset IdealZero AcualSlope ActualIntercept IdealSlope ActualSlope Of fsetCorrection Offset CorrectionFactor GainCorrection CorrectionFactor 2 The values calculated for OffsetCorrection and GainCorrection are stored in FLASH memory for each gain selection for each ADC channel The values are then used in the following equation to correct each input sample for offset and gain errors CountIN Of fsetCorrection GainCorrection CorrectedData 216 Note The average of many ADC values e g 2048 should be used when calculating new correction coefficients to reduce the measurement uncertainty DAC Channels There are four registers associated with each of the eight ADC channels data coarse gain correction
23. ry to program and operate the mezzanine board This mezzanine board is intended only for use on specific Acromag PMC XMC FPGA modules As such only a small portion of I O memory space is currently reserved for operation of the mezzanine board The remaining memory space is defined in the base board s User s Manual The AXM A75 specific memory space address map for the board is shown in Table 3 1 Note that the base address from the base PMC XMC module in memory space must be added to the addresses shown to properly access the board registers Register accesses as 32 16 and 8 bits in memory space are permitted unless otherwise indicated A detailed description of each of the registers follows after Table 3 1 Table 3 1 Memory Map PCIBar2 PCIBar2 0003 Reserved for base PMC XMC Module 0000 y y 7FFF 7FFC 8003 Board Status Register and Software Reset 8000 8007 Reserved for base PMC XMC Module 8004 y y 80FF 80FC 8103 Control Register 8100 AXM A75 User s Manual Multifunction I O Mezzanine Board PCIBar2 PCIBar2 Status Register 0 8108 StatusRegisteri sor Digitalyo 8113 cConversontimer 8117 FLASH 8114 si 8118 Digital oDirection 811F unused 811C y y 81FF 81FC PoC data 8200 8207 ADC1 gain correction 8204 8208 ADCioffset 8208 820C 8213 ADC2data 8210 8217 8214 8218 ADc2offset 8218 821F 821C __ ADCIAata 8220 8227 ADC3 gain correction 8224 8228
24. te PCIBar2 810CH 16 Conversion Timer Register Read Write PCIBar2 8110H n 16 FLASH Data Register Read Write PCIBar2 8114H 17 Digital I O Direction Register Read Write PCIBar2 8118H 17 ADC Channels iia A A A s 17 ADC Data OMA ccc cccestcccctecssiecertscgeuccevseucvers AKEn IAEE DEARC KAAR VTA ipa 17 ADC Offset Register ii aa a ea R EL Lana ao aa 18 ADC Gaih Register enalotto 18 Uncalibrated ADC Performance 18 Analog Input Channel Calibration Procedure i 19 DAGChannels a billo aa nani 19 DAC Data Register irreale 21 DAC Coarse Gain Register 21 DAG Fine Gain Register siii E ii air ci 21 DAC Offset Registera illa a it lalla en dd 22 Updating DAC OUTPUTS La ili o 22 THEORY OF OPERATION ccie monien naea A AIA RIA ia aaa 23 Field OCN alal ALA 23 AXM A75 User s Manual Multifunction I O Mezzanine Board 5 0 6 0 7 0 8 0 Digitall Disc AS canile San Dea Bathe bees tt 24 Analog Qutputs cetacei Aiea ieee eae ee 24 Analoginputs rt iii kita Sel eae sk ele AE E eS 24 SERVICE AND REPAIR Una e Ri 25 SERVICE AND REPAIR ASSISTANCE 25 PRELIMINARY SERVICE PROCEDURE ccoo nano na nn naco na rra nn c rancia cnn cnn crac 25 WHERE TOGET HELP 000 dit A A AAA A A anes 25 SPECIFICATIONS viii ROSA 26 A AUDI a aa a LIA AL LR cl Li e 26 CONNECT AAA 26 ENVIO Maldita A A dai aia 26 Power Requirements tt
25. te PCIBar2 810CH The Digital I O register provides access to the 16 digital I O lines Digital I O lines are pulled high via a 4 75K Ohm resistor to 5 Volts The levels of the digital I O lines are returned upon a read to this address The appropriate output enable bit must be 1 in the Digital I O Direction register to enable writing to a digital output Table 3 7 Digital I O 810CH BIT FUNCTION 31 16 15 0 Digital I O signals 15 0 Conversion Timer Register Read Write PCIBar2 8110H This read write register controls the sample period of all A D converters Sample period count ADC Clock Period Set count to zero to allow A D converters to sample at their maximum rate of 500 KHz For sample rates less than 500 KHz enter a count gt 2 uS ADC Clock Period This register must be written using a 32 bit write command The minimum sample period is 2 uS The maximum sample period is 2 1 ADC Clock Period The ADC Clock Period is 10 101 nS for host boards based on Xilinx Virtex 4 FPGA s The ADC Clock Period is 8 nS for host boards based on Virtex 5 or Spartan 6 16 AXM A75 User s Manual Multifunction I O Mezzanine Board Table 3 8 Conversion Timer 8110H FUNCTION 31 0 Sample Period register value ADC Clock Period FLASH Data Register Read Write PCIBar2 8114H A byte write to this address triggers a write read serial transfer to from the serial FLASH device A byte read from this a
26. te the power requirements of the carrier board plus the installed PMC or AXM A75 User s Manual Multifunction I O Mezzanine Board XMC modules plus the AXM A75 within the voltage tolerances specified IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature The lack of air circulation within the computer chassis is a cause for some concern Most if not all computer chassis do not provide a fan for cooling of add in boards The dense packing of the mezzanine modules to the carrier board alone results in elevated module and carrier board temperatures and the restricted air flow within the chassis aggravates this problem Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering AXM A75 User s Manual Multifunction I O Mezzanine Board Front Panel Field I O Connector J1 The AXM A75 front panel field I O connector J1 is a 68 pin VHDCI receptacle A cable assembly and termination panel or user defined terminations can be quickly mated to the field I O connector The pin assignment for this connector is shown in Table 2 1 Table 2 1 J1 Pin Assignment in Description Number pin Description Number GND sii II IS
27. to date product and software information Go to the Support tab to access e Application Notes e Frequently Asked Questions FAQ s 25 AXM A75 User s Manual Multifunction I O Mezzanine Board e Product Knowledge Base e Tutorials e Software Updates Drivers An email question can also be submitted from within the Knowledge Base or directly from the Contact Us tab Acromag s application engineers can also be contacted directly for technical assistance via telephone or FAX through the numbers listed below When needed complete repair services are also available Phone 248 295 0310 Fax 248 624 9234 Email solutions acromag com 6 0 SPECIFICATIONS Physical Physical Configuration Single AXM Module Stacking Height 5mm Length i 38 5 mm 1 516 inches Width 73 75 mm 2 904 inches Board Thickness 1 59 mm 0 062 inches Connectors P1 FPGA Interface 162 pin receptacle 5 mm stack height high speed terminal strip Samtec QTS 075 01 L D A K J1 Field I O 68 pin VHDCI receptacle Amphenol HE11 RDA 101 3 C Environmental Operating Temperature O to 70 C Relative Humidity 5 95 non condensing Storage Temperature 55 C to 150 C Non Isolated Logic and field commons have a direct electrical connection Radiated Field Immunity
28. tor spec s 1 Amp maximum at 50 energized SCSI 3 connector spec s Operating Temperature 30 C to 80 C Storage Temperature 40 C to 85 C Shipping Weight 1 0 pound 0 5Kg packed 30 AXM A75 User s Manual Multifunction I O Mezzanine Board TERMINATION PANEL MODEL 5025 288 Type Termination Panel for 68 Pin SCSI 3 Cable Connection Application To connect field I O signals to the board Termination Panel Acromag Part 4001 066 The 5025 288 termination panel facilitates the connection of up to 68 field I O signals and connects to the board connectors only via a round shielded cable Model 5028 432 Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 68 correspond to field I O pins 1 68 on the board Each board has its own unique pin assignments Refer to the board manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 920 Field Wiring 68 position terminal blocks with screw clamps Wire range 12 to 26 AWG Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperature 40 C to 100 C Shipping Weight 1 0 pounds 0 5kg packaged 31 AXM A75 User s Manual Multifunction I O Mezzanine Board 8 0 DRAWINGS
29. write register is used to issue a software reset view and clear pending interrupts and to identify the attached AXM module It may also provide other functions that are defined by the base board Writing a 1 to bit 31 of this register will cause a software reset affecting both the PMC base board and the majority of AXM A75 registers Bits 15 to 13 are used for AXM identification code Read of this register reflects the interrupt pending status Read of a 1 in bits 1 or O indicates that an interrupt is pending for the corresponding interrupt Table 3 3 Board Status and Reset Register 8000H FUNCTION 31 Software Reset Write Only 14 AXM A75 User s Manual Multifunction I O Mezzanine Board BIT FUNCTION 30 16 Reserved for base board AXM Identification bits Read Only 15 13 AXM EDK 001 AXM A75 011 12 2 eserved for base board 1 IFO overflow interrupt pending FIFO half full interrupt pending Control Register Read Write PCIBar2 8100H The control register is used to enable interrupts control amplifier gain control the FLASH chip select signal and start stop the A D converter for each channel See Table 3 4 for a description of each of the register bits Table 3 4 Control Register 8100H BIT FUNCTION 31 FIFO overflow interrupt enable FIFO half full interrupt enable Amplifier Gain 00 Gain 1 full scale input range 10 24 Volts 01 Gain 2 full scale input
30. xas Instruments INA159 level translation difference amplifier that divides its input voltage by 5 and level shifts the output by one half of the 4 096 reference voltage The output from the difference amplifier drives an Analog Devices AD7686 16 bit 500 kSPS ADC Each of the ADCs has separate clock convert and serial data connections to the FPGA allowing synchronous acquisition and simultaneous data transfer 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in section 2 0 PREPARATION FOR USE have been followed Replacement of a suspected faulty unit with one that is known to work correctly is a good technique to isolate a faulty board CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up

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