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EFM8 Busy Bee Family EFM8BB2 Reference Manual

1. DATA BUS amp 8 ACCUMULATOR B REGISTER STACK POINTER no 1 2 lt SRAM a PSW 4 ADDRESS eo d ALU REGISTER 8 a s DATA BUS i SFR ADDRESS BUFFER SER SFR_CONTROL BUS DATA POINTER INTERFACE DATA SFR READ DATA PC INCREMENTER Ds MEM_ADDRESS PROGRAM COUNTER PC 2 MEM _ a MEMORY PRGM ADDRESS REG IA INTERFACE MEM WRITE DATA a MEM READ DATA PIPELINE CONTROL LOGIC SYSTEM IRQs CLOCK INTERRUPT INTERFACE EMULATION IRI STOP 08 DEATIONSIRG lt POWER CONTROL IDLE REGISTER Miis d Figure 10 1 CIP 51 Block Diagram silabs com Smart Connected Energy friendly Preliminary Rev 0 2 67 EFM8BB2 Reference Manual CIP 51 Microcontroller Core Performance The CIP 51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture The CIP 51 core executes 76 of its 109 instructions in one or two clock cycles with no instructions taking more than eight clock cycles The table bel
2. ANL A direct AND direct byte to A 2 2 2 ANL A Ri AND indirect RAM to A 1 2 2 ANL A data AND immediate to A 2 2 2 ANL direct A AND A to direct byte 2 2 2 ANL direct data AND immediate to direct byte 3 3 3 ORL A Rn OR Register to A 1 1 1 ORL A direct OR direct byte to A 2 2 2 ORL Ri OR indirect RAM to A 1 2 2 ORL A data OR immediate to A 2 2 2 ORL direct A OR A to direct byte 2 2 2 ORL direct data OR immediate to direct byte 3 3 3 XRL A Rn Exclusive OR Register to A 1 1 1 XRL A direct Exclusive OR direct byte to A 2 2 2 XRL A Ri Exclusive OR indirect RAM to A 1 2 2 XRL A data Exclusive OR immediate to A 2 2 2 XRL direct A Exclusive OR A to direct byte 2 2 2 XRL direct data Exclusive OR immediate to direct byte 3 3 3 CLRA Clear A 1 1 1 CPLA Complement A 1 1 1 RLA Rotate A left 1 1 1 RLCA Rotate A left through Carry 1 1 1 RRA Rotate A right 1 1 1 RRCA Rotate A right through Carry 1 1 1 SWAP A Swap nibbles of A 1 1 1 Data Transfer MOV A Rn Move Register to A 1 1 1 MOV A direct Move direct byte to A 2 2 2 MOV A Ri Move indirect RAM to A 1 2 2 MOV A data Move immediate to A 2 2 2 MOV Rn A Move A to Register 1 1 1 MOV Rn direct Move direct byte to Register 2 2 2 MOV Rn data Move immediate to Register 2 2 2 MOV direct A Move A to direct byte 2 2 2 MOV direct Rn Move Register to direct byte 2 2 2 MOV direct direct Move direct byte to direct byte 3 3 3 MOV direct
3. Ex CKPOL 1 1 3 z F VVVVVVV Figure 17 5 Master Mode Data Clock Timing SCK 1 LI LT LT LT LI LI LT Le SCK CKPOL 1 0 LF LI LI LIP LI vosi wes X ses X X viso us y X 2 X YX NSS 4 Wire Mode A Figure 17 6 Slave Mode Data Clock Timing CKPHA 0 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 203 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO SCK CKPOL 0 CKPHA 1 SCK CKPOL 1 1 MOSI MISO NSS 4 Wire Mode Figure 17 7 Slave Mode Data Clock Timing CKPHA 1 17 3 5 Basic Data Transfer The SPI bus is inherently full duplex It sends and receives a single byte on every transfer The SPI peripheral may be operated on a byte by byte basis using the SPInDAT register and the SPIF flag The method firmware uses to send and receive data through the SPI interface is the same in either mode but the hardware will react differently Master Transfers As SPI master all transfers are initiated with a write to SPINDAT and the SPIF flag will be set by hardware to indicate the end of each transfer The general method for a single byte master transfer follows 1 Write
4. 3 Special Function Registers 13 3 1 Special Function Register Access 43 3 2 Special Function Register Memory 6 3 3 SFR Access Control Registers 21 30 1 SFRPAGE SER Page iode ds se fe ROO Ae ose de boues de 3 3 2 SFRPGGN SFR Page Control oo x22 3 3 3 SFRSTACK SER Page Stack 254 24 4 W 40 Gow el ae 22 4 Flash Memory 4 e x 0 ox xo Romo Ro Rok 9o x x 23 4 1 Introduction 2 2 2 28 4 2 Features 24 4 3 Functional 2 25 4 3 1 Security Options ee 329 4 3 2 Programming the Flash Memory je ADU tee ER A tUe 6 0 226 4 3 2 1 Flash Lock Key Functions aaa 26 4 3 2 2 Flash Page Erase Procedure 126 4 3 2 3 Flash Byte Write Procedure DT 4 3 3 Flash Write and Erase Precautions 27 44 Flash Control Registers 5 2 2 2 29 4 4 1 PSCTL Program Store Control 29 442 FLKEY Flash Lock and Key
5. Bit 7 6 5 4 3 2 1 0 CRCODAT Access RW Reset 0x00 SFR Page 0x0 0x20 SFR Address OxDE Bit Reset Access Description 7 0 CRCODAT 0x00 RW CRC Data Output Each read or write performed on CRCODAT targets the CRC result bits pointed to by the CRCO Result Pointer CRCPNT bits in CRCOCNO CRCODAT may not be valid for one cycle after setting the CRCINIT bit in the CRCOCNO register to 1 Any time CRCINIT is written to 1 by firmware at least one instruction should be performed before reading CRCODAT 14 4 4 CRCOST 0 Automatic Flash Sector Start Bit 7 6 5 4 3 2 1 0 CRCST Access RW Reset 0x00 SFR Page 0x0 0x20 SFR Address 0 02 Bit 7 0 Reset Access Description CRCST 0x00 RW Automatic CRC Calculation Starting Block These bits specify the flash block to start the automatic CRC calculation The starting address of the first flash block inclu ded in the automatic CRC calculation is CRCST x block_size where block_size is 256 bytes 14 4 5 CRCOCNT CRCO Automatic Flash Sector Count Bit 7 6 4 3 2 1 0 CRCCNT Access RW Reset 0x00 SFR Page 0x0 0x20 SFR Address OxD3 Bit Name Reset Access Description 7 0 CRCCNT 0x00 RW Automatic CRC Calculation Block Count These bits specify the number of flash blocks to include in an automatic CRC calculation The last address of the last flash block included in th
6. Bit 7 6 5 4 3 2 1 0 Reserved BREN Reserved BPS Access RW RW RW RW Reset 0 0 0x0 SFR Page 0x20 SFR Address 0x94 Bit Reset Access Description 7 Reserved Must write reset value 6 BREN 0 RW Baud Rate Generator Enable Value Name Description 0 DISABLED Disable the baud rate generator UART1 will not function 1 ENABLED Enable the baud rate generator 5 3 Reserved Must write reset value 2 0 BPS 0x0 RW Baud Rate Prescaler Select Value Name Description 0x0 DIV BY 12 Prescaler 12 0 1 BY 4 Prescaler 4 0x2 DIV BY 48 Prescaler 48 0x3 DIV_BY_1 Prescaler 1 0 4 DIV BY 8 Prescaler 8 0x5 DIV BY 16 Prescaler 16 0x6 DIV BY 24 Prescaler 24 0 7 DIV BY 32 Prescaler 32 21 4 5 SBRLH1 UART1 Baud Rate Generator High Byte Bit 7 6 5 4 3 2 1 0 Access RW Reset 0x00 SFR Page 0x20 SFR Address 0x96 Reset Access Description 7 0 BRH 0x00 RW UART1 Baud Rate Reload High This field is the high byte of the 16 bit UART1 baud rate generator The high byte of the baud rate generator should be written first then the low byte The baud rate is determined by the following equation Baud Rate SYSCLK 65536 BRH1 BRL1 1 2 1 Prescaler silabs com Smart Connected Energy friendly Preliminary Rev 0 2 280 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1
7. 8 4 2 HFOOCAL High Frequency Oscillator 0 Calibration Bit 7 6 5 4 3 2 1 0 HFOOCAL Access RW Reset Varies SFR Page 7 0x0 0x10 SFR Address OxC7 Bit Reset Access Description 7 0 HFOOCAL Varies RW Oscillator Calibration These bits determine the period for high frequency oscillator 0 When set to 0x00 the oscillator operates at its fastest set ting When set to OxFF the oscillator operates at its slowest setting The reset value is factory calibrated and the oscillator will revert to the calibrated frequency upon reset 8 4 3 HFO1CAL High Frequency Oscillator 1 Calibration Bit 7 6 4 3 2 1 0 Reserved HFO1CAL Access R RW Reset 0 Varies SFR Page 0x10 SFR Address 0xD6 Bit Name Reset Access Description 7 Reserved Must write reset value 6 0 HFO1CAL Varies RW Oscillator Calibration These bits determine the period for high frequency oscillator 1 When set to 0x00 the oscillator operates at its fastest set ting When set to 0x7F the oscillator operates at its slowest setting The reset value is factory calibrated and the oscillator will revert to the calibrated frequency upon reset silabs com Smart Connected Energy friendly Preliminary Rev 0 2 57 EFM8BB2 Reference Manual Clocking and Oscillators 8 4 4 HFOCN High Frequency Oscillator Control Bit 7 6 5 4 3 2 1 0 HFO1EN Reserved HFOOEN Res
8. Value Name Description 0 DISABLED Disable all Port Match interrupts 1 ENABLED Enable interrupt requests generated by a Port Match 0 ESMBO 0 RW SMBus 5 0 Interrupt Enable This bit sets the masking of the SMBO interrupt Value Name Description 0 DISABLED Disable all SMBO interrupts 1 ENABLED Enable interrupt requests generated by SMBO silabs com Smart Connected Energy friendly Preliminary Rev 0 2 42 EFM8BB2 Reference Manual Interrupts 6 3 5 EIP1 Extended Interrupt Priority 1 Low Bit 7 6 5 4 3 2 1 0 Name PT3 1 PADCO PWADCO PMAT PSMBO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 0x10 SFR Address OxF3 Bit Name Reset Access Description 7 PT3 0 RW Timer 3 Interrupt Priority Control LSB This bit sets the LSB of the priority field for the Timer 3 interrupt 6 PCP1 0 RW This bit sets the LSB of the priority field for the CP1 interrupt Comparator1 1 Interrupt Priority Control LSB 5 PCPO 0 RW This bit sets the LSB of the priority field for the CPO interrupt Comparator0 Interrupt Priority Control LSB 4 PPCAO 0 RW Programmable Counter Array Interrupt Priority Control LSB This bit sets the LSB of the priority field for the PCAO interrupt 3 PADCO 0 RW ADCO Conversion Complete Interrupt Priority Control LSB This bit sets the LSB of the priority fiel
9. ADCOL Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address OXBD Bit Reset Access Description 7 0 ADCOL 0x00 RW Data Word Low Byte When read this register returns the least significant byte of the 16 bit ADCO accumulator formatted according to the set tings in ADSJST The register may also be written to set the lower byte of the 16 bit ADCO accumulator If Accumulator shifting is enabled the most significant bits of the value read will be zeros 12 4 9 ADCOGTH ADCO Greater Than High Byte Bit 7 6 5 4 3 1 0 ADCOGTH Access RW Reset OxFF SFR Page 0x0 0x10 SFR Address OxC4 Bit Name Reset Access Description 7 0 ADCOGTH OxFF RW Greater Than High Byte Most significant byte of the 16 bit greater than window compare register 12 4 10 ADCOGTL ADCO Greater Than Low Byte Bit 7 6 5 4 3 1 0 ADCOGTL Access RW Reset OxFF SFR Page 0x0 0x10 SFR Address 0xC3 Bit Reset Access Description 7 0 ADCOGTL OxFF RW Greater Than Low Byte Least significant byte of the 16 bit greater than window compare register In 8 bit mode this register should be set to 0x00 Preliminary Rev 0 2 131 silabs com Smart Connected Energy friendly EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 4 11 ADCOLTH ADCO Less Than High Byte Bit
10. Reset Access Description 7 16 0 RW Channel 0 16 bit Pulse Width Modulation Enable This bit enables 16 bit mode when Pulse Width Modulation mode is enabled Value Name Description 0 8 BIT 8 to 11 bit PWM selected 1 16 BIT 16 bit PWM selected 6 ECOM 0 RW Channel 0 Comparator Function Enable This bit enables the comparator function 5 CAPP 0 RW Channel 0 Capture Positive Function Enable This bit enables the positive edge capture capability 4 CAPN 0 RW Channel 0 Capture Negative Function Enable This bit enables the negative edge capture capability 3 MAT 0 RW Channel 0 Match Function Enable This bit enables the match function When enabled matches of the PCA counter with a module s capture compare register cause the CCFO bit in the PCAOMD register to be set to logic 1 2 TOG 0 RW Channel 0 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEXO pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW Channel 0 Pulse Width Modulation Mode Enable This bit enables the PWM function When enabled a pulse width modulated signal is output on the CEXO pin 8 to 11 bit PWM is used if PWM16 is cleared to 0 16 bit mode is used if PWM16 is set to 1 If the TOG bit is also set the module operates in Frequency Output Mode 0 ECCF 0 RW Channel 0 Capture Compare Flag Interrupt
11. 2 9 Ae papse um o AN WA alea Rod ue De TAS ME ue ee wA 52 284 8 3 Functional Description s 5 154 8 3 1 Clock Selection e 4 8 3 2 HFOSCO 24 5 MHz Internal Oscillator 54 Table of Contents 294 8 3 3 HFOSC1 49 MHz Internal Oscillator 8 3 4 LFOSCO 80 kHz Internal Oscillator 8 3 5 External Clock 8 4 Clocking and Oscillator Control Registers 8 4 1 CLKSEL Clock Select 8 4 2 HFOOCAL High Frequency Oscillator 0 Calibration 8 4 3 HFO1CAL High Frequency Oscillator 1 Calibration 8 4 4 HFOCN High Frequency Oscillator Control 8 4 5 LFOOCN Low Frequency Oscillator Control 9 Reset Sources and Power Supply Monitor 10 11 9 1 Introduction 9 2 Features 9 3 Functional Description 9 3 1 Device Reset 9 3 2 Power On Reset 9 3 3 Supply Monitor Reset 9 3 4 External Reset 5 3 9 3 5 Missing Clock Detector Reset 9 3 6 Comparator CMPO Reset 9 3 7 Watchdog Timer Reset 9 3 8 Flash Error Reset 9 3 9 Software Reset 9 4 Reset Sources and Supply Monitor Control Registers 9 4 1 RSTSRC Reset Source 9 4 2 VDMOCN Supply Monitor Control CIP 51 Microcontroller Core 10 1 Introduction 10 2 Features 10 3 Functional Description 10 3 1 Programming and Debugging Support 10 3 2 Prefetch Engine 10 3 3 Instruction Set 10 4 CPU Core Registers 10 4 1 DPL Data Pointer Low
12. Value Name Description 0 DISABLED SPIO interrupts will not be generated when RFRQ is set 1 ENABLED SPIO interrupts will be generated if RFRQ is set 2 RFLSH 0 RW RX FIFO Flush This bit flushes the RX FIFO When firmware sets this bit to 1 the internal FIFO counters will be reset and any remaining data will be lost Hardware will clear the RFLSH bit back to 0 when the operation is complete 1 SYSCLK cycle 1 0 RXTH 0x0 RW RX FIFO Threshold This field configures when hardware will set the receive FIFO request bit RFRQ RFRQ is set whenever the number of bytes in the RX FIFO exceeds the value in RXTH Value Name Description 0x0 ZERO RFRQ will be set anytime new data arrives in the RX FIFO when the RX FIFO is not empty 0 1 RFRQ will be set if the FIFO contains more than one byte silabs com Smart Connected Energy friendly Preliminary Rev 0 2 214 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO Reset Access Description 0 2 TWO RFRQ will be set if the RX FIFO contains more than two bytes 0 3 THREE RFRQ will be set if the RX FIFO contains more than three bytes silabs com Smart Connected Energy friendly Preliminary Rev 0 2 215 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO 17 4 6 SPIOFCN1 SPIO FIFO Control 1 Bit 7 6 5 4 3 2
13. silabs com Smart Connected Energy friendly Preliminary Rev 0 2 31 EFM8BB2 Reference Manual Device Identification 5 3 3 REVID Revision Identifcation Bit 7 6 5 4 3 2 1 0 Access R Reset Varies SFR Page 0x0 SFR Address 0 6 Bit Reset Access Description 7 0 REVID Varies R Revision ID This read only register returns the revision ID Value Name Description 0x02 REV A Revision A 0x03 REV_B Revision B silabs com Smart Connected Energy friendly Preliminary Rev 0 2 32 EFM8BB2 Reference Manual Interrupts 6 Interrupts 6 1 Introduction The MCU core includes an extended interrupt system supporting multiple interrupt sources and priority levels The allocation of interrupt sources between on chip peripherals and external input pins varies according to the specific version of the device Interrupt sources may have one or more associated interrupt pending flag s located in an SFR local to the associated peripheral When a peripheral or external source meets a valid interrupt condition the associated interrupt pending flag is set to logic 1 If interrupts are enabled for the source an interrupt request is generated when the interrupt pending flag is set As soon as execution of the current instruction is complete the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine ISR Each
14. writing a 0 generates a NACK Software should write 0 to the bit for the last data transfer to transmit a NACK The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated The interface will switch to Master Transmitter Mode if SMBODAT is written while an active Master Receiver Figure 18 7 Typical Master Read Se quence on page 228 shows a typical master read sequence as it appears on the bus and Figure 18 8 Master Read Sequence State Diagram EHACK 1 on page 229 shows the corresponding firmware state machine Two received data bytes are shown though any number of bytes may be received Notice that the data byte transferred interrupts occur at different places in the sequence depending on whether hardware ACK generation is enabled The interrupt occurs before the ACK with hardware ACK generation disabled and after the ACK when hardware ACK generation is enabled Interrupts with Hardware Enabled EHACK 1 Data Byte Data Byte Interrupts with Hardware Disabled EHACK 0 Received by SMBus S START Interface Haud Transmitted by R READ SMBus Interface SLA Slave Address Figure 18 7 Typical Master Read Sequence silabs com Smart Connected Energy friendly Preliminary Rev 0 2 228 EFM8BB2 Reference Manual System Management Bus 2 SMBO STA sent 1 Clear the STA and STO flags 2 Write SMBODA
15. 8 Code x 64 Byte Pages 16 x 512 Byte pages OxF800 0x0000 Figure 2 2 Flash Memory Map 8 KB Devices On Chip RAM Accessed with MOV Instructions as Indicated OxFF Upper 128 Bytes Special Function RAM Registers Indirect Access Direct Access 0x80 0x7F Lower 128 Bytes RAM Direct or Indirect Access 0x30 0x2F 0x20 0x1F 0x00 General Purpose Register Banks Figure 2 3 Direct Indirect RAM Memory silabs com Smart Connected Energy friendly Preliminary Rev 0 2 11 EFM8BB2 Reference Manual Memory Organization On Chip XRAM Accessed with MOVX Instructions OxFFFF Shadow XRAM Duplicates 0x0000 0x07FF On 2 KB boundaries 0x0800 OxO7FF XRAM 2048 Bytes 0x0000 Figure 2 4 XRAM Memory 2 5 XRAM Control Registers 2 5 1 EMIOCN External Memory Interface Control Bit 7 6 4 3 2 1 0 Reserved PGSEL Access R RW Reset 0x00 SFR Page ALL SFR Address OxE7 Bit Reset Access Description 7 3 Reserved Must write reset value 2 0 PGSEL 0 0 RW XRAM Page Select The XRAM Page Select field provides the high byte of the 16 bit data memory address when using 8 bit MOVX commands effectively selecting a 256 byte page of RAM Since the upper unused bits of the register are always zero the PGSEL field determines which page of XRAM is accessed For example if PGSEL 0x01 addresses 0x0100 to 0x0
16. Hardware CRC Memory ET Seed Calculation Unit 0x0000 or OxFFFF byte level bit reversal CRCOFLIP CRCODAT Figure 14 1 CRC Functional Block Diagram 14 2 Features The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols The CRC module supports the standard CCITT 16 16 bit polynomial 0x1021 and includes the following features Support for CCITT 16 polynomial Byte level bit reversal Automatic CRC of flash contents on one or more 256 byte blocks Initial seed selection of 0x0000 or OXFFFF silabs com Smart Connected Energy friendly Preliminary Rev 0 2 152 EFM8BB2 Reference Manual Cyclic Redundancy Check CRCO 14 3 Functional Description 14 3 1 16 bit CRC Algorithm The CRC unit generates a 16 bit CRC result equivalent to the following algorithm 1 XOR the input with the most significant bits of the current CRC result If this is the first iteration of the CRC unit the current CRC result will be the set initial value 0x0000 or OxFFFF 2 If the MSB of the CRC result is set shift the CRC result and XOR the result with the polynomial 3 the MSB of the result is not set shift the result 4 Repeat steps 2 and 3 for all 8 bits The algorithm is also described in the following example unsigned short UpdateCRC unsigned short CRC acc unsigned char CRC input unsigned char i loop counter define P
17. and CMP1 Bit Reset Access Description 0x3 CMXP_DAC Connect the CMP input to the internal DAC output and CMP is selected by CMXP The internal DAC uses the signal specified by CMXN as its full scale ref erence 1 0 CPMD 0 2 RW Comparator Mode Select These bits affect the response time and power consumption of the comparator Value Name Description 0 0 MODEO Mode 0 Fastest Response Time Highest Power Consumption 0 1 MODE1 Mode 1 0x2 MODE2 Mode 2 0x3 MODE3 Mode 3 Slowest Response Time Lowest Power Consumption 13 4 3 CMPOMX Comparator 0 Multiplexer Selection Bit 7 6 4 3 2 1 0 CMXN CMXP Access RW RW Reset OxF OxF SFR Page 7 0x0 0x10 SFR Address Ox9F Bit Reset Access Description 7 4 CMXN OxF RW Comparator Negative Input MUX Selection This field selects the negative input for the comparator 3 0 CMXP OxF RW Comparator Positive Input MUX Selection This field selects the positive input for the comparator silabs com Smart Connected Energy friendly Preliminary Rev 0 2 145 EFM8BB2 Reference Manual Comparators and CMP1 13 4 4 1 Comparator 0 Control 1 Bit 7 6 5 4 3 2 1 0 Reserved DACLVL Access RW R RW Reset 0 0 0x00 SFR Page 0x10 SFR Address 0x99 Bit Reset Access Description 7 CPINH 0 RW Output Inhibit Th
18. 1 RTS1 routed to Port pin 0 URT1E 0 RW UART1 I O Enable Value Name Description 0 DISABLED UART1 I O unavailable at Port pin 1 ENABLED UART1 1 RX1 routed to Port pins silabs com Smart Connected Energy friendly Preliminary Rev 0 2 88 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 4 PRTDRV Port Drive Strength Bit 7 6 5 4 3 2 1 0 Reserved P3DRV P2DRV P1DRV PODRV Access R RW RW RW RW Reset 0 0 1 1 1 1 SFR Page 0x0 0x20 SFR Address OxF6 Bit Name Reset Access Description 7 4 Reserved Must write reset value 3 P3DRV 1 RW Port 3 Drive Strength Value Name Description 0 LOW DRIVE All pins on P3 use low drive strength 1 HIGH DRIVE All pins on P3 use high drive strength 2 P2DRV 1 RW Port 2 Drive Strength Value Name Description 0 LOW DRIVE All pins on P2 use low drive strength 1 HIGH DRIVE All pins on P2 use high drive strength 1 P1DRV 1 RW Port 1 Drive Strength Value Name Description 0 LOW DRIVE All pins on P1 use low drive strength 1 HIGH DRIVE All pins on P1 use high drive strength 0 PODRV 1 RW Port 0 Drive Strength Value Name Description 0 LOW DRIVE All pins on PO use low drive strength 1 HIGH DRIVE All pins on PO use high drive strength silabs com Smart Connected Energy friendly Preliminary Rev 0 2 89 EFM8BB2 Reference Man
19. 21 4 6 SBRLL1 UART1 Baud Rate Generator Low Byte Bit 7 6 5 4 3 2 1 0 BRL Access RW Reset 0x00 SFR Page 0x20 SFR Address 0x95 Bit Reset Access Description 7 0 BRL 0x00 RW UART1 Baud Rate Reload Low This field is the low byte of the 16 bit UART1 baud rate generator The high byte of the baud rate generator should be writ ten first then the low byte The baud rate is determined by the following equation Baud Rate SYSCLK 65536 BRH1 BRL1 1 2 1 Prescaler silabs com Smart Connected Energy friendly Preliminary Rev 0 2 281 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 4 7 UART1FCNO UART1 FIFO Control 0 Bit 7 6 3 2 1 0 TFLSH TXTH RFRQE RFLSH RXTH Access RW RW RW RW RW RW Reset 0 0 0x0 0 0 0x0 SFR Page 0x20 SFR Address Ox9D Bit Reset Access Description 7 TFRQE 0 RW Write Request Interrupt Enable When set to 1 a UART1 interrupt will be generated any time is logic 1 Value Name Description 0 DISABLED UART1 interrupts will not be generated when is set 1 ENABLED UART1 interrupts will be generated if is set 6 TFLSH 0 RW TX FIFO Flush This bit flushes the TX FIFO When firmware sets this bit to 1 the internal FIFO counters will be reset and any remaining data will not be sent Hardware will clear the
20. 3 TTY gt sh Output CEXO down edge up edge Capture Compare T 0 04 PCAQCPL1 Output CEX1 down edge up edge Figure 16 9 Center Aligned PWM Timing Figure 16 10 N bit Center Aligned PWM Duty Cycle With CEXnPOL 0 PWM resolution on page 185 describes the duty cycle when CEXnPOL in the PCAOPOL regsiter is cleared to 0 Figure 16 11 N bit Center Aligned PWM Duty Cycle With CEXnPOL 1 PWM resolution on page 185 describes the duty cycle when CEXnPOL in the PCAOPOL regsiter is set to 1 The equations are true only when the lowest N bits of the PCAOCPn register are not all Os or all 1s With CEXnPOL equal to zero 10096 duty cycle is produced when the lowest bits of PCAOCPn are all 0 and 0 duty cycle is produced when the lowest bits of PCAOCPn are all 1 For a given PCA resolution the unused high bits in the PCAO counter and the PCAOCPn compare registers are ignored and only the used bits of the PCAOCPn register determine the duty cycle Note Although the PCAOCPn compare register determines the duty cycle it is not always appropriate for firmware to update this regis ter directly See the sections on 8 to 11 bit and 16 bit PWM mode for additional details on adjusting duty cycle in the various modes silabs com Smart Connected Energy friendly Preliminary Rev 0 2 184 EFM8BB2 Reference Manual P
21. Bit 7 6 5 4 3 2 1 0 HSMODE ACTIVE I2COINT NACK START STOP WR RD Access R R RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 7 0x20 SFR Address OxB9 Bit Reset Access Description 7 HSMODE 0 R High Speed Mode This bit is set to 1 by hardware when a High Speed master code is received and automatically clears when a STOP event occurs 6 ACTIVE 0 R Bus Active This bit is set to 1 by hardware when an incoming slave address matches and automatically clears when the transfer com pletes with either a STOP or a NACK event 5 I2COINT 0 RW 12 Interrupt This bit is set when a read RD write WR or a STOP event STOP occurs This bit will also set when the ACTIVE bit goes low to indicate the end of a transfer This bit will generate an interrupt and hardware will automatically clear this bit after the RD and WR bits clear 4 NACK 0 RW NACK This bit is set by hardware when one of the following conditions are met is transmitted by either a Master or a Slave when the ACTIVE bit is high An I2C slave transmits a NACK to a matching slave address Hardware will automatically clear this bit 3 START 0 RW Start This bit is set by hardware when a START is received and a matching slave address is received Software must clear this bit 2 STOP 0 RW Stop This bit is set by hardware when a STOP is received and the last slave address received was a match Software must clear this bit 1 WR 0 RW 2 Write This bit is s
22. ESPIO ET2 ESO ET1 EX1 ETO EXO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0xA8 bit addressable Bit Name Reset Access Description 7 EA 0 RW All Interrupts Enable Globally enables disables all interrupts and overrides individual interrupt mask settings Value Name Description 0 DISABLED Disable all interrupt sources 1 ENABLED Enable each interrupt according to its individual mask setting 6 ESPIO 0 RW SPIO Interrupt Enable This bit sets the masking of the SPIO interrupts Value Name Description 0 DISABLED Disable all SPIO interrupts 1 ENABLED Enable interrupt requests generated by SPIO 5 ET2 0 RW Timer 2 Interrupt Enable This bit sets the masking of the Timer 2 interrupt Value Name Description 0 DISABLED Disable Timer 2 interrupt 1 ENABLED Enable interrupt requests generated by the TF2L or TF2H flags 4 ESO 0 RW UARTO Interrupt Enable This bit sets the masking of the UARTO interrupt Value Name Description 0 DISABLED Disable UARTO interrupt 1 ENABLED Enable UARTO interrupt 3 ET1 0 RW Timer 1 Interrupt Enable This bit sets the masking of the Timer 1 interrupt Value Name Description 0 1 DISABLED ENABLED Disable all Timer 1 interrupt Enable interrupt requests generated by the TF1 flag silabs com Smart Connected Energy friendly Preliminary Rev 0 2 37 EFM8BB2
23. 0 0 RW TX FIFO Threshold This field configures when hardware will set the transmit FIFO request bit TFRQ TFRQ is set whenever the number of bytes in the TX FIFO is equal to or less than the value in TXTH Value Name Description 0x0 ZERO TFRQ will be set when the TX FIFO is empty Ox1 ONE TFRQ will be set when the TX FIFO contains one or fewer bytes 3 RFRQE 0 RW Read Request Interrupt Enable When set to 1 I2CO interrupt will be generated any time RFRQ is logic 1 Value Name Description 0 DISABLED 2 0 interrupts will not be generated when RFRQ is set 1 ENABLED 12 0 interrupts will be generated if RFRQ is set 2 RFLSH 0 RW RX FIFO Flush This bit flushes the RX FIFO When firmware sets this bit to 1 the internal FIFO counters will be reset and any remaining data will be lost Hardware will clear the RFLSH bit back to 0 when the operation is complete 1 SYSCLK cycle 1 0 RXTH 0x0 RW RX FIFO Threshold This field configures when hardware will set the receive FIFO request bit RFRQ RFRQ is set whenever the number of bytes in the RX FIFO exceeds the value in RXTH Value Name Description 0x0 ZERO RFRQ will be set anytime new data arrives in the RX FIFO when the RX FIFO is not empty 0 1 RFRQ will be set if the FIFO contains more than one byte silabs com Smart Connected Energy friendly Preliminary Rev 0 2 172 EFM8BB2 Reference Manual I2C
24. When operating in capture mode TMR2RLH is the captured value of TMR2H 19 4 12 TMR2L Timer 2 Low Byte Bit 7 6 5 4 3 2 1 0 TMR2L Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address 0xCC Bit Reset Access Description 7 0 TMR2L 0x00 RW Timer 2 Low Byte In 16 bit mode the TMR2L register contains the low byte of the 16 bit Timer 2 In 8 bit mode TMR2L contains the 8 bit low byte timer value silabs com Smart Connected Energy friendly Preliminary Rev 0 2 258 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 19 4 13 TMR2H Timer 2 High Byte Bit 7 6 5 4 3 2 1 0 2 Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address 0xCD Bit Reset Access Description 7 0 TMR2H 0x00 RW Timer 2 High Byte In 16 bit mode the TMR2H register contains the high byte of the 16 bit Timer 2 In 8 bit mode TMR2H contains the 8 bit high byte timer value 19 4 14 TMR2CN1 Timer 2 Control 1 Bit 7 6 5 4 3 2 1 0 Reserved T2CSEL Access R RW Reset 0x00 SFR Page 0x10 SFR Address Bit Reset Access Description 7 3 Reserved Must write reset value 2 0 T2CSEL 0 0 RW Timer 2 Capture Select When used in capture mode the T2CSEL register selects the input capture signal Value Name Description 0x0 PIN Capture high
25. If the SCL line is held low by a slave device on the bus no further communication is possible Furthermore the master cannot force the SCL line high to correct the error condition To solve this problem the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a timeout condition Devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition For the SMBus 0 interface Timer 3 is used to implement SCL low timeouts The SCL low timeout feature is enabled by setting the SMBOTOE bit in SMBOCF The associated timer is forced to reload when SCL is high and allowed to count when SCL is low With the associated timer enabled and configured to overflow after 25 ms and SMBOTOE set the timer interrupt service routine can be used to reset disable and re enable the SMBus in the event of an SCL low timeout SCL High SMBus Free Timeout The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 us the bus is designated as free When the SMBOFTE bit in SMBOCF is set the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods as defined by the timer configured for the SMBus clock source If the SMBus is waiting to generate a Master START the START will be generated following this timeout A clock source is required for free timeout dete
26. Value Name Description 0 DISABLED Disable CCF2 interrupts 1 ENABLED Enable a Capture Compare Flag interrupt request when CCF2 is set silabs com Smart Connected Energy friendly Preliminary Rev 0 2 198 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 4 16 PCAOCPL2 PCA Channel 2 Capture Module Low Byte Bit 7 6 5 4 3 2 1 0 PCAOCPL2 Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address Bit Reset Access Description 7 0 PCAOCPL2 0x00 RW PCA Channel 2 Capture Module Low Byte The PCAOCPL2 register holds the low byte LSB of the 16 bit capture module This register address also allows access to the low byte of the corresponding PCA channel s auto reload value for 9 to 11 bit PWM mode The ARSEL bit in register PCAOPWM controls which register is accessed write to this register will clear the module s ECOM bit to a 0 16 4 17 PCAOCPH2 PCA Channel 2 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 2 Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address Bit Reset Access Description 7 0 PCAOCPH 0 00 RW PCA Channel 2 Capture Module High Byte 2 The 2 register holds the high byte MSB of the 16 bit capture module This register address also allows access to the high byte of the corresponding PCA channel s auto reload value for 9 to 11 bit PWM mode The ARS
27. 07 SMBOADR SFRSTACK SMBOADR 0x98 SCONO TMR4CNO SCONO OxD8 PCAOCNO UART1FCN1 0x99 SBUFO 1 SBUFO OxD9 PCAOMD Ox9A PCON1 SPIOFCNO OxDA PCAOCPMO Ox9B CMPOCNO SPIOFCN1 OxDB PCAOCPM1 Ox9C PCAOCLR P3MDOUT OxDC 2 0 9 UART1FCNO OxDD CRCOIN CRCOIN Ox9E PCAOCENT UART1LIN OxDE CRCODAT CRCODAT Ox9F CMPOMX OxDF ADCOPWR OxA0 P2 OxEO ACC silabs com Smart Connected Energy friendly Preliminary Rev 0 2 15 EFM8BB2 Reference Manual Special Function Registers Address SFR Page Address SFR Page bit address 0x00 0 10 bit address 0x00 0x10 able able OxA1 SPIOCFG SPIOCFG OxE1 XBRO XBRO OxA2 SPIOCKR TMR4RLL SPIOCKR 0 2 XBR1 XBR1 OxA3 SPIODAT TMR4RLH SPIODAT 0 XBR2 XBR2 0 4 POMDOUT TMR4L POMDOUT OxE4 ITO1CF 0 5 P1MDOUT P1MDOUT OxE5 OxA6 P2MDOUT CKCON1 P2MDOUT OxE6 EIE1 0 7 SFRPAGE OxE7 EMIOCN 0 8 IE OxE8 ADCOCNO OxA9 CLKSEL OxE9 PCAOCPL1 OxAA CMP1MX OxEA PCAOCPH1 OxAB CMP1MD I2COFCN1 OxEB PCAOCPL2 OxAC SMBOTC CMP1CN1 SMBOTC OxEC 2 OxAD DERIVID I2COFCNO OxED P1MAT P1MAT OxAE OxEE P1MASK P1MASK OxAF OxEF RSTSRC HFOCN SMBOFCT OxBO P3 OxFO B 1 LFOOCN OxF1 POMDIN POMDIN 0 2 ADCOCN1 OxF2 P1MDIN IPH P1MDIN 0xB3 ADCOAC OxF3 EIP1 P2MD
28. 11 4 Port I O Control Registers 11 4 1 XBRO Port I O Crossbar 0 Bit 7 6 5 4 3 2 1 0 SYSCKE CP1AE CP1E CPOAE CPOE SMBOE SPIOE URTOE Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 0x20 SFR Address OxE1 Bit Reset Access Description 7 SYSCKE 0 RW SYSCLK Output Enable Value Name Description 0 DISABLED SYSCLK unavailable at Port pin 1 ENABLED SYSCLK output routed to Port pin 6 CP1AE 0 RW Comparator1 Asynchronous Output Enable Value Name Description 0 DISABLED Asynchronous 1 unavailable at Port pin 1 ENABLED Asynchronous 1 routed to Port pin 5 CP1E 0 RW Comparator1 Output Enable Value Name Description 0 DISABLED CP1 unavailable at Port pin 1 ENABLED CP1 routed to Port pin 4 CPOAE 0 RW Comparator0 Asynchronous Output Enable Value Name Description 0 DISABLED Asynchronous unavailable at Port pin 1 ENABLED Asynchronous routed to Port pin 3 CPOE 0 RW Comparator0 Output Enable Value Name Description 0 DISABLED CPO unavailable at Port pin 1 ENABLED routed to Port pin 2 SMBOE 0 RW SMBO I O Enable Value Name Description 0 DISABLED SMBus 0 unavailable at Port pins 1 ENABLED SMBus 0 I O routed to Port pins 1 SPIOE 0 RW SPI I O Enable silabs com Smart Connected Energy friendly Preliminary Rev 0 2 85 EFM8BB2 Ref
29. 153 154 154 154 155 155 155 156 156 156 157 157 158 158 158 159 159 159 162 167 167 167 168 168 169 170 172 173 174 175 175 176 176 176 176 177 177 298 17 18 16 3 4 Edge Triggered Capture Mode 16 3 5 Software Timer Compare Mode 16 3 6 High Speed Output Mode 16 3 7 Frequency Output Mode 16 3 8 PWM Waveform Generation 16 3 8 1 8 to 11 Bit PWM Modes 16 3 8 2 16 Bit PWM Mode 16 3 8 3 Comparator Clear Function 16 4 PCAO Control Registers 16 4 1 PCAOCNO PCA Control 16 4 2 PCAOMD PCA Mode gov ood 16 4 3 PCAOPWM PCA PWM Configuration 16 4 4 PCAOCLR PCA Comparator Clear Control 16 4 5 PCAOL PCA Counter Timer Low Byte 16 4 6 PCAOH PCA Counter Timer High Byte 16 4 7 PCAOPOL PCA Output Polarity 16 4 8 PCAOCENT Center Alignment Enable 16 4 9 Channel 0 Capture Compare Mode 16 4 10 PCAOCPLO Channel 0 Capture Module Low Byte 16 4 11 PCAOCPHO PCA Channel 0 Capture Module High Byte 16 4 12 PCAOCPM1 PCA Channel 1 Capture Compare Mode 16 4 13 PCAOCPL1 PCA Channel 1 Capture Module Low Byte 16 4 14 PCAOCPH1 PCA Channel 1 Capture Module High Byte 16 4 15 PCAOCPM2 PCA Channel 2 Capture Compare Mode 16 4 16 PCAOCPL2 PCA Channel 2 Capture Module Low Byte 16 4 17 2 Channel 2 Capture Module High Byte Serial Peripheral Interface SPIO 17 1 Introduction 17 2 Features
30. 17 3 Functional Description 17 3 1 Signals 17 3 2 Master Mode Operation 17 3 3 Slave Mode Operation 17 3 4 Clock Phase and Polarity 17 3 5 Basic Data Transfer 17 3 6 Using the SPI FIFOs 17 3 7 SPI Timing Diagrams 17 4 SPIO Control Registers 17 4 1 SPIOCFG SPIO Configuration 17 4 2 SPIOCNO SPIO Control 17 4 3 SPIOCKR SPIO Clock Rate 17 4 4 SPIODAT SPIO Data 17 4 5 SPIOFCNO SPIO FIFO Control 0 17 4 6 SPIOFCN1 SPIO FIFO Control 1 17 4 7 SPIOFCT SPIO FIFO Count System Management Bus I2C SMBO Table of Contents 178 179 180 181 181 185 186 187 188 188 189 190 191 191 192 192 193 194 195 195 196 197 197 198 199 199 200 200 200 201 201 202 202 203 204 204 207 210 210 212 213 213 214 216 217 218 299 19 18 1 Introduction 18 2 Features 18 3 Functional Description 18 3 1 Supporting Documents 18 3 2 SMBus Protocol 18 3 3 Configuring the SMBus Module 18 3 4 Operational Modes 18 4 SMBO Control Registers 18 4 1 SMBOCF SMBus 0 Gentiguration 18 4 2 SMBOTC SMBus 0 Timing and Pin Control 18 4 3 SMBOCNO SMBus 0 Control 18 4 4 SMBOADR SMBus 0 Slave Address 18 4 5 SMBOADM SMBus 0 Slave Address Mask 18 4 6 SMBODAT SMBus 0 Data 18 4 7 SMBOFCNO SMBus 0 FIFO Control 0 18 4 8 SMBOFCN1 SMBus 0 FIFO Control 1 18 4 9 SMBORXLN SMBus 0 Receive Length Counter 18 4 10 SMBOFCT
31. ADWINT can also be used in polled mode The ADC Greater Than ADCOGTH ADCOGTL and Less Than ADCOLTH ADCOLTL registers hold the comparison values The window detector flag can be programmed to indicate when measured data is inside or outside of the user programmed limits de pending on the contents of the ADCOGT and ADCOLT registers The following tables show how the ADCOGT and ADCOLT registers may be configured to set the ADWINT flag when the ADC output code is above below beween or outside of specific values Table 12 7 ADC Window Comparator Example Above 0x0080 Comparison Register Settings Output Code ADCOH L OxO3FF 0x0081 ADWINT Effects ADWINT 1 ADCOGTH L 0x0080 0x0080 0x007F 0x0001 ADCOLTH L 0x0000 0x0000 ADWINT Not Affected Table 12 8 ADC Window Comparator Example Below 0x0040 Comparison Register Settings ADCOGTH L 0x03FF Output Code ADCOH L OxO3FF OxO3FE 0x0041 ADCOLTH L 0x0040 0x0040 ADWINT Effects ADWINT Not Affected 0x003F 0x0000 ADWINT 1 Table 12 9 ADC Window Comparator Example Between 0x0040 and 0x0080 Comparison Register Settings Output Code ADCOH L ADWINT Effects OxO3FF ADWINT Not Affected 0x0081 ADCOLTH L 0x0080 0x0080 0x007F ADWINT 1 0x0041 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 12
32. ANL C bit AND direct bit to Carry 2 2 2 ANL C bit AND complement of direct bit to Carry 2 2 2 ORL C bit OR direct bit to carry 2 2 2 ORL C bit OR complement of direct bit to Carry 2 2 2 MOV C bit Move direct bit to Carry 2 2 2 MOV bit C Move Carry to direct bit 2 2 2 JC rel Jump if Carry is set 2 20r3 20r6 JNC rel Jump if Carry is not set 2 20r3 20 5 JB bit Jump if direct bit is set 3 3or4 3or7 JNB bit rel Jump if direct bit is not set 3 3or4 3or6 JBC bit rel Jump if direct bit is set and clear bit 3 3or4 3or 7 Program Branching silabs com Smart Connected Energy friendly Preliminary Rev 0 2 71 EFM8BB2 Reference Manual CIP 51 Microcontroller Core Mnemonic Description Clock Cycles prefetch off prefetch on ACALL addr11 Absolute subroutine call 2 3 6 LCALL addr16 Long subroutine call 3 4 7 RET Return from subroutine 1 5 8 RETI Return from interrupt 1 5 7 AJMP addr11 Absolute jump 2 3 6 LJMP addr16 Long jump 3 4 6 SJMP rel Short jump relative address 2 3 6 JMP A DPTR Jump indirect relative to DPTR 1 3 5 JZ rel Jump if A equals zero 2 20r3 20 5 JNZ rel Jump if A does not equal zero 2 20r3 20 5 direct rel Compare direct byte and jump if equal 3 4or5 4or 7 CJNE A data rel Compare immediate to A and jump if not equal 3 3or4 3 or6 CJNE Rn data rel Compare immediate to Register and
33. Automatic hardware switching of the SFR page upon interrupt entries and exits may be enabled or disabled using the SFRPGEN loca ted in SFRPGCN Automatic SFR page switching is enabled after any reset silabs com Smart Connected Energy friendly Preliminary Rev 0 2 14 EFM8BB2 Reference Manual Special Function Registers 3 2 Special Function Register Memory Map Table 3 2 Special Function Registers by Address Address SFR Page Address SFR Page bit address 0x00 0 10 bit address 0x00 0x10 able 0 80 0 SMBOCNO SMBOCNO 0x81 SP 1 SMBOCF PFEOCN SMBOCF 0x82 DPL 0 2 SMBODAT SMBODAT 0x83 DPH OxC3 ADCOGTL SMBOFCNO 0x84 4 ADCOGTH SMBOFCN1 0x85 0 5 ADCOLTL SMBORXLN 0x86 CRCOCN1 CRCOCN1 0xC6 ADCOLTH REG1CN 0x87 PCONO OxC7 HFOOCAL 0x88 TCON OxC8 TMR2CNO SCON1 0x89 TMOD OxC9 REGOCN REGOCN Ox8A TLO OxCA TMR2RLL 8 OxCB TMR2RLH 0 8 THO OxCC TMR2L P2SKIP 0x8D TH1 OxCD TMR2H Ox8E CKCONO OxCE CRCOCNO EIE2 CRCOCNO Ox8F PSCTL OxCF CRCOFLIP SFRPGCN CRCOFLIP 0 90 1 OxDO PSW 0x91 TMR3CNO OxD1 REFOCN 0x92 TMR3RLL SBUF1 OxD2 CRCOST CRCOST 0x93 TMR3RLH SMOD1 OxD3 CRCOCNT CRCOCNT 0x94 TMR3L SBCON1 0 04 0 95 TMR3H SBRLL1 OxD5 P1SKIP P1SKIP 0x96 PCAOPOL SBRLH1 OxD6 SMBOADM HFO1CAL SMBOADM 0x97 WDTCN 0
34. Interrupts with Hardware ACK Disabled 0 Received by SMBus S START Interface STOP W WRITE Transmitted by SLA Slave Address SMBus Interface Figure 18 9 Typical Slave Write Sequence silabs com Smart Connected Energy friendly Preliminary Rev 0 2 230 EFM8BB2 Reference Manual System Management Bus I2C SMBO Interrupt QE 1 Clear STA 2 Read Address R W from SMBODAT 1 Set 2 Clear SI Interrupt b ae 1 Read Data From SMBODAT 2 Clear 51 7 1 1 Figure 18 10 Slave State Diagram 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 231 EFM8BB2 Reference Manual System Management Bus I2C SMBO Slave Read Sequence During a read sequence an SMBus master reads data from a slave device The slave in this transfer will be a receiver during the ad dress byte and a transmitter during all data bytes When slave events are enabled INH 0 the interface enters Slave Receiver Mode to receive the slave address when a START followed by a slave address and direction bit READ in this case is received If hardware ACK generation is disabled upon entering Slave Receiver Mode an interrupt is generated and the ACKRQ bit is set The software must respond to the received slave address with an ACK or ignore the received slave address with a NACK If ha
35. PO 7 ITO1CF Conversion Start CNVSTR P0 6 ADCOCNO External Clock Input EXTCLK P0 3 CLKSEL Port Match P0 0 P2 3 POMASK POMAT P1MASK 1 P2MASK P2MAT Any pin used for GPIO P0 0 P3 1 POSKIP P1SKIP P2SKIP silabs com Smart Connected Energy friendly Preliminary Rev 0 2 80 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 3 3 Priority Crossbar Decoder The priority crossbar decoder assigns a priority to each I O function starting at the top with UARTO The XBRn registers are used to control which crossbar resources are assigned to physical I O port pins When a digital resource is selected the least significant unassigned port pin is assigned to that resource excluding UARTO which is always assigned to dedicated pins If a port pin is assigned the crossbar skips that pin when assigning the next selected resource Additionally the the PnSKIP registers allow software to skip port pins that are to be used for analog functions dedicated digital func tions or GPIO If a port pin is to be used by a function which is not assigned through the crossbar its corresponding PnSKIP bit should be set to 1 in most cases The crossbar skips these pins as if they were already assigned and moves to the next unassigned pin It is possible for crossbar assigned peripherals and dedicated functions to coexist on the same pin For example the port match func tion could be configured
36. Ri Move indirect RAM to direct byte 2 2 2 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 70 EFM8BB2 Reference Manual CIP 51 Microcontroller Core Description Clock Cycles prefetch off prefetch on MOV direct data Move immediate to direct byte 3 3 3 MOV Ri A Move A to indirect RAM 1 2 2 MOV direct Move direct byte to indirect RAM 2 2 2 MOV Ri data Move immediate to indirect RAM 2 2 2 MOV DPTR data16 Load DPTR with 16 bit constant 3 3 3 MOVC A Move code byte relative DPTR to A 1 3 6 MOVC A Move code byte relative PC to A 1 3 3 MOVX A Ri Move external data 8 bit address to A 1 3 3 MOVX Ri A Move A to external data 8 bit address 1 3 3 MOVX A DPTR Move external data 16 bit address to A 1 3 3 MOVX DPTR A Move A to external data 16 bit address 1 3 3 PUSH direct Push direct byte onto stack 2 2 2 POP direct Pop direct byte from stack 2 2 2 XCH A Rn Exchange Register with A 1 1 1 XCH A direct Exchange direct byte with A 2 2 2 XCH Ri Exchange indirect RAM with A 1 2 2 XCHD A Ri Exchange low nibble of indirect RAM with A 1 2 2 Boolean Manipulation CLR C Clear Carry 1 1 1 CLR bit Clear direct bit 2 2 2 SETBC Set Carry 1 1 2 SETB bit Set direct bit 2 2 2 CPL C Complement Carry 1 1 1 CPL bit Complement direct bit 2 2 2
37. SMBus 0 FIFO Count Timers 0 Timer1 2 Timer3 and Timer4 19 1 Introduction 19 2 Features 19 3 Functional Description 19 3 1 System Connections 19 3 2 Timer 0 and Timer 1 19 3 2 1 Operational Modes 19 3 3 Timer 2 Timer 3 and Timer 4 19 3 3 1 16 bit Timer with Auto Reload 19 3 3 2 8 bit Timers with Auto Reload Split Mode 19 3 3 3 Capture Mode 19 3 3 4 Timer 3 and Timer 4 Chaining and Wake Source 19 4 Timer 1 2 3 and 4 Control Registers 19 4 1 CKCONO Clock Control 19 4 2 CKCON1 Clock Control 1 19 4 3 TCON Timer 0 1 Control 19 4 4 TMOD Timer 0 1 Mode 19 4 5 TLO Timer 0 Low Byte 19 4 6 TL1 Timer 1 Low Byte 19 4 7 THO Timer 0 High Byte 19 4 8 TH1 Timer 1 High Byte 19 4 9 TMR2CNO Timer 2 Control 0 19 4 10 TMR2RLL Timer 2 Reload Low Byte 19 4 11 TMR2RLH Timer 2 Reload High Byte 19 4 12 TMR2L Timer 2 Low Byte 19 4 13 TMR2H Timer 2 High Byte 19 4 14 TMR2CN1 Timer 2 Control 1 19 4 15 TMR3RLL Timer 3 Reload Low Byte 19 4 16 TMR3RLH Timer 3 Reload High Byte Table of Contents 218 218 218 218 219 221 225 233 233 234 235 236 237 237 238 239 240 240 241 241 241 242 242 242 243 246 248 249 250 250 251 e 251 252 253 254 255 255 256 256 257 258 258 258 259 259 259 260 300 19 4 17 TMR3L Timer
38. THO 8 bits TF1 Interrupt Flag SYSCLK TO TLO 8 bits TFO Interrupt Flag Figure 19 3 TO Mode 3 Block Diagram 19 3 3 Timer 2 Timer 3 and Timer 4 Timer 2 Timer 3 and Timer 4 are functionally equivalent with the only differences being the top level connections to other parts of the system The timers are 16 bits wide formed by two 8 bit SFRs TMRnL low byte and TMRnH high byte Each timer may operate in 16 bit auto reload mode dual 8 bit auto reload split mode or capture mode silabs com Smart Connected Energy friendly Preliminary Rev 0 2 246 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 Clock Selection Clocking for each timer is configured using the TnXCLK bit field the TnML and TnMH bits Timer 2 may be clocked by the system clock the system clock divided by 12 or the external clock source divided by 8 synchronized with SYSCLK The maximum frequency for the external clock is gt ke SYSCLK EXTCLK 7 Timers 3 and 4 may additionally be clocked from the LFOSCO output divided by 8 and are capable of operating in both the Suspend and Snooze power modes Timer 4 includes Timer 3 overflows as a clock source allowing the two to be chained together for longer sleep intervals When operating in one of the 16 bit modes the low side timer clock is used to clock the entire 16 bit timer TnXCLK SYSCLK 12 External Clock 8 LFOSCO 8 T3 and
39. THO TLO 7 65536 THO TLO silabs com Smart Connected Energy friendly Preliminary Rev 0 2 244 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 Mode 2 8 bit Counter Timer with Auto Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8 bit counter timers with automatic reload of the start value TLO holds the count and THO holds the reload value When the counter in TLO overflows from all ones to 0x00 the timer overflow flag TFO in the TCON register is set and the counter in TLO is reloaded from THO If Timer 0 interrupts are enabled an interrupt will occur when the flag is set The reload value in THO is not changed TLO must be initialized to the desired value before enabling the timer for the first count to be correct When in Mode 2 Timer 1 operates identically to Timer O The overflow rate for Timer 0 in 8 bit auto reload mode is F F input Clock Finput Clock TIMERO 28 THO 256 THO Both counter timers are enabled and configured in Mode 2 in the same manner as Mode 0 Setting the TRO bit enables the timer when either GATEO in the TMOD register is logic 0 or when the input signal INTO is active as defined by bit INOPL in register ITO1CF Pre scaled Clock SYSCLK TFO Interrupt Flag INTO THO 8 bits Figure 19 2 TO Mode 2 Block Diagram silabs com Smart Connected Energy friendly Preliminary Rev 0 2 245 EFM8BB2 Reference Manual
40. The generated waveforms are centered about the points where the lower bits of the counter are zero The 1 bit in the PCAO counter acts as a selection between up and down edges In 16 bit mode a special 17th bit is implemented internally for this purpose At the center point the non inverted channel output is low when the 1 bit is 0 and high when the 1 bit is 1 except for cases of 0 and 100 duty cycle Prior to inversion an up edge sets the channel to logic high and a down edge clears the channel to logic low Down edges occur when the 1 bit in the PCAO counter is one and a logical inversion of the value in the module s PCAOCPn regis ter matches the main PCAO counter register for the lowest N bits For example with 10 bit PWM the down edge occurs when the one s complement of bits 9 0 of the PCAOCPn register match bits 9 0 of the PCAO counter bit 10 of the PCAO counter is 1 Up edges occur when the 1 bit in the PCAO counter is zero and the lowest bits of the module s PCAOCPn register match the value of PCAO 1 For example with 10 bit PWM the up edge occurs when bits 9 0 of the PCAOCPn register are one less than bits 9 0 of the PCAO counter and bit 10 of the PCAO counter is 0 An example of the PWM timing in center aligned mode for two channels is shown here In this example the CEXOPOL and CEX1POL bits are cleared to 0 center l Capture Compare 0 01 PCAOCPLO
41. Timers 0 Timer1 Timer2 Timer3 and Timer4 Mode 3 Two 8 bit Counter Timers Timer 0 Only In Mode 3 Timer 0 is configured as two separate 8 bit counter timers held in TLO and THO The counter timer in TLO is controlled using the Timer 0 control status bits in TCON and TMOD TRO CTO GATEO and TFO TLO can use either the system clock or an external input signal as its timebase The THO register is restricted to a timer function sourced by the system clock or prescaled clock THO is enabled using the Timer 1 run control bit TR1 THO sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 inter rupt The overflow rate for Timer Low in 8 bit mode is F F input Clock Finput Clock TIMERO 28 TLO 256 TLO The overflow rate for Timer 0 High in 8 bit mode is F input Clock _ F input Clock 28 THO 7 256 THO FTIMERO Timer 1 is inactive in Mode 3 When Timer 0 is operating in Mode 3 Timer 1 can be operated in Modes 0 1 or 2 but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt However the Timer 1 overflow can be used to generate baud rates for the SMBus and or UART and or initiate ADC conversions While Timer 0 is operating in Mode 3 Timer 1 run control is handled through its mode settings To run Timer 1 while Timer 0 is in Mode 3 set the Timer 1 Mode as 0 1 or 2 To disable Timer 1 configure it for Mode 3 TOM Pre scaled Clock
42. as a transmitter reading the ACK bit indicates the value received during the last ACK cycle ACKRQ is set each time a byte is received indicating that an outgoing ACK value is needed When is set software should write the desired outgoing value to the ACK bit before clearing 1 NACK will be generated if software does not write the ACK bit before clearing SI SDA will reflect the defined ACK value immediately following a write to the ACK bit however SCL will remain low until 1 is cleared If a received slave address is not acknowledged further slave events will be ignored until the next START is detec ted SMBus Data Register The SMBus Data register SMBODAT holds a byte of serial data to be transmitted or one that has just been received Software may safely read or write to the data register when the SI flag is set Software should not attempt to access the SMBODAT register when the SMBus is enabled and the SI flag is cleared to logic 0 Note Certain device families have a transmit and receive buffer interface which is accessed by reading and writing the SMBODAT reg ister To promote software portability between devices with and without this buffer interface it is recommended that SMBODAT not be used as a temporary storage location On buffer enabled devices writing the register multiple times will push multiple bytes into the transmit FIFO 18 3 4 Operational Modes The SMBus interface may be configured to operate as master an
43. iv 5 Drivers 24 PO n 3 ch PCA Priority 256 Byte SRAM Crossbar 12 Slave Decoder Port 1 lt 12 Dri P1 n Voltage 2048 Byte XRAM SMBus yers Regulators Port 2 Supply Monitor SPI CRC 5 P2 n Independent SYSCLK Bi Crossbar Control Drivers Watchdog Timer Bus i Port 3 System Clock Analog Peripherals x P3 n Configuration Drivers Internal Reference 48 MHz 1 5 Oscillator VDD gt o 24 5 MHz 2 VDD Oscillator Low Freq Oscillator enson CMOS Oscillator Input EXTCLK 2 Comparators Figure 1 1 Detailed EFM8BB2 Block Diagram silabs com Smart Connected Energy friendly Preliminary Rev 0 2 1 EFM8BB2 Reference Manual System Overview 1 2 Power All internal circuitry draws power from the VDD supply pin External I O pins are powered from the VIO supply voltage VDD on devi ces without a separate VIO connection while most of the internal circuitry is supplied by an on chip LDO regulator Control over the device power can be achieved by enabling disabling individual peripherals as needed Each analog peripheral can be disabled when not in use and placed in low power mode Digital peripherals such as timers and serial buses have their clocks gated off and draw little power when they are not in use Table 1 1 Power Modes Power Mode Details Mode Entry Wake Up Sources Normal Core and all peripherals clocked and
44. logic low followed by the data bits sent LSB first a parity or extra bit if selected and end with one or two stop bits logic high The data length is variable between 5 and 8 bits A parity bit can be appended to the data and automatically generated and detected by hardware for even odd mark or space parity The stop bit length is selectable between short 1 bit time and long 1 5 or 2 bit times and a multi processor communica tion mode is available for implementing networked UART buses All of the data formatting options can be configured using the SMOD register Note that the extra bit feature is not available when parity is enabled and the second stop bit is only an option for data lengths of 6 7 or 8 bits MARK START ar A gt SPACE BIT TIMES lt N bits N 5 6 7 or8 Figure 21 3 UART1 Timing Without Parity or Extra Bit MARK START 5 N bits N 5 6 7 or 8 Figure 21 4 UART1 Timing With Parity MARK START y 5 BIT TIMES N bits N 5 6 7 or8 Figure 21 5 UART1 Timing With Extra Bit silabs com Smart Connected Energy friendly Preliminary Rev 0 2 272 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 3 3 Flow Control The UART provides hardware flow control via the CTS
45. 0 SFR Page 0x0 0x10 SFR Address 0 9 Bit Name Reset Access Description 7 3 Reserved Must write reset value 2 CEX2CEN 0 RW CEX2 Center Alignment Enable Selects the alignment properties of the CEX2 output channel when operated in any of the PWM modes This bit does not affect the operation of non PWM modes Value Name Description 0 EDGE Edge aligned 1 CENTER Center aligned 1 1 0 RW CEX1 Center Alignment Enable Selects the alignment properties of the CEX1 output channel when operated in any of the PWM modes This bit does not affect the operation of non PWM modes Value Name Description 0 EDGE Edge aligned 1 CENTER Center aligned 0 CEXOCEN 0 RW Center Alignment Enable Selects the alignment properties of the CEXO output channel when operated in any of the PWM modes This bit does not affect the operation of non PWM modes Value Name Description 0 EDGE Edge aligned 1 CENTER Center aligned silabs com Smart Connected Energy friendly Preliminary Rev 0 2 193 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 4 9 PCAOCPMO PCA Channel 0 Capture Compare Mode Bit 7 6 5 4 3 2 1 0 16 TOG PWM ECCF Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 0x10 SFR Address Bit
46. 0 DISABLED BREAKDN flag will not generate UART1 interrupts 1 ENABLED BREAKDN flag will generate UART1 interrupts when it is set 1 SYNCTOIE 0 RW LIN Sync Detect Timeout Interrupt Enable Enables the synctimeout interrupt source Value Name Description 0 DISABLED The SYNCTO flag will not generate UART1 interrupts 1 ENABLED The SYNCTO flag will generate UART1 interrupts when it is set 0 SYNCDIE 0 RW LIN Sync Detect Interrupt Enable Enables the sync detection interrupt source Value Name Description 0 DISABLED The SYNCD flag will not generate UART 1 interrupts 1 ENABLED The SYNCD flag will generate UART1 interrupts when it is set silabs com Smart Connected Energy friendly Preliminary Rev 0 2 287 EFM8BB2 Reference Manual Watchdog Timer WDTO 22 Watchdog Timer WDTO 22 1 Introduction The device includes a programmable watchdog timer WDT running off the low frequency oscillator A WDT overflow forces the MCU into the reset state To prevent the reset the WDT must be restarted by application software before overflow the system experiences a software or hardware malfunction preventing the software from restarting the WDT the WDT overflows and causes a reset Following a reset the WDT is automatically enabled and running with the default maximum time interval If needed the WDT can be disabled by system software or locked on to prevent accidental disabling Once locked the WDT
47. 0 DISABLED Timer 0 enabled when TRO 1 irrespective of INTO logic level 1 ENABLED Timer 0 enabled only when TRO 1 and INTO is active as defined by bit INOPL in register ITO1CF 2 CTO 0 RW Counter Timer 0 Select Value Name Description 0 TIMER Timer Mode Timer increments on the clock defined by TOM in the CKCONO register 1 COUNTER Counter Mode Timer 0 increments on high to low transitions of an external pin TO silabs com Smart Connected Energy friendly Preliminary Rev 0 2 254 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 Bit Name Reset Access Description 1 0 TOM 0 0 RW Timer 0 Mode Select These bits select the Timer 0 operation mode Value Name Description 0 0 MODEO Mode 0 13 bit Counter Timer 0 1 MODE1 Mode 1 16 bit Counter Timer 0x2 MODE2 Mode 2 8 bit Counter Timer with Auto Reload 0x3 MODE3 Mode 3 Two 8 bit Counter Timers 19 4 5 TLO Timer 0 Low Byte Bit 7 6 4 3 2 1 0 TLO Access RW Reset 0x00 SFR Page ALL SFR Address 0x8A Bit Reset Access Description 7 0 TLO 0x00 RW Timer 0 Low Byte The TLO register is the low byte of the 16 bit Timer 0 19 4 6 TL1 Timer 1 Low Byte Bit 7 6 4 3 2 1 0 TL1 Access RW Reset 0x00 SFR Page ALL SFR Address 0x8B Bit Name Reset Access Description 7 0 TL1 0x00 RW Timer 1 Low Byte
48. 0 LOW 7 pin logic value is compared with logic LOW 1 HIGH 7 pin logic value is compared with logic HIGH 6 B6 1 RW Port 0 Bit 6 Match Value See bit 7 description 5 B5 1 RW Port 0 Bit 5 Match Value See bit 7 description 4 B4 1 RW Port 0 Bit 4 Match Value See bit 7 description 3 B3 1 RW Port 0 Bit 3 Match Value See bit 7 description 2 B2 1 RW Port 0 Bit 2 Match Value See bit 7 description 1 B1 1 RW Port 0 Bit 1 Match Value See bit 7 description 0 BO 1 RW Port 0 Bit 0 Match Value See bit 7 description silabs com Smart Connected Energy friendly Preliminary Rev 0 2 91 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 7 Port 0 Pin Latch Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 SFR Page ALL SFR Address 0x80 bit addressable Bit Reset Access Description 7 B7 1 RW Port 0 Bit 7 Latch Value Name Description 0 LOW 7 is low Set PO 7 to drive low 1 HIGH 7 is high Set PO 7 to drive or float high 6 B6 1 RW Port 0 Bit 6 Latch See bit 7 description 5 B5 1 RW Port 0 Bit 5 Latch See bit 7 description 4 B4 1 RW Port 0 Bit 4 Latch See bit 7 description 3 B3 1 RW Port 0 Bit 3 Latch See bit 7 description 2 B2 1 RW Port 0 Bit 2 Latch See bit 7 description 1 B1 1 RW Port 0 Bit 1 Latch See bit 7 desc
49. 0x10 Extended Interrupt Priority 1 Low OxF5 0x10 Extended Interrupt Priority 1 High EIP2 OxF4 0x10 Extended Interrupt Priority 2 EIP2H OxF6 0x10 Extended Interrupt Priority 2 High EMIOCN OxE7 ALL External Memory Interface Control FLKEY 0 7 ALL Flash Lock and Key HFOOCAL OxC7 0x00 0x10 High Frequency Oscillator O Calibration HFO1CAL OxD6 0x10 High Frequency Oscillator 1 Calibration HFOCN OxEF 0x10 High Frequency Oscillator Control I2COCNO OxBA 0x20 2 0 Control I2CODIN OxBC 0x20 2 0 Received Data I2CODOUT OxBB 0x20 2 0 Transmit Data I2COFCNO OxAD 0x20 2 0 FIFO Control 0 I2COFCN1 OxAB 0x20 2 0 FIFO Control 1 I2COFCT OxF5 0x20 2 0 FIFO Count I2COSLAD OxBD 0x20 12 0 Slave Address I2COSTAT 0 9 0 20 2 0 Status IE 0 8 ALL Interrupt Enable IP 0 8 ALL Interrupt Priority IPH OxF2 0x10 Interrupt Priority High ITO1CF 0 4 0 00 0 10 INTO INT1 Configuration LFOOCN OxB1 0x00 0x10 Low Frequency Oscillator Control PO 0x80 ALL Port 0 Pin Latch POMASK OxFE 0x00 0x20 Port 0 Mask POMAT OxFD 0x00 0x20 Port 0 Match POMDIN OxF1 0x00 0x20 Port 0 Input Mode POMDOUT OxA4 0x00 0x20 Port 0 Output Mode POSKIP 0 04 0 00 0 20 Port 0 Skip P1 0x90 ALL Port 1 Pin Latch P1MASK OxEE 0x00 0x20 Port 1 Mask P1MAT OxED 0x00 0x20 Port 1 Match P1MDIN OxF2 0x00 0x20 Port 1 Input Mode P1MDOUT 0 5 0 00 0 20 Port 1 Output Mode P1SKIP 0 05 0 00 0 20 Port 1 Skip P2 0 0 ALL Port 2 Pin Latch
50. 0xC2 0x00 0x20 SMBus 0 Data SMBOFCNO 0xC3 0x20 SMBus 0 FIFO Control 0 SMBOFCN1 0 4 0 20 SMBus 0 FIFO Control 1 SMBOFCT OxEF 0x20 SMBus 0 FIFO Count SMBORXLN 0xC5 0x20 SMBus 0 Receive Length Counter SMBOTC OxAC 0x00 0x20 SMBus 0 Timing and Pin Control SMOD1 0x93 0x20 UART1 Mode SP 0x81 ALL Stack Pointer SPIOCFG OxA1 0x00 0x20 SPIO Configuration SPIOCKR 0 2 0 00 0 20 SPIO Clock Rate SPIOCNO OxF8 0x00 0x20 SPIO Control SPIODAT 0 0 00 0 20 SPIO Data SPIOFCNO Ox9A 0x20 SPIO FIFO Control 0 SPIOFCN1 Ox9B 0x20 SPIO FIFO Control 1 SPIOFCT OxF7 0x20 SPIO FIFO Count TCON 0x88 ALL Timer 0 1 Control THO 0 8 ALL Timer 0 High Byte TH1 0x8D ALL Timer 1 High Byte TLO 0x8A ALL Timer 0 Low Byte TL 1 0 8 ALL Timer 1 Low Byte TMOD 0x89 ALL Timer 0 1 Mode TMR2CNO 0xC8 0x00 0x10 Timer 2 Control 0 TMR2CN1 OxFD 0x10 Timer 2 Control 1 TMR2H OxCD 0x00 0x10 Timer 2 High Byte TMR2L OxCC 0x00 0x10 Timer 2 Low Byte silabs com Smart Connected Energy friendly Preliminary Rev 0 2 20 EFM8BB2 Reference Manual Special Function Registers Register Address SFR Pages Description TMR2RLH OxCB 0x00 0x10 Timer 2 Reload High Byte TMR2RLL OxCA 0x00 0x10 Timer 2 Reload Low Byte TMR3CNO 0x91 0x00 0x10 Timer 3 Control 0 TMR3CN1 OxFE 0x10 Timer 3 Control 1 TMR3H 0x95 0x00 0x10 Timer 3 High Byte TMR3L 0x94 0x00 0x10 Timer 3 Low By
51. 10 4 2 DPH Data Pointer High 10 4 3 SP Stack Pointer 10 4 4 ACC Accumulator 10 4 5 B B Register 10 4 6 PSW Program Status Word 10 4 7 PFEOCN Prefetch Engine Control Port I O Crossbar External Interrupts and Port Match 11 1 Introduction 11 2 Features 11 3 Functional Description 55 55 55 56 56 57 Of 58 59 60 60 60 61 61 62 63 63 63 63 64 64 64 65 65 66 67 67 68 68 68 68 69 73 73 73 3 74 74 75 76 77 77 77 78 Table of Contents 295 12 11 3 1 Port Modes of Operation 11 3 1 1 Port Drive Strength 11 3 2 Analog and Digital Functions 11 3 2 1 Port Analog Assignments 11 3 2 2 Port Digital Assignments 11 3 3 Priority Crossbar Decoder 11 3 3 1 Crossbar Functional Map 11 3 4 INTO and INT1 11 3 5 Port Match gt fu de 11 3 6 Direct Port I O Access Read Write 11 4 Port Control Registers 11 4 1 XBRO Port I O Crossbar 0 11 4 2 XBR1 Port Crossbar 1 11 4 3 XBR2 Port I O Crossbar 2 11 4 4 PRTDRV Port Drive Strength 11 4 5 POMASK Port 0 Mask 11 4 6 Port 0 Match 11 4 7 Port Pin Latch 11 4 8 POMDIN Port 0 Input Mode 11 4 9 POMDOUT Port 0 Output Mode 11 4 10 POSKIP Port 0 Skip 11 4 11 P1MASK Port 1 Mask 11 4 12 P1MAT Port 1 Match 11 4 13 P1 Port 1 Pin Latch 11 4 14 P1MDIN Port 1 Input Mode 11 4 15 P1MDOU
52. 8 or 9 bit data Automatic start and stop generation silabs com Smart Connected Energy friendly Preliminary Rev 0 2 4 EFM8BB2 Reference Manual System Overview Universal Asynchronous Receiver Transmitter UART1 UART1 is an asynchronous full duplex serial port offering a variety of data formatting options A dedicated baud rate generator with 16 bit timer and selectable prescaler is included which can generate a wide range of baud rates A received data FIFO allows UART1 to receive multiple bytes before data is lost and an overflow occurs UART 1 provides the following features Asynchronous transmissions and receptions Dedicated baud rate generator supports baud rates up to SYSCLK 2 transmit or SYSCLK 8 receive 5 6 7 8 or 9 bit data Automatic start and stop generation Automatic parity generation and checking Four byte FIFO on transmit and receive Auto baud detection LIN break and sync field detection CTS RTS hardware flow control Serial Peripheral Interface SPIO The serial peripheral interface SPI module provides access to a flexible full duplex synchronous serial bus The SPI can operate as a master or slave device in both 3 wire or 4 wire modes and supports multiple masters and slaves on a single SPI bus The slave select NSS signal can be configured as an input to select the SPI in slave mode or to disable master mode operation in a multi master environment avoi
53. Address 0 0 bit addressable Bit Reset Access Description 7 MASTER 0 R SMBus Master Slave Indicator This read only bit indicates when the SMBus is operating as a master Value Name Description 0 SLAVE SMBus operating in slave mode 1 MASTER SMBus operating in master mode 6 TXMODE 0 R SMBus Transmit Mode Indicator This read only bit indicates when the SMBus is operating as a transmitter Value Name Description 0 RECEIVER SMBus in Receiver Mode 1 TRANSMITTER SMBus in Transmitter Mode 5 STA 0 RW SMBus Start Flag When reading STA a 1 indicates that a start or repeated start condition was detected on the bus Writing a 1 to the STA bit initiates a start or repeated start on the bus 4 STO 0 RW SMBus Stop Flag When reading STO a 1 indicates that a stop condition was detected on the bus in slave mode or is pending in master mode When acting as a master writing a 1 to the STO bit initiates a stop condition on the bus This bit is cleared by hardware 3 ACKRQ 0 R SMBus Acknowledge Request Value Name Description 0 NOT SET No ACK requested 1 REQUESTED ACK requested 2 ARBLOST 0 R SMBus Arbitration Lost Indicator Value Name Description 0 NOT SET No arbitration error 1 ERROR Arbitration error occurred 1 ACK 0 RW SMBus Acknowledge When read as a master the ACK bit indicates whether an ACK 1 or NACK 0 is received during the most recent byte transfer As a slave this bit should be writ
54. Any Always On Burst Mode 12 25 MHz ADCOPWR 0x40 ADEN 1 ADBMEN 1 ADSC 1 ADCOTK OxBF ADRPT 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 120 EFM8BB2 Reference Manual Analog to Digital Converter ADCO Required Reference Source Mode Configuration SAR Clock Speed Other Register Field Set Throughput tings 125 180 ksps Any Always On Burst Mode 12 25 MHz ADCOPWR 0x40 ADEN 1 ADBMEN 1 ADSC 1 ADCOTK 0x3A ADRPT 1 0 125 ksps External Burst Mode 12 25 MHz ADCOPWR 0x44 ADEN 0 ADBMEN 1 ADSC 1 ADCOTK 0x3A ADRPT 1 50 125 ksps Internal Burst Mode 12 25 MHz ADCOPWR 0x44 ADEN 0 ADBMEN 1 ADSC 1 ADCOTK 0x3A ADRPT 1 0 50 ksps Internal Burst Mode 4 08 MHz ADCOPWR OxF4 ADEN 0 ADBMEN 1 ADSC 5 ADCOTK 0x34 ADRPT 1 Notes 1 ADRPT reflects the minimum setting for this bit field When using the ADC in burst mode up to 64 samples may be auto accumu lated per conversion trigger by adjusting ADRPT For applications where burst mode is used to automatically accumulate multiple results additional supply current savings can be realiz ed The length of time the ADC is active during each burst contains power up time at the beginning of the burst as well as the conver sion time required for each conversion in the burst The power on time is only required at the beginning of each burst When compared with single sample bur
55. CLKSL field selects which oscillator source is used as the system clock while CLKDIV controls the programmable divider When an internal oscillator source is selected as the SYSCLK the external oscillator may still clock certain peripherals In these cases the external oscillator source is synchronized to the SYSCLK source The system clock may be switched on the fly between any of the oscillator sources so long as the selected clock Source is enabled and has settled and CLKDIV may be changed at any time Note Some device families do place restrictions on the difference in operating frequency when switching clock sources Please see the CLKSEL register description for details 8 3 2 HFOSCO 24 5 MHz Internal Oscillator HFOSCO is a programmable internal high frequency oscillator that is factory calibrated to 24 5 MHz The oscillator is automatically ena bled when it is requested The oscillator period can be adjusted via the HFOOCAL register to obtain other frequencies silabs com Smart Connected Energy friendly Preliminary Rev 0 2 54 EFM8BB2 Reference Manual Clocking and Oscillators 8 3 3 HFOSC1 49 MHz Internal Oscillator HFOSC1 is a programmable internal high frequency oscillator that is factory calibrated to 49 MHz The oscillator is automatically ena bled when it is requested The oscillator period can be adjusted via the HFO1CAL register to obtain other frequencies 8 3 4 LFOSCO 80 kHz Internal Oscillator LFOSCO is a
56. CMP1 When INSL is configured to use the reference DAC on the positive channel the negative comparator mux selection is directly connec ted to the negative comparator input The positive mux selection becomes the full scale voltage reference for the DAC and the DAC output is connected to the positive comparator input e Full Scale Reference CMPnP x DACLVL CMPnN 0 CMPnN 1 CMPnN 3 66 CMPnN x x Figure 13 6 Positive Input DAC Connection 13 3 4 Output Routing The comparator s synchronous and asynchronous outputs can optionally be routed to port I O pins through the port I O crossbar The output of either comparator may be configured to generate a system interrupt on rising falling or both edges may also be used as a reset source or as a trigger to kill PCA output channel The output state of the comparator can be obtained at any time by reading the CPOUT bit The comparator is enabled by setting the CPEN bit to logic 1 and is disabled by clearing this bit to logic 0 When disabled the comparator output if assigned to a port I O pin via the crossbar defaults to the logic low state and the power supply to the comparator is turned off Comparator interrupts can be generated on both rising edge and falling edge output transitions The CPFIF flag is set to logic 1 upon a comparator falling edge occurrence and the CPRIF flag is set to logic 1 upon the comparator rising edge occurre
57. Connected Energy friendly Preliminary Rev 0 2 288 EFM8BB2 Reference Manual Watchdog Timer WDTO Disabling the WDT Writing OxDE followed by OxAD to the WDTCN register disables the WDT The following code segment illustrates disabling the WDT CLR EA disable all interrupts MOV WDTCN 0DEh disable software watchdog timer MOV WDTCN 0ADh SETB EA re enable interrupts The writes of OxDE and OxAD must occur within 4 clock cycles of each other or the disable operation is ignored Interrupts should be disabled during this procedure to avoid delay between the two writes Disabling the WDT Lockout Writing OxFF to WDTCN locks out the disable feature Once locked out the disable operation is ignored until the next system reset Writing OxFF does not enable or reset the watchdog timer Applications always intending to use the watchdog should write OxFF to WDTON in the initialization code Setting the WDT Interval WDTON 2 0 controls the watchdog timeout interval The interval is given by the following equation where T rosc is the low frequency oscillator clock period WDTCN 2 0 3 TiFosc 4 This provides a nominal interval range of 0 8 ms to 13 1 s when LFOSCO is configured to run at 80 kHz WDTCN 7 must be logic 0 when setting this interval Reading WDTCN returns the programmed interval WDTCN 2 0 reads 111b after a system reset 22 4 WDTO Control Registers 22 4 1 WDTCN Watchdog Timer Control B
58. CsAMPLE is the size of the ADC sampling capacitor nis the ADC resolution in bits When measuring any internal source RtotaL reduces to Ryux See the electrical specification tables in the datasheet for ADC mini mum settling time requirements as well as the mux impedance and sampling capacitor values silabs com Smart Connected Energy friendly Preliminary Rev 0 2 115 EFM8BB2 Reference Manual Analog to Digital Converter ADCO Configuring the Tracking Time When burst mode is disabled the ADTM bit controls the ADC track and hold mode In its default state the ADC input is continuously tracked except when a conversion is in progress A conversion will begin immediately when the start of conversion trigger occurs When the ADTM bit is logic 1 each conversion is preceded by a tracking period of 4 SAR clocks after the start of conversion signal for any internal conversion trigger source When the CNVSTR signal is used to initiate conversions with ADTM set to 1 ADCO tracks only when CNVSTR is low conversion begins on the rising edge of CNVSTR Setting ADTM to 1 is primarily useful when AMUX set tings are frequently changed and conversions are started using the ADBUSY bit A ADCO Timing for External Trigger Source CNVSTR 1234567289 1011121314 SAR Clocks ADTM 1 OW Power tack Convert a d uid or Convert Mode ADTM 0 Track or Convert Convert Track B ADCO Timing for Internal Trigger Source Writ
59. Enable This bit enables 16 bit mode when Pulse Width Modulation mode is enabled Value Name Description 0 8 BIT 8 to 11 bit PWM selected 1 16 BIT 16 bit PWM selected 6 ECOM 0 RW Channel 2 Comparator Function Enable This bit enables the comparator function 5 CAPP 0 RW Channel 2 Capture Positive Function Enable This bit enables the positive edge capture capability 4 CAPN 0 RW Channel 2 Capture Negative Function Enable This bit enables the negative edge capture capability 3 MAT 0 RW Channel 2 Match Function Enable This bit enables the match function When enabled matches of the PCA counter with a module s capture compare register cause the CCF2 bit in the PCAOMD register to be set to logic 1 2 TOG 0 RW Channel 2 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEX2 pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW Channel 2 Pulse Width Modulation Mode Enable This bit enables the PWM function When enabled a pulse width modulated signal is output on the CEX2 pin 8 to 11 bit PWM is used if PWM16 is cleared to 0 16 bit mode is used if PWM16 is set to 1 If the TOG bit is also set the module operates in Frequency Output Mode 0 ECCF 0 RW Channel 2 Capture Compare Flag Interrupt Enable This bit sets the masking of the Capture Compare Flag CCF2 interrupt
60. Expected Actions Next Status Status Vector ted Write Master to 01010 START Address W received Clear START and I2COINT 00010 Slave ACK sent 00010 Data byte received ACK sent Read data from I2CODIN and clear 00010 or I2COINT Set BUSY to NACK the next byte 10010 or or keep BUSY clear to ACK the next byte 00100 10010 Data byte received NACK sent Read data from I2CODIN and cclear 00010 or I2COINT Clear BUSY to ACK the next byte 10010 or or keep BUSY set to NACK the next byte 00100 00000 Repeated Start Clear I2COINT 01010 00100 STOP received Clear STOP and I2COINT Read Slave to Mas 01001 START Address received Clear START write data to I2CODOUT 00001 ter ACK sent and clear I2COINT 00001 Data byte sent master ACK re Write data to I2CODOUT and clear 00100 ceived I2COINT 10001 Data byte sent master NACK re Clear NACK and I2COINT 00100 ceived 00100 STOP received Clear STOP and I2COINT 15 4 12 0 Slave Control Registers 15 4 1 I2CODIN 12 0 Received Data Bit 7 6 5 4 3 2 1 0 I2CODIN Access R Reset Varies SFR Page 0x20 SFR Address 0xBC Bit Name Reset Access Description 7 0 I2CODIN Varies R 12 0 Received Data Reading this register reads any data received from the RX FIFO I2CODIN may be read until RXE is set to 1 indicating there is no more data in the RX FIFO If this register is rea
61. ISR must end with an RETI instruction which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred If interrupts are not enabled the interrupt pending flag is ignored by the hard ware and program execution continues as normal The interrupt pending flag is set to logic 1 regardless of whether the interrupt is ena bled Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in the IE and ElEn registers However interrupts must first be globally enabled by setting the EA bit to logic 1 before the individual interrupt enables are recognized Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt enable settings Some interrupt pending flags are automatically cleared by the hardware when the CPU vectors to the ISR or by other hardware condi tions However most are not cleared by the hardware and must be cleared by software before returning from the ISR If an interrupt pending flag remains set after the CPU completes the return from interrupt RETI instruction a new interrupt request will be generated immediately and the CPU will re enter the ISR after the completion of the next instruction 6 2 Interrupt Sources and Vectors The CIP51 core supports interrupt sources for each peripheral on the device Software can simulate an interrupt for many peripherals by setting any interru
62. L F Oscillator Ready Value Name Description 0 NOT_SET Internal L F Oscillator frequency not stabilized 1 Internal L F Oscillator frequency stabilized 5 2 OSCLF Varies RW Internal L F Oscillator Frequency Control Fine tune control bits for the Internal L F oscillator frequency When set to 0000b the L F oscillator operates at its fastest setting When set to 1111b the L F oscillator operates at its slowest setting The OSCLF bits should only be changed by firmware when the L F oscillator is disabled OSCLEN 0 1 0 OSCLD 0x3 RW Internal L F Oscillator Divider Select Value Name Description 0 0 DIVIDE BY 8 Divide by 8 selected 0 1 DIVIDE BY 4 Divide by 4 selected 0x2 DIVIDE BY 2 Divide by 2 selected 0 3 DIVIDE BY 1 Divide by 1 selected OSCLRDY is only set back to 0 in the event of a device reset or a change to the OSCLD bits silabs com Smart Connected Energy friendly Preliminary Rev 0 2 59 EFM8BB2 Reference Manual Reset Sources and Power Supply Monitor 9 Reset Sources and Power Supply Monitor 9 1 Introduction Reset circuitry allows the controller to be easily placed in a predefined default condition On entry to this reset state the following occur The core halts program execution Module registers are initialized to their defined reset values unless the bits reset only with a power on reset External port pins are forced to a known state Interrupts and timers are disable
63. Low Byte 19 4 18 TMR3H Timer 3 High Byte 19 4 19 TMR3CNO Timer Control O 19 4 20 TMR3CN1 Timer Control 1 19 4 24 TMR4RLL Timer 4 Reload Low Byte 19 4 22 TMRARLH Timer 4 Reload High Byte 19 4 23 TMRAL Timer 4 Low Byte 19 4 24 TMRAH Timer 4 High Byte 19 4 25 TMRACNO Timer 4 Control O 19 4 26 TMR4CN1 Timer 4 Control 1 20 Universal Asynchronous Receiver Transmitter 0 UARTO 20 1 Introduction 20 2 Features 20 3 Functional Description 20 3 1 Baud Rate Generation 20 3 2 Data Format 20 3 3 Data Transfer 20 3 4 Multiprocessor 20 4 UARTO Control Registers 20 4 1 SCONO UARTO Serial Port Control 20 4 2 SBUFO UARTO Serial Port Data Buffer 21 Universal Asynchronous Receiver Transmitter 1 UART1 21 1 Introduction 21 2 Features 21 3 Functional Description 21 3 1 Baud Rate Generation 21 3 2 Data Format 21 3 3 Flow Control 21 3 4 Basic Data Transfer 21 3 5 Data Transfer With FIFO 21 3 6 Multiprocessor Communications 21 3 7 LIN Break and Sync Detect 21 3 8 Autobaud Detection 21 4 UART1 Control Registers 21 4 1 SCON1 UART1 Serial Port Control 21 4 2 SMOD1 UART1 Mode 21 4 3 SBUF1 Serial Port Data Buffer 21 4 4 SBCON 1 UART1 Baud Rate Generator Control 21 4 5 SBRLH1 UART1 Baud Rate Generator High Byte 21 4 6 SBRLL1 UART1 Baud Rate Generator Low Byte 21 4 7 UART1FCNO UART1 FIFO Control 0 21 4 8 UART1FCN1 UART1 FIFO Cont
64. Name Description 0 DISABLED Disable the 2 0 Slave module 1 ENABLED Enable the I2CO Slave module silabs com Smart Connected Energy friendly Preliminary Rev 0 2 170 EFM8BB2 Reference Manual I2C Slave I2CSLAVEO Bit Name Reset Access Description 0 BUSY 1 RW Busy Value Name Description 0 NOT SET Device will acknowledge an I2C master 1 Device will not respond to an 2 master All I2C data sent to the device will be NACKed silabs com Smart Connected Energy friendly Preliminary Rev 0 2 171 EFM8BB2 Reference Manual I2C Slave I2CSLAVEO 15 4 6 I2COFCNO 12 0 FIFO Control 0 Bit 7 6 3 2 1 0 TFLSH TXTH RFRQE RFLSH RXTH Access RW RW RW RW RW RW Reset 0 0 0x0 0 0 0x0 SFR Page 7 0x20 SFR Address OxAD Bit Reset Access Description 7 TFRQE 0 RW Write Request Interrupt Enable When set to 1 an I2CO interrupt will be generated any time is logic 1 Value Name Description 0 DISABLED 12 0 interrupts will not be generated when is set 1 ENABLED 12 0 interrupts will be generated if TFRQ is set 6 TFLSH 0 RW TX FIFO Flush This bit flushes the TX FIFO When firmware sets this bit to 1 the internal FIFO counters will be reset and any remaining data will not be sent Hardware will clear the TFLSH bit back to 0 when the operation is complete 1 SYSCLK cycle 5 4
65. O 12 4 2 ADCOCN1 ADCO Control 1 12 4 3 ADCOCF ADCO Configuration 12 4 4 ADCOAC ADCO Accumulator Configuration 12 4 5 ADCOPWR ADCO Power Control 12 4 6 ADCOTK ADCO Burst Mode Track Time 12 4 7 ADCOH ADCO Data Word High Byte 12 4 8 ADCOL ADCO Data Word Low Byte 12 4 9 ADCOGTH ADCO Greater Than High Byte 12 4 10 ADCOGTL ADCO Greater Than Low Byte 12 4 11 ADCOLTH ADCO Less Than High Byte 12 4 12 ADCOLTL ADCO Less Than Low Byte 12 4 13 ADCOMX ADCO Multiplexer Selection 12 4 14 REFOCN Voltage Reference Control Comparators and CMP1 13 1 Introduction 13 2 Features 13 3 Functional Description 13 3 1 Response Time and Supply Current 13 3 2 Hysteresis 13 3 3 Input Selection 13 3 3 1 Multiplexer Channel Selection 13 3 3 2 Reference DAC 13 3 4 Output Routing 13 3 4 1 Output Inversion 13 3 4 2 Output Inhibit 13 4 CMPO Control Registers 13 4 1 CMPOCNO Comparator 0 Canina 0 13 4 2 CMPOMD Comparator 0 Mode 13 4 3 CMPOMX Comparator 0 Multiplexer Selection 13 4 4 CMPOCN 1 Comparator 0 Control 1 13 5 1 Control Registers 13 5 1 CMP1CNO Comparator 1 Control 0 Table of Contents 113 113 114 114 114 117 117 118 119 120 122 124 124 125 125 126 127 128 129 130 130 131 131 131 132 132 132 133 134 134 134 134 134 135 135 136 138 140 140 141 142 142 144 145 146 147 147 297 14 15 16 13
66. OxFF to 0x00 TF3L will be set when the low byte overflows regardless of the Timer 3 mode This bit must be cleared by firmware 5 TF3LEN 0 RW Timer 3 Low Byte Interrupt Enable When set to 1 this bit enables Timer 3 Low Byte interrupts If Timer 3 interrupts are also enabled an interrupt will be gen erated when the low byte of Timer 3 overflows 4 TF3CEN 0 RW Timer 3 Capture Enable When set to 1 this bit enables Timer 3 Capture Mode If TF3CEN is set and Timer 3 interrupts are enabled an interrupt will be generated according to the capture source selected by the T3CSEL bits and the current 16 bit timer value in TMR3H TMR3L will be copied to TMR3RLH TMR3RLL 3 T3SPLIT 0 RW Timer 3 Split Mode Enable When this bit is set Timer 3 operates as two 8 bit timers with auto reload Value Name Description 0 16_BIT_RELOAD Timer 3 operates in 16 bit auto reload mode 1 8 BIT RELOAD Timer 3 operates as two 8 bit auto reload timers 2 0 RW Timer 3 Run Control Timer 3 is enabled by setting this bit to 1 In 8 bit mode this bit enables disables TMR3H only TMR3L is always enabled in split mode 1 0 T3XCLK 0x0 RW Timer 3 External Clock Select This bit selects the external clock source for Timer 3 If Timer 3 is in 8 bit mode this bit selects the external oscillator clock source for both timer bytes However the Timer 3 Clock Select bits and T3ML may still be used to select between the externa
67. P2MASK OxFC 0x20 Port 2 Mask silabs com Smart Connected Energy friendly Preliminary Rev 0 2 18 EFM8BB2 Reference Manual Special Function Registers Register Address SFR Pages Description P2MAT 0 0 20 2 P2MDIN OxF3 0x20 Port 2 Input Mode P2MDOUT 0 0 00 0 20 Port 2 Output Mode P2SKIP OxCC 0x20 Port 2 Skip P3 0 0 ALL Port 3 Pin Latch P3MDIN OxF4 0x20 Port 3 Input Mode P3MDOUT Ox9C 0x20 Port 3 Output Mode PCAOCENT Ox9E 0x00 0x10 PCA Center Alignment Enable PCAOCLR Ox9C 0x00 0x10 PCA Comparator Clear Control PCAOCNO OxD8 0x00 0x10 PCA Control PCAOCPHO OxFC 0x00 0x10 PCA Channel 0 Capture Module High Byte PCAOCPH1 OxEA 0x00 0x10 PCA Channel 1 Capture Module High Byte PCAOCPH2 OxEC 0x00 0x10 PCA Channel 2 Capture Module High Byte PCAOCPLO OxFB 0x00 0x10 PCA Channel 0 Capture Module Low Byte PCAOCPL1 OxE9 0x00 0x10 PCA Channel 1 Capture Module Low Byte PCAOCPL2 OxEB 0x00 0x10 PCA Channel 2 Capture Module Low Byte PCAOCPMO OxDA 0x00 0x10 PCA Channel 0 Capture Compare Mode PCAOCPM1 OxDB 0x00 0x10 PCA Channel 1 Capture Compare Mode 2 OxDC 0x00 0x10 PCA Channel 2 Capture Compare Mode PCAOH OxFA 0x00 0x10 PCA Counter Timer High Byte PCAOL OxF9 0x00 0x10 PCA Counter Timer Low Byte PCAOMD OxD9 0x00 0x10 PCA Mode PCAOPOL 0x96 0x00 0x10 PCA
68. RSTb pin is driven low until the supply voltage settles above Vgsr Two delays are present during the supply ramp time First a delay occurs before the POR circuitry fires and pulls the RSTb pin low A second delay occurs before the device is released from reset the delay decreases as the supply ramp time increases supply ramp time is defined as how fast the supply pin ramps from 0 V to For ramp times less than 1 ms the power on reset time is typically less than 0 3 ms Additionally the power supply must reach before the POR circuit releases the device from reset On exit from a power on reset the PORSF flag is set by hardware to logic 1 When PORSF is set all of the other reset flags the RSTSRC register are indeterminate PORSF is cleared by all other resets Since all resets cause program execution to begin at the same location 0x0000 software can read the PORSF flag to determine if a power up was the cause of reset The content of internal data memory should be assumed to be undefined after a power on reset The supply monitor is enabled following a power on reset RSTb Logic HIGH Logic LOW Power On Reset Figure 9 2 Power On Reset Timing silabs com Smart Connected Energy friendly Preliminary Rev 0 2 62 EFM8BB2 Reference Manual Reset Sources and Power Supply Monitor 9 3 3 Supply Monitor Reset The supply monitor senses the voltage on the device s supply pin and
69. RW Flash Programming Control Register This register is used to enable flash programming via the C2 interface To enable C2 flash programming the following co des must be written in order 0x02 0x01 Note that once C2 flash programming is enabled a system reset must be issued to resume normal operation 23 4 5 C2FPDAT C2 Flash Programming Data Bit 7 6 5 4 3 2 1 0 C2FPDAT Access RW Reset 0x00 C2 Address 0 4 Bit Name Reset Access Description 7 0 C2FPDAT 0x00 RW C2 Flash Programming Data Register This register is used to pass flash commands addresses and data during C2 flash accesses Valid commands are listed below 0x03 Device Erase 0x06 Flash Block Read 0x07 Flash Block Write 0x08 Flash Page Erase silabs com Smart Connected Energy friendly Preliminary Rev 0 2 292 Table of Contents 1 System Overview 1 1 Introduction gt 1 2 2 1 3 I O 2 1 4 Clocking EC 1 5 Counters Timers and PWM 3 1 6 Communications and Other Digital Peripherals 4 1 7 Analog 6 1 8 Reset Sources cu 1 9 Debugging T7 1 10 Bootloader T7 2 Memory Organization 8 2 1 Memory Organization 8 2 2 Program Memory 8 2 3 Data Memory 8 24 Memory Map m6 ROUES xe de 510 2 5 XRAM Control Registers AACE GAO BME lun Tuc ake ESCALA Mie 2 5 1 EMIOCN External Memory Merdaco Control
70. Reference Manual Interrupts Bit Name Reset Access Description 2 1 0 RW External Interrupt 1 Enable This bit sets the masking of External Interrupt 1 Value Name Description 0 DISABLED Disable external interrupt 1 1 ENABLED Enable interrupt requests generated by the INT1 input 1 ETO 0 RW Timer 0 Interrupt Enable This bit sets the masking of the Timer 0 interrupt Value Name Description 0 DISABLED Disable all Timer O interrupt 1 ENABLED Enable interrupt requests generated by the TFO flag 0 EXO 0 RW External Interrupt 0 Enable This bit sets the masking of External Interrupt O Value Name Description 0 DISABLED Disable external interrupt 0 1 ENABLED Enable interrupt requests generated by the INTO input silabs com Smart Connected Energy friendly Preliminary Rev 0 2 38 EFM8BB2 Reference Manual Interrupts 6 3 2 IP Interrupt Priority Bit 7 6 5 4 3 2 1 0 Reserved PSPIO PT2 PSO PT1 PX1 PTO Access R RW RW RW RW RW RW RW Reset 1 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0xB8 bit addressable Bit Name Reset Access Description 7 Reserved Must write reset value 6 PSPIO 0 RW Serial Peripheral Interface SPIO Interrupt Priority Control LSB This bit sets the LSB of the priority field for the SPIO interrupt 5 PT2 0 RW Timer 2 Interrupt Priority Control LSB This bit sets the LSB of the pr
71. Register Bit 7 6 5 4 3 1 0 Access RW Reset 0x00 SFR Page ALL SFR Address OxFO bit addressable Bit Name Reset Access Description 7 0 B 0x00 RW B Register This register serves as a second accumulator for certain arithmetic operations silabs com Smart Connected Energy friendly Preliminary Rev 0 2 74 EFM8BB2 Reference Manual CIP 51 Microcontroller Core 10 4 6 PSW Program Status Word Bit 7 6 5 2 1 0 RS 1 PARITY Access RW RW RW RW RW RW R Reset 0 0 0 0 0 0 SFR ALL SFR Address 0 00 bit addressable Bit Name Reset Access Description 7 CY 0 RW Carry Flag This bit is set when the last arithmetic operation resulted in a carry addition or a borrow subtraction It is cleared to logic 0 by all other arithmetic operations 6 AC 0 RW Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into addition or a borrow from subtraction the high order nibble It is cleared to logic 0 by all other arithmetic operations 5 FO 0 RW User Flag 0 This is a bit addressable general purpose flag for use under firmware control 4 3 RS 0x0 RW Register Bank Select These bits select which register bank is used during register accesses Value Name Description 0x0 BANKO Bank 0 Addresses 0x00 0x07 0 1 1 Bank 1 Addresse
72. SFR Page Stack K This register is used to read the contents of the SFR page stack The SFRPGIDX field in the SFRPGCN register controls the level of the stack this register will access silabs com Smart Connected Energy friendly Preliminary Rev 0 2 22 EFM8BB2 Reference Manual Flash Memory 4 Flash Memory 4 1 Introduction On chip re programmable flash memory is included for program code and non volatile data storage The bulk of the flash memory is organized in 512 byte pages 1 KB of the flash is organized in 64 byte pages to simplify EEPROM emulation or other non volatile data storage tasks Either of the flash areas may be used to store code or non volatile data Flash memory may be erased and written through the C2 interface or from firmware by overloading the MOVX instruction Any individual byte in flash memory must only be writ ten once between page erase operations OxFFFF OxFFFE OxFFDO OxFFCF OxFFCO OxFBFF OxFBFE OxFBCO OxFBBF OxFBBE OxFB80 OxFB7F OxF800 Memory Lock Read Only 64 Bytes Read Only 64 Bytes Reserved Code Security Page 64 Bytes Code Security Page 2 Nonvolatile Data 64 Bytes 960 Bytes 15 x 64 Byte Pages Reserved NV Data Security Page 64 Bytes 16 KB Code Nonvolatile Data 32 x 512 Byte pages 14 x 64 Byte Pages Figure 4 1 Flash Memory Map 16 KB Devices silabs com Smart Connected Energy friendly OxFFFF OxFFCO OxFFBF
73. Slave I2CSLAVEO 15 4 7 I2COFCN1 12 0 FIFO Control 1 Bit 7 6 3 2 1 TXNF Reserved RFRQ RXE Reserved Access R R R R R R Reset 1 1 0x0 0 1 0 0 SFR Page 0x20 SFR Address OxAB Bit Name Reset Access Description 7 TFRQ 1 R Transmit FIFO Request Set to 1 by hardware when the number of bytes in the TX FIFO is less than or equal to the TX FIFO threshold TXTH Value Name Description 0 NOT_SET The number of bytes in the TX FIFO is greater than TXTH 1 SET The number of bytes in the TX FIFO is less than or equal to TXTH 6 TXNF 1 R TX FIFO Not Full This bit indicates when the TX FIFO is full and can no longer be written to If a write is performed when TXNF is cleared to 0 it will replace the most recent byte in the FIFO Value Name Description 0 FULL The TX FIFO is full 1 NOT_FULL The TX FIFO has room for more data 5 4 Reserved Must write reset value 3 RFRQ 0 R Receive FIFO Request Set to 1 by hardware when the number of bytes in the RX FIFO is larger than specified by the RX FIFO threshold RXTH Value Name Description 0 NOT SET The number of bytes in the RX FIFO is less than or equal to RXTH 1 SET The number of bytes in the RX FIFO is greater than RXTH 2 RXE 1 R RX FIFO Empty This bit indicates when the RX FIFO is empty If a read is performed when RXE is set the last byte will be returned Value Name Description 0 NOT EMPTY The R
74. TFLSH bit back to 0 when the operation is complete 1 SYSCLK cycle 5 4 0 0 RW TX FIFO Threshold This field configures when hardware will set the transmit FIFO request bit TFRQ TFRQ is set whenever the number of bytes in the TX FIFO is equal to or less than the value in TXTH Value Name Description 0x0 ZERO TFRQ will be set when the TX FIFO is empty 0 1 will be set when the TX FIFO contains one or fewer bytes 0 2 TWO TFRQ will be set when the TX FIFO contains two or fewer bytes 0x3 THREE TFRQ will be set when the TX FIFO contains three or fewer bytes 3 RFRQE 0 RW Read Request Interrupt Enable When set to 1 a UART1 interrupt will be generated any time RFRQ is logic 1 Value Name Description 0 DISABLED UART1 interrupts will not be generated when RFRQ is set 1 ENABLED UART1 interrupts will be generated if RFRQ is set 2 RFLSH 0 RW RX FIFO Flush This bit flushes the RX FIFO When firmware sets this bit to 1 the internal FIFO counters will be reset and any remaining data will be lost Hardware will clear the RFLSH bit back to 0 when the operation is complete 1 SYSCLK cycle 1 0 RXTH 0x0 RW RX FIFO Threshold This field configures when hardware will set the receive FIFO request bit RFRQ RFRQ is set whenever the number of bytes in the RX FIFO exceeds the value in RXTH Value Name Description 0x0 ZERO RFRQ will be set anytime new data arrives in the
75. The TL1 register is the low byte of the 16 bit Timer 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 255 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 19 4 7 Timer 0 High Byte Bit 7 6 5 4 3 2 1 0 THO Access RW Reset 0x00 SFR Page ALL SFR Address 0x8C Bit Reset Access Description 7 0 THO 0x00 RW Timer 0 High Byte The THO register is the high byte of the 16 bit Timer 0 19 4 8 TH1 Timer 1 High Byte Bit 7 6 5 4 3 2 1 0 1 Access RW Reset 0x00 SFR Page ALL SFR Address 0x8D Bit 7 0 Name Reset Access Description TH1 0x00 RW Timer 1 High Byte The 1 register is the high byte of the 16 bit Timer 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 256 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 19 4 9 TMR2CNO Timer 2 Control 0 Bit 7 6 5 4 3 2 1 2 TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK Access RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0x0 SFR Page 0x0 0x10 SFR Address 0 8 bit addressable Bit Reset Access Description 7 TF2H 0 RW Timer 2 High Byte Overflow Flag Set by hardware when the Timer 2 high byte overflows from OxFF to 0x00 In 16 bit mode this will occur when Timer 2 overflows from OxFFFF to 0x0000 When the Timer 2 interrupt i
76. The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW Since the bus is open drain the bus will be pulled LOW The master attempting the HIGH will detect a LOW SDA and lose the arbitration The winning master continues its transmission without interruption the losing master becomes a slave and receives the rest of the transfer if addressed This arbitration scheme is non destructive one device always wins and no data is lost Clock Low Extension 2 provides a clock synchronization mechanism which allows devices with different speed capabilities to coexist on the bus A clock low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters The slave may tem porarily hold the SCL line LOW to extend the clock low period effectively decreasing the serial clock frequency In the 2 Slave peripheral clock stretching is only performed on the SCL falling edge associated with the ACK or NACK bit Clock stretching is always performed on every byte transaction that is addressed to the peripheral Clock stretching is completed by the I2CSLAVEO peripheral when it releases the SCL line from the low state The I2CSLAVEO peripheral releases the SCL line when firm ware writes 0 to the I2COINT bit in the I2COSTAT register SCL Low Timeout If the SCL line is held low by a slave device on the bus no further communication is possible Furthermore the master ca
77. VDD 5V VDD 3V Master SlaveDevice SlaveDevice Device 1 2 SDA SCL Figure 18 2 Typical SMBus System Connection Two types of data transfers are possible data transfers from a master transmitter to an addressed slave receiver WRITE and data transfers from an addressed slave transmitter to a master receiver READ The master device initiates both types of data transfers and provides the serial clock pulses on SCL The SMBus interface may operate as a master or a slave and multiple master devices on the same bus are supported If two or more masters attempt to initiate a data transfer simultaneously an arbitration scheme is employed with a single master always winning the arbitration It is not necessary to specify one device as the Master in a system any device who transmits a START and a slave address becomes the master for the duration of that transfer A typical SMBus transaction consists of a START condition followed by an address byte Bits7 1 7 bit slave address Bit0 R W direc tion bit one or more bytes of data and a STOP condition Bytes that are received by a master or slave are acknowledged ACK with a low SDA during a high SCL see Figure 18 3 SMBus Transaction on page 220 If the receiving device does not ACK the transmit ting device will read a NACK not acknowledge which is a high SDA during a high SCL The direction bit R W occupies the least significant bit position of the address byte The direction bit
78. active it regulates the input voltage to 3 3 V at the VDD pin providing up to 100 mA for the device and system In addition to the normal mode of operation the regulator has two low power modes which may be used to reduce the supply current and may be disabled when not in use Table 7 2 Voltage Regulator Operational Modes Regulator Condition SUSEN Bit BIASENB Bit REG1ENB Bit Relative Power Consumption Normal 0 0 0 highest Suspend 1 0 0 low Bias Disabled X 1 0 extremely low Disabled X 1 1 off The voltage regulator is enabled in normal mode by default Normal mode offers the fastest response times for systems with dynami cally changing loads For applications which can tolerate a lower regulator bandwidth but still require a tightly regulated output voltage the regulator may be placed in suspend mode Suspend mode is activated when firmware sets the SUSEN bit Suspend mode reduces the regulator bias current at the expense of bandwidth For low power applications that can tolerate reduced output voltage accuracy and load regulation the internal bias current may be disa bled completely using the BIASENB bit If firmware sets the BIASENB bit the regulator will regulate the voltage using a method that is more susceptible to process and temperature variations In addition the actual output voltage may drop substantially under heavy loads The bias should only be disabled for light loads 5 mA or less or whe
79. are recommended for different applications Master mode transmit only Use only the TFRQ flag as an interrupt source Inside the ISR check TXNF before writing more data to the FIFO When all data to be sent has been processed through the ISR the ISR may clear TFRQE to 0 to prevent further inter rupts Main threads may then set TFRQE back to 1 when additional data is to be sent Master mode full duplex or receive only Use only the RFRQ flag as an interrupt source Transfers may be started by a write to SPInDAT Inside the ISR check RXE and read bytes from the FIFO as they are available For every byte read a new byte may be written to the transmit FIFO until there are no more bytes to send If operating half duplex in receive only mode the SPInDAT regis ter must still be written to initiate new transfers Slave mode transmit only Use the TFRQ flag as an interrupt source Inside the ISR check TXNF before writing more data to the FIFO The receive FIFO may also be disabled if desired Slave mode receive only Use the flag as an interrupt source If the RXTH field is set to anything other than 0 it is recom mended to configure and enable RX timeouts Inside the ISR check RXE and read bytes from the FIFO as they are available The transmit FIFO may be disabled if desired Note that if the transmit FIFO is not disabled and firmware does not write to SPInDAT bytes received in the shift register could be sent back out on the S
80. as the SYSCLK source the EXTCLK input is always re synchronized to SYSCLK Note When selecting the EXTCLK pin as a clock input source the pin should be skipped in the crossbar and configured as a digital input Firmware should ensure that the external clock source is present or enable the missing clock detector before switching the CLKSL field silabs com Smart Connected Energy friendly Preliminary Rev 0 2 55 EFM8BB2 Reference Manual Clocking and Oscillators 8 4 Clocking and Oscillator Control Registers 8 4 1 CLKSEL Clock Select Bit 7 6 5 4 3 2 1 0 DIVRDY CLKDIV Reserved CLKSL Access R RW R RW Reset 1 0x3 0 0 0 SFR ALL SFR Address 9 Bit Reset Access Description 7 DIVRDY 1 R Clock Divider Ready Indicates when the clock has propagated through the divider with the current CLKDIV setting Value Name Description 0 NOT_READY Clock has not propagated through divider yet 1 READY Clock has proagated through divider 6 4 CLKDIV 0x3 RW Clock Source Divider This field controls the divider applied to the clock source selected by CLKSL The output of this divider is the system clock SYSCLK Value Name Description 0 0 SYSCLK_DIV_1 SYSCLK is equal to selected clock source divided by 1 0 1 SYSCLK DIV 2 SYSCLK is equal to selected clock source divided by 2 0x2 SYSCLK DIV 4 SYSCLK is equal to selected clock source divided by 4 0x
81. auto reload mode is F B F input Clock _ F input Clock TIMERn High 28 TMRnRLH 7 256 TMRnRLH The TFnH bit is set when TMRnH overflows from OxFF to 0x00 the TFnL bit is set when TMRnL overflows from OxFF to 0x00 When timer interrupts are enabled an interrupt is generated each time TMRnH overflows If timer interrupts are enabled and TFnLEN is set an interrupt is generated each time either TMRnL or TMRnH overflows When TFnLEN is enabled software must check the TFnH and TFnL flags to determine the source of the timer interrupt The TFnH and TFnL interrupt flags are not cleared by hardware and must be manually cleared by software TMRnRLH TFnH Overflow TRn Interrupt Timer High Clock TMRnRLL TCLK Timer Low 7 1108 TFnL Overflow Figure 19 7 8 Bit Split Mode Block Diagram silabs com Smart Connected Energy friendly Preliminary Rev 0 2 249 EFM8BB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 and Timer4 19 3 3 3 Capture Mode Capture mode allows a system event to be measured against the selected clock source When used in capture mode the timer clocks normally from the selected clock source through the entire range of 16 bit values from 0x0000 to OxFFFF Setting TFnCEN to 1 enables capture mode In this mode TnSPLIT should be set to 0 as the full 16 bit timer is used Upon a falling edge of the input capture signal the content
82. cannot be disabled until the next sys tem reset The state of the RSTb pin is unaffected by this reset The WDT consists of an internal timer running from the low frequency oscillator The timer measures the period between specific writes to its control register If this period exceeds the programmed limit a WDT reset is generated The WDT can be enabled and disabled as needed in software or can be permanently enabled if desired When the WDT is active the low frequency oscillator is forced on All watchdog features are controlled via the Watchdog Timer Control Register WDTCN Watchdog Timer Lock and Key Watchdog Timer LFOSCO Watchdog Reset Timeout Interval Figure 22 1 Watchdog Timer Block Diagram 22 2 Features The watchdog timer includes a 16 bit timer with a programmable reset period The registers are protected from inadvertent access by an independent lock and key interface The Watchdog Timer has the following features Programmable timeout interval Runs from the low frequency oscillator Lock out feature to prevent any modification until a system reset 22 3 Using the Watchdog Timer Enabling Resetting the WDT The watchdog timer is both enabled and reset by writing OxA5 to the WDTCN register The user s application software should include periodic writes of OxA5 to WDTCN as needed to prevent a watchdog timer overflow WDT is enabled and reset as a result of any system reset silabs com Smart
83. change functionality to suit the capabilities of that MCU 5 2 Unique Identifier A128 bit universally unique identifier UUID is pre programmed into all devices The UUID resides in the read only area of flash memo ry which cannot be erased or written in the end application The UUID can be read by firmware or through the debug interface at flash locations OXFFCO OxFFCF 5 3 Device Identification Registers 5 3 1 DEVICEID Device Identification Bit 7 6 5 4 3 2 1 0 DEVICEID Access R Reset 0x32 SFR Page 0x0 SFR Address 0 5 Bit Reset Access Description 7 0 DEVICEID 0x32 R Device ID This read only register returns the 8 bit device ID 5 3 2 DERIVID Derivative Identification Bit 7 6 4 3 2 1 0 DERIVID Access R Reset Varies SFR Page 0x0 SFR Address OxAD Bit Reset Access Description 7 0 DERIVID Varies R Derivative ID This read only register returns the 8 bit derivative ID which can be used by firmware to identify which device in the product family the code is executing on The R tag in the part numbers indicates the device revision letter in the ordering code The revision letter may be determined by decoding the REVID register Value Name Description 0x01 EFM8BB22F16G QFN2 EFM8BB22F16G R QFN28 8 0x02 EFM8BB21F16G QSO EFM8BB21F16G R QSOP24 P24 0x03 EFM8BB21F16G QFN2 EFM8BB21F16G R QFN20 0
84. for all clock phase and polarity modes 8 bit programmable clock rate master Programmable receive timeout slave Four byte FIFO on transmit and receive Can operate in suspend or snooze modes and wake the CPU on reception of a byte Support for multiple masters on the same data lines silabs com Smart Connected Energy friendly Preliminary Rev 0 2 200 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO 17 3 Functional Description 17 3 1 Signals The SPI interface consists of up to four signals MOSI MISO SCK and NSS Master Out Slave In MOSI The MOSI signal is the data output pin when configured as a master device and the data input pin when configured as a slave It is used to serially transfer data from the master to the slave Data is transferred on the MOSI pin most signifi cant bit first When configured as a master MOSI is driven from the internal shift register in both 3 and 4 wire mode Master In Slave Out MISO The MISO signal is the data input pin when configured as a master device and the data output pin when configured as a slave It is used to serially transfer data from the slave to the master Data is transferred on the MISO pin most signifi cant bit first The MISO pin is placed in a high impedance state when the SPI module is disabled or when the SPI operates in 4 wire mode as a slave that is not selected When acting as a slave in 3 wire mode MISO is always driven from the i
85. in Stop mode This bit will always be read as 0 0 IDLE 0 RW Idle Mode Select Setting this bit will place the CIP 51 in Idle mode This bit will always be read as 0 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 51 EFM8BB2 Reference Manual Power Management and Internal Regulators 7 9 2 PCON1 Power Control 1 Bit 7 6 5 4 3 2 1 0 SNOOZE SUSPEND Reserved Access RW RW R Reset 0 0 0x00 SFR Page 0x0 SFR Address 0x9A Bit Name Reset Access Description 7 SNOOZE 0 RW Snooze Mode Select Setting this bit will place the device in snooze mode High speed oscillators will be halted the SYSCLK signal will be gated off and the internal regulator will be placed in a low power state 6 SUSPEND 0 RW Suspend Mode Select Setting this bit will place the device in suspend mode High speed oscillators will be halted and the SYSCLK signal will be gated off 5 0 Reserved Must write reset value 7 9 3 REGOCN Voltage Regulator 0 Control Bit 7 6 5 4 3 2 1 0 Reserved STOPCF Reserved Access R RW R Reset 0 0 0 0 0 SFR Page 0x0 0x20 SFR Address 0 9 Bit Reset Access Description 7 4 Reserved Must write reset value 3 STOPCF 0 RW Stop Mode Configuration This bit configures the regulator s behavior when the device enters stop mode Value Name Description 0 ACTIVE Regulator is s
86. in stop mode for longer than the missing clock detector timeout the missing clock detector should be disabled in firmware prior to setting the STOP bit 7 5 Suspend Mode Suspend mode is entered by setting the SUSPEND bit while operating from the internal 24 5 MHz oscillator HFOSCO Upon entry into suspend mode the hardware halts both of the high frequency internal oscillators and goes into a low power state as soon as the in struction that sets the bit completes execution All internal registers and memory maintain their original data Suspend mode is terminated by any enabled wake or reset source When suspend mode is terminated the device will continue execu tion on the instruction following the one that set the SUSPEND bit If the wake event was configured to generate an interrupt the inter rupt will be serviced upon waking the device If suspend mode is terminated by an internal or external reset the CIP 51 performs a normal reset sequence and begins program execution at address 0x0000 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 49 EFM8BB2 Reference Manual Power Management and Internal Regulators 7 6 Snooze Mode Snooze mode is entered by setting the SNOOZE bit while operating from the internal 24 5 MHz oscillator HFOSCO Upon entry into snooze mode the hardware halts both of the high frequency internal oscillators and goes into a low power state as soon as the instruc tion that sets the bit com
87. initiates both types of data transfers and provides the serial clock pulses that the I2C slave peripheral detects on the SCL pin This section describes in detail the setting and clearing of various status bits in the I2COSTAT register during different modes of operations In all modes the I2CSLAVEO peripheral performs clock stretching automatically on every SCL falling edge associated with the ACK or NACK bit silabs com Smart Connected Energy friendly Preliminary Rev 0 2 162 EFM8BB2 Reference Manual I2C Slave I2CSLAVEO 12 Write Sequence The 12 Write sequence with the I2C Slave peripheral consists of a series of interrupts and required actions in each interrupt The write sequence consists of the following steps 1 An incoming START and Address W byte causes the peripheral to exit idle mode or wakes the device from a low power state The peripheral will automatically ACK a matching address if BUSY is cleared to 0 2 An interrupt occurs after the automatic ACK of the address The 2 peripheral holds the SCL line low for clock streching until firm ware clears I2COINT Firmware should take the actions indicated by Figure 15 6 12 Write Flow Diagram with the I2C Slave Pe ripheral on page 164 3 Firmware reads one or more bytes of data from the master on each subsequent data interrupt acknowledging ACK or non ac knowledging the data 4 The master sends a STOP when the entire data transfer completes F
88. is 18 system clock cycles 1 clock cycle to detect the interrupt 5 clock cycles to execute the RETI 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR If the CPU is executing an ISR for an interrupt with equal or higher priority the new interrupt will not be serviced until the current ISR completes including the RETI and following instruction If more than one interrupt is pending when the CPU exits an ISR the CPU will service the next highest priority interrupt that is pending silabs com Smart Connected Energy friendly Preliminary Rev 0 2 34 EFM8BB2 Reference Manual Interrupts 6 2 3 Interrupt Summary Table 6 2 Interrupt Priority Table Interrupt Source Priority Primary Enable Auxiliary Enable s Reset 0x0000 Top External Interrupt 0 0x0003 0 IE EXO TCON IEO Timer 0 Overflow 0 000 1 IE ETO TCON TFO External Interrupt 1 0x0013 2 IE EX1 TCON IE1 Timer 1 Overflow 0x001B 3 TCON TF1 UARTO 0x0023 4 IE ESO SCONO RI SCONO TI Timer 2 Overflow Cap 0x002B 5 IE 2 TMR2CNO TF2CEN TMR2CNO TF2H TMR2CNO TF2LEN TMR2CNO TF2L SPIO 0x0033 6 IE ESPIO SPIOFCNO RFRQE SPIOCNO MODF SPIOFCNO TFRQE SPIOCNO RXOVRN SPIOFCN1 SPIFEN SPIOCNO SPIF SPIOCNO WCOL SPIOFCN1 RFRQ SPIOFCN1 TFRQ SMBus 0 0 003 7 EIE1 ESMBO SMBOCNO SI Port Match 0x0043 8 EIE1 EMAT ADCO Wi
89. is reloaded automatically with the value stored in the auto reload registers during the overflow edge in edge aligned mode or the up edge in center aligned mode Setting the ECOMn and PWMn bits in the PCAOCPMn register and setting the CLSEL bits in register PCAOPWM to 00b enables 8 Bit pulse width modulator mode If the bit is set to 1 the CCFn flag for the module is set each time a match edge or up edge occurs The COVF flag in PCAOPWM can be used to detect the overflow or down edge The 9 to 11 bit PWM mode is selected by setting the ECOMn and PWMn bits the PCAOCPMn register and setting the CLSEL bits in register PCAOPWM to the desired cycle length other than 8 bits If the MATn bit is set to 1 the CCFn flag for the module is set each time a match edge or up edge occurs The COVF flag in PCAOPWM can be used to detect the overflow or down edge Important When writing a 16 bit value to the PCAOCPn registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMn bit to 0 writing to PCAOCPHn sets ECOMn to 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 185 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 3 8 2 16 Bit PWM Mode A PCA module may also be operated in 16 Bit PWM mode 16 bit PWM mode is independent of the other PWM modes The entire PCAOCP register is used to determine the duty cycle in 16 bit PWM mode To output a varying duty cycle new
90. jump if not 3 3 or 4 3 or6 equal CJNE Ri data rel Compare immediate to indirect and jump if not 3 4or 5 4or 7 equal DJNZ Rn rel Decrement Register and jump if not zero 2 20r3 2or5 DJNZ direct rel Decrement direct byte and jump if not zero 3 3 or 4 1 1 1 Notes Rn Register RO R7 of the currently selected register bank QRi Data RAM location addressed indirectly through RO or R1 rel 8 bit signed twos complement offset relative to the first byte of the following instruction Used by SJMP and all conditional jumps direct 8 bit internal data location s address This could be a direct access Data RAM location 0 00 0 7 or an SFR 0x80 OxFF data 8 bit constant data16 16 bit constant bit Direct accessed bit in Data RAM or SFR addr11 11 bit destination address used by ACALL and AJMP The destination must be within the same 2 KB page of program memory as the first byte of the following instruction addr16 16 bit destination address used by LCALL and LJMP The destination may be anywhere within the 8 KB program memory space There is one unused opcode 0xA5 that performs the same function as mnemonics copyrighted Intel Corporation 1980 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 72 EFM8BB2 Reference Manual CIP 51 Microcontroller Core 10 4 CPU Core Registers 10 4 1 DPL Data Pointer Low Bit 7
91. last byte will be returned Preliminary Rev 0 2 210 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO Reset Access Description Value Name Description 0 NOT_EMPTY The RX FIFO contains data 1 EMPTY The RX FIFO is empty silabs com Smart Connected Energy friendly Preliminary Rev 0 2 211 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO 17 4 2 SPIOCNO SPIO Control Bit 7 6 5 4 3 2 1 0 SPIF WCOL MODF RXOVRN NSSMD TXNF SPIEN Access RW RW RW RW RW R RW Reset 0 0 0 0 0 1 1 0 SFR Page 0x0 0x20 SFR Address OxF8 bit addressable Bit Name Reset Access Description 7 SPIF 0 RW SPIO Interrupt Flag This bit is set to logic 1 by hardware at the end of a data transfer If SPIF interrupts are enabled with the SPIFEN bit an interrupt will be generated This bit is not automatically cleared by hardware and must be cleared by firmware 6 WCOL 0 RW Write Collision Flag This bit is set to logic 1 if a write to SPIODAT is attempted when TXNF is 0 When this occurs the write to SPIODAT will be ignored and the transmit buffer will not be written If SPI interrupts are enabled an interrupt will be generated This bit is not automatically cleared by hardware and must be cleared by firmware 5 MODF 0 RW Mode Fault Flag This bit is set to logic 1 by hardware when a master mode collision is detected NSS is low MSTEN 1 and NS
92. length 8 11 bits Setting the ECCFn bit in a PCAOCPMnh register enables the module s CCFn interrupt Table 16 2 and PCAOPWM Bit Settings for Capture Compare Modules Operational Mode gt a a e Bit Name a p 0 cia 8 e 5 1 Capture triggered by positive edge X X 1 0 0 0 0 A 0 X B X X CEXn Capture triggered by negative edge on X X 0 1 0 0 0 A 0 X B X X CEXn Capture triggered by any transition on X X 1 1 0 0 0 0 X B X X CEXn Software Timer X 0 0 1 0 0 0 X B X X High Speed Output X 0 0 1 1 0 0 X B X X Frequency Output X C 0 0 0 1 1 0 X B X X 8 Bit Pulse Width Modulator 0 C 0 0 E 0 1 A 0 X B X 0 9 Bit Pulse Width Modulator 0 C 0 0 E 0 1 A D X B X 1 10 Bit Pulse Width Modulator 0 C 0 0 E 0 1 A D X B X 2 11 Bit Pulse Width Modulator 0 C 0 0 E 0 1 A D X B X 3 16 Bit Pulse Width Modulator 1 C 0 0 E 0 1 A 0 X B X X Notes 1 X Don t Care no functional difference for individual module if 1 or 0 2 Enable interrupts for this module interrupt triggered on CCFn set to 1 Enable 8th 11th bit overflow interrupt Depends on setting of CLSEL 4 C When set to 0 the digital comparator is off For high speed and frequency output modes the associated pin will not toggle In any of the PWM modes this generates a 096 duty cycle output 0 5 D Selects whether
93. of the common 8051 SFRs are available on all pages Certain SFRs are only available on a subset of pages SFR pages are selected using the SFRPAGE register The procedure for reading and writing an SFR is as follows 1 Select the appropriate SFR page using the SFRPAGE register 2 Use direct accessing mode to read or write the special function register MOV instruction The SFRPAGE register only needs to be changed in the case that the SFR to be accessed does not exist on the currently selected page See the SFR memory map for details on the locations of each SFR silabs com Smart Connected Energy friendly Preliminary Rev 0 2 13 EFM8BB2 Reference Manual Special Function Registers Interrupts and the SFR Page Stack When an interrupt occurs the current SFRPAGE is pushed onto an SFR page stack to preserve the current context of SFRPAGE Upon execution of the RETI instruction the SFRPAGE register is automatically restored to the SFR page that was in use prior to the interrupt The stack is five elements deep to accomodate interrupts of different priority levels pre empting lower priority interrupts Firm ware can read any element of the SFR page stack by setting the SFRPGIDX field in the SFRPGON register and reading the SFRSTACK register Table 3 1 SFR Page Stack Access SFRPGIDX Value SFRSTACK Contains 0 Value of the first top byte of the stack 1 Value of the second byte of the stack 2 Value of the third b
94. pin as open drain 3 Set the bit associated with the pin in the Pn register to 1 This tells the output driver to drive logic high Because the is config ured as open drain the high side driver is disabled and the pin may be used as an input Open drain outputs are configured exactly as digital inputs The pin may be driven low by an assigned peripheral or by writing O to the associated bit in the Pn register if the signal is a GPIO To configure a pin as a digital push pull output 1 Set the bit associated with the pin in the PnMDIN register to 1 This selects digital mode for the pin 2 Set the bit associated with the pin in the PnMDOUT register to 1 This configures the pin as push pull If a digital pin is to be used as a general purpose I O or with a digital function that is not part of the crossbar the bit associated with the pin in the PnSKIP register can be set to 1 to ensure the crossbar does not attempt to assign a function to the pin The crossbar must be enabled to use port pins as standard port in output mode Port output drivers of all I O pins are disabled whenever the crossbar is disabled 11 3 1 1 Port Drive Strength Port drive strength can be controlled on a port by port basis using the PRTDRV register Each port has a bit in PRTDRV to select the high or low drive strength setting for all pins on that port By default all ports are configured for high drive strength 11 3 2 Analog and Digital Functio
95. power up and wait for the amount of time programmed to the ADPWR bits be fore performing a conversion Otherwise the ADC will start tracking and converting immediately When burst mode is enabled a single convert start will initiate a number of conversions equal to the repeat count When burst mode is disabled a convert start is required to initiate each conversion In both modes the ADC end of conversion interrupt flag ADINT will be set after repeat count conversions have been accumulated Similarly the window comparator will not compare the result to the great er than and less than registers until repeat count conversions have been accumulated 12 3 8 8 Bit Mode Setting the AD8BE bit to 1 will put the ADC in 8 bit mode In 8 bit mode only the 8 MSBs of data are converted allowing the conversion to be completed in fewer SAR clock cycles than a 10 bit conversion The two LSBs of a conversion are always 00 in this mode and the ADCOL register will always read back 0x00 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 117 EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 3 9 12 Bit Mode When configured for 12 bit conversions the ADC performs four 10 bit conversions using four different reference voltages and combines the results into a single 12 bit value Unlike simple averaging techniques this method provides true 12 bit resolution of ac or dc input signals without depending on noise t
96. reference DAC and the comparator inputs There are four possible configurations When INSL is configured for direct input connection the comparator mux channels are directly connected to the comparator inputs The reference DAC is not used in this configuration CMPnP x CMPnN x x Figure 13 3 Direct Input Connection When INSL is configured to ground the negative input the positive comparator mux selection is directly connected to the positive com parator input and the negative comparator input is connected to GND The reference DAC is not used in this configuration silabs com Smart Connected Energy friendly Preliminary Rev 0 2 138 EFM8BB2 Reference Manual Comparators and CMP1 CMPnP 0 CMPnP 1 CMPnP 2 CMPnP 3 QE e e e GND Figure 13 4 Negative Input Ground Connection When INSL is configured to use the reference DAC on the negative channel the positive comparator mux selection is directly connec ted to the positive comparator input The negative mux selection becomes the full scale voltage reference for the DAC and the DAC output is connected to the negative comparator input CMPnP x Full Scale Reference CMPnN 0 X DACLVL CMPnN 1 CMPnN 3 CMPnN x x Figure 13 5 Negative Input DAC Connection silabs com Smart Connected Energy friendly Preliminary Rev 0 2 139 EFM8BB2 Reference Manual Comparators and
97. the Capture Compare register 0 or the Auto Reload register 1 for the associated channel is accessed via addresses PCAOCPHn and PCAOCPLn 6 E When set a match event will cause the CCFn flag for the associated channel to be set 7 All modules set to 8 9 10 or 11 bit PWM mode use the same cycle length setting 16 3 3 1 Output Polarity The output polarity of each PCA channel is individually selectable using the PCAOPOL register By default all output channels are con figured to drive the PCA output signals CEXn with their internal polarity When the CEXnPOL bit for a specific channel is set to 1 that channel s output signal will be inverted at the pin All other properties of the channel are unaffected and the inversion does not apply to PCA input signals Changes in the PCAOPOL register take effect immediately at the associated output pin silabs com Smart Connected Energy friendly Preliminary Rev 0 2 177 EFM8BB2 Reference Manual Programmable Counter Array 16 3 4 Edge Triggered Capture Mode In this mode a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter timer and load it into the corresponding module s 16 bit capture compare register PCAOCPLn and PCAOCPHn The CAPPn and CAPNn bits in the PCAOCPMn register are used to select the type of transition that triggers the capture low to high transition positive edge high to low transition negative edge or eithe
98. the PCONO register causes the hardware to halt the CPU and enter idle mode as soon as the instruction that sets the bit completes execution All internal registers and memory maintain their original data All analog and digital peripherals can remain active during idle mode Idle mode is terminated when an enabled interrupt is asserted or a reset occurs The assertion of an enabled interrupt will cause the IDLE bit to be cleared and the CPU to resume operation The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt RETI will be the instruction immediately following the one that set the IDLE bit If idle mode is terminated by an internal or external reset the CIP 51 performs a normal reset sequence and begins program execution at address 0x0000 Note If the instruction following the write of the IDLE bit is a single byte instruction and an interrupt occurs during the execution phase of the instruction that sets the IDLE bit the CPU may not wake from idle mode when a future interrupt occurs Therefore instructions that set the IDLE bit should be followed by an instruction that has two or more opcode bytes For example ff s OU PCONO 0x01 set IDLE bit PCONO PCONO followed by a 3 cycle dummy instruction in assembly ORL PCONO 016 set IDLE bit PCONO PCONOU 7 followed by a s cycle dummy 1ustructrion If enabled the Watchdog Timer WDT will eventually cause an
99. the data to CRCOIN one byte at a time The CRC result registers are automatically updated after each byte is written 4 Write the CRCPNT bit to 0 to target the low byte of the result 5 Read CRCODAT multiple times to access each byte of the CRC result CRCPNT will automatically point to the next value after each read 14 3 3 Using the CRC to Check Code Memory The CRC module may be configured to automatically perform a CRC on one or more blocks of code memory To perform a CRC on code contents 1 Select the initial result value using CRCVAL 2 Set the result to its initial value write 1 to CRCINIT 3 Write the high byte of the starting address to the CRCST bit field 4 Set the AUTOEN bit to 1 5 Write the number of byte blocks to perform in the CRC calculation to CRCCNT 6 Write any value to CRCOCNO or OR its contents with 0x00 to initiate the CRC calculation The CPU will not execute code additional code until the CRC operation completes Note Upon initiation of an automatic CRC calculation the three cycles following a write to CRCOCNO that initiate a CRC operation must only contain instructions which execute in the same number of cycles as the number of bytes in the instruction An example of such an instruction is a 3 byte MOV that targets the CRCOFLIP register When programming in C the dummy value written to CRCOFLIP should be a non zero value to prevent the compiler from generating a 2 byte MOV instruction 7 Clea
100. the data to be sent to SPInDAT The transfer will begin on the bus at this time 2 Wait for the SPIF flag to generate an interrupt or poll SPIF until it is set to 1 3 Read the received data from SPInDAT 4 Clear the SPIF flag to O 5 Repeat the sequence for any additional transfers Slave Transfers As a SPI slave the transfers are initiated by an external master device driving the bus Slave firmware may anticipate any output data needs by pre loading the SPInDAT register before the master begins the transfer 1 Write any data to be sent to SPInDAT The transfer will not begin until the external master device initiates it 2 Wait for the SPIF flag to generate an interrupt or poll SPIF until it is set to 1 3 Read the received data from SPInDAT 4 Clear the SPIF flag to O 5 Repeat the sequence for any additional transfers 17 3 6 Using the SPI FIFOs The SPI peripheral implements independent four byte FIFOs for both the transmit and receive paths The FIFOs are active in both mas ter and slave modes and a number of configuration features are available to accomodate a variety of SPI implementations Preliminary Rev 0 2 204 silabs com Smart Connected Energy friendly EFM8BB2 Reference Manual Serial Peripheral Interface SPIO FIFO Data Interface Writing and reading the FIFOs is straightforward and similar to the procedure outlined in 17 3 5 Basic Data Transfer All FIFO writes and reads are performed thro
101. the end of each byte For READ operations the slave transmits the data waiting for an ACK from the master at the end of each byte At the end of the data transfer the master gener ates a STOP condition to terminate the transaction and free the bus Figure 15 3 I2C Transaction on page 160 illustrates a typical I2C transaction VIXI DXX T bit Address 8 bit Data NACK START Address Data Phase STOP Time Figure 15 3 12 Transaction Transmitter vs Receiver On the I2C communications interface a device is the transmitter when it is sending an address or data byte to another device on the bus A device is a receiver when an address or data byte is being sent to it from another device on the bus The transmitter controls the SDA line during the address or data byte After each byte of address or data information is sent by the transmitter the receiver sends an ACK or NACK bit during the ACK phase of the transfer during which time the receiver controls the SDA line silabs com Smart Connected Energy friendly Preliminary Rev 0 2 160 EFM8BB2 Reference Manual 2 Slave I2CSLAVEO Arbitration A master may start a transfer only if the bus is free The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time see In the event that two or more devices attempt to begin a transfer at the same time an arbitration scheme is employed to force one master to give up the bus
102. the external data memory space XRAM Addresses in XRAM area accessed using the external move MOVX instructions Note The 16 bit MOVX write instruction is also used for writing and erasing the flash memory More details may be found in the flash memory section silabs com Smart Connected Energy friendly Preliminary Rev 0 2 9 8 2 Reference Manual Memory Organization 2 4 Memory Map OxFFFF Memory Lock OxFFFF Read Only 64 Bytes OxFFCO 64 Bytes OxFFBF OxFFDO OxFFCF ee x Code Security Page 64 Bytes OxFBFE Code Security Nonvolatile Data 64 Bytes 960 Bytes OxFBCO 15 x 64 Byte Pages OxF800 OxFBBF NV Data Lock Byte OxF7FF OxFBBE EIS 0x4000 Rede Ox3FFF OxFB80 64 Bytes id 16 KB Code Nonvolatile Data 32 x 512 Byte pages 14 x 64 Byte Pages OxF800 0x0000 Figure 2 1 Flash Memory Map 16 KB Devices silabs com Smart Connected Energy friendly Preliminary Rev 0 2 10 EFM8BB2 Reference Manual Memory Organization OxFFFF Memory Lock OxFFFF Read Only OxFFFE 64 Bytes Read Only OxFFCO 64 Bytes OxFFBF OxFFDO Reserved x _OxFFCO Code Security Page 64 Bytes m OxFBCO OxFBFE Code Security Page 4 Nonvolatile Data 64 Bytes p 960 Bytes 7 15 x 64 Byte Pages OxF800 OxFBBF OxF7FF OxFBBE 9717 Page Reserved OxFB80 64 Bytes OxFB7F 0x2000 1 latile Dat eu
103. the high byte of the 16 bit Timer 4 In 8 bit mode TMR4H contains the 8 bit high byte timer value silabs com Smart Connected Energy friendly Preliminary Rev 0 2 263 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 19 4 25 0 Timer 4 Control 0 Bit 7 6 5 4 3 2 1 TF4H TF4L TF4LEN TF4CEN T4SPLIT TR4 T4XCLK Access RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x10 SFR Address 0x98 bit addressable Bit Reset Access Description 7 TF4H 0 RW Timer 4 High Byte Overflow Flag Set by hardware when the Timer 4 high byte overflows from OxFF to 0x00 In 16 bit mode this will occur when Timer 4 overflows from OxFFFF to 0x0000 When the Timer 4 interrupt is enabled setting this bit causes the CPU to vector to the Timer 4 interrupt service routine This bit must be cleared by firmware 6 TF4L 0 RW Timer 4 Low Byte Overflow Flag Set by hardware when the Timer 4 low byte overflows from OxFF to 0x00 TF4L will be set when the low byte overflows regardless of the Timer 4 mode This bit must be cleared by firmware 5 TFALEN 0 RW Timer 4 Low Byte Interrupt Enable When set to 1 this bit enables Timer 4 Low Byte interrupts If Timer 4 interrupts are also enabled an interrupt will be gen erated when the low byte of Timer 4 overflows 4 TFACEN 0 RW Timer 4 Capture Enable When set to 1 this bit enables Time
104. the slave The transfer is ended when the STO bit is set and a STOP is generated The interface will switch to Master Receiver Mode if SMBODAT is not written following a Master Transmitter interrupt Figure 18 5 Typical Master Write Sequence on page 226 shows a typical master write sequence as it appears on the bus and Figure 18 6 Master Write Sequence State Diagram EHACK 1 on page 227 shows the corresponding firmware state machine Two transmit data bytes are shown though any number of bytes may be transmitted Notice that all of the data byte transferred interrupts occur after the ACK cycle in this mode regardless of whether hardware ACK generation is enabled Interrupts with Hardware Enabled EHACK 1 Data Byte Data Byte Interrupts with Hardware ACK Disabled 0 Received by SMBus S START Interface P STOP Transmitted by W WRITE SMBus Interface SLA Slave Address Figure 18 5 Typical Master Write Sequence silabs com Smart Connected Energy friendly Preliminary Rev 0 2 226 EFM8BB2 Reference Manual System Management Bus I2C SMBO Interrupt STA sent 1 Clear the STA and STO flags 2 Write SMBODAT with the slave address and R W bit set to 1 3 Clear the interrupt flag 51 Interrupt Send Repeated Start More Data to Send 1 Set the STO 1 Set the STA flag flag 2 Clear the 2 Clear th
105. to the low byte of the corresponding PCA channel s auto reload value for 9 to 11 bit PWM mode The ARSEL bit in register PCAOPWM controls which register is accessed A write to this register will clear the module s ECOM bit to a 0 16 4 14 1 Channel 1 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 1 Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address Bit Reset Access Description 7 0 PCAOCPH 0x00 RW PCA Channel 1 Capture Module High Byte 1 The PCAOCPH 1 register holds the high byte MSB of the 16 bit capture module This register address also allows access to the high byte of the corresponding PCA channel s auto reload value for 9 to 11 bit PWM mode The ARSEL bit in register PCAOPWM controls which register is accessed A write to this register will set the module s ECOM bit to a 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 197 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 4 15 2 Channel 2 Capture Compare Mode Bit 7 6 5 4 3 2 1 0 16 TOG PWM ECCF Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 0x10 SFR Address OXDC Bit Reset Access Description 7 16 0 RW Channel 2 16 bit Pulse Width Modulation
106. to adjust the duty cycle using the high byte of the PCAOCPn register register PCAOCPHn This allows seamless updating of the PWM waveform as PCAOCPLn is reloaded auto matically with the value stored in PCAOCPHn during the overflow edge in edge aligned mode or the up edge in center aligned mode Setting the ECOMn and PWMn bits the register and setting the CLSEL bits in register PCAOPWM to 00b enables 8 Bit pulse width modulator mode If the MATn bit is set to 1 the CCFn flag for the module is set each time a match edge or up edge occurs The COVF flag in PCAOPWM can be used to detect the overflow falling edge which occurs every 256 clock cycles 9 to 11 bit Pulse Width Modulator Mode In 9 to 11 bit PWM mode the duty cycle is determined by the value of the least significant N bits of the PCAOCPn register where N is the selected PWM resolution To adjust the duty cycle PCAOCPn should not normally be written directly Instead the recommendation is to adjust the duty cycle by writing to an Auto Reload register which is dual mapped into the and PCAOCPLn register locations The data written to define the duty cycle should be right justified in the registers The auto reload registers are accessed read or written when the bit AR SEL in PCAOPWM is set to 1 The capture compare registers are accessed when ARSEL is set to 0 This allows seamless updating of the PWM waveform as the PCAOCPn register
107. 0 Slave SCL Yes Low Timeout PCAO Clock Yes ADCO Conversion Yes Yes Yes Yes Yes Yes Yes Start T2 Input Capture Yes Yes Yes Pin LFOSCO Capture Yes Yes Yes Comparator 0 Out Yes Yes Yes put Capture Notes 1 The high side overflow is used when the timer is in 16 bit mode The low side overflow is used 8 bit mode 19 3 2 Timer 0 and Timer 1 Timer 0 and Timer 1 are each implemented as a 16 bit register accessed as two separate bytes a low byte TLO or TL1 and a high byte THO or TH1 The Counter Timer Control register TCON is used to enable Timer 0 and Timer 1 as well as indicate status Timer 0 interrupts can be enabled by setting the bit in the IE register Timer 1 interrupts can be enabled by setting the 1 bit in the IE register Both counter timers operate in one of four primary modes selected by setting the Mode Select bits T1M1 TOMO in the Counter Timer Mode register TMOD Each timer can be configured independently for the supported operating modes silabs com Smart Connected Energy friendly Preliminary Rev 0 2 242 EFM8BB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 and Timer4 19 3 2 1 Operational Modes Mode 0 13 bit Counter Timer Timer 0 and Timer 1 operate as 13 bit counter timers in Mode 0 The following describes the configuration and operation of Timer 0 However both timers operate identically
108. 0 Timing and Pin Control Bit 7 6 5 4 3 2 1 0 SWAP Reserved SDD Access RW R RW Reset 0 0x00 SFR Page 0x0 0x20 SFR Address OxAC Bit Reset Access Description 7 SWAP 0 RW SMBus Swap Pins This bit swaps the order of the SMBus pins on the crossbar Value Name Description 0 SDA_LOW_PIN SDA is mapped to the lower numbered port pin and SCL is mapped to the high er numbered port pin 1 SDA_HIGH_PIN SCL is mapped to the lower numbered port pin and SDA is mapped to the high er numbered port pin 6 2 Reserved Must write reset value 1 0 SDD 0 0 RW SMBus Start Detection Window These bits increase the hold time requirement between SDA falling and SCL falling for START detection Value Name Description 0 0 No additional hold time window 0 1 SYSCLK 0 1 ADD 2 SYSCLKS Increase hold time window to 2 3 SYSCLKs 0x2 ADD 4 SYSCLKS Increase hold time window to 4 5 SYSCLKs 0 3 ADD 8 SYSCLKS Increase hold time window to 8 9 SYSCLKs silabs com Smart Connected Energy friendly Preliminary Rev 0 2 234 EFM8BB2 Reference Manual System Management Bus I2C SMBO 18 4 3 SMBOCNO SMBus 0 Control Bit 7 6 5 4 3 2 1 0 MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI Access R R RW RW R R RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 0x20 SFR
109. 1 0 THPOL TXHOLD SPIFEN RFRQ Reserved RXTOE RXFIFOE Access R RW RW RW R R RW RW Reset 1 1 0 1 0 0 0 1 SFR Page 7 0x20 SFR Address Ox9B Bit Reset Access Description 7 TFRQ 1 R Transmit FIFO Request Set to 1 by hardware when the number of bytes in the TX FIFO is less than or equal to the TX FIFO threshold TXTH Value Name Description 0 NOT_SET The number of bytes in the TX FIFO is greater than TXTH 1 SET The number of bytes in the TX FIFO is less than or equal to TXTH 6 THPOL 1 RW Transmit Hold Polarity Selects the polarity of the data out signal when TXHOLD is active Value Name Description 0 HOLD 0 Data output will be held at logic low when TXHOLD is set 1 HOLD 1 Data output will be held at logic high when TXHOLD is set 5 TXHOLD 0 RW Transmit Hold This bit allows firmware to stall transmission of bytes from the TX FIFO until cleared When set the SPI will complete any byte transmission in progress but any new transfers will be OxFF and not pull data from the TX FIFO Bytes will continue to be pulled from the TX FIFO when the TXHOLD bit is cleared Value Name Description 0 CONTINUE The UART will continue to transmit any available data in the TX FIFO 1 HOLD The UART will not transmit any new data from the TX FIFO 4 SPIFEN 1 RW SPIF Interrupt Enable When set to 1 a SPIO interrupt will be generated any time SPIF is setto 1 Value Name Description 0 DISABLED SPIO interrupts will not be generated when SPIF is se
110. 1 0 CPLOUT CPINV CPRIE CPFIE INSL CPMD Access RW RW RW RW RW RW Reset 0 0 0 0 0x0 0x2 SFR Page 0x0 0x10 SFR Address OxAB Bit Reset Access Description 7 CPLOUT 0 RW Comparator Latched Output Flag This bit represents the comparator output value at the most recent PCA counter overflow Value Name Description 0 LOW Comparator output was logic low at last PCA overflow 1 HIGH Comparator output was logic high at last PCA overflow 6 CPINV 0 RW Output Inversion This bit inverts the polarity of the comparator output when set Value Name Description 0 NORMAL Output is not inverted 1 INVERT Output is inverted 5 CPRIE 0 RW Comparator Rising Edge Interrupt Enable Value Name Description 0 RISE_INT_DISABLED Comparator rising edge interrupt disabled 1 RISE INT ENABLED Comparator rising edge interrupt enabled 4 CPFIE 0 RW Comparator Falling Edge Interrupt Enable Value Name Description 0 FALL INT DISABLED Comparator falling edge interrupt disabled 1 FALL INT ENABLED Comparator falling edge interrupt enabled 3 2 INSL 0 0 RW Comparator Input Selection These bits control how the comparator input pins and CMP are connected internally Value Name Description 0x0 CMXN Connect the comparator inputs directly to the signals selected in the CMP1MX register is selected by CMXP and CMP is selected by CMXN The inter nal DAC is not active Ox1 CMXP GND Connect the input to the signal selected by CMXP a
111. 1 0 SMODE Reserved MCE REN TB8 RB8 TI RI Access RW R RW RW RW R RW R Reset 0 1 0 0 0 Varies 0 0 SFR Page 0x0 0x20 SFR Address 0x98 bit addressable Bit Reset Access Description 7 SMODE 0 RW Serial Port 0 Operation Mode Selects the UARTO Operation Mode Value Name Description 0 8 BIT 8 bit with Variable Baud Rate Mode 0 1 9 BIT 9 bit with Variable Baud Rate Mode 1 6 Reserved Must write reset value 5 MCE 0 RW Multiprocessor Communication Enable This bit enables checking of the stop bit or the 9th bit in multi drop communication buses The function of this bit is depend ent on the UARTO operation mode selected by the SMODE bit In Mode 0 8 bits the peripheral will check that the stop bit is logic 1 In Mode 1 9 bits the peripheral will check for a logic 1 on the 9th bit Value Name Description 0 MULTI DISABLED Ignore level of 9th bit Stop bit 1 MULTI ENABLED RI is set and an interrupt is generated only when the stop bit is logic 1 Mode 0 or when the 9th bit is logic 1 Mode 1 4 REN 0 RW Receive Enable This bit enables disables the UART receiver When disabled bytes can still be read from the receive FIFO but the receiver will not place new data into the FIFO Value Name Description 0 RECEIVE DISABLED UARTO reception disabled 1 RECEIVE ENABLED UARTO reception enabled 3 TB8 0 RW Ninth Transmission Bit The logic level of thi
112. 1 ENABLED Enable the extra bit silabs com Smart Connected Energy friendly Preliminary Rev 0 2 278 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 Bit Reset Access Description 0 SBL 0 RW Stop Bit Length Value Name Description 0 SHORT Short Stop bit is active for one bit time 1 LONG Long Stop bit is active for two bit times data length 6 7 or 8 bits or 1 5 bit times data length 5 bits 21 4 3 SBUF1 UART1 Serial Port Data Buffer Bit 7 6 5 4 3 2 1 0 SBUF1 Access RW Reset Varies SFR Page 0x20 SFR Address 0x92 Bit Reset Access Description 7 0 SBUF1 Varies RW Serial Port Data Buffer This SFR accesses the transmit and receive FIFOs When data is written to SBUF1 and TXNF is 1 the data is placed into the transmit FIFO and is held for serial transmission Any data in the TX FIFO will initiate a transmission Writing to SBUF1 while TXNF is 0 will over write the most recent byte in the TX FIFO A read of 1 returns the oldest byte in the RX FIFO Reading SBUF1 when RI is 0 will continue to return the last avail able data byte in the RX FIFO silabs com Smart Connected Energy friendly Preliminary Rev 0 2 279 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 4 4 SBCON1 UART1 Baud Rate Generator Control
113. 13 ADCOP13 P1 5 P1 5 P1 5 01110 ADCO 14 ADCOP14 P1 6 P1 6 P1 6 01111 ADCO 15 ADCOP15 P1 7 P1 7 Reserved 10000 ADCO 16 TEMP Internal Temperature Sensor 10001 ADCO 17 LDO OUT Internal 1 8 V LDO Output 10010 ADCO 18 VDD VDD Supply Pin 10011 ADCO 19 GND GND Supply Pin 10100 ADCO 20 ADCOP20 P2 0 P2 0 Reserved silabs com Smart Connected Energy friendly Preliminary Rev 0 2 113 EFM8BB2 Reference Manual Analog to Digital Converter ADCO setting Signal Name Enumeration Name QFN28 Pin QSOP24 Pin QFN20 Pin Name Name Name 10101 ADCO 21 ADCOP21 P2 1 P2 1 Reserved 10110 ADCO 22 ADCOP22 P2 2 P2 2 Reserved 10111 ADCO 23 ADCOP23 P2 3 P2 3 Reserved 11000 11110 ADCO 24 ADCO 30 Reserved Reserved Reserved 11111 ADCO 31 NONE No connection 12 3 4 Gain Setting The ADC has settings of 1x and 0 5 In 1x mode the full scale reading of the ADC is determined directly by VREF In 0 5x mode the full scale reading of the ADC occurs when the input voltage is VREF x 2 The 0 5x gain setting can be useful to obtain a higher input voltage range when using a small VREF voltage or to measure input voltages that are between VREF and the supply voltage Gain settings for the ADC are controlled by the ADGN bit in register ADCOCF Note that even with a gain setting of 0 5 voltages above the supply rail cannot be measured directly by the ADC 12 3 5 Initiating Conversions A co
114. 1FF will be accessed by 8 bit MOVX instructions silabs com Smart Connected Energy friendly Preliminary Rev 0 2 12 EFM8BB2 Reference Manual Special Function Registers 3 Special Function Registers 3 1 Special Function Register Access The direct access data memory locations from 0x80 to OxFF constitute the special function registers SFRs The SFRs provide control and data exchange with the CIP 51 s resources and peripherals The CIP 51 duplicates the SFRs found in a typical 8051 implementa tion as well as implementing additional SFRs used to configure and access the sub systems unique to the MCU This allows the addi tion of new functionality while retaining compatibility with the MCS 51 instruction set The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to OxFF SFRs with addresses ending 0x0 or 0x8 e g TCON SCONO IE etc are bit addressable as well as byte addressable All other SFRs are byte addressable only Unoccupied addresses in the SFR space are reserved for future use Accessing these areas will have an indeterminate effect and should be avoided SFR Paging CIP 51 features SFR paging allowing the device to map many SFRs into the 0x80 to OxFF memory address space The SFR memory space has 256 pages In this way each memory location from 0x80 to OxFF can access up to 256 SFRs The EFM8BB2 devices utilize multiple SFR pages All
115. 2 EFM8BB2 Reference Manual Analog to Digital Converter ADCO Comparison Register Settings ADCOGTH L 0x0040 Output Code ADCOH L 0x0040 0x003F 0x0000 ADWINT Effects ADWINT Not Affected Table 12 10 ADC Window Comparator Example Outside the 0x0040 to 0x0080 range Comparison Register Settings Output Code ADCOH L Ox03FF 0x0081 ADWINT Effects ADWINT 1 ADCOGTH L 0x0080 0x0080 0x007F 0x0041 ADCOLTH L 0x0040 0x0040 ADWINT Not Affected 0x003F 0x0000 ADWINT 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 123 EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 3 13 Temperature Sensor An on chip analog temperature sensor is available to the ADC multiplexer input To use the ADC to measure the temperature sensor the ADC mux channel should select the temperature sensor The temperature sensor transfer function is shown in Figure 12 6 Temper ature Sensor Transfer Function on page 124 The output voltage is the positive ADC input when the ADC multiplexer is set correctly The TEMPE bit in register REFOCN enables disables the temperature sensor While disabled the temperature sensor de faults to a high impedance state and any ADC measurements performed on the sensor will result in meaningless data Refer to the electrical specification tables for the slo
116. 2 1 RXTO This field defines the length of the timeout on the RX FIFO If the RX FIFO is not empty but the number of bytes the FIFO is not enough to generate a Receive FIFO request an RFRQ interrupt will be generated after the specified number of idle frames An idle frame is defined as the length of a single transfer on the bus For example with a typical 8 N 1 configura tion there are 8 data bits 1 start bit and 1 stop bit per transfer An idle frame with this configuration is 10 bit times at the selected baud rate Description 0 0 RW Receive Timeout Value Name Description 0x0 DISABLED The receive timeout feature is disabled 0 1 TIMEOUT 2 A receive timeout will occur after 2 idle periods on the UART RX line 0x2 TIMEOUT 4 A receive timeout will occur after 4 idle periods on the UART RX line 0x3 TIMEOUT_16 A receive timeout will occur after 16 idle periods on the UART RX line 0 RIE 1 RW Receive Interrupt Enable This bit enables the RI flag to generate UART1 interrupts when there is information available in the receive FIFO regard less of the RXTH settings Value Name Description 0 DISABLED The RI flag will not generate UART1 interrupts 1 ENABLED The RI flag will generate UART1 interrupts when it is set 21 4 9 UART1FCT UART1 FIFO Count Bit 7 6 3 1 Reserved TXCNT Reserved RXCNT Access R R R R Reset 0 0x0 0 0 0 SFR Page 0x20 SFR Add
117. 3 SYSCLK_DIV_8 SYSCLK is equal to selected clock source divided by 8 0 4 SYSCLK DIV 16 SYSCLK is equal to selected clock source divided by 16 0x5 SYSCLK DIV 32 SYSCLK is equal to selected clock source divided by 32 0x6 SYSCLK DIV 64 SYSCLK is equal to selected clock source divided by 64 0 7 SYSCLK DIV 128 SYSCLK is equal to selected clock source divided by 128 3 Reserved Must write reset value 2 0 CLKSL 0 0 RW Clock Source Select Selects the system clock source Value Name Description 0x0 HFOSCO Clock derived from the Internal High Frequency 0 0 1 EXTOSC Clock derived from the External Oscillator circuit 0x2 LFOSC Clock derived from the Internal Low Frequency Oscillator 0x3 HFOSC1 Clock derived from the Internal High Frequency Oscillator 1 0 4 HFOSCO DIV 1P5 Clock derived from the Internal High Frequency Oscillator 0 pre scaled by 1 5 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 56 EFM8BB2 Reference Manual Clocking and Oscillators Bit Name Reset Access Description 0 7 HFOSC1 DIV 1P5 Clock derived from the Internal High Frequency Oscillator 1 pre scaled by 1 5 This device family has restrictions when switching to clock sources that are greater than 25 MHz SYSCLK must be running at a fre quency of 24 MHz or greater before switching the CLKSL field to HFOSC1 When transitioning from slower clock frequencies firm ware should make two writes to CLKSEL
118. 300 ns respectively Setup and hold time exten sions are typically necessary for SMBus compliance when SYSCLK is above 10 MHz Table 18 1 Minimum SDA Setup and Hold Times EXTHOLD Minimum SDA Setup Time Minimum SDA Hold Time 0 Tiow 4 system clocks or 1 system clock 3 system clocks s w delay 1 11 system clocks 12 system clocks Note Setup Time for ACK bit transmissions and the MSB of all data transfers When using software acknowl edgment the s w delay occurs between the time SMBODAT or ACK is written and when SI is cleared Note that if 1 is cleared in the same write that defines the outgoing ACK value s w delay is zero With the SMBTOE bit set Timer 3 should be configured to overflow after 25 ms in order to detect SCL low timeouts The SMBus inter face will force the associated timer to reload while SCL is high and allow the timer to count when SCL is low The timer interrupt serv ice routine should be used to reset SMBus communication by disabling and re enabling the SMBus SMBus Free Timeout detection can be enabled by setting the SMBFTE bit When this bit is set the bus will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods SMBus Pin Swap The SMBus peripheral is assigned to pins using the priority crossbar decoder By default the SMBus signals are assigned to port pins starting with SDA on the lower numbered pin and SCL on the next available pin The SWAP bit
119. 5 2 CMP1MD 1 Mode 13 5 3 CMP1MX Comparator 1 Multiplexer 13 5 4 CMP1CN1 Comparator 1 Control 1 Cyclic Redundancy Check CRCO 14 1 Introduction 14 2 Features 14 3 Functional Description 14 3 1 16 bit CRC Algorithm 14 3 2 Using the on Data Stream 14 3 3 Using the CRC to Check Code Memory 14 3 4 Bit Reversal 14 4 CRCO Control Registers 14 4 1 CRCOCNO CRCO Control 0 14 4 2 CRCOIN CRCO Data Input 14 4 3 CRCODAT CRCO Data Output 14 4 4 CRCOST CRCO Automatic Flash Sector Stat 14 4 5 CRCOCNT CRCO Automatic Flash Sector Count 14 4 6 CRCOFLIP CRCO Bit Flip 14 4 7 CRCOCN1 CRCO Control 1 I2C Slave I2CSLAVEO 15 1 Introduction 15 2 Features 15 3 Functional Description 15 3 1 Overview 15 3 2 12 Protocol 15 3 3 Operational Modes 15 3 4 Status Decoding 15 4 2 0 Slave Control Registers 15 4 1 I2CODIN 2 0 Received Data 15 4 2 I2CODOUT 12 0 Transmit Data 15 4 3 I2COSLAD 12 0 Slave Address 15 4 4 I2COSTAT I2CO Status 15 4 5 I2COCNO 2 0 Control 15 4 6 I2COFCNO 2 0 FIFO Control 0 15 4 7 I2COFCN1 I2CO FIFO Control 1 15 4 8 I2COFCT 12 0 FIFO Count Programmable Counter Array 0 16 1 Introduction 16 2 Features 16 3 Functional Description 16 3 1 Counter Timer 16 3 2 Interrupt Sources 16 3 3 Capture Compare Modules 16 3 3 1 Output Polarity Table of Contents 149 150 151 152 152 152 153
120. 6 5 0 DPL Access RW Reset 0x00 SFR Page ALL SFR Address 0x82 Bit Reset Access Description 7 0 DPL 0x00 RW Data Pointer Low The DPL register is the low byte of the 16 bit DPTR DPTR is used to access indirectly addressed flash memory or XRAM 10 4 2 DPH Data Pointer High Bit 7 6 5 Access RW Reset 0x00 SFR Page ALL SFR Address 0x83 Bit Name Reset Access Description 7 0 DPH 0x00 RW Data Pointer High The DPH register is the high byte of the 16 bit DPTR DPTR is used to access indirectly addressed flash memory or XRAM 10 4 3 SP Stack Pointer Bit 7 6 5 0 SP Access RW Reset 0x07 SFR Page ALL SFR Address 0x81 Bit Reset Access Description 7 0 SP 0x07 RW Stack Pointer The Stack Pointer holds the location of the top of the stack The stack pointer is incremented before every PUSH operation The SP register defaults to 0x07 after reset silabs com Smart Connected Energy friendly Preliminary Rev 0 2 73 EFM8BB2 Reference Manual CIP 51 Microcontroller Core 10 4 4 ACC Accumulator Bit 7 6 5 4 3 1 0 Access RW Reset 0x00 SFR Page ALL SFR Address OxEO bit addressable Bit Reset Access Description 7 0 ACC 0x00 RW Accumulator This register is the accumulator for arithmetic operations 10 4 5 B B
121. 7 3 2 1 0 Reserved B3 B2 B1 BO Access R RW RW RW RW Reset 0 0 1 1 1 1 SFR Page ALL SFR Address 0 bit addressable Bit Reset Access Description 7 4 Reserved Must write reset value 3 B3 1 RW Port 2 Bit 3 Latch Value Name Description 0 LOW P2 3 is low Set P2 3 to drive low 1 HIGH P2 3 is high Set P2 3 to drive or float high 2 B2 1 RW Port 2 Bit 2 Latch See bit 3 description 1 B1 1 RW Port 2 Bit 1 Latch See bit 3 description 0 BO 1 RW Port 2 Bit 0 Latch See bit 3 description Writing this register sets the port latch logic value for the associated I O pins configured as digital I O Reading this register returns the logic value at the pin regardless if it is configured as output or input silabs com Smart Connected Energy friendly Preliminary Rev 0 2 104 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 20 P2MDIN Port 2 Input Mode Bit 7 6 4 3 2 1 0 Reserved B3 B2 B1 BO Access R RW RW RW RW Reset 0 0 1 1 1 1 SFR Page 0x20 SFR Address OxF3 Bit Reset Access Description 7 4 Reserved Must write reset value 3 B3 1 RW Port 2 Bit 3 Input Mode Value Name Description 0 ANALOG P2 3 pin is configured for analog mode 1 DIGITAL P2 3 pin is configured for digital mode 2 B2 1 RW Port 2 Bit 2 Input Mode See bit 3 de
122. 7 6 5 4 3 2 1 0 ADCOLTH Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address 0xC6 Bit Reset Access Description 7 0 ADCOLTH 0x00 RW Less Than High Byte Most significant byte of the 16 bit less than window compare register 12 4 12 ADCOLTL ADCO Less Than Low Byte Bit 7 6 5 4 3 2 1 0 ADCOLTL Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address 0xC5 Bit Name Reset Access Description 7 0 ADCOLTL 0x00 RW Less Than Low Byte Least significant byte of the 16 bit less than window compare register In 8 bit mode this register should be set to 0 00 12 4 13 ADCOMX ADCO Multiplexer Selection Bit 7 6 5 4 3 2 1 0 Reserved ADCOMX Access R RW Reset 0 0 1 SFR Page 0x0 0x10 SFR Address Bit Name Reset Description 7 5 Reserved Must write reset value 4 0 ADCOMX Ox1F RW AMUXO Positive Input Selection Selects the positive input channel for ADCO For reserved bit combinations no input is selected silabs com Smart Connected Energy friendly Preliminary Rev 0 2 132 EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 4 14 REFOCN Voltage Reference Control Bit 7 6 5 2 1 0 IREFLVL Reserved GNDSL REFSL TEMPE Reserved Access RW R RW RW RW R Reset 0 0 0 0x3 0 0 0 SFR Page 0x0 0x10 SFR Address OxD1 Bit Name Reset Access Des
123. CMP1P11 P2 2 P2 2 Reserved 1100 CMP1P 12 CMP1P12 P2 3 P2 3 Reserved 1101 1110 CMP1P 13 CMP1P 14 No connection Reserved 1111 CMP1P 15 VDD VDD Supply Pin Table 13 4 CMP1 Negative Input Multiplexer Channels CMXN Setting in Signal Name Enumeration Name QFN28 Pin QSOP24 Pin QFN20 Pin Register Name Name Name CMP1MX 0000 1 0 CMP1NO P1 0 P1 0 P1 0 0001 CMP1N 1 CMP1N1 P1 1 1 1 1 1 0010 CMP1N 2 CMP1N2 P1 2 P1 2 P1 2 0011 CMP1N 3 CMP1N3 P1 3 P1 3 P1 3 0100 CMP1N 4 1 4 1 4 1 4 1 4 0101 1 5 1 5 1 5 1 5 1 5 0110 1 6 1 6 1 6 1 6 1 6 0111 1 7 CMP1N7 P1 7 P1 7 Reserved 1000 CMP1N 8 GND GND Supply Pin 1001 CMP1N 9 CMP1N9 P2 0 P2 0 Reserved 1010 CMP1N 10 CMP1N10 P2 1 P2 1 Reserved 1011 CMP1N 11 CMP1N11 P2 2 P2 2 Reserved 1100 CMP1N 12 CMP1N12 P2 3 P2 3 Reserved 1101 1110 CMP1N 13 CMP1N 14 No connection Reserved 1111 CMP1N 15 VDD VDD Supply Pin silabs com Smart Connected Energy friendly Preliminary Rev 0 2 137 EFM8BB2 Reference Manual Comparators and CMP1 13 3 3 2 Reference DAC The comparator module includes a dedicated reference DAC which can be inserted between the selected mux channel and the com parator on either the positive or negative inputs The INSL field in the CMPnMD register determines the connections between the selec ted mux inputs the
124. D 0 for n XBARE Crossbar 1 j WEAK Enable 52 PORT Px x Output ZN PAD Logic Value Port Latch or Crossbar PxMDIN x NI ND 1 for digital 0 for analog To From Analog Peripheral Px x Input Logic Value Reads 0 when is configured as an analog I O Lo Se Figure 11 2 Port I O Cell Block Diagram Configuring Port Pins For Analog Modes Any pins to be used for analog functions should be configured for analog mode When a pin is configured for analog I O its weak pull up digital driver and digital receiver are disabled This saves power by eliminating crowbar current and reduces noise on the analog input Pins configured as digital inputs may still be used by analog peripherals however this practice is not recommended Port pins configured for analog functions will always read back a value of 0 in the corresponding Pn Port Latch register To configure a pin as analog the following steps should be taken 1 Clear the bit associated with the pin in the PnMDIN register to 0 This selects analog mode for the pin 2 Set the bit associated with the pin in the Pn register to 1 3 Skip the bit associated with the pin in the PnSKIP register to ensure the crossbar does not attempt to assign a function to the pin silabs com Smart Connected Energy friendly Preliminary Rev 0 2 78 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match Configuring Port Pins For
125. Description 7 3 ADSC Ox1F RW SAR Clock Divider This field sets the ADC clock divider value It should be configured to be as close to the maximum SAR clock speed as the datasheet will allow The SAR clock frequency is given by the following equation Fadcclk ADSC 1 is equal to the selected SYSCLK when ADBMEN is 0 and the high frequency oscillator when ADBMEN is 1 2 AD8BE 0 RW 8 Bit Mode Enable Value Name Description 0 NORMAL ADCO operates in 10 bit or 12 bit mode normal operation 1 8 BIT ADCO operates in 8 bit mode 1 ADTM 0 RW Track Mode Selects between Normal or Delayed Tracking Modes Value Name Description 0 TRACK NORMAL Normal Track Mode When ADCO is enabled conversion begins immediately fol lowing the start of conversion signal 1 TRACK DELAYED Delayed Track Mode When ADCO is enabled conversion begins 4 SAR clock cy cles following the start of conversion signal The ADC is allowed to track during this time 0 ADGN 0 RW Gain Control Value Name Description 0 GAIN 5 The on chip PGA gain is 0 5 1 GAIN 1 The on chip gain is 1 Preliminary Rev 0 2 127 silabs com Smart Connected Energy friendly EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 4 4 ADCOAC ADCO Accumulator Configuration Bit 7 6 4 1 AD12BE ADAE ADSJS
126. Description 0 0 ZERO TFRQ will be set when the TX FIFO is empty 3 RFRQE 0 RW Read Request Interrupt Enable When set to 1 an SMBus 0 interrupt will be generated any time RFRQ is logic 1 Value Name Description 0 DISABLED SMBus 0 interrupts will not be generated when RFRQ is set 1 ENABLED SMBus 0 interrupts will be generated if RFRQ is set 2 RFLSH 0 RW RX FIFO Flush This bit flushes the RX FIFO When firmware sets this bit to 1 the internal FIFO counters will be reset and any remaining data will be lost Hardware will clear the RFLSH bit back to 0 when the operation is complete 1 SYSCLK cycle 1 0 RXTH 0x0 RW RX FIFO Threshold This field configures when hardware will set the receive FIFO request bit RFRQ RFRQ is set whenever the number of bytes in the RX FIFO exceeds the value in RXTH Value Name Description 0 0 RFRQ will be set anytime new data arrives in the RX FIFO when the RX FIFO is not empty silabs com Smart Connected Energy friendly Preliminary Rev 0 2 238 EFM8BB2 Reference Manual System Management Bus I2C SMBO 18 4 8 SMBOFCN1 SMBus 0 FIFO Control 1 Bit 7 6 3 2 1 Name TFRQ TXNF Reserved RFRQ RXE Reserved Access R R R R R R Reset 1 1 0 0 0 1 0 0 SFR Page 0x20 SFR Address 0 4 Bit Name Reset Access Description 7 TFRQ 1 R Transmit FIFO Request Set to 1 by hardware w
127. Digital Modes Any pins to be used by digital peripherals or GPIO should be configured as digital PnMDIN n 1 For digital I O pins one of two output modes push pull or open drain must be selected using the PhMDOUT registers Push pull outputs PnMDOUT n 1 drive the port pad to the supply rails based on the output logic value of the port pin Open drain outputs have the high side driver disabled therefore they only drive the port pad to the lowside rail when the output logic value is 0 and become high impedance inputs both high low drivers turned off when the output logic value is 1 When a digital I O cell is placed in the high impedance state a weak pull up transistor pulls the port pad to the high side rail to ensure the digital input is at a defined logic state Weak pull ups are disabled when the cell is driven low to minimize power consumption and they be globally disabled by setting WEAKPUD to 1 The user should ensure that digital are always internally or externally pulled or driven to a valid logic state to minimize power consumption Port pins configured for digital always read back the logic state of the port pad regardless of the output logic value of the port pin To configure a pin as a digital input 1 Set the bit associated with the pin in the PnMDIN register to 1 This selects digital mode for the pin 2 lear the bit associated with the pin in the PhMDOUT register to 0 This configures the
128. EL bit in register PCAOPWM controls which register is accessed A write to this register will set the module s ECOM bit to a 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 199 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO 17 Serial Peripheral Interface SPIO 17 1 Introduction The serial peripheral interface SPI module provides access to a flexible full duplex synchronous serial bus The SPI can operate as a master or slave device in both 3 wire or 4 wire modes and supports multiple masters and slaves on a single SPI bus The slave select NSS signal can be configured as an input to select the SPI in slave mode or to disable master mode operation in a multi master environment avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers NSS can also be configured as a firmware controlled chip select output in master mode or disabled to reduce the number of pins required Additional general purpose port pins can be used to select multiple slave devices in master mode SCK Phase Master Slave SCK Polarity NSS Control FIFO Control Interrupt Selection SYSCLK Clock Rate Generator TX Buffer RX Buffer 4 bytes 4 bytes SPIODAT Figure 17 1 SPI Block Diagram 17 2 Features Supports 3 or 4 wire master slave modes Supports external clock frequencies up to 12 Mbps in master or slave mode Support
129. ENABLED ECI routed to Port pin 1 0 PCAOME 0 0 RW PCA Module I O Enable Value Name Description 0 0 DISABLED All PCA I O unavailable at Port pins 0 1 routed to Port pin 0x2 CEXO CEX1 CEXO CEX1 routed to Port pins 0x3 CEX0_CEX1_CEX2 CEXO 1 CEX2 routed to Port pins silabs com Smart Connected Energy friendly Preliminary Rev 0 2 87 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 3 XBR2 Port I O Crossbar 2 Bit 7 6 4 2 1 0 WEAKPUD XBARE Reserved URT1CTSE 1 URT1E Access RW RW R RW RW RW Reset 0 0 0 0 0 0 0 SFR Page 0x0 0x20 SFR Address OxE3 Bit Name Reset Access Description 7 WEAKPUD 0 RW Port I O Weak Pullup Disable Value Name Description 0 PULL UPS ENABLED Weak Pullups enabled except for Ports whose I O are configured for analog mode 1 PULL UPS DISABLED Weak Pullups disabled 6 XBARE 0 RW Crossbar Enable Value Name Description 0 DISABLED Crossbar disabled 1 ENABLED Crossbar enabled 5 3 Reserved Must write reset value 2 URT1CTS 0 RW UART1 CTS Input Enable E Value Name Description 0 DISABLED UART1 CTS1 unavailable at Port pin 1 ENABLED 1 CTS1 routed to Port pin 1 5 0 RW UART1 RTS Output Enable E Value Name Description 0 DISABLED UART1 RTS1 unavailable at Port pin 1 ENABLED
130. Enable This bit sets the masking of the Capture Compare Flag CCFO interrupt Value Name Description 0 DISABLED Disable CCFO interrupts 1 ENABLED Enable a Capture Compare Flag interrupt request when CCFO is set silabs com Smart Connected Energy friendly Preliminary Rev 0 2 194 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 4 10 PCAOCPLO PCA Channel 0 Capture Module Low Byte Bit 7 6 5 4 3 2 1 0 Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address OxFB Bit Reset Access Description 7 0 PCAOCPLO 0x00 RW PCA Channel 0 Capture Module Low Byte The PCAOCPLO register holds the low byte LSB of the 16 bit capture module This register address also allows access to the low byte of the corresponding PCA channel s auto reload value for 9 to 11 bit PWM mode The ARSEL bit in register PCAOPWM controls which register is accessed write to this register will clear the module s ECOM bit to a 0 16 4 11 PCA Channel 0 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address OxFC Bit Reset Access Description 7 0 PCAOCPH 0x00 RW PCA Channel 0 Capture Module High Byte 0 The PCAOCPHO register holds the high byte MSB of the 16 bit capture module This register address also allows access to the hig
131. FCNO SPIO FIFO Control 0 Bit 7 6 3 2 1 0 TFLSH TXTH RFRQE RFLSH RXTH Access RW RW RW RW RW RW Reset 0 0 0x0 0 0 0x0 SFR Page 0x20 SFR Address 0x9A Bit Reset Access Description 7 TFRQE 0 RW Write Request Interrupt Enable When set to 1 a SPIO interrupt will be generated any time TFRQ is logic 1 Value Name Description 0 DISABLED SPIO interrupts will not be generated when TFRQ is set 1 ENABLED SPIO interrupts will be generated if TFRQ is set 6 TFLSH 0 RW TX FIFO Flush This bit flushes the TX FIFO When firmware sets this bit to 1 the internal FIFO counters will be reset and any remaining data will not be sent Hardware will clear the TFLSH bit back to 0 when the operation is complete 1 SYSCLK cycle 5 4 TXTH 0x0 RW TX FIFO Threshold This field configures when hardware will set the transmit FIFO request bit TFRQ TFRQ is set whenever the number of bytes in the TX FIFO is equal to or less than the value in TXTH Value Name Description 0x0 ZERO TFRQ will be set when the TX FIFO is empty 0 1 will be set when the TX FIFO contains one or fewer bytes 0 2 TWO TFRQ will be set when the TX FIFO contains two or fewer bytes 0x3 THREE TFRQ will be set when the TX FIFO contains three or fewer bytes 3 RFRQE 0 RW Read Request Interrupt Enable When set to 1 a SPIO interrupt will be generated any time RFRQ is logic 1
132. High Byte Overflow Flag TFnH is set If the timer interrupts are enabled an interrupt is generated on each timer overflow Additionally if the timer interrupts are enabled and the TFnLEN bit is set an interrupt is generated each time the lower 8 bits TMRnL overflow from OxFF to 0x00 The overflow rate of the timer in split 16 bit auto reload mode is F F input Clock Clock TIMERn 216 TMRnRLH TMRnRLL 65536 TMRnRLH TMRnRLL TFnL Overflow TFnLEN TFnH TRn Overflow Interrupt Timer Low Clock TMRnRLL TMRnRLH Reload Figure 19 6 16 Bit Mode Block Diagram silabs com Smart Connected Energy friendly Preliminary Rev 0 2 248 EFM8BB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 and Timer4 19 3 3 2 8 bit Timers with Auto Reload Split Mode When TnSPLIT is set the timer operates as two 8 bit timers TMRnH and TMRnL Both 8 bit timers operate in auto reload mode TMRnRLL holds the reload value for TMRnL TMRnRLH holds the reload value for TMRnH The TRn bit in TMRnCN handles the run control for TMRnH TMRnL is always running when configured for 8 bit auto reload mode As shown in the clock source selection tree the two halves of the timer may be clocked from SYSCLK or by the source selected by the TnXCLK bits The overflow rate of the low timer in split 8 bit auto reload mode is F F input Clock z Finput Clock The overflow rate of the high timer in split 8 bit
133. I and into the shift register MSB first on MISO Upon completing a transfer the data received is moved from the shift register into the receive buffer If the transmit buffer is not empty the next byte in the transmit buffer will be moved into the shift register and the next data transfer will begin If no new data is available in the transmit buffer the SPI will halt and wait for new data to initiate the next transfer Bytes that have been received and stored in the receive buffer may be read from the buffer via the SPInDAT register 17 3 3 Slave Mode Operation When the SPI block is enabled and not configured as a master it will operate as a SPI slave As a slave bytes are shifted in through the MOSI pin and out through the MISO pin by an external master device controlling the SCK signal A bit counter in the SPI logic counts SCK edges When 8 bits have been shifted through the shift register a byte is copied into the receive buffer Data is read from the receive buffer by reading SPInDAT A slave device cannot initiate transfers Data to be transferred to the master device is pre loa ded into the transmit buffer by writing to SPInDAT and will transfer to the shift register on byte boundaries in the order in which they were written to the buffer When configured as a slave SPIO can be configured for 4 wire or 3 wire operation In the default 4 wire slave mode the NSS signal is routed to a port pin and configured as a digital input The SPI interfa
134. IN 0 4 4 EIP2 P3MDIN 0 5 DEVICEID OxF5 EIP1H I2COFCT 0 6 REVID OxF6 PRTDRV EIP2H PRTDRV 0 7 FLKEY OxF7 PCAOPWM SPIOFCT 0xB8 IP OxF8 SPIOCNO SPIOCNO 0 9 ADCOTK I2COSTAT OxF9 PCAOL OxBA I2COCNO OxFA PCAOH UART1FCT OxBB ADCOMX I2CODOUT OxFB PCAOCPLO P2MAT OxBC ADCOCF I2CODIN OxFC PCAOCPHO P2MASK OxBD ADCOL I2COSLAD OxFD POMAT TMR2CN1 POMAT OxBE ADCOH OxFE POMASK TMR3CN1 POMASK OxBF CMP1CNO OxFF VDMOCN TMR4CN1 Table 3 3 Special Function Registers by Name Register Address SFR Pages Description ACC OxEO ALL Accumulator silabs com Smart Connected Energy friendly Preliminary Rev 0 2 16 EFM8BB2 Reference Manual Special Function Registers Register Address SFR Pages Description ADCOAC OxB3 0x00 0x10 ADCO Accumulator Configuration ADCOCF OxBC 0x00 0x10 ADCO Configuration ADCOCNO OxE8 0x00 0x10 ADCO Control 0 ADCOCN1 0 2 0 00 0 10 ADCO Control 1 ADCOGTH 0 4 0 00 0 10 ADCO Greater Than High Byte ADCOGTL 0xC3 0x00 0x10 ADCO Greater Than Low Byte ADCOH OxBE 0x00 0x10 ADCO Data Word High Byte ADCOL OxBD 0x00 0x10 ADCO Data Word Low Byte ADCOLTH 0xC6 0x00 0x10 ADCO Less Than High Byte ADCOLTL 0xC5 0x00 0x10 ADCO Less Than Low Byte ADCOMX OxBB 0x00 0x10 ADCO Multiplexer Selection ADCOPWR OxDF 0x00 0x10 ADCO Power Control ADCO
135. LH1 SBRLL1 registers must be at least 50 i e the maximum value of SBRLH1 SBRLL1 must be 65536 50 or 65486 and OxFFCE silabs com Smart Connected Energy friendly Preliminary Rev 0 2 275 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 4 UART1 Control Registers 21 4 1 SCON1 UART1 Serial Port Control Bit 7 6 5 4 3 2 1 0 OVR PERR Reserved REN TBX RBX TI RI Access RW RW R RW RW R RW R Reset 0 0 0 0 0 Varies 0 0 SFR Page 0x20 SFR Address 0 8 bit addressable Bit Name Reset Access Description 7 OVR 0 RW Receive FIFO Overrun Flag This bit indicates a receive FIFO overrun condition where an incoming character is discarded due to a full FIFO This bit must be cleared by firmware Value Name Description 0 NOT_SET Receive FIFO overrun has not occurred 1 Receive overrun has occurred 6 PERR 0 RW Parity Error Flag When parity is enabled this bit indicates that a parity error has occurred It is set to 1 when the parity of the oldest byte in the FIFO available when reading SBUF 1 does not match the selected parity type This bit must be cleared by firmware Value Name Description 0 NOT SET Parity error has not occurred 1 SET Parity error has occurred 5 Reserved Must write reset value 4 REN 0 RW Receive Enable This bit enables disables the UART receiver When disabled bytes
136. LKEY 0x00 RW Flash Lock and Key Write This register provides a lock and key function for flash erasures and writes Flash writes and erases are enabled by writing 0xA5 followed OxF1 to the FLKEY register Flash writes and erases are automatically disabled after the next write or erase is complete If any writes to FLKEY are performed incorrectly or if a flash write or erase operation is attempted while these operations are disabled the flash will be permanently locked from writes or erasures until the next device reset If an application never writes to flash it can intentionally lock the flash by writing a non 0xA5 value to FLKEY from firmware Read When read bits 1 0 indicate the current flash lock state 00 Flash is write erase locked 01 The first key code has been written 0xA5 10 Flash is unlocked writes erases allowed 11 Flash writes erases are disabled until the next reset silabs com Smart Connected Energy friendly Preliminary Rev 0 2 30 EFM8BB2 Reference Manual Device Identification 5 Device Identification 5 1 Device Identification The SFR map includes registers that may be used to identify the device family DEVICEID derivative DERIVID and revision RE VID These SFRs can be read by firmware at runtime to determine the capabilities of the MCU that is executing code This allows the same firmware image to run on MCUs with different memory sizes and peripherals and dynamically
137. Must write reset value 1 B1 1 RW Port 3 Bit 1 Input Mode Value Name Description 0 ANALOG P3 1 pin is configured for analog mode 1 DIGITAL P3 1 pin is configured for digital mode 0 BO 1 RW Port 3 Bit 0 Input Mode See bit 1 description Port pins configured for analog mode have their weak pullup digital driver and digital receiver disabled 11 4 25 P3MDOUT Port 3 Output Mode Bit 7 6 4 3 2 1 0 Reserved B1 BO Access R RW RW Reset 0x00 0 0 SFR Page 0x20 SFR Address 0 9 Bit Reset Access Description 7 2 Reserved Must write reset value 1 B1 0 RW Port 3 Bit 1 Output Mode Value Name Description 0 OPEN DRAIN P3 1 output is open drain 1 PUSH PULL P3 1 output is push pull 0 BO 0 RW Port 3 Bit 0 Output Mode See bit 1 description silabs com Smart Connected Energy friendly Preliminary Rev 0 2 108 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 5 INTO and INT1 Control Registers 11 5 1 ITO1CF INTO INT1 Configuration Bit 7 6 5 4 3 2 1 0 IN1PL IN1SL INOPL INOSL Access RW RW RW RW Reset 0 0x0 0 Ox1 SFR Page 0x0 0x10 SFR Address OxEA Bit Name Reset Access Description 7 IN1PL 0 RW INT1 Polarity Value Name Description 0 ACTIVE LOW INT1 input is active low 1 ACTIVE HIGH INT1 input is active high 6 4 IN1SL 0x0 RW INT1 Port Pin Sele
138. Must write reset value 6 4 SFRPGIDX 0 0 RW SFR Page Stack Index This field can be used to access the SFRPAGE values stored in the SFR page stack It selects the level of the stack firm ware can access when reading the SFRSTACK register Value Name Description 0 0 FIRST BYTE SFRSTACK contains the value of SFRPAGE the first top byte of the SFR page stack Ox1 SECOND BYTE SFRSTACK contains the value of the second byte of the SFR page stack 0 2 THIRD BYTE SFRSTACK contains the value of the third byte of the SFR page stack 0x3 FOURTH_BYTE SFRSTACK contains the value of the fourth byte of the SFR page stack 0 4 SFRSTACK contains the value of the fifth byte of the SFR page stack 3 1 Reserved Must write reset value 0 SFRPGEN 1 RW SFR Automatic Page Control Enable This bit is used to enable automatic page switching on ISR entry exit When set to 1 the current SFRPAGE value will be pushed onto the SFR page stack and SFRPAGE will be set to the page corresponding to the flag which generated the in terrupt upon ISR exit hardware will pop the value from the SFR page stack and restore SFRPAGE Value Name Description 0 DISABLED Disable automatic SFR paging 1 ENABLED Enable automatic SFR paging 3 3 3 SFRSTACK SFR Page Stack Bit 7 6 5 4 3 2 1 0 SFRSTACK Access R Reset 0x00 SFR Page 0x10 SFR Address OxD7 Access Description 7 0 SFRSTAC 0x00 R
139. N 0 RW ADC Enable Value Name Description 0 DISABLED Disable ADCO low power shutdown 1 ENABLED Enable ADCO active and ready for data conversions 6 0 RW Burst Mode Enable Value Name Description 0 BURST DISABLED Disable ADCO burst mode 1 BURST ENABLED Enable ADCO burst mode 5 ADINT 0 RW Conversion Complete Interrupt Flag Set by hardware upon completion of a data conversion ADBMEN O or a burst of conversions ADBMEN 1 Can trigger an interrupt Must be cleared by firmware 4 ADBUSY 0 RW ADC Busy Writing 1 to this bit initiates an ADC conversion when ADCM 000 This bit should not be polled to indicate when a conver sion is complete Instead the ADINT bit should be used when polling for conversion completion 3 ADWINT 0 RW Set by hardware when the contents of ADCOH ADCOL fall within the window specified by ADCOGTH ADCOGTL and ADCOLTH ADCOLTL Can trigger an interrupt Must be cleared by firmware Window Compare Interrupt Flag 2 0 ADCM 0 0 RW Start of Conversion Mode Select Specifies the ADCO start of conversion source All remaining bit combinations are reserved Value Name Description 0x0 ADBUSY ADCO conversion initiated on write of 1 to ADBUSY 0 1 TIMERO ADCO conversion initiated on overflow of Timer 0 0x2 TIMER2 ADCO conversion initiated on overflow of Timer 2 0x3 ADCO conversion initiated on overflow of Timer 3 0 4 CNVSTR ADCO conversion initiated on ri
140. Name Description 0 DISABLED Disable CP1 interrupts 1 ENABLED Enable interrupt requests generated by the comparator 1 CPRIF or CPFIF flags 5 ECPO 0 RW Comparator0 Interrupt Enable This bit sets the masking of the CPO interrupt Value Name Description 0 DISABLED Disable CPO interrupts 1 ENABLED Enable interrupt requests generated by the comparator 0 CPRIF or CPFIF flags 4 0 RW Programmable Counter Array 0 Interrupt Enable This bit sets the masking of the PCAO interrupts Value Name Description 0 DISABLED Disable all PCAO interrupts 1 ENABLED Enable interrupt requests generated by PCAO 3 EADCO 0 RW ADCO Conversion Complete Interrupt Enable This bit sets the masking of the ADCO Conversion Complete interrupt Value Name Description 0 DISABLED Disable ADCO Conversion Complete interrupt 1 ENABLED Enable interrupt requests generated by the ADINT flag 2 EWADCO 0 RW ADCO Window Comparison Interrupt Enable silabs com Smart Connected Energy friendly This bit sets the masking of ADCO Window Comparison interrupt Preliminary Rev 0 2 41 EFM8BB2 Reference Manual Interrupts Bit Name Reset Access Description Value Name Description 0 DISABLED Disable ADCO Window Comparison interrupt 1 ENABLED Enable interrupt requests generated by ADCO Window Compare flag ADWINT 1 EMAT 0 RW Port Match Interrupts Enable This bit sets the masking of the Port Match Event interrupt
141. Name Description 0 NOT_SKIPPED 7 pin is not skipped by the crossbar 1 SKIPPED 7 is skipped by the crossbar 6 B6 0 RW Port 0 Bit 6 Skip See bit 7 description 5 B5 0 RW Port 0 Bit 5 Skip See bit 7 description 4 B4 0 RW Port 0 Bit 4 Skip See bit 7 description 3 B3 0 RW Port 0 Bit 3 Skip See bit 7 description 2 B2 0 RW Port 0 Bit 2 Skip See bit 7 description 1 B1 0 RW Port 0 Bit 1 Skip See bit 7 description 0 BO 0 RW Port 0 Bit 0 Skip See bit 7 description silabs com Smart Connected Energy friendly Preliminary Rev 0 2 95 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 11 P1MASK Port 1 Mask Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 0x20 SFR Address OxEE Bit Reset Access Description 7 B7 0 RW Port 1 Bit 7 Mask Value Value Name Description 0 IGNORED P1 7 pin logic value is ignored and will not cause a port mismatch event 1 COMPARED P1 7 pin logic value is compared to P1MAT 7 6 B6 0 RW Port 1 Bit 6 Mask Value See bit 7 description 5 5 0 RW Port 1 Bit 5 Mask Value See bit 7 description 4 B4 0 RW Port 1 Bit 4 Mask Value See bit 7 description 3 B3 0 RW Port 1 Bit 3 Mask Value See bit 7 description 2 B2 0 RW Port 1 Bit 2 Mask Value See bit 7 description 1 B1 0 RW Port 1 Bit 1 Mask Val
142. OCPLn clears the ECOMnh bit to 0 writing to PCAOCPHn sets ECOMn to 1 PCAOCPLn PCAOCPHn MATn Match Enable match gt Interrupt Flag ECOMn Compare Enable X CEXn PCA Clock i TOGn Toggle Enable Figure 16 4 PCA High Speed Output Mode Diagram silabs com Smart Connected Energy friendly Preliminary Rev 0 2 180 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 3 7 Frequency Output Mode Frequency Output Mode produces a programmable frequency square wave on the module s associated CEXn pin The capture compare module high byte holds the number of PCA clocks to count before the output is toggled The frequency of the square wave is then defined as follows PEE M 2x PCAOCPHn Note A value of 0x00 in the PCAOCPHn register is equal to 256 for this equation Where is the frequency of the clock selected by the CPS2 0 bits in the PCA mode register PCAOMD The lower byte of the cap ture compare module is compared to the PCA counter low byte on a match n is toggled and the offset held in the high byte is added to the matched value in PCAOCPLn Frequency Output Mode is enabled by setting the ECOMn TOGn and PWMn bits in the PCAOCPMn register Note The MATn bit should normally be set to 0 in this mode If the bit is set to 1 the CCFn flag for the channel will be set when the 16 bit PCAO counter and the 16 bit capture compare register fo
143. OLY 0x1021 Create the CRC dividend for polynomial arithmetic binary arithmetic with no carries Divide the poly into the dividend using CRC subtraction holds the remainder of each divide 0 Only complete this division for 8 bits since input is 1 byte for i 0 i lt 8 i 1 Check if the MSB is set if MSB is 1 then the POLY can divide into the dividend if CRC acc amp 0x8000 0x8000 if so shift the CRC value and XOR subtract the poly ORC dcc acc lt lt 1 ORC doc POLY 1 if not just shift the CRC value CRC lt lt I Return the final remainder CRC value return C The following table lists several input values and the associated outputs using the 16 bit algorithm Table 14 1 Example 16 bit CRC Outputs 0x63 OxBD35 0x8C OxB1F4 Ox7D OxAECA OxBB 0xCC Ox6CF6 0x00 0x00 OxBB OxCC 0xB166 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 153 EFM8BB2 Reference Manual Cyclic Redundancy Check CRCO 14 3 2 Using the CRC on a Data Stream The CRC module may be used to perform CRC calculations on any data set available to the firmware To perform a CRC on an arbitra ry data sream 1 Select the initial result value using CRCVAL 2 Set the result to its initial value write 1 to CRCINIT 3 Write
144. Output Polarity PCAOPWM OxF7 0x00 0x10 PCA PWM Configuration PCONO 0x87 ALL Power Control 1 0x9A 0x00 Power Control 1 OxC1 0x10 Prefetch Engine Control PRTDRV OxF6 0x00 0x20 Port Drive Strength PSCTL Ox8F ALL Program Store Control PSW OxDO ALL Program Status Word REFOCN OxD1 0x00 0x10 Voltage Reference Control REGOCN 0 9 0 00 0 20 Voltage Regulator 0 Control REG1CN 0xC6 0x20 Voltage Regulator 1 Control REVID 0 6 0 00 Revision Identifcation RSTSRC OxEF 0x00 Reset Source SBCON1 0x94 0x20 UART1 Baud Rate Generator Control SBRLH1 0x96 0x20 UART1 Baud Rate Generator High Byte silabs com Smart Connected Energy friendly Preliminary Rev 0 2 19 EFM8BB2 Reference Manual Special Function Registers Register Address SFR Pages Description SBRLL1 0x95 0x20 UART1 Baud Rate Generator Low Byte SBUFO 0x99 0x00 0x20 UARTO Serial Port Data Buffer SBUF1 0x92 0x20 UART1 Serial Port Data Buffer SCONO 0x98 0x00 0x20 UARTO Serial Port Control SCON1 0xC8 0x20 UART1 Serial Port Control SFRPAGE OxA7 ALL SFR Page SFRPGCN OxCF 0x10 SFR Page Control SFRSTACK 0 07 0 10 SFR Page Stack SMBOADM OxD6 0x00 0x20 SMBus 0 Slave Address Mask SMBOADR 0 07 0 00 0 20 SMBus 0 Slave Address SMBOCF 1 0 00 0 20 SMBus 0 Configuration SMBOCNO 0xCO 0x00 0x20 SMBus 0 Control SMBODAT
145. OxFCOO OxFBFF OxFBCO OxF800 OxFBBF OxF7FF 0x4000 Ox3FFF 0x0000 Preliminary Rev 0 2 23 EFM8BB2 Reference Manual Flash Memory OxFFFF Memory Lock OxFFFE Read Only 64 Bytes OxFFDO OxFFCF OxFFCO OxFBFE Code Security 64 Bytes OxFBCO OxFBBF OxFBBE 9717 Page OxFB80 64 Bytes OxFB7F Nonvolatile Data 14 x 64 Byte Pages OxF800 OxFFFF Read Only 64 Bytes OxFFCO OxFFBF Reserved 0 00 OxFBFF Code Security Page 64 Bytes OxFBCO OxFBBF Nonvolatile Data 960 Bytes 15 x 64 Byte Pages OxF800 OxF7FF Reserved 0 2000 1 8 KB Code 16 x 512 Byte pages 0 0000 Figure 4 2 Flash Memory Map 8 KB Devices 4 2 Features The flash memory has the following features Upto 16 KB in 512 byte sectors and 1 KB in 64 byte sectors In system programmable from user firmware Security lock to prevent unwanted read write erase access silabs com Smart Connected Energy friendly Preliminary Rev 0 2 24 EFM8BB2 Reference Manual Flash Memory 4 3 Functional Description 4 3 1 Security Options The CIP 51 provides security options to protect the flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants The Program Store Write Enable bit PSWE in register PSCTL and the Program Store Erase Enable bit PSEE in register PSCTL bits protect the flash memory from accidental modific
146. PCAO interrupt 3 PHADCO 0 RW ADCO Conversion Complete Interrupt Priority Control MSB This bit sets the MSB of the priority field for the ADCO Conversion Complete interrupt 2 PHWADCO 0 RW This bit sets the MSB of the priority field for the ADCO Window interrupt ADCO Window Comparator Interrupt Priority Control MSB 1 PHMAT 0 RW Port Match Interrupt Priority Control MSB This bit sets the MSB of the priority field for the Port Match Event interrupt 0 PHSMBO 0 RW This bit sets the MSB of the priority field for the SMBO interrupt SMBus 5 0 Interrupt Priority Control MSB silabs com Smart Connected Energy friendly Preliminary Rev 0 2 44 EFM8BB2 Reference Manual Interrupts 6 3 7 EIE2 Extended Interrupt Enable 2 Bit 7 6 5 4 3 2 1 0 Reserved 4 2 0 ES1 Reserved Access RW RW RW RW RW Reset 0 0 0 0 0 0 0 SFR Page 0x10 SFR Address OxCE Bit Reset Access Description 7 5 Reserved Must write reset value 4 4 0 RW Timer 4 Interrupt Enable This bit sets the masking of the Timer 4 interrupt Value Name Description 0 DISABLED Disable Timer 4 interrupts 1 ENABLED Enable interrupt requests generated by the TF4L or TF4H flags 3 EI2CO 0 RW 12 0 Slave Interrupt Enable This bit sets the masking of the I2CO slave interrupt Value Name Description 0 DISABLED Disable all 2 0 slav
147. PI MISO pin Slave mode full duplex Pre load the transmit FIFO with the initial bytes to be sent Use the RFRQ flag as an interrupt source If the RXTH field is set to anything other than it is recommended to configure and enable RX timeouts Inside the ISR check RXE and read bytes from the FIFO as they are available For every byte read a new byte may be written to the transmit FIFO silabs com Smart Connected Energy friendly Preliminary Rev 0 2 205 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO Slave Receiver Timeout When acting as a SPI slave using RFRQ interrupts and with the RXTH field set to a value greater than it is possible for the external master to write too few bytes to the device to immediately generate an interrupt To avoid leaving lingering bytes in the receive FIFO the slave receiver timeout feature may be used Receive timeouts are enabled by setting the RXTOE bit to 1 The length of a receive timeout may be specified in the SPInCKR register and is equivalent to SPInCKR x 32 system clock cycles SYSCLKs The internal timeout counter will run when at least one byte has been received in the receive FIFO but the RFRQ flag is not set the RFTH threshold has not been crossed The counter is reloaded from the SPInCKR register under any of the following con ditions The receive buffer is read by firmware The RFRQ flag is set A valid SCK occurs on the SPI interface If the inte
148. Port pins assigned to the associated peripheral P0 3 is skipped by setting POSKIP 3 to 1 Figure 11 3 Crossbar Priority Decoder Example Assignments silabs com Smart Connected Energy friendly Preliminary Rev 0 2 81 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 3 3 1 Crossbar Functional Map Figure 11 4 Full Crossbar Map on page 83 shows all of the potential peripheral to pin assignments available to the crossbar Note that this does not mean any peripheral can always be assigned to the highlighted pins The actual pin assignments are determined by the priority of the enabled peripherals Preliminary Rev 0 2 82 silabs com Smart Connected Energy friendly EFM8BB2 Reference Manual SPIO SCK SPIO MISO SPIO MOSI SPIO NSS SMBO SDA m Pin Skip Settings Q 17 2 E lt 172 E o 010 0 P1SKIP P2SKIP The crossbar peripherals are assigned in priority order from top to bottom These boxes represent Port pins which can potentially be assigned to a peripheral Special Function Signals are not assigned by the crossbar When these signals are enabled the Crossbar should be manually configured to skip the corresponding port pins Pins can be skipped by setting the corres
149. R R Reset 0 0x0 0 0 0 SFR Page 0x20 SFR Address OxF7 Bit Reset Access Description 7 Reserved Must write reset value 6 4 0 0 R TX FIFO Count This field indicates the number of bytes in the transmit FIFO 3 Reserved Must write reset value 2 0 RXCNT 0x0 R RX FIFO Count This field indicates the number of bytes in the receive FIFO silabs com Smart Connected Energy friendly Preliminary Rev 0 2 217 EFM8BB2 Reference Manual System Management Bus I2C SMBO 18 System Management Bus 2 SMBO 18 1 Introduction The SMBus interface is a two wire bi directional serial bus The SMBus is compliant with the System Management Bus Specifica tion version 1 1 and compatible with the 12C serial bus Data SMBODAT Shift Register SDA State Control Slave Address SCL Logic Recognition Timers 0 Master SCL Clock 1or2 Generation Timer 3 Figure 18 1 SMBus 0 Block Diagram 18 2 Features The SMBus module includes the following features Standard up to 100 kbps and Fast 400 kbps transfer speeds Support for master slave and multi master modes Hardware synchronization and arbitration for multi master mode Clock low extending clock stretching to interface with faster masters Hardware support for 7 bit slave and general call address recognition Firmware support for 10 bit slave address decoding Ability to inhibit all sla
150. RSF bit will read 1 following a software forced reset The state of the RSTb pin is unaffected by this reset silabs com Smart Connected Energy friendly Preliminary Rev 0 2 64 EFM8BB2 Reference Manual Reset Sources and Power Supply Monitor 9 4 Reset Sources and Supply Monitor Control Registers 9 4 1 RSTSRC Reset Source Bit 7 6 5 4 3 2 1 0 Reserved FERROR CORSEF SWRSF WDTRSF MCDRSF PORSF PINRSF Access RW R RW RW R RW RW R Reset Varies Varies Varies Varies Varies Varies Varies Varies SFR Page 0x0 SFR Address OxEF Bit Reset Access Description 7 Reserved Must write reset value 6 FERROR Varies R Flash Error Reset Flag This read only bit is set to 1 if a flash read write erase error caused the last reset 5 CORSEF Varies RW Comparator0 Reset Enable and Flag Read This bit reads 1 if Comparator 0 caused the last reset Write Writing a 1 to this bit enables Comparator 0 active low as a reset source 4 SWRSF Varies RW Software Reset Force and Flag Read This bit reads 1 if last reset was caused by a write to SWRSF Write Writing a 1 to this bit forces a system reset 3 WDTRSF Varies R Watchdog Timer Reset Flag This read only bit is set to 1 if a watchdog timer overflow caused the last reset 2 MCDRSF Varies RW Missing Clock Detector Enable and Flag Read This bit reads 1 if a missing clock detector timeout caused the last reset Write Writin
151. RX FIFO when the RX FIFO is not empty 0 1 RFRQ will be set if the FIFO contains more than one byte silabs com Smart Connected Energy friendly Preliminary Rev 0 2 282 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 Reset Access Description 0 2 TWO RFRQ will be set if the RX FIFO contains more than two bytes 0 3 THREE RFRQ will be set if the RX FIFO contains more than three bytes silabs com Smart Connected Energy friendly Preliminary Rev 0 2 283 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 4 8 UART1FCN1 UART1 FIFO Control 1 Bit 7 6 5 4 3 2 1 0 TXHOLD TIE RFRQ RXTO RIE Access R R RW RW R RW RW Reset 1 1 0 1 0 0x0 1 SFR Page 0x20 SFR Address 0xD8 bit addressable Bit Reset Access Description 7 TFRQ 1 R Transmit FIFO Request Set to 1 by hardware when the number of bytes in the TX FIFO is less than or equal to the TX FIFO threshold TXTH Value Name Description 0 NOT_SET The number of bytes in the TX FIFO is greater than TXTH 1 SET The number of bytes in the TX FIFO is less than or equal to TXTH 6 TXNF 1 R TX FIFO Not Full This bit indicates when the TX FIFO is full and can no longer be written to If a write is performed when TXNF is cleared to 0 it will replace the most recent byte i
152. SILICON LABS EFM8 Busy Bee Family EFM8BB2 Reference Manual The 8 2 part of the Busy Bee family of MCUs is a multi purpose line of 8 bit microcontrollers with a comprehensive feature set in small packages These devices offer high value by integrating advanced analog and enhanced high speed communication peripherals into small packages making them ideal for space con strained applications With an efficient 8051 core enhanced pulse width modulation and precision analog the EFM8BB2 family is also optimal for embedded applications EFM8BBz2 applications include the following Motor control Medical equipment Consumer electronics Lighting systems Sensor controllers High speed communication hub Clock Management Energy Management MH tale Power On Reset Flash Program Memory 16 KB Debug Interface with C2 5 V to 3 3 V LDO Regulator Serial Interfaces Ports Lowest power mode with peripheral operational Security Pin Reset EONS Normal Idle Suspend Snooze Shutdown EFM8BB2 Reference Manual System Overview 1 System Overview 1 1 Introduction Port I O Configuration C2D Debug Programming C2CK RSTb x Hardware Reset Digital Peripherals 51 8051 Controller Core UARTO 16 KB ISP Flash Program Memory Power On Reset UART1 Timers 0 1 2 3 4 Port 0
153. SMD 01 If SPI interrupts are enabled an interrupt will be generated This bit is not automatically cleared by hardware and must be cleared by firmware 4 RXOVRN 0 RW Receive Overrun Flag This bit is set to logic 1 by hardware when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPIO shift register If SPI interrupts are enabled an interrupt will be generated This bit is not automatically cleared by hardware and must be cleared by firmware 3 2 NSSMD Ox1 RW Slave Select Mode Selects between the following NSS operation modes Value Name Description 0x0 3 WIRE 3 Wire Slave or 3 Wire Master Mode NSS signal is not routed to a port pin 0 1 4 WIRE SLAVE 4 Wire Slave or Multi Master Mode NSS is an input to the device 0x2 4 WIRE MAS 4 Wire Single Master Mode NSS is an output and logic low TER NSS LOW 0x3 4 WIRE MAS 4 Wire Single Master Mode NSS is an output and logic high TER NSS HIGH 1 TXNF 1 R TX FIFO Not Full This bit indicates when the TX FIFO is full and can no longer be written to If a write is performed when is cleared to 0 a WCOL error will be generated Value Name Description 0 FULL The TX FIFO is full 1 NOT FULL The TX FIFO has room for more data 0 SPIEN 0 RW SPIO Enable Value Name Description 0 DISABLED Disable the SPI module silabs com Smart Connected Energy friend
154. T Port 1 Output Mode 11 4 16 P1SKIP Port 1 Skip 11 4 17 P2MASK Port 2 Mask 11 4 18 P2MAT Port 2 Match 11 4 19 P2 Port 2 Pin Latch 11 4 20 P2MDIN Port 2 Input Mode 11 4 24 P2MDOUT Port 2 Output Mode 11 4 22 P2SKIP Port 2 Skip 11 4 23 P3 Port 3 Pin Latch 11 4 24 P3MDIN Port 3 Input Mode 11 4 25 P3MDOUT Port 3 Output Mode 11 5 INTO and INT1 Control Registers 11 5 1 ITO1CF INTO INT1 Configuration Analog to Digital Converter ADCO 12 1 Introduction 12 2 Features 12 3 Functional Description 12 3 1 Clocking 12 3 2 Voltage Reference Options 12 3 2 1 Internal Voltage Reference 12 3 2 2 Supply or LDO Voltage Reference 12 3 2 3 External Voltage Reference 12 3 2 4 Ground Reference Table of Contents 78 19 19 19 80 81 82 84 84 84 85 85 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 107 108 108 109 109 111 111 112 112 112 112 112 112 112 113 296 13 12 3 3 Input Selection 12 3 3 1 Multiplexer Channel Selection 12 3 4 Gain Setting 12 3 5 Initiating Conversions 12 3 6 Input Tracking 12 3 7 Burst Mode 12 3 8 8 Bit 12 3 9 12 Bit Mode 12 3 10 Output Formatting 12 3 11 Power Considerations 12 3 12 Window Comparator 12 3 13 Temperature Sensor 12 3 13 1 Temperature Sensor Calibration 12 4 ADCO Control Registers 12 4 1 ADCOCNO ADCO Control
155. T ADRPT Access RW RW RW RW Reset 0 0 0x0 SFR Page 0x0 0x10 SFR Address OxB3 Bit Reset Access Description 7 AD12BE 0 RW 12 Bit Mode Enable Enables 12 bit mode In 12 bit mode the ADC throughput is reduced by a factor of 4 Value Name Description 0 12_BIT_DISABLED Disable 12 bit mode 1 12_BIT_ENABLED Enable 12 bit mode 6 ADAE 0 RW Accumulate Enable Enables multiple conversions to be accumulated when burst mode is disabled Value Name Description 0 ACC_DISABLED ADCOH ADCOL contain the result of the latest conversion when Burst Mode is disabled 1 ACC_ENABLED ADCOH ADCOL contain the accumulated conversion results when Burst Mode is disabled Firmware must write 0 0000 to ADCOH ADCOL to clear the accumula ted result 5 3 ADSJST 0 0 RW Accumulator Shift and Justify Specifies the format of data read from ADCOH ADCOL All remaining bit combinations are reserved Value Name Description 0x0 RIGHT NO SHIFT Right justified No shifting applied 0 1 RIGHT SHIFT 1 Right justified Shifted right by 1 bit 0x2 RIGHT SHIFT 2 Right justified Shifted right by 2 bits 0x3 RIGHT SHIFT 3 Right justified Shifted right by 3 bits 0 4 LEFT NO SHIFT Left justified No shifting applied 2 0 ADRPT 0x0 RW Repeat Count Selects the number of conversions to perform and accumulate in Burst Mode This bit field must be set to 000 if Burst Mode is disabled Value Name Description 0x0 ACC 1 Perform and Accumulate 1 conversi
156. T with the slave address and R W bit set to 1 3 Clear the interrupt flag 51 Send Repeated Start 1 Set the STO 1 Set the STA flag flag 2 Clear the 2 Clear the interrupt flag 51 interrupt flag SI Interrupt 1 Read Data From SMBODAT 2 Clear the interrupt flag SI Figure 18 8 Master Read Sequence State Diagram EHACK 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 229 EFM8BB2 Reference Manual System Management Bus I2C SMBO Slave Write Sequence During a write sequence an SMBus master writes data to a slave device The slave in this transfer will be a receiver during the address byte and a receiver during all data bytes When slave events are enabled INH 0 the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit WRITE in this case is received If hardware ACK generation is disabled upon entering Slave Receiver Mode an interrupt is generated and the ACKRQ bit is set The software must respond to the received slave address with an ACK or ignore the received slave address with a NACK If hardware ACK generation is enabled the hardware will apply the ACK for a slave address which matches the criteria set up by SMBOADR and SMBOADM The interrupt will occur after the ACK cycle If the received slave address is ignored by software or hardware slave interrupts will be inhibited until the next START is detected I
157. T4 T3 Overflows T4 To Timer Low SYSCLK Clock Input To Timer High Clock Input for split mode Timer Clock Selection Figure 19 4 Timer 2 3 and 4 Clock Source Selection silabs com Smart Connected Energy friendly Preliminary Rev 0 2 247 EFM8BB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 and Timer4 Capture Source Selection Capture mode allows an external input the low frequency oscillator clock or comparator 0 events to be measured against the selected clock source Each timer may individually select one of four capture sources in capture mode An external input T2 routed through the crossbar the low frequency oscillator clock or comparator 0 events The capture input signal for the timer is selected using the TnCSEL field in the TMRnCN 1 register T2 Pin via Crossbar LFOSCO To Timer Capture Input 1 1 1 1 1 1 1 1 Comparator 0 Output TnCSEL i 1 Capture Source Selection Figure 19 5 Timer 2 3 and 4 Capture Source Selection 19 3 3 1 16 bit Timer with Auto Reload When TnSPLIT is zero the timer operates as a 16 bit timer with auto reload In this mode the selected clock source increments the timer on every clock As the 16 bit timer register increments and overflows from OxFFFF to 0x0000 the 16 bit value in the timer reload registers TMRnRLH and TMRnRLL is loaded into the main timer count register and the
158. TER_DISABLED Disable master mode Operate in slave mode 1 MASTER ENABLED Enable master mode Operate as a master 5 CKPHA 0 RW SPIO Clock Phase Value Name Description 0 DATA_CEN Data centered on first edge of SCK period TERED_FIRST 1 DATA_CEN Data centered on second edge of SCK period TERED_SECOND 4 CKPOL 0 RW SPIO Clock Polarity Value Name Description 0 IDLE_LOW SCK line low in idle state 1 IDLE_HIGH SCK line high in idle state 3 SLVSEL 0 R Slave Selected Flag This bit is set to logic 1 whenever the NSS pin is low indicating SPIO is the selected slave It is cleared to logic 0 when NSS is high slave not selected This bit does not indicate the instantaneous value at the NSS pin but rather a de glitched ver sion of the pin input 2 NSSIN 1 R NSS Instantaneous Pin Input This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read This input is not de glitched 1 SRMT 1 R Shift Register Empty This bit will be set to logic 1 when all data has been transferred in out of the shift register and there is no new information available to read from the transmit buffer or write to the receive buffer It returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on SCK 0 RXE 1 R RX FIFO Empty silabs com Smart Connected Energy friendly This bit indicates when the RX FIFO is empty If a read is performed when RXE is set the
159. TK 0 9 0 00 0 10 ADCO Burst Mode Track Time B OxFO ALL B Register CKCONO Ox8E ALL Clock Control 0 1 OxA6 0x10 Clock Control 1 CLKSEL 0 9 ALL Clock Select CMPOCNO Ox9B 0x00 0x10 Comparator 0 Control 0 1 0 99 0 10 Comparator 0 Control 1 CMPOMD Ox9D 0x00 0x10 Comparator 0 Mode CMPOMX Ox9F 0x00 0x10 Comparator 0 Multiplexer Selection 1 OxBF 0x00 0x10 Comparator 1 Control 0 1 1 OxAC 0x10 Comparator 1 Control 1 CMP1MD OxAB 0x00 0x10 Comparator 1 Mode CMP1MX OxAA 0x00 0x10 Comparator 1 Multiplexer Selection CRCOCNO OxCE 0x00 0x20 CRCO Control 0 CRCOCN1 0x86 0x00 0x20 CRCO Control 1 CRCOCNT OxD3 0x00 0x20 CRCO Automatic Flash Sector Count CRCODAT OxDE 0x00 0x20 CRCO Data Output CRCOFLIP OxCF 0x00 0x20 CRCO Bit Flip CRCOIN OxDD 0x00 0x20 CRCO Data Input CRCOST 0 2 0 00 0 20 Automatic Flash Sector Start DERIVID OxAD 0x00 Derivative Identification DEVICEID 0 5 0 00 Device Identification DPH 0x83 ALL Data Pointer High DPL 0x82 ALL Data Pointer Low EIE1 OxE6 0x00 0x10 Extended Interrupt Enable 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 17 EFM8BB2 Reference Manual Special Function Registers Register Address SFR Pages Description EIE2 OxCE 0x10 Extended Interrupt Enable 2 EIP1 OxF3 0x00
160. This field should be programmed to the smallest allowed value according to the system clock speed When transitioning to a faster clock speed program FLRT before changing the clock When changing to a slower clock speed change the clock before changing FLRT Value Name Description 0 SYSCLK_BE SYSCLK lt 25 MHz LOW_25 MHZ 1 SYSCLK BE SYSCLK 50 MHz LOW 50 MHZ 3 0 Reserved Must write reset value silabs com Smart Connected Energy friendly Preliminary Rev 0 2 76 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 Port I O Crossbar External Interrupts and Port Match 11 1 Introduction Digital and analog resources are externally available on the device s multi purpose I O pins Port pins 0 2 3 can be defined as gen eral purpose I O GPIO assigned to one of the internal digital resources through the crossbar or dedicated channels or assigned to an analog function Port pins P3 0 and P3 1 can be used as GPIO Additionally the C2 Interface Data signal C2D is shared with P3 0 UARTO Priority Crossbar 4 Decoder SPIO P0 0 VREF SMBO 2 PO P4 P2 x 4 SMBO Eo UBER 4 PO 4 Out P0 6 CNVSTR 1 7 P1 0 SYSCLK Po P1 P2 Port P1 1 ADCO In Control P1 2 Poj and E PCA CEXn CMPO In iod 214 P4 P2 B 1 6 PCA ECI a Pis 1 i PO 1 P2 Port Match P2 0 1 P2 2 2
161. Track ADTM 0 Powered Power Up ADEN 0 Down and Track lt ADPWR T Tracking set by ADTK 4 Tracking set by ADTM 4 SAR clocks C Converting 12 3 7 Burst Mode Burst mode is a power saving feature that allows the ADC to remain in a low power state between conversions When burst mode is enabled the ADC wakes from a low power state accumulates 1 4 8 16 32 or 64 samples using the internal low power high frequen oscillator then re enters a low power state Since the burst mode clock is independent of the system clock the can perform multiple conversions then enter a low power state within a single system clock cycle even if the system clock is running from a slow oscillator Note When using burst mode care must be taken to issue a convert start signal no faster than once every four SYSCLK periods This includes external convert start signals The ADC will ignore convert start signals which arrive before a burst is finished Burst mode is enabled by setting ADBMEN to logic 1 When in burst mode ADEN controls the ADC idle power state i e the state the ADC enters when not tracking or performing conversions If ADEN is set to logic 0 the ADC is powered down after each burst If AD EN is set to logic 1 the ADC remains enabled after each burst On each convert start signal the ADC is awakened from its idle power state If the ADC is powered down it will automatically
162. Universal Asynchronous Receiver Transmitter 0 UARTO 20 3 Functional Description 20 3 1 Baud Rate Generation The UARTO baud rate is generated by Timer 1 in 8 bit auto reload mode The TX clock is generated by TL1 the RX clock is generated by a copy of TL1 which is not user accessible Both TX and RX timer overflows are divided by two to generate the TX and RX baud rates The RX timer runs when Timer 1 is enabled and uses the same reload value TH1 However an RX timer reload is forced when a START condition is detected on the RX pin This allows a receive to begin any time a START is detected independent of the TX timer state Baud Rate Generator In Timer 1 TX Clock START y Detection SPUREN RX Timer RX Clock Figure 20 2 UARTO Baud Rate Logic Block Diagram Timer 1 should be configured for 8 bit auto reload mode mode 2 The Timer 1 reload value and prescaler should be set so that over flows occur at twice the desired UARTO baud rate The UARTO baud rate is half of the Timer 1 overflow rate Configuring the Timer 1 overflow rate is discussed in the timer sections 20 3 2 Data Format UARTO has two options for data formatting All data transfers begin with a start bit logic low followed by the data sent LSB first and end with a stop bit logic high The data length of the UARTO module is normally 8 bits An extra 9th bit may be added to the MSB of data field for use in multi processor communications or for implem
163. W RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 SFR Page ALL SFR Address 0x90 bit addressable Bit Reset Access Description 7 B7 1 RW Port 1 Bit 7 Latch Value Name Description 0 LOW P1 7 is low Set P1 7 to drive low 1 HIGH P1 7 is high Set P1 7 to drive or float high 6 B6 1 RW Port 1 Bit 6 Latch See bit 7 description 5 B5 1 RW Port 1 Bit 5 Latch See bit 7 description 4 B4 1 RW Port 1 Bit 4 Latch See bit 7 description 3 B3 1 RW Port 1 Bit 3 Latch See bit 7 description 2 B2 1 RW Port 1 Bit 2 Latch See bit 7 description 1 B1 1 RW Port 1 Bit 1 Latch See bit 7 description 0 BO 1 RW Port 1 Bit 0 Latch See bit 7 description Writing this register sets the port latch logic value for the associated I O pins configured as digital I O Reading this register returns the logic value at the pin regardless if it is configured as output or input silabs com Smart Connected Energy friendly Preliminary Rev 0 2 98 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 14 P1MDIN Port 1 Input Mode Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 SFR Page 0x0 0x20 SFR Address OxF2 Bit Reset Access Description 7 B7 1 RW Port 1 Bit 7 Input Mode Value Name Description 0 ANALOG P1 7 pin is configured for analog mode 1 DIGITAL P1 7 pin is con
164. WE to a 1 and leave them disabled until after PSWE has been reset to 0 Any interrupts posted during the flash write or erase operation will be serviced in priority order after the flash operation has been completed and interrupts have been re enabled by software Make certain that the flash write and erase pointer variables are not located in XRAM See your compiler documentation for instruc tions regarding how to explicitly locate variables in different memory areas Add address bounds checking to the routines that write or erase flash memory to ensure that a routine called with an illegal address does not result in modification of the flash System Clock If operating from an external crystal based source be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature If the system is operating in an electrically noisy environment use the internal oscillator or use an external CMOS clock If operating from the external oscillator switch to the internal oscillator during flash write or erase operations The external oscillator can continue to run and the CPU can switch back to the external oscillator after the flash operation has completed silabs com Smart Connected Energy friendly Preliminary Rev 0 2 28 EFM8BB2 Reference Manual Flash Memory 4 4 Flash Control Registers 4 4 1 PSCTL Program Store Control Bit 7 6 5 4 3 2 1 0 Res
165. WIHW Quality Support and Community www silabs com mcu www silabs com simplicity www silabs com quality community silabs com Disclaimer Silicon Laboratories intends to provide customers with the latest accurate and in depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products Characterization data available modules and peripherals memory sizes and memory addresses refer to each specific device and Typical parameters provided can and do vary in different applications Application examples described herein are for illustrative purposes only Silicon Laboratories reserves the right to make changes without further notice and limitation to product information specifications and descriptions herein and does not give warranties as to the accuracy or completeness of the included information Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories A Life Support System is any product or system intended to support or sustain life and or health which if it fails can be reasonably expected to result in significant personal injury or death Silicon Laboratories pro
166. X FIFO Reading SMBODAT reads data from the RX FIFO If SMBODAT is written when TXNF is 0 the data will over write the last data byte present in the TX FIFO If SMBODAT is read when RXE is set the last byte in the RX FIFO will be returned silabs com Smart Connected Energy friendly Preliminary Rev 0 2 237 EFM8BB2 Reference Manual System Management Bus 2 SMBO 18 4 7 SMBOFCNO SMBus 0 FIFO Control 0 Bit 7 6 3 2 1 0 TFLSH TXTH RFRQE RFLSH RXTH Access RW RW RW RW RW RW Reset 0 0 0x0 0 0 0 0 SFR Page 0x20 SFR Address 0xC3 Bit Reset Access Description 7 TFRQE 0 RW Write Request Interrupt Enable When set to 1 an SMBus 0 interrupt will be generated any time TFRQ is logic 1 Value Name Description 0 DISABLED SMBus 0 interrupts will not be generated when TFRQ is set 1 ENABLED SMBus 0 interrupts will be generated if TFRQ is set 6 TFLSH 0 RW TX FIFO Flush This bit flushes the TX FIFO When firmware sets this bit to 1 the internal FIFO counters will be reset and any remaining data will not be sent Hardware will clear the TFLSH bit back to 0 when the operation is complete 1 SYSCLK cycle 5 4 TXTH 0x0 RW TX FIFO Threshold This field configures when hardware will set the transmit FIFO request bit TFRQ TFRQ is set whenever the number of bytes in the TX FIFO is equal to or less than the value in TXTH Value Name
167. X FIFO contains data 1 EMPTY The RX FIFO is empty 1 0 Reserved Must write reset value silabs com Smart Connected Energy friendly Preliminary Rev 0 2 173 EFM8BB2 Reference Manual I2C Slave I2CSLAVEO 15 4 8 I2COFCT 2 0 FIFO Count Bit 7 6 5 4 3 1 0 Reserved TXCNT Reserved RXCNT Access R R R R Reset 0 0x0 0 SFR Page 0x20 SFR Address OxF5 Bit Reset Access Description 7 Reserved Must write reset value 6 4 TXCNT 0 0 R TX FIFO Count This field indicates the number of bytes in the transmit FIFO 3 Reserved Must write reset value 2 0 RXCNT 0 0 R RX FIFO Count This field indicates the number of bytes in the receive FIFO silabs com Smart Connected Energy friendly Preliminary Rev 0 2 174 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 Programmable Counter Array 0 16 1 Introduction The programmable counter array PCA provides multiple channels of enhanced timer and PWM functionality while requiring less CPU intervention than standard counter timers The PCA consists of a dedicated 16 bit counter timer and one 16 bit capture compare mod ule for each channel The counter timer is driven by a programmable timebase that has flexible external and internal clocking options Each capture compare module may be configured to operate independently in one of five modes Edge Triggered Captu
168. ace uses a clock signal C2CK and a bi directional C2 data signal C2D to transfer information between the device and a host system See the C2 Interface Specification for details on the C2 protocol 1 10 Bootloader All devices come pre programmed with a UART bootloader This bootloader resides in flash and can be erased if it is not needed silabs com Smart Connected Energy friendly Preliminary Rev 0 2 7 EFM8BB2 Reference Manual Memory Organization 2 Memory Organization 2 1 Memory Organization The memory organization of the CIP 51 System Controller is similar to that of a standard 8051 There are two separate memory spaces program memory and data memory Program and data memory share the same address space but are accessed via different instruction types Program memory consists of a non volatile storage area that may be used for either program code or non volatile data storage The data memory consisting of internal and external data space is implemented as RAM and may be used only for data storage Program execution is not supported from the data memory space 2 2 Program Memory The CIP 51 core has a 64 KB program memory space The product family implements some of this program memory space as in sys tem re programmable flash memory Flash security is implemented by a user programmable location in the flash block and provides read write and erase protection All addresses not specified in the device memory ma
169. age 0x20 SFR Address 0xC5 Bit Reset Access Description 7 0 RXLN 0x00 RW SMBus Receive Length Counter Master Receiver This field allows firmware to set the number of bytes to receive as a master receiver with EHACK set to 1 before stalling the bus As long as the RX FIFO is serviced and RXLN is greater than zero hardware will continue to read new bytes from the slave device and send ACKs Each received byte decrements RXLN until RXLN reaches 0 If RXLN is 0 and a new byte is received hardware will set the SI bit and stall the bus The last byte recieved will be ACKed if the ACK bit is set to 1 or NAKed if the ACK bit is cleared to 0 Slave Receiver When RXLN is cleared to 0 the bus will stall and generate an interrupt after every received byte regard less of the FIFO status Any other value programmed here will allow the FIFO to operate RXLN is not decremented as new bytes arrive in slave receiver mode This register should not be modified by firmware in the middle of a transfer except when SI 1 and the bus is stalled 18 4 10 SMBOFCT SMBus 0 FIFO Count Bit 7 6 4 3 2 1 0 Reserved TXCNT Reserved RXCNT Access R R R R Reset 0x0 0 0x0 0 SFR Page 7 0x20 SFR Address OxEF Bit Name Reset Access Description 7 5 Reserved Must write reset value 4 TXCNT 0 R TX FIFO Count This field indicates the number of bytes in the transmit FIFO 3 1 Reserved Must write
170. also cessible as 128 individually addressable bits Each bit has a bit address from 0x00 to Ox7F Bit O of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07 Bit 7 of the byte at Ox2F has bit address Ox7F A bit access is distinguished from a full byte access by the type of instruction used bit source or destination operands as opposed to a byte source or destination The MCS 51 assembly language allows an alternate notation for bit addressing of the form XX B where is the byte address and B is the bit position within the byte For example the instruction Mov C 22 3h moves the Boolean value at 0x13 bit 3 of the byte at location 0x22 into the Carry flag Stack A programmer s stack can be located anywhere in the 256 byte data memory The stack area is designated using the Stack Pointer SP SFR The SP will point to the last location used The next value pushed on the stack is placed at SP 1 and then SP is incremen ted A reset initializes the stack pointer to location 0x07 Therefore the first value pushed on the stack is placed at location 0x08 which is also the first register RO of register bank 1 Thus if more than one register bank is to be used the SP should be initialized to a location in the data memory not being used for data storage The stack depth can extend up to 256 bytes External RAM On devices with more than 256 bytes of on chip RAM the additional RAM is mapped into
171. ameters Parameter Description Min Max Units Master Mode Timing TMCKH SCK High Time 1 x ns SCK Low Time 1x TsvscLK ns MISO Valid to SCK Sample Edge 20 ns Sample Edge to MISO Change 5 ns Slave Mode Timing TsE NSS Falling to First SCK Edge 5 ns Tsp Last SCK Edge to NSS Rising 5 ns Tsgz NSS Falling to MISO Valid 20 ns Tspz NSS Rising to MISO High Z 20 ns TckH SCK High Time 40 ns TCKL SCK Low Time 40 ns Tsis MOSI Valid to SCK Sample Edge 20 ns SCK Sample Edge to MOSI Change 5 ns TsoH SCK Shift Edge to MISO Change 20 ns Note 1 is equal to one period of the device system clock SYSCLK silabs com Smart Connected Energy friendly Preliminary Rev 0 2 209 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO 17 4 SPIO Control Registers 17 4 1 SPIOCFG SPIO Configuration Bit 7 6 5 4 3 2 1 0 SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXE Access R RW RW RW R R R R Reset 0 0 0 0 0 1 1 1 SFR Page 0x0 0x20 SFR Address OxA1 Bit Name Reset Access Description 7 SPIBSY 0 R SPI Busy This bit is set to logic 1 when a SPI transfer is in progress master or slave mode 6 MSTEN 0 RW Master Mode Enable Value Name Description 0 MAS
172. anagement features of these devices include Supports five power modes 1 Normal mode Core and all peripherals fully operational 2 Idle mode Core halted peripherals fully operational core waiting for interrupt to continue 3 Suspend mode High frequency internal clocks halted select peripherals active waiting for wake signal to continue 4 Snooze mode High frequency internal clocks halted select peripherals active regulators in low power mode waiting for wake signal to continue 5 Shutdown mode All clocks stopped and internal LDO shut off device waiting for POR or pin reset Note Legacy 8051 Stop mode is also supported but Suspend and Snooze offer more functionality with better power consumption nternal Core LDO Supplies power to majority of blocks Low power consumption in Snooze mode can be shut down completely in Shutdown mode 5V to 3 3V Regulator not available on all product variants Allows direct connection to 5 supply Provides up to 100 mA for system level use Low power consumption in Snooze mode silabs com Smart Connected Energy friendly Preliminary Rev 0 2 48 EFM8BB2 Reference Manual Power Management and Internal Regulators 7 3 Idle Mode In idle mode CPU core execution is halted while any enabled peripherals and clocks remain active Power consumption in idle mode is dependent upon the system clock frequency and any active peripherals Setting the IDLE bit in
173. and RTS pins CTS and RTS may be individually enabled using the crossbar may be operated independently of one another and are active only when enabled through the crossbar The CTS pin is an input to the device When CTS is held high the UART will finish any byte transfer that is currently in progress and then will halt before sending any more data CTS must be returned low before data transfer will continue The RTS pin is an output from the device When the receive buffer is full RTS will toggle high When data has been read from the buffer and there is additional room available RTS will be cleared low 21 3 4 Basic Data Transfer UART provides standard asynchronous full duplex communication All data sent or received goes through the SBUF1 register and when an extra bit is enabled the RBX bit in the SCON1 register Transmitting Data Data transmission is initiated when software writes a data byte to the SBUF1 register If XBE is set extra bit enable software should set up the desired extra bit in TBX prior to writing SBUF1 Data is transmitted LSB first from the TX pin The TI flag is set at the end of the transmission at the beginning of the stop bit time If TI interrupts are enabled TI will trigger an interrupt Receiving Data To enable data reception firmware should write the REN bit to 1 Data reception begins when a start condition is recognized on the RX pin Data will be received at the selected baud rate
174. and Timer 1 is configured in the same manner as described for Timer 0 The THO register holds the eight MSBs of the 13 bit counter timer TLO holds the five LSBs in bit positions TLO 4 TLO O The three upper bits of TLO 1 0 7 0 5 are indeterminate and should be masked out or ignored when reading the 13 bit timer register increments and overflows from Ox1FFF all ones to 0x0000 the timer overflow flag TFO in TCON is set and an interrupt occurs if Timer 0 interrupts are enabled The overflow rate for Timer 0 in 13 bit mode is F F input Clock Finput Clock TIMERO 213 THO TLO 8192 THO TLO The CTO bit in the TMOD register selects the counter timer s clock source When CTO is set to logic 1 high to low transitions at the selected Timer 0 input pin TO increment the timer register Events with a frequency of up to one fourth the system clock frequency can be counted The input signal need not be periodic but it must be held at a given level for at least two full system clock cycles to ensure the level is properly sampled Clearing CT selects the clock defined by the TOM bit in register CKCONO When TOM is set Timer 0 is clocked by the system clock When TOM is cleared Timer 0 is clocked by the source selected by the Clock Scale bits in CKCONO Setting the TRO bit enables the timer when either GATEO in the TMOD register is logic O or based on the input signal INTO The INOPL bit setting in ITO1TCF changes which state of INTO i
175. any erase or write performed on flash memory will be ignor ed Supply Voltage Reset Threshold RSTb Supply Monitor Reset Figure 9 3 Reset Sources 9 3 4 External Reset The external RSTb pin provides a means for external circuitry to force the device into a reset state Asserting an active low signal on the RSTb pin generates a reset an external pullup and or decoupling of the RSTb pin may be necessary to avoid erroneous noise induced resets The PINRSF flag is set on exit from an external reset 9 3 5 Missing Clock Detector Reset The Missing Clock Detector MCD is a one shot circuit that is triggered by the system clock If the system clock remains high or low for more than the MCD time window the one shot will time out and generate a reset After a MCD reset the MCDRSF flag will read 1 signifying the MCD as the reset source otherwise this bit reads 0 Writing a 1 to the MCDRSF bit enables the Missing Clock Detector writing a O disables it The state of the RSTb pin is unaffected by this reset 9 3 6 Comparator 0 Reset ComparatorO can be configured as a reset source by writing a 1 to the CORSEF flag ComparatorO should be enabled and allowed to settle prior to writing to CORSEF to prevent any turn on chatter on the output from generating an unwanted reset The ComparatorO reset is active low if the non inverting input voltage on is less than the inverting input voltage on the de
176. ardware acknowledgement is enabled these interrupts are always generated after the ACK cycle Interrupts are also generated to indicate the beginning of a transfer when a master START generated or the end of a transfer when a slave STOP detected Software should read the SMBOCNO register to find the cause of the SMBus interrupt silabs com Smart Connected Energy friendly Preliminary Rev 0 2 221 EFM8BB2 Reference Manual System Management Bus I2C SMBO SMBus Configuration Register The SMBus Configuration register SMBOCF is used to enable the SMBus master and or slave modes select the SMBus clock source and select the SMBus timing and timeout options When the ENSMB bit is set the SMBus is enabled for all master and slave events Slave events may be disabled by setting the INH bit With slave events inhibited the SMBus interface will still monitor the SCL and SDA pins however the interface will NACK all received addresses and will not generate any slave interrupts When the INH bit is set all slave events will be inhibited following the next START interrupts will continue for the duration of the current transfer The SMBCS bit field selects the SMBus clock source which is used only when operating as a master or when the Free Timeout detec tion is enabled When operating as a master overflows from the selected source determine both the bit rate and the absolute minimum SCL low and high times The selected clock source m
177. are intervention other than requiring that firmware enable the I2CSLAVEO peripheral By default the I2C bus operates at speeds of up to Fast mode F S mode only where the maximum transfer rate is 400 kbps The 2 bus switches to from F S mode to HS mode only after the following sequence of bits appear on the I2C bus 1 START bit S 2 8 bit master code 0000 1XXX 3 NACK bit N The HS mode master codes are reserved 8 bit codes which are not used for slave addressing or other purposes An HS mode compati ble I2C master device will switch the I2C bus to HS mode by transmitting the above sequence of bits on the I2C bus at a transfer rate of not more than 400 kbps After that the master can switch to HS mode to transfer data at a rate of up to 3 4 Mbps The I2C bus Switches back to F S mode when the I2C master transmits a STOP bit Standard Read Write Transaction 9 S Master code SLA RW JA DWiReACKs P Repeated Start Read Transaction e riso e M Hs mare S Master code SUA RW AN S SA RW R ____ P Figure 15 4 Fast Mode to High Speed Mode Transition 15 3 3 Operational Modes The I2C Slave peripheral supports two types of data transfers I2C Read data transfers where data is transferred from the 2 Slave peripheral to I2C master and I2C Write data transfers where data is transferred from an 2 master to the I2C Slave peripheral The I2C master
178. art Connected Energy friendly Preliminary Rev 0 2 27 EFM8BB2 Reference Manual Flash Memory Voltage Supply Maintenance and the Supply Monitor If the system power supply is subject to voltage or current spikes add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings table are not exceeded Make certain that the minimum supply rise time specification is met If the system cannot meet this rise time specification then add an external supply brownout circuit to the RSTb pin of the device that holds the device in reset until the voltage supply reaches the lower limit and re asserts RSTb if the supply drops below the low supply limit Do not disable the supply monitor If the supply monitor must be disabled in the system firmware should be added to the startup routine to enable the on chip supply monitor and enable the supply monitor as a reset source as early in code as possible This should be the first set of instructions executed after the reset vector For C based systems this may involve modifying the startup code added by the C compiler See your compiler documentation for more details Make certain that there are no delays in software between enabling the supply monitor and enabling the supply monitor as a reset source Note The supply monitor must be enabled and enabled as a reset source when writing or erasing flash memory A flash error reset
179. ation Automatic parity generation and checking Four byte FIFO on transmit and receive Auto baud detection LIN break and sync field detection CTS RTS hardware flow control silabs com Smart Connected Energy friendly Preliminary Rev 0 2 271 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 3 Functional Description 21 3 1 Baud Rate Generation The UART1 baud rate is generated by a dedicated 16 bit timer which runs from the controller s core clock SYSCLK and has prescaler options of 1 4 12 or 48 The timer and prescaler options combined allow for a wide selection of baud rates over many SYSCLK fre quencies The baud rate generator is configured using three registers SBCON1 SBRLH1 and SBRLL1 The SBCON 1 register enables or disa bles the baud rate generator and selects the prescaler value for the timer The baud rate generator must be enabled for UART1 to function Registers SBRLH1 and SBRLL1 constitute a 16 bit reload value 5 1 for the dedicated 16 bit timer The internal timer counts up from the reload value on every clock tick On timer overflows OxFFFF to 0x0000 the timer is reloaded For reliable UART receive operation it is typically recommended that the UART baud rate does not exceed SYSCLK 16 Figure 21 2 Baud Rate Generation 21 3 2 Data Format UARTI1 has a number of available options for data formatting Data transfers begin with a start bit
180. ation by software PSWE must be explicitly set to 1 before software can modify the flash memory both PSWE and PSEE must be set to 1 before software can erase flash memory Additional security features prevent proprietary program code and data constants from being read or altered across the C2 interface Security lock bytes located in flash user space offer individual protection for the data flash and user flash regions of flash memory Read write and erase access can be restricted from both unprotected code or the C2 interface See the specific device memory map for the location of the security bytes and the regions they protect The user lock security byte controls access to the user flash region and allows the user to lock n flash pages starting at page 0 where n is the 1s complement number represented by the user lock security byte The data lock security byte controls access to the data flash region and operates as an all or nothing lock If the data lock security byte is OxFF all of data area including the page containing the lock byte will be open If the data lock security bytes is a non OxFF value all of data area will be locked Note The page containing the user lock security byte is unlocked when no other flash pages are locked all bits of the user lock securi ty byte are 1 and locked when any other flash pages are locked any bit of the user lock security byte is O Table 4 1 User Lock Security Byte Decoding Us
181. aud feature is primarily targeted at LIN applications it may be used stand alone as well For use in LIN applications the LINMDE bit should be set to 1 This requires that the UART see a valid LIN break followed by a delimit er and then a valid LIN sync word 0x55 before adjusting the baud rate When used in LIN mode the autobaud detection circuit may be left on during normal communications If LIN mode is not enabled LINMDE 0 the autobaud detection circuit will expect to see an 0x55 word on the received data path The autobaud detection circuit operates by measuring the amount of time it takes to receive a sync word 0x55 and then adjusting the SBRL register value according to the measured time given the current prescale settings Important Because there is no break involved when autobaud is used in non LIN applications it is important that the autobaud circuit only be enabled when the receiver is expecting an 0x55 sync byte The SYNCD flag will be set upon detection of the sync byte and firmware should disable auto baud once the sync detection flag has been set The autobaud feature counts the number of prescaled clocks starting from the first rising edge of the sync field and ending on the last rising edge of the sync field For 1 accuracy the prescaler system clock and baud rate must be selected such that there are at least 100 clocks per bit Because the baud rate generator overflows twice per bit the resulting counts in the SBR
182. ay be shared by other peripherals so long as the timer is left running at all times The selected clock source should typically be configured to overflow at three times the desired bit rate When the interface is operating as a master and SCL is not driven or extended by any other devices on the bus the device will hold the SCL line low for one overflow period and release it for two overflow periods is typically twice as large as ow The actual SCL output may vary due to other devices on the bus SCL may be extended low by slower slave devices driven low by contending master devices or have long ramp times The SMBus hardware will ensure that once SCL does return high it reads a logic high state for a minimum of one overflow period Timer Source Overflows SCL Thigh SCL High Timeout Figure 18 4 Typical SMBus SCL Generation Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line The minimum SDA setup time defines the abso lute minimum time that SDA is stable before SCL transitions from low to high The minimum SDA hold time defines the absolute mini mum time that the current SDA value remains stable after SCL transitions from high to low EXTHOLD should be set so that the mini mum setup and hold times meet the SMBus Specification requirements of 250 ns and
183. be set to logic 1 2 TOG 0 RW Channel 1 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEX1 pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW Channel 1 Pulse Width Modulation Mode Enable This bit enables the PWM function When enabled a pulse width modulated signal is output on the CEX1 pin 8 to 11 bit PWM is used if PWM16 is cleared to 0 16 bit mode is used if PWM16 is set to 1 If the TOG bit is also set the module operates in Frequency Output Mode 0 ECCF 0 RW Channel 1 Capture Compare Flag Interrupt Enable This bit sets the masking of the Capture Compare Flag CCF1 interrupt Value Name Description 0 DISABLED Disable CCF1 interrupts 1 ENABLED Enable a Capture Compare Flag interrupt request when CCF1 is set silabs com Smart Connected Energy friendly Preliminary Rev 0 2 196 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 4 13 PCAOCPL1 PCA Channel 1 Capture Module Low Byte Bit 7 6 5 4 3 2 1 0 PCAOCPL1 Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address OxE9 Bit Reset Access Description 7 0 PCAOCPL1 0x00 RW PCA Channel 1 Capture Module Low Byte The PCAOCPL1 register holds the low byte LSB of the 16 bit capture module This register address also allows access
184. but increases the response times 0 Reserved Must write reset value silabs com Smart Connected Energy friendly Preliminary Rev 0 2 53 EFM8BB2 Reference Manual Clocking and Oscillators 8 Clocking and Oscillators 8 1 Introduction The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources By default the system clock comes up running from the 24 5 MHz oscillator divided by 8 Clock Control 49 MHz Oscillator HFOSC1 24 5 MHz Oscillator Programmable SYSCLK HFOSCO Divider 1 2 4 128 To core and peripherals External Clock Input EXTCLK 80 kHz Oscillator Divider 0 1 2 4 8 Figure 8 1 Clock Control Block Diagram 8 2 Features The clock control system offers the following features Provides clock to core and peripherals 24 5 MHz internal oscillator HFOSCO accurate to 2 over supply and temperature corners 49 MHz internal oscillator HFOSC1 accurate to 1 5 over supply and temperature corners 80 kHz low frequency oscillator LFOSCO External CMOS clock input EXTCLK Clock divider with eight settings for flexible clock scaling Divide the selected clock source by 1 2 4 8 16 32 64 or 128 e HFOSCO and HFOSC 1 include 1 5x pre scalers for further flexibility 8 3 Functional Description 8 3 1 Clock Selection The CLKSEL register is used to select the clock source for the system SYSCLK The
185. can be found in the C2 Interface Speci fication 23 2 Features The C2 interface provides the following features In system device programming and debugging Non intrusive no firmware or hardware peripheral resources required Allows inspection and modification of all memory spaces and registers Provides hardware breakpoints and single step capabilites Can be locked via flash security mechanism to prevent unwanted access 23 3 Pin Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in system debugging and flash programming may be per formed C2CK is shared with the RSTb pin while the C2D signal is shared with a port I O pin This is possible because C2 communica tion is typically performed when the device is in the halt state where all on chip peripherals and user software are stalled In this halted state the C2 interface can safely borrow the C2CK and C2D pins In most applications external resistors are required to isolate C2 interface traffic from the user application RSTb a Input b Output c C2 Interface Master Figure 23 1 Typical C2 Pin Sharing The configuration above assumes the following The user input b cannot change state while the target device is halted The RSTb pin on the target device is used as an input only Additional resistors may be necessary depending on the specific application silabs com Smart Connected Energy friendly Prelimi
186. can generate a reset if the supply drops below the corresponding threshold This monitor is enabled and enabled as a reset source after initial power on to protect the device until the supply is an ade quate and stable voltage When enabled and selected as a reset source any power down transition or power irregularity that causes the supply to drop below the reset threshold will drive the RSTb pin low and hold the core in a reset state When the supply returns to a level above the reset threshold the monitor will release the core from the reset state The reset status can then be read using the device reset sources module After a power fail reset the PORF flag reads 1 and all of the other reset flags in the RSTSRC register are indeterminate The power on reset delay tpog is not incurred after a supply monitor reset The contents of RAM should be presumed invalid after a supply monitor reset The enable state of the supply monitor and its selection as a reset source is not altered by device resets For example if the supply monitor is de selected as a reset source and disabled by software using the VDMEN bit in the VDMOCN register and then firmware performs a software reset the supply monitor will remain disabled and de selected after the reset To protect the integrity of flash contents the supply monitor must be enabled and selected as a reset source if software contains rou tines that erase or write flash memory If the supply monitor is not enabled
187. can still be read from the receive FIFO but the receiver will not place new data into the FIFO Value Name Description 0 RECEIVE DISABLED UARTI reception disabled 1 RECEIVE ENABLED UART reception enabled 3 TBX 0 RW Extra Transmission Bit The logic level of this bit will be assigned to the extra transmission bit when 1 the SMOD register This bit is not used when parity is enabled 2 RBX Varies R Extra Receive Bit RBX is assigned the value of the extra bit when XBE 1 in the SMOD1 register This bit is not valid when parity is enabled or when XBE is cleared to 0 1 TI 0 RW Transmit Interrupt Flag Set to a 1 by hardware after data has been transmitted at the beginning of the STOP bit When the TI interrupt is enabled setting this bit causes the CPU to vector to the UART1 interrupt service routine This bit must be cleared by firm ware silabs com Smart Connected Energy friendly Preliminary Rev 0 2 276 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 Reset Access Description 0 RI 0 R Receive Interrupt Flag Set to 1 by hardware when a byte of data has been received by UART1 set at the STOP bit sampling time RI remains set while the receive FIFO contains any data Hardware will clear this bit when the receive FIFO is empty If a read of SBUF1 is performed when RI is cleared the most recently received byte will be returned silabs com Smart Co
188. ccess RW RW R RW RW RW Reset 0 0 0x0 0 0 0 SFR Page 0x0 0x10 SFR Address 0 08 bit addressable Bit Reset Access Description 7 CF 0 RW PCA Counter Timer Overflow Flag Set by hardware when the PCA Counter Timer overflows from OxFFFF to 0x0000 When the Counter Timer Overflow CF interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automati cally cleared by hardware and must be cleared by firmware 6 CR 0 RW PCA Counter Timer Run Control This bit enables disables the PCA Counter Timer Value Name Description 0 STOP Stop the PCA Counter Timer 1 RUN Start the PCA Counter Timer running 5 3 Reserved Must write reset value 2 CCF2 0 RW PCA Module 2 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF2 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by firmware 1 CCF1 0 RW PCA Module 1 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF1 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by firmware 0 CCFO 0 RW PCA Module 0 Capture Compare Flag This bit is set by hardware when a match or capture o
189. ccurred 3 2 CPHYP 0 0 RW Comparator Positive Hysteresis Control Value Name Description 0 0 DISABLED Positive Hysteresis disabled 0 1 ENABLED MODE1 Positive Hysteresis Hysteresis 1 0x2 ENABLED MODE2 Positive Hysteresis Hysteresis 2 0 3 ENABLED MODE3 Positive Hysteresis Hysteresis 3 Maximum 1 0 CPHYN 0 0 RW Comparator Negative Hysteresis Control silabs com Smart Connected Energy friendly Preliminary Rev 0 2 142 EFM8BB2 Reference Manual Comparators and CMP1 Bit Reset Access Description Value Name Description 0 0 DISABLED Negative Hysteresis disabled 0 1 ENABLED MODE1 Negative Hysteresis Hysteresis 1 0x2 ENABLED MODE2 Negative Hysteresis Hysteresis 2 0 3 ENABLED MODES3 Negative Hysteresis Hysteresis 3 Maximum silabs com Smart Connected Energy friendly Preliminary Rev 0 2 143 EFM8BB2 Reference Manual Comparators and CMP1 13 4 2 CMPOMD Comparator 0 Mode Bit 7 6 5 4 1 0 CPLOUT CPINV CPRIE CPFIE INSL CPMD Access RW RW RW RW RW RW Reset 0 0 0 0 0x0 0x2 SFR Page 0x0 0x10 SFR Address Ox9D Bit Reset Access Description 7 CPLOUT 0 RW Comparator Latched Output Flag This bit represents the comparator output value at the most recent PCA counter overflow Value Name Description 0 LOW Comparator output was logic low a
190. ccurs When the CCFO interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by firmware silabs com Smart Connected Energy friendly Preliminary Rev 0 2 188 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 4 2 PCAOMD PCA Mode Bit 7 6 5 4 3 2 1 0 CIDL Reserved CPS ECF Access RW R RW RW Reset 0 0x0 0x0 0 SFR Page 0x0 0x10 SFR Address OxD9 Bit Name Reset Access Description 7 CIDL 0 RW PCA Counter Timer Idle Control Specifies PCA behavior when CPU is in Idle Mode Value Name Description 0 NORMAL PCA continues to function normally while the system controller is in Idle Mode 1 SUSPEND PCA operation is suspended while the system controller is in Idle Mode 6 4 Reserved Must write reset value 3 1 0x0 RW PCA Counter Timer Pulse Select These bits select the timebase source for the PCA counter Value Name Description 0x0 SYSCLK DIV 12 System clock divided by 12 0 1 SYSCLK DIV 4 System clock divided by 4 0 2 TO OVERFLOW Timer 0 overflow 0 3 High to low transitions max rate system clock divided by 4 0 4 SYSCLK System clock 0x5 EXTOSC DIV 8 External clock divided by 8 synchronized with the system clock 0x6 LFOSC DIV 8 Low frequency oscillator divided by 8 0 ECF 0 RW PCA Counter Timer Ov
191. ce is enabled when NSS is logic 0 and disabled when NSS is logic 1 The internal shift register bit counter is reset on a falling edge of NSS When operated in 3 wire slave mode NSS is not mapped to an external port pin through the crossbar Since there is no way of uniquely addressing the device in 3 wire slave mode the SPI must be the only slave device present on the bus It is important to note that in 3 wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received The bit counter can only be reset by disabling and re enabling the SPI module with the SPIEN bit silabs com Smart Connected Energy friendly Preliminary Rev 0 2 202 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO 17 3 4 Clock Phase and Polarity Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPInCFG register The CKPHA bit selects one of two clock phases edge used to latch the data The CKPOL bit selects between an active high or active low clock Both master and slave devices must be configured to use the same clock phase and polarity The SPI module should be disabled by clearing the SPIEN bit when changing the clock phase or polarity Note that CKPHA should be set to 0 on both the master and slave SPI when communicating between two Silicon Labs devices CKPOL 0 CKPHA 0 SCK CKPOL 0 CKPHA 1 CKPOL 1 CKPHA 0 ck X
192. ce multiplexer is configurable to use a number of different internal and external reference sources The ground ref erence mux allows the ground reference for ADCO to be selected between the ground pin GND or a port pin dedicated to analog ground AGND The voltage and ground reference options are configured using the REFOCN register The REFSL field selects be tween the different reference options while GNDSL configures the ground connection 12 3 2 1 Internal Voltage Reference The high speed internal reference offers two programmable voltage levels and is self contained and stabilized It is not routed to an external pin and requires no external decoupling When selected the internal reference will be automatically enabled disabled on an as needed basis by the ADC The reference can be set to one of two voltage values 1 65 V or 2 4 V depending on the value of the IREFLVL bit The electrical specifications tables detail SAR clock and throughput limitations for each reference source 12 3 2 2 Supply or LDO Voltage Reference For applications with a non varying power supply voltage using the power supply as the voltage reference can provide the ADC with added dynamic range at the cost of reduced power supply noise rejection Additionally the internal 1 8 V LDO supply to the core may be used as a reference Neither of these reference sources are routed to the VREF pin and do not require additional external decou pling 12 3 2 3 External V
193. cess Description 7 4 Reserved Must write reset value 3 B3 0 RW Port 2 Bit 3 Mask Value Value Name Description 0 IGNORED P2 3 pin logic value is ignored and will not cause a port mismatch event 1 COMPARED P2 3 pin logic value is compared to P2MAT 3 2 B2 0 RW Port 2 Bit 2 Mask Value See bit 3 description 1 B1 0 RW Port 2 Bit 1 Mask Value See bit 3 description 0 BO 0 RW Port 2 Bit 0 Mask Value See bit 3 description silabs com Smart Connected Energy friendly Preliminary Rev 0 2 102 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 18 P2MAT Port 2 Match Bit 7 3 2 1 0 Reserved B3 B2 B1 BO Access R RW RW RW RW Reset 0 0 1 1 1 1 SFR Page 0x20 SFR Address OxFB Bit Reset Access Description 7 4 Reserved Must write reset value 3 B3 1 RW Port 2 Bit 3 Match Value Value Name Description 0 LOW P2 3 pin logic value is compared with logic LOW 1 HIGH P2 3 pin logic value is compared with logic HIGH 2 B2 1 RW Port 2 Bit 2 Match Value See bit 3 description 1 B1 1 RW Port 2 Bit 1 Match Value See bit 3 description 0 BO 1 RW Port 2 Bit 0 Match Value See bit 3 description silabs com Smart Connected Energy friendly Preliminary Rev 0 2 103 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 19 P2 Port 2 Pin Latch Bit
194. cluded in the device two are 16 bit counter timers compatible with those found in the standard 8051 and the rest are 16 bit auto reload timers for timing peripherals or for general purpose use These timers can be used to measure time inter vals count external events and generate periodic interrupt requests Timer 0 and Timer 1 are nearly identical and have four primary modes of operation The other timers offer both 16 bit and split 8 bit timer functionality with auto reload and capture capabilities Timer 0 and Timer 1 include the following features Standard 8051 timers supporting backwards compatibility with firmware and hardware Clock sources include SYSCLK SYSCLK divided by 12 4 or 48 the External Clock divided by 8 or an external pin 8 bit auto reload counter timer mode 13 bit counter timer mode 16 bit counter timer mode Dual 8 bit counter timer mode Timer 0 Timer 2 Timer 3 and Timer 4 are 16 bit timers including the following features Clock sources for all timers include SYSCLK SYSCLK divided by 12 or the External Clock divided by 8 LFOSCO divided by 8 may be used to clock Timer 3 and Timer 4 in active or suspend snooze power modes Timer 4 is a low power wake source and can be chained together with Timer 3 16 bit auto reload timer mode Dual 8 bit auto reload timer mode External pin capture LFOSCO capture Comparator 0 capture Watchdog Timer WDTO The device includes a programmabl
195. cription 0 NOT SET No comparator rising edge has occurred since this flag was last cleared 1 RISING EDGE Comparator rising edge has occurred 4 CPFIF 0 RW Comparator Falling Edge Flag Must be cleared by firmware Value Name Description 0 NOT SET No comparator falling edge has occurred since this flag was last cleared 1 FALLING EDGE Comparator falling edge has occurred 3 2 CPHYP 0 0 RW Comparator Positive Hysteresis Control Value Name Description 0 0 DISABLED Positive Hysteresis disabled 0 1 ENABLED MODE1 Positive Hysteresis Hysteresis 1 0x2 ENABLED MODE2 Positive Hysteresis Hysteresis 2 0 3 ENABLED MODE3 Positive Hysteresis Hysteresis 3 Maximum 1 0 CPHYN 0 0 RW Comparator Negative Hysteresis Control silabs com Smart Connected Energy friendly Preliminary Rev 0 2 147 EFM8BB2 Reference Manual Comparators and CMP1 Bit Reset Access Description Value Name Description 0 0 DISABLED Negative Hysteresis disabled 0 1 ENABLED MODE1 Negative Hysteresis Hysteresis 1 0x2 ENABLED MODE2 Negative Hysteresis Hysteresis 2 0 3 ENABLED MODES3 Negative Hysteresis Hysteresis 3 Maximum silabs com Smart Connected Energy friendly Preliminary Rev 0 2 148 EFM8BB2 Reference Manual Comparators and CMP1 13 5 2 CMP1MD Comparator 1 Mode Bit 7 6 5 4
196. cription 7 IREFLVL 0 RW Internal Voltage Reference Level Sets the voltage level for the internal reference source Value Name Description 0 1P65 The internal reference operates at 1 65 V nominal 1 2P4 The internal reference operates at 2 4 V nominal 6 Reserved Must write reset value 5 GNDSL 0 RW Analog Ground Reference Selects the ADCO ground reference Value Name Description 0 GND PIN The ADCO ground reference is the GND pin 1 AGND PIN The ADCO ground reference is the PO 1 AGND pin 4 3 REFSL 0 3 RW Voltage Reference Select Selects the ADCO voltage reference Value Name Description 0x0 VREF PIN The ADCO voltage reference is the pin 0 1 VDD PIN The ADCO voltage reference is the VDD pin 0 2 INTERNAL LDO The ADCO voltage reference is the internal 1 8 V digital supply voltage 0x3 INTERNAL_VREF The ADCO voltage reference is the internal voltage reference 2 TEMPE 0 RW Temperature Sensor Enable Enables Disables the internal temperature sensor Value Name Description 0 TEMP_DISABLED Disable the Temperature Sensor 1 TEMP ENABLED Enable the Temperature Sensor 1 0 Reserved Must write reset value silabs com Smart Connected Energy friendly Preliminary Rev 0 2 133 EFM8BB2 Reference Manual Comparators and CMP1 13 Comparators 0 and CMP1 13 1 Introduction Analog comparators are used to compare the voltage of two analog inputs with a digital output indicating which input
197. ction These bits select which port pin is assigned to INT1 This pin assignment is independent of the Crossbar INT1 will monitor the assigned port pin without disturbing the peripheral that has been assigned the port pin via the Crossbar The Crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin Value Name Description 0 0 PO 0 Select P0 0 0 1 _1 Select 1 0 2 _2 Select 2 0x3 3 Select P0 3 0 4 4 Select P0 4 0 5 _5 Select 5 0x6 PO 6 Select PO 6 0 7 7 Select PO 7 3 INOPL 0 RW INTO Polarity Value Name Description 0 ACTIVE LOW INTO input is active low 1 ACTIVE HIGH INTO input is active high 2 0 INOSL 0 1 RW INTO Port Pin Selection These bits select which port pin is assigned to INTO This pin assignment is independent of the Crossbar INTO will monitor the assigned port pin without disturbing the peripheral that has been assigned the port pin via the Crossbar The Crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin Value Name Description 0 0 PO 0 Select 0 0 0 1 PO 1 Select PO 1 0x2 2 Select P0 2 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 109 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match Bit Name Reset Access Description 0x3 3 Select P0 3 0 4 4 Sel
198. ction even in a slave only implementa tion silabs com Smart Connected Energy friendly Preliminary Rev 0 2 220 EFM8BB2 Reference Manual System Management Bus I2C SMBO 18 3 3 Configuring the SMBus Module The SMBus can operate in both Master and Slave modes The interface provides timing and shifting control for serial transfers higher level protocol is determined by user software The SMBus interface provides the following application independent features Byte wise serial data transfers Clock signal generation on SCL Master Mode only and SDA data synchronization Timeout bus error recognition as defined by the SMBOCF configuration register START STOP timing detection and generation Bus arbitration Interrupt generation Status information Optional hardware recognition of slave address and automatic acknowledgement of address data SMBus interrupts are generated for each data byte or slave address that is transferred When hardware acknowledgement is disabled the point at which the interrupt is generated depends on whether the hardware is acting as a data transmitter or receiver When a trans mitter i e sending address data receiving an ACK this interrupt is generated after the ACK cycle so that software may read the re ceived ACK value when receiving data i e receiving address data sending an ACK this interrupt is generated before the ACK cycle so that software may define the outgoing ACK value If h
199. d registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power on reset The contents of RAM are unaffected during a reset any previously stored data is preserved as long as power is not lost The Port I O latch es are reset to 1 in open drain mode Weak pullups are enabled during and after the reset For Supply Monitor and power on resets the RSTb pin is driven low until the device exits the reset state On exit from the reset state the program counter PC is reset and the system clock defaults to an internal oscillator The Watchdog Timer is enabled and program execution begins at location 0x0000 Reset Sources Supply Monitor or Power up gt lt Se 4 gt lt Se Missing Clock Detector Watchdog Timer X AX System reset Software Reset X XX Comparator 0 V Flash Error XX Figure 9 1 Reset Sources Block Diagram 9 2 Features Reset sources on the device include the following Power on reset External reset pin Comparator reset Software triggered reset Supply monitor reset monitors VDD supply Watchdog timer reset Missing clock detector reset Flash error reset silabs com Smart Connected Energy friendly Preliminary Rev 0 2 60 EFM8BB2 Reference Manual Reset Sources and Power Supply Monitor 9 3 Functional Description 9 3 1 Device Reset Upon entering a reset state from any source the fol
200. d for the ADCO Conversion Complete interrupt 2 PWADCO 0 RW This bit sets the LSB of the priority field for the ADCO Window interrupt ADCO Window Comparator Interrupt Priority Control LSB 1 PMAT 0 RW Port Match Interrupt Priority Control LSB This bit sets the LSB of the priority field for the Port Match Event interrupt 0 PSMBO 0 RW This bit sets the LSB of the priority field for the SMBO interrupt SMBus 5 0 Interrupt Priority Control LSB silabs com Smart Connected Energy friendly Preliminary Rev 0 2 43 EFM8BB2 Reference Manual Interrupts 6 3 6 EIP1H Extended Interrupt Priority 1 High Bit 7 6 5 4 3 2 1 0 1 PHADCO PHWADCO PHMAT PHSMBO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 7 0x10 SFR Address OxF5 Bit Reset Access Description 7 PHT3 0 RW Timer 3 Interrupt Priority Control MSB This bit sets the MSB of the priority field for the Timer 3 interrupt 6 1 0 RW This bit sets the MSB of the priority field for the CP1 interrupt Comparator1 CP1 Interrupt Priority Control MSB 5 PHCPO 0 RW This bit sets the MSB of the priority field for the CPO interrupt Comparator0 Interrupt Priority Control MSB 4 0 RW Programmable Counter Array 0 Interrupt Priority Control MSB This bit sets the MSB of the priority field for the
201. d or slave At any particular time it will be operating in one of the following four modes Master Transmitter Master Receiver Slave Transmitter or Slave Receiver The SMBus interface enters Master Mode any time a START is generated and remains in Master Mode until it loses an arbitration or generates a STOP An SMBus inter rupt is generated at the end of all SMBus byte frames The position of the ACK interrupt when operating as a receiver depends on whether hardware ACK generation is enabled As a receiver the interrupt for an ACK occurs before the ACK with hardware ACK gener ation disabled and after the ACK when hardware ACK generation is enabled As a transmitter interrupts occur after the ACK regard less of whether hardware ACK generation is enabled or not silabs com Smart Connected Energy friendly Preliminary Rev 0 2 225 EFM8BB2 Reference Manual System Management Bus I2C SMBO Master Write Sequence During a write sequence an SMBus master writes data to a slave device The master in this transfer will be a transmitter during the address byte and a transmitter during all data bytes The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit In this case the data direction bit R W will be logic 0 WRITE The master then transmits one or more bytes of serial data After each byte is transmitted an acknowledge bit is generated by
202. d when RXE is set to 1 the last byte in the RX FIFO is returned silabs com Smart Connected Energy friendly Preliminary Rev 0 2 167 EFM8BB2 Reference Manual I2C Slave IZCSLAVEO 15 4 2 I2CODOUT 12 0 Transmit Data Bit 7 6 4 3 2 1 0 I2CODOUT Access RW Reset Varies SFR Page 7 0x20 SFR Address OxBB Bit Reset Access Description 7 0 I2CODOUT Varies RW 12 0 Transmit Data Writing this register writes a byte into the TX FIFO I2CODOUT may be written when is set to 1 which indicates that there is more room available the TX FIFO If this register is written when TXNF is cleared to 0 the most recent byte written to the TX FIFO will be overwritten 15 4 3 I2COSLAD 12 0 Slave Address Bit 7 6 5 4 3 2 1 0 Reserved I2COSLAD Access RW RW Reset 0 0x00 SFR Page 0x20 SFR Address 0xBD Bit Name Reset Access Description 7 Reserved Must write reset value 6 0 I2COSLAD 0 00 RW I2C Hardware Slave Address This field defines the I2CO Slave Address for automatic hardware acknowledgement When the received I2C address matches this field hardware sets the I2COINT bit in the I2COSTAT register silabs com Smart Connected Energy friendly Preliminary Rev 0 2 168 EFM8BB2 Reference Manual I2C Slave I2CSLAVEO 15 4 4 I2COSTAT 12 0 Status
203. de See bit 7 description 0 BO 0 RW Port 1 Bit 0 Output Mode See bit 7 description silabs com Smart Connected Energy friendly Preliminary Rev 0 2 100 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 16 P1SKIP Port 1 Skip Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 0x20 SFR Address OxD5 Bit Reset Access Description 7 B7 0 RW Port 1 Bit 7 Skip Value Name Description 0 NOT_SKIPPED P1 7 pin is not skipped by the crossbar 1 SKIPPED P1 7 pin is skipped by the crossbar 6 B6 0 RW Port 1 Bit 6 Skip See bit 7 description 5 B5 0 RW Port 1 Bit 5 Skip See bit 7 description 4 B4 0 RW Port 1 Bit 4 Skip See bit 7 description 3 B3 0 RW Port 1 Bit 3 Skip See bit 7 description 2 B2 0 RW Port 1 Bit 2 Skip See bit 7 description 1 B1 0 RW Port 1 Bit 1 Skip See bit 7 description 0 BO 0 RW Port 1 Bit 0 Skip See bit 7 description silabs com Smart Connected Energy friendly Preliminary Rev 0 2 101 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 17 P2MASK Port 2 Mask Bit 7 6 5 4 3 2 1 0 Reserved B3 B2 B1 BO Access R RW RW RW RW Reset 0 0 0 0 0 0 SFR Page 0x20 SFR Address OxFC Bit Reset Ac
204. ding contention on the SPI bus when more than one master attempts simultaneous data transfers NSS can also be configured as a firmware controlled chip select output in master mode or disabled to reduce the number of pins required Additional general purpose port I O pins can be used to select multiple slave devices in master mode Supports 3 or 4 wire master or slave modes Supports external clock frequencies up to 12 Mbps in master or slave mode Support for all clock phase and polarity modes 8 bit programmable clock rate master Programmable receive timeout slave Four byte FIFO on transmit and receive Can operate in suspend or snooze modes and wake the CPU on reception of a byte Support for multiple masters on the same data lines System Management Bus 12 5 0 The SMBus interface is a two wire bi directional serial bus The SMBus is compliant with the System Management Bus Specifica tion version 1 1 and compatible with the 12C serial bus The SMBus module includes the following features Standard up to 100 kbps and Fast 400 kbps transfer speeds Support for master slave and multi master modes Hardware synchronization and arbitration for multi master mode Clock low extending clock stretching to interface with faster masters Hardware support for 7 bit slave and general call address recognition Firmware support for 10 bit slave address decoding Ability to inhibit all slave state
205. divided by 8 Additionally Timer 3 and Timer 4 may be clocked from the LFOSCO divided by 8 and operate in Suspend or Snooze modes Timer 4 is a wake source for the device and be chained together with Timer 3 to produce long sleep intervals Timer 0 and Timer 1 may also be operated as counters When functioning as a counter a counter timer register is incremented on each high to low transition at the selected input pin TO or T1 Events with a frequency of up to one fourth the system clock frequency can be counted The input signal need not be periodic but it must be held at a given level for at least two full system clock cycles to ensure the level is properly sampled Table 19 1 Timer Modes Timer 0 and Timer 1 Modes Timer 2 Modes Timer 3 and 4 Modes 13 bit counter timer 16 bit timer with auto reload 16 bit timer with auto reload 16 bit counter timer Two 8 bit timers with auto reload Two 8 bit timers with auto reload 8 bit counter timer with auto reload Input capture Input capture Two 8 bit counter timers Timer 0 only Suspend Snooze wake timer 19 2 Features Timer 0 and Timer 1 include the following features Standard 8051 timers supporting backwards compatibility with firmware and hardware Clock sources include SYSCLK SYSCLK divided by 12 4 or 48 the External Clock divided by 8 or an external pin 8 bit auto reload counter timer mode 13 bit counter timer mode 16 bit counter timer mod
206. dly Preliminary Rev 0 2 93 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 9 POMDOUT Port 0 Output Mode Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 0x20 SFR Address 4 Bit Reset Access Description 7 B7 0 RW Port 0 Bit 7 Output Mode Value Name Description 0 OPEN_DRAIN 7 output is open drain 1 PUSH_PULL 7 output is push pull 6 B6 0 RW Port 0 Bit 6 Output Mode See bit 7 description 5 5 0 RW Port 0 Bit 5 Output Mode See bit 7 description 4 B4 0 RW Port 0 Bit 4 Output Mode See bit 7 description 3 B3 0 RW Port 0 Bit 3 Output Mode See bit 7 description 2 B2 0 RW Port 0 Bit 2 Output Mode See bit 7 description 1 B1 0 RW Port 0 Bit 1 Output Mode See bit 7 description 0 BO 0 RW Port 0 Bit 0 Output Mode See bit 7 description silabs com Smart Connected Energy friendly Preliminary Rev 0 2 94 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 10 POSKIP Port 0 Skip Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 7 0x0 0x20 SFR Address OxD4 Bit Reset Access Description 7 B7 0 RW Port 0 Bit 7 Skip Value
207. ducts are generally not intended for military applications Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including but not limited to nuclear biological or chemical weapons or missiles capable of delivering such weapons Trademark Information Silicon Laboratories Inc Silicon Laboratories Silicon Labs SiLabs and the Silicon Labs logo CMEMS EFM EFM32 EFR Energy Micro Energy Micro logo and combinations thereof the world s most energy friendly microcontrollers Ember amp EZLink EZMac EZRadio amp EZRadioPRO DSPLL ISOmodem 6 Precision32 ProSLIC SiPHY USBXpress and others are trademarks or registered trademarks of Silicon Laboratories Inc ARM CORTEX Cortex M3 and THUMB are trademarks or registered trademarks of ARM Holdings Keil is a registered trademark of ARM Limited All other products or brand names mentioned herein are trademarks of their respective holders Silicon Laboratories Inc 400 West Cesar Chavez Austin TX 78701 USA SILICON LABS
208. e Dual 8 bit counter timer mode Timer 0 Timer 2 Timer 3 and Timer 4 are 16 bit timers including the following features Clock sources for all timers include SYSCLK SYSCLK divided by 12 or the External Clock divided by 8 LFOSCO divided by 8 may be used to clock Timer 3 and Timer 4 in active or suspend snooze power modes Timer 4 is a low power wake source and can be chained together with Timer 3 16 bit auto reload timer mode Dual 8 bit auto reload timer mode External pin capture LFOSCO capture Comparator 0 capture silabs com Smart Connected Energy friendly Preliminary Rev 0 2 241 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 19 3 Functional Description 19 3 1 System Connections five timers are capable of clocking other peripherals and triggering events in the system The individual peripherals select which timer to use for their respective functions Note that the Timer 2 3 and 4 high overflows apply to the full timer when operating in 16 bit mode or the high byte timer when operating in 8 bit split mode Table 19 2 Timer Peripheral Clocking Event Triggering Function T2 High T2Low T2Input High Low Input T4High T4Low 4 Input Over Over Capture Over Over Capture Over Over Capture flow flow UARTO Baud Rate Yes SMBus 0 Clock Yes Yes Yes Yes Rate Master SMBus 0 SCL Low Yes Timeout 2
209. e When operating in one of the auto reload modes TMR4RLL holds the reload value for the low byte of Timer 4 TMR4L When operating in capture mode TMR4RLL is the captured value of TMR4L 19 4 22 TMR4RLH Timer 4 Reload High Byte Bit 7 6 5 4 3 2 1 0 TMR4RLH Access RW Reset 0x00 SFR Page 0x10 SFR Address OxA3 Reset Access Description 7 0 TMR4RLH 0x00 RW Timer 4 Reload High Byte When operating in one of the auto reload modes TMR4RLH holds the reload value for the high byte of Timer 4 When operating in capture mode TMR4RLH is the captured value of TMR4H silabs com Smart Connected Energy friendly Preliminary Rev 0 2 262 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 19 4 23 TMR4L Timer 4 Low Byte Bit 7 6 5 4 3 2 1 0 TMR4L Access RW Reset 0x00 SFR Page 0x10 SFR Address 0 4 Bit 7 0 Name Reset Access Description TMR4L 0x00 RW Timer 4 Low Byte In 16 bit mode the TMRA4L register contains the low byte of the 16 bit Timer 4 In 8 bit mode TMR4L contains the 8 bit low byte timer value 19 4 24 TMR4H Timer 4 High Byte Bit 7 6 5 4 3 2 1 0 TMR4H Access RW Reset 0x00 SFR Page 0x10 SFR Address 0 5 Bit 7 0 Reset Access Description TMR4H 0x00 RW Timer 4 High Byte In 16 bit mode the TMR4H register contains
210. e 1 to ADBUSY Timer Overflow 123456 7 8 9 1011 12 13 14 15 16 17 18 meu Clocks Low Power or Convert ADTM 1 Track Convert Low Power Mode 1234567289 1011 12 13 14 cee Figure 12 3 Track and Conversion Example Timing Normal Non Burst Operation When burst mode is enabled additional tracking times may need to be specified Because burst mode may power the ADC on from an unpowered state and take multiple conversions for each start of conversion source two additional timing fields are provided If the ADC is powered down when the burst sequence begins it will automatically power up and wait for the time specified in the ADPWR bit field If the ADC is already powered on tracking depends solely on ADTM for the first conversion The ADTK field determines the amount of tracking time given to any subsequent samples in burst mode essentially ADTK specifies how long the ADC will wait between burt mode conversions If ADTM is set an additional 4 SAR clocks will be added to the tracking phase of all conversions in burst mode silabs com Smart Connected Energy friendly Preliminary Rev 0 2 116 EFM8BB2 Reference Manual Analog to Digital Converter ADCO Figure 12 4 Burst Mode Timing Convert Start gt Powered Down ADTM 7 1 ADEN 0 Power Up T Powered Power Up 4 Down and Track Powered Power Up and
211. e interrupt flag SI interrupt flag SI ACK received 1 Write next data to SMBODAT 2 Clear the interrupt flag SI Interrupt Figure 18 6 Master Write Sequence State Diagram 1 Preliminary Rev 0 2 227 silabs com Smart Connected Energy friendly EFM8BB2 Reference Manual System Management Bus I2C SMBO Master Read Sequence During a read sequence an SMBus master reads data from a slave device The master in this transfer will be a transmitter during the address byte and a receiver during all data bytes The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit In this case the data direction bit R W will be logic 1 READ Serial data is then received from the slave on SDA while the SMBus outputs the serial clock The slave transmits one or more bytes of serial data If hardware ACK generation is disabled the ACKRQ is set to 1 and an interrupt is generated after each received byte Software must write the ACK bit at that time to ACK or NACK the received byte With hardware ACK generation enabled the SMBus hardware will automatically generate the ACK NACK and then post the interrupt It is important to note that the appropriate ACK or NACK value should be set up by the software prior to receiving the byte when hardware ACK generation is enabled Writing a 1 to the bit generates an
212. e automatic ACK response 2 Write the slave address to I2COSLAD 3 Set the I2COSEL bit in I2COCNTL to 1 to enable the SCL and SDA pins 4 Set the I2COEN bit in I2COCNTL to 1 to enable the I2CSLAVEO peripheral 15 3 2 2 Protocol The I2C specification allows any recessive voltage between 3 0 and 5 0 V different devices on the bus may operate at different voltage levels However the maximum voltage on any port pin must conform to the electrical characteristics specifications The bi directional SCL serial clock and SDA serial data lines must be connected to a positive power supply voltage through a pullup resistor or similar circuit Every device connected to the bus must have an open drain or open collector output for both the SCL and SDA lines so that both are pulled high recessive state when the bus is free silabs com Smart Connected Energy friendly Preliminary Rev 0 2 159 EFM8BB2 Reference Manual 2 Slave I2CSLAVEO 5V 3 3V 3 6 V 5V 3 3V I2C Master I2C Slave Master 12C Slave and Slave Device Device Device Device SCL SDA Figure 15 2 Typical I2C System Connection Two types of data transfers are possible data transfers from a master transmitter to an addressed slave receiver WRITE and data transfers from an addressed slave transmitter to a master receiver READ The master device initiates both types of data transfers and provides the serial clock pulses on SCL The 2 inte
213. e automatic CRC calculation is CRCST CRCCNT x Block Size 1 The block size is 256 bytes Preliminary Rev 0 2 156 silabs com Smart Connected Energy friendly EFM8BB2 Reference Manual Cyclic Redundancy Check CRCO 14 4 6 CRCOFLIP CRCO Bit Flip Bit 7 6 5 4 3 2 1 0 CRCOFLIP Access RW Reset 0x00 SFR Page 0x0 0x20 SFR Address OxCF Bit Reset Access Description 7 0 CRCOFLIP 0x00 RW CRCO Bit Flip Any byte written to CRCOFLIP is read back in a bit reversed order i e the written LSB becomes the MSB For example If OxCO is written to CRCOFLIP the data read back will be 0x03 If 0x05 is written to CRCOFLIP the data read back will be OxAO 14 4 7 CRCOCN1 CRCO Control 1 Bit 7 6 5 4 3 2 1 0 AUTOEN CRCDN Reserved Access RW R R Reset 0 1 0x00 SFR Page 0x0 0x20 SFR Address 0x86 Bit Reset Access Description 7 AUTOEN 0 RW Automatic CRC Calculation Enable When AUTOEN is set to 1 any write to CRCOCNO will initiate an automatic CRC starting at flash sector CRCST and con tinuing for CRCCNT sectors 6 CRCDN 1 R Automatic CRC Calculation Complete Set to 0 when a CRC calculation is in progress Code execution is stopped during a CRC calculation therefore reads from firmware will always return 1 5 0 Reserved Must write reset value silabs com Smart Connected Energy friendly Prelim
214. e data is placed into the transmit FIFO and is held for serial transmission Any data in the TX FIFO will initiate a transmission Writing to SBUFO while is 0 will over write the most recent byte in the TX FIFO A read of SBUFO returns the oldest byte in the RX FIFO Reading SBUFO when RI is 0 will continue to return the last avail able data byte in the RX FIFO silabs com Smart Connected Energy friendly Preliminary Rev 0 2 270 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 Universal Asynchronous Receiver Transmitter 1 UART1 21 1 Introduction UART1 is an asynchronous full duplex serial port offering a variety of data formatting options A dedicated baud rate generator with 16 bit timer and selectable prescaler is included which can generate a wide range of baud rates A received data FIFO allows UART1 to receive multiple bytes before data is lost and an overflow occurs Interrupt Generation TBX extra bit Configuration SBUF 8 LSBs Dedicated Baud Receive Buffer Rate Generator RBX extra bit LIN Break Detection Autobaud Figure 21 1 UART 1 Block Diagram 21 2 Features UART1 provides the following features Asynchronous transmissions and receptions Dedicated baud rate generator supports baud rates up to SYSCLK 2 transmit or SYSCLK 8 receive 5 6 7 8 or 9 bit data Automatic start and stop gener
215. e each of the four conversions in a set When maximum throughput 180 200 ksps is needed it is recommended that AD12SM be set to 1 and ADTK to Ox3F and that the ADC be placed in always on mode ADEN 1 For sample rates under 180 ksps or when accumulating multiple samples AD12SM should normally be cleared to 0 and ADTK should be configured to provide the appropriate settling time for the subsequent conversions silabs com Smart Connected Energy friendly Preliminary Rev 0 2 118 EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 3 10 Output Formatting The registers ADCOH and ADCOL contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion Data can be right justified or left justified depending on the setting of the ADSJST field When the repeat count is set to 1 in 10 bit mode conversion codes are represented as 10 bit unsigned integers Inputs are measured from 0 to VREF x 1023 1024 Ex ample codes are shown below for both right justified and left justified data Unused bits in the ADCOH and ADCOL registers are set to 0 Table 12 2 10 Bit Output Code Example Input Voltage Right Justified ADSJST 000 Left Justified ADSJST 100 ADCOH L ADCOH L VREF x 1023 1024 OxO3FF OxFFCO VREF x 512 1024 0x0200 0x8000 VREF x 256 1024 0x0100 0x4000 0 0x0000 0x0000 When the repeat count is greater than 1 the output conversion code repre
216. e interrupts 1 ENABLED Enable interrupt requests generated by the 2 0 slave 2 ES1 0 RW UARTI1 Interrupt Enable This bit sets the masking of the UART1 interrupts Value Name Description 0 DISABLED Disable UART1 interrupts 1 ENABLED Enable UART 1 interrupts 1 0 Reserved Must write reset value silabs com Smart Connected Energy friendly Preliminary Rev 0 2 45 EFM8BB2 Reference Manual Interrupts 6 3 8 EIP2 Extended Interrupt Priority 2 Bit 7 6 5 4 3 2 1 0 Reserved 2 0 51 Reserved Access RW RW RW RW RW Reset 0 0 0 0 0 SFR Page 0x10 SFR Address OxF4 Bit Name Reset Access Description 7 5 Reserved Must write reset value 4 4 0 RW Timer 4 Interrupt Priority Control LSB This bit sets the LSB of the priority field for the Timer 4 interrupt 3 PI2CO 0 RW 12 0 Slave Interrupt Priority Control LSB This bit sets the LSB of the priority field for the I2CO Slave interrupt 2 PS1 0 RW UART1 Interrupt Priority Control LSB This bit sets the LSB of the priority field for the UART1 interrupt 1 0 Reserved Must write reset value 6 3 9 EIP2H Extended Interrupt Priority 2 High Bit 7 6 5 4 3 2 1 0 Name Reserved PHT4 2 0 1 Reserved Access RW RW RW RW RW Reset 0 0 0 0 0 SFR Page 0x10 SFR Address OxF6 Bit Reset Access Description 7 5 Reserved Must write res
217. e watchdog timer WDT running off the low frequency oscillator A WDT overflow forces the MCU into the reset state To prevent the reset the WDT must be restarted by application software before overflow If the system experiences a software or hardware malfunction preventing the software from restarting the WDT the WDT overflows and causes a reset Following a reset the WDT is automatically enabled and running with the default maximum time interval If needed the WDT can be disabled by System software or locked on to prevent accidental disabling Once locked the WDT cannot be disabled until the next system reset The state of the RST pin is unaffected by this reset The Watchdog Timer has the following features Programmable timeout interval Runs from the low frequency oscillator Lock out feature to prevent any modification until a system reset 1 6 Communications and Other Digital Peripherals Universal Asynchronous Receiver Transmitter UARTO UARTO is an asynchronous full duplex serial port offering modes 1 and 3 of the standard 8051 UART Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates Received data buffering allows UARTO to start reception of a second incoming data byte before software has finished reading the previous data byte The UART module provides the following features Asynchronous transmissions and receptions Baud rates up to SYSCLK 2 transmit or SYSCLK 8 receive
218. ect P0 4 0 5 5 Select 0 5 0 6 6 Select P0 6 0 7 7 Select PO 7 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 110 EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 Analog to Digital Converter ADCO 12 1 Introduction The ADC is a successive approximation register SAR ADC with 12 10 and 8 bit modes integrated track and hold and a program mable window detector The ADC is fully configurable under software control via several registers The ADC may be configured to measure different signals using the analog multiplexer The voltage reference for the ADC is selectable between internal and external reference sources Input Multiplexer Selection Greater Control Than Configuration External Pins ADWINT Window amparo Window Interrupt SAR Analog to VDD Digital Converter Accumulator ADCO GND ADINT Interrupt Fla Internal LDO ADBUSY On Demand Timer 0 Overflow 1 665V 24V Timer 2 Overflow Timer 3 Overflow CNVSTR Rising Edge External Pin Internal LDO g Edge VDD CEX2 Rising Edge VREF Reference Timer 2 Overflow with CEX2 High Selection Timer 4 Overflow Trigger Selection Clock Divider SYSCLK Figure 12 1 ADC Block Diagram silabs com Smart Connected Energy friendly Preliminary Rev 0 2 111 EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 2 Features Up
219. ed against the PnMATCH registers A port mis match event is generated if Pn amp PnMASK does not equal amp PnMASK for all ports with a and PnMASK register A port mismatch event may be used to generate an interrupt or wake the device from low power modes See the interrupts and power options chapters for more details on interrupt and wake up sources 11 3 6 Direct Port Access Read Write All port are accessed through corresponding special function registers When writing to a port the value written to the SFR is latch ed to maintain the output data value at each pin When reading the logic levels of the port s input pins are returned regardless of the XBRn settings i e even when the pin is assigned to another signal by the crossbar the port register can always read its corresponding port I O pin The exception to this is the execution of the read modify write instructions that target a Port Latch register as the destina tion The read modify write instructions when operating on a port SFR are the following ANL ORL XRL JBC CPL INC DEC DJNZ and MOV CLR or SETB when the destination is an individual bit in a port SFR For these instructions the value of the latch register not the pin is read modified and written back to the SFR silabs com Smart Connected Energy friendly Preliminary Rev 0 2 84 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match
220. efault condition On entry to this reset state the following occur The core halts program execution Module registers are initialized to their defined reset values unless the bits reset only with a power on reset External port pins are forced to a known state Interrupts and timers are disabled All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power on reset The contents of RAM are unaffected during a reset any previously stored data is preserved as long as power is not lost The Port latch es are reset to 1 in open drain mode Weak pullups are enabled during and after the reset For Supply Monitor and power on resets the RSTb pin is driven low until the device exits the reset state On exit from the reset state the program counter PC is reset and the system clock defaults to an internal oscillator The Watchdog Timer is enabled and program execution begins at location 0x0000 Reset sources on the device include the following Power on reset External reset pin Comparator reset Software triggered reset Supply monitor reset monitors VDD supply Watchdog timer reset Missing clock detector reset Flash error reset 1 9 Debugging The 8 2 devices include an on chip Silicon Labs 2 Wire C2 debug interface to allow flash programming and in system debug ging with the production part installed in the end application The C2 interf
221. enting parity checks on the data The SOMODE bit in the SCON reg ister selects between 8 or 9 bit data transfers MARK START BIT DO 01 02 03 04 05 06 07 5 BIT prt TIMES Ff f 1 A A A A A A A A A A BIT SAMPLING Figure 20 3 8 Bit Data Transfer STOP MARK START DO x D1 02 D3 04 Y D5 Y D6 07 Y D8 BIT BIT SPACE a 7 m BIT SAMPLING Figure 20 4 9 Bit Data Transfer Preliminary Rev 0 2 267 silabs com Smart Connected Energy friendly EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 0 UARTO 20 3 3 Data Transfer UARTO provides standard asynchronous full duplex communication data sent or received goes through the SBUFO register and in 9 bit mode the 8 bit in the SCONO register Transmitting Data Data transmission is initiated when software writes a data byte to the SBUFO register If 9 bit mode is used software should set up the desired 9th bit in TB8 prior to writing SBUFO Data is transmitted LSB first from the TX pin The TI flag in SCONO is set at the end of the transmission at the beginning of the stop bit time If Tl interrupts are enabled TI will trigger an interrupt Receiving Data To enable data reception firmware should write the REN bit to 1 Data reception begin
222. ents such as power FET switching The CPINH bit in register CMPnCN1 ena bles this option When CPINH is set to 1 the comparator output will hold its current state any time the CEX2 channel is logic low Preliminary Rev 0 2 141 silabs com Smart Connected Energy friendly EFM8BB2 Reference Manual Comparators and CMP1 13 4 CMPO Control Registers 13 4 1 CMPOCNO Comparator 0 Control 0 Bit 7 6 4 1 0 CPRIF CPFIF CPHYP CPHYN Access RW R RW RW RW RW Reset 0 0 0 0x0 0 0 SFR Page 0x0 0x10 SFR Address Ox9B Bit Reset Access Description 7 CPEN 0 RW Comparator Enable Value Name Description 0 DISABLED Comparator disabled 1 ENABLED Comparator enabled 6 CPOUT 0 R Comparator Output State Flag Value Name Description 0 5 1 55 Voltage on lt G 1 POS_GREAT Voltage on CPOP gt CPON ER_THAN_NEG 5 CPRIF 0 RW Comparator Rising Edge Flag Must be cleared by firmware Value Name Description 0 NOT SET No comparator rising edge has occurred since this flag was last cleared 1 RISING EDGE Comparator rising edge has occurred 4 CPFIF 0 RW Comparator Falling Edge Flag Must be cleared by firmware Value Name Description 0 NOT SET No comparator falling edge has occurred since this flag was last cleared 1 FALLING EDGE Comparator falling edge has o
223. er Lock Security Lock Byte 111111101b 00000010b 1s Complement Flash Pages Locked 3 First two flash pages in user flash user lock byte page The level of flash security depends on the flash access method The three flash access methods that can be restricted are reads writes and erases from the C2 debug interface user firmware executing on unlocked pages and user firmware executing on locked pages Additional restrictions between the two regions of flash are also enforced per the following tables Table 4 2 Flash Security Summary Firmware Permissions Permissions according to the area firmware is executing from Target Area for Read Write Erase Unlocked User Locked User Page Unlocked Data Page Page Locked Data Any Unlocked User Page R W E R W E R W E R W E Locked User Page except user security reset R W E reset R W E page Locked User Security Page reset R W reset R W Any Unlocked Data Page R W E R W E R W E n a Locked Data Page except data security reset R W E n a R W E page Locked Data Security Page reset R W n a R W Read Only Area R R R R Reserved Area reset reset reset reset silabs com Smart Connected Energy friendly Preliminary Rev 0 2 25 EFM8BB2 Reference Manual Flash Memory Permissions according to the area firmware is executi
224. erence Manual Port I O Crossbar External Interrupts and Port Match Bit Name Reset Access Description Value Name Description 0 DISABLED SPI I O unavailable at Port pins 1 ENABLED SPI I O routed to Port pins The SPI can be assigned either 3 or 4 GPIO pins 0 URTOE 0 RW UARTO I O Enable Value Name Description 0 DISABLED UARTO I O unavailable at Port pin 1 ENABLED UARTO TXO RXO routed to Port pins P0 4 and 5 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 86 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 2 XBR1 Port I O Crossbar 1 Bit 7 6 5 4 3 2 1 Reserved 2 1 Access R RW RW RW RW RW Reset 0x0 0 0 0 0 SFR Page 0x0 0x20 SFR Address 0 2 Bit Reset Access Description 7 6 Reserved Must write reset value 5 2 0 RW T2 Enable Value Name Description 0 DISABLED T2 unavailable at Port pin 1 ENABLED T2 routed to Port pin 4 1 0 RW T1 Enable Value Name Description 0 DISABLED T1 unavailable at Port pin 1 ENABLED T1 routed to Port pin 3 TOE 0 RW 0 Enable Value Name Description 0 DISABLED TO unavailable at Port pin 1 ENABLED TO routed to Port pin 2 ECIE 0 RW PCAO External Counter Input Enable Value Name Description 0 DISABLED ECI unavailable at Port pin 1
225. erflow Interrupt Enable This bit sets the masking of the PCA Counter Timer Overflow CF interrupt Value Name Description 0 OVF INT DISABLED Disable the CF interrupt 1 OVF INT ENABLED Enable a PCA Counter Timer Overflow interrupt request when CF is set silabs com Smart Connected Energy friendly Preliminary Rev 0 2 189 EFM8BB2 Reference Manual Programmable Counter Array 16 4 3 PCAOPWM PWM Configuration Bit 7 6 5 1 ARSEL ECOV COVF Reserved CLSEL Access RW RW RW R RW Reset 0 0 0 0 0 0 0 SFR Page 0x0 0x10 SFR Address OxF7 Bit Reset Access Description 7 ARSEL 0 RW Auto Reload Register Select This bit selects whether to read and write the normal PCA capture compare registers or the Auto Reload reg isters at the same SFR addresses This function is used to define the reload value for 9 to 11 bit PWM modes In all other modes the Auto Reload registers have no function Value Name Description 0 CAPTURE COMPARE Read Write Capture Compare Registers at PCAOCPLn 1 AUTORELOAD Read Write Auto Reload Registers at PCAOCPHn and PCAOCPLn 6 ECOV 0 RW Cycle Overflow Interrupt Enable This bit sets the masking of the Cycle Overflow Flag COVF interrupt Value Name Description 0 COVF MASK DISA COVF will not generate PCA interrupts BLED 1 COVF MASK ENA A PCA interrup
226. erflow flag CF which is set upon 16 bit overflow of the PCAO coun ter an intermediate overflow flag COVF which can be set on an overflow from the 8th 11th bit of the PCAO counter and the individu al flags for each PCA channel CCFn which are set according to the operation mode of that module These event flags are always set when the trigger condition occurs Each of these flags can be individually selected to generate a PCAO interrupt using the correspond ing interrupt enable flag for CF ECOV for COVF and ECCFn for each CCFn interrupts must be globally enabled before any individual interrupt sources are recognized by the processor interrupts are globally enabled by setting the EA bit and the bit to logic 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 176 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 3 3 Capture Compare Modules Each module can be configured to operate independently in one of six operation modes edge triggered capture software timer high speed output frequency output 8 to 11 bit pulse width modulator or 16 bit pulse width modulator Table 16 2 PCAOCPM and PCAOPWM Bit Settings for PCA Capture Compare Modules on page 177 summarizes the bit settings in the PCAOCPMn and PCAOPWM registers used to select the PCA capture compare module s operating mode All modules set to use 8 9 10 or 11 bit PWM mode must use the same cycle
227. erved Access RW R RW R Reset 0 0x0 0 SFR Page 0x10 SFR Address OxEF Bit Reset Access Description 7 HFO1EN 0 RW HFOSC1 Oscillator Enable Value Name Description 0 DISABLED Disable High Frequency Oscillator 1 HFOSC1 will still turn on if requested by block in the device 1 ENABLED Force High Frequency Oscillator 1 to run 6 4 Reserved Must write reset value 3 HFOOEN 0 RW HFOSCO Oscillator Enable Value Name Description 0 DISABLED Disable High Frequency Oscillator 0 HFOSCO will still turn on if requested by any block in the device 1 ENABLED Force High Frequency Oscillator O to run 2 0 Reserved Must write reset value silabs com Smart Connected Energy friendly Preliminary Rev 0 2 58 EFM8BB2 Reference Manual Clocking and Oscillators 8 4 5 LFOOCN Low Frequency Oscillator Control Bit 7 6 5 4 3 2 1 0 OSCLEN OSCLRDY OSCLF OSCLD Access RW R RW RW Reset 0 1 Varies 0x3 SFR Page 0x0 0x10 SFR Address 0xB1 Bit Reset Access Description 7 OSCLEN 0 RW Internal L F Oscillator Enable This bit enables the internal low frequency oscillator Note that the low frequency oscillator is automatically enabled when the watchdog timer is active Value Name Description 0 DISABLED Internal L F Oscillator Disabled 1 ENABLED Internal L F Oscillator Enabled 6 OSCLRDY 1 R Internal
228. erved PSEE PSWE Access R RW RW Reset 0x00 0 0 SFR Page ALL SFR Address Ox8F Bit Reset Access Description 7 2 Reserved Must write reset value 1 PSEE 0 RW Program Store Erase Enable Setting this bit in combination with PSWE allows an entire page of flash program memory to be erased If this bit is logic 1 and flash writes are enabled PSWE is logic 1 a write to flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction The value of the data byte written does not matter Value Name Description 0 ERASE DISABLED Flash program memory erasure disabled 1 ERASE ENABLED Flash program memory erasure enabled 0 PSWE 0 RW Program Store Write Enable Setting this bit allows writing a byte of data to the flash program memory using the MOVX write instruction The flash loca tion should be erased before writing data Value Name Description 0 WRITE DISABLED Writes to flash program memory disabled 1 WRITE ENABLED Writes to flash program memory enabled the MOVX write instruction targets flash memory silabs com Smart Connected Energy friendly Preliminary Rev 0 2 29 EFM8BB2 Reference Manual Flash Memory 4 4 2 FLKEY Flash Lock and Key Bit 7 6 5 4 3 2 1 0 Access RW Reset 0x00 SFR Page ALL SFR Address OxB7 Bit Reset Access Description 7 0 F
229. ess or data information is sent by the transmitter the receiver sends an ACK or NACK bit during the ACK phase of the transfer during which time the receiver controls the SDA line Arbitration A master may start a transfer only if the bus is free The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time see e SCL High SMBus Free Timeout on page 220 In the event that two or more devices attempt to begin a transfer at the same time an arbitration scheme is employed to force one master to give up the bus The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW Since the bus is open drain the bus will be pulled LOW The master attempting the HIGH will detect a LOW SDA and lose the arbitration The winning master continues its transmission without interruption the losing master becomes a slave and receives the rest of the transfer if addressed This arbitration scheme is non de structive one device always wins and no data is lost Clock Low Extension SMBus provides a clock synchronization mechanism similar to 12C which allows devices with different speed capabilities to coexist on the bus A clock low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters The slave may temporarily hold the SCL line LOW to extend the clock low period effectively decreasing the serial clock frequency SCL Low Timeout
230. et by hardware on the 9th SCL falling edge when one of the following conditions are met The I2CO Slave responds with ACK and the RX FIFO is full The 2 0 Slave responds with a NACK and the RX FIFO is full The current byte transaction has a matching I2CO Slave address and the 8th bit was a WRITE bit 0 This bit will set the I2COINT bit and generate an interrupt if enabled Software must clear this bit 0 RD 0 RW 2 Read This bit is set by hardware on the 9th SCL falling edge when one of the following conditions are met The I2C Master responds with an ACK and there is no more data in the TX FIFO 12C Master responds with a The current byte transaction has a matching I2C slave address and the 8th bit was a READ bit 1 This bit will set the I2COINT bit and generate an interrupt if enabled Software must clear this bit silabs com Smart Connected Energy friendly Preliminary Rev 0 2 169 EFM8BB2 Reference Manual I2C Slave I2CSLAVEO 15 4 5 2 0 0 12 0 Control Bit 7 6 5 4 3 2 1 0 Reserved PINDRV PINMD TIMEOUT PRELOAD I2COEN BUSY Access R RW RW RW RW RW RW Reset 0x0 0 0 0 1 0 1 SFR Page 0x20 SFR Address 0xBA Bit Reset Access Description 7 6 Reserved Must write reset value 5 PINDRV 0 RW Pin Drive Strength When this bit is set the SCL and SDA pins will use high d
231. et value 4 4 0 RW Timer 4 Interrupt Priority Control MSB This bit sets the MSB of the priority field for the Timer 4 interrupt 3 PHI2CO 0 RW 12 0 Slave Interrupt Priority Control MSB This bit sets the MSB of the priority field for the 2 0 Slave interrupt 2 PHS1 0 RW UART1 Interrupt Priority Control MSB This bit sets the MSB of the priority field for the UART1 interrupt 1 0 Reserved Must write reset value silabs com Smart Connected Energy friendly Preliminary Rev 0 2 46 EFM8BB2 Reference Manual Power Management and Internal Regulators 7 Power Management and Internal Regulators 7 1 Introduction All internal circuitry draws power from the VDD supply pin External I O pins are powered from the VIO supply voltage VDD on devi ces without a separate VIO connection while most of the internal circuitry is supplied by an on chip LDO regulator Control over the device power can be achieved by enabling disabling individual peripherals as needed Each analog peripheral can be disabled when not in use and placed in low power mode Digital peripherals such as timers and serial buses have their clocks gated off and draw little power when they are not in use Power Distribution VREGIN VDD X 7 10 GND Xx CPU Core Digital I O Interface Peripheral Logic Figure 7 1 Power System Block Diagram Table 7 1 Power Modes Power Mode Details Mode Entry Wake Up Sou
232. evel a fixed order is used to arbitrate based on the interrupt source s location in the interrupt vector table Interrupts with a lower number in the vector table have priority If legacy 8051 operation is desired the bits of the high priority registers and EIPnH should all be configured to 0 Table 6 1 Configurable Interrupt Priority Decoding Priority MSB Priority LSB Priority Level from IPH or EIPnH from IP or EIPn 0 0 Priority 0 lowest priority default 0 1 Priority 1 1 0 Priority 2 1 1 Priority 3 highest priority silabs com Smart Connected Energy friendly Preliminary Rev 0 2 33 EFM8BB2 Reference Manual Interrupts 6 2 2 Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs Pending interrupts are sampled and priority deco ded on every system clock cycle Therefore the fastest possible response time is 5 system clock cycles 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR If an interrupt is pending when a RETI is executed a single instruction is executed before an LCALL is made to service the pending interrupt Therefore the maximum response time for an interrupt when no other interrupt is currently being serviced or the new interrupt is of greater priority occurs when the CPU is performing an RETI instruc tion followed by a DIV as the next instruction In this case the response time
233. even bits of the two registers are used to define which addresses will be ACKed A 1 in a bit of the slave address mask SLVM enables a comparison between the received slave address and the hardware s slave address SLV for that bit A 0 in a bit of the slave address mask means that bit will be treated as a don t care for comparison purposes In this case either a 1 or a 0 value are acceptable on the incoming slave address Additionally if the GC bit in register SMBOADR is set to 1 hard ware will recognize the General Call Address 0x00 Table 18 3 Hardware Address Recognition Examples 1 Hardware Slave Address Slave Address Mask Slave Addresses Recognized by Hardware SLV SLVM 0x34 Ox7F 0 0x34 0x34 0 7 1 0 34 0 00 0 34 Ox7E 0 0x34 0x35 0x34 Ox7E 1 0x34 0x35 0x00 General Call 0 70 0x73 0 0x70 0x74 0x78 0 7 Note These addresses must be shifted to the left by one bit when writing to the SMBOADR register Software ACK Generation In general it is recommended for applications to use hardware ACK and address recognition In some cases it may be desirable to drive ACK generation and address recognition from firmware When the EHACK bit in register SMBOADM is cleared to 0 the firmware on the device must detect incoming slave addresses and ACK or NACK the slave address and incoming data bytes As a receiver writing the ACK bit defines the outgoing ACK value
234. f the received slave address is acknowledged zero or more data bytes are received If hardware ACK generation is disabled the ACKRQ is set to 1 and an interrupt is generated after each received byte Software must write the ACK bit at that time to ACK or NACK the received byte With hardware ACK generation enabled the SMBus hardware will automatically generate the ACK NACK and then post the interrupt It is important to note that the appropriate ACK or NACK value should be set up by the software prior to receiving the byte when hardware ACK generation is enabled The interface exits Slave Receiver Mode after receiving a STOP The interface will switch to Slave Transmitter Mode if SMBODAT is written while an active Slave Receiver Figure 18 9 Typical Slave Write Sequence on page 230 shows a typical slave write sequence as it appears on the bus The corresponding firmware state diagram combined with the slave read sequence is shown in Figure 18 10 Slave State Diagram EHACK 1 on page 231 Two received data bytes are shown though any number of bytes may be re ceived Notice that the data byte transferred interrupts occur at different places in the sequence depending on whether hardware ACK generation is enabled The interrupt occurs before the ACK with hardware ACK generation disabled and after the ACK when hardware ACK generation is enabled Interrupts with Hardware Enabled EHACK 1 Gi E A Data Byte Data Byte p
235. field selects the comparator s negative input CPnN x Note Any port pins selected as comparator inputs should be configured as analog inputs in their associated port configuration register and configured to be skipped by the crossbar silabs com Smart Connected Energy friendly Preliminary Rev 0 2 135 EFM8BB2 Reference Manual Comparators and CMP1 13 3 3 1 Multiplexer Channel Selection Table 13 1 CMPO Positive Input Multiplexer Channels CMXP Setting in Signal Name Enumeration Name QFN28 Pin QSOP24 Pin QFN20 Pin Register Name Name 0000 0 P0 0 P0 0 0001 1 1 1 P0 1 1 0010 2 2 2 2 2 0011 0100 4 4 4 4 4 0101 5 5 5 P0 5 P0 5 0110 6 6 P0 6 P0 6 0111 CMPOP 7 CMPOP7 7 7 7 1000 8 LDO OUT Internal 1 8 V LDO output 1001 CMPOP 9 CMPOP9 P1 0 P1 0 P1 0 1010 CMPOP 10 10 1 1 1 1 1 1 1011 1110 CMPOP 11 14 No connection Reserved 1111 15 VDD VDD Supply Pin Table 13 2 0 Negative Input Multiplexer Channels CMXN Setting in Signal Name Enumeration Name QFN28 Pin QSOP24 Pin QFN20 Pin Regi
236. figured for digital mode 6 B6 1 RW Port 1 Bit 6 Input Mode See bit 7 description 5 B5 1 RW Port 1 Bit 5 Input Mode See bit 7 description 4 B4 1 RW Port 1 Bit 4 Input Mode See bit 7 description 3 B3 1 RW Port 1 Bit 3 Input Mode See bit 7 description 2 B2 1 RW Port 1 Bit 2 Input Mode See bit 7 description 1 B1 1 RW Port 1 Bit 1 Input Mode See bit 7 description 0 BO 1 RW Port 1 Bit 0 Input Mode See bit 7 description Port pins configured for analog mode have their weak pullup digital driver and digital receiver disabled silabs com Smart Connected Energy friendly Preliminary Rev 0 2 99 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 15 P1MDOUT Port 1 Output Mode Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 0x20 SFR Address 0xA5 Bit Reset Access Description 7 B7 0 RW Port 1 Bit 7 Output Mode Value Name Description 0 OPEN_DRAIN P1 7 output is open drain 1 PUSH_PULL P1 7 output is push pull 6 B6 0 RW Port 1 Bit 6 Output Mode See bit 7 description 5 5 0 RW Port 1 Bit 5 Output Mode See bit 7 description 4 B4 0 RW Port 1 Bit 4 Output Mode See bit 7 description 3 B3 0 RW Port 1 Bit 3 Output Mode See bit 7 description 2 B2 0 RW Port 1 Bit 2 Output Mode See bit 7 description 1 B1 0 RW Port 1 Bit 1 Output Mo
237. friendly Preliminary Rev 0 2 150 EFM8BB2 Reference Manual Comparators and CMP1 13 5 4 CMP1CN1 Comparator 1 Control 1 Bit 7 6 4 3 2 1 0 Reserved DACLVL Access RW R RW Reset 0 0 0x00 SFR Page 0x10 SFR Address Bit Reset Access Description 7 CPINH 0 RW Output Inhibit This bit is used to inhibit the comparator output during CEX2 low times Value Name Description 0 DISABLED The comparator output will always reflect the input conditions 1 ENABLED The comparator output will hold state any time the PCA CEX2 channel is low 6 Reserved Must write reset value 5 0 DACLVL 0x00 RW Internal Comparator DAC Reference Level These bits control the output of the comparator reference DAC The voltage is given by DAC Output CMPREF DACLVL 64 CMPREF is the selected input reference for the DAC according to INSL CMXP and CMXN silabs com Smart Connected Energy friendly Preliminary Rev 0 2 151 EFM8BB2 Reference Manual Cyclic Redundancy Check CRCO 14 Cyclic Redundancy Check CRCO 14 1 Introduction The cyclic redundancy check CRC module performs a CRC using a 16 bit polynomial CRCO accepts a stream of 8 bit data and posts the 16 bit result to an internal register In addition to using the CRC block for data manipulation hardware can automatically CRC the flash contents of the device CRCOIN Flash
238. fully operational Idle Core halted Set IDLE bit in PCONO Any interrupt All peripherals clocked and fully operational Code resumes execution wake event Suspend Core and peripheral clocks halted 1 Switch SYSCLK to Timer 4 Event HFOSCO and HFOSC1 oscillators stopped HFOSCO SPIO Activity Regulators in normal bias mode for fast wake 2 Set SUSPEND bitin 2 0 Slave Activity Timer 3 and 4 may clock from LFOSCO Port Match Event Code resumes execution on wake event Comparator 0 Rising Edge Snooze Core and peripheral clocks halted 1 Switch SYSCLK to Timer 4 Event HFOSCO and HFOSC1 oscillators stopped HFOSCO SPIO Activity Regulators in low bias current mode for energy sav 2 Set SNOOZE bit in 12 0 Slave Activity ings Port Match Event Timer 3 and 4 may clock from LFOSCO Comparator 0 Rising Code resumes execution on wake event Edge Shutdown All internal power nets shut down 1 Set STOPCF bit in RSTb pin reset 5V regulator remains active if enabled REGOCN Power on reset Pins retain state 2 Set STOP bit in Exit pin power on reset 1 3 1 0 Digital and analog resources are externally available on the device s multi purpose I O pins Port pins 0 2 3 can be defined as gen eral purpose I O GPIO assigned to one of the internal digital resources through the crossbar or dedicated channels or assi
239. g This bit is set by hardware if a sync measurement in process overflows the baud rate generator This is usually an indica tion that the prescaler must be increased When a sync timeout occurs the baud rate generator is not updated Firmware must clear this bit to 0 Value Name Description 0 NOT_SET A sync timeout has not occured 1 sync timeout occured 4 SYNCD 0 RW LIN Sync Detect Flag This bit is set by hardware after detection of a valid sync word If LINMDE is set the sync word must be part of a valid break sync sequence This flag must be cleared by software Value Name Description 0 NOT SET A sync has not been detected or is not yet complete 1 SYNC DONE A valid sync word was detected 3 LINMDE 0 RW LIN Mode Enable silabs com Smart Connected Energy friendly Enables a full LIN check on incoming data Value Name Description 0 DISABLED If AUTOBDE is set to 1 sync detection and autobaud will begin on the first falling edge of RX Preliminary Rev 0 2 286 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 Bit Reset Access Description 1 ENABLED A valid LIN break field and delimiter must be detected prior to the hardware state machine recognizing a sync word and performing autobaud 2 BREAK 0 RW LIN Break Done Interrupt Enable DNIE Enables the break done interrupt source Value Name Description
240. g a 1 to this bit enables the missing clock detector The MCD triggers a reset if a missing clock condition is detected 1 PORSF Varies RW Power On Supply Monitor Reset Flag and Supply Monitor Reset Enable Read This bit reads 1 anytime a power on or supply monitor reset has occurred Write Writing a 1 to this bit enables the supply monitor as a reset source 0 PINRSF Varies R HW Pin Reset Flag This read only bit is set to 1 if the RSTb pin caused the last reset Reads and writes of the RSTSRC register access different logic in the device Reading the register always returns status information to indicate the source of the most recent reset Writing to the register activates certain options as reset sources It is recommended to not use any kind of read modify write operation on this register When the PORSF bit reads back 1 all other RSTSRC flags are indeterminate Writing 1 to the PORSF bit when the supply monitor is not enabled and stabilized may cause a system reset silabs com Smart Connected Energy friendly Preliminary Rev 0 2 65 EFM8BB2 Reference Manual Reset Sources and Power Supply Monitor 9 4 2 VDMOCN Supply Monitor Control Bit 7 6 5 4 3 2 1 0 VDMEN VDDSTAT Reserved Access RW R R Reset Varies Varies Varies SFR Page 0x0 SFR Address OxFF Bit Reset Access Description 7 VDMEN Varies RW Supply Monitor Enable This bit t
241. g in one of these modes the overflow event from Timer 4 will trigger a wake for the device silabs com Smart Connected Energy friendly Preliminary Rev 0 2 250 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 19 4 Timer 0 1 2 3 and 4 Control Registers 19 4 1 CKCONO Clock Control 0 Bit 7 6 5 4 3 2 1 T3MH T3ML T2MH T2ML T1M TOM SCA Access RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page SFR Address 0 8 Bit Reset Access Description 7 T3MH 0 RW Timer 3 High Byte Clock Select Selects the clock supplied to the Timer 3 high byte split 8 bit timer mode only Value Name Description 0 EXTERNAL_CLOCK Timer 3 high byte uses the clock defined by T3XCLK in TMR3CNO 1 SYSCLK Timer 3 high byte uses the system clock 6 T3ML 0 RW Timer 3 Low Byte Clock Select Selects the clock supplied to Timer 3 Selects the clock supplied to the lower 8 bit timer in split 8 bit timer mode Value Name Description 0 EXTERNAL_CLOCK Timer 3 low byte uses the clock defined by T3XCLK in TMR3CNO 1 SYSCLK Timer 3 low byte uses the system clock 5 T2MH 0 RW Timer 2 High Byte Clock Select Selects the clock supplied to the Timer 2 high byte split 8 bit timer mode only Value Name Description 0 EXTERNAL_CLOCK Timer 2 high byte uses the clock defined by T2XCLK in TMR2CNO 1 SYSCLK Timer 2 high byte uses the sys
242. gh AA 6 3 7 EIE2 Extended Interrupt Enable 2 1145 6 3 8 EIP2 Extended Interrupt 2 46 6 3 9 EIP2H Extended Interrupt Priority 2 High 46 7 Power Management and Internal Regulators 47 T A Introduction 2 5 2 ad cava che Ss ve ca ee SE Ob Blame ta 7 2 5 amp xs 4 46 Ec e x xdTM LA StopMode o dog 5 5 49 ee wc o e re A Wo wow 949 To Suspend Mode 4 oe ROR oue e XO woe CES Ce se 440 76 Snooze Mode 4 ox S Xo Ge BL uA S hi dm E te Jio e 299 7 7 Shutdown Mode 4 2 6 xoxo Goode xo RS ox Ro dA OE 290 7 8 5V to 3 3V Regulator 4 4 2 x 4 ox XR ee 9 7 9 Power Management Control Registers 4 7 9 1 7 9 2 PCON1 Power Control 14 a a a a 1 52 7 9 3 REGOCN Voltage Regulator 0 Control 152 7 9 4 REG1CN Voltage Regulator 1 Control 53 8 Clocking and Oscillators 3 2 2 54 8 1 Introduction 4 8 2 Features i
243. gned to an analog function Port pins P3 0 and P3 1 can be used as GPIO Additionally the C2 Interface Data signal C2D is shared with P3 0 The port control block offers the following features Up to 22 multi functions pins supporting digital and analog functions Flexible priority crossbar decoder for digital peripheral assignment Two drive strength settings for each port e Two direct pin interrupt sources with dedicated interrupt vectors INTO and INT1 Up to 20 direct pin interrupt sources with shared interrupt vector Port Match silabs com Smart Connected Energy friendly Preliminary Rev 0 2 2 EFM8BB2 Reference Manual System Overview 1 4 Clocking The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources By default the system clock comes up running from the 24 5 MHz oscillator divided by 8 The clock control system offers the following features Provides clock to core and peripherals 24 5 MHz internal oscillator HFOSCO accurate to 2 over supply and temperature corners 49 MHz internal oscillator HFOSC1 accurate to 1 5 over supply and temperature corners 80 kHz low frequency oscillator LFOSCO External CMOS clock input EXTCLK Clock divider with eight settings for flexible clock scaling Divide the selected clock source by 1 2 4 8 16 32 64 or 128 HFOSCO and HFOSC 1 include 1 5x pre scalers for further flexibi
244. h byte of the corresponding PCA channel s auto reload value for 9 to 11 bit PWM mode The ARSEL bit in register PCAOPWM controls which register is accessed A write to this register will set the module s ECOM bit to a 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 195 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 4 12 1 PCA Channel 1 Capture Compare Mode Bit 7 6 5 4 3 2 1 0 16 TOG PWM ECCF Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 0x10 SFR Address OxDB Bit Reset Access Description 7 16 0 RW Channel 1 16 bit Pulse Width Modulation Enable This bit enables 16 bit mode when Pulse Width Modulation mode is enabled Value Name Description 0 8 BIT 8 to 11 bit PWM selected 1 16 BIT 16 bit PWM selected 6 ECOM 0 RW Channel 1 Comparator Function Enable This bit enables the comparator function 5 CAPP 0 RW Channel 1 Capture Positive Function Enable This bit enables the positive edge capture capability 4 CAPN 0 RW Channel 1 Capture Negative Function Enable This bit enables the negative edge capture capability 3 MAT 0 RW Channel 1 Match Function Enable This bit enables the match function When enabled matches of the PCA counter with a module s capture compare register cause the CCF1 bit in the PCAOMD register to
245. he internal chip ground is always used during the conversion period regardless of the setting of the GNDSL bit Note The AGND pin is a multi function GPIO pin When using AGND as the ground reference to the ADC AGND should be configured as an analog input and skipped by the crossbar 12 3 3 Input Selection The ADC has an analog multiplexer which allows selection of external pins the on chip temperature sensor the internal regulated sup ply the VDD supply or GND ADC input channels are selected using the ADCOMX register Note Any port pins selected as ADC inputs should be configured as analog inputs in their associated port configuration register and configured to be skipped by the crossbar 12 3 3 1 Multiplexer Channel Selection Table 12 1 ADCO Input Multiplexer Channels setting Signal Enumeration 28 QSOP24 Pin QFN20 Pin Name Name Name 00000 ADCO 0 ADCOPO 0 0 0 0 00001 ADCO 1 ADCOP1 1 P0 1 1 00010 ADCO 2 ADCOP2 P0 2 P0 2 P0 2 00011 ADCO 3 ADCOP3 P0 3 P0 3 P0 3 00100 ADCO 4 ADCOP4 P0 4 P0 4 P0 4 00101 ADCO 5 ADCOP5 P0 5 P0 5 P0 5 00110 ADCO 6 ADCOP6 P0 6 P0 6 6 00111 ADCO 7 ADCOP7 P0 7 0 7 0 7 01000 ADCO 8 ADCOP8 P1 0 P1 0 P1 0 01001 ADCO 9 ADCOP9 P1 1 1 1 1 1 01010 ADCO 10 ADCOP10 P1 2 P1 2 P1 2 01011 ADCO 11 ADCOP 11 P1 3 P1 3 P1 3 01100 ADCO 12 ADCOP12 P1 4 1 4 1 4 01101 ADCO
246. hen the number of bytes in the TX FIFO is less than or equal to the TX FIFO threshold TXTH Value Name Description 0 NOT_SET The number of bytes in the TX FIFO is greater than TXTH 1 SET The number of bytes in the TX FIFO is less than or equal to TXTH 6 TXNF 1 R TX FIFO Not Full This bit indicates when the TX FIFO is full and can no longer be written to If a write is performed when TXNF is cleared to 0 it will replace the most recent byte in the FIFO Value Name Description 0 FULL The TX FIFO is full 1 NOT_FULL The TX FIFO has room for more data 5 4 Reserved Must write reset value 3 RFRQ 0 R Receive FIFO Request Set to 1 by hardware when the number of bytes in the RX FIFO is larger than specified by the RX FIFO threshold RXTH Value Name Description 0 NOT SET The number of bytes in the RX FIFO is less than or equal to RXTH 1 SET The number of bytes in the RX FIFO is greater than RXTH 2 RXE 1 R RX FIFO Empty This bit indicates when the RX FIFO is empty If a read is performed when RXE is set the last byte will be returned Value Name Description 0 NOT EMPTY The RX FIFO contains data 1 EMPTY The RX FIFO is empty 1 0 Reserved Must write reset value silabs com Smart Connected Energy friendly Preliminary Rev 0 2 239 EFM8BB2 Reference Manual System Management Bus I2C SMBO 18 4 9 SMBORXLN SMBus 0 Receive Length Counter Bit 7 6 5 4 3 2 1 0 RXLN Access RW Reset 0x00 SFR P
247. i P1 P3 0 Timer 2 3 4 12 0 Slave uis UART1 Figure 11 1 Port Block Diagram 11 2 Features The port control block offers the following features Up to 22 multi functions pins supporting digital and analog functions Flexible priority crossbar decoder for digital peripheral assignment Two drive strength settings for each port Two direct pin interrupt sources with dedicated interrupt vectors INTO and INT1 Up to 20 direct pin interrupt sources with shared interrupt vector Port Match silabs com Smart Connected Energy friendly Preliminary Rev 0 2 77 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 3 Functional Description 11 3 1 Port Modes of Operation Port pins are configured by firmware as digital or analog I O using the special function registers Port I O initialization consists of the following general steps 1 Select the input mode analog or digital for all port pins using the Port Input Mode register PnMDIN 2 Select the output mode open drain or push pull for all port pins using the Port Output Mode register PRMDOUT 3 Select any pins to be skipped by the I O crossbar using the Port Skip registers PnSKIP 4 Assign port pins to desired peripherals 5 Enable the crossbar XBARE 1 A diagram of the port I O cell is shown in the following figure WEAKPUD Weak Pull Up Disable PxMDOUT x gt 1 for push pull VDD VD
248. ice to implement code loader functions or allow non volatile data stor age To ensure the integrity of flash contents it is strongly recommended that the on chip supply monitor be enabled in any system that includes code that writes and or erases flash memory from software 4 3 2 1 Flash Lock and Key Functions Flash writes and erases by user software are protected with a lock and key function The FLKEY register must be written with the cor rect key codes in sequence before flash operations be performed The key codes 0 5 OxF1 The timing does not mat ter but the codes must be written in order If the key codes are written out of order or the wrong codes are written flash writes and erases will be disabled until the next system reset Flash writes and erases will also be disabled if a flash write or erase is attempted before the key codes have been written properly The flash lock resets after each write or erase the key codes must be written again before another flash write or erase operation can be performed 4 3 2 2 Flash Page Erase Procedure The flash memory is erased one page at a time by firmware using the MOVX write instruction with the address targeted to any byte within the page Before erasing a page of flash memory flash write and erase operations must be enabled by setting the PSWE and PSEE bits in the PSCTL register to logic 1 this directs the MOVX writes to target flash memory and enables page erasure and
249. igure 15 5 Example I2C Write Sequence with the 2 Slave Peripheral on page 163 demonstrates an example sequence including a repeated start and Figure 15 6 12 Write Flow Diagram with the I2C Slave Peripheral on page 164 describes the I2C Write sequence and firmware actions in each interrupt Power S START L 1 L L 1 L L 1 5 9 9 66 90 Read W Write Sr repeated START Shaded blocks are generated by I2C Slave peripheral Figure 15 5 Example I2C Write Sequence with the I2C Slave Peripheral silabs com Smart Connected Energy friendly Preliminary Rev 0 2 163 EFM8BB2 Reference Manual 2 Slave I2CSLAVEO Idle Low Power Interrupt Address W received sent Clear START next byte Ne Clear BUSY et BUSY Data received ACK NACK sent 1 Read data from I2CODIN 2 Clear I2COINT Interrupt Interrupt Stop received 1 Clear STOP 2 Clear I2COINT Idle Low Power Figure 15 6 12 Write Flow Diagram with the I2C Slave Peripheral Note Firmware can leave the BUSY bit as 0 in step F in the Figure 15 5 Example I2C Write Sequence with the I2C Slave Peripheral on page 163 sequence In this case the master will receive an ACK instead at step G could still generate a STOP bit immediately after the ACK silabs com Smart Connected Energy friendly Preliminary Rev 0 2 164 EFM8BB2 Reference Manua
250. in the SMBTC register can be set to 1 to reverse the order in which the SMBus signals are assigned silabs com Smart Connected Energy friendly Preliminary Rev 0 2 222 EFM8BB2 Reference Manual System Management Bus I2C SMBO SMBus Timing Control The SDD field in the SMBTC register is used to restrict the detection of a START condition under certain circumstances In some sys tems where there is significant mismatch between the impedance or the capacitance on the SDA and SCL lines it may be possible for SCL to fall after SDA during an address or data transfer Such an event can cause a false START detection on the bus These kind of events are not expected in a standard SMBus or I2C compliant system Note In most systems this parameter should not be adjusted and it is recommended that it be left at its default value By default if the SCL falling edge is detected after the falling edge of SDA i e one SYSCLK cycle or more the device will detect this as a START condition The SDD field is used to increase the amount of hold time that is required between SDA and SCL falling before a START is recognized An additional 2 4 or 8 SYSCLKs can be added to prevent false START detection in systems where the bus conditions warrant this SMBus Control Register SMBOCNO is used to control the interface and to provide status information The higher four bits of SMBOCNO MASTER TXMODE STA and STO form a status vector that can be u
251. inary Rev 0 2 157 EFM8BB2 Reference Manual I2C Slave I2CSLAVEO 15 12C Slave I2CSLAVEO 15 1 Introduction 2 Slave interface is 2 wire bidirectional serial bus that is compatible with the 2 Bus Specification 3 0 It is capable of transfer ring in high speed mode HS mode at speeds of to 3 4 Mbps Firmware can write to the I2C interface and the 2 interface can autonomously control the serial transfer of data The interface also supports clock stretching for cases where the core may be tempora prohibited from transmitting a byte or processing a received byte during an 2 transaction It can also operate in low power modes without an active system clock and wake the core when a matching slave address is received This module operates only as 12 slave device The I2C Slave peripheral provides control of the SCL serial clock synchronization SDA serial data SCL clock stretching I2C arbitration logic and low power mode operation I2CSLAVEO Module I2CODIN Data em I2CODOUT T State Control Slave Address Timer 4 SCL Low Figure 15 1 IZCSLAVE0 Block Diagram 15 2 Features The I2C module includes the following features Standard up to 100 kbps Fast 400 kbps Fast Plus 1 Mbps and High speed 3 4 Mbps transfer speeds Support for slave mode only Clock low extending clock stretching to interface with faster masters Hardware supp
252. ine must be enabled To enable the prefetch engine both the FLRT and PFEN bit should be set to 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 68 EFM8BB2 Reference Manual CIP 51 Microcontroller Core 10 3 3 Instruction Set The instruction set of the CIP 51 System Controller is fully compatible with the standard MCS 51 instruction set Standard 8051 de velopment tools can be used to develop software for the CIP 51 All CIP 51 instructions are the binary and functional equivalent of their MCS 51 counterparts including opcodes addressing modes and effect on PSW flags However instruction timing is much faster than that of the standard 8051 All instruction timing on the CIP 51 controller is based directly on the core clock timing This is in contrast to many other 8 bit architec tures where a distinction is made between machine cycles and clock cycles with machine cycles taking multiple core clock cycles Due to the pipelined architecture of the CIP 51 most instructions execute in the same number of clock cycles as there are program bytes in the instruction Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken The following table summarizes the instruction set including the mnemonic number of bytes and number of clock cycles for each instruction Table 10 2 CIP 51 Instruction Set Summary Mnemonic Description Cloc
253. ine when the FIFO is full either by reading the TXCNT directly from UART1FCT or by monitoring the TXNF flag TXNF is normally set to 1 when the transmit FIFO is not full indicating that more data may be written Any data written to SBUF1 when the transmit FIFO is full will over write the most recent data written to the buffer and a data byte will be lost In the course of normal operations the transmit FIFO may be maintained with an interrupt based system filling the FIFO as space al lows and servicing any write request interrupts that occur If no more data is to be sent for some period of time the TFRQ interrupt should be disabled by firmware until additional data will be sent In some situations it may be necessary to halt transmission when there is still data in the FIFO To do this firmware should set the TXHOLD bit to 1 If a data byte is currently in progress the UART will finish sending that byte and then halt before the nxet data byte Trasnmission will not continue until TXHOLD is cleared to 0 If it is necessary to flush the contents of the transmit FIFO entirely firmware may do so by writing the TFLSH bit to 1 A flush will reset the internal FIFO counters and the UART will cease sending data Note Hardware will clear the TFLSH bit back to 0 when the flush operation is complete This takes only one SYSCLK cycle so firm ware will always read a on this bit Using the Receive FIFO The receive FIFO also has configuration sett
254. ings which should be established prior to enabling UART reception The RXTH field should be adjusted to the desired level determines when the hardware will generate read requests set the RXRQ flag RXTH acts as a high watermark for the FIFO data and the RXRQ flag will be set any time the number of bytes in the FIFO is greater than the value of RXTH For example if the RXTH field is configured to 0 RXRQ will be set any time there is at least one byte in the receive FIFO Optional Disable RI interrupt by clearing the RIE bit to 0 The RI bit is still used in conjunction with receive FIFO operation any time RI is set to 1 it indicates that the receive FIFO has more data In most applications it is more efficient to use the RXTH field to allow multiple bytes to be received between interrupts Optional Enable RFRQ interrupts by setting the RFRQE bit to 1 and configure the RXTO field to enable receive timeouts Receive timeouts may be adjusted using the RXTO field to occur after 2 4 or 16 idle periods without any activity on the RX pin An idle period is defined as the full length of one transfer at the current baud rate including start stop data and any additional bits Once the receive buffer parameters and interrupts are configured firmware should write the REN bit to 1 to enable data reception Data reception begins when a start condition is recognized on the RX pin Data will be received at the selected baud rate
255. internal watchdog reset and thereby terminate the Idle mode This fea ture protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCONO register If this behavior is not desired the WDT may be disabled by software prior to entering the idle mode if the WDT was initially configured to allow this operation This provides the opportunity for additional power savings allowing the system to remain in the idle mode indefi nitely waiting for an external stimulus to wake up the system 7 4 Stop Mode In stop mode the CPU is halted and peripheral clocks are stopped Analog peripherals remain in their selected states Setting the STOP bit in the PCONO register causes the controller core to enter stop mode as soon as the instruction that sets the bit completes execution Before entering stop mode the system clock must be sourced by HFOSCO In stop mode the CPU and internal clocks are stopped Analog peripherals may remain enabled but will not be provided a clock Each analog peripheral may be shut down individually by firmware prior to entering stop mode Stop mode can only be terminated by an internal or external reset On reset the device performs the normal reset sequence and begins program execution at address 0x0000 If enabled as a reset source the missing clock detector will cause an internal reset and thereby terminate the stop mode If this reset is undesirable in the system and the CPU is to be placed
256. iority field for the Timer 2 interrupt 4 50 0 RW This bit sets the LSB of the priority field for the UARTO interrupt UARTO Interrupt Priority Control LSB 3 PT1 0 RW Timer 1 Interrupt Priority Control LSB This bit sets the LSB of the priority field for the Timer 1 interrupt 2 PX1 0 RW External Interrupt 1 Priority Control LSB This bit sets the LSB of the priority field for the External Interrupt 1 interrupt 1 PTO 0 RW Timer 0 Interrupt Priority Control LSB This bit sets the LSB of the priority field for the Timer 0 interrupt 0 PXO 0 RW External Interrupt 0 Priority Control LSB This bit sets the LSB of the priority field for the External Interrupt O interrupt Preliminary Rev 0 2 39 silabs com Smart Connected Energy friendly EFM8BB2 Reference Manual Interrupts 6 3 3 IPH Interrupt Priority High Bit 7 6 5 4 3 2 1 0 Reserved PHSPIO PHT2 PHSO PHT1 PHX1 PHTO PHXO Access R RW RW RW RW RW RW RW Reset 1 0 0 0 0 0 0 0 SFR Page 7 0x10 SFR Address OxF2 Bit Name Reset Access Description 7 Reserved Must write reset value 6 PHSPIO 0 RW Serial Peripheral Interface SPIO Interrupt Priority Control MSB This bit sets the MSB of the priority field for the SPIO interrupt 5 PHT2 0 RW Timer 2 Interrupt Priority Control MSB This bit sets the MSB of the priority field for the Timer 2 interrupt 4 PHSO 0 RW This bit sets
257. is bit is used to inhibit the comparator output during CEX2 low times Value Name Description 0 DISABLED The comparator output will always reflect the input conditions 1 ENABLED The comparator output will hold state any time the PCA CEX2 channel is low 6 Reserved Must write reset value 5 0 DACLVL 0x00 RW Internal Comparator DAC Reference Level These bits control the output of the comparator reference DAC The voltage is given by DAC Output CMPREF DACLVL 64 CMPREF is the selected input reference for the DAC according to INSL CMXP and CMXN silabs com Smart Connected Energy friendly Preliminary Rev 0 2 146 EFM8BB2 Reference Manual Comparators and CMP1 13 5 CMP1 Control Registers 13 5 1 1 0 Comparator 1 Control 0 Bit 7 6 4 1 0 CPRIF CPFIF CPHYP CPHYN Access RW R RW RW RW RW Reset 0 0 0 0x0 0 0 SFR Page 0x0 0x10 SFR Address Bit Reset Access Description 7 CPEN 0 RW Comparator Enable Value Name Description 0 DISABLED Comparator disabled 1 ENABLED Comparator enabled 6 CPOUT 0 R Comparator Output State Flag Value Name Description 0 POS LESS THAN NE Voltage CP1P lt CP1N G 1 POS GREAT Voltage on CP1P CP1N ER THAN NEG 5 CPRIF 0 RW Comparator Rising Edge Flag Must be cleared by firmware Value Name Des
258. is flag can be cleared by firmware but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine 6 TR1 0 RW Timer 1 Run Control Timer 1 is enabled by setting this bit to 1 5 TFO 0 RW Timer 0 Overflow Flag Set to 1 by hardware when Timer 0 overflows This flag can be cleared by firmware but is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine 4 TRO 0 RW Timer 0 Run Control Timer 0 is enabled by setting this bit to 1 3 IE1 0 RW External Interrupt 1 This flag is set by hardware when an edge level of type defined by IT1 is detected It can be cleared by firmware but is automatically cleared when the CPU vectors to the External Interrupt 1 service routine in edge triggered mode 2 IT1 0 RW Interrupt 1 Type Select This bit selects whether the configured INT1 interrupt will be edge or level sensitive INT1 is configured active low or high by the IN1PL bit in register ITO1CF Value Name Description 0 LEVEL INT1 is level triggered 1 EDGE INT1 is edge triggered 1 IEO 0 RW External Interrupt 0 This flag is set by hardware when an edge level of type defined by ITO is detected It can be cleared by firmware but is automatically cleared when the CPU vectors to the External Interrupt 0 service routine in edge triggered mode 0 ITO 0 RW Interrupt 0 Type Select This bit selects whether the configured INTO interrupt will be edge or level
259. is set to logic 1 to indicate a READ operation and cleared to logic 0 to indicate a WRITE operation All transactions are initiated by a master with one or more addressed slave devices as the target The master generates the START condition and then transmits the slave address and direction bit If the transaction is a WRITE operation from the master to the slave the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte For READ operations the slave transmits the data waiting for an ACK from the master at the end of each byte At the end of the data transfer the master gener ates a STOP condition to terminate the transaction and free the bus Figure 18 3 SMBus Transaction on page 220 illustrates a typical SMBus transaction silabs com Smart Connected Energy friendly Preliminary Rev 0 2 219 EFM8BB2 Reference Manual System Management Bus I2C SMBO 11 SDA SLA6 1 5 0 R W D7 D6 0 START Slave Address R W ACK Data Byte NACK STOP Figure 18 3 SMBus Transaction Transmitter vs Receiver On the SMBus communications interface a device is the transmitter when it is sending an address or data byte to another device on the bus A device is a receiver when an address or data byte is being sent to it from another device on the bus The transmitter con trols the SDA line during the address or data byte After each byte of addr
260. it 7 6 5 4 3 2 1 0 WDTCN Access RW Reset 0x17 SFR Page ALL SFR Address 0x97 Bit Reset Access Description 7 0 WDTCN 0x17 RW WDT Control The WDT control field has different behavior for reads and writes Read When reading the WDTCN register the lower three bits WDTCN 2 0 indicate the current timeout interval Bit WDTCN 4 indicates whether the WDT is active logic 1 or inactive logic O Write Writing the WDTCN register can set the timeout interval enable the WDT disable the WDT reset the WDT or lock the WDT to prevent disabling Writing to WDTCN with the MSB WDTCN 7 cleared to 0 will set the timeout interval to the value bits WDTCN 2 0 Writing OxA5 both enables and reloads the WDT Writing OXDE followed within 4 system clocks by OxAD disables the WDT Writing OXFF locks out the disable feature until the next device reset silabs com Smart Connected Energy friendly Preliminary Rev 0 2 289 EFM8BB2 Reference Manual C2 Debug and Programming Interface 23 C2 Debug and Programming Interface 23 1 Introduction The device includes an on chip Silicon Labs 2 Wire C2 debug interface that allows flash programming and in system debugging with the production part installed in the end application The C2 interface uses a clock signal C2CK and a bi directional C2 data signal C2D to transfer information between the device and a host system Details on the C2 protocol
261. its multiplexer and reference buffers respectively In general these options are used together when operating with a SAR conversion clock frequency of 4 MHz Table 12 5 ADC Optimal Power Configuration 8 and 10 bit Mode Required Reference Source Mode Configuration SAR Clock Speed Other Register Field Set Throughput tings 325 800 ksps Any Always On 12 25 MHz ADCOPWR 0x40 ADEN 1 ADBMEN 0 ADSC 1 ADCOTK N A ADRPT 0 0 325 ksps External Burst Mode 12 25 MHz ADCOPWR 0x44 ADEN 0 ADBMEN 1 ADSC 1 ADCOTK 0x3A ADRPT 0 250 325 ksps Internal Burst Mode 12 25 MHz ADCOPWR 0x44 ADEN 0 ADBMEN 1 ADSC 1 ADCOTK 0x3A ADRPT 0 200 250 ksps Internal Burst Mode 4 08 MHz ADCOPWR OxFO ADEN 0 ADBMEN 1 ADSC 5 ADCOTK N A ADRPT 0 0 200 ksps Internal Burst Mode 4 08 MHz ADCOPWR OxF4 ADEN 0 ADBMEN 1 ADSC 5 ADCOTK 0x34 ADRPT 0 Notes 1 For always on configuration ADSC settings assume SYSCLK is the internal 24 5 MHz high frequency oscillator Adjust ADSC as needed if using a different source for SYSCLK 2 ADRPT reflects the minimum setting for this bit field When using the ADC in Burst Mode up to 64 samples may be auto accumu lated per conversion start by adjusting ADRPT Table 12 6 ADC Optimal Power Configuration 12 bit Mode Required Reference Source Mode Configuration SAR Clock Speed Other Register Field Set Throughput tings 180 200 ksps
262. ived data from being orphaned in the receive buffer Both the receive and transmit FIFOs are configured using the UART1FCNO and UART1FCN1 registers and the number of bytes in the FIFOs be determined at any time by reading UART1FCT silabs com Smart Connected Energy friendly Preliminary Rev 0 2 273 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 Using the Transmit FIFO Prior to using the transmit FIFO the appropriate configuration settings for the application should be established The TXTH field should be adjusted to the desired level TXTH determines when the hardware will generate write requests and set the TXRQ flag TXTH acts as a low watermark for the FIFO data and the TXRQ flag will be set any time the number of bytes in the FIFO is less than or equal to the value of TXTH For example if the TXTH field is configured to 1 TXRQ will be set any time there are zero or one bytes left to send in the transmit FIFO Disable TI interrupts by clearing the TIE bit to O TI will still be set at the completion of every byte sent from the UART but the TI flag is typically not used in conjunction with the FIFO Enable TFRQ interrupts by setting the TFRQE bit to 1 As with basic data transfer data transmission is initiated when software writes a data byte to the SBUF1 register However software may continue to write bytes to the buffer until the transmit FIFO is full Software may determ
263. ively without CPU intervention Table 12 4 Using ADSJST for Output Formatting Input Voltage Repeat Count 4 Repeat Count 16 Repeat Count 64 Shift Right 1 Shift Right 2 Shift Right 3 11 Bit Result 12 Bit Result 12 Bit Result VREF x 1023 1024 0x07F7 OxOFFC Ox1FF8 VREF x 512 1024 0x0400 0x0800 0x1000 VREF x 511 1024 OxO3FE 0 04 OxOFF8 0 0x0000 0x0000 0x0000 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 119 EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 3 11 Power Considerations The ADC has several power saving features which can help the user optimize power consumption according to the needs of the appli cation The most efficient way to use the ADC for slower sample rates is by using burst mode Burst mode dynamically controls power to the ADC and if used the internal voltage reference By completely powering off these circuits when the ADC is not tracking or con verting the average supply current required for lower sampling rates is reduced significantly The ADC also provides low power options that allow reduction in operating current when operating at low SAR clock frequencies or with longer tracking times The internal common mode buffer can be configured for low power mode by setting the ADLPM bit in ADCOPWR to 1 Two other fields in the ADCOPWR register ADBIAS and ADMXLP may be used together to adjust the power consumed by the ADC and
264. k Cycles prefetch off prefetch on Arithmetic Operations ADD A Rn Add register to A 1 1 1 ADD A direct Add direct byte to A 2 2 2 ADD A Ri Add indirect RAM to A 1 2 2 ADD A data Add immediate to A 2 2 2 ADDC A Rn Add register to A with carry 1 1 1 ADDC A direct Add direct byte to A with carry 2 2 2 ADDC A Ri Add indirect RAM to A with carry 1 2 2 ADDC A data Add immediate to A with carry 2 2 2 SUBB A Rn Subtract register from A with borrow 1 1 1 SUBB A direct Subtract direct byte from A with borrow 2 2 2 SUBB A Ri Subtract indirect RAM from A with borrow 1 2 2 SUBB A data Subtract immediate from A with borrow 2 2 2 INCA Increment A 1 1 1 INC Rn Increment register 1 1 1 INC direct Increment direct byte 2 2 2 INC Ri Increment indirect RAM 1 2 2 DECA Decrement A 1 1 1 DEC Rn Decrement register 1 1 1 DEC direct Decrement direct byte 2 2 2 DEC Ri Decrement indirect RAM 1 2 2 INC DPTR Increment Data Pointer 1 1 1 MUL AB Multiply A and B 1 4 4 DIV AB Divide A by B 1 8 8 DAA Decimal adjust A 1 1 1 Logical Operations ANL A Rn AND Register to A 1 1 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 69 EFM8BB2 Reference Manual CIP 51 Microcontroller Core Mnemonic Description Clock Cycles prefetch off prefetch on
265. l I2C Slave I2CSLAVEO 2 Read Sequence 2 Read sequence with the 2 Slave peripheral consists of a series of interrupts and required actions in each interrupt The read sequence consists of the following steps 1 An incoming START and Address R byte causes the peripheral to exit idle mode or wakes the device from a low power state The peripheral will automatically ACK a matching address if BUSY is cleared to 0 2 An interrupt occurs after the automatic ACK of the address The 2 peripheral holds the SCL line low for clock streching until firm ware clears I2COINT Firmware should read the data from the master and take the actions indicated by Figure 15 8 12 Read Flow Diagram with the 12 Slave Peripheral on page 166 3 Firmware writes one or more bytes of data to the master on each subsequent data interrupt 4 The master sends a NACKwhen the current data transfer completes and either a repeated START or STOP 5 The master sends a STOP when the entire data transfer completes Figure 15 7 Example 2 Read Sequence with the 2 Slave Peripheral on 165 demonstrates an example sequence including repeated start and Figure 15 8 2 Read Flow Diagram with the 2 Slave Peripheral on page 166 describes the 2 Read sequence and firmware actions in each interrupt Power S START STOP A ACK R Read W Write Sr repeated START Shaded blocks are genera
266. l clock and the system clock for either timer Value Name Description 0x0 SYSCLK DIV 12 Timer 3 clock is the system clock divided by 12 0 1 EXTOSC DIV 8 Timer 3 clock is the external oscillator divided by 8 synchronized with SYSCLK when not in suspend or snooze mode 0 3 LFOSC DIV 8 Timer 3 clock is the low frequency oscillator divided by 8 synchronized with SYSCLK when not in suspend or snooze mode silabs com Smart Connected Energy friendly Preliminary Rev 0 2 261 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 19 4 20 TMR3CN1 Timer 3 Control 1 Bit 7 6 5 4 3 2 1 0 Reserved T3CSEL Access RW RW Reset 0x00 Ox1 SFR Page 0x10 SFR Address OxFE Bit Reset Access Description 7 3 Reserved Must write reset value 2 0 T3CSEL 0 1 RW Timer 3 Capture Select When used in capture mode the T3CSEL register selects the input capture signal Value Name Description 0x0 PIN Capture high to low transitions on the T2 input pin 0 1 LFOSC Capture high to low transitions of the LFO oscillator 0 2 COMPARATORO Capture high to low transitions of the Comparator 0 output 19 4 21 TMR4RLL Timer 4 Reload Low Byte Bit 7 6 5 4 3 2 1 0 TMR4RLL Access RW Reset 0x00 SFR Page 0x10 SFR Address 0 2 Bit Name Reset Access Description 7 0 TMR4RLL 0x00 RW Timer 4 Reload Low Byt
267. l the NSS pin will output This configuration should only be used when operating the SPI as a master device The setting of NSSMD bits affects the pinout of the device When in 3 wire master or 3 wire slave mode the NSS pin will not be map ped by the crossbar In all other modes the NSS signal will be mapped to a pin on the device Master Device Slave Device MISO 54 55 5 Figure 17 2 4 Wire Connection Diagram Master Device Slave Device MOSI 7 ya MOSI Figure 17 3 3 Wire Connection Diagram silabs com Smart Connected Energy friendly Preliminary Rev 0 2 201 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO Master Device 1 Slave Device y SCK MISO 54 x MISO aec 50 QTY port pin XA Master Device 2 55 MISO SCK Figure 17 4 Multi Master Connection Diagram 17 3 2 Master Mode Operation An SPI master device initiates all data transfers on a SPI bus It drives the SCK line and controls the speed at which data is transferred To place the SPI in master mode the MSTEN bit should be set to 1 Writing a byte of data to the SPInDAT register writes to the trans mit buffer If the SPI shift register is empty a byte is moved from the transmit buffer into the shift register and a bi directional data transfer begins The SPI module provides the serial clock on SCK while simultaneously shifting data out of the shift register MSB first on MOS
268. lete and window compare interrupts supported Flexible output data formatting Includes an internal fast settling reference with two levels 1 65 V and 2 4 V and support for external reference and signal ground Integrated temperature sensor silabs com Smart Connected Energy friendly Preliminary Rev 0 2 6 EFM8BB2 Reference Manual System Overview Low Current Comparators 0 CMP1 Analog comparators are used to compare the voltage of two analog inputs with a digital output indicating which input voltage is higher External input connections to device I O pins and internal connections are available through separate multiplexers the positive and negative inputs Hysteresis response time and current consumption may be programmed to suit the specific needs of the application The comparator includes the following features Up to 10 CMPO or 12 1 external positive inputs Up to 10 CMPO or 12 1 external negative inputs Additional input options Internal connection to LDO output Direct connection to GND Direct connection to VDD Dedicated 6 bit reference DAC Synchronous and asynchronous outputs can be routed to pins via crossbar Programmable hysteresis between 0 and 20 mV Programmable response time Interrupts generated on rising falling or both edges PWM output kill feature 1 8 Reset Sources Reset circuitry allows the controller to be easily placed in a predefined d
269. lity 1 5 Counters Timers and PWM Programmable Counter Array 0 The programmable counter array PCA provides multiple channels of enhanced timer and PWM functionality while requiring less CPU intervention than standard counter timers The PCA consists of a dedicated 16 bit counter timer and one 16 bit capture compare mod ule for each channel The counter timer is driven by a programmable timebase that has flexible external and internal clocking options Each capture compare module may be configured to operate independently in one of five modes Edge Triggered Capture Software Timer High Speed Output Frequency Output or Pulse Width Modulated PWM Output Each capture compare module has its own associated I O line CEXn which is routed through the crossbar to port I O when enabled 16 bit time base Programmable clock divisor and clock source selection Up to three independently configurable channels 8 9 10 11 and 16 bit PWM modes center or edge aligned operation Output polarity control Frequency output mode Capture on rising falling or any edge Compare function for arbitrary waveform generation Software timer internal compare mode Can accept hardware signal from comparator 0 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 3 EFM8BB2 Reference Manual System Overview Timers Timer 0 Timer 1 Timer 2 Timer 3 and Timer 4 Several counter timers are in
270. lock 19 4 2 CKCON1 Clock Control 1 Bit 7 6 5 4 3 2 1 0 Reserved TAMH Access R RW RW Reset 0x00 0 0 SFR Page 0x10 SFR Address 0xA6 Bit Name Reset Access Description 7 2 Reserved Must write reset value 1 0 RW Timer 4 High Byte Clock Select Selects the clock supplied to the Timer 4 high byte split 8 bit timer mode only Value Name Description 0 EXTERNAL CLOCK Timer 4 high byte uses the clock defined by TAXCLK in TMRACNO 1 SYSCLK Timer 4 high byte uses the system clock 0 T4ML 0 RW Timer 4 Low Byte Clock Select Selects the clock supplied to Timer 4 If Timer 4 is configured in split 8 bit timer mode this bit selects the clock supplied to the lower 8 bit timer Value Name Description 0 EXTERNAL_CLOCK Timer 4 low byte uses the clock defined by T4XCLK in TMR4CNO 1 SYSCLK Timer 4 low byte uses the system clock silabs com Smart Connected Energy friendly Preliminary Rev 0 2 252 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 19 4 3 TCON Timer 0 1 Control Bit 7 6 5 4 3 2 1 0 TF1 TR1 TFO TRO IE1 IT1 IEO ITO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0x88 bit addressable Bit Reset Access Description 7 TF1 0 RW Timer 1 Overflow Flag Set to 1 by hardware when Timer 1 overflows Th
271. lock source for Timer 2 If Timer 2 is in 8 bit mode T2XCLK selects the external oscillator clock source for both timer bytes However the Timer 2 Clock Select bits T2MH and T2ML may still be used to select between the external clock and the system clock for either timer Value Name Description 0x0 SYSCLK DIV 12 Timer 2 clock is the system clock divided by 12 0 1 EXTOSC DIV 8 Timer 2 clock is the external oscillator divided by 8 synchronized with SYSCLK silabs com Smart Connected Energy friendly Preliminary Rev 0 2 257 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 19 4 10 TMR2RLL Timer 2 Reload Low Byte Bit 7 6 5 4 3 2 1 0 TMR2RLL Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address 0xCA Bit Reset Access Description 7 0 TMR2RLL 0x00 RW Timer 2 Reload Low Byte When operating in one of the auto reload modes TMR2RLL holds the reload value for the low byte of Timer 2 TMR2L When operating in capture mode TMR2RLL is the captured value of TMR2L 19 4 11 TMR2RLH Timer 2 Reload High Byte Bit 7 6 5 4 3 2 1 0 TMR2RLH Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address OxCB Bit Reset Access Description 7 0 TMR2RLH 0x00 RW Timer 2 Reload High Byte When operating in one of the auto reload modes TMR2RLH holds the reload value for the high byte of Timer 2 TMR2H
272. lowing events occur The processor core halts program execution Special Function Registers SFRs are initialized to their defined reset values External port pins are placed in a known state Interrupts and timers are disabled SFRs are reset to the predefined reset values noted in the detailed register descriptions The contents of internal data memory are unaffected during a reset any previously stored data is preserved However since the stack pointer SFR is reset the stack is effective ly lost even though the data on the stack is not altered The port I O latches are reset to OxFF all logic ones open drain mode Weak pullups are enabled during and after the reset For Supply Monitor and power on resets the RSTb pin is driven low until the device exits the reset state Note During a power on event there may be a short delay before the POR circuitry fires and the RSTb pin is driven low During that time the RSTb pin will be weakly pulled to the supply pin On exit from the reset state the program counter PC is reset the watchdog timer is enabled and the system clock defaults to an internal oscillator Program execution begins at location 0 0000 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 61 EFM8BB2 Reference Manual Reset Sources and Power Supply Monitor 9 3 2 Power On Reset During power up the POR circuit fires When POR fires the device is held in a reset state and the
273. ly Preliminary Rev 0 2 212 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO Reset Access Description 1 ENABLED Enable the SPI module 17 4 3 SPIOCKR SPIO Clock Rate Bit 7 6 4 3 2 1 0 SPIOCKR Access RW Reset 0x00 SFR Page 0x0 0x20 SFR Address 2 Bit 7 0 Name Reset Access Description SPIOCKR 0x00 RW SPIO Clock Rate These bits determine the frequency of the SCK output when the SPIO module is configured for master mode operation The SCK clock frequency is a divided version of the system clock and is given in the following equation where SYSCLK is the system clock frequency and SPIOCKR is the 8 bit value held in the SPIOCKR register fsck SYSCLK 2 SPIOCKR 1 for 0 lt SPIOCKR lt 255 17 4 4 SPIODAT SPIO Data Bit 7 6 5 4 3 2 1 0 SPIODAT Access RW Reset Varies SFR Page 0x0 0x20 SFR Address OxA3 Bit 7 0 Reset Access Description SPIODAT Varies RW SPIO Transmit and Receive Data The SPIODAT register is used to transmit and receive SPIO data Writing data to SPIODAT places the data into the transmit buffer and initiates a transfer when in master mode A read of SPIODAT returns the contents of the receive buffer silabs com Smart Connected Energy friendly Preliminary Rev 0 2 213 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO 17 4 5 SPIO
274. may be transmitted Notice that all of the data byte transferred interrupts occur after the ACK cycle in this mode regardless of whether hardware ACK generation is enabled Interrupts with Hardware Enabled EHACK 1 Interrupts with Hardware ACK Disabled 0 Received by SMBus S START Interface STOP 5 R READ Transmitted by SLA Slave Address SMBus Interface Figure 18 11 Typical Slave Read Sequence silabs com Smart Connected Energy friendly Preliminary Rev 0 2 232 EFM8BB2 Reference Manual System Management Bus I2C SMBO 18 4 SMBO Control Registers 18 4 1 SMBOCF SMBus 0 Configuration Bit 7 6 5 4 3 2 1 0 5 BUSY EXTHOLD SMBTOE SMBFTE SMBCS Access RW RW R RW RW RW RW Reset 0 0 0 0 0 0 SFR Page 0x0 0x20 SFR Address OxC1 Bit Reset Access Description 7 ENSMB 0 RW SMBus Enable This bit enables the SMBus interface when set to 1 When enabled the interface constantly monitors the SDA and SCL pins 6 INH 0 RW SMBus Slave Inhibit When this bit is set to logic 1 the SMBus does not generate an interrupt when slave events occur This effectively removes the SMBus slave from the bus Master Mode interrupts are not affected 5 BUSY 0 R SMBus Busy Indicator This bit is set to logic 1 by hardware when a transfer is in progress It is cleared to logic 0 when a STOP
275. n the FIFO Value Name Description 0 FULL The TX FIFO is full 1 NOT_FULL The TX FIFO has room for more data 5 TXHOLD 0 RW Transmit Hold This bit allows firmware to stall transmission until cleared When set the UART will complete any byte transmission in pro gress but no further data will be sent Transmission will continue when the TXHOLD bit is cleared If CTS is used for hard ware flow control either TXHOLD or CTS assertion will cause transmission to stall Value Name Description 0 CONTINUE The UART will continue to transmit any available data in the TX FIFO 1 HOLD The UART will not transmit any new data from the TX FIFO 4 TIE 1 RW Transmit Interrupt Enable This bit enables the TI flag to generate UARTI1 interrupts after each byte is sent regardless of the THTH settings Value Name Description 0 DISABLED The TI flag will not generate UART1 interrupts 1 ENABLED The TI flag will generate UART1 interrupts when it is set 3 RFRQ 0 R Receive FIFO Request Set to 1 by hardware when the number of bytes in the RX FIFO is larger than specified by the RX FIFO threshold RXTH Value Name Description 0 NOT_SET The number of bytes in the RX FIFO is less than or equal to RXTH 1 SET The number of bytes in the RX FIFO is greater than RXTH silabs com Smart Connected Energy friendly Preliminary Rev 0 2 284 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 Bit Name Reset Access
276. n the PCAOCPMn register enables Software Timer mode Note When writing a 16 bit value to the PCAO Capture Compare registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMn bit to 0 writing to PCAOCPHn sets ECOMn to 1 PCAOCPLn Interrupt Flag Clock Figure 16 3 PCA Software Timer Mode Diagram silabs com Smart Connected Energy friendly Preliminary Rev 0 2 179 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 3 6 High Speed Output Mode In High Speed Output mode a module s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module s 16 bit capture compare register and PCAOCPLn When a match occurs the capture compare flag CCFn in PCAOCNO is set to logic 1 An interrupt request is generated if the CCFn interrupt for that module is enabled The CCFn bit is not auto matically cleared by hardware when the CPU vectors to the interrupt service routine It must be cleared by software Setting the TOGn MATn and ECOMn bits in the PCAOCPMn register enables the High Speed Output mode If ECOMn is cleared the associated retains its state and not toggle on the next match event Note When writing a 16 bit value to the Capture Compare registers the low byte should always be written first Writing to PCA
277. n the voltage regulator is disabled If the regulator is not used in a system the VREGIN and VDD pins should be connected together Firmware may disable the regulator by writing both the REG1ENB and BIASENB bits in REG1CN to turn off the regulator and all associated bias currents silabs com Smart Connected Energy friendly Preliminary Rev 0 2 50 EFM8BB2 Reference Manual Power Management and Internal Regulators 7 9 Power Management Control Registers 7 9 1 PCONO Power Control Bit 7 6 5 4 3 2 1 0 5 GF4 GF3 GF2 GF1 STOP IDLE Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0x87 Bit Reset Access Description 7 GF5 0 RW General Purpose Flag 5 This flag is a general purpose flag for use under firmware control 6 GF4 0 RW General Purpose Flag 4 This flag is a general purpose flag for use under firmware control 5 GF3 0 RW General Purpose Flag 3 This flag is a general purpose flag for use under firmware control 4 GF2 0 RW General Purpose Flag 2 This flag is a general purpose flag for use under firmware control 3 GF1 0 RW General Purpose Flag 1 This flag is a general purpose flag for use under firmware control 2 GFO 0 RW General Purpose Flag 0 This flag is a general purpose flag for use under firmware control 1 STOP 0 RW Stop Mode Select Setting this bit will place the CIP 51
278. nary Rev 0 2 290 EFM8BB2 Reference Manual C2 Debug and Programming Interface 23 4 C2 Interface Registers 23 4 1 C2ADD C2 Address Bit 7 6 5 4 3 2 1 0 C2ADD Access RW Reset 0x00 This register is part of the C2 protocol Bit Reset Access Description 7 0 C2ADD 0x00 RW C2 Address The C2ADD register is accessed via the C2 interface The value written to C2ADD selects the target data register for C2 Data Read and Data Write commands 0x00 C2DEVID 0x01 C2REVID 0x02 C2FPCTL 0 4 C2FPDAT 23 4 2 C2DEVID C2 Device ID Bit 7 6 4 3 2 1 0 C2DEVID Access R Reset 0x32 C2 Address 0x00 Reset Access Description 7 0 C2DEVID 0x32 R Device ID This read only register returns the 8 bit device ID 23 4 3 C2REVID C2 Revision ID Bit 7 6 4 3 2 1 0 2 Access R Reset Varies C2 Address 0x01 Reset Access Description 7 0 C2REVID Varies R Revision ID This read only register returns the 8 bit revision ID For example 0x02 Revision A silabs com Smart Connected Energy friendly Preliminary Rev 0 2 291 EFM8BB2 Reference Manual C2 Debug and Programming Interface 23 4 4 C2FPCTL C2 Flash Programming Control Bit 7 6 5 4 3 2 1 0 C2FPCTL Access RW Reset 0x00 C2 Address 0x02 Bit Name Reset Access Description 7 0 C2FPCTL 0x00
279. nce Once set these bits remain set until cleared by software The comparator rising edge interrupt mask is enabled by setting CPRIE to a logic 1 The com parator falling edge interrupt mask is enabled by setting CPFIE to a logic 1 False rising edges and falling edges may be detected when the comparator is first powered on or if changes are made to the hysteresis or response time control bits Therefore it is recommended that the rising edge and falling edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed before enabling comparator interrupts 13 3 4 1 Output Inversion The output state of the comparator may be inverted using the CPINV bit in register CMPnMD When CPINV is 0 the output reflects the non inverted state CPOUT will be 1 when gt CP and 0 when lt CP When CPINV is set to 1 the output reflects the inverted state CPOUT will be 0 when gt CP and 1 when CP Output inversion is applied directly at the comparator module output and affects the signal anywhere else it is used in the system silabs com Smart Connected Energy friendly Preliminary Rev 0 2 140 EFM8BB2 Reference Manual Comparators and CMP1 13 3 4 2 Output Inhibit The comparator module includes a feature to inhibit output changes whenever the PCA s CEX2 channel is logic low This can be used to prevent undersirable glitches during known noise ev
280. nd CMP is connected to GND The internal DAC is not active 0 2 DAC CMXN Connect the CMP input to the internal DAC output and CMP is selected by CMXN The internal DAC uses the signal specified by CMXP as its full scale ref erence silabs com Smart Connected Energy friendly Preliminary Rev 0 2 149 EFM8BB2 Reference Manual Comparators and CMP1 Bit Reset Access Description 0x3 CMXP_DAC Connect the CMP input to the internal DAC output and CMP is selected by CMXP The internal DAC uses the signal specified by CMXN as its full scale ref erence 1 0 CPMD 0 2 RW Comparator Mode Select These bits affect the response time and power consumption of the comparator Value Name Description 0 0 MODEO Mode 0 Fastest Response Time Highest Power Consumption 0 1 MODE1 Mode 1 0x2 MODE2 Mode 2 0x3 MODE3 Mode 3 Slowest Response Time Lowest Power Consumption 13 5 3 1 Comparator 1 Multiplexer Selection Bit 7 6 4 3 2 1 0 CMXN CMXP Access RW RW Reset OxF OxF SFR Page 0x0 0x10 SFR Address OxAA Bit Reset Access Description 7 4 CMXN OxF RW Comparator Negative Input MUX Selection This field selects the negative input for the comparator 3 0 CMXP OxF RW Comparator Positive Input MUX Selection This field selects the positive input for the comparator silabs com Smart Connected Energy
281. ndow Compare 0x004B 9 EIE1 EWADCO ADCOCNO ADWINT ADCO End of Conversion 0x0053 10 EIE1 EADCO ADCOCNO ADINT 0 005 11 EIE1 EPCAO PCAOCPMO ECCF PCAOCNO CCFO PCAOCPM1 ECCF PCAOCNO CCF1 PCAOCPM2 ECCF PCAOCNO CCF2 PCAOPWM ECOV PCAOCNO CF PCAOPWM COVF Comparator 0 0x0063 12 EIE1 ECPO CMPOMD CPRIE CMPOCNO CPFIF CMPOMD CPFIE CMPOCNO CPRIF Comparator 1 0 006 13 CMP1MD CPFIE CMP1CNO CPFIF CMP1MD CPRIE CMP1CNO CPRIF Timer 3 Overflow Cap 0 0073 14 EIE1 ET3 TMR3CNO TF3CEN TMR3CNO TMR3CNO TF3LEN TMR3CNO Reserved 0x007B 15 Reserved 0x0083 16 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 35 EFM8BB2 Reference Manual Interrupts Interrupt Source Priority Primary Enable Auxiliary Enable s 1 UART1 0x008B 17 EIE2 ES1 UART1FCNO_RFRQE SCON1_RI UART1FCNO_TFRQE SCON1_TI UART1FCN1_RIE UART1FCN1_RFRQ UART1FCN1_RXTO UART1FCN1_TFRQ UART1FCN1_TIE 2 0 Slave 0x0093 18 EIE2 EI2CO I2COFCNO RFRQE I2COSTAT I2COINT I2COFCNO TFRQE I2COFCN1 RFRQ I2COFCN1 TFRQ Timer 4 Overflow Cap 0x009B 19 EIE2_ET4 TMR4CNO_TF4CEN TMR4CNO_TF4H ture TMR4CNO_TF4LEN TMR4CNO_TF4L silabs com Smart Connected Energy friendly Preliminary Rev 0 2 36 EFM8BB2 Reference Manual Interrupts 6 3 Interrupt Control Registers 6 3 1 IE Interrupt Enable Bit 7 6 5 4 3 2 1 0
282. ng from Target Area for Read Write Erase Unlocked User Locked User Page Unlocked Data Locked Data Page R Read permitted W Write permitted Erase permitted reset Flash error reset triggered n a Not applicable Table 4 3 Flash Security Summary C2 Permissions Target Area for Read Write Erase Permissions from C2 interface Any Unlocked User Page R W E Any Locked User Page Device Erase Only Any Unlocked Data Page R W E Any Locked Data Page Device Erase Only Read Only Area R Reserved Area None R Read permitted W Write permitted E Erase permitted Device Erase Only No read write or individual page erase is allowed Must erase entire flash space None Read write and erase are not permitted 4 3 2 Programming the Flash Memory Writes to flash memory clear bits from logic 1 to logic 0 and can be performed on single byte locations Flash erasures set bits back to logic 1 and occur only on full pages The write and erase operations are automatically timed by hardware for proper execution data polling to determine the end of the write erase operation is not required Code execution is stalled during a flash write erase operation The simplest means of programming the flash memory is through the C2 interface using programming tools provided by Silicon Labs or a third party vendor Firmware may also be loaded into the dev
283. nnected Energy friendly Preliminary Rev 0 2 277 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 4 2 SMOD1 UART1 Mode Bit 7 6 5 4 3 2 1 0 SPT PE SDL XBE SBL Access RW RW RW RW RW RW Reset 0 0 0 0 0 3 0 0 SFR Page 0x20 SFR Address 0x93 Bit Name Reset Access Description 7 MCE 0 RW Multiprocessor Communication Enable This function is not available when hardware parity is enabled Value Name Description 0 MULTI_DISABLED RI will be activated if the stop bits are 1 1 MULTI_ENABLED RI will be activated if the stop bits and extra bit are 1 The extra bit must be ena bled using XBE 6 5 SPT 0 0 RW Parity Type Value Name Description 0x0 ODD PARTY Odd 0 1 EVEN PARITY Even 0x2 MARK PARITY Mark 0x3 SPACE_PARITY Space 4 PE 0 RW Parity Enable This bit activates hardware parity generation and checking The parity type is selected by the SPT field when parity is ena bled Value Name Description 0 PARITY_DISABLED Disable hardware parity 1 PARITY ENABLED Enable hardware parity 3 2 SDL 0x3 RW Data Length Value Name Description 0 0 5 BITS 5 bits 0 1 6 5 6 bits 0x2 7 BITS 7 bits 0x3 8 BITS 8 bits 1 XBE 0 RW Extra Bit Enable When enabled the value of TBX in the SCON1 register will be appended to the data field Value Name Description 0 DISABLED Disable the extra bit
284. nnot force the SCL line high to correct the error condition To solve this problem the 2 protocol specifies that devices participating a transfer must detect any clock cycle held low longer than 25 ms as a timeout condition Devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition For the 2 Slave interface an on chip timer is used to implement SCL low timeouts The SCL low timeout feature is enabled by setting the TIMEOUT bit in I2COCNO The associated timer is forced to reload when SCL is high and allowed to count when SCL is low With the associated timer enabled and configured to overflow after 25 ms and TIMEOUT set the timer interrupt service routine can be used to reset disable and re enable the I2C module in the event of an SCL low timeout silabs com Smart Connected Energy friendly Preliminary Rev 0 2 161 EFM8BB2 Reference Manual I2C Slave I2CSLAVEO High Speed Mode The 12 specification supports High speed mode HS mode transfers which allow devices to transfer data at rates of up to 3 4 Mbps and remain fully downward compatible with slower speed devices This allows HS mode devices to operate in a mixed speed bus sys tem Refer to the 2 Specification for details on the electrical and timing requirements for HS mode operation I2CSLAVEO periph eral is compatible with the 2 HS mode operation without any firmw
285. nput starts the timer counting Setting GATEO to 1 allows the timer to be controlled by the external input signal INTO facilitating pulse width measurements Table 19 3 Timer 0 Run Control Options TRO GATEO INTO INOPL Counter Timer 0 X X X Disabled 1 0 X X Enabled 1 1 0 0 Disabled 1 1 0 1 Enabled 1 1 1 0 Enabled 1 1 1 1 Disabled Note 1 X Don t Care Setting TRO does not force the timer to reset The timer registers should be loaded with the desired initial value before the timer is enabled TL1 and TH1 form the 13 bit register for Timer 1 in the same manner as described above for TLO and THO Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0 The input signal INT1 is used with Timer 1 and IN1PL in register ITO1CF determines the INT1 state that starts Timer 1 counting silabs com Smart Connected Energy friendly Preliminary Rev 0 2 243 EFM8BB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 and Timer4 Pre scaled Clock SYSCLK TLO THO Interrupt Flag Figure 19 1 TO Mode 0 Block Diagram Mode 1 16 bit Counter Timer Mode 1 operation is the same as Mode 0 except that the counter timer registers use all 16 bits The counter timers are enabled and configured in Mode 1 in the same manner as for Mode 0 The overflow rate for Timer 0 in 16 bit mode is F F input Clock _ F input Clock TIMERO 216
286. ns 11 3 2 1 Port I O Analog Assignments The following table displays the potential mapping of port I O to each analog function Table 11 1 Port I O Assignment for Analog Functions Analog Function Potentially Assignable Port Pins SFR s Used For Assignment ADC Input 0 P2 3 ADCOMX PnSKIP PnMDIN Comparator 0 Input P0 0 P1 2 PnSKIP PnMDIN Comparator 1 Input P1 0 P2 3 CMP1MX PnSKIP PnMDIN Voltage Reference VREF P0 0 REFOCN PnSKIP PnMDIN Reference Ground AGND PO 1 REFOCN PnSKIP PnMDIN silabs com Smart Connected Energy friendly Preliminary Rev 0 2 79 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 3 2 2 Port I O Digital Assignments The following table displays the potential mapping of port I O to each digital function Table 11 2 Port I O Assignment for Digital Functions Digital Function UARTO UART1 SPIO SMBO CPOA CP1 CP1A SYSCLK 2 and 1 T2 3 4 Potentially Assignable Port Pins Any port pin available for assignment by the crossbar This includes P0 0 P2 3 pins which have their PnSKIP bit set to 0 The crossbar will always assign UARTO pins to P0 4 and 5 SFR s Used For Assignment XBRO XBR1 XBR2 12 0 Slave P1 1 P1 2 QFN20 I2COCNO P1 5 P1 6 QFN28 QSOP24 External Interrupt 0 External Interrupt 1 P0 0
287. nternal shift register Serial Clock SCK The SCK signal is an output from the master device and an input to slave devices It is used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines The SPI module generates this signal when operating as a master and receives it as a slave The SCK signal is ignored by a SPI slave when the slave is not selected in 4 wire slave mode Slave Select NSS The function of the slave select NSS signal is dependent on the setting of the NSSMD bitfield There are three possible modes that can be selected with these bits NSSMD 1 0 00 3 Wire Master or 3 Wire Slave Mode The SPI operates in 3 wire mode and NSS is disabled When operating as a slave device the SPI is always selected in 3 wire mode Since no select signal is present the SPI must be the only slave on the bus in 3 wire mode This is intended for point to point communication between a master and a single slave NSSMD 1 0 01 4 Wire Slave or Multi Master Mode The SPI operates in 4 wire mode and NSS is configured as an input When operating as a slave NSS selects the SPI device When operating as a master a 1 to 0 transition of the NSS signal disables the master function of the SPI module so that multiple master devices can be used on the same SPI bus NSSMD 1 0 1x 4 Wire Master Mode The SPI operates in 4 wire mode and NSS is enabled as an output The setting of NSSMDO determines what logic leve
288. nts of a snapshot register whose contents are updated only when the contents of PCAOL are read 16 4 7 PCAOPOL PCA Output Polarity Bit 7 6 5 4 3 2 1 0 Reserved CEX2POL CEX1POL CEXOPOL Access R RW RW RW Reset 0x00 0 0 0 SFR Page 7 0x0 0x10 SFR Address 0x96 Bit Reset Access Description 7 3 Reserved Must write reset value 2 CEX2POL 0 RW CEX2 Output Polarity Selects the polarity of the CEX2 output channel When this bit is modified the change takes effect at the pin immediately Value Name Description 0 DEFAULT Use default polarity 1 INVERT Invert polarity 1 CEX1POL 0 RW CEX1 Output Polarity Selects the polarity of the CEX1 output channel When this bit is modified the change takes effect at the pin immediately Value Name Description 0 DEFAULT Use default polarity 1 INVERT Invert polarity 0 CEXOPOL 0 RW CEXO0 Output Polarity Selects the polarity of the CEXO output channel When this bit is modified the change takes effect at the pin immediately Value Name Description 0 DEFAULT Use default polarity 1 INVERT Invert polarity silabs com Smart Connected Energy friendly Preliminary Rev 0 2 192 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 4 8 PCAOCENT PCA Center Alignment Enable Bit 7 6 5 4 3 2 1 0 Reserved CEX2CEN CEX1CEN CEXOCEN Access R RW RW RW Reset 0x00 0 0
289. nversion can be initiated in many ways depending on the programmed state of the ADCM bitfield Conversions may be initiated by one of the following 1 Software triggered Writing a 1 to the ADBUSY bit initiates the conversion 2 Hardware triggered An automatic internal event such as a timer overflow initiates the conversion 3 External pin triggered A rising edge on the CNVSTR input signal initiates the conversion Writing a 1 to ADBUSY provides software control of ADCO whereby conversions are performed on demand All other trigger sources occur autonomous to code execution When the conversion is complete the ADC posts the result to its output register and sets the ADC interrupt flag ADINT ADINT may be used to trigger a system interrupts if enabled or polled by firmware During a conversion the ADBUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete However the ADBUSY bit should not be used to poll for ADC conversion completion The ADCO interrupt flag ADINT should be used instead of the ADBUSY bit Converted data is available in the ADCO data registers ADCOH ADCOL when the conversion is complete Note The CNVSTR pin is a multi function GPIO pin When the CNVSTR input is used as the ADC conversion source the associated port pin should be skipped in the crossbar settings 12 3 6 Input Tracking Each ADC conversion must be preceded by a minimum tracking time to allow the voltage on the sampling capaci
290. o provide dithering The converter also employs a hardware dynamic element matching algorithm that reconfigures the largest elements of the internal DAC for each of the four 10 bit conversions This reconfiguration cancels any matching errors and enables the converter to achieve 12 bit linearity performance to go along with its 12 bit resolution The 12 bit mode is enabled by setting the AD12BE bit in register ADCOAC to logic 1 and configuring the ADC in burst mode ADBMEN 1 for four or more conversions The conversion can be initiated using any of the conversion start sources and the 12 bit result will appear in the ADCOH and ADCOL registers Since the 12 bit result is formed from a combination of four 10 bit results the maximum output value is 4 x 1023 4092 rather than the max value of 2 12 1 4095 that is produced by a traditional 12 bit converter To further increase resolution the burst mode repeat value may be configured to any multiple of four conversions For example if a repeat value of 16 is selected the ADCO output will be a 14 bit number sum of four 12 bit numbers with 13 effective bits of resolution The AD12SM bit in register ADCOTK controls when the ADC will track and sample the input signal When AD12SM is set to 1 the selected input signal will be tracked before the first conversion of a set and held internally during all four conversions When AD12SM is cleared to 0 the ADC will track and sample the selected input befor
291. oltage Reference An external reference may be applied to the VREF pin Bypass capacitors should be added as recommended by the manufacturer of the external voltage reference If the manufacturer does not provide recommendations 4 7 pF in parallel with a 0 1 uF capacitor is recommended Note The VREF pin is a multi function GPIO pin When using an external voltage reference VREF should be configured as an analog input and skipped by the crossbar silabs com Smart Connected Energy friendly Preliminary Rev 0 2 112 EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 3 2 4 Ground Reference To prevent ground noise generated by switching digital logic from affecting sensitive analog measurements a separate analog ground reference option is available When enabled the ground reference for the ADC during both the tracking sampling and the conversion periods is taken from the AGND pin Any external sensors sampled by the ADC should be referenced to the AGND pin If an external voltage reference is used the AGND pin should be connected to the ground of the external reference and its associated decoupling capacitor The separate analog ground reference option is enabled by setting GNDSL to 1 Note that when sampling the internal tem perature sensor the internal chip ground is always used for the sampling operation regardless of the setting of the GNDSL bit Similarly whenever the internal high speed reference is selected t
292. omparator result that will clear the PCA channel s Value Name Description 0 LOW PCA channel s will be cleared when comparator result goes logic low 1 HIGH PCA channel s will be cleared when comparator result goes logic high 6 3 Reserved Must write reset value 2 CPCE2 0 RW Comparator Clear Enable for CEX2 Enables the comparator clear function on PCA channel 2 1 CPCE1 0 RW Comparator Clear Enable for CEX1 Enables the comparator clear function on PCA channel 1 0 CPCEO 0 RW Comparator Clear Enable for CEXO Enables the comparator clear function on PCA channel 0 16 4 5 PCAOL PCA Counter Timer Low Byte Bit 7 6 5 4 3 2 1 0 PCAOL Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address OxF9 Bit 7 0 Reset Access Description PCAOL 0x00 RW PCA Counter Timer Low Byte The PCAOL register holds the low byte LSB of the 16 bit PCA Counter Timer silabs com Smart Connected Energy friendly Preliminary Rev 0 2 191 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 4 6 Counter Timer High Byte Bit 7 6 5 4 3 2 1 0 Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address Bit Reset Access Description 7 0 PCAOH 0x00 RW PCA Counter Timer High Byte The PCAOH register holds the high byte MSB of the 16 bit PCA Counter Timer Reads of this register will read the con te
293. on not used in 12 bit mode 0 1 _4 Perform Accumulate 4 conversions 1 conversion 12 bit mode 0x2 ACC 8 Perform and Accumulate 8 conversions 2 conversions in 12 bit mode 0x3 ACC_16 Perform and Accumulate 16 conversions 4 conversions in 12 bit mode 0 4 _32 Perform and Accumulate 32 conversions 8 conversions in 12 bit mode silabs com Smart Connected Energy friendly Preliminary Rev 0 2 128 EFM8BB2 Reference Manual Analog to Digital Converter ADCO Reset Access Description 0 5 _64 Perform and Accumulate 64 conversions 16 conversions in 12 bit mode 12 4 5 ADCOPWR ADCO Power Control Bit 7 6 4 3 2 1 0 ADBIAS ADMXLP ADLPM ADPWR Access RW RW RW RW Reset 0x0 0 0 OxF SFR Page 0x0 0x10 SFR Address OxDF Bit Name Reset Access Description 7 6 ADBIAS 0 0 RW Bias Power Select This field can be used to adjust the ADC s power consumption based on the conversion speed Higher bias currents allow for faster conversion times Value Name Description 0x0 MODEO Select bias current mode 0 Recommended to use modes 1 2 or 3 0 1 MODE1 Select bias current mode 1 SARCLK 16 MHz 0x2 MODE2 Select bias current mode 2 0x3 MODE3 Select bias current mode 3 SARCLK lt 4 MHz 5 ADMXLP 0 RW Mux and Reference Low Power Mode Enable Enables low power mode operation for the multi
294. or free timeout is sensed 4 EXTHOLD 0 RW SMBus Setup and Hold Time Extension Enable This bit controls the SDA setup and hold times Value Name Description 0 DISABLED Disable SDA extended setup and hold times 1 ENABLED Enable SDA extended setup and hold times 3 SMBTOE 0 RW SMBus SCL Timeout Detection Enable This bit enables SCL low timeout detection If set to logic 1 the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low If Timer 3 is configured to Split Mode only the High Byte of the timer is held in reload while SCL is high Timer 3 should be programmed to generate interrupts at 25 ms and the Timer 3 interrupt service routine should reset SMBus communication 2 SMBFTE 0 RW SMBus Free Timeout Detection Enable When this bit is set to logic 1 the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods 1 0 SMBCS 0 0 RW SMBus Clock Source Selection This field selects the SMBus clock source which is used to generate the SMBus bit rate See the SMBus clock timing sec tion for additional details Value Name Description 0x0 TIMERO Timer 0 Overflow 0 1 TIMER1 Timer 1 Overflow 0x2 TIMER2 HIGH Timer 2 High Byte Overflow 0x3 TIMER2_LOW Timer 2 Low Byte Overflow silabs com Smart Connected Energy friendly Preliminary Rev 0 2 233 EFM8BB2 Reference Manual System Management Bus I2C SMBO 18 4 2 SMBOTC SMBus
295. ort for 7 bit slave address recognition silabs com Smart Connected Energy friendly Preliminary Rev 0 2 158 EFM8BB2 Reference Manual I2C Slave I2CSLAVEO 15 3 Functional Description 15 3 1 Overview 2 Slave module operates only in slave mode The hardware provides timing and shifting control for serial transfers the higher level protocol is determined by user software The 12 hardware interface provides the following application independent features Byte wise serial data transfers SDA data synchronization Timeout recognition as defined by the I2COCNTL configuration register START STOP detection Interrupt generation Status information High speed I2C mode detection Automatic wakeup from lower power modes when a matching slave address is received Hardware recognition of the slave address and automatic acknowledgment of address data An I2CSLAVEO interrupt is generated when the RD WR or STOP bit is set in the I2COSTAT register It is also generated when the ACTIVE bit goes low to indicate the end of an I2C bus transfer Refer to the I2COSTAT register definition for complete details on the conditions for the setting and clearing of these bits Automatic Address Recognition The I2CSLAVEO peripheral can be configured to recognize a specific slave address and respond with an ACK without any software intervention This feature is enabled by firmware 1 Clear BUSY bit in IZCOCNTL to enabl
296. ow shows the distribution of instructions vs the number of clock cycles required for execution Table 10 1 Instruction Execution Timing Clocks to 1 2 2 or 3 3 3 or 4 4 4 or 5 5 8 Execute Number of 26 50 5 14 7 3 1 2 1 Instructions Notes 1 Conditional branch instructions indicated by 2 or 3 3 or 4 and 4 or 5 require extra clock cycles if the branch is taken See the instruction table for more information 10 2 Features The CIP 51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability The CIP 51 includes the following features Fast efficient pipelined architecture Fully compatible with MCS 51 instruction set 0 to 50 MHz operating clock frequency 50 MIPS peak throughput with 50 MHz clock Extended interrupt handler Power management modes On chip debug logic Program and data memory security 10 3 Functional Description 10 3 1 Programming and Debugging Support In system programming of the flash program memory and communication with on chip debug support logic is accomplished via the Sili con Labs 2 Wire development interface C2 The on chip debug support logic facilitates full speed in circuit debugging allowing the setting of hardware breakpoints starting stop ping and single stepping through program execution including interrupt ser
297. p are reserved and may not be used for code or data storage MOVX Instruction and Program Memory The MOVX instruction in an 8051 device is typically used to access external data memory On the devices the MOVX instruction is normally used to read and write on chip XRAM but can be re configured to write and erase on chip flash memory space MOVC in structions are always used to read flash memory while MOVX write instructions are used to erase and write flash This flash access feature provides a mechanism for the product to update program code and use the program memory space for non volatile data stor age 2 3 Data Memory The RAM space on the chip includes both an internal RAM area which is accessed with MOV instructions and an on chip external RAM area which is accessed using MOVX instructions Total RAM varies based on the specific device The device memory has more details about the specific amount of RAM available in each area for the different device variants Internal RAM There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through OxFF The lower 128 bytes of data memo ry are used for general purpose registers and scratch pad memory Either direct or indirect addressing may be used to access the lower 128 bytes of data memory Locations 0 00 through Ox1F are addressable as four banks of general purpose registers each bank con sisting of eight byte wide registers The next 16 bytes locations 0
298. page 183 describes the duty cycle when CEXnPOL in the PCAOPOL regsiter is set to 1 A 096 duty cycle for the channel with CEXnPOL 0 is achieved by clearing the module s ECOM bit to 0 This will disable the comparison and prevent the match edge from occuring Note Although the PCAOCPn compare register determines the duty cycle it is not always appropriate for firmware to update this regis ter directly See the sections on 8 to 11 bit and 16 bit PWM mode for additional details on adjusting duty cycle in the various modes N Duty Cycle UN S Figure 16 7 N bit Edge Aligned PWM Duty Cycle With CEXnPOL 0 PWM resolution silabs com Smart Connected Energy friendly Preliminary Rev 0 2 182 EFM8BB2 Reference Manual Programmable Counter Array PCAO Duty Cycle ON Figure 16 8 N bit Edge Aligned PWM Duty Cycle With CEXnPOL 1 N PWM resolution silabs com Smart Connected Energy friendly Preliminary Rev 0 2 183 EFM8BB2 Reference Manual Programmable Counter Array PCAO Center Aligned PWM When configured for center aligned mode a module generates an edge transition at two points for every 2 N 1 PCA clock cycles where is the selected PWM resolution in bits In center aligned mode these two edges are referred to as the up and down edges The polarity at the output pin is selectable and can be inverted by setting the appropriate channel bit to 1 in the PCAOPOL register
299. pe and offset parameters of the temperature sensor V temp Slope x Temp Offset Temp V temp Offset Slope Slope V deg C Voltage ie 4 offset V at 0 deg Celsius Temperature Figure 12 6 Temperature Sensor Transfer Function 12 3 13 1 Temperature Sensor Calibration The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature measurements For absolute tem perature measurements offset and or gain calibration is recommended Typically a 1 point offset calibration includes the following steps 1 Control measure the ambient temperature this temperature must be known 2 Power the device and delay for a few seconds to allow for self heating 3 Perform an ADC conversion with the temperature sensor selected as the ADC input 4 Calculate the offset characteristics and store this value in non volatile memory for use with subsequent temperature sensor meas urements Preliminary Rev 0 2 124 silabs com Smart Connected Energy friendly EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 4 ADCO Control Registers 12 4 1 ADCOCNO ADCO Control 0 Bit 7 6 5 4 3 1 ADEN ADBMEN ADINT ADBUSY ADWINT ADCM Access RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 SFR Page 0x0 0x10 SFR Address 0 8 bit addressable Bit Reset Access Description 7 ADE
300. pletes execution The internal LDO is then placed into a low current standby mode All internal registers and memory maintain their original data Snooze mode is terminated by any enabled wake or reset source When snooze mode is terminated the LDO is returned to normal operating conditions and the device will continue execution on the instruction following the one that set the SNOOZE bit If the wake event was configured to generate an interrupt the interrupt will be serviced upon waking the device If snooze mode is terminated by an internal or external reset the CIP 51 performs a normal reset sequence and begins program execution at address 0 0000 7 7 Shutdown Mode In shutdown mode the CPU is halted and the internal LDO is powered down External will retain their configured states To enter Shutdown mode firmware should set the STOPCF bit in the regulator control register to 1 and then set the STOP bit in PCONO In Shutdown the RSTb pin and a full power cycle of the device are the only methods of generating a reset and waking the device Note In Shutdown mode all internal device circuitry is powered down and no RAM registers are retained The debug circuitry will not be able to connect to a device while it is in Shutdown Coming out of Shutdown mode whether by POR or pin reset will appear as a power on reset of the device 7 8 5V to 3 3V Regulator The 5 to 3 3 V regulator is powered from the VREGIN pin on the device When
301. plexer and voltage reference buffers Value Name Description 0 LP_MUX_VREF_DISA Low power mode disabled BLED 1 LP_MUX_VREF_ENA Low power mode enabled SAR clock lt 4 MHz BLED 4 ADLPM 0 RW Low Power Mode Enable This bit can be used to reduce power to the ADC s internal common mode buffer It can be set to 1 to reduce power when tracking times in the application are longer slower sample rates Value Name Description 0 LP_BUFFER_DISA Disable low power mode BLED 1 LP_BUFFER_ENA Enable low power mode requires extended tracking time BLED 3 0 ADPWR OxF RW Burst Mode Power Up Time This field sets the time delay allowed for the ADC to power up from a low power state When ADTM is set an additional 4 SARCLKs are added to this time Tpwrtime 8 ADPWR Fhfosc silabs com Smart Connected Energy friendly Preliminary Rev 0 2 129 EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 4 6 ADCOTK ADCO Burst Mode Track Time Bit 7 6 5 4 3 2 1 0 AD12SM Reserved ADTK Access RW RW RW Reset 0 0 Ox1E SFR Page 0x0 0x10 SFR Address OxB9 Bit Reset Access Description 7 125 0 RW 12 Bit Sampling Mode This bit controls the way that the ADC samples the input when in 12 bit mode When the ADC is configured for multiple 12 bit conversions in burst mode the AD12SM bit should be cleared to 0 Value Name Description 0 SAMPLE_FOUR The ADC will
302. ponding bit in PnSKIP to 1 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 3 4 INTO and INT1 Two direct pin digital interrupt sources INTO and INT1 are included which can be routed to port 0 pins Additional I O interrupts are available through the port match function As is the case on a standard 8051 architecture certain controls for these two interrupt sour ces are available in the 0 1 registers Extensions to these controls which provide additional functionality are available in the ITO1CF register INTO and INT1 are configurable as active high or low edge or level sensitive The INOPL and IN1PL bits in the ITO1CF register select active high or active low the ITO and IT1 bits in TCON select level or edge sensitive The table below lists the possible configurations Table 11 3 INTO INT1 configuration ITO or IT1 INOPL or INTPL INTO or INT1 Interrupt 1 0 Interrupt on falling edge 1 1 Interrupt on rising edge 0 0 Interrupt on low level 0 1 Interrupt on high level INTO and INT1 are assigned to port pins as defined in the ITO1CF register INTO and INT1 port pin assignments are independent of any crossbar assignments and be assigned to pins used by crossbar peripherals INTO and INT1 will monitor their assigned port pins without disturbing the peripheral that was assigned the port pin via the crossbar To assign a port pin only to INTO and or INT1 config
303. progammable low frequency oscillator factory calibrated to a nominal frequency of 80 kHz A dedicated divider at the oscillator output is capable of dividing the output clock by 1 2 4 or 8 using the OSCLD bits in the LFOOCN register The OSCLF bits can be used to coarsely adjust the oscillator s output frequency The LFOSCO circuit requires very little start up time and may be selected as the system clock immediately following the register write which enables the oscillator Calibrating LFOSCO On chip calibration of the LFOSCO can be performed using a timer to capture the oscillator period when running from a known time base When a timer is configured for L F Oscillator capture mode a rising edge of the low frequency oscillator s output will cause a capture event on the corresponding timer As a capture event occurs the current timer value is copied into the timer reload registers By recording the difference between two successive timer capture values the low frequency oscillator s period can be calculated The OSCLF bits can then be adjusted to produce the desired oscillator frequency 8 3 5 External Clock An external CMOS clock source is also supported as a core clock source The EXTCLK pin on the device serves as the external clock input when running in this mode The EXTCLK input may also be used to clock certain digital peripherals e g Timers PCA etc while SYSCLK runs from one of the internal oscillator sources When not selected
304. pt pending flag to logic 1 If interrupts are enabled for the flag an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt pending flag Refer to the data sheet section associated with a particular on chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt pending flag s 6 2 1 Interrupt Priorities Each interrupt source can be individually programmed to one of four priority levels This differs from the traditional two priority levels on the 8051 core However the implementation of the extra levels is backwards compatible with legacy 8051 code An interrupt service routine can be preempted by any interrupt of higher priority Interrupts at the highest priority level cannot be pre empted Each interrupt has two associated priority bits which are used to configure the priority level For backwards compatibility the bits are spread across two different registers The LSBs of the priority setting are located in the IP and EIPn registers while the MSBs are located in the IPH and EIPnH registers Priority levels according to the MSB and LSB are decoded in Table 6 1 Configurable Inter rupt Priority Decoding on page 33 The lowest priority setting is the default for all interrupts If two or more interrupts are recognized simultaneously the interrupt with the highest priority is serviced first If both interrupts have the same priority l
305. ption 7 4 Reserved Must write reset value 3 B3 0 RW Port 2 Bit 3 Skip Value Name Description 0 NOT SKIPPED P2 3 pin is not skipped by the crossbar 1 SKIPPED P2 3 pin is skipped by the crossbar 2 B2 0 RW Port 2 Bit 2 Skip See bit 3 description 1 B1 0 RW Port 2 Bit 1 Skip See bit 3 description 0 BO 0 RW Port 2 Bit 0 Skip See bit 3 description 11 4 23 P3 Port 3 Pin Latch Bit 7 6 5 4 3 2 1 0 Reserved B1 BO Access R RW RW Reset 0x00 1 1 SFR Page ALL SFR Address 0 0 bit addressable Bit Name Reset Access Description 7 2 Reserved Must write reset value 1 B1 1 RW Port 3 Bit 1 Latch Value Name Description 0 LOW P3 1 is low Set P3 1 to drive low 1 HIGH P3 1 is high Set P3 1 to drive or float high 0 BO 1 RW Port 3 Bit 0 Latch See bit 1 description Writing this register sets the port latch logic value for the associated I O pins configured as digital Reading this register returns the logic value at the pin regardless if it is configured as output or input Preliminary Rev 0 2 107 silabs com Smart Connected Energy friendly EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 24 P3MDIN Port 3 Input Mode Bit 7 6 4 3 2 1 0 1 BO Access R RW RW Reset 0x00 1 1 SFR Page 7 0x20 SFR Address OxF4 Bit Reset Access Description 7 2 Reserved
306. r 4 Capture Mode If TFACEN is set and Timer 4 interrupts are enabled an interrupt will be generated according to the capture source selected by the T4CSEL bits and the current 16 bit timer value in TMR4H TMRA4L will be copied to TMRARLH TMRARLL 3 TASPLIT 0 RW Timer 4 Split Mode Enable When this bit is set Timer 4 operates as two 8 bit timers with auto reload Value Name Description 0 16 BIT RELOAD Timer 4 operates 16 bit auto reload mode 1 8 BIT RELOAD Timer 4 operates as two 8 bit auto reload timers 2 TR4 0 RW Timer 4 Run Control Timer 4 is enabled by setting this bit to 1 In 8 bit mode this bit enables disables TMR4H only TMRAL is always enabled split mode 1 0 T4XCLK 0 0 RW Timer 4 External Clock Select This bit selects the external clock source for Timer 4 If Timer 4 is in 8 bit mode this bit selects the external oscillator clock source for both timer bytes However the Timer 4 Clock Select bits T4MH and T4ML may still be used to select between the external clock and the system clock for either timer Value Name Description 0x0 SYSCLK DIV 12 Timer 4 clock is the system clock divided by 12 0 1 EXTOSC DIV 8 Timer 4 clock is the external oscillator divided by 8 synchronized with SYSCLK when not in suspend or snooze mode 0x2 TIMER3 Timer 4 is clocked by Timer 3 overflows 0x3 LFOSC_DIV_8 Timer 4 clock is the low frequency oscillator divided by 8 synchronized with SYSCLK when no
307. r the AUTOEN 8 Write the CRCPNT bit to 0 to target the low byte of the result 9 Read CRCODAT multiple times to access each byte of the CRC result CRCPNT will automatically point to the next value after each read 14 3 4 Bit Reversal CRCO includes hardware to reverse the bit order of each bit in a byte Writing a byte to CRCOFLIP initiates the bit reversal operation and the result may be read back from CRCOFLIP on the next instruction For example if OXCO is written to CRCOFLIP the data read back is 0 03 Bit reversal can be used to change the order of information passing through the engine and is also used in algo rithms such as FFT silabs com Smart Connected Energy friendly Preliminary Rev 0 2 154 EFM8BB2 Reference Manual Cyclic Redundancy Check CRCO 14 4 CRCO Control Registers 14 4 1 CRCOCNO CRCO Control 0 Bit 7 6 3 2 1 0 Reserved CRCINIT CRCVAL Reserved CRCPNT Access R RW RW R RW Reset Ox1 0 0 0 0 SFR Page 0x0 0x20 SFR Address OxCE Bit Reset Access Description 7 4 Reserved Must write reset value 3 CRCINIT 0 RW CRC Initialization Enable Writing a 1 to this bit initializes the entire CRC result based CRCVAL 2 CRCVAL 0 RW CRC Initialization Value This bit selects the set value of the CRC result Value Name Description 0 SET_ZEROES CRC result is set to 0x0000 on write of 1 to CRCINIT 1 SET_ONES CRC result is
308. r the channel are equal PCAOCPLn 8 bit Adder PCAOCPHn Adder Enable 8 bit match ECOMn gt Comparator CEXn Compare Enable TOGn Toggle Enable PCA Clock gt Figure 16 5 PCA Frequency Output Mode 16 3 8 PWM Waveform Generation The PCA can generate edge or center aligned PWM waveforms with resolutions of 8 9 10 11 or 16 bits PWM resolution depends on the module setup as specified within the individual module PCAOCPMn registers as well as the PCAOPWM register Modules can be configured for 8 11 bit mode or for 16 bit mode individually using the registers All modules configured for 8 11 bit mode have the same resolution specified by the PCAOPWM register When operating in one of the PWM modes each module may be indi vidually configured for center or edge aligned PWM waveforms Each channel has a single bit in the PCAOCENT register to select be tween the two options silabs com Smart Connected Energy friendly Preliminary Rev 0 2 181 EFM8BB2 Reference Manual Programmable Counter Array PCAO Edge Aligned PWM When configured for edge aligned mode a module generates an edge transition at two points for every 2N PCA clock cycles where N is the selected PWM resolution in bits In edge aligned mode these two edges are referred to as the match and overflow edges The polarity at the output pin is selectable and can be inverted by setting the appropria
309. r transition positive or negative edge When a capture occurs the Capture Compare Flag CCFn in PCAOCNO is set to logic 1 An interrupt request is generated if the CCFn interrupt for that module is enabled The CCFn bit is not auto matically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by software If both CAPPn and CAPNn bits are set to logic 1 then the state of the port pin associated with CEXn can be read directly to determine whether a rising edge or falling edge caused the capture CCFn Interrupt Flag CAPPn PCAOCPLn PCAOCPHn CEXn PCA Clock Figure 16 2 PCA Capture Mode Diagram Note The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware silabs com Smart Connected Energy friendly Preliminary Rev 0 2 178 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 3 5 Software Timer Compare Mode In Software Timer mode the counter timer value is compared to the module s 16 bit capture compare register PCAOCPHn and PCAOCPLn When a match occurs the Capture Compare Flag CCFn in PCAOCNO is set to logic 1 An interrupt request is generated if the CCFn interrupt for that module is enabled The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and it must be cleared by software Setting the ECOMn and bits i
310. rces Normal Core and all peripherals clocked and fully operational Idle Core halted Set IDLE bit in PCONO Any interrupt All peripherals clocked and fully operational Code resumes execution on wake event Suspend Core and peripheral clocks halted 1 Switch SYSCLK to Timer 4 Event HFOSCO and 5 1 oscillators stopped HFOSCO SPIO Activity Regulators in normal bias mode for fast wake 2 Set SUSPEND bitin 2 0 Slave Activity Timer 3 and 4 may clock from LFOSCO Port Match Event Code resumes execution on wake event Comparator 0 Rising Edge silabs com Smart Connected Energy friendly Preliminary Rev 0 2 47 EFM8BB2 Reference Manual Power Management and Internal Regulators Power Mode Details Mode Entry Wake Up Sources Snooze Core and peripheral clocks halted 1 Switch SYSCLK to Timer 4 Event HFOSCO and HFOSC 1 oscillators stopped HFOSCO SPIO Activity Regulators in low bias current mode for energy sav 2 Set SNOOZE bit in 12 0 Slave Activity ings 1 Port Match Event Timer 3 and 4 may clock from LFOSCO 0 Rising Code resumes execution on wake event Edge Shutdown All internal power nets shut down 1 Set STOPCF bit in RSTb pin reset 5V regulator remains active if enabled Pins retain state Exit on pin or power on reset REGOCN 2 Set STOP bit in PCONO Power on reset 7 2 Features The power m
311. rdware ACK genera tion is enabled the hardware will apply the ACK for a slave address which matches the criteria set up by SMBOADR and SMBOADM The interrupt will occur after the ACK cycle If the received slave address is ignored by software or hardware slave interrupts will be inhibited until the next START is detected If the received slave address is acknowledged zero or more data bytes are transmitted If the received slave address is acknowledged data should be written to SMBODAT to be transmitted The interface enters slave transmitter mode and transmits one or more bytes of data After each byte is transmitted the master sends an acknowledge bit if the acknowledge bit is an ACK SMBODAT should be writ ten with the next data byte If the acknowledge bit is a NACK SMBODAT should not be written to before SI is cleared an error condition may be generated if SMBODAT is written following a received NACK while in slave transmitter mode The interface exits slave trans mitter mode after receiving a STOP The interface will switch to slave receiver mode if SMBODAT is not written following a Slave Trans mitter interrupt Figure 18 11 Typical Slave Read Sequence on page 232 shows a typical slave read sequence as it appears on the bus The corresponding firmware state diagram combined with the slave read sequence is shown in Figure 18 10 Slave State Dia gram EHACK 1 on page 231 Two transmitted data bytes are shown though any number of bytes
312. re Software Timer High Speed Output Frequency Output or Pulse Width Modulated PWM Output Each capture compare module has its own associated I O line CEXn which is routed through the crossbar to port I O when enabled SYSCLK SYSCLK 4 SYSCLK 12 Timer 0 Overflow PCA Counter EXTCLK 8 L F Oscillator 8 Control Interrupt Configuration Logic Channel 0 Mode Control Capture Compare Comparator 0 Output Polarity Select Comparator Clear Enable Figure 16 1 PCA Block Diagram silabs com Smart Connected Energy friendly Preliminary Rev 0 2 175 EFM8BB2 Reference Manual Programmable Counter Array 16 2 Features 16 bit time base Programmable clock divisor and clock source selection Upto three independently configurable channels 8 9 10 11 and 16 bit PWM modes center or edge aligned operation Output polarity control Frequency output mode Capture on rising falling or any edge Compare function for arbitrary waveform generation Software timer internal compare mode Can accept hardware kill signal from comparator 0 16 3 Functional Description 16 3 1 Counter Timer The 16 bit PCA counter timer consists of two 8 bit SFRs PCAOL and PCAOH PCAOH is the high byte of the 16 bit counter timer and is the low byte Reading PCAOL automatically latches the value of PCAOH into a snapshot register the following PCAOH read accesse
313. re than one slave simultaneously The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master slave role is temporarily reversed to enable half duplex transmission between the original master and slave s Master Device Figure 21 6 Multi Processor Mode Interconnect Diagram 21 3 7 LIN Break and Sync Detect UART contains dedicated hardware to assist firmware LIN slave applications It includes automatic detection of LIN break and sync fields and can optionally perform automatic baud rate adjustment based on the LIN 0x55 sync word The LIN features are enabled by setting the LINMDE bit in UART1LIN to enable LIN mode When enabled both break and sync detec tion will be enabled for all incoming data The circuitry can detect a break sync sequence in the middle of an incoming data stream and react accordingly The UART will indicate that a break has been detected by setting the BREAKDN flag to 1 Likewise hardware will set the SYNCD bit if a valid sync is detected and the SYNCTO bit will indicate if a sync timeout has occured The break done and sync flags may be individ ually enabled to generate UART1 interrupts by setting the BREAKDNIE SYNCDIE SYNCTOIE bits to 1 21 3 8 Autobaud Detection Automatic baud rate detection and adjustment is supported by the UART Autobaud may be enabled by setting the AUTOBDE bit in the register to 1 Although the autob
314. re track and sample the input four times during a 12 bit conversion 1 SAMPLE_ONCE The ADC will sample the input once at the beginning of each 12 bit conversion The ADTK field can be set to 63 to maximize throughput 6 Reserved Must write reset value 5 0 ADTK Ox1E RW Burst Mode Tracking Time This field sets the time delay between consecutive conversions performed in Burst Mode When ADTM is set an additional 4 SARCLKs are added to this time Tbmtk 64 ADTK Fhfosc The Burst Mode track delay is not inserted prior to the first conversion The required tracking time for the first conversion should be defined with the ADPWR field 12 4 7 ADCOH ADCO Data Word High Byte Bit 7 6 5 4 3 2 1 0 ADCOH Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address Bit Reset Access Description 7 0 ADCOH 0x00 RW Data Word High Byte When read this register returns the most significant byte of the 16 bit ADCO accumulator formatted according to the set tings in ADSJST The register may also be written to set the upper byte of the 16 bit ADCO accumulator If Accumulator shifting is enabled the most significant bits of the value read will be zeros silabs com Smart Connected Energy friendly Preliminary Rev 0 2 130 EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 4 8 ADCOL ADCO Data Word Low Byte Bit 7 6 5 4 3 2 1 0
315. red TER when STA is low unwanted repeated START SCL is sensed low while attempting to gen erate a STOP or repeated START condition SDA is sensed low while transmitting a 1 excluding ACK bits ACK The incoming ACK value is low AC The incoming ACK value is high NOT ACKNOWL KNOWLEDGE EDGE SI A START has been generated Must be cleared by software Lost arbitration A byte has been transmitted and an ACK NACK received A byte has been received A START or repeated START followed by a slave address R W has been received A STOP has been received silabs com Smart Connected Energy friendly Preliminary Rev 0 2 224 EFM8BB2 Reference Manual System Management Bus I2C SMBO Hardware Slave Address Recognition The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an ACK without software inter vention Automatic slave address recognition is enabled by setting the EHACK bit in register SMBOADM to 1 This will enable both auto matic slave address recognition and automatic hardware ACK generation for received bytes as a master or slave The registers used to define which address es are recognized by the hardware are the SMBus Slave Address register and the SMBus Slave Address Mask register A single address or range of addresses including the General Call Address 0 00 can be specified using these two registers The most significant s
316. rence Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 3 6 Multiprocessor Communications UART1 supports multiprocessor communication between a master processor one or more slave processors by special use of the extra data bit When a master processor wants to transmit to one or more slaves it first sends an address byte to select the target s An address byte differs from a data byte in that its extra bit is logic 1 in a data byte the extra bit is always set to logic O Setting the MCE bit and the bit in the SMOD register configures the UART for multi processor communications When a stop bit is received the UART will generate an interrupt only if the extra bit is logic 1 RBX 7 1 signifying an address byte has been received In the UART interrupt handler software will compare the received address with the slave s own assigned address If the addresses match the slave will clear its MCE bit to enable interrupts on the reception of the following data byte s Slaves that weren t addressed leave their MCE bits set and do not generate interrupts on the reception of the following data bytes thereby ignoring the data Once the entire message is received the addressed slave resets its MCE bit to ignore all transmissions until it receives the next address byte Multiple addresses can be assigned to a single slave and or a single address can be assigned to multiple slaves thereby enabling broadcast transmissions to mo
317. reset value 0 RXCNT 0 R RX FIFO Count This field indicates the number of bytes in the receive FIFO silabs com Smart Connected Energy friendly Preliminary Rev 0 2 240 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 19 Timers 0 Timer1 Timer2 Timer3 and Timer4 19 1 Introduction Five counter timers ar included in the device two are 16 bit counter timers compatible with those found in the standard 8051 and three are 16 bit auto reload timers for timing peripherals or for general purpose use These timers can be used to measure time intervals count external events and generate periodic interrupt requests Timer 0 and Timer 1 are nearly identical and have four primary modes of operation Timer 2 Timer 3 and Timer 4 are also similar and offer both 16 bit and split 8 bit timer functionality with auto reload ca pabilities Timer 2 3 and 4 offer capture functions that may be selected from several on chip sources or an external pin Timers 0 and 1 may be clocked by one of five sources determined by the Timer Mode Select bits 1 and the Clock Scale bits SCA1 SCAO The Clock Scale bits define a pre scaled clock from which Timer 0 and or Timer 1 be clocked Timer 0 1 may then be configured to use this pre scaled clock signal or the system clock Timers 2 3 and 4 may be clocked by the system clock the system clock divided by 12 or the external clock
318. ress Bit Reset Access Description 7 Reserved Must write reset value 6 4 TXCNT 0 0 R TX FIFO Count This field indicates the number of bytes in the transmit FIFO 3 Reserved Must write reset value 2 0 RXCNT 0x0 R RX FIFO Count This field indicates the number of bytes in the receive FIFO silabs com Smart Connected Energy friendly Preliminary Rev 0 2 285 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 4 10 UART1LIN UART1 LIN Configuration Bit 7 6 5 4 3 2 1 0 AUTOBDE BREAKDN SYNCTO SYNCD LINMDE BREAKDNIE SYNCTOIE SYNCDIE Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 7 0x20 SFR Address Ox9E Bit Reset Access Description 7 AUTOBDE 0 RW Auto Baud Detection Enable This bit enables auto baud detection Auto baud measures the time it takes to receive the sync field an 0x55 byte and updates the baud rate reload registers accordingly Value Name Description 0 DISABLED Autobaud is not enabled 1 ENABLED Autobaud is enabled 6 BREAKDN 0 RW LIN Break Done Flag This bit is set by hardware after detection of a valid LIN break This flag must be cleared by software Value Name Description 0 NOT_SET A LIN break has not been detected 1 BREAK A LIN break was detected since the flag was last cleared 5 SYNCTO 0 RW LIN Sync Timeout Fla
319. rface may operate as a master or a slave and multiple master devices on the same bus are supported If two or more masters attempt to initiate a data transfer simultaneously an arbitration scheme is employed with a single master always winning the arbitration It is not necessary to specify one device as the Master in a system any device who transmits a START and a slave address becomes the master for the duration of that transfer A typical I2C transaction consists of a START condition followed by an address byte Bits 7 1 7 bit slave address Bit 0 R W direction bit one or more bytes of data and a STOP condition Bytes that are received by a master or slave are acknowledged ACK with a low SDA during a high SCL see Figure 15 3 I2C Transaction on page 160 If the receiving device does not ACK the transmitting device will read a NACK not acknowledge which is a high SDA during a high SCL The direction bit R W occupies the least significant bit position of the address byte The direction bit is set to logic 1 to indicate a READ operation and cleared to logic 0 to indicate a WRITE operation All transactions are initiated by a master with one or more addressed slave devices as the target The master generates the START condition and then transmits the slave address and direction bit If the transaction is a WRITE operation from the master to the slave the master transmits the data a byte at a time waiting for an ACK from the slave at
320. rial Control Register 0 SCONO and Serial Data Buffer 0 SBUFO The single SBUFO location provides access to both transmit and receive registers Note Writes to SBUFO always access the transmit register Reads of SBUFO always access the buffered receive register it is not pos sible to read data from the transmit register With UARTO interrupts enabled an interrupt is generated each time a transmit is completed TI is set in SCONO or a data byte has been received RI is set in SCONO The UARTO interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine They must be cleared manually by software allowing software to determine the cause of the UARTO interrupt transmit complete or receive complete TB8 RI 9 bit Interrupts Output Shift Register Control Configuration SBUF 8 LSBs Baud Rate Timer 1 Input Shift Register RB8 9 bit START Detection Figure 20 1 UARTO Block Diagram 20 2 Features The UART uses two signals TX and RX and a predetermined fixed baud rate to provide asynchronous communications with other devices The UART module provides the following features Asynchronous transmissions and receptions Baud rates up to SYSCLK 2 transmit or SYSCLK 8 receive 8 or 9 bit data Automatic start and stop generation silabs com Smart Connected Energy friendly Preliminary Rev 0 2 266 EFM8BB2 Reference Manual
321. ription 0 BO 1 RW Port 0 Bit 0 Latch See bit 7 description Writing this register sets the port latch logic value for the associated I O pins configured as digital I O Reading this register returns the logic value at the pin regardless if it is configured as output or input silabs com Smart Connected Energy friendly Preliminary Rev 0 2 92 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 8 POMDIN Port 0 Input Mode Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 SFR Page 0x0 0x20 SFR Address OxF 1 Bit Reset Access Description 7 B7 1 RW Port 0 Bit 7 Input Mode Value Name Description 0 ANALOG 7 pin is configured for analog mode 1 DIGITAL 0 7 pin is configured for digital mode 6 B6 1 RW Port 0 Bit 6 Input Mode See bit 7 description 5 B5 1 RW Port 0 Bit 5 Input Mode See bit 7 description 4 B4 1 RW Port 0 Bit 4 Input Mode See bit 7 description 3 B3 1 RW Port 0 Bit 3 Input Mode See bit 7 description 2 B2 1 RW Port 0 Bit 2 Input Mode See bit 7 description 1 B1 1 RW Port 0 Bit 1 Input Mode See bit 7 description 0 0 1 RW Port 0 Bit 0 Input Mode See bit 7 description Port pins configured for analog mode have their weak pullup digital driver and digital receiver disabled silabs com Smart Connected Energy frien
322. ription 0 IGNORED General Call Address is ignored 1 RECOGNIZED General Call Address is recognized silabs com Smart Connected Energy friendly Preliminary Rev 0 2 236 EFM8BB2 Reference Manual System Management Bus I2C SMBO 18 4 5 SMBOADM SMBus 0 Slave Address Mask Bit 7 6 5 4 3 2 1 0 SLVM EHACK Access RW RW Reset Ox7F 0 SFR Page 7 0x0 0x20 SFR Address OxD6 Bit Reset Access Description 7 1 SLVM Ox7F RW SMBus Slave Address Mask Defines which bits of register SMBOADR are compared with an incoming address byte and which bits are ignored Any bit set to 1 in SLVM enables comparisons with the corresponding bit in SLV Bits set to 0 are ignored can be either or 1 in the incoming address 0 EHACK 0 RW Hardware Acknowledge Enable Enables hardware acknowledgement of slave address and received data bytes Value Name Description 0 ADR ACK MANUAL Firmware must manually acknowledge all incoming address and data bytes 1 ADR ACK AUTOMAT Automatic slave address recognition and hardware acknowledge is enabled IC 18 4 6 SMBODAT SMBus 0 Data Bit 7 6 5 4 3 2 1 0 SMBODAT Access RW Reset Varies SFR Page 0x0 0x20 SFR Address 0 2 Bit 7 0 Name Reset Access Description SMBODAT Varies RW SMBus 0 Data The SMBODAT register is used to access the TX and RX FIFOs When written data will go into the T
323. rive strength to drive low When cleared the pins will use low drive strength This overrides the drive strength setting for the I O port Value Name Description 0 LOW DRIVE SDA and SCL will use low drive strength 1 HIGH DRIVE SDA and SCL will use high drive strength 4 PINMD 0 RW Pin Mode Enable Value Name Description 0 GPIO MODE Set the 2 0 Slave pins in GPIO mode 1 I2C MODE Set the 2 0 Slave pins in I2C mode 3 TIMEOUT 0 RW SCL Low Timeout Enable When this bit is set Timer 4 will start counting only when SCL is low When SCL is high Timer 4 will auto reload with the value from the reload registers If Timer 4 is configured to Split Mode only the High Byte of the timer is held in reload while SCL is high The Timer 4 interrupt service routine should reset I2C communication Value Name Description 0 DISABLED Disable I2C SCL low timeout detection using Timer 4 1 ENABLED Enable 2 SCL low timeout detection using Timer 4 2 PRELOAD 1 RW Preload Disable Value Name Description 0 ENABLED Data bytes must be written into the TX FIFO via the I2CODOUT register before the 8th SCL clock of the matching slave address byte transfer arrives for 2 read operation 1 DISABLED Data bytes need not be preloaded for I2C read operations The data byte can be written to I2CODOUT during interrupt servicing 1 I2COEN 0 RW I2C Enable This bit enables the 2 0 Slave module PINMD must be enabled first before this bit is enabled Value
324. rnal counter runs out a SPI interrupt will be generated allowing firmware to read any bytes remaining in the receive FIFO silabs com Smart Connected Energy friendly Preliminary Rev 0 2 206 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO 17 3 7 SPI Timing Diagrams SCK MCKH MCKL MIS Tun wo MOSI SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 17 8 SPI Master Timing CKPHA 0 SCK Tuck lus gt MISO MOSI SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 17 9 SPI Master Timing CKPHA 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 207 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO NSS SCK MOSI n 502 MISO SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 17 10 SPI Slave Timing CKPHA 0 NSS M sD gt SCK 6 gt gt lt SIH MOSI Tes Ton gt 07 SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 17 11 SPI Slave Timing CKPHA 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 208 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO Table 17 1 SPI Timing Par
325. rogrammable Counter Array PCAO 2N PCAOCPn 2 Duty Cycle ON Figure 16 10 N bit Center Aligned PWM Duty Cycle With CEXnPOL 0 N PWM resolution gt PCAOCPn Duty Cycle EE Figure 16 11 N bit Center Aligned PWM Duty Cycle With CEXnPOL 1 PWM resolution 16 3 8 1 8 to 11 Bit PWM Modes Each module can be used independently to generate a pulse width modulated PWM output on its associated CEXn pin The frequen cy of the output is dependent the timebase for the PCA counter timer and the setting of the PWM cycle length 8 through 11 bits For backwards compatibility with the 8 bit PWM mode available on other devices the 8 bit PWM mode operates slightly different than 9 through 11 bit PWM modes Important All channels configured for 8 to 11 bit PWM mode use the same cycle length It is not possible to configure one channel for 8 bit PWM mode and another for 11 bit mode for example However other PCA channels can be configured to Pin Capture High Speed Output Software Timer Frequency Output or 16 bit PWM mode independently Each channel configured for a PWM mode can be individually selected to operate in edge aligned or center aligned mode 8 bit Pulse Width Modulator Mode In 8 bit PWM mode the duty cycle is determined by the value of the low byte of the PCAOCPn register PCAOCPLn To adjust the duty cycle PCAOCPLn should not normally be written directly Instead the recommendation is
326. rol 1 21 4 9 UART1FCT UART1 FIFO Count 21 4 10 UART1 LIN Configuration 22 Watchdog Timer WDTO Table of Contents 260 260 261 262 262 262 263 263 264 265 266 266 266 267 267 267 268 268 269 269 270 271 271 271 272 272 272 273 273 273 275 275 275 276 276 278 279 280 280 281 282 284 285 286 288 301 23 22 1 Introduction 22 2 Features 22 3 Using the Watchdog Timer 22 4 WDTO Control Registers 22 4 1 WDTCN Watchdog Timer Control C2 Debug and Programming Interface 23 1 Introduction 23 2 Features 23 3 Pin Sharing 23 4 C2 Interface Registers 23 4 1 C2ADD C2 Address 23 4 2 C2DEVID C2 Device ID 23 4 3 C2REVID C2 Revision ID 23 4 4 C2FPCTL C2 Flash Programming Control 23 4 5 C2FPDAT C2 Flash Programming Data Table of Contents Table of Contents 288 288 288 289 289 290 290 290 290 291 291 291 291 292 292 293 302 SILICON Laks amat CNET Ls ibas of Vk Ur been 4 Den Bein CL cee 1024 ci meer E kl E Simpilcity Studio One click access to MCU tools documentation software source code libraries amp more Available for Windows Mac and Linux www silabs com simplicity MCU Portfolio S
327. rupts recommended 2 Write the first key code to FLKEY 0 5 3 Write the second key code to FLKEY OxF1 4 Set the PSWE bit register PSCTL 5 Clear the PSEE bit register PSCTL 6 Using the MOVX instruction write a single data byte to the desired location within the desired page 7 Clear the PSWE bit 4 3 3 Flash Write and Erase Precautions Any system which contains routines which write or erase flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified operating range of supply voltage system clock frequency or temperature This accidental execution of flash modifying code can result in alteration of flash memory contents causing a system fail ure that is only recoverable by re flashing the code in the device To help prevent the accidental modification of flash by firmware hardware restricts flash writes and erasures when the supply monitor is not active and selected as a reset source As the monitor is enabled and selected as a reset source by default it is recommended that systems writing or erasing flash simply maintain the default state The following sections provide general guidelines for any system which contains routines which write or erase flash from code Addi tional flash recommendations and example code can be found in AN201 Writing to Flash From Firmware available from the Silicon Laboratories website silabs com Sm
328. s Programmable data setup hold times Transmit and receive buffers to help increase throughput in faster applications silabs com Smart Connected Energy friendly Preliminary Rev 0 2 5 EFM8BB2 Reference Manual System Overview I2C Slave IZCSLAVEO The I2C Slave interface is a 2 wire bidirectional serial bus that is compatible with the I2C Bus Specification 3 0 It is capable of transfer ring in high speed mode HS mode at speeds of up to 3 4 Mbps Firmware can write to the I2C interface and the I2C interface can autonomously control the serial transfer of data The interface also supports clock stretching for cases where the core may be tempora rily prohibited from transmitting a byte or processing a received byte during an I2C transaction This module operates only as an I2C slave device The I2C module includes the following features Standard up to 100 kbps Fast 400 kbps Fast Plus 1 Mbps and High speed 3 4 Mbps transfer speeds Support for slave mode only Clock low extending clock stretching to interface with faster masters Hardware support for 7 bit slave address recognition 16 bit CRC CRCO The cyclic redundancy check CRC module performs a CRC using a 16 bit polynomial CRCO accepts a stream of 8 bit data and posts the 16 bit result to an internal register In addition to using the CRC block for data manipulation hardware can automatically CRC the flash contents of the device The CRC mod
329. s 0x08 0x0F 0x2 BANK2 Bank 2 Addresses 0x10 0x17 0x3 BANK3 Bank 3 Addresses 0x18 0x1F 2 OV 0 RW Overflow Flag This bit is set to 1 under the following circumstances 1 An ADD ADDC or SUBB instruction causes a sign change overflow 2 A MUL instruction results in an overflow result is greater than 255 3 A DIV instruction causes a divide by zero condition The OV bit is cleared to 0 by the ADD ADDC SUBB MUL and DIV instructions in all other cases 1 F1 0 RW User Flag 1 This is a bit addressable general purpose flag for use under firmware control 0 PARITY 0 R Parity Flag This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even Preliminary Rev 0 2 75 silabs com Smart Connected Energy friendly EFM8BB2 Reference Manual CIP 51 Microcontroller Core 10 4 7 PFEOCN Prefetch Engine Control Bit 7 6 4 3 2 1 0 Reserved PFEN FLRT Reserved Access R RW RW R Reset 0x0 0 0 0x0 SFR Page 0x10 SFR Address 0xC1 Bit Reset Access Description 7 6 Reserved Must write reset value 5 PFEN 0 RW Prefetch Enable The prefetch engine should be disabled when the device is in suspend mode to save power Value Name Description 0 DISABLED Disable the prefetch engine SYSCLK lt 25 MHz 1 ENABLED Enable the prefetch engine SYSCLK gt 25 MHz 4 FLRT 0 RW Flash Read Timing
330. s bit will be sent as the ninth transmission bit in 9 bit UART Mode Mode 1 Unused in 8 bit mode Mode 0 2 RB8 Varies R Ninth Receive Bit RB8 is assigned the value of the STOP bit in Mode 0 it is assigned the value of the 9th data bit in Mode 1 1 TI 0 RW Transmit Interrupt Flag Set to a 1 by hardware after data has been transmitted at the beginning of the STOP bit When the UARTO TI interrupt is enabled setting this bit causes the CPU to vector to the UARTO interrupt service routine This bit must be cleared by firm ware silabs com Smart Connected Energy friendly Preliminary Rev 0 2 269 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter O UARTO Reset Access Description RI 0 R Receive Interrupt Flag Set to 1 by hardware when a byte of data has been received by UARTO set at the STOP bit sampling time RI remains set while the receive FIFO contains any data Hardware will clear this bit when the receive FIFO is empty If a read of SBUFO is performed when RI is cleared the most recently received byte will be returned 20 4 2 SBUFO UARTO Serial Port Data Buffer Bit 7 6 5 4 3 2 1 0 SBUFO Access RW Reset Varies SFR Page 0x0 0x20 SFR Address 0x99 Bit 7 0 Reset Access Description SBUFO Varies RW Serial Data Buffer This SFR accesses the transmit and receive FIFOs When data is written to SBUFO and is 1 th
331. s enabled setting this bit causes the CPU to vector to the Timer 2 interrupt service routine This bit must be cleared by firmware 6 TF2L 0 RW Timer 2 Low Byte Overflow Flag Set by hardware when the Timer 2 low byte overflows from OxFF to 0x00 TF2L will be set when the low byte overflows regardless of the Timer 2 mode This bit must be cleared by firmware 5 TF2LEN 0 RW Timer 2 Low Byte Interrupt Enable When set to 1 this bit enables Timer 2 Low Byte interrupts If Timer 2 interrupts are also enabled an interrupt will be gen erated when the low byte of Timer 2 overflows 4 TF2CEN 0 RW Timer 2 Capture Enable When set to 1 this bit enables Timer 2 Capture Mode If TF2CEN is set and Timer 2 interrupts are enabled an interrupt will be generated according to the capture source selected by the T2CSEL bits and the current 16 bit timer value in TMR2H TMR2L will be copied to TMR2RLH TMR2RLL 3 T2SPLIT 0 RW Timer 2 Split Mode Enable When this bit is set Timer 2 operates as two 8 bit timers with auto reload Value Name Description 0 16 BIT RELOAD Timer 2 operates in 16 bit auto reload mode 1 8 BIT RELOAD Timer 2 operates as two 8 bit auto reload timers 2 TR2 0 RW Timer 2 Run Control Timer 2 is enabled by setting this bit to 1 In 8 bit mode this bit enables disables TMR2H only TMR2L is always enabled in split mode 1 0 T2XCLK 0x0 RW Timer 2 External Clock Select T2XCLK selects the external c
332. s of the timer register TMRnH TMRnL are loaded into the reload registers TMRnRLH TMRnRLL and the TFnH flag is set By recording the difference between two successive timer capture values the period of the captured signal can be determined with respect to the selected timer clock Timer Low Clock Capture Source TMRnRLL TMRnRLH TFnH Interrupt Figure 19 8 Capture Mode Block Diagram 19 3 3 4 Timer 3 and Timer 4 Chaining and Wake Source Timer 3 and Timer 4 may be chained together to provide a longer counter option This is accomplished by configuring Timer 4 s T4XCLK field to clock from Timer 3 overflows The primary use of this mode is to wake the device from long term Suspend or Snooze operations but it may also be used effectively as a 32 bit capture source It is important to note the relationship between the two timers when they are chained together in this manner The timer 3 overflow rate becomes the Timer 4 clock and essentially acts as a prescaler to the 16 bit Timer 4 function For example if Timer 3 is configured to overflow every 3 SYSCLKs and Timer 4 is configured to overflow every 5 clocks coming from Timer 3 overflows the Timer 4 overflow will occur every 15 SYSCLKs Timer 4 is capable of waking the device from the low power Suspend and Snooze modes To operate in either mode the timer must be running from either the LFOSC 8 option or Timer 3 overflows with Timer 3 configured to run from LFOSC 8 If runnin
333. s this snapshot register Note Reading the PCAOL Register first guarantees an accurate reading of the entire 16 bit PCAO counter Reading or PCAOL does not disturb the counter operation The CPS2 CPSO bits in the PCAOMD register select the timebase for the counter timer When the counter timer overflows from OxFFFF to 0x0000 the Counter Overflow Flag CF in PCAOMD is set to logic 1 and an interrupt request is generated if CF interrupts are enabled Setting the ECF bit in PCAOMD to logic 1 enables the CF flag to generate an interrupt request The CF bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by software Clearing the CIDL bit in the PCAOMD register allows the PCA to continue normal operation while the CPU is in Idle mode Table 16 1 PCA Timebase Input Options CPS2 0 Timebase 000 System clock divided by 12 001 System clock divided by 4 010 Timer 0 overflow 011 High to low transitions max rate system clock divided by 4 1 100 System clock 101 External oscillator source divided by 8 1 110 Low frequency oscillator divided by 8 1 111 Reserved Note 1 Synchronized with the system clock 16 3 2 Interrupt Sources The PCAO module shares one interrupt vector among all of its modules There are are several event flags that can be used to generate a PCAO interrupt They are as follows the PCA counter ov
334. s when a start condition is recognized on the RX pin Data will be received at the selected baud rate through the end of the data phase Data will be transferred into the receive buffer under the following conditions There is room in the receive buffer for the data MCE is setto 1 and the stop bit is also 1 8 bit mode MCE is setto 1 and the 9th bitis also 1 9 bit mode MCE is 0 stop or 9th bit will be ignored In the event that there is not room in the receive buffer for the data the most recently received data will be lost The RI flag will be set any time that valid data has been pushed into the receive buffer If RI interrupts are enabled RI will trigger an interrupt Firmware may read the 8 LSBs of received data by reading the SBUFO register The RB8 bit in SCONO will represent the 9th received bit in 9 bit mode or the stop bit in 8 bit mode and should be read prior to reading SBUFO 20 3 4 Multiprocessor Communications 9 Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit When a master processor wants to transmit to one or more slaves it first sends an address byte to select the target s An address byte differs from a data byte in that its ninth bit is logic 1 in a data byte the ninth bit is always set to logic O Setting the MCE bit of a slave processor configures its UART such that when a stop bit is received the UART
335. scription 1 B1 1 RW Port 2 Bit 1 Input Mode See bit 3 description 0 BO 1 RW Port 2 Bit 0 Input Mode See bit 3 description Port pins configured for analog mode have their weak pullup digital driver and digital receiver disabled silabs com Smart Connected Energy friendly Preliminary Rev 0 2 105 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 24 P2MDOUT Port 2 Output Mode Bit 7 6 5 4 3 2 1 0 Reserved B3 B2 B1 BO Access R RW RW RW RW Reset 0 0 0 0 0 0 SFR Page 0x0 0x20 SFR Address 0xA6 Bit Reset Access Description 7 4 Reserved Must write reset value 3 B3 0 RW Port 2 Bit 3 Output Mode Value Name Description 0 OPEN DRAIN P2 3 output is open drain 1 PUSH PULL P2 3 output is push pull 2 B2 0 RW Port 2 Bit 2 Output Mode See bit 3 description 1 B1 0 RW Port 2 Bit 1 Output Mode See bit 3 description 0 BO 0 RW Port 2 Bit 0 Output Mode See bit 3 description silabs com Smart Connected Energy friendly Preliminary Rev 0 2 106 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 22 P2SKIP Port 2 Skip Bit 7 6 4 3 2 1 0 Reserved B3 B2 B1 BO Access R RW RW RW RW Reset 0 0 0 0 0 0 SFR Page 0x20 SFR Address OxCC Bit Reset Access Descri
336. sed to jump to service routines MASTER indicates whether a device is the master or slave during the current transfer TXMODE indicates whether the device is transmitting or receiving data for the current byte STA and STO indicate that a START and or STOP has been detected or generated since the last SMBus interrupt STA and STO are also used to generate START and STOP conditions when operating as a master Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when the bus becomes free STA is not cleared by hardware after the START is generated Writing a 1 to STO while in Master Mode will cause the interface to generate a STOP and end the current transfer after the next ACK cycle If STO and STA are both set while in Master Mode a STOP followed by a START will be generated The ARBLOST bit indicates that the interface has lost an arbitration This may occur anytime the interface is transmitting master or slave A lost arbitration while operating as a slave indicates a bus error condition ARBLOST is cleared by hardware each time SI is cleared The SI bit SMBus Interrupt Flag is set at the beginning and end of each transfer after each byte frame or when an arbitration is lost Note The SMBus interface is stalled while SI is set if SCL is held low at this time the bus is stalled until software clears 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 223 EFM8BB2 Reference Man
337. sensitive INTO is configured active low or high by the INOPL bit in register ITO1CF Value Name Description 0 LEVEL INTO is level triggered 1 EDGE INTO is edge triggered silabs com Smart Connected Energy friendly Preliminary Rev 0 2 253 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 19 4 4 TMOD Timer 0 1 Mode Bit 7 6 4 3 2 1 0 1 CT1 T1M GATEO CTO TOM Access RW RW RW RW RW RW Reset 0 0 0x0 0 0 0x0 SFR Page ALL SFR Address 0x89 Bit Name Reset Access Description 7 GATE1 0 RW Timer 1 Gate Control Value Name Description 0 DISABLED Timer 1 enabled when TR1 1 irrespective of INT1 logic level 1 ENABLED Timer 1 enabled only when TR1 1 and INT1 is active as defined by bit IN1PL in register ITO1CF 6 CT1 0 RW Counter Timer 1 Select Value Name Description 0 TIMER Timer Mode Timer 1 increments on the clock defined by T1M in the CKCONO register 1 COUNTER Counter Mode Timer 1 increments on high to low transitions of an external pin T1 5 4 1 0 0 RW Timer 1 Mode Select These bits select the Timer 1 operation mode Value Name Description 0x0 MODEO Mode 0 13 bit Counter Timer 0 1 MODE1 Mode 1 16 bit Counter Timer 0x2 MODE2 Mode 2 8 bit Counter Timer with Auto Reload 0x3 MODE3 Mode 3 Timer 1 Inactive 3 GATEO 0 RW Timer 0 Gate Control Value Name Description
338. sents the accumulated result of the conversions performed and is updated after the last conversion in the series is finished Sets of 4 8 16 32 or 64 consecutive samples can be accumulated and represented in unsigned integer format The repeat count can be selected using the ADRPT bit field When a repeat count is higher than 1 the ADC output must be right justified ADSJST unused bits in the ADCOH and ADCOL registers are set to 0 The exam ple below shows the right justified result for various input voltages and repeat counts Notice that accumulating 2n samples is equiva lent to left shifting by n bit positions when all samples returned from the ADC have the same value Table 12 3 Effects of ADRPT on Output Code Input Voltage Repeat Count 4 Repeat Count 16 Repeat Count 64 VREF x 1023 1024 OxOFFC Ox3FFO OxFFCO VREF x 512 1024 0x0800 0x2000 0x8000 VREF x 511 1024 0 07 0 1 Ox7FCO 0 0x0000 0x0000 0x0000 Additionally the ADSJST bit field can be used to format the contents of the 16 bit accumulator The accumulated result can be shifted right by 1 2 or 3 bit positions Based on the principles of oversampling and averaging the effective ADC resolution increases by 1 bit each time the oversampling rate is increased by a factor of 4 The example below shows how to increase the effective ADC resolution by 1 2 and 3 bits to obtain an effective ADC resolution of 11 bit 12 bit or 13 bit respect
339. set to OxFFFF on write of 1 to CRCINIT 1 Reserved Must write reset value 0 CRCPNT 0 RW CRC Result Pointer Specifies the byte of the CRC result to be read written on the next access to CRCODAT This bit will automatically toggle upon each read or write Value Name Description 0 ACCESS LOWER CRCODAT accesses bits 7 0 of the 16 bit CRC result 1 ACCESS UPPER CRCODAT accesses bits 15 8 of the 16 bit CRC result Upon initiation of an automatic CRC calculation the three cycles following a write to CRCOCNO that initiate a CRC operation must only contain instructions which execute in the same number of cycles as the number of bytes in the instruction An example of such an instruction is a 3 byte MOV that targets the CRCOFLIP register When programming in C the dummy value written to CRCOFLIP should be a non zero value to prevent the compiler from generating a 2 byte MOV instruction 14 4 2 CRCOIN CRCO Data Input Bit 7 6 5 4 3 2 1 0 CRCOIN Access RW Reset 0x00 SFR Page 0x0 0x20 SFR Address 0xDD Bit Reset Access Description 7 0 CRCOIN 0x00 RW CRC Data Input Each write to CRCOIN results in the written data being computed into the existing CRC result according to the CRC algo rithm Preliminary Rev 0 2 155 silabs com Smart Connected Energy friendly EFM8BB2 Reference Manual Cyclic Redundancy Check CRCO 14 4 3 CRCODAT CRCO Data Output
340. sing edge of CNVSTR 0x5 CEX2 ADCO conversion initiated on rising edge of CEX2 0x6 GATED TIMER2 ADCO conversion initiated on overflow of Timer 2 when 2 is logic high 0 7 TIMER4 ADCO conversion initiated on overflow of Timer 4 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 125 EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 4 2 ADCOCN1 ADCO Control 1 Bit 7 6 5 4 3 2 1 0 Reserved ADCMBE Access R RW Reset 0x00 1 SFR Page 0x0 0x10 SFR Address 0 2 Bit Reset Access Description 7 1 Reserved Must write reset value 0 ADCMBE 1 RW Common Mode Buffer Enable Value Name Description 0 CM_BUFFER_DISA Disable the common mode buffer This setting should be used only if the tracking BLED time of the signal is greater than 1 5 us 1 CM_BUFFER_ENA Enable the common mode buffer This setting should be used in most cases and BLED will give the best dynamic ADC performance The common mode buffer must be enabled if signal tracking time is less than or equal to 1 5 us silabs com Smart Connected Energy friendly Preliminary Rev 0 2 126 EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 4 3 ADCOCF ADCO Configuration Bit 7 6 5 4 2 1 0 ADSC AD8BE ADTM ADGN Access RW RW RW RW Reset Ox1F 0 0 0 SFR Page 0x0 0x10 SFR Address 0xBC Bit Name Reset Access
341. ster Name Name 0000 0 0 P0 0 P0 0 0001 1 1 1 1 1 0010 2 2 P0 2 P0 2 P0 2 0011 CMPON 3 CMPON3 P0 3 P0 3 P0 3 0100 4 4 4 4 4 0101 5 5 5 P0 5 P0 5 0110 6 6 P0 6 P0 6 P0 6 0111 CMPON 7 CMPON7 7 7 7 1000 8 GND GND Supply Pin 1001 CMPON 9 CMPON9 P1 0 P1 0 P1 0 1010 CMPON 10 10 1 1 1 1 P1 1 1011 1110 CMPON 11 CMPON 14 No connection Reserved 1111 15 VDD VDD Supply Pin silabs com Smart Connected Energy friendly Preliminary Rev 0 2 136 EFM8BB2 Reference Manual Comparators and CMP1 Table 13 3 CMP1 Positive Input Multiplexer Channels Setting Signal Enumeration 28 QSOP24 Pin QFN20 Pin Register Name Name Name CMP1MX 0000 CMP1P 0 CMP1PO P1 0 P1 0 P1 0 0001 1 CMP1P1 P1 1 P1 1 P1 1 0010 CMP1P 2 CMP1P2 P1 2 P1 2 P1 2 0011 CMP1P 3 CMP1P3 P1 3 P1 3 P1 3 0100 CMP1P 4 1 4 1 4 1 4 1 4 0101 1 5 1 5 1 5 1 5 1 5 0110 CMP1P 6 CMP1P6 P1 6 P1 6 P1 6 0111 CMP1P 7 CMP1P7 P1 7 P1 7 Reserved 1000 CMP1P 8 LDO OUT Internal 1 8 V LDO output 1001 CMP1P 9 CMP1P9 P2 0 P2 0 Reserved 1010 CMP1P 10 CMP1P10 P2 1 P2 1 Reserved 1011 CMP1P 11
342. sts to collect the same number of conversions multi sample bursts will consume significantly less power For example performing an eight cycle burst of 10 bit conversions consumes about 61 of the power required to perform those same eight samples in single cycle bursts For 12 bit conversions an eight cycle burst results in about 85 of the equivalent single cycle bursts See the electrical characteristics tables for details on power consumption and the maximum clock frequencies allowed in each mode 10 Bit Burst Mode Power 12 Bit Burst Mode Power 100 100 95 98 90 96 85 94 80 92 75 70 65 86 60 84 55 82 Average Current Compared to Single Cycle Average Current Compared to Single Cycle 50 2 4 8 16 32 1 4 8 16 Number of Cycles Accumulated in Burst Number of Cycles Accumulated in Burst Figure 12 5 Burst Mode Accumulation Power Savings silabs com Smart Connected Energy friendly Preliminary Rev 0 2 121 EFM8BB2 Reference Manual Analog to Digital Converter ADCO 12 3 12 Window Comparator The ADC s programmable window detector continuously compares the ADC output registers to user programmed limits and notifies the system when a desired condition is detected This is especially effective in an interrupt driven system saving code space and CPU bandwidth while delivering faster system response times The window detector interrupt flag
343. t 1 ENABLED SPIO interrupts will be generated if SPIF is set 3 RFRQ 0 R Receive FIFO Request Set to 1 by hardware when the number of bytes in the RX FIFO is larger than specified by the RX FIFO threshold RXTH Value Name Description 0 NOT SET The number of bytes in the RX FIFO is less than or equal to RXTH 1 SET The number of bytes in the RX FIFO is greater than RXTH 2 Reserved Must write reset value silabs com Smart Connected Energy friendly Preliminary Rev 0 2 216 EFM8BB2 Reference Manual Serial Peripheral Interface SPIO Bit Name Reset Access Description 1 RXTOE 0 RW Receive Timeout Enable This bit enables the RX FIFO timeout function If the RX FIFO is not empty the number of bytes in the FIFO is not enough to generate a Receive FIFO request and the timeout is reached a SPIO interrupt will be generated Value Name Description 0 DISABLED Lingering bytes in the RX FIFO will not generate an interrupt 1 ENABLED Lingering bytes in the RX FIFO will generate an interrupt after timeout 0 RXFIFOE 1 RW Receive FIFO Enable This bit enables the SPI receive FIFO When enabled any received bytes will be placed into the RX FIFO Value Name Description 0 DISABLED Received bytes will be discarded 1 ENABLED Received bytes will be placed in the RX FIFO 17 4 7 SPIOFCT SPIO FIFO Count Bit 7 6 5 4 3 2 1 0 Reserved TXCNT Reserved RXCNT Access R R
344. t in suspend or snooze mode silabs com Smart Connected Energy friendly Preliminary Rev 0 2 264 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 19 4 26 TMR4CN1 Timer 4 Control 1 Bit 7 6 5 4 3 2 1 0 Reserved T4CSEL Access RW RW Reset 0x00 0 1 SFR Page 0x10 SFR Address OxFF Bit Reset Access Description 7 3 Reserved Must write reset value 2 0 TACSEL 0 1 RW Timer 4 Capture Select When used in capture mode the TACSEL register selects the input capture signal Value Name Description 0 0 Capture high to low transitions on the T2 input pin 0 1 LFOSC Capture high to low transitions of the LFO oscillator 0 2 Capture high to low transitions of the Comparator 0 output silabs com Smart Connected Energy friendly Preliminary Rev 0 2 265 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 0 UARTO 20 Universal Asynchronous Receiver Transmitter 0 UARTO 20 1 Introduction UARTO is an asynchronous full duplex serial port offering modes 1 and 3 of the standard 8051 UART Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates Received data buffering allows UARTO to start reception of a second incoming data byte before software has finished reading the previous data byte UARTO has two associated SFRs Se
345. t last PCA overflow 1 HIGH Comparator output was logic high at last PCA overflow 6 CPINV 0 RW Output Inversion This bit inverts the polarity of the comparator output when set Value Name Description 0 NORMAL Output is not inverted 1 INVERT Output is inverted 5 CPRIE 0 RW Comparator Rising Edge Interrupt Enable Value Name Description 0 RISE_INT_DISABLED Comparator rising edge interrupt disabled 1 RISE INT ENABLED Comparator rising edge interrupt enabled 4 CPFIE 0 RW Comparator Falling Edge Interrupt Enable Value Name Description 0 FALL INT DISABLED Comparator falling edge interrupt disabled 1 FALL INT ENABLED Comparator falling edge interrupt enabled 3 2 INSL 0 0 RW Comparator Input Selection These bits control how the comparator input pins and CMP are connected internally Value Name Description 0x0 CMXN Connect the comparator inputs directly to the signals selected in the CMPOMX register is selected by CMXP and CMP is selected by CMXN The inter nal DAC is not active Ox1 CMXP GND Connect the input to the signal selected by CMXP and CMP is connected to GND The internal DAC is not active 0 2 DAC CMXN Connect the input to the internal DAC output and CMP is selected by CMXN The internal DAC uses the signal specified by CMXP as its full scale ref erence silabs com Smart Connected Energy friendly Preliminary Rev 0 2 144 EFM8BB2 Reference Manual Comparators
346. t will be generated when COVF is set BLED 5 COVF 0 RW Cycle Overflow Flag This bit indicates an overflow of the 8th to 11th bit of the main PCA counter PCAO The specific bit used for this flag de pends on the setting of the Cycle Length Select bits The bit can be set by hardware or firmware but must be cleared by firmware Value Name Description 0 NO OVERFLOW No overflow has occurred since the last time this bit was cleared 1 OVERFLOW An overflow has occurred since the last time this bit was cleared 4 3 Reserved Must write reset value 2 0 CLSEL 0 0 RW Cycle Length Select When 16 bit PWM mode is not selected these bits select the length of the PWM cycle This affects all channels configured for PWM which are not using 16 bit PWM mode These bits are ignored for individual channels configured to 16 bit PWM mode Value Name Description 0 0 8 BITS 8 bits 0 1 9 5 9 bits 0x2 10 BITS 10 bits 0x3 11_BITS 11 bits silabs com Smart Connected Energy friendly Preliminary Rev 0 2 190 EFM8BB2 Reference Manual Programmable Counter Array 16 4 4 PCAOCLR PCA Comparator Clear Control Bit 7 6 2 1 0 CPCPOL Reserved CPCE2 CPCE1 CPCEO Access RW R RW RW RW Reset 0 0x0 0 0 0 SFR Page 0x0 0x10 SFR Address 0x9C Bit Reset Access Description 7 CPCPOL 0 RW Comparator Clear Polarity Selects the polarity of the c
347. te In 16 bit mode the TMR3L register contains the low byte of the 16 bit Timer 3 In 8 bit mode TMR3L contains the 8 bit low byte timer value 19 4 18 TMR3H Timer 3 High Byte Bit 7 6 4 1 0 Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address 0x95 Bit Reset Access Description 7 0 TMR3H 0x00 RW Timer 3 High Byte In 16 bit mode the TMR3H register contains the high byte of the 16 bit Timer 3 In 8 bit mode TMR3H contains the 8 bit high byte timer value silabs com Smart Connected Energy friendly Preliminary Rev 0 2 260 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 19 4 19 TMR3CNO Timer 3 Control 0 Bit 7 6 5 4 3 2 1 T3SPLIT TR3 T3XCLK Access RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0x0 SFR Page 0x0 0x10 SFR Address 0x91 Bit Reset Access Description 7 TF3H 0 RW Timer 3 High Byte Overflow Flag Set by hardware when the Timer 3 high byte overflows from OxFF to 0x00 In 16 bit mode this will occur when Timer 3 overflows from OxFFFF to 0x0000 When the Timer 3 interrupt is enabled setting this bit causes the CPU to vector to the Timer 3 interrupt service routine This bit must be cleared by firmware 6 0 RW Timer 3 Low Byte Overflow Flag Set by hardware when the Timer 3 low byte overflows from
348. te TMR3RLH 0x93 0x00 0x10 Timer 3 Reload High Byte TMR3RLL 0x92 0x00 0x10 Timer 3 Reload Low Byte TMRACNO 0x98 0x10 Timer 4 Control 0 TMR4CN1 OxFF 0x10 Timer 4 Control 1 TMR4H 0 5 0 10 Timer 4 High Byte TMR4L 0 4 0x10 Timer 4 Low Byte TMR4RLH 0 0x10 Timer 4 Reload High Byte TMR4RLL OxA2 0x10 Timer 4 Reload Low Byte UART1FCNO Ox9D 0x20 UART1 FIFO Control 0 UART1FCN1 OxD8 0x20 UART1 FIFO Control 1 UART1FCT OxFA 0x20 UART1 FIFO Count UART1LIN Ox9E 0x20 UART1 LIN Configuration VDMOCN OxFF 0x00 Supply Monitor Control WDTCN 0x97 ALL Watchdog Timer Control XBRO OxE1 0x00 0x20 Port Crossbar 0 XBR1 OxE2 0x00 0x20 Port I O Crossbar 1 XBR2 0 0 00 0 20 Port I O Crossbar 2 3 3 SFR Access Control Registers 3 3 1 SFRPAGE SFR Page Bit 7 6 4 3 2 1 0 Access RW Reset 0x00 SFR Page ALL SFR Address OxA7 Bit Name Reset Access Description 7 0 SFRPAGE 0x00 RW SFR Page Specifies the SFR Page used when reading writing or modifying special function registers silabs com Smart Connected Energy friendly Preliminary Rev 0 2 21 EFM8BB2 Reference Manual Special Function Registers 3 3 2 SFRPGCN SFR Page Control Bit 7 6 5 4 3 2 1 0 Reserved SFRPGIDX Reserved SFRPGEN Access RW RW RW RW Reset 0 0x0 0x0 1 SFR Page 0x10 SFR Address OxCF Bit Name Reset Access Description 7 Reserved
349. te channel bit to 1 in the PCAOPOL register Prior to inversion a match edge sets the channel to logic high and an overflow edge clears the channel to logic low The match edge occurs when the the lowest N bits of the module s PCAOCPn register match the corresponding bits of the main PCAO counter register For example with 10 bit PWM the match edge occurs any time bits 9 0 of the PCAOCPn register match bits 9 0 of the PCAO counter value The overflow edge occurs when an overflow of the PCAO counter happens at the desired resolution For example with 10 bit PWM the overflow edge occurs when bits 0 9 of the PCAO counter transition from all 1s to all Os All modules configured for edge aligned mode at the same resolution align on the overflow edge of the waveforms An example of the PWM timing in edge aligned mode for two channels is shown here In this example the CEXOPOL and CEX1POL bits are cleared to 0 OxFFFF Counter PCAO overflow edge match edge Figure 16 6 Edge Aligned PWM Timing For a given PCA resolution the unused high bits in the PCAO counter and the PCAOCPn compare registers are ignored and only the used bits of the PCAOCPn register determine the duty cycle Figure 16 7 N bit Edge Aligned PWM Duty Cycle With CEXnPOL 0 PWM resolution on page 182describes the duty cycle when CEXnPOL in the PCAOPOL regsiter is cleared to 0 Figure 16 8 N bit Edge Aligned PWM Duty Cycle With CEXnPOL 1 PWM resolution on
350. ted by the I2C Slave peripheral Figure 15 7 Example I2C Read Sequence with the I2C Slave Peripheral silabs com Smart Connected Energy friendly Preliminary Rev 0 2 165 EFM8BB2 Reference Manual I2C Slave I2CSLAVEO Idle Low Power Interrupt Address R received ACK sent 1 Clear START 2 Write first data to I2CODOUT 3 Clear I2COINT Interrupt Data sent Ack received Data sent Nack received Write next data to I2CODOUT Clear NACK Idle Low Power Figure 15 8 2 Read Flow Diagram with the I2C Slave Peripheral Note The I2C master must always generate a NACK before it can generate a repeated START bit or a STOP bit This NACK causes I2C Slave peripheral to release the SDA line for the I2C master to generate the START or STOP bit silabs com Smart Connected Energy friendly Preliminary Rev 0 2 166 EFM8BB2 Reference Manual I2C Slave I2CSLAVEO 15 3 4 Status Decoding The current I2C status can be easily decoded using the I2COSTAT register Table 15 1 12 Status Decoding on page 167 describes the typical actions firmware should take in each state In the tables STATUS VECTOR refers to the lower five bits 2 05 NACK START STOP WR and RD The shown response options are only the typical responses application specific procedures are allowed as long as they conform to the I2C specification Table 15 1 12 Status Decoding Current Current 2 State
351. tem clock 4 T2ML 0 RW Timer 2 Low Byte Clock Select Selects the clock supplied to Timer 2 If Timer 2 is configured in split 8 bit timer mode this bit selects the clock supplied to the lower 8 bit timer Value Name Description 0 EXTERNAL_CLOCK Timer 2 low byte uses the clock defined by T2XCLK in TMR2CNO 1 SYSCLK Timer 2 low byte uses the system clock 3 T1M 0 RW Timer 1 Clock Select Selects the clock source supplied to Timer 1 Ignored when C T1 is set to 1 Value Name Description 0 PRESCALE Timer 1 uses the clock defined by the prescale field SCA 1 SYSCLK Timer 1 uses the system clock silabs com Smart Connected Energy friendly Preliminary Rev 0 2 251 EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 Bit 2 TOM 0 RW Reset Access Description Timer 0 Clock Select Selects the clock source supplied to Timer Ignored when is set to 1 Value Name Description 0 PRESCALE Counter Timer 0 uses the clock defined by the prescale field SCA 1 SYSCLK Counter Timer 0 uses the system clock 1 0 SCA 0 0 RW Timer 0 1 Prescale These bits control the Timer 0 1 Clock Prescaler Value Name Description 0x0 SYSCLK DIV 12 System clock divided by 12 0 1 SYSCLK DIV 4 System clock divided by 4 0x2 SYSCLK DIV 48 System clock divided by 48 0 3 EXTOSC DIV 8 External oscillator divided by 8 synchronized with the system c
352. ten to send an ACK 1 or NACK 0 to a master request Note that the logic level of the ACK bit on the SMBus interface is inverted from the logic of the register ACK bit silabs com Smart Connected Energy friendly Preliminary Rev 0 2 235 EFM8BB2 Reference Manual System Management Bus I2C SMBO Reset Access Description 0 Sl 0 RW SMBus Interrupt Flag This bit is set by hardware to indicate that the current SMBus state machine operation such as writing a data or address byte is complete and the hardware needs additional control from the firmware to proceed While SI is set SCL is held low and SMBus is stalled SI must be cleared by firmware Clearing SI initiates the next SMBus state machine operation 18 4 4 SMBOADR SMBus 0 Slave Address Bit 7 6 5 4 3 2 1 0 SLV GC Access RW RW Reset 0x00 0 SFR Page 0x0 0x20 SFR Address OxD7 Bit Name Reset Access Description 7 1 SLV 0x00 RW SMBus Hardware Slave Address Defines the SMBus Slave Address es for automatic hardware acknowledgement Only address bits which have a 1 in the corresponding bit position in SLVM are checked against the incoming address This allows multiple addresses to be recog nized 0 GC 0 RW General Call Address Enable When hardware address recognition is enabled EHACK 1 this bit will determine whether the General Call Address 0x00 is also recognized by hardware Value Name Desc
353. the MSB of the priority field for the UARTO interrupt UARTO Interrupt Priority Control MSB 3 PHT1 0 RW Timer 1 Interrupt Priority Control MSB This bit sets the MSB of the priority field for the Timer 1 interrupt 2 PHX1 0 RW External Interrupt 1 Priority Control MSB This bit sets the MSB of the priority field for the External Interrupt 1 interrupt 1 PHTO 0 RW Timer 0 Interrupt Priority Control MSB This bit sets the MSB of the priority field for the Timer 0 interrupt 0 PHXO 0 RW External Interrupt 0 Priority Control MSB This bit sets the MSB of the priority field for the External Interrupt O interrupt Preliminary Rev 0 2 40 silabs com Smart Connected Energy friendly EFM8BB2 Reference Manual Interrupts 6 3 4 EIE1 Extended Interrupt Enable 1 Bit 7 6 5 4 3 2 1 0 ECP1 ECPO EADCO EWADCO EMAT ESMBO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 0x10 SFR Address Bit Reset Access Description 7 0 RW Timer 3 Interrupt Enable This bit sets the masking of the Timer 3 interrupt Value Name Description 0 DISABLED Disable Timer 3 interrupts 1 ENABLED Enable interrupt requests generated by the or TF3H flags 6 ECP1 0 RW Comparator1 CP1 Interrupt Enable This bit sets the masking of the CP1 interrupt Value
354. the comparator supply current while shorter response times require more supply current silabs com Smart Connected Energy friendly Preliminary Rev 0 2 134 EFM8BB2 Reference Manual Comparators and CMP1 13 3 2 Hysteresis The comparator hysteresis is software programmable via its Comparator Control register CMPnCN The user can program both the amount of hysteresis voltage referred to the input voltage and the positive and negative going symmetry of this hysteresis around the threshold voltage The comparator hysteresis is programmable using the CPHYN and CPHYP fields in the Comparator Control Register CMPnCN The amount of negative hysteresis voltage is determined by the settings of the CPHYN bits Settings of 20 10 or 5 mV nominal of nega tive hysteresis can be programmed or negative hysteresis can be disabled In a similar way the amount of positive hysteresis is deter mined by the setting the CPHYP bits Positive programmable hysteresis CPHYP Negative programmable hysteresis CPHYN Figure 13 2 Comparator Hysteresis Plot 13 3 3 Input Selection Comparator inputs may be routed to port I O pins or internal signals When connected externally the comparator inputs can be driven from 0 25 V to VDD 0 25 V without damage or upset The register selects the inputs for the associated comparator The field selects the comparator s positive input CPnP x and the CMXN
355. through the end of the data phase Data will be transferred into the receive buffer under the following conditions There is room in the receive buffer for the data MCE is setto 1 and the stop bit is also 1 XBE 0 MCE is set to 1 and the extra bit is also 1 XBE 1 MCE is 0 stop or extra bit will be ignored In the event that there is not room in the receive buffer for the data the most recently received data will be lost The RI flag will be set any time an unread data byte is in the buffer RXCNT is not equal to 0 Firmware may read the 8 LSBs of received data by reading the SBUF1 register The RBX bit in SCON1 will represent the extra received bit or the stop bit depending on whether is enabled If the extra bit is enabled it should be read prior to reading SBUF1 Firmware may continue to read the re ceive buffer until it is empty RI will be cleared to 0 If firmware reads the buffer while it is empty the most recent data byte will be returned again If it is necessary to flush the contents of the receive FIFO entirely firmware may do so by writing the RFLSH bit to 1 A flush will reset the internal FIFO counters and any data in the buffer will be lost Note Hardware will clear the RFLSH bit back to 0 when the flush operation is complete This takes only one SYSCLK cycle so firm ware will always read a 0 on this bit silabs com Smart Connected Energy friendly Preliminary Rev 0 2 274 EFM8BB2 Refe
356. through the end of the data phase Data will be transferred into the receive buffer under the following conditions There is room in the receive buffer for the data MCE is setto 1 and the stop bit is also 1 XBE 0 MCE is set to 1 and the extra bit is also 1 XBE 1 MCE is 0 stop or extra bit will be ignored In the event that there is not room in the receive buffer for the data the most recently received data will be lost The RI flag will be set any time that valid data has been pushed into the receive buffer If RI interrupts are enabled RI will trigger an interrupt Firmware may read the 8 LSBs of received data by reading the SBUF 1 register The RBX bit in SCON1 will represent the extra received bit or the stop bit depending on whether is enabled If the extra bit is enabled it should be read prior to reading SBUF1 21 3 5 Data Transfer With FIFO UART 1 includes receive and transmit buffers to reduce the amount of overhead required for system interrupts In applications requiring higher baud rates the FIFOs may also be used to allow for additional latency when servicing interrupts The transmit FIFO may be pre loaded with additional bytes to maximize the outgoing throughput while the receive FIFO allows the UART to continue receiving addi tional bytes of data between firmware reads Configurable thresholds may be set by firmware to dictate when interrupts will be gener ated and a receive timeout feature keeps rece
357. till active in stop mode Any enabled reset source will reset the de vice 1 SHUTDOWN Regulator is shut down in stop mode Only the RSTb pin or power cycle can reset the device 2 0 Reserved Must write reset value silabs com Smart Connected Energy friendly Preliminary Rev 0 2 52 EFM8BB2 Reference Manual Power Management and Internal Regulators 7 9 4 REG1CN Voltage Regulator 1 Control Bit 7 6 2 1 0 REG1ENB Reserved BIASENB SUSEN Reserved Access RW R RW RW R Reset 0 0x0 0 0 0 SFR Page 0x20 SFR Address 0xC6 Bit Reset Access Description 7 0 RW Voltage Regulator 1 Disable This bit may be used to disable the 5V regulator if an external regulator is used to power VDD VREGIN should be tied to VDD in any system that disables this regulator 6 3 Reserved Must write reset value 2 BIASENB 0 RW Regulator Bias Disable The BIASENB bit disables the regulator bias voltage when set to 1 Value Name Description 0 ENABLED Regulator bias is enabled 1 DISABLED Regulator bias is disabled 1 SUSEN 0 RW Voltage Regulator 1 Suspend Enable When set to 1 this bit places the 5V regulator into suspend mode Value Name Description 0 NORMAL The 5V regulator is in normal power mode Normal mode is the highest perform ance mode for the regulator 1 SUSPEND The 5V regulator is in suspend power mode Suspend mode reduces the regula tor bias current
358. to 20 external inputs Single ended 12 bit and 10 bit modes Supports an output update rate of 200 ksps samples per second in 12 bit mode or 800 ksps samples per second in 10 bit mode Operation in low power modes at lower conversion speeds Asynchronous hardware conversion trigger selectable between software external I O and internal timer sources Output data window comparator allows automatic range checking Support for burst mode which produces one set of accumulated data per conversion start trigger with programmable power on set tling and tracking time Conversion complete and window compare interrupts supported Flexible output data formatting Includes an internal fast settling reference with two levels 1 65 V and 2 4 V and support for external reference and signal ground Integrated temperature sensor 12 3 Functional Description 12 3 1 Clocking The ADC is clocked by an adjustable conversion clock SARCLK SARCLK is a divided version of the selected system clock when burst mode is disabled ADBMEN 0 or a divided version of the HFOSCO oscillator when burst mode is enabled ADBMEN 1 The clock divide value is determined by the ADOSC field In most applications SARCLK should be adjusted to operate as fast as possible without exceeding the maximum electrical specifications The SARCLK does not directly determine sampling times or sampling rates 12 3 2 Voltage Reference Options The voltage referen
359. to low transitions on the T2 input pin 0 1 LFOSC Capture high to low transitions of the LFO oscillator 0x2 COMPARATORO Capture high to low transitions of the Comparator 0 output 19 4 15 TMR3RLL Timer 3 Reload Low Byte Bit 7 6 5 4 3 2 1 0 TMR3RLL Access RW Reset 0x00 SFR Page 7 0x0 0x10 SFR Address 0x92 Description Reset Access 7 0 TMR3RLL 0x00 RW Timer 3 Reload Low Byte When operating one of the auto reload modes TMR3RLL holds the reload value for the low byte of Timer 3 TMR3L When operating in capture mode TMR3RLL is the captured value of TMR3L Preliminary Rev 0 2 259 silabs com Smart Connected Energy friendly EFM8BB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 and Timer4 19 4 16 TMR3RLH Timer 3 Reload High Byte Bit 7 6 4 1 0 TMR3RLH Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address 0x93 Bit Reset Access Description 7 0 TMR3RLH 0x00 RW Timer 3 Reload High Byte When operating in one of the auto reload modes TMR3RLH holds the reload value for the high byte of Timer 3 TMR3H When operating in capture mode TMR3RLH is the captured value of TMR3H 19 4 17 TMR3L Timer 3 Low Byte Bit 7 6 4 1 0 TMR3L Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address 0x94 Bit Reset Access Description 7 0 TMR3L 0x00 RW Timer 3 Low By
360. to watch for a falling edge on a UART RX line and generate an interrupt or wake up the device from a low power state However if two functions share the same pin the crossbar will have control over the output characteristics of that pin and the dedicated function will only have input access Likewise it is possible for firmware to read the logic state of any digital I O pin as signed to a crossbar peripheral but the output state cannot be directly modified Figure 11 3 Crossbar Priority Decoder Example Assignments on page 81 shows an example of the resulting pin assignments of the device with UARTO and SPIO enabled and P0 3 skipped POSKIP 0x08 UARTO is the highest priority and it will be assigned first The UARTO pins can only appear at fixed locations in this example P0 4 and 0 5 so it occupies those pins next highest ena bled peripheral is SPIO P0 0 1 and 2 are free so SPIO takes these three pins The fourth pin NSS is routed to P0 6 because 0 3 is skipped 0 4 and 5 are already occupied by the UART Any other pins on the device are available for use as general purpose digital I O or analog functions 312 T5 4 T8 T8 7 UARTO TX UARTO RX SPIO SCK SPIO MISO SPIO MOSI SPIO NSS 0 0 0 10000 Pin Skip Settings POSKIP UARTO is assigned to fixed pins and has priority over SPIO SPIO is assigned to available un skipped pins
361. tor to settle and for the converted result to be accurate silabs com Smart Connected Energy friendly Preliminary Rev 0 2 114 EFM8BB2 Reference Manual Analog to Digital Converter ADCO Settling Time Requirements The absolute minimum tracking time is given in the electrical specifications tables It may be necessary to track for longer than the mini mum tracking time specification depending on the application For example if the ADC input is presented with a large series impe dance it will take longer for the sampling cap to settle on the final value during the tracking phase The exact amount of tracking time required is a function of all series impedance including the internal mux impedance and any external impedance sources the sam pling capacitance and the desired accuracy MUX Select Input Channel RCinput Ruux Note The value of CsampLe depends on the gain See the electrical specifications for details CSAMPLE Figure 12 2 ADC Eqivalent Input Circuit The required ADCO settling time for a given settling accuracy SA may be approximated as follows n t n SA TOTAL X Where SA is the settling accuracy given as a fraction of an LSB for example 0 25 to settle within 1 4 LSB tis the required settling time in seconds is the sum of the ADC mux resistance and any external source resistance
362. ual Port I O Crossbar External Interrupts and Port Match 11 4 5 POMASK Port 0 Mask Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 0x20 SFR Address OxFE Bit Reset Access Description 7 B7 0 RW Port 0 Bit 7 Mask Value Value Name Description 0 IGNORED 7 pin logic value is ignored and will not cause a port mismatch event 1 COMPARED 7 pin logic value is compared to POMAT 7 6 B6 0 RW Port 0 Bit 6 Mask Value See bit 7 description 5 B5 0 RW Port 0 Bit 5 Mask Value See bit 7 description 4 B4 0 RW Port 0 Bit 4 Mask Value See bit 7 description 3 B3 0 RW Port 0 Bit 3 Mask Value See bit 7 description 2 B2 0 RW Port 0 Bit 2 Mask Value See bit 7 description 1 B1 0 RW Port 0 Bit 1 Mask Value See bit 7 description 0 BO 0 RW Port 0 Bit 0 Mask Value See bit 7 description silabs com Smart Connected Energy friendly Preliminary Rev 0 2 90 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 6 POMAT Port 0 Match Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 SFR Page 0x0 0x20 SFR Address OxFD Bit Reset Access Description 7 B7 1 RW Port 0 Bit 7 Match Value Value Name Description
363. ual System Management Bus I2C SMBO Hardware ACK Generation When the EHACK bit in register SMBOADM is set to 1 automatic slave address recognition and ACK generation is enabled As a re ceiver the value currently specified by the ACK bit will be automatically sent on the bus during the ACK cycle of an incoming data byte As a transmitter reading the ACK bit indicates the value received on the last ACK cycle The ACKRQ bit is not used when hardware ACK generation is enabled If a received slave address is NACKed by hardware further slave events will be ignored until the next START is detected and no interrupt will be generated Table 18 2 Sources for Hardware Changes to SMBOCNO Bit Set by Hardware When Cleared by Hardware When MASTER A START is generated A STOP is generated Arbitration is lost TXMODE START is generated A START is detected SMBODAT is written before the start of an Arbitration is lost SMBus frame SMBODAT is not written before the start of an SMBus frame STA A START followed by an address byte is re Must be cleared by software ceived STO STOP is detected while addressed pending STOP is generated slave Arbitration is lost due to a detected STOP ACKRQ A byte has been received and an re After each ACK cycle sponse value is needed only when hard ware ACK is not enabled ARBLOST A repeated START is detected as a MAS Each time is clea
364. ue See bit 7 description 0 BO 0 RW Port 1 Bit 0 Mask Value See bit 7 description silabs com Smart Connected Energy friendly Preliminary Rev 0 2 96 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 12 P1MAT Port 1 Match Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 SFR Page 0x0 0x20 SFR Address OXED Bit Reset Access Description 7 B7 1 RW Port 1 Bit 7 Match Value Value Name Description 0 LOW P1 7 pin logic value is compared with logic LOW 1 HIGH P1 7 pin logic value is compared with logic HIGH 6 B6 1 RW Port 1 Bit 6 Match Value See bit 7 description 5 B5 1 RW Port 1 Bit 5 Match Value See bit 7 description 4 B4 1 RW Port 1 Bit 4 Match Value See bit 7 description 3 B3 1 RW Port 1 Bit 3 Match Value See bit 7 description 2 B2 1 RW Port 1 Bit 2 Match Value See bit 7 description 1 B1 1 RW Port 1 Bit 1 Match Value See bit 7 description 0 BO 1 RW Port 1 Bit 0 Match Value See bit 7 description silabs com Smart Connected Energy friendly Preliminary Rev 0 2 97 EFM8BB2 Reference Manual Port I O Crossbar External Interrupts and Port Match 11 4 13 P1 Port 1 Pin Latch Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access R
365. ugh the SPInDAT register To write data into the transmit buffer firmware should first check the status of the TXNF bit If TXNF reads 1 there is room in the buffer and firmware may write to the SPInDAT register Writing the transmit buffer when TXNF is 0 will cause a write collision error and the data written will not be accepted into the buffer To read data from the receive FIFO firmware should check the state of the RXE bit When RXE is 0 it means there is data available in the receive FIFO and it may be read using the SPInDAT register When RXE is 1 the receive FIFO is empty Reading an empty receive FIFO returns the most recently received byte The data in either FIFO may be flushed i e FIFO pointers reset by setting the corresponding flush bit to 1 TFLSH will reset the trans mit FIFO and RFLSH will reset the receive FIFO Half Duplex Operation SPI transfers are inherently full duplex However the operation of either FIFO may be disabled to facilitate half duplex operation The TXHOLD bit is used to stall transmission of bytes from the transmit FIFO TXHOLD is checked by hardware at the beginning of a byte transfer If TXHOLD is 1 at the beginning of a byte transfer data will not be pulled from the transmit FIFO Instead the inter face will hold the output pin at the logic level defined by the TXPOL bit The RXFIFOE bit may be used to disable the receive FIFO If RXFIFOE is 0 at the end of a byte transfer the received byte
366. ule is designed to provide hardware calculations for flash memory verification and communications protocols The CRC module supports the standard CCITT 16 16 bit polynomial 0x1021 and includes the following features Support for CCITT 16 polynomial Byte level bit reversal Automatic CRC of flash contents on one or more 256 byte blocks nitial seed selection of 0x0000 or OxFFFF 1 7 Analog 12 Bit Analog to Digital Converter ADCO The ADC is a successive approximation register SAR ADC with 12 10 and 8 bit modes integrated track and hold and a program mable window detector The ADC is fully configurable under software control via several registers The ADC may be configured to measure different signals using the analog multiplexer The voltage reference for the ADC is selectable between internal and external reference sources Up to 20 external inputs Single ended 12 bit and 10 bit modes Supports an output update rate of 200 ksps samples per second in 12 bit mode or 800 ksps samples per second in 10 bit mode Operation in low power modes at lower conversion speeds Asynchronous hardware conversion trigger selectable between software external and internal timer sources Output data window comparator allows automatic range checking Support for burst mode which produces one set of accumulated data per conversion start trigger with programmable power on set tling and tracking time Conversion comp
367. ure the crossbar to skip the selected pin s IEO and IE1 in the TCON register serve as the interrupt pending flags for the INTO and INT1 external interrupts respectively If an INTO or INT1 external interrupt is configured as edge sensitive the corresponding interrupt pending flag is automatically cleared by the hard ware when the CPU vectors to the ISR When configured as level sensitive the interrupt pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit INOPL or IN1PL the flag remains logic O while the input is inactive The external interrupt source must hold the input active until the interrupt request is recognized It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated 11 3 5 Port Match Port match functionality allows system events to be triggered by a logic value change one or more port I O pins A software control led value stored the registers specifies the expected or normal logic values of the associated port pins for example POMATCH 0 would correspond to P0 0 A port mismatch event occurs if the logic levels of the port s input pins no longer match the software controlled value This allows software to be notified if a certain change or pattern occurs on the input pins regardless of the XBRn settings The PnMASK registers be used to individually select which pins should be compar
368. urns the supply monitor circuit on off The supply monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC Selecting the supply monitor as a reset source before it has stabilized may generate a system reset In systems where this reset would be undesirable a delay should be introduced between enabling the supply monitor and selecting it as a reset source Value Name Description 0 DISABLED Supply Monitor Disabled 1 ENABLED Supply Monitor Enabled 6 VDDSTAT Varies R Supply Status This bit indicates the current power supply status Supply monitor output Value Name Description 0 BELOW Vpp is at or below the supply monitor threshold 1 ABOVE Vpp is above the supply monitor threshold 5 0 Reserved Must write reset value silabs com Smart Connected Energy friendly Preliminary Rev 0 2 66 EFM8BB2 Reference Manual CIP 51 Microcontroller Core 10 CIP 51 Microcontroller Core 10 1 Introduction The CIP 51 microcontroller core is a high speed pipelined 8 bit core utilizing the standard MCS 51 instruction set Any standard 803x 805x assemblers and compilers can be used to develop software The MCU family has a superset of all the peripherals included with a standard 8051 The CIP 51 includes on chip debug hardware and interfaces directly with the analog and digital subsystems pro viding a complete data acquisition or control system solution
369. utput is used to clear CEXn as follows when CPCPOL 0 CEXn is cleared on the falling edge of the ComparatorO output 0 Output 22 CPCPOL 0 1 Figure 16 12 CEXn with CPCEn 1 CPCPOL 0 When CPCPOL 1 CEXn is cleared the rising edge of the ComparatorO output CEXn CPCEn 0 2 1 Output 1 34 22 3 1 Figure 16 13 CEXn with CPCEn 1 CPCPOL 1 In the PWM cycle following the current cycle should the Comparator 0 output remain logic low when CPCPOL 0 or logic high when CPCPOL 1 CEXn will continue to be cleared 0 Output CPCPOL 0 1 Figure 16 14 CEXn with CPCEn 1 CPCPOL 0 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 187 EFM8BB2 Reference Manual Programmable Counter Array PCAO 0 01 Output CPCPOL 1 1 16 4 0 Control Registers 16 4 1 0 Control Figure 16 15 CEXn with CPCEn 1 CPCPOL 1 Bit 7 6 4 2 1 0 CR Reserved CCF2 CCF1 CCFO A
370. value writes should be synchronized with the PCA CCFn match flag to ensure seamless updates 16 Bit PWM mode is enabled by setting the ECOMn PWMn and PWM16n bits in the PCAOCPMn register For a varying duty cycle the match interrupt flag should be enabled ECCFn 1 AND MATn 1 to help synchronize the capture compare register writes If the bit is set to 1 the CCFn flag for the module is set each time a match edge or up edge occurs The CF flag in PCAOCNO can be used to detect the overflow or down edge Important When writing a 16 bit value to the PCAO Capture Compare registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMn bit to 0 writing to PCAOCPHn sets ECOMn to 1 silabs com Smart Connected Energy friendly Preliminary Rev 0 2 186 EFM8BB2 Reference Manual Programmable Counter Array PCAO 16 3 8 3 Comparator Clear Function In 8 9 10 11 16 bit PWM modes the comparator clear function utilizes the ComparatorO output synchronized to the system clock to clear CEXn to logic low for the current PWM cycle This comparator clear function can be enabled for each PWM channel by setting the CPCEn bits to 1 in the PCAOCLR SFR When the comparator clear function is disabled CEXn is unaffected The asynchronous Comparator 0 output is logic high when the voltage of is greater than and logic low when the voltage of is less than The polarity of the Comparator 0 o
371. ve states Programmable data setup hold times Transmit and receive buffers to help increase throughput in faster applications 18 3 Functional Description 18 3 1 Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The 12 and How to Use It including specifications Philips Semiconductor The 2 Specification Version 2 0 Philips Semiconductor System Management Bus Specification Version 1 1 SBS Implementers Forum silabs com Smart Connected Energy friendly Preliminary Rev 0 2 218 EFM8BB2 Reference Manual System Management Bus I2C SMBO 18 3 2 SMBus Protocol The SMBus specification allows any recessive voltage between 3 0 and 5 0 V different devices on the bus may operate at different voltage levels However the maximum voltage on any port pin must conform to the electrical characteristics specifications The bi direc tional SCL serial clock and SDA serial data lines must be connected to a positive power supply voltage through a pullup resistor or similar circuit Every device connected to the bus must have an open drain or open collector output for both the SCL and SDA lines so that both are pulled high recessive state when the bus is free The maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns respectively VDD 5V VDD 3V
372. vice is put into the reset state After a ComparatorO reset the CORSEF flag will read 1 signifying ComparatorO as the reset source otherwise this bit reads 0 The state of the RSTb pin is unaffected by this reset silabs com Smart Connected Energy friendly Preliminary Rev 0 2 63 EFM8BB2 Reference Manual Reset Sources and Power Supply Monitor 9 3 7 Watchdog Timer Reset The programmable Watchdog Timer WDT can be used to prevent software from running out of control during a system malfunction The WDT function can be enabled or disabled by software as described in the watchdog timer section If a system malfunction prevents user software from updating the WDT a reset is generated and the WDTRSF bit is set to 1 The state of the RSTb pin is unaffected by this reset 9 3 8 Flash Error Reset If a flash read write erase or program read targets an illegal address a system reset is generated This may occur due to any of the following A flash write or erase is attempted above user code space A flash read is attempted above user code space A program read is attempted above user code space i e a branch instruction to the reserved area A flash read write or erase attempt is restricted due to a flash security setting The FERROR bit is set following a flash error reset The state of the RSTb pin is unaffected by this reset 9 3 9 Software Reset Software may force a reset by writing a 1 to the SWRSF bit The SW
373. vice routines examination of the program s call stack and reading writing the contents of registers and memory This method of on chip debugging is completely non intrusive requiring no RAM stack timers or other on chip resources The CIP 51 is supported by development tools from Silicon Labs and third party vendors Silicon Labs provides an integrated develop ment environment IDE including editor debugger and programmer The IDE s debugger and programmer interface to the CIP 51 via the C2 interface to provide fast and efficient in system device programming and debugging Third party macro assemblers and C com pilers are also available 10 3 2 Prefetch Engine The CIP 51 core incorporates a 2 byte prefetch engine to enable faster core clock speeds Because the access time of the flash memo ry is 40 ns and the minimum instruction time is 20 ns the prefetch engine is necessary for full speed code execution Instructions are read from flash memory two bytes at a time by the prefetch engine and given to the CIP 51 processor core to execute When running linear code code without any jumps or branches the prefetch engine allows instructions to be executed at full speed When a code branch occurs the processor may be stalled for up to two clock cycles while the next set of code bytes is retrieved from flash memory The PFEOCN register controls the behavior of the prefetch engine When operating at speeds greater than 25 the prefetch eng
374. voltage is higher External input connections to device I O pins and internal connections are available through separate multiplexers on the positive and negative inputs Hysteresis response time and current consumption may be programmed to suit the specific needs of the application Positive Input Selection Programmable Hysteresis Port Pins Inversion asynchronous Internal LDO Negative Input Reference Selection synchronous Programmable Response Time Figure 13 1 Comparator Block Diagram 13 2 Features The comparator includes the following features Up to 10 or 12 1 external positive inputs Up to 10 or 12 1 external negative inputs Additional input options Internal connection to LDO output Direct connection to GND Direct connection to VDD Dedicated 6 bit reference DAC Synchronous and asynchronous outputs can be routed to pins via crossbar Programmable hysteresis between 0 and 20 mV Programmable response time Interrupts generated on rising falling or both edges PWM output kill feature 13 3 Functional Description 13 3 1 Response Time and Supply Current Response time is the amount of time delay between a change at the comparator inputs and the comparator s reaction at the output The comparator response time may be configured in software via the CPMD field in the CMPnMD register Selecting a longer response time reduces
375. we amp cx wx x90 5 Device Identification 2 2 2 2 2 31 Table of Contents 293 5 1 Device 2 34 5 2 Unique ldentifier 131 5 3 Device Identification Registers oe e 01 5 3 1 DEVICEID Device Identification 8 5 3 2 DERIVID Derivative Identification 8 5 3 3 REVID Revision Identifcation 82 6 Interrupts x uou CX ES 08 D T re Pe 098 6 1 Introduction s e e 133 6 2 Interrupt Sources Vectors 133 6 2 1 Interrupt Priorities 998 6 2 2 Interrupt Late cy 2 2 ee Xe IER qe SE TE Rouge TR Sd 6 2 3 5 RS 223436 89 6 3 Interrupt Control Registers 7 6 33 1 IE Interrupt Enable he Es a 6 3 2 Pz Interrupt Priority d we 6 3 3 IPH Interrupt Priority High e s rl s os or 40 6 3 4 EIE1 Extended Interrupt Enable 1 6 3 5 EIP1 Extended Interrupt Priority 1Low s AB 6 3 6 EIP1H Extended Interrupt Priority 1 Hi
376. will be discarded and the receive FIFO will not be updated TXHOLD and RXFIFOE can be changed by firmware at any time during a transfer Any data currently being shifted out on the SPI interface has already been pulled from the transmit FIFO and changing TXFLSH will not abort that data transfer FIFO Thresholds and Interrupts The number of bytes present in the FIFOs is stored in the SPInFCT register The field indicates the number of bytes in the transmit FIFO while the RXCNT field indicates the number of bytes in the receive FIFO Each FIFO has a threshold field which firmware may use to define when transmit and receive requests will occur The transmit thresh old TXTH is continually compared with the TXCNT field If TXCNT is less than or equal to TXTH hardware will set the flag to 1 The receive threshold RXTH is continually compared with RXCNT If RXCNT is greater than RXTH hardware will set the RFRQ flag to 1 The thresholds can be used in interrupt based systems to specify when the associated interrupt occurs Both the RFRQ and TFRQ flags may be individually enabled to generate an SPI interrupt using the RFRQE and TFRQE bits respecitvely In most applications when RFRQ or TFRQ are used to generate interrupts the SPIF flag should be disabled as an interrupt source by clearing the SPIFEN control bit to 0 Applications may choose to use any combination of interrupt sources as needed In general the following settings
377. will generate an interrupt only if the ninth bit is logic 1 RB8 1 signifying an address byte has been received In the UART interrupt handler software will com pare the received address with the slave s own assigned 8 bit address If the addresses match the slave will clear its MCE bit to enable interrupts on the reception of the following data byte s Slaves that weren t addressed leave their MCE bits set and do not generate interrupts on the reception of the following data bytes thereby ignoring the data Once the entire message is received the addressed slave resets its MCE bit to ignore all transmissions until it receives the next address byte Multiple addresses can be assigned to a single slave and or a single address can be assigned to multiple slaves thereby enabling broadcast transmissions to more than one slave simultaneously The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master slave role is temporarily reversed to enable half duplex transmission between the original master and slave s Master 1 Device Device Figure 20 5 Multi Processor Mode Interconnect Diagram silabs com Smart Connected Energy friendly Preliminary Rev 0 2 268 EFM8BB2 Reference Manual Universal Asynchronous Receiver Transmitter 0 UARTO 20 4 UARTO Control Registers 20 4 1 SCONO UARTO Serial Port Control Bit 7 6 5 4 3 2
378. will occur if either condition is not met As an added precaution if the supply monitor is ever disabled explicitly enable the supply monitor and enable the supply monitor as a reset source inside the functions that write and erase flash memory The supply monitor enable instructions should be placed just after the instruction to set PSWE to a 1 but before the flash write or erase operation instruction Make certain that all writes to the RSTSRC Reset Sources register use direct assignment operators and explicitly do not use the bit wise operators such as AND or OR For example RSTSRC 0x02 is correct RSTSRC 0x02 is incorrect Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1 Areas to check are initialization code which enables other reset sources such as the Missing Clock Detector or Comparator for example and instructions which force a Soft ware Reset A global search on RSTSRC can quickly verify this PSWE Maintenance Reduce the number of places in code where the PSWE bit in register PSCTL is set to a 1 There should be exactly one routine in code that sets PSWE to a 1 to write flash bytes and one routine in code that sets PSWE and PSEE both to a 1 to erase flash pages Minimize the number of variable accesses while PSWE is set to a 1 Handle pointer address updates and loop variable maintenance outside the PSWE 1 PSWE 0 area Disable interrupts prior to setting PS
379. writing the flash key codes in sequence to the FLKEY register The PSWE and PSEE bits remain set until cleared by firmware silabs com Smart Connected Energy friendly Preliminary Rev 0 2 26 EFM8BB2 Reference Manual Flash Memory Erase operation applies to an entire page setting all bytes in the page to OxFF To erase an entire page perform the following steps 1 Disable interrupts recommended 2 Write the first key code to FLKEY 5 3 Write the second key code to FLKEY OxF1 4 Set the PSEE bit register PSCTL 5 Set the PSWE bit register PSCTL 6 Using the MOVX instruction write a data byte to any location within the page to be erased 7 Clear the PSWE and PSEE bits 4 3 2 3 Flash Byte Write Procedure The flash memory is written by firmware using the MOVX write instruction with the address and data byte to be programmed provided as normal operands in DPTR and A Before writing to flash memory using MOVX flash write operations must be enabled by setting the PSWE bit in the PSCTL register to logic 1 this directs the MOVX writes to target flash memory and writing the flash key codes in sequence to the FLKEY register The PSWE bit remains set until cleared by firmware A write to flash memory can clear bits to logic 0 but cannot set them A byte location to be programmed should be erased already set to OxFF before a new value is written To write a byte of flash perform the following steps 1 Disable inter
380. x20 through Ox2F may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode The upper 128 bytes of data memory are accessible only by indirect addressing This region occupies the same address space as the Special Function Registers SFR but is physically separate from the SFR space The addressing mode used by an instruction when accessing locations above Ox7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs In structions that use direct addressing will access the SFR space Instructions using indirect addressing above Ox7F access the upper 128 bytes of data memory General Purpose Registers The lower 32 bytes of data memory locations 0 00 through Ox1F may be addressed as four banks of general purpose registers Each bank consists of eight byte wide registers designated RO through R7 Only one of these banks may be enabled at a time Two bits in the program status word PSW register RSO and RS1 select the active register bank This allows fast context switching when entering subroutines and interrupt service routines Indirect addressing modes use registers RO and R1 as index registers silabs com Smart Connected Energy friendly Preliminary Rev 0 2 8 EFM8BB2 Reference Manual Memory Organization Bit Addressable Locations In addition to direct access to data memory organized as bytes the sixteen data memory locations at 0x20 through Ox2F are
381. yte of the stack 3 Value of the fourth byte of the stack 4 Value of the fifth bottom byte of the stack Notes 1 The top of the stack is the current SFRPAGE setting and can also be directly accessed via the SFRPAGE register Figure 3 1 SFR Page Stack Block Diagram a SFRPGEN oO Y LL D 1 L gt 001 SFR Page t Stack 011 1 100 Y When an interrupt occurs hardware performs the following operations 1 The value if any in the SFRPGIDX 011b location is pushed to the SFRPAGE 100b location 2 The value if any in the SFRPGIDX 010b location is pushed to the SFRPAGE 011b location 3 The value if any in the SFRPGIDX 001b location is pushed to the SFRPAGE 010b location 4 The current SFRPAGE value is pushed to the SFRPGIDX 001b location in the stack 5 SFRPAGE is set to the page associated with the flag that generated the interrupt On a return from interrupt hardware performs the following operations 1 The SFR page stack is popped to the SFRPAGE register This restores the SFR page context prior to the interrupt without soft ware intervention 2 The value in the SFRPGIDX 010b location of the stack is placed in the SFRPGIDX 001b location 3 The value in the SFRPGIDX 011b location of the stack is placed in the SFRPGIDX 010b location 4 The value in the SFRPGIDX 100b location of the stack is placed in the SFRPGIDX 011b location

EFM8 Busy Bee Family EFM8BB2 Reference Manual

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