Cybernetic Micro P-51 User`s Manual
Contents
1. Classical ICE expensive kludge based on umbilical extension P 51 Debugging natural extension P 51 Debug Support The P 51 offers these features that support debugging 8051 software None of these features is available on standard 8051s e Breakpoint operation e Single step operation Each of these features allows the user via the host processor to detect P 51 code execution or data access details that are useful in debugging software All these features are patented or patent pending 20 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM P 51 Breakpoint Processing The 8051 has an undefined opcode 0xA5 that has been defined as a breakpoint instruction in the P 51 When the P 51 encounters a breakpoint instruction it copies the address or location of the breakpoint into a mailbox in dual port RAM then decrements the program counter and pushes it onto the stack and then sets the P 51 program counter to an address in high code RAM address space issues an interrupt 0x2E to the host via IRQ and freezes SERVICE IRQ Fig xxx P 51 Breakpoint processing algorithm Typical Breakpoint Usage Breakpoints break the flow of execution at a particular point in address space then typically turn control over to the user A breakpoint is typically used to determine whether or when the 8051 code execution follows a path including the breakpoin2. OxF0 DPTR Data Pointer 2 bytes 0x82 0x83 Po Poto amp 0x80 0x90 OxAO OxB0 IP Interrupt Priority Control 0xB8 OxA8 0x89 0x88 OxC8 Ox8C Ox8A 0x8D 0x8B OxCD OxCC OxCB OxCA 0x98 0x99 0x87 32 PRELIMINARY 05 30 00 8 51 PM 1999 2000 Cybernetic Micro Systems C My Documents P51chip P51_Man5 doc Working Draft In addition to the standard 8052 special function registers the P 51 implements a few additional registers The additional registers are shown below Additional P 51 Special Function Registers Symbol Square Root data low byte Square Root data high byte Square Root result Dual Data Pointer Select The following locations in the P 51 memory space are used for special functions They Special P 51 Memory Locations are discussed in other sections of this manual and are summarized here Special Memory Function Locations Host Relative Address BASE 0x0000 Function Control Register P 51 Relative Addr XXXX Host access only P51 can only access dpRAM BASE 0x0001 IRQ Control Reg XXXX Host access only P51 can only access dpRAM BASE 0x0002 Base Address Reg XXXX Host access only P51 can only access dpRAM BASE 0x0003 Reserved XXXX Host access only P51 can only access dpRAM BASE OxOFFB Mail Box Lo Byte Data OxOFFB Low byte of break point and single ste
3. The P 51 Peripheral 8051 System on a Chip Cybernetic Micro Systems amp www ControlChips com O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM US patent and copyright law protects Cybernetic Micro Systems hardware and software products This intellectual property shall remain the property of Cybernetic Micro Systems Duplication is subject to a license from Cybernetic Micro Systems Cybernetic Micro Systems reserves the right to improve design or performance characteristics Cybernetic Micro Systems assumes no responsibility for the use of any circuitry other than circuitry embodied in Cybernetic Micro Systems products No other circuit patent licenses are implied Information furnished by Cybernetic Micro Systems is believed to be accurate and reliable However no responsibility is assumed by Cybernetic Micro Systems for its use nor for any infringement of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent right of Cybernetic Micro Systems Further Cybernetic Micro Systems reserves the right to revise this publication and to make changes from time to time in the content hereof without obligation to notify any person or organization of such revision or changes Cybernetic Micro Systems assumes no responsibility for any errors that may appear in this document and makes not comm
4. then execution will continue normally from this location Summary of breakpoint operations required of the user PRE BREAKPOINT 1 Determine location in Code RAM to place breakpoint 2 Save instruction at this code location 3 Write breakpoint into code location 4 Release P 51 from RESET 5 P 51 runs until breakpoint executed POST BREAKPOINT 6 Host reads breakpoint address from dual port RAM mailbox OxFFB OxFFC 7 Host identifies original instruction at this address 8 Host writes original instruction back into Code RAM 9 Host writes breakpoint service routine plus return into high location in Code RAM Base Ox3E2F gt P 51 Code Address 0x2E2F 10 Host releases the P 51 to execute breakpoint service by clearing the Wait flag The Wait flag is bit 6 of the Control Register 11 After the Wait flag is cleared the P 51 will execute the code from address 0x2E2F until a return instruction is encountered The P 51 returns to the location at which the breakpoint was originally detected which now holds the original instruction as per step 8 12 The Host can access data if any placed in dual port RAM by breakpoint service processing 13 Host options using single step may be employed 22 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM P 51 Single Step Processing Breakpoints are stealthy in that they lie unnoticed unless a
5. cleared by the P 51 software the integral dual port RAM is enabled and when this bit is set external devices are enabled As a convenience in selecting the external device the P 51 also generates the CE Out signal which is the inverse of the P1 6 pin Most devices use an active low chip enable signal so the CE Out signal allows you to directly connect an external device to the P 51 without the need for an external inverter Use of these pins for the hardware selection of an external device is optional However P1 6 must always be cleared to allow the P 51 software to access the integral dual port RAM and set to allow access to an external device Finally port pin P3 3 is reserved for use as the interrupt to the P 51 from the integral dual port RAM When the host software writes to dual port RAM location OxFFF this generates an interrupt to the P 51 That interrupt comes to the P 51 through internal logic to the P 51 Extint1 interrupt If the P 51 software has enabled External Interrupt 1 this dual port RAM interrupt causes the P 51 to go to the Extint1 interrupt vector at location 0x13 of the P 51 code space The interrupt signal is removed when the P 51 software reads the dual port RAM location OxFFF to see what code was written by the host Normal applications of the P 51 should not use P3 3 for any purpose except as the dual port RAM interrupt The port 3 register bit P3 3 should be kept high the reset default to allow the dual por
6. finding it set to one 23 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM will again execute the operations described above for the Single Step procedure In this manner the P 51 can be made to single step through its code interrupting the host at every step and telling the host via the mailbox where the next instruction is located Combination of Single Step and Breakpoint Operations Once the P 51 has seen the Single Step flag and entered the WAIT state it will remain there until the host resets the WAIT flag b6 While the P 51 waits the host can access the P 51 Code RAM just as if the P 51 were held in RESET However unlike the case of RESET the P 51 will not begin executing at location zero but will execute from the location specified in the mailbox This is a major difference and allows the host to combine the Breakpoint features with the Single Step features to achieve a very powerful debug capability In particular the host can reach into Code RAM pick up the instruction about to be executed save this instruction and replace it with the breakpoint opcode If the host then clears the WAIT flag the P 51 will execute the breakpoint instruction and generate a breakpoint interrupt with or without the Single Step flag set This breakpoint interrupt service can then be used to access P 51 resources as described in the section on Breakpoint behavior In thi
7. 51 I O pin port 1 6 is used to select between dual port RAM and an external memory or device When P1 6 is set as it is by RESET then the P 51 movx instructions address external memory via the CE out pin 73 When P1 6 is cleared as it is by the clr P1 6 instruction then CE out is disabled i e goes to 1 and the internal dual port RAM is enabled When dual port RAM is enabled all movx operations operate on dual port RAM These include movx a RN read thru P2 Rn movx a Dptr read thru Dptr movx Rn a write thru P2 Rn movx Dptr a write thru Dptr 17 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM P 51 Dual Data Pointers The P 51 possesses two 16 bit Data Pointers instead of the single 16 bit Dptr of the standard 8051 These data pointers are accessed one at a time and are selected by setting or clearing a bit in a special function register as follows The Auxiliary Data Pointer control register exists in Special Function Register space at address 0xA2 The least significant bit bO of this register controls which data pointer is in use The data pointers are identical in behavior although the second data pointer is only accessible when selected and has no separate SFR location Their utility lies in the ability to pre load both data pointers then switch between them by toggling the selection bit in the special functi
8. Bus Base Address jumper inputs rystal Oscillator circuit input also external oscillator module input rystal Oscillator circuit input no connect for 8051 Address Latch Enable output hip Enable Output when low all movx _ instructions access external memory or devices inverse of P1 6 signal O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM P 51 Code RAM Because its operation is simplest we discuss the P 51 Code RAM first As a peripheral device the P 51 expects to be reset by the host via a signal such as the E ISA RESETDRV signal which resets all devices at startup While the P 51 can be placed in reset via this hardware strobe the P 51 will remain in the reset state until released via a software operation as described below During the period while the P 51 is held in RESET the host has access to the P 51 Code RAM This is a key fact of the P 51 operation so we repeat it While the P 51 is RESET the host processor can write into the P 51 s Code RAM When released from RESET the P 51 executes from location O in Code RAM This is the most significant difference between a standalone 8051 52 and the peripheral P 51 Standalone devices store code in non volatile memory such as EPROM ROM FLASH etc Peripheral devices store code in volatile memory therefore a host or an Internet connected device can supply code to the P 51 The
9. P3 3 The inputs to port pins P1 1 and P1 2 are specified by Control Register bits 1 and 2 as discussed in the section describing the Control Register Host Relative Address BASE 0 This allows the host software to optionally control the execution of P 51 code by selecting various combinations of these two bit values Note that both the host and the 25 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM P 51 software must agree on the interpretation of these bit values They are not predefined in any way by the P 51 device Also the bit values read by the P 51 are the inverse of the bit values written into the Control Register In this way a reset in which the Control Register bits are cleared to zero will drive the P1 1 and P1 2 bits of the P 51 to a one value If the P 51 software writes to bits P1 1 and P1 2 the values written will be output on the actual P 51 port pins P1 1 and P1 2 device pins 8 and 7 The values read by the P 51 will still be the values from the Control Register This means that P1 1 and P1 2 do not have the normal bi directional I O behavior of standard 8051 ports Rather these bits have separate outputs P1 1 and P1 2 device pins and separate inputs Control Register bits P 51 port pin P1 6 is used to select between the integral dual port RAM and external devices as explained in the section P 51 Access to Dual Port RAM When this bit is
10. The P 51 may operate with crystal or external clock circuits as shown in the clock figures An external oscillator in the range of 1 to 60 MHz may be used on XTAL1 and must use the same VDD voltage as the P 51 The frequency range for the crystal circuit is 4 to 51 MHz The circuitry is slightly different for fundamental vs third overtone crystals The boundary between fundamental and third overtone crystals is approximately 26 MHz and should be verified with the crystal manufacturer As with standard 8051 devices the internal P 51 serial baud rates assume an 11 059 MHz crystal and multiples thereof O 1999 2000 Cybernetic Micro Systems PRELI M INARY ent lans Working Draft 05 P 51 Demo Circuit SBHE C01 cae ISA BUS PCI 04 coe SIGNALS P4 0 cod F1 1 co Piz Eos P4 3 cor P14 cos SDF P45 coa spa P4 6 C 140 SDS P17 ca Spa PO CA Sba PO C4 SD2 ad PO z C4 Sp 1 PO C45 spa PO 4 C16 IOC HRD Y FOS spia CT 5A19 POE SAI P20 SAI P24 SA15 P22 SA14 P23 GND BOM SA13 P24 STORY BOZ SA12 P25 54 BOG SA11 P285 IRGO B04 SA10 P27 5w BOS SADO P3 0 DRO BOG SADS P3 4 42 BOF SAO P32 SRD ri BOS SADE P33 12 BO SADS P24 GND B40 sand F35 E MES B11 SAn3 P385 EMEMR B12 SAD P37 ID B13 sand CEOUT IOR B14 SADO ALE DACK3 ES RESETDRY CLEOUT DRO B16 ME hii XTALZ DACKI BAF MM las nr XTAL1 DROI B10 EE he RFRSH B18 BELK BA1 ESC LE B20 IRD BA IRQ B21 ROF BA IR QS B22 IR QE CE IRQS B23 ROS WSs I
11. address space are dedicated to system memory and the upper 384K bytes are shared among the system BIOS video memory and special adapters such as the P 51 After a hardware reset from the RstDrv signal the P 51 base address is always set from the values of the Base Address signals to the selected one of 16 addresses Once this base address is known host software can access the Base Address Control Register at the current BASE 2 to change the base address to another value By writing to the Base Address Control Register host software has access to all 6 upper address bits and can select any of the 64 possible Base Addresses The format for the Base Address Control Register is shown below b7 b6 b5 b4 b3 b2 bi b0 BASE ADDR Note that the upper 6 bits of the register correspond to the upper 6 address lines of the desired address pattern Host software would write the desired segment address into this register to select the desired base address For example to select a base address of 0xD4000 1101 0100 0000 0000 0000 host software would write 0xD4 into the Base Address Control Register Also note that the two least significant bits of this register must always be 00 The Base Address Control Register is most useful for selecting base addresses that cannot be selected by the Base Address signals but may also be used to select the same addresses as the Base Address signals as shown above with the 0xD4 example Examples of base
12. every instruction fetch proceeding as usual if the bit is zero When the Single Step flag is set to one the P 51 will enter the Single Step mode as follows The P 51 upon detecting the Single Step flag writes the current value of the Program Counter into the same mailbox used by the Breakpoint instruction that is into location OxFFB OxFFC of the shared memory space It then writes the Single Step Interrupt value Ox2F to location OxFFE thereby generating an interrupt to the host processor Finally the P 51 sets bit 6 of the Control Register to 1 and enters the WAIT state In this fashion the host can at any time during execution halt the P 51 and test the mailbox to find out where the P 51 was executing when halted This information can be used in several ways but we first examine the two main ways in which the P 51 is released from the WAIT state The P 51 is released from the WAIT state when the host processor resets bit b6 of the Control Register The host can optionally reset the Single Step flag at this time or leave the Single Step flag set to one If the Single Step flag is reset when the WAIT flag is reset then the P 51 resumes full speed execution from the location specified in the mailbox OxFFB OxFFC If the Single Step flag is left set to one when the WAIT flag is reset to zero then the P 51 will execute the instruction at the location specified in the mailbox fetch the next instruction test the Single Step flag and
13. host can access the P 51 s code memory only while the P 51 is RESET When the P 51 executes from Code RAM the host is locked out of Code RAM The host can reset the P 51 at any time and regain access to Code RAM Because most users are familiar with the 8051 and understand its standalone capability and limitation we emphasize still again the differences in operation The host downloads code to the P 51 s Code RAM while the P 51 is RESET When the P 51 is released from reset it wakes up and immediately begins executing the downloaded code from location zero O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM The Reset Control Register of the P 51 The P 51 possesses a host accessible control register that is mapped into dual port RAM address space as described below This control register allows the host to bring the P 51 in and out of reset via software as well as driving the P 51 into the reset state via the reset pin RSTDRV on the P 51 P 51 Reset Behavior RESET pin The P 51 is reset when the reset pin RSTDRV is driven hi and remains in reset when the RSTDRV pin returns low RESET control Register The P 51 is reset when the least significant bit of the control register is cleared to 0 and released from reset when this bit is set to 1 Control Register 0 Reset 1 Run The multiple address spaces probably represent the most complex a
14. na aa nde dd nud ecce 21 P 51 Single Step Processing sac ocio cte rama A meras tiennenite 23 Combination of Single Step and Breakpoint Operations 24 The SOST Ports rne eed Dese adque d eod CONDES eaqui doses Qa dod Qe ade dra ub Do 25 Non Standard 8051 Port Usage 25 MEPS SAN SUAUIC HOI SC NEN E o DR O p 27 ARITHMETIC OPERATIONS nn recta se dae se iat ce atc 27 LOGICAL OPERATIONS teet Al ch ts a Erde e ee 28 DATA TRANSFER CRX M 29 BOOLEAN VARIABLE MANIPULATION sm 30 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM PROGRAM BRANCHING ttr nn die dur ter ddr dir en dure 30 Instructions that Affect Flag Settings 31 The P 51 Special Function Registers sstm 32 Standard P 51 Special Function Registers 32 Additional P 51 Special Function Registers 33 Special P 51 Memory Locations recette trennen deerunt 33 Special Memory Function Locations 33 The Base Address Control Register san 34 Physical Dimensions sense 36 PCB Layouten to Eo tI E O RR O en te tee AR end ide ia nine na it 37 Electrical Specificatons 1x9 9 5 o benne COL Es 38 COCK CC UNS O nn ns tes ot te OA SA OUR SEA SD O ANTOINE ne pe ne 39 PaO DEMO CCUM ae eek
15. root is read from a third The square root is computed in one instruction cycle so that the answer may be read as soon as the value has been loaded The Special Function Register locations involved are shown below Special Function Space Reg Name Reg Address SQRT lo SQRT hi SQRT The code fragment below illustrates the use the SQRT function SQRT lo data 0x84 SQRT hi data 0x85 SQRT data 0x86 mov a 4 get hi byte mov SQRT hi a write hi byte mov SQRT lo 0 write lo byte mov a SQRT read answer Note that the data can be loaded directly as an immediate constant value or can be loaded from the accumulator allowing variable data to picked up from memory and loaded into the square root circuits The answer can be read from the SQRT register into the accumulator then used as appropriate Any direct moves to and from the SQRT registers can be used 19 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM Debug Features of the P 51 The classical 8051 does not support debugging with either breakpoints or single step capability Instead special bond out versions of the chips are packaged by specialist companies and sold as ICE In Circuit Emulation tools typically for thousands of dollars The ICE is controlled by a host connected by an umbilical cord to the 8051 bond out chip that is plugged into the system Umbilical Cable 8051 ICE p
16. will interpret the value read from this location The interrupt appearing on IRQ N is a low going pulse When this pulse has been generated by the P 51 writing to 0xFFE all further interrupt pulses to the host are inhibited until the host reads the BASE 0xFFE location After the host reads this location another interrupt can be generated by the P 51 since the lock is removed by the read However a P 51 program does not know that the interrupt has been cleared therefore the appropriate protocol is as follows 13 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM P 51 Protocol to interrupt the host Host BASE 0 BASE 1 BASE FFE FFE Host relative address P 51 relative address P 51 writes INT REQ value to FFE Host receives IRQ N INTERRUPT Host reads SINE RE BASE FFE gt P 51 reads FFE if non zero wait Host writes zero to BASE FFE gt P 51 reads FFE zero indicates host ready for next interrupt To summarize the host must setup the IRQ Control Register and the Master Control Register to allow interrupts to the host on a specified IRQ pin Once this has been done the P 51 can interrupt the host by writing any non zero value into address OxFFE in shared RAM space causing the selected IRQ pin to pulse low The host should respond to this IRQ pulse by reading the value of location BASE OxFFE and interpretin
17. 0 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM Instructions that Affect Flag Settings Instruction Instruction ADD CLR C CPL C ANL C bit ANL C bit ORL C bit ORL C bit MOV C bit CJNE ADDC SUBB MUL DIV DA RRC RLC SETBC Note that operations on SFR byte address 208 or bit addresses 209 215 i e the PSW or bits in the PSW will also affect flag settings X xX x x x x x 0 0 lt gt lt gt lt OOX XXO Note on instruction set and addressing modes Rn Register R7 RO of the currently selected Register Bank direct 8 bit internal data location s address This could be an Internal Data RAM location 0 127 or a SFR i e I O port control register status register etc 128 255 Ri 8 bit internal data RAM location 0 255 addressed indirectly through register R1 or RO data 8 bit constant included in instruction data 16 16 bit constant included in instruction addr 16 16 bit destinationaddress Used by LCALL amp LJMP A branch can be anywhere within the 64K byte Program Memory address space addr 11 11 bit destination address Used by ACALL amp AJMP The branch will be within the same 2K byte page of program memory as the first byte of the following instruction rel Signed two s complement 8 bit offset byte Used by SJMP and all condi
18. 1_Man5 doc Working Draft 05 30 00 8 51 PM Electrical Specifications Absolute Maximum Ratings Ambient Temperature under bias 0 C to 70 C Storage Temperature 55 C to 125 C Vdd Supply Voltage 0 3V to 4 0V Voltage on any I O pin with respect to GND Power Dissipation Temperature Range 0 C to 70 C Vdd Supply Voltage 3 0V to 3 6V Sym Parameter Min Typ Max Unit Remarks Icc pwr supply current 46 80 mA 60 MHz 20 40 mA 40 MHz 16 35 mA 11 MHz 5 Volt tolerant inputs Vih input high voltage 2 0 5 5 M TTL compatible Vil input low voltage 0 2 0 8 V TTL compatible lih input high current 10 10 UA Vin Vdd lil input low current 10 10 UA Vin GND Voh output high voltage 2 4 V loh 4 mA Vol output low voltage 0 4 V lol 4 mA 0 4 V lol 8 mA on loChRdy ioe RER EE vida 10 UA Vin GND to Vdd current Ipu Pull up current 22 66 160 uA Vin GND R 50K ohm Fcy crystal frequency 4 51 MHz see clock circuits Fos oscillator frequency 1 60 MHz see clock circuits 38 O 1999 2000 Cybernetic Micro Systems C My Documents P51chip P51_Man5 doc Working Draft CRYSTAL OSCILLATOR 1 60 MHz Crystal Oscillator Circuit XTAL lt 26 MHz 1MQ XTAL1 5 30pF Fundamental Crystal Circuit XTAL 226 MHz 1M Q 5 30pF Third Overtone Crystal Circuit 39 PRELIMINARY 05 30 00 8 51 PM Clock Circuits
19. AU ek nr ek PRA re 40 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM The P 51 Peripheral 8051 System on a Chip For two decades the 8051 microprocessor computer has served as the standalone solution to countless embedded system applications The flexibility power and familiarity of the 8051 are such that 8051 knowledge is in almost every designer s tool kit A major weakness of the 51 is its interface to a host processor typically either UART based or parallel handshake Because these typically mismatch the speed of the host the Cybernetics P 51 provides a novel tightly coupled architecture for adding the power of the 8051 to a host processor OLD EISA Address Decoder amp Glue Logic amp Bidirectional buffer Peripheral Figure 1 The P 51 peripheral 8051 interfaces directly to an ISA bus PC 104 or equivalent instead of requiring 10 to 20 glue chips as does an 8051 processor The P 51 Peripheral 8051 Architecture Why P 51 First the name As most engineers know the P 51 was the fastest propeller driven fighter in WW Il achieving 451 MPH in level flight and exhibiting a graceful beauty and a deadly effectiveness In honor of this marvelous design we have chosen the P 51 logo The P 51 name is a reminder that this device is a Peripheral 8051 processor not a standalone 8051 processor Most engineers have a clear image of the 8051 CPU so the name
20. FFE BASE FFF Host Intr P 51 FFF Host relative address P 51 relative address Host writes interrupt to BASE FFF to interrupt P 51 gt P 51 interrupted via Extint1 vectors through Code RAM 0013 gt P 51 writes zero to FFF when ready for next interrupt from host Host reads BASE FFF before next interrupt to P 51 must be zero 15 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM Summary of Software Controlled Interrupts dual port RAM Interrupt Host BASE FFE vialRQN BASE FFF gt Interrupt P 51 via Extint1 lt Host Side gt P 51 Side gt The Software Interrupts are symmetrical and are supported by P 51 hardware and extended by software protocols The hardware support allows the interrupts to write to a location and thereby generate an interrupt to the other side If the other side writes to the same location there is no effect except to write a value into memory however if the other side reads the same location then the effect is to clear the interrupts When the interrupting side reads the same location there is no effect Interrupt Location Interrupter gt Interrupted Hardware Mechanism Write Interrupt Write No Effect Read No Effect Read Clear Interrupt Software Protocol Write Interrupt Request Value Write To Signal Ready 0 Read see if other side is ready Read To decode interru
21. INC Increment direct RAM DEC Ri A Decrement Accumulator DEC Rn Decrement Register DEC direct Decrement direct byte DEC Ri Decrement indirect RAM INC DPTR Increment Data Pointer MUL AB Multiply A amp B DIV AB Divide A by B DA All Mnemonics copyrighted Olntel Corporation 1980 A Decimal Adjust Accumulator 27 e N I N Where P 51 timing differs from the original 8051 the 8051 timing is shown in parentheses O 1999 2000 Cybernetic Micro Systems C My Documents P51chip P51_Man5 doc Working Draft LOGICAL OPERATIONS Mnemonic Description PRELIMINARY ANL A Rn AND Register to Accumulator ANL A direct AND direct byte to Accumulator ANL AQRI AND indirect RAM to Accumulator ANL A data AND immediate data to Accumulator ANL direct A AND Accumulator to direct byte ANL direct data AND immediate data to direct byte ORL A Rn OR register to Accumulator ORL A direct OR direct byte to Accumulator ORL A Ri OR indirect RAM to Accumulator ORL A data OR immediate data to Accumulator ORL direct A OR Accumulator to direct byte ORL direct data OR immediate data to direct byte XRL A Rn Exclusive OR register to Accumulator XRL A direct Exclusive OR direct byte to Accumulator XRL A GRi Exclus
22. P 51 focuses on the unique aspect of the P 51 A peripheral 8051 requires a host to which it is peripheral O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM This important difference is key to understanding the P 51 architecture below Host Interface I I I Address gt 256 x8 Data Control DPTR RAM PC 8051 CPU SFR nd IRQ RR PC 104 EISA uC The P 51 Host Bus Interface The P 51 is a peripheral processor and thus serves as a peripheral to a host processor Because most of the ports instruction set I O hardware etc are identical to the 8052 micro controller most engineers need only understand the new host bus interface to begin using the device Host HOST Interface Address Processor DPTR I I IRQ lt q q I I Reset 91i Refresh 3J9 IOChRdy Figure 2 The host interface provides host access to Dual Port RAM and Code RAM and allows the P 51 to interrupt the host using IRQs O 1999 2000 Cybernetic Micro Systems C My Documents P51chip P51_Man5 doc Working Draft PRELIMINARY 05 30 00 8 51 PM As shown in Figure 2 the host processor can access the P 51 s Code RAM and Dual Port RAM via a simple ISA bus compatible interface The host provides a 20 bit address and 8 bit bi directional data bus to the P 51 The P 51 supports the EISA REFRESH amp IOCHRDY and provides a user select
23. R DS B24 IRQA vss IRQS B25 IR Q3 WES DACKS B28 R010 WES TC B27 IRO11 vss BALE B23 IDE S16 IR Q12 WSS 54 B20 IRO4O IRQ15 WES osc Bad IRQ41 Rod vss GND B31 IRQ12 IRDAS IR GH Isa puS Poio4 Pam SIGNALS DACs DROS DACKE P 51 Demonstration Circuit DROG DACT Cybemetic Micro Systems 12 h 2000 DRQ www Control Chips ea m HLMP 6600 T4HCT244 LEDS 1H4002 C8 5201 373 VU LTAGE REGULATO F CRYSTAL OSCILLATOR 1 60 hz ARES RGRSRSSARIIAA PHATE SR ERAS HBSS RABE RSE DELOMAwE 40
24. able IRQ output VDD P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 BCLK RFRSH GND GND GND IRQ15 IRQ14 IRQ12 IRQ11 IRQ10 IRQ9 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 SONS O1 BR N a 10 11 12 13 14 5 P 51 Pinout Diagram DASuANMOATMONOHANTNHONODOMK ANT ASSOC SOZBDSD OBO SANNANNNANNN ZINN gt 000000000000000000000000 94 89 88 87 86 85 84 83 82 80 79 78 99 98 97 96 95 93 92 91 90 81 77 76 O 19 Peripheral 8051 with EISA interface SPOT ANMTMWOR OBST AMYTNORDGDSLWO moeoeooeoooeooeooeooeooeooeorte Se Se ee rtr soa Q LLLLLLLLLLLLLLLLLLLLES gt Ba 9n 01 000 0110 05 190 90 0 0030 a em o c P3 6 P3 7 CE OUT ALE CLK OUT BAO BA1 BA2 XTAL2 XTAL1 GND GND GND BA3 SDO SD1 SD2 SD3 SD4 SD5 SD6 SD7 ALI IOCHRDY VDD O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM P 51 Pin List 1 0 Description 1 50 51 100 3 3 Volt Power Supply Pin Name 90 89 88 87 86 rait 5 84 83 RN 81 80 79 78 77 25 24 23 22 21 20 19 18 17 16 15 ISA Interrupt Request signals open drain No IRQ8 or IRQ13 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 ISA Address Bus Chip Enable low during ISA Read Write _ valid as address signals low to latch SAO to SAT for multiplexed Address Data bus non ISA ISA Data
25. addresses that are not selectable by the external signals would be 0xC4 0xB8 0xA0 and any address between 0x00 and OxA4 However you must verify that the desired base address is available within the memory space of your system and is not being used by another device or system memory If there is a conflict between multiple devices itis possible that the P 51 cannot be accessed at that address 34 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM Since inadvertent writes to the Base Address Control Register can have severe consequences possibly making the P 51 device inaccessible to the host software write access to this register is protected by a 5 step sequence All steps must be taken in the proper sequence to successfully change the P 51 base address Also the P 51 base address should only be changed while the P 51 is being held in reset through the main Control Register at BASE 0 This is shown as step 0 of the sequence below but is not required if the P 51 is still in the reset state from a system hardware reset The steps for changing the P 51 base address are O Write 0x00 0000 0000 to the Control Register at the current BASE O 1 Write 0x40 0100 0000 to the IRQ Control Register at the current BASE 1 2 Write the desired new base address value to the Base Address Control Register at the current BASE 2 3 Write 0x80 1000 0000 to the IRQ Cont
26. al port RAM is at the BASE address as seen by the host and at address zero of Data Memory as seen by the P 51 Host Address of Dual P 51 Address of Dual Port Ram Port Ram using movx Shared Ram BASE 3 0 P 51 Address BASE FFF 3 Host Data Note that unlike Code RAM which is accessible only when the P 51 is RESET and the BASE address 1000 is presented to the P 51 the dual port RAM is accessible by the host whenever the BASE address is presented to the P 51 Chip Enable and Read Write strobes Although the host must present an address that matches the BASE address set into the BASE address latch the P 51 does not actually allow access to dual port RAM or Code RAM unless the Chip Enable pin 49 is asserted low and a read or write strobe is presented to the P 51 10 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM Special Control Registers in Shared Memory Space Now that we know how to access shared memory space from the host we can understand how to access several control registers mapped into dual port RAM space Specifically the first four addresses in shared memory space access control registers as well as dual port RAM Thus when the host writes to address BASE 0 BASE 1 BASE 2 or BASE 3 the control registers are addressed and data is also written into dual port RAM Similarly the last two addresses in dual port RAM space are ma
27. at BASE 0x1000 BASE 4096 For example if BASE is set to OxOD 1101 then the base address is set to OxE4 11100100 which corresponds to segment 0xE400 in an 80x86 Real mode segment register The net effect is to set the six most significant bits from the appropriate base address value in the Base Table as the active Base Address These six bits are compared to the six most significant bits of the 20 bit address applied by the host to the P 51 When these six address bits match the P 51 is selected else the P 51 is de selected and no access to P 51 Address space is available to the host O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM Base Address Switch Settings Switch Segment Settings Address usas All Open 1111 We consider three example cases in detail Base Address Host Address to select P 51 Base 000000 0000 0000 0000 0000 0000 101101 1011 0100 0000 0000 0000 The first case is the default base in which both the P 51 and the host addresses begin at zero While this may be appropriate for many embedded applications it is typically inappropriate for IBM PC type applications in which address zero for the PC is dedicated to other functions In the case in which the Base address is set to 0101 the six base address bits are 101100 which corresponds to a host address 1011 0100 0000 0000 0000 When t
28. bit to Carry ORL C bit OR direct bit to Carry ORL C bit OR complement of direct bit to Carry MOV C bit Move direct bit to Carry bit C Move Carry to direct bit Rel Jump if Carry is set Rel Jump if Carry not set bit rel Jump if direct Bit is set bit rel Jump if direct Bit is Not set bit rel Jump if direct Bit is set amp clear bit WIWVIWVINININININININININI gt INJ gt IN gt PROGRAM BRANCHING Mnemonic Description U lt gt D Period 24 24 24 24 ACALL addr11 Absolute Subroutine Call LCALL addr16 Long Subroutine Call RET Return from Subroutine RETI Return from interrupt AJMP addr11 Absolute Jump LJMP addr16 Long Jump SJMP rel Short Jump relative addr JMP A DPTR Jump indirect relative to the DPTR JZ rel Jump if Accumulator is Zero JNZ rel Jump if Accumulator is Not Zero CJNE A direct rel Compare direct byte to Acc and Jump if Not Equal CJNE A data rel Compare Immediate to Acc and Jump if Not Equal CJNE Rn data rel Compare immediate to register and Jump if Not Equal CJNE Ri data rel Compare immediate to indirect and Jump if Not Equal DJNZ Rn rel Decrement register amp Jump if Not Zero DJNZ direct rel Decrement direct byte and Jump if Not Zero NOP No Operation COININ AIN O IN A CIN All Mnemonics copyrighted Olntel Corporation 1980 3
29. d Cot 4 PES Code RAM S c oce pe ee DDD DL pite 5 The Reset Control Register of the P 51 ees 6 P 51 Reset Behavior uude riis ie t don La tristes less 6 PAST Address SDaCe AN a mi tue ode 7 Base Address Switch Settings 8 Gode RAM ACCESS un and ates tie as tls cht hed le is ts UA 9 Host Access to the Dual Port RAM 10 Chip Enable and Read Write strobes eee 10 Special Control Registers in Shared Memory Space 11 Control Register Detail sn en tod ele a ad le nile ile nile ile 12 The IRQ Control Register issues 13 Shared Memory Interrupt Locations 13 P 51 Protocol to interrupt the host 14 Host Software Interrupt of P 51 e rreeeeeeaeaaeaererea 15 Summary of Software Controlled Interrupts 16 Hardware Mechanism oasis tol eant ne nd is ne nca 16 Software PTOtOCOL autesteps temores ro eret ote Pt inia 16 P 51 Access to Code RAM Es ein ii ei ann En De XE s CR 17 Host Access to Gode ISAME een ennemis 17 P 51 Access t Dual Port RAM ee once poen Nr E ER ELO Esta Eua 17 51 Dual Data Painters soie da AN ada aa 18 P 51 SQRT function Re eia aguda Ia SEMEN lat I IR ada da 19 Debug Features or the P 571 conocen teet e thee the eet ehe coh 20 51 Debug SUDpDOLL washes tp REM IE Ep chee a 20 P 51 Breakpoint Processing ctia pair add R Ad capice easiest capice ee ns ote 21 Typical Breakpoint Usage o2 24 024 nus odia ndn
30. e IRQ Control Register As may be seen from the pinout diagram the P 51 supports numerous IRQ output pins IRQ 3 to IRQ 15 covering most of the IBM PC IRQ pins of the EISA bus These are open collector outputs that are typically pulled up to 5 volts but can be driven low to interrupt the host Because IRQs are a scarce resource only one is used by the P 51 and is selected by the host via the IRQ Control Register mapped into location BASE 1 of the host address space b7 b6 b5 b4 b3 b2 b1 bO BASE 1 IRQ IRQ Gate The low nibble is set to the desired IRQ for example 0101 selects IRQ 5 while 1111 selects IRQ 15 etc Bit G IRQ 4 is the Interrupt GATE which enables or disables the IRQ in combination with Control Register bit CR 3 The most significant bits of the IRQ Control Register must be set to zero Shared Memory Interrupt Locations Although the IRQ control gate determines which IRQ output will be used to interrupt the host the actual interrupt mechanism is associated with the INTERRUPT Register at address BASE 0xFFE host perspective or equivalent address 0xFFE P 51 perspective When the P 51 writes to address 0xFFE in shared memory space an interrupt is generated and sent to the host on IRQ N if the IRQ control register contains 0001 N and the Control Register 0001 1xx1 The host is assumed to contain an appropriate ISR Interrupt Service Routine which will read the interrupt register at BASE 0xFFE and
31. e P 51 to the host For example if the host is not prepared to service interrupts from the P 51 then CR 3 should be set to zero To allow P 51 interrupts set bit CR 3 to one CR 1 and CR 2 control register bits are mapped into Port 1 bit 1 and Port 1 bit 2 that is a P 51 can read CR 1 on P1 1 and CR 2 on P1 2 These user definable bits allow for example the user to specify two mode bits that the P 51 software can test while executing There are no preferred values for these bits as their value and their meanings are completely user defined Debug Bits CR 5 CR 6 and CR 7 are defined in a later section and should usually be set to zero Note that the Control Register does not allow individual bit access That is all eight bits must be written at once Therefore the values written to the control register must set or reset the desired bit while preserving the remaining bits For example to reset the P 51 and then download code to address N of the Code RAM at host address BASE 0x1000 N the user host should write 0001 0000 0x10 to the Control Register which is located at BASE address After the download is finished the user can write 0001 0001 0x11 to release the P 51 from RESET but with interrupts inhibited or write 0001 1001 0x19 to release the P 51 to execute and to enable the IRQ output to the host 12 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM Th
32. g the value the interpretation is by a pre agreed convention between P 51 program and host When the host has finished and is able and willing to accept more interrupts the host writes zero to BASE OxFFE to signal READY to the P 51 The P 51 should test location OxFFE for zero before writing a value to this address If the value is non zero the P 51 should wait for the value to become zero before writing a non zero interrupt value to OxFFE 14 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM Host Software Interrupt of P 51 The above description details how the P 51 software can generate interrupts to the host via an IRQ pin The converse operation allows the host software to interrupt the P 51 by writing to location BASE OxFFF This write will generate an interrupt on P 51 Port 3 Pin 3 P3 3 which vectors through 8051 External Interrupt 1 location 0x13 hex in P 51 Code RAM The interrupt will cause P3 3 to go low and remain low until the P 51 reads location OxFFF in shared space dual port RAM The act of reading OxFFF from the P 51 side clears the interrupt and P3 3 returns hi The P 51 can interpret the value read from OxFFF to decide what action is being requested Finally the P 51 can write zero to OxFFF signifying to the host that the P 51 is ready to accept further interrupts Host Shared RAM BASE 0 BASE 1 000 1 IRQ N BASE FFE P 51 Intr host
33. he host addresses 0xB4000 the Base address of the P 51 is selected O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM Code RAM Access Assume that the P 51 is attached to an E ISA bus and that it s Base address jumpers are set to 1010 As can be read from the Base Address Table above this selects a Base address of 0xD8000 for the P 51 as seen by the host Since Code RAM is at Base 0x1000 to access the first byte of Code RAM the host must put address D9000 D8000 1000 1101 1001 0000 0000 0000 To access the second byte of Code RAM the host must put hex address 0xD9001 1101 1001 0000 0000 0001 on the 20 bit P 51 host address bus Using these addresses the host can write 8051 binary opcodes into Code RAM that will be executed by the P 51 when the P 51 is released from RESET From the P 51 s perspective the first byte of Code RAM is at location address zero O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM Host Access to the Dual Port RAM As discussed above address zero in the P 51 Code RAM is offset hex into host address space by BASE 0x1000 Thus Code read from location 0x100 as seen by the P 51 program counter will be written into BASE 0x1000 0x100 as seen by the host If this is understood then access to the Dual Port RAM shared memory space is simple The first byte of du
34. i direct Move direct byte to indirect RAM MOV Ri Data Move immediate data to indirect RAM MOV DPTR data16 Load Data Pointer with 16 bit constant MOVC A A DPTR Move Code byte relative to DPTR to Acc MOVC A A PC Move Code byte relative to PC to Acc MOVX A Ri Move External RAM 8 bit addr to Acc MOVX A DPTR Move External RAM 16 bit addr to Acc MOVX 2 Ri A Move Acc to External RAM 8 bit addr MOVX QDPTRA Move Acc to External RAM 16 bit addr PUSH Direct Push direct byte onto stack POP Direct Pop direct byte from stack XCH A Rn Exchange register with Accumulator XCH A direct Exchange direct byte with Accumulator XCH A ORI Exchange indirect RAM with Accumulator N N IN L L B GOJNIINN CONI PN IPININIPKNP2NANN XCHD A GRi Exchange low order Digit indirect RAM with Acc All Mnemonics copyrighted Olntel Corporation 1980 29 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM BOOLEAN VARIABLE MANIPULATION Mnemonic Description U lt gt D CLR C Clear Carry CLR bit Clear direct bit SETB C Set Carry SETB bit Set direct bit CPL C Complement Carry CPL Bit Complement direct bit ANL C bit AND direct bit to Carry ANL C bit AND complement of direct
35. itment to update the information contained herein Because of the wide variety of applications in which this product may be used Cybernetic Micro Systems makes no claim as to the product s fitness for any given application It is therefore the user s responsibility to ensure the safety and viability of using this product in the user s application The following are trademarks and U S patents of Cybernetic Micro Systems Inc Trademarks Patents Bin ASCII CY123 CY300 CY525 5 452 301 CYMPL CY132 CY325 CY545 5 541 930 Analog ASCII CY232 CY327 CY550 5 680 589 ASCII Analog CY233 CY308 CY600 5 721 729 CY233 LINC CY250 CY480 CY750 5 860 021 USB RAM CY251 CY500 6 021 453 P 51 CY252 CY512 Copyright 2000 by Cybernetic Micro Systems Inc All rights reserved no part of this publication may be reproduced for distribution without the prior written permission of Cybernetic Micro Systems Inc PO Box 3000 San Gregorio CA 94074 Tel 650 726 3000 Fax 650 726 3003 www ControlChips com info ControlChips com O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM Table of Contents Table of COnmlentS Lee sa ads ara bI REN ad A HEN S FI E Rn i The P 51 Peripheral 8051 System on a Chip 1 The P 51 Peripheral 8051 Architecture 1 The P 51 Host Bus InterTaee asie dati coire aa t cot Lor tiere 2 P 51 EPITOME VACHE AIM REPRE EAR 3 P5 V PUES cca tec Saree ete a a ae hes re dean un
36. ive OR indirect RAM to Accumulator IN OININ IN OININ A data Exclusive OR immediate data to Accumulator N direct A Exclusive OR Accumulator to direct byte direct data Exclusive OR immediate data to direct byte WIN Clear Accumulator Complement Accumulator Rotate Accumulator Left Rotate Accumulator Left through the Carry Rotate Accumulator Right Rotate Accumulator Right through the Carry Swap nibbles within the Accumulator All Mnemonics copyrighted lntel Corporation 1980 28 O 1999 2000 Cybernetic Micro Systems C My Documents P51chip P51_Man5 doc DATA TRANSFER Mnemonic Working Draft Description PRELIMINARY MOV A Rn Move register to Accumulator MOV A direct Move direct byte to Accumulator MOV A Ri Move indirect RAM to Accumulator MOV A data Move immediate data to Accumulator MOV Rn A Move Accumulator to register MOV Rn direct Move direct byte to register MOV Rn data Move immediate data to register MOV direct A Move Accumulator to direct byte MOV direct Rn Move register to direct byte MOV direct direct Move direct byte to direct MOV direct QRi Move indirect RAM to direct byte MOV direct data Move immediate data to direct byte MOV RiA Move Accumulator to indirect RAM MOV DR
37. nd until they are encountered during the course of execution Associated with this is the need to place the breakpoint opcode in the code space while the host has control of the Code RAM that is while the P 51 is RESET If the host has not placed any break points in Code RAM this feature is not available during the period of execution The host can always access Code RAM by setting the Reset bit b0 in the Control register but this will cause the P 51 to begin execution again therefore it is not generally possible to add breakpoints to Code RAM after execution has begun The P 51 Single Step capability on the other hand allows the host to take control of the P51 while the P 51 is executing code with no prior preparation required This very useful feature is described below The P 51 Single Step is controlled by bit b7 of the Master Control Register which is located at BASE address as seen by the host This bit is normally set to 0 when the P 51 is released from RESET Because this Control register is mapped into shared memory space it is accessible at all times including while the P 51 is executing code Thus the Single Step bit can be set to 1 during P 51 execution Remember that the Control Register is byte accessible not bit accessible so it is necessary to preserve all of the other bits of the Control Register when setting the Single Step bit to one The P 51 actually tests the state of the Single Step bit at then end of
38. on registers This precludes the need with only a single data pointer to point to a first location then save the address point to a second location etc An example of the use of two data pointers to move data from a source buffer to a destination buffer is shown below CONSTANTS SRC_buffer 0x400 location of source bytes DST buffer 0x500 location of destination buffer buf length 0x40 number of bytes to move DP_sel data OxA2 Special function register CODE mov Dptr SRC buffer setup source pointer inc DP sel switch data pointers mov Dptr DST buffer setup destination ptr mov rO buf length Copy Loop inc DP sel switch to source pointer movx a Dptr get source byte inc Dptr next source location inc DP sel switch to dest pointer movx Dptr a put byte into dest buf inc Dptr next destination location djnz r0 Copy Loop repeat til done fall thru with Dptr gt destination 18 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM P 51 SQRT function The P 51 possesses a Square Root function that takes a 16 bit value and returns an 8 bit square root This function does not exist on any other 8051 so we describe its operation below The P 51 SQRT operation utilizes special locations in the Special Function Register address space The 16 bit value is written into two of these locations and the 8 bit square
39. p address BASE OxOFFC Mail Box Hi Byte Data OxOFFC High byte of break point and single step address BASE OxOFFE Interrupt Host Data OxOFFE P51 write interrupts host Host read clears interrupt BASE OxOFFF Interrupt P51 Data OxOFFF Host write interrupts P51 P51 read clears interrupt BASE Ox3E2F Breakpoint Subroutine Code 0x2E2F 33 Start of P51 Subroutine executed after a breakpoint O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM The Base Address Control Register Another special control register is the Base Address Control Register mapped into location BASE 2 of the host address space This register allows the host to dynamically change the base address of the P 51 through software control As indicated previously in the Base Address Settings section one of 16 base addresses may be selected for the P 51 by properly setting the values on the four Base Address signals BAO to BA3 These settings map to 16 specific segment addresses specified by the bit pattern on the upper 6 address lines SA14 to SA19 However with 6 bits it is possible to specify up to 64 possible combinations so the Base Address signals only allow you to select one quarter of the possible addresses We have selected the most useful 16 addresses based on a standard PC architecture where the lower 640K bytes of the
40. pped by special registers Host Addresses Shared Memory P 51 Addresses Space BASE Control Register BASE 1 BASE 2 BASE 3 Locations BASE 4 to BASE FFD are accessed as data by host rd and wr strobes Locations 4 to FFD are accessed as data by P 51 rd and wr strobes BASE FFE FFE BASE FFF Interrupt P 51 FFF The control registers at BASE to BASE 3 are write only and can only be written by the host If the P 51 writes to these locations it only writes into the dual port RAM not into the control registers A read of these location returns the last data written into the dual port RAM 11 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM Control Register Detail b7 b6 b5 b4 b3 b2 b1 bO RESET 0 RUN 1 P1 1 input P1 2 input IRQ enable 1 disable 0 Code RAM enable 1 Reserved Wait flag Single Step flag The P 51 Control Register is the master control that causes the P 51 to be held in the RESET state or to RUN programs from Code RAM If zero is written to this register the P 51 is reset and remains reset while CR O 0 If access to Code RAM is desired then CR 4 must be set to 1 Although CR 4 may be zero for manufacturing test of the P 51 all user operations either downloading code while reset or executing code while running require CR 4 1 CR 3 is an IRQ enable bit that can disable interrupts from th
41. pt request value 16 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM P 51 Access to Code RAM When the P 51 is released from reset the Control Reg must contain 0001 xxx1 its Program Counter PC is set to zero This causes the P 51 to fetch the first byte from Code RAM and begin executing code Normally the first instruction is a jump over vectors During execution the P 51 fetches all instructions from Code RAM using the Program Counter The P 51 has only one access mechanism to Code RAM The 8051 movc a a Dptr allows the P 51 to use a value in the accumulator as an index into a table that Dptr points to and read from the table into the accumulator There is no other P 51 access to Code RAM Host Access to Code RAM The host processor can while the P 51 is held in Reset access Code RAM at locations BASE 0x1000 to BASE Ox2FFF using normal read and write operations from the EISA bus side of Code RAM There is no other host access to Code RAM P 51 Access to Dual Port RAM The P 51 uses the 8051 movx instruction to access its own internal dual port RAM Those familiar with the 8051 will remember that movx is normally used in conjunction with P2 and PO to access external memory or devices outside the 8051 This is still the case in the P 51 however it is complicated by the existence of the integral dual port RAM The solution is as follows The P
42. rol Register at the current BASE 1 4 Again write the new base address value to the BASE Address Control Register at the current BASE 2 5 Now write 0x10 0001 0000 to the Control Register at the new BASE 0 The final step provides host software with access to the P 51 Code RAM so the desired program can be downloaded before the P 51 is released from reset Host software should also select the desired interrupt by writing the proper value to the IRQ Control Register at the new BASE 1 since the above sequence disables any interrupt selection The P 51 may now be used at the new base address and will stay at that base address until either 1 a hardware reset for which the base address will become that selected by the Base Address input signals or 2 until the host software changes the base address again through the Base Address Control Register 35 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM Physical Dimensions 100 PIN QUAD FLAT PKG Gull Leads 14 0 mm 0 4 A B C D E F G J 36 O 1999 2000 benc Micro iios PRELIMINAR Y C My Documents WP51chipP51 Man Draft 05 30 00 8 51 PM PCB Layout 100 PIN SQUARE QUAD FLAT PKG PCB LAYOUT A B C D E F G H J 00 0 079 PAD 1 52x0 23 PAD 0 060x0 009 Jr 8 4J e 37 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P5
43. s way the host can break into P 51 execution at arbitrary times and gain control of the P 51 processor in a way not possible with standard 8051s and more flexibly even than most ICEs 24 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM The 8051 Ports The standard 8051 ports are reproduced in the P 51 All four ports are bi directional eight bit ports with individually SET able and CLR able pins that can be read or written as an eight bit port or can be treated as eight individual I O lines in any combination 5 in 3 out etc With the exception of P1 1 P1 2 P1 6 and the External Interrupt P3 3 discussed later all of the pins are functionally identical to the 8051 micro controller In addition P 51 ports have the special functions associated with 8051 ports that is PO serves as multiplexed address and data port and P2 provides the associated high address bits for movx instructions The Address Latch Enable ALE pin serves to latch the low address from PO and the RD and WR pins P3 6 and P3 7 read or write data to or from PO Other P3 pins provide UART functionality counter timer interface and external interrupt capability LO ADDR DATA EE RD P3 6 WR P3 7 Figure 4 The P 51 supports 8051 movx instructions Non Standard 8051 Port Usage Four 8051 Port pins are not used in their standard way by the P 51 They are P1 1 P1 2 P1 6 and
44. spect of the 8051 and the P 51 is slightly more complex The basic 8051 address spaces are relative only to the 8051 while a subset of the P 51 address spaces are also relative to the host Although each address space effectively starts at location address zero from the 8051 perspective the address as seen by the host is more complicated The complication comes from a base address register whose contents are pin selectable and software selectable that is the base address can be specified via four pins connected through jumpers to ground or VCC The high bits of the host address bus are compared to these pins If they match the P 51 is chip selected by the host and its relevant address spaces become accessible to the host Thus the P 51 can be mapped into the address space of an IBM PC class computer and can function as truly intelligent memory O 1999 2000 Cybernetic Micro Systems C My Documents P51chip P51_Man5 doc Working Draft PRELIMINARY 05 30 00 8 51 PM P 51 Address Space BASE REG BASE USER ADDR Specified DUAL PORT RAM BASE 0 0 DpRAM Space Shared BASE FFF FFF 4K CODE RAM BASE 1000 0 Code Space BASE 2FFF 1FFF 8K DATA RAM O Int Data RAM Space hs Register Bank Space lt Bit Space A Indirect Access FF IO and External Address Space movx IRQ Space Figure 3 The basic address spaces of the P 51 As shown in this figure Dual port RAM is at BASE 0 Code RAM is
45. t If multiple paths are possible multiple breakpoints can be used Breakpoint operation typically requires some level of intervention or cooperation on the part of the user The P 51 allows the user to specify what actions are to occur when a breakpoint event occurs At a minimum the host must replace the breakpoint with a NOP or must restore the original instruction that was previously overwritten by the breakpoint The P 51 must also write at least a return opcode into the Breakpoint service routine in Code RAM The P 51 can optionally write almost any breakpoint service code terminated with a return In this manner the P 51 can access resources such as data RAM contents port I O accumulator PSW timer contents or any other location or data accessible by the P 51 These resources can be copied into dual port RAM locations by the P 51 where the host can access them and the user can display them etc Finally the return code at the end of the breakpoint service is encountered and the address of the breakpoint is popped from the stack into the P 51 program counter register Remember that the PC was decremented before being pushed on the stack so the P 51 tries to execute the instruction at the breakpoint address again If the 21 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM breakpoint has been replaced by a NOP or by the original pre breakpoint opcode
46. t RAM interrupt signal to properly drive the internal ExtInt1 signal If this bit is driven to zero by P 51 software the ExtInt1 signal will always be low and will no longer indicate the interrupt request from the dual port RAM 26 O 1999 2000 Cybernetic Micro Systems C My Documents P51chip P51_Man5 doc All 8051 instructions are executed by the P 51 These are listed below Working Draft The P 51 Instruction Set ARITHMETIC OPERATIONS Mnemonic Description PRELIMINARY 05 30 00 8 51 PM U lt gt D Oscil Period ADD A Rn Add register to Accumulator 12 ADD A direct Add direct byte to Accumulator 12 ADD A ORI Add indirect RAM to Accumulator 12 ADD A data Add immediate data to Accumulator 12 ADDC A Rn Add register to Accumulator with Carry 12 ADDC A direct Add direct byte to Accumulator with Carry ADDC A Ri Add indirect RAM to Accumulator with Carry ADDC A data Add immediate data to Acc with Carry SUBB A Rn Subtract Register from Acc with borrow SUBB A direct Subtract direct byte from Acc with borrow SUBB A Ri Subtract indirect RAM from Acc with borrow N I IN INI INI IN IN SUBB A data Subtract immediate data from Acc with borrow INC A Increment Accumulator INC Rn Increment register INC direct Increment direct byte
47. tional jumps Range is 128 to 127 bytes relative to first byte of the following instruction bit Direct Addressed bit in Internal Data RAM or Special Function Register 31 O 1999 2000 Cybernetic Micro Systems PRELIMINARY C My Documents P51chip P51_Man5 doc Working Draft 05 30 00 8 51 PM The P 51 Special Function Registers Single chip micro controllers differ from microprocessors in that they possess peripheral interface components and controller oriented hardware on a chip For example the 8051 supports timers counters UARTS interrupt pins I O ports and memory on a single chip whereas most microprocessors require external UART external counter timer external interrupt support chips and external memory The first true single chip controller Intel s 8048 contained this special hardware and a set of instructions such as START Time to control the hardware The 8051 advanced the state of the art considerably by mapping all of the special purpose hardware into a special function register file which could be accessed by both bit and byte instructions This not only organized the I O nicely but by using mov instructions and clr bit and set bit instructions to control the I O hardware it eliminated the need for special instructions thereby freeing up the opcode space for more general instructions The P 51 supports all 8052 special function registers Standard P 51 Special Function Registers B_ BRegister
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