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1. SMA T 2 SMA3 SMA 4 ooh ono BLOCK DIAGRAM i Ojo gt 5 222 160 osc i SMARTMEDIA i CARD X i i PowerPC 405 Vegas PROCESSOR BLOCK 1 3 osc a i Rocket 5 gt NET D x Mm PowerPC 405 s E 8B sel udi Us JB Processor stock 2 MICTOR 281 i userctock 78 PPC JTAG us i REUS CONNECTORS EE 2 EN 4 a gt gt Rezs2X2 SRAM 32K X 8 osc UR CY62256 x XILINX VIRTEXI aconess prask ERE ut 4 PRO FPGA fe DATA 5 POWER HEADER SMARTMEDIA CONFIGURATION DCLKO PEZVEZOSOISOISO fe CONTROL Uum aw li ECLKO FF1152 i DDRCLKp i SWITCHING CONFIG ADDRESS f ppmspRAM DDR PLLip 4 REGULATOR DDR JUMPERS DATA 32Mb X 16 T CONTROL gt MT46V64M16 CLOCK SOURCE Eck ADDRESS NR i JUMPER GRID i SWITCHING jn 000901 rr PLL1 i le CONTROL gt ose 9 Ce E SWITCHING Eue 4 ADDRESS ADDRESS DDR SDRAM DDR PLL2p 425 10 MODULE DATA DATA 32MbX16 4 u25 075883 OR
2. Test Signal Name Connector Test Signal Name FPGA Pin Header 1 00 P3N46 2 20 IP8 51 IST HDRA36 U13 N32 1 052 BP3N43 P3N43 4 5 IP8 52 IST HDRA37 U13 N31 1 053 BP3N42 P8N42 47 IP8 53 IST HDRA38 013 28 1 004 BP3N39 P3N39 14 9 8 54 IST HDRA39 U13 P27 1 055 Connect P8 55 GND U13 E5 1 056 BP3N38 P3N38 4 11 P8 56 IST HDRA40 U13 N34 1 057 BP3N35 P3N35 413 IP8 57 IST HDRA41 U13 M34 1 058 BP3N34 P3N34 415 IP8 58 IST HDRA42 1013 330 1 009 BP3N29 P3N29 4 17 IP8 59 IST HDRA43 U13 N29 1 060 BP3N28 P3N28 14 19 IP8 60 IST HDRA44 U13 P26 1 000 BP3N27 P3N27 4 21 P8 61 IST HDRA45 U13 P25 1 002 _ BP3N26 P3N26 4 23 IP8 62 IST HDRA46 U13 M32 1 063 P3N23 2 21 IP8 63 IST HDRA47 U13 M31 1 064 P3N22 2 22 P8 64 TST_HDRA48 U13 L32 1 065 19 3 19 4 25 IP8 65 IST HDRA49 U13 L31 1 006 Connect 8 66 GND U13 E5 1 007 BP3N18 P3N18 4 27 IP8 67 IST HDRAS50 U13 N28 1 008 BP3N15 P3N15 14 29 IP8 68 IST HDRA51 U13 N27 1 069 BP3N14 P3N14 4 31 P8 69 TST_HDRA52 U13 M33 1 070 P3N9 2 23 8 70 IST HDRA53 U13 L33 1071 P3N8 2 24 P8 71 IST HDRA54 U13 M29 1 072 BP3N7 P3N7 4 33 P8 72 TST_HDRA55 U13 M28 1073 BP3NG6 P3N6O 4 35 IP8 73 IST HDRA56 U13 N26 1074 BP3N3 P3N2 4 37 IP8 74 IST HDRAS57 U13 N25 1075 BP3N2 P3N2 4 39 IP8 75 IST HDRAS58 U13 L34 1076 BPAN27 PAN27 441 D8 76 IST HDRAS59 U1
3. LTC1326 FPGA 2 5V XC2VP20 30 40 50 3 3V FPGA_DONE 2 2 5V Reset Circuit LTC1326 MCU e ATmega128L Push Button SPI Interface Header JTAG TRSTOUTRn FLASH 28F640B3 MCU JTAG gt gt CPLD XC95288XV FPGA_GRSTn PPC JTAG JTAG 5 PWRRST n DEBUG Note RS232 Tranceiver must be disabled RS232 during MCU programming phase in order to avoid contention on the BTXD signal pin 1013221 Figure 44 Reset Topology Block Diagram Note The Serial Programming Cable SPI when connected to P3 will assert PWRRSTn The CPLD inverts the PWRRSTn signal to PWRRST that is used to disable the transmitter in the RS232 interface U6 during programming of the Atmel MCU U3 This is done to avoid contention on the BRXD signal Depressing the reset push button 51 causes the following sequence of events 1 2 5 Reset of the CPLD and MCU Reset of FPGA through FPGA_GRSTn signal FPGA configuration is cleared If the dipswitch is set for SelectMAP configuration option and there is a valid SmartMedia catd inserted into the socket then the FPGA will be configured A SmartMedia card is valid if it complies with the SSFDC specification and contains a file named main txt in the root directory If the card is invalid or there is no card present then the FPGA will not be configured
4. 2 3 Online Documentation siisii iiie PROGRAMMING CONFIGURING THE HARDWARE sssesseseseesroresreseoeesroseseeseosesreseoresrosesroseoreseoseeroseoresroseoresesresroresreseeresroresrosroreseoseeresesreseeeeoreseseeseene 42 1 PROGRAMMING THE CPLD s n EE 42 2 PROGRAMMING THE MCU 2 47 3 CONFIGURING HYPER TERMINAL 5 rere ACER YER E TE E TDI HEY RENE EE CURE 51 4 BOARD HARDWARE 1 2 CONFIGURING THE FPGA USING 5 E E eaa 52 4 1 Bit File Generation SelectMAP Configuration ui tte tr tte RE vous EIE ERREUR NIE da Te Te aT 52 4 2 Creating Configuration File Main txt 57 4 2 1 Verbose Level 4 2 2 Sanity Check 4 2 3 Format of main txt 4 3 Starting Select MAP Configuration 4 3 1 Description of Main Menu Options ing ee Re Hate HH 61 44 PC Bit File Sanity Check 4 5 Bitstream m INTRODUCTION TO TH BOARD orearen 66 1 1 POT TL AT SIMON TI TET II MEME 66 VIRTEX ILPBO BEPGA A SPERO NEM ANTENNEN 2 1 FPGA 2VP20 Facts 5 2 2 FPGA Ba a
5. 0 FPGA configuration file sizes 1 Connection between CPLD MCU 2 FPGA JTAG connection to CPLD 3 Clocking inputs to the FPGA 4 Clock Source Signals 5 RoboClock Configuration Signals 6 Connection between FPGA and DDR PLL Clock Driver 7 Connection between FPGA and External PPC Oscillator 8 Connections between FPGA and Rocket IO Oscillators 96 ABOUT THIS MANUAL Chapter About This Manual This User Guide accompanies the DN6000K10SC LOGIC Emulation Board For specific information regarding the Virtex II Pro parts please reference the datasheet 1 Manual Contents This manual contains the following chapters Chapter 1 Getting Started contains information on the contents of the LOGIC Emulation Kit Chapter 2 Introduction to the Virtex II ISE an overview of the Vitex II platform and the software features Chapter 3 Introduction to the Software Tools information regarding test software Chapter 4 Programming Configuring the Hardware step by step information on programming and configuring the hardware Chapter 5 Board Hardware detailed description of board hardware 2 Additional Resources For additional information go to http www dinigroup com The following table lists some of the resources you can access from this website You can also directly access these resources using
6. 12V 45V PCI TDIO A Tuer BS B4 GND TMS Hag B5 Ms TD LAS 45V 0 6 I E 25 INTA A PCL _ lt PCIINTAn Be NIE INTC ag PRSNT1 am pp NID w T FESNTT RSVD VIO 1 PRSNT2 BSV PRSNT2 rsvp Hx 43 3V Keyway TPS sana PCI Bie GND RST Tate Woz eot nem Pgs PCI lt Bi7 7 PCI GNTn PCI GNT Fare lt 96 PCLREOn voz Big REQ GND Fats PMEn PCI AD31 B20 VIO PME A20 030 1 PCI AD28 031 030 57 S B22 AD29 3 3 PCI AD28 PCI AD27 823 GND AD28 423 PCI AD26 PCI AD25 B24 027 AD26 VS S Bas 025 GND 25 PCI 024 CBEn3 B26 23 3 AD24 PCI IDSEL Boe IDSEL Haso PCLIDSEL Pg6 Bog AD23 3 3 A28 PCI AD22 PCI AD21 29 GND AD22 PCI AD20 PCI ADIS 021 020 A3 v35 B31 019 GND AD18 PCI AD17 B32 3 3V 18 16 PCI CBEn2 Bas ADI ps A33 4 PCI IRDYn anD FRAME Ass Pol FRAMEN lt gt PCLFRAMEn PCLIRDYn lt gt va oY lt GND a36 PCI TRDYn PCI DEVSELn 837 TROY lt gt POLTRDYn Pgs PCI DEVSELn lt gt Bag DEVSEL GND a8 PCI STOPn 3 3V PCI LOCKn 839 PGIXCAP STOP VES PCLSTOPn PC
7. 12 INTRODUCTION TO VIRTEX H PRO AND USE 16 1 VIRTEX cuo E Y 1 1 Summary of Virtex 1I Pro Features 1 2 MR 1 3 RocketlO 3 125 Gbps Transceivers sse HEY 17 1 4 FPGA Fabric 2 FOUNDATION ISE 6 11 2 1 Foundation Features 5 2 1 1 EERE EAE EE AAE 2 1 2 2 1 3 Implementation and Configuration 2 1 4 Boat evel Inte Station Rem 3 PRO DEVELOPERS INTRODUCTION TO THE SOFTWARE TOOLS eese eee inen ansa 24 1 EXPLORING THE SOFTWARE TOOLS AR REC EPA E XA REC E XA DARE 1 1 APTES T 1 1 1 Getting Started with AETEST ES 1 1 2 M in MEMU ead at 1 1 3 I euim Pee eee 1 1 4 Memory Menu m 1 1 5 ORE ATAARE E AA OEE RE 1 1 6 Daughter Board Menu nmn ccn etr p EE RN 1 2 GNU Tools ise 2 GETTING MORE INFORMATION 2 1 Printed Documentation 2 2 ElectronicDocumentotiOnse neo
8. 269 2 Ve gt 22 v 7 24 C279 C270 C265 Our 10 Interface Peripheral Component Interconnect PCT Local Bus is a bus standard that is mainstay of many different computer systems PCI is a high performance bus with multiplexed address and data lines Defined for both 32 bit and 64 bit wide data buses PCI is intended for use as an interconnect mechanism between highly integrated peripheral controller components peripheral add in boards and processor memory systems The DN6000K10SC can be hosted in a 32 bit or 64 bit PCI PCI X slot and includes two main components e FPGA as the PCI bus Master e PCI Edge Connector Virtex II Pro parts does not tolerate 5V signaling so the DN6000K10SC must be plugged into a 3 3V PCI slot PCI X by definition is 3 3V signaling The PWB is keyed so that it is not possible to mistakenly plug the board into a 5V PCI slot Do NOT out the key in the PCI host slot and do NOT modify the DN6000K10SC to get it to fit into the slot If you need a 3 3V PCI slot the DNPCIEXT S3 Extender card can perform this function Please refer to the Dini Group website The extender also has the capability to slow the clock frequency of the PCI bus by a factor of two function that is very useful when prototyping ASIC s The 3 3V power on the PCI connector is not used Instead 3 3V is generated from the 5V supply
9. SRAMI1 A2 U13 M2 DN6000K10SC User Guide www dinigroup com 103 BOARD HARDWARE Signal Name FPGA Pin 5 1 013 18 5 1 A4 U13 L7 5 1 5 U13 L6 5 1 U13 U9 SRAM1_A7 13 U8 SRAM1_A8 15 15 SRAM1 9 13 12 5 1 A10 5 1 A11 13 N2 SRAMI1 A12 13 N3 SRAMI1 A13 13 N4 SRAMI1 A14 13 N5 SRAMI A15 13 N6 SRAMI1 A16 13 N7 5 1 A17 U13 M10 SRAMI1 A18 U13 M9 5 1 A19 U13 M7 SRAMI1 A20 U13 M6 SRAM1 ADSCN U13 T6 SRAM1_ADSPN U13 15 SRAM1_ADVN U13 T4 SRAM1_BWAN U13 T11 SRAM1_BWBN U13 U3 SRAM1_BWCN U13 U4 SRAMI BWDN U13 U5 8 7 ue uei ne SRAM1_BWEN U13 T SRAM1_CEN U13 U SRAM1_DQAO U13 N9 5 1 DQA1 U13 N10 se Ge SG ea ae ee S DN6000K10SC User Guide Www dinigroup com 104 BOARD HARDWARE Signal Name FPGA Pin SRAM1_DQA2 U13 P1 SRAM1_DQA3 13 P2 SRAM1_DQA4 13 P3 SRAM1_DQA5 13 P5 SRAM1_DQAG 13 P6 SRAM1_DQA7 13 P7 SRAM1 DQBO 13 P9 SRAM1_DQB1 13 P10 SRAM1_DQB2 13 R1 SRAM1_DQB3 13 R3 SRAM1_DQB4 13 R4 SRAM1_DQB5 13 R6 SRAM1_DQB6 13 R7 SRAM1_DQB7 13 R9 SRAM1 DQCO 13 E3 SRAM1_DQC1 13 E4 SRAM1_DQC2 13 F4 SRAM1_DQC3 13 F5 SRAM1_DQC4 13 F7 SRAM1_DQCS5 13 F8 SRAM1_DQC6 U13 H1 SRAM1_DQC7 U13 H2 SRAM1_DQD0 U13J7 SRAM1_DQD1 013 8 SRAM1_DQD2 U13 K1 SRAM1_DQD3 U13 K2 SRAM1_DQD4 U13 K4 SRAM1_DQD5 U13 K5 S
10. 100 79 AR Look 109 Locke H 19 FBKA CLKR LAE XT 88 _FBLCLKR X ree arao Ha HEFRESS 80 Feke FBT NT 580 EE FESEL FBSEL 16 3 nern PER ie nera PIER PLLIBC 70 SOA ose Fe REFA PLENT T s rg PLENT 4081 nere 4081 REFSEL REFSEL H s coro HS o Hex Sourur AA 33 4 ourpur move 30m 385 4 P3 X 3080 aT mam 3080 Fas 57 FBFO2 57 ERR z FBDSTT 56 99 ECLKAR mas FBDIST BEDS 2040 FEDISZ 89 reps pep Ean 99 505 20A bE TP10 82 rapis 20am Eg X 2080 57 5 59 5 aro E DCLKAR RI7B ABEFO sf aro 2080 85 5 EDSO zr 45 COST 3 4050 050 i050 s ECLKOR a Bisa 52 at DUIKTH Ri63 Da 521 4051 es 0154 ELT Diss 10M1 1080 5 1 2 ECLKS 44 aro 1980 98 pcikam R157 33 pa ila 1980 173 RE 21 SSS 28 aoso 2 30
11. 4QB0 4051 Matrix 4QB1 DIS4 3F0 30A0 Divide and 3QA1 Bank3 Phase 3DS1 Select 3QB0 505 2 0153 Matrix 3QB1 gt 2F0 gt Divide and 30 gt 20 1 2 251 p Phase 45 Select 2QB0 2DS Matrix 2081 DIS2 Bi 0 10 0 ES Divide and E IA E Phase Bank 1 1050 CE 7 select 1QB0 Matrix 1 1 Figure 35 RoboClock Functional Block Diagram 4 5 1 RoboClock Configuration J umpers Header JP6 JP7 and JP8 enable the user to configure the RoboClocks as required These 3 way headers and allow the signal to float MID or be pulled to GND LOW or 3 3V HIGH A brief description of each pin is given in Table 15 Table 15 RoboClock Configuration Signals DN6000K 10SC User Guide www dinigroup com 83 BOARD HARDWARE Desctiption Connector Output Phase Function Select Controls the phase function of bank 3 amp 4 CCLK of outputs refer to Table 3 in the datasheet JP6 B1 Output Phase Function Select Controls the phase function of bank 3 amp 4 CCLK of outputs refer to Table 3 in the datasheet JP6 B2 ROBOCLOCK 7H Output Divider Function Select Controls the divider function of bank 3 amp 4 CCLK of outputs Refer to Table 4 in the datasheet JP6 B3 ROBOCLOCK 74 Output Divider Function Select Controls the divider function of bank 3 amp 4 CCLK of outputs Refer to Table 4 in the
12. APPENDIX 2 11 pci rdwr rdwr is a function used in older revisions of AETEST Users of the DN6000K10SC are advised to use current functions such as write dword and bar read dword for development 2 11 1 Description pci rdwr is the primary function for reading and writing to the Base Address Registers BARs 2 11 2 Arguments The arguments for pci rdwr are shown in Table 46 They are listed in order Argument Table 46 pci rdwr Arguments Desctiption Possible Values long batnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 BAR5 5 long byte_offset Address Number of bytes to offset data 0 0 bytes in BAR s mem space long upper data The upper 32 bits of data for a 64 bit access 0 00000000 long lower data Data the lower 32 bits of a 64 bit access 0x00000000 int command PCI command MEM_READ 0x6 ot MEM_WRITE 0x7 int be Byte Enables 0x00 DWORD BYTE 0 00 int dwotdcount Number of DWORDs 10r2 int verify Verify TRUE or do not verify access FALSE 2 11 3 ReturnValues 0 0 Ox1 When pci rdwr is called with READ as its command argument the returned DWORD is placed into the variable access_memory_dword_read The declaration for access memory dword read is Extern unsigned long access memory dword r
13. BANK 1 25V BANK 25V CLK p DDR gt DDR SDRAM EE DDR 16Mx16 XILINX FPGA FP BUFFER m MI i XC2VP20 30 40 50 BANK 6 2 5V Prieveas7 DDR CLK2p DDR SDRAM me DDR On 16Mx16 BANK 4 30V 5 30 gt DDR_PLLFBp n FLASH osc clocks PLLIB 25 DOM DOW FLASH x xivo PLLIBN ps RoboClock I cra CYBo4aV gt to SSRAM uP 512K 32036 ATmega 1281 TST_HDRA_CLKIN Polak y 512K x 32 36 System 4 FPGA GCLKOUT ee ssc y 100MHz p Test ECLK3 j Header A Figure 31 Clocking Block Diagram The clocking structures for the DN6000K10SC include the following features Two user selectable socketed oscillators X4 X5 One 48 MHz oscillator X1 e Two RoboclockII CY7B994V Multi Phase PLL Clock Buffers DN6000K10SC User Guide www dinigroup com 78 BOARD HARDWARE The clock source selection grid formed by JP5 distributes clock signals to two Roboclock PLL clock buffers U21 U22 The clock outputs from the buffers are dispersed throughout the board Two 3 3 V half can oscillator sockets X4 X5 and the signal CPDL_CLKOUT from the CPLD provide on board
14. Daughter Card Connections DN6000K10SC IO Connections Test Signal Name Connector Test Signal Name FPGA Pin Header Header 1001 Connect P8 1 12V No Pin 1 002 Connect P8 2 GND U13 E5 1 000 5 1 IP8 3 2 5V U13 B32 1 004 Connect P8 4 T5V No Pin 1 005 BCLK1 J5 3 P8 5 2 5V U13 B32 1 006 Connect P8 6 5V No Pin 1 007 CCLK1 5 5 IP8 7 CCLKI No Pin 1 008 Connect P8 8 GND U13 E5 1 000 Connect P8 9 3 3V No Pin 1010 BP2N3 P2N3 J3 1 P8 10 ECLK3 No Pin 1 011 Connect P8 11 GND U13 E5 1012 BP2N2 P2N2 3 3 IP8 12 TST_HDRAO 13 22 1 013 2 1 2 8 IP8 13 IST HDRA1 013 031 1 04 2 0 2 9 P8 14 IST HDRA2 1013 028 1015 BP2NX7 P2NX7 J3 5 IP8 15 IST HDRA3 13 27 1 06 BP2NX6 P2NXO 3 7 P8 16 IST HDRA4 U13 V33 1 07 BP2NX5 P2NX5 3 9 P8 17 IST HDRA5 013 033 1018 BP2NX4 PZNX4 J3 11 8 18 IST 6 013 030 1 019 P2NX1 2 10 IP8 19 IST HDRA7 1013 029 1 020 P2NXO 2 11 IP8 20 TST_HDRA8 1013 026 1 021 P3NX9 2 40 IP8 21 TST_HDRA9 1713 025 1 022 Connect 8 22 GND U13 E5 1 003 P3NX8 J2 41 IP8 23 IST HDRA10 013 132 DN6000K10SC User Guide www dinigroup com 144 BOARD HARDWARE Daughter Card Connections DN6000K10SC IO Connections Test Signal Name Connector Test Signal Name FPGA Pin Header 1 004 BP3NX5 P3NX5 J3 13 P8 24 TST_HDRA11 U13 131 1 025 BP3NX4 P3NX4
15. and Infiniband compliant transceivers 8 16 or 32 bit selectable internal FPGA interface 10B encoder and decoder e 50 75 on chip selectable transmit and receive terminations e Programmable comma detection e Channel bonding support two to sixteen channels Rate matching via insertion deletion characters e Four levels of selectable pre emphasis Five levels of output differential voltage Per channel internal loopback modes 2 5V transceiver supply voltage 1 4 Virtex4l FPGA Fabric Description of the Virtex II Family fabric follows SeleccRAM memory hierarchy o Up to 10 Mb of True Dual Port RAM in 18 Kb block SeleccRAM resoutces o Upto 1 7 Mb of distributed SelectRAM resources o High performance interfaces to external memory e Arithmetic functions o Dedicated 18 bit x 18 bit multiplier blocks o Fast look ahead carry logic chains e Flexible logic resources Up to 111 232 internal registers latches with Clock Enable o Up to 111 232 look up tables LUTs or cascadable variable 1 to 16 bits shift registers o Wide multiplexers and wide input function support o Horizontal cascade chain and Sum of Products support Internal 3 state busing DN6000K10SC User Guide www dinigroup com 18 INTRODUCTION TO VIRTEX II AAND ISE e High performance clock management circuitry o Up to eight Digital Clock Manager DCM modules Precise clock de skew Flexible frequency synthesis Hig
16. 3 Unload the driver type sh dndev unload 4 After the driver is loaded run the utility aetest_linux DN6000K10SC User Guide www dinigroup com 156 APPENDIX 5 The usert may need to run chmod on aetest linux to make it executable y type chmod aetest linux NOTE All text files including scripts are DOS text format with an extra carriage return character after every new line they must be converted 1 6 Solaris The utility and driver are tested on Solaris 7 0 Sparc with the 32 bit kernel Follow the procedures listed below for installation 1 Login as root to install and run AETEST 2 Go to the driver directory make sure the driver file dndev is in the sparc sub directory 3 install the driver run sh dndev install sh 4 To uninstall the driver run sh dndev_uninstall sh 5 Run aetest_solaris 6 The user may need to run chmod on aetest_solaris to make it executable y type chmod u x aetest solaris The driver is compiled with the gcc compiler aetest solaris is compiled with gmake You can download it from the GNU website The make from the Solaris installation does not work with our makefile format NOTE All text files including scripts are DOS text format with an extra carriage return character after every new line they must be converted DN6000K 10SC User Guide ww w dinigroup com 157 APPENDIX 2 Appendix AETEST Basic C424 Functions
17. NOTE To re compile the driver file PCICFG VXD the user must download the VtoolsD compiler from http www numega com 1 3 Windows 2000 XP The precompiled executable aetest wdm exe and its source code included in the DN6000K10SC CD ROM The driver file DnDev sys and its corresponding inf file are also included in the CD ROM Follow the procedures listed below for installation 1 9 If the old version of AETEST s NT dtiver is installed on the machine it must be uninstalled Start the PC with the DN6000K10SC plugged Windows should recognize the board and ask for a driver Note that the board must be configured with a valid bitfile Our reference design will work When the Found New Hardware Wizard box pops up click Next Select Display a list of the known drivers for this device so that I can choose a specific driver Select Other device Select Have Disk Go to the directory where Dndev inf is located Source Code PCI_Software wdmdtv drv and select it Locate the driver file DnDev sys under the directory Source Code PCI_Software wdmdrv objchk i386 Click on one of the devices and select Next 10 Run aetest wdm exe DN6000K10SC User Guide ww w dinigroup com 155 APPENDIX NOTE To compile aetest wdm exe the user must use Visual C 6 0 setupapi lib in version 5 0 does not contain all of the necessary functions 1 4 Windows NT Precompiled
18. The Main Menu will appear in the Terminal Window Note The identical sequence of events occurs at power up DN6000K10SC User Guide www dinigroup com 95 BOARD HARDWARE 5 2 PPC Reset The DN6000K10SC also contains another RESET push button S3 used to reset the PPC This signal is pulled up on the DN6000K10SC The user is responsible for debouncing the reset signal in the FPGA Table 20 shows the connection between the reset push button and the FPGA PPC Reset Switch 42 5V R140 R137 RESETn 10K Table 20 PPC Reset Signal Name FPGA Pin Push Button Switch PPC RESETn U13 L16 53 4 6 Memory The DN6000K10SC provides three different memory technologies to the user FLASH Synchronous SRAM and DDR SDRAM in various densities 6 1 FLASH The FLASH U11 memory component on the DN6000K10SC can accommodate up to 4M x 16 devices refer to Figure 45 In addition to programming the FPGA and storing bitstreams the FLASH may be used for non volatile storage FLASHI 4Mb x 16 Bank 1 Pg4 FLASH ADDR O 21 CERRADO E 15 S FLASH DATA o 15 Pg4 2 FLASH1 ADDRO FLASH1 DATAO LASHT ADDR LASAT DATA 4 FLASH CEn Pg4 FLASH OEn Pg4 FLASH1_WEn gt Intel Boot Block Flash 28F640B3 Pg3 8 FPGA DONE 4 FLASH1_WPn RP GND WP 48 28F640B3 TSOP48 Figure 45 FLASH Connection DN6000K10SC User Guide ww w dinigroup com 96 BOARD HAR
19. 10 1 Connection to the FPGA The FPGA connections to the PCI bus consist of 91 signals spread across two banks Bank 4 and Bank 5 A description of these signals can be found are in the following sections DN6000K10SC User Guide Www dinigroup com 124 BOARD HARDWARE Note The PCI interface is not 5V tolerant Do not modify the PCI edge connector to fit in the host PC 10 1 1 PCI VCCO on the FPGA A Linear Technology LTC1763 regulator refer to Figure 59 is used to ensure electrical compatibility to PCI and to protect the Virtex II Pro from over voltage conditions It is used for the VCCO of the banks connected to the PCI interface For more information see XAPP653 Virtex II Pro PCI Reference Design at http www xilinx com xa xapp653 pdf 0 1uF 10V ls TANT n OV C14 LI 22uF C168 16V 0 1uF R78 20 26 1 TANT 3 0V R77 38 3 Figure 59 VirtexII Pro PCI VCCO Regulator 10 1 2 PCI Edge Connector Figure 60 shows P2 the PCI 3 3V 64 bit edge connector used to interface with the host PC DN6000K10SC User Guide www dinigroup com 125 BOARD HARDWARE
20. The AETEST utility program is built on a core of basic C functions These functions perform a variety of PCI accesses e g configuration reads writes memory read wtites and test functions e g memory tests This appendix will describe a handful of these functions 2 1 bar write byte bar write byte is a high level function C function which is recommended for development by users of the DN6000K10SC 2 1 1 Description bar write byte allows users of the DN6000K10SC to write a byte of data to any location in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 1 2 Arguments The arguments for bar write byte are shown in Table 36 They are listed in order Table 36 write byte Arguments Argument Desctiption Possible Values unsigned long barnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 or BAR5 5 unsigned long byte offset Address Number of bytes to bytes in BAR s mem space offset data byte data A byte of data for the write 0x00 Oxff operation 8 bits typedef unsigned char byte 2 1 3 Return Values A successful function call will return zeto 2 1 4 Notes The source code for bar write byte is portable to each of the operating systems intended for AETEST usage DN6000K 10SC User Guide ww w dinigroup com 158 APPENDIX 2 2 bar write word write word is a high level fun
21. 0x1607 standard configuration with Opencore 0x1608 2vp20 with Opencore The VENDOR_ID is 0x17DF CA WINNT System32 cmd exe aetest_wdm exe x icrosoft Windows 2888 Version 5 00 21951 lt C gt Copyright 1985 2000 Microsoft Corp 1 gt aetest wdm TNaetest wdm aetest wdm exe ymbolic link is pcifftven_17df amp dev_1605 amp subs ys_9 ab56 78 amp rev_47 381435f ed58083 78H f 8bida27 6ac7 4d1f 9e bB 1daf ib7e7131 gt ound device vi7df 41605 name DN68BB88K18SC UirtexII Pro Single FPGA board ompiled on Jan 28 2004 at 11 05 29 ress any key 4 Follow the on screen instructions until the Main Menu is displayed DN6000K 10SC User Guide ww w dinigroup com 13 ABOUT THIS MANUAL WINNT System32 cmd exe aetest_wdm exe ASIC Emulator PCI Controller Driver v5 Compiled on Jan 20 2004 at 11 05 27 P PCI Menu M Memory Menu gt Read FPGA revision 3 Flash Menu 52 Daughter Board Menu 02 Quit DDRESS 6000000 00000 Please select option 5 From the Main Menu choose Memory Menu The memory menu will now appear 5 C WINNT System32 cmd exe aetest_wdm exe ASIC Emulator PCI Controller Driver v5 Compiled on Jan 20 2004 at 11 05 27 Write Dword Same Address gt 22 Read Dword Same Address Write Read Dword Same Address BAR Memory Fill BAR Memory Write BAR Memory Display bar memory range test bar memory address data bitw
22. 3 2 Online Document The following conventions are used in this document Convention Meaning or Use Example DN6000K 10SC User Guide ww w dinigroup com 3 ABOUT THIS MANUAL Blue Text Cross refetence link to a See the section Additional location in the current file or in Resources for details another file in the current Refer to Title Formats in document Chapter 1 for details Red Text Cross reference link to a See Figure 2 5 in the location in another document Virtex IT Handbook Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest datasheets 4 Relevant Information Information about PCI can be obtained from the following sources Reference the PCI Special Interest Group for the latest in PCI PCI X Specifications PCI Special Interest Group http www pcisig com 2575 NE Kathryn St 17 Hillsboro OR 97124 FAX 503 693 8344 Other recommended specifications include PCI Industrial Computer Manufacturers Group PICMG http picmg org 401 Edgewater Place Suite 500 Wakefield MA 01880 USA TEL 781 224 1100 FAX 781 224 1239 Suggested reference books available from Amazon Tom Shanley Don Anderson PCI System Architecture e Edition Inc Mindshare Tom Shanley Karen Gettman PCI X System Architecture With CD Edition Inc Mindshare Samir Palnitkar 1 22 00 HDL A Guide fo Digital Design and Synthesis ISBN
23. 8 177 IST HDRA139 013 02 1 178 P4N24 7 3 8 178 5 140 U13 V2 1 179 P4N23 17 5 8 179 IST HDRA141 U13 V5 1180 P4N22 7 7 P8 180 IST HDRA142 U13 W2 1 181 P4N17 7 9 8 181 HDRA143 U13 V9 1 482 P4N16 7 11 IP8 182 IST HDRA144 U13 V10 1 193 P4N15 7 13 8 183 TST HDRA145 U13 V11 1 184 GND J2 36 IP8 184 GND U13 E5 DN6000K 10SC User Guide www dinigroup com 150 BOARD HARDWARE Daughter Card Connections DN6000K10SC IO Connections Test Signal Name Connector Test Signal Name FPGA Pin Header 1 185 PAN14 7 15 28 185 TST HDRA146 U13 Y3 1 186 P4N9 7 17 28 186 IST HDRA147 U13 W9 1 187 P4N8 7 19 P8 187 HDRA148 U13 AB1 1 188 P4N5 pau P8 188 IST HDRA149 U13 AC2 1 189 P4N4 7 23 28 189 TST HDRA150 U13 AD3 1 190 PAN1 7 25 28 190 IST HDRA151 U13 AG1 1 191 PANO 7 27 28 191 TST HDRA152 U13 AK3 1 192 P4N X13 7 29 Connect 1 193 PANX12 7 31 Connect 1 194 P4NX9 7 33 Connect 1 195 INo Connect 28 195 GND U13 E5 1 196 P4NX8 7 35 Connect 1 197 PANX3 7 37 Connect 1 198 PANX2 7 39 Connect 1 199 PANX1 7 41 Connect 1 200 PANXO 7 43 Connect 13 Mechanical Two bus bars MP2 and MP3 are installed to prevent flexing of the PWB They are connected to the ground plane and can be used to ground test equipment Be careful not to short any power rails or signals to these
24. 85 BOARD HARDWARE Desctiption Connector ROBOCLOCK 1 Output Mode This pin determines the clock outputs disable state When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD OFF mode When in MID the device will enter factory test mode JP8 B3 ROBOCLOCK 2 Output Mode This pin determines the clock outputs disable state When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD OFF mode When in MID the device will enter factory test mode FBDIS1 ROBOCLOCK 1 Feedback Disable This input controls the state of QFA 0 1 When HIGH the QFA 0 1 is disabled to the HOLD OFP or HI Z state the disable state is determined by OUTPUT MODE When LOW the QFA 0 1 is enabled Refer to Table 5 in the datasheet This input has an internal pull down FBDIS2 ROBOCLOCK 1 Feedback Disable This input controls the state of QFA 0 1 When HIGH the QFA 0 1 is disabled to the HOLD OFF or HI Z state the disable state is determined by OUTPUT MODE When LOW the QFA 0 1 is enabled Refer to Table 5 in the datasheet This input has an internal pull down ROBOCLOCK 2 Output Phase Function Select Controls the phase function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 3 in the datasheet ROBOCL
25. Auto detect 960081 SCROLL 5 NUM Capture Print echo Figure 23 Interactive Configuration Option Menu DN6000K 10SC User Guide ww w dinigroup com 62 PROGRAMMING CONFIGURING THE HARDWARE Table 7 desctibes the Interactive Configuration Menu options Table 7 HyperTerminal Interactive Configuration Menu Options Function Description Select a bit file to The user is able to select a bit file from a list of bit files found on configure FPGA s the SmartMedia card for configuring the FPGA Set verbose level The user can change the verbose level from the current setting current level 2 NOTE If the user goes back to the main menu and configures the FPGA s using main txt the verbose level will be set to whatever setting is specified in main txt Disable Enable The user can disable or enable the sanity check depending on what sanity check for bit the current setting is files NOTE If the user goes back to the main menu and configures the FPGA s using main txt the sanity check will be set to whatever setting is specified in main txt Main menu Returns the user to the Main Menu 4 4 PCBitFile Sanity Check A version of the sanity check has been compiled for use on a PC the executable is sanityCheck exe which can be found on the CD shipped with the DN6000K10SC This allows you to run the sanity check on bit files before copying them onto the Smart Media card This PC bit file sanity
26. Generate Programming File process and select Run The bit file will be generated and may be found in the project directory 4 2 Creating Configuration File main txt To control which bit file on the Smart Media card is used to configure the FPGA in SelectMAP mode a file named main txt must be created and copied to the root directory of the Smart Media card The configuration process cannot be performed without this file Below is a description of the options that can be set in the file a description of the format this file needs to follow and an example of a main txt file 4 2 1 Verbose Level During the configuration process there are three different verbose levels that can be selected for the serial port messages e Level 0 Fatal error messages Bit file errors e g bit file was created for the wrong part bit file was created with wrong version of Xilinx tools or bitgen options are set incorrectly Initializing message will appear before configuration single message will appear once the FPGA is configured level All messages that Level 0 displays Displays configuration type should be DN6000K 10SC User Guide ww w dinigroup com 57 PROGRAMMING CONFIGURING THE HARDWARE Displays current FPGA being configured if the configuration type is set to SeleccMAP Displays a message at the completion of configuration for each FPGA configured e Level 2 All m
27. P2 A64 13 AD18 PCI CLK P2 B16 PCI DEVSELN 2 37 13 AM13 PCI FRAMEN P2 A34 13 AG14 PCI GNTN P2 A17 U U U U13 AK17 U U U 13 AG10 PCI IDSEL 2 26 U13 AF13 PCI_INTAN P2 A6 U13 AD16 PCI IRDYN P2 B35 LUIS ALIS PCI LOCKN 22 839 U13 AJ14 PCI PAR P2 A43 U13 AF15 PCI PAR64 P2 A67 U13 AF19 PCI_PERRN P2 B40 U13 AK14 PCI_REQ64N P2 A60 U13 AE18 PCI ACK64N P2 B60 U13 AJ19 PCI REQN P2 B18 U13 AL7 PCI RSTN P2 A15 U13 AF10 PCI SERRN P2 B42 U13 AL14 PCI STOPN DN6000K10SC User Guide P2 A38 Www dinigroup com U13 AE15 129 BOARD HARDWARE Signal Name Connector FPGA Pin PCI TRDYN P2 A36 U13 AH14 10 2 PCI PCI X Hardware Setup The following section describes the PCI PCI X hardware setup More information is available from the PCI PCI X Specifications available PCI SIG http www pcisig com home 10 2 1 Present Signals The Present signals jumper block JP1 indicate to the system board whether an add in catd is physically present in the slot and if one is present the total power requirements of the add in card refer to Table 31 Table 31 Present Signal Definition PRSNT1 PRSNT2 Add in Card Configuration Add in card present 25 W maximum Add in card present 15 W maximum Add in card present 7 5 W max
28. PCI ADO P2 A58 U13 AF18 PCI_AD1 P2 B58 U13 AK19 DN6000K10SC User Guide www dinigroup com 126 BOARD HARDWARE Signal Name Connector FPGA Pin PCI AD2 p2 A57 U13 AG18 PCI AD3 P2 B56 U13 AL19 PCI_AD4 P2 A55 U13 AG17 PCI AD5 P2 B55 U13 AL16 PCI AD6 P2 A54 U13 AP17 PCI AD7 P2 B53 U13 AK16 PCI_AD8 P2 B52 U13 AJ16 PCI AD9 P2 A49 U13 AD17 PCI AD10 P2 B48 L3 ALAS PCI AD11 P2 A47 U13 AG16 PCI AD12 P2 B47 U13 AJ15 PCI AD13 P2 A46 U13 AF16 PCI AD14 P2 B45 U13 AH15 PCI AD15 P2 A44 U13 AE16 PCI_AD16 P2132 U13 AF14 PCI AD17 2 32 U13 AJ13 PCI_AD18 P2 A31 U13 AE14 PCI_AD19 P2 B30 U13 AL12 PCI_AD20 P2 A29 U13 AH13 PCI_AD21 P2 B29 U13 AM11 PCI_AD22 2 26 U13 AG13 PCI AD23 2 27 U13 ALT1 PCI AD24 P2 A25 U13 AE13 PCI_AD25 P2 B24 U13 A 11 PCI AD26 2 23 U13 AF11 PCI AD27 2 23 U13 AL8 PCI AD28 2 22 U13 AE11 PCI_AD29 P2 B21 U13 AK8 PCI AD30 DN6000K 10SC User Guide P2 A20 www dinigroup com U13 AH10 BOARD HARDWARE Signal Name Connector FPGA Pin PCI AD31 P2 B20 U13 AM7 PCI_AD32 P2 A91 U13 AF25 PCI_AD33 P2 B90 U13 AK27 PCI_AD34 P2 A
29. datasheet ROBOCLOCK 2 Frequency Select This input must be set according to the nominal frequency Refer to Table 1 in the datasheet ROBOCLOCK 2 Feedback Output Phase Function Select This input determines the phase function of the Feedback Bank s 0 1 outputs Refer to Table 3 in the datasheet FBDS02 ROBOCLOCK 2 Feedback Divider Function select These inputs determine the function of the QFAO QFA1 outputs Refer to Table 4 in the datasheet FBDS12 ROBOCLOCK 2 Feedback Divider Function Select These inputs determine the function of the QFAO and QFA1 outputs Refer to Table 4 in the datasheet OSCA Enable for Oscillator A X4 JP8 B9 OSCB Enable for Oscillator B X5 JP8 B10 REFSEL1 ROBOCLOCK 1 Reference Select Input The REFSEL input controls how the reference input is configured When LOW it will use the REFA pair PLL1A as the reference input When HIGH it will use the REFB pair PLL1BC PLLIBNO as the reference input This input has an internal pull down JP8 B1 REFSEL2 ROBOCLOCK 2 Reference Select Input The REFSEL input controls how the reference input is configured When LOW it will use the REFA pair DCLK3 or CLKOUT as the reference input When HIGH it will use the REFB pair PLL2BC or PLL2BNC as the reference input This input has an internal pull down DN6000K 10SC User Guide www dinigroup com
30. so an external 32K x 8 SRAM U1 was added The micro controller is programmed in system via the serial programming interface SPI The micro controller has the following responsibilities e Reading the SmartMedia card e Configuring the Virtex II Pro FPGA e Executing DN6000K10SC self tests DN6000K10SC User Guide www dinigroup com 69 BOARD HARDWARE Other than FPGA configuration the micro controller has no other function Less than half of the 128KB of FLASH is used for FPGA configuration and utilities so the user is welcome to utilize the rest of the resources of the micro controller for their own applications Instructions for customizing the micro controller are contained in the file Atmegal128L datasheet please reference CD ROM or contact Atmel 3 1 1 MCU Programming Connector programming cable for the ATmega128L is shipped with the DN6000K10SC mates to the MCU programming header P3 as shown in Figure 26 The programming header is used to download the files to the MCU using the AVR In System Programming Cable PWRRSTn MCU_TXD Figure 26 MCU Programming Connector 3 1 2 RS232 Interface An RS232 serial port P4 is provided for low speed communication with the MCU The RS 232 standatd specifies output voltage levels between 5 to 15 Volts for logical 1 and 5 to 15 Volts for logical 0 Input must be compatible with voltages in the range of 3V to 15V for logical 1 and 3V to 15V for logical 0 This e
31. va 2 10 veg C322 0 001uF 3 E 3 2 5 a TANT TANT TANT TANT vrT 125V o VTT 1 25V PGND1 PGND2 VREF OUT TANT 14 17 DEINE DDR VREF Pg7 13 1 colon gt 1 AGND R139 100K DGND PKG GND R138 ML6554 PSOP16 1K Figure 56 DDR VTT Termination Regulator 6 3 6 DDR SDRAM Connection to the FPGA The DDR SDRAM memory components are connected to the FPGA on Bank 6 and Bank 7 As mentioned the connections between the FPGA and the DDR SDRAM are not homogeneous as control and address are handled differently from the data and differently from the clocks However all of these signals are controlled impedance and are SSTL2 terminated The termination of these signals is covered in DDR SDRAM Termination The Data signals DQ the Data Strobe DQS and the Data Mask DM signals are point to point signals going from the FPGA to the DDR SDRAM components As mentioned above these signals are controlled impedance and terminated according to the DDR SDRAM specification This termination is covered below in DDR SDRAM Termination The connection of the Data the Data Strobe and the Data Mask signals between the FPGA and the DDR SDRAM components in covered in Table 23 The data data strobe and data mask signals all serve different purposes The data signals are self evident carrying the raw data between the chi
32. will further enhance the turnaround time Xilinx ISE provides the seamless integration with the leading synthesis engines from Mentor Graphics Synopsys and Synplicity You can use the synthesis engine of your choice In addition ISE includes Xilinx proptietary synthesis technology XST You have options to use multiple synthesis engines to obtain the best optimized result of your programmable logic design 2 1 3 Implementation and Configuration Programmable logic design implementation assigns the logic created during design entry and synthesis into specific physical resources of the target device The term place and route has historically been used to describe the implementation process for FPGA devices and fitting that has been used for CPLDs Implementation is followed by device configuration where a bitstream is generated from the physical place and route information and downloaded into the target programmable logic device To ensure designers get their product to market quickly Xilinx ISE software provides several key technologies required for design implementation e Ultra fast runtimes enable multiple turns per day ProActive Timing Closure drives high performance results Timing driven place and route combined with push button ease e Incremental Design DN6000K10SC User Guide www dinigroup com 21 INTRODUCTION TO VIRTEX II AAND ISE e Macro Builder 2 1 4 Board Level Integration Xili
33. 6B DATAT7 13 AF31 18 13 DDR_6B_DATA8 13 AE28 18 54 DDR_6B_DATA9 13 AE27 18 56 DDR_6B_DATA10 13 AF30 18 57 DDR 6B DATA11 13 29 18 59 DDR 6B DATA12 U13 AH32 18 60 DDR 6B DATA13 U13 AH31 18 62 DDR_6B_DATA14 U13 A 34 18 63 DDR 6B DATA15 U13 AJ33 18 65 DDR_FPGA_6B_UDQS 13 26 18 51 DDR FPGA 6B 1005 13 AD28 18 16 DDR FPGA 6B UDM 13 AG31 18 47 DDR FPGA 6B LDM 13 AG33 18 20 DDR FPGA 6B BAO 13 AH34 18 26 DDR FPGA 6B BA1 13 AH33 18 27 DDR FPGA 6B CASN 13 AD30 18 22 DDR FPGA 6B CKE 13 AD31 18 44 DDR FPGA 6B CSN U13 AB25 18 24 DDR FPGA 6B RASN U13 AD29 18 23 DDR FPGA 6B WEN U13 AB26 18 21 U U U U U U U U U U U U U U U U U U ct c be pem em Se GS UG EGG p m eL edu 7 RocketlO Transceivers RocketIO transceivers an exciting new feature of the Virtex II Pro family These multigigabit transceivers can transmit data at speeds from 622 Mb s up to 3 125 Gb s determined be the speed grade of the part please refer to the Xilinx DN6000K10SC User Guide Www dinigroup com 115 BOARD HARDWARE datasheet The DN6000k10SC cannot support the series FPGAs Xilinx does not make an series part in 1152 BGA package MGTs are capable of various high speed serial standards such as Gigabit Ethernet FiberChannel InfiniBand and XAUI In addition the channel bonding feature aggregates multi
34. A0 A15 46 UNBUFFERED V0 0 25 N 50 PIN MINI D RIBBON CABLE p CONNECTOR J7 UNBUFFERED l O 0 23 LINEAR REGULATOR 12VDC TO 3 3V 8 9VDC A POWER INDICATORS A N C3 CC BUFFEREDIO 0 15 Ut UNBUFFERED 1 0 0 15 WAVE V y 3 3V 5 0V 12 0V J3 BUFFERED 1 0 0 7 N 0 POWER u2 UNBUFFERED 100 15 BUFFERED 1 0 0 7 41 5V I 3 3V J4 5 0V gt 12 0 6 BUFFERED I O 0 15 U3 UNBUFFERED I O 0 15 12 0V N GND 20 PIN IDC 741 16245 200 PIN MICROPAX HEADER 74 5 163245 BOTTOM OF PWB U1 U2 U3 BUFFERS OR LEVEL TRANSLATORS Figure 66 DN3000K10SD Daughter Card Block Diagram The DN3000K10SD Daughter Card provides 16 differential pairs 48 buffered passive active I O and 66 unbuffered I O signals The DN3000K10SD Daughter Card is pictured in Figure 67 DN6000K10SC User Guide Www dinigroup com 139 Lab m ze i nta Figure 67 DN3000K10S Daughter Card U3 ate used as bus switches in the passive mode U2 gt 140 www dinigroup com BOARD HARDWARE 7 NOK P N DN3KIODT REV Figure 68 show the assembly drawing of the DN3000K10SD Daughter Card IDT74FST163245 devices U1 and the IDT74LVC16245A U1 U2 U3 devices ate used as bus transceivers in the DN6000K10SC User Guide BOARD HAR
35. ADDRESS 5 0x24 PCI CS EXPANSION ROM x30 PCI CS INTERRUPT LINE Ox3c PCI CS INTERRUPT PIN x3d PCI CS MIN Ox3e PCI_CS_MAX_LAT Ox3f Input config offset hex 0x00 Oxff wotd to write in hex Loop indefinitely y or Iflooping was selected pressing any key will stop the loop 7 Read Config DWORD Allows the user to read from configuration space This function has the option to single read loop read with display and loop read without display 8 Display Config registers Reads and displays the entire set of configuration registers 0 0 OxFC for device 0x00 OxFC for the active device and function function 1 0 number Use options S and F to change the active device and function numbers respectively DN6000K 10SC User Guide ww w dinigroup com 30 INTRODUCTION TO THE SOFTWARE TOOLS Description Reloads the PCI configuration of the active device from a file It writes to the command register and writes the 6 BARs with the values from the file This function is useful for hot swapping devices power switch still required on extender or reinitializing a device when its configuration has been altered WARNING Since the PCI BIOS is not assigning the BARs for this device a memory conflict may be induced by using this option This option is for advanced user only Option Function Name C Configure BARs from a file V Save BAR configuration to a
36. Controller Driver v5 Compiled on Jan 20 2804 at 11 05 27 PCI Menu Memory Menu Read FPGA revision Flash Menu Daughter Board Menu Quit PCI BASE ADDRESS 4 1 6000000 2 68880000 4 98000000 5 1 Please select option Figure 5 Main Menu The possible Main Menu options and a description can be found in Table 2 DN6000K 10SC User Guide www dinigroup com 27 INTRODUCTION TO THE SOFTWARE TOOLS Table 2 Main Menu Options Function Name Description Read FPGA F Revision Displays the revision of the reference design in FPGA F PCI Menu Takes User to PCI Menu Memory Menu Takes User to Memory Menu Daughter Board Menu Take User to Daughter Board Menu 1 1 3 PCI Menu Upon entering the PCI Menu from the Main Menu AETEST will output a screen similar to the one shown in Figure 6 S C WINNT System32 cmd exe aetest_wdm exe ASIC Emulator PCI Controller Driver v4 1 gt Display Vendor and Device ID M gt Main Menu 9 gt Quit PCI BASE ADDRESS bbaie888 1 b3ale 2 98800000 66660000 4 99990000 5 8888008088 Please select option m Figure 6 PCI Menu The possible PCI Menu options and a description can be found in Table 3 Table 3 PCI Menu Options Option Function Name Desctiption S Set PCI Device Number Sets a PCI device number of your choice as the active device hex input Available device numbers is
37. JP3 3 PPC_JTAG_TRSTN U12 79 JP3 4 PPC_JTAG_TCK 0113 119 JP3 7 PPC_JTAG_TMS U13 K19 3 9 PPC DBG HALTN U13 F20 JP3 11 8 1 3 CPU Trace The CPU Trace port accesses the real time trace debug capabilities built into the PowerPC 405 CPU core Real time trace debug mode supports real time tracing of the instruction stream executed by the processor In this mode debug events are used to cause external trigger events An external trace tool uses the trigger events to control the collection of trace information The broadcast of trace information occurs independently of external trigger events trace information is always supplied by the processor Real time trace debug does not affect processor performance Real time trace debug mode is always enabled However the trigger events occur only when both internal debug mode and external debug mode are disabled Most trigger events are blocked when either of those two debug modes is enabled Information on the trace debug capabilities how trace debug works and how to connect an external trace tool is available in the RISCWatch Debugger User s Guide 8 1 4 CPU Trace Connector Agilent Windriver has defined a Trace Port Analyzer TPA port for the PowerPC 4xx line of CPU cores that combines the CPU Trace and the CPU Debug interfaces onto a single 38 pin Mictor connector This provides for high speed controlled impedance signaling DN6000K10SC User Guide www dinigroup
38. Name JP7 A10 B10 OSCB Enable for Oscillator B X5 JP8 A1 B1 REFSEL1 ROBOCLOCK 1 Reference Select Input The REFSEL input controls how the reference input is configured When LOW it will use the REFA pair PLL1A as the reference input When HIGH it will use the REFB pair PLL1BC PLL1BNO as the reference input This input has an internal pull down REFSEL2 ROBOCLOCK Z2 Reference Select Input The REFSEL input controls how the reference input is configured When LOW it will use the REFA pair DCLK3 or FPGA_CLKOUT as the reference input When HIGH it will use the REFB pair PLL2BC or PLL2BNC as the reference input This input has an internal pull down JP8 A3 B3 ROBOCLOCK 1 Output Mode This pin determines the clock outputs disable state When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD OFF mode When in MID the device will enter factory test mode ROBOCLOCK 2 Output Mode This pin determines the clock outputs disable state When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD OFF mode When in MID the device will enter factory test mode JP8 A9 B9 ROBOCLOCK 2 Output Divider Function Select Controls the divider function of bank 1 2 3 amp 4 of outputs Refer to Table 4 in the datasheet J
39. PRO AAND ISE o Up to two IBM PowerPC RISC processor blocks Based on Virtex IT FPGA technology o Flexible logic resources up to 125 136 Logic Cells o SRAM based in system configuration O Active Interconnect technology SelectRAM memory hierarchy Up to 556 Dedicated 18 bit x 18 bit multiplier blocks o High performance clock management circuitry SelectIOTM Ultra technology o Digitally Controlled Impedance I O 1 2 PowerPC 405 Core Embedded 300 MHz Harvard architecture core Low power consumption 0 9 mW MHz Five stage data path pipeline Hardware multiply divide unit Thirty two 32 bit general purpose registers 16 KB two way set associative instruction cache 16 KB two way set associative data cache Memory Management Unit MMU 64entry unified Translation Look aside Buffers TLB o Variable page sizes 1 KB to 16 MB Dedicated on chip memory OCM interface Supports IBM CoreConnect bus architecture Debug and trace support Timer facilities 1 3 RocketlO 3 125 Gbps Transceivers Full duplex serial transceiver SERDES capable of baud rates from 622 Mb s to 3 125 Gb s please reference the Xilinx datasheet for speed grade limitations 80 Gb s duplex data rate 16 channels DN6000K10SC User Guide www dinigroup com 17 INTRODUCTION TO VIRTEX II PRO AAND ISE Monolithic clock synthesis and clock recovery CDR e Fibre Channel Gigabit Ethernet 10 Gb Attachment Unit Interface
40. SSRAM using two activation signals ADSC and ADSP an activation with ADSP requires data and byte enables one clock cycle after the address and activation Syncburst Pipelined Figure 48 is identical except for registered outputs which delay read data an additional clock cycle but may be necessary for high speed designs 18 2 Burst B Control 1 0 Memory Block Address Register Read Control Logic Figure 47 SSRAM Flow trough DN6000K10SC User Guide www dinigroup com 100 BOARD HARDWARE 18 2 EN Burst H Control Address Read Control Logic Figure 48 SSRAM Pipeline Zero Bus Turnaround ZBT SSRAM s are designed to eliminate wait states between reads and writes by synchronizing data Figure 49 accept and return data one clock cycle after the address phase and ZBT Pipeline SSRAMs Figure 50 accept and return data two clock cycles after the address phase This allows the user to begin a write burst immediately after the last word of a read burst because read data will be returned before the first write data is required The timing is illustrated in Figure 51 Write Control amp Data Coherency Control Logic Figure 49 SSRAM ZBT Flow trough DN6000K10SC User Guide www dinigroup com 101 BOARD HARDWARE Write Control amp Data Coherency Write Address L Register Bupeeys Figure 50 SSRAM
41. This is technically a violation of the PCI specification but there are systems that have these signals floating PCI LOCKn PCI REQ64n PCI ACK64n DN6000K 10SC User Guide www dinigroup com 131 BOARD HARDWARE Note The function of LOCKn pin was deleted in version 2 3 of the PCI Specification The PCI JTAG signals TDI 5 are not used TDI are connected together per the PCI Specification to maintain JTAG chain integrity on the motherboard The signals TMS and TRSTn are left unconnected The following signals are not connected on the DN6000K10SC 4 3 3VAUX INTBn INTCn INTDn 11 Power System The DN6000K10SC supports a wide range of technologies from legacy devices like serial ports to DDR SDRAM and RocketIO multi gigabit transceivers This wide range of technologies requires a wide range of power supplies These are provided on the DN6000K10SC using a combination of switching and linear power regulators The DN6000K10SC can be hosted in a 3 3V PCI PCI X slot or it can be used in a standalone configuration During in system operation the primary supply to the DN6000K10SC secondary supplies is derived from the PCI 5V fingers while in standalone operation the primary power to the DN6000K10SC is derived from an external ATX type power supply 11 1 In System Operation Power is supplied to all the secondary supplies on the DN6000K10SC from the PCI 5V fin
42. ZBT Pipeline Clock Jf Lf LCT e Setup Hold Address Phase 1 i Syncburst Phase ZBTFT 1 1 1 Flowthrough Pipeli Phase Jin 1 i 8 L a Figure 51 Syncburst and ZBT SSRAM Timing 6 2 1 SSRAM Configuration The DN6000K10SC is factory stuffed with the Cypress P N CY7C1380B 133AC SSRAM devices please refer to datasheet for more information There are 524 288 x 36 SSRAM cells with advanced synchronous peripheral circuitry and a 2 bit counter for internal burst operation All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input ECLK 1 2 The synchronous inputs include all addresses all data inputs address pipelining Chip Enable CE burst control inputs ADSC ADSP and ADV write enables BWa BWb BWc BWd and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and burst mode control MODE DQa b c d and DPa b c d a b c d each ate 8 bits wide in the case of DQ and 1 bit wide in the case of DP Addresses and chip enables are registered with either Address Status Processor ADSP or Address Status Controller ADSC input pins Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin ADV DN6000K10SC User Guide www dinigroup com 102 BOARD HARDWARE Address data inputs and write controls are registered on chip to initiate self timed WRITE cycle WRITE cycles can be
43. a ground reference for signals in the ribbon cable 4 2 1 Clock Source J umper Header Figure 33 shows JP5 the clock source header connector used to select between different clock soutces Clock Source Jumpers Figure 33 Clock Source Jumper 4 3 External Clocks The clock source jumper allows the user a simple means to attach external clocks to the clock gtid The user can attach 10 pin ribbon cable to JP5B C which allows for connection the differential pair inputs of both RoboClocks JP5C ground pins for signal integrity These signals are described in Table 14 Both differential pairs provide some flexibility The user can bring a single 3 3V TTL input It can be attached to either input Howevet the other input must be left open The user can provide a differential clock input to the pair to the RoboClocks 4 3 1 Running The Whole Board Synchronously DCLKs ECLKs be set to run the same frequency The jumper JP4 is used to supply the clock from RoboClock1 to RoboClock2 See figure 34 DN6000K 10SC User Guide www dinigroup com 81 BOARD HARDWARE RoboClock I RoboClock II FB1 FB2 CLK R177 u22 R175 100 Lm 100 roso
44. at least 2 Otherwise the RoboClocks will output gatbage 4 5 4 Customizing the Oscillators The user can customize the frequency of the clock networks by stuffing different oscillators in and X5 The DN6000K10SC is shipped with a 14 318MHz oscillator in location X4 and a 33 333MHz oscillator in X5 The RoboClocks are not 5V tolerant so 3 3V oscillators are necessary The Dini Group suggests Digi Key http www digikey com as a possible source for the oscillators Of note is the Epson line of oscillators called the SG 8002 Programmable Oscillators Any frequency between 1 00MHz 106 25MHz can be procured in the normal Digi Key shipping time of 24 hours A half can 3 3 V CMOS version is needed with a tolerance of 50ppm The part number for an acceptable oscillator from this family would be SG 8002DC PCB ND e Package SG 8002DC Halfcan Output Enable e 33V CMOS e 50ppm If the order is placed via the web page the requested frequency to two decimal places is placed in the Web Order Notes The datasheet is on the CD ROM for this oscillator Any polarity of output enabled for each oscillator on pin 1 is acceptable Ensure the proper jumper settings for JP7 B9 JP7 B10 See Table 15 for a description 4 6 DDR Clocking The DDR Clock is generated in the FPGA by using the Digital Clock Managers DCM Clocking for DDR SDRAM requires the transmission of two clocks the positive clock and the negative clock SSTL 2 differential Thes
45. check verifies that the right version of Xilinx tools was used and the bitgen options have been set correctly To run the sanity check from the command line V osanityCheck f fpga bit d s See Table 8 for command line options Table 8 Sanity Check Command Line Options Command Line Required or Optional Desctiption Option f Required This option must be followed by the name of the bit file to perform the sanity check on d Optional This option prints out a description of the different bitgen options and their DN6000K 10SC User Guide ww w dinigroup com 63 PROGRAMMING CONFIGURING THE HARDWARE Command Line Required or Optional Description Option different values 5 Optional This option prints out the current bitgen settings found in the file specified with the f option If the bit file passes the sanity check you should see something similar to sanityCheck f fpga_sm bit Performing Sanity Check on File fpga_sm bit DATE 2003 07 16 TIME 10 47 01 PART 2vp50ff1 152 PILE SIZE 3262448 bytes ALL BITGEN OPTIONS ARE SET CORRECTLY If the bit file does not pass then a message stating why it didn t pass will print out For example sanityCheck f fpga_sm bit Performing Sanity Check on File fpga_sm bit DATE 2003 17 03 TIME 10 47 01 PART 2vp50ff1704 FILE SIZE 3262448 bytes ERROR PowerDown status pin is enabled you must disable this option to config
46. data cpu_addr gt with memory test a key enter Figure 14 Bar Memory Range Test Bar Memory Address Data Bitwise Test Opt k Same as BAR Memory Range Test except this tests the data bits one at a time DN6000K10SC User Guide www dinigroup com 38 INTRODUCTION TO THE SOFTWARE TOOLS c IC WINNTSystem32 cmd exe aetest_wdm c memory test on SSRAM 1 d gt memory test on SSRAM 2 h gt memory test on DDR 12 full memory test Cincluding blockram a M gt Main Menu 9 gt Quit PCI BASE ADDRESS 8600000 1 2 68000000 3 68000000 4 90000088 5 988900000 Please select option lemory test of range bitwise address data within a bar ar lt 52 0 tarting address offset byte addr Ux18800808 word count of memory range 0x20 lumber of Iterations for endless gt 1 top if an error occurs Cy or isplay any errors that occur or one with memory test ress a key Cpossibly twice Figure 15 Bar Memory Address Data Bitwise Test 1 1 5 Flash Menu Upon entering the Flash Menu from the Main Menu AETEST will output a screen similar to the one shown in Figure 16 IC WINNTSystem32 cmd exe aetest_wdm ASIC Emulator Flash Programming v5 1 gt Flashi Display 3 gt Flashi Erase amp Program Test tests Ux18880B8 bytes 55 Flashi Erase amp Program Test tests entire flash bootblock gt 7 Flashi Erase Ux18
47. datasheet RBDF1 ROBOCLOCK 1 Output Phase Function Select Controls the phase function of bank 1 amp 2 DCLK of outputs Refer to Table 3 in the datasheet ROBOCLOCK 1 Output Phase Function Select Controls the phase function of bank 1 amp 2 DCLK of outputs Refer to Table 3 in the datasheet JP6 B6 DDSO ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 1 amp 1 DCLK of outputs Refer to Table 4 in the datasheet JP6 B7 DDS1 ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 1 amp 1 DCLK of outputs Refer to Table 4 in the datasheet JP6 B8 FS1 ROBOCLOCK 1 Frequency Select This input must be set according to the nominal frequency Refer to Table 1 in the datasheet JP7 B1 FBFO1 ROBOCLOCK 1 Feedback Output Phase Function Select This input determines the phase function of the Feedback Bank s 0 1 outputs Refer to Table 3 in the datasheet JP7 B2 0501 ROBOCLOCK 1 Feedback Divider Function DN6000K10SC User Guide www dinigroup com JP7 B3 84 BOARD HARDWARE Desctiption Connector Select These inputs determine the function of the QFAO QFA1 outputs Refer to Table 4 in the datasheet FBDS11 ROBOCLOCK 1 Feedback Divider Function Select These inputs determine the function of the QFAO QFA1 outputs Refer to Table 4 in the
48. executables aetestnt exe and install exe are included in the CD ROM which is shipped with your DN6000K10SC Logic Emulation board The driver files QLDriver sys and QLDriver 16MB sys also included in the CD ROM located under Source CodeVPCI Software ntdriver driver 1386 checked The two driver files are identical except QLDriver 16MB sys only allocates a maximum of 16MB per BAR It is useful for systems with insufficient RAM To use it rename it to QLDriver sys and re install Follow the procedures listed below for installation 1 Place the files install exe and QLDriver sys into the same directory on your PC machine 2 Type install 3 After the driver is installed start the driver by selecting Control Panel Devices find QLDriver click Start 4 Run aetestnt exe Note Although this driver will work under Windows 2000 we recommend using the WDM driver instead If you must use it see the README txt file in the ntdriver docs directory on the CD ROM 1 5 Linux This version of AETEST has been tested on Red Hat Linux 7 2 kernel version 2 4 x The driver file dndev o and its source code ate included in the DN6000K10SC CD ROM The scripts dndev load and dndev unload which are also included in the CD ROM are used to load and unload the driver Follow the procedures listed below for installation 1 Login as root to start the driver and run the program 2 Load the driver type sh dndev load
49. file 1 1 4 Memory Menu Writes PCI Device ID Vendor ID and the BARs into a file from the active device This option is for advanced users only Upon entering the Memory Menu from the Main Menu AETEST will output a screen similar to the one shown in Figure 7 WINNT System32 cmd exe aetest_wdm ASIC Emulator PCI Controller Driver v5 Compiled on Jan 20 2004 at 11 05 27 12 Write Dword Same Address gt 2 gt Read Dword Same Address 3 Write Read Duord Same Address 4 gt BAR Memory Fill 5 gt BAR Memory Write 8 gt BAR Memory Display p gt bar memory range test k gt bar memory address data bitwise test n gt memory test on FPGA block memory c gt memory test on SSRAM 1 d gt memory test on SSRAM 2 h gt memory test on DDR 12 full memory test including blockram gt M Main Menu Q gt Quit PCI BASE ADDRESS 28000000 1 3 68000006 4 Please select option 9000000 2 99808000 66880000 5 00000000 Figure 7 Memory Menu The possible Memory Menu options and their descriptions are listed below In each description an example transaction will be shown The accesses will focus on SSRAM 2 at the AETEST address location of 0x200000 NOTE The AETEST addtess is offset by 2 to the left when compared to the actual SSRAM address For example AETEST address 0x200000 is equivalent to the SSRAM address 0x80000 DN6000K10SC User Guide ww w d
50. information The circuit shown in Figure 40 must be used to interface the oscillator s LVPECL outputs to the LVDS inputs of the transceiver reference clock Alternatively DN6000K10SC User Guide www dinigroup com 92 BOARD HARDWARE the LVDS 25 DCI input buffer may be used to terminate the signals with on chip termination as shown in Figure 41 EG2121CA 2 5V PECL 1000 05024 025a 121102 Figure 40 LVPECL Reference Clock Oscillator Interface EG2121CA 2 5V PECL 10022 UG0e4_025e_ 112202 Figure 41 LVPECL Reference Clock Oscillator Interface DCI Pletronics LV1145B LVDS Outputs See the Pletronics website for detailed information The circuit shown in Figure 42 must be used to interface the oscillators LVDS outputs to the LVDS inputs of the transceiver reference clock Alternatively the LVDS 25 DCI input buffer may be used to terminate the signals with on chip termination as shown in Figure 43 LV1145B 2 5V LVDS Figure 42 LVDS Reference Clock Oscillator Interface DN6000K 10SC User Guide www dinigroup com 93 BOARD HARDWARE LV1145B 2 5V LVDS UGae4 oesd 112202 Figure 43 LVDS Reference Clock Oscillator Interface DCI Note Depending on weather or not the LVPECL or the LVDS parts is selected the user must appropriately terminate the differential signals with R87 R91 and R95 to maintain optimum signal integrity 4 9 External User Clock SMA The SMA connectors J13 J7 allow
51. input clock solutions The DN6000K10SC is shipped with both a 14 318 MHz X4 and a 33 33 MHz X5 oscillator Neither X4 nor X5 is used by the configuration circuitry so the user is free to stuff any standard 3 3 V half can oscillators in the X4 and X5 The Clock Grid can also accept a 5x2 ribbon cable This cable can provide input clocks to the RoboClocks The two RoboClocks offer functional control of clock frequency and skew among other things The two RoboClocks PLL clock buffers U21 and U22 are configured via header arrays JP6 JP7 JP8 The DN6000K10SC is factory stuffed with CYB994V which can operate at frequencies from 24 MHz to 200 MHz respectively Each Roboclock clock chip has 16 output clocks along with two feedback output clocks Two sets of eight output clocks are jumper selectable for each chip The feedback clocks are controlled separately The PLL clock buffers can accept either LVTTL33 or Differential LVPECL reference inputs refer to Figure 32 devices can operate at up to 12x the input frequency while the output clocks can be divided up to 12x the operating frequency 43 8V 3 3 3 3 3 3V Figure 32 LVPECL Clock Input and Termination Note The schematic shows capacitors in locations C354 C358 C356 C355 These are actually populated with 0 ohm resistors for direct connection to the RoboClock reference inputs The terminating resistors to GDN and 3 3V are not stuffed When using LVPECL it is nec
52. listed to help the user match up the Device ID and Vendor ID with the desired device number DN6000K 10SC User Guide ww w dinigroup com 28 INTRODUCTION TO THE SOFTWARE TOOLS Option Function Name Description Set PCI Function Number Sets a PCI function number of your choice as the active function of a multi function device hex input The Device ID and Vendor ID of each function within the active device number to help the user choose the desired function D Display all configured PCI Displays the PCI device numbers and corresponding devices Device ID and Vendor ID of all devices seen on the bus This function will not display device numbers with a Device ID and Vendor ID of all one OxFFFF 1 Display Vendor and Device Displays the Vendor ID and the Device ID for the ID DN6000K10SC which should be Ox17df and 0x1605 0x1608 respectively 2 Display Vendor and Device Displays the Vendor ID and Device ID of the active ID for PCI device function device and function number 3 Loop on PCI device Reads and displays the Vendor ID and Device ID of the function 7 and display active device number and function number Repeats Vendor and Device ID until the user presses a key to stop it 4 Loop on PCI device Reads the Vendor ID and Device ID of the active function 7F 0 and without device number and function number without displaying displaying Vendor and them This f
53. machine the PC must be booted using a DOS boot disk A DOS boot disk is packaged with the DN6000K10SC The user only needs to follow the steps listed below to run the DPMI version of AETEST Follow the procedures listed below for installation 1 Place the files aetestdj exe and cwsdpmi exe The DOS Extender into the same directory on your PC machine 2 Bootinto DOS mode if you have not already done so 3 A DOS Boot disk must be used on the Windows machine 4 Runaetestdj exe 1 2 Windows 98 ME using a VxD driver Instead of running AETEST directly from DOS the user can run AETEST with a VxD device driver The driver file PCICFG VXD and the executable aetest98 exe ate included on the DN6000K10SC CD ROM drivers source code and its makefile are also included Follow the procedures listed below for installation 1 Place PCICFG VXD and aetest98 exe into the same directory 2 When Windows fitst statts with the device plugged in it should ask for a device driver Select Specify the location of the driver Note that the board must be configured with a valid bitfile Our reference design will work DN6000K10SC User Guide www dinigroup com 13 154 APPENDIX 3 4 6 Select Display a list of the drivers in a specific location Select Other devices Under the Manufacturers tab select unknown device Under Models select unsupported device Run aetest98 exe
54. metal bars they can carry a lot of current The PCI bracket MP1 is also connected to the ground plane at each of the screw mounts Mounting holes are provided for standalone operation DN6000K10SC User Guide Www dinigroup com 151 BOARD HARDWARE The DN6000K10SC conforms to the following dimensions DN6000K10SC User Guide www dinigroup com 152 BOARD HARDWARE uwun 444 3000000 X x x POOKIE x 56 x t X xt tt tt tt ttt X x X X MK x Mir jt Mii del RGN X X xx 5 Lupe x hota 44 e t 44 es ie s nu 42 3 E ox 66 de i up ft T Ht x 8 3 5 DN6000K10SC User Guide www dinigroup com 153 APPENDIX Chapter Appendix 1 Appendix A AETEST Installation Instructions 1 1 DOS and Windows 95 98 ME using DPMI Precompiled executables aetestdj exe and cwsdpmi exe are included in the CD ROM which is shipped with your DN6000K10SC Logic Emulation board If the user is running DOS on a Windows 95 98 ME
55. one to four bytes wide as controlled by the write control inputs Individual byte write allows individual byte to be written Bwa controls DQa and DPa BWb controls DQb and DPb BWe controls DQc and DPc BWd controls DOd and BWa BWb BWc BWd can be active only with BWE being LOW GW being LOW causes all bytes to be written WRITE pass through capability allows written data available at the output for the immediately next READ cycle This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance All inputs and outputs of the CY7C1380B and is JEDEC standard JESD8 5 compatible Note CE2 and CE2n are hard wired on PWB to thete respective active states Use SRAM_CExn signal to select the individual devices 6 2 2 SSRAM Clocking The SSRAMs are clocked directly by RoboClock 2 021 ECLK1 and ECLK2 are LVTTL33 signals and the SSRAMs ate LVCMOS25 The CLK interface is level translated by the flowing circuit in Figure 52 3 3V Figure 52 Clock Level Translation 6 2 3 SRAM Termination No termination is necessary but the option to use DCI is available on all signals 6 2 4 SSRAM Connection to the FPGA The SSRAM memory components are connected to the FPGA on Bank 2 and Bank 3 as listed in Table 22 The VCCO of the IO banks are connected to 2 5V Table 22 Connection between FPGA and SRAM s Signal Name FPGA Pin 5 1 0 U13 M4 SRAMI1 1 U13 M3
56. s is number from left to right LEDO to LED7 Table 28 GPIO LED s Signal Name Description CPLD LEDOn Always Off CPLD_LED1n Indicates data transfer between SM and FPGA CPLD_LED2n Lights when FPGA is not configured CPLD_LED3n Lights when PWR_RSTn is active DN6000K10SC User Guide www dinigroup com 121 BOARD HARDWARE FPGA LEDO0n LEDin MCU_LED2n MCU_LED3n Status FPGA On On Successful On Configuration Error during Configuration ot No FPGAs configured 9 2 FPGA GPIO LED s The DN6000K10SC provides 10 GPIO LED s directly connected to the FPGA IO pins Table 29 lists the FPGA GPIO on the DN6000K10SC and is available to the user The signals are active LOW Table 29 FPGA GPIO LED s FPGA U13 20 U13 K20 U13 C21 U13 D21 U13 E21 U13 F21 U13 G21 U13 H241 115 024 1013 22 9 3 Test Points The DN6000k10SC has several test points for logic analyzers oscilloscopes or other pieces of test equipment They are TP1 TP2 For possible uP crystal Not used DN6000K10SC User Guide Www dinigroup com 122 BOARD HARDWARE TP3 PCI PCI X PME rewotk point if needed TP4 GND TP5 PCI PCI X 3 3V AUX not used 6 3 0 VCCO voltage for PCI PCI X VCCO TP7 DDR Termination voltage 1 25V TP8 GND TP9 ECLK4 TP10 DCLK4 TP11 CCLK3 TP12 GND TP13 GND TP14 1 5V TP15
57. silkscreen as well as a dot Pin 1 on the 5 X 2 cable header is indicated with a triangular shape printed on the connector MCU TXD MCU 69232 Interface 3 3 U6 TUN x i 2 ROUT RN 3 t x 2 BEEN x ENEHSE 71 EN xH Hx FORCEON INVALID x zo a 1 7 0 1uF P ps V C1 V C2 vec C9 i qe GND 1CL3221 n C129 C131 C130 0duF o female to female RS232 cable is provided with the DN6000K10SC This cable will attach directly to the RS232 port of a PC The Dini Group suggests Jameco as a possible supplier http www jameco com The part number is 132345 Male to female extension cables are part number 25700 DN6000K 10SC User Guide ww w dinigroup com 51 PROGRAMMING CONFIGURING THE HARDWARE 4 Configuring the FPGA using SelectMAP The simplest mode of configuration for the DN6000K10SC Virtex II PRO FPGA involves the SeleccMAP configuration method using a SmartMedia card The DN6000K10SC ships with two 32 MB SmartMedia cards One of these SmartMedia catds contains a reference design bit file produced for SelectMAP configuration and a file named main txt that sets the configuration options see Creating Configuration File main txt The SmartMedia card containing the reference design has been write protected by the application of the silver write prot
58. source code for bar read dword is portable to each of the operating systems intended for AETEST usage DN6000K 10SC User Guide ww w dinigroup com 163 APPENDIX 2 7 dma buffer allocate dma buffer allocate is a high level function C function which is recommended for development by users of the DN6000K108C 2 7 1 Description buffer allocate allows users of the DN6000K10SC to allocate a DMA buffet 2 7 2 Arguments The arguments for dma buffer allocate are shown in Table 42 They are listed in order Table 42 dma buffer allocate Arguments Argument Description buffer handle hndl Pointer to a handle int for the allocated DMA buffer int nbytes Number of bytes of memory to allocate int phy_addr Pointer to an int specifying the physical address of the DMA buffer typedef int dma_buffer_handle 2 7 3 Return Values A successful function call will return zero An error will return a non zero value If 1 is returned the allocation failed If 2 is returned the DPMI implementation of AETEST is not being used See Notes An integer indicating the handle for the DMA buffer is placed in the variable location pointed to by An integer indicating the physical address of the DMA buffer is placed in the variable location pointed to by 2 7 4 Notes The dma buffer allocate code is written for use in the DPMI DOS implementation of AETEST DN6000K 10SC User Guide ww w dinig
59. the call will fail However DeviceloControl will return all of the data in the output buffer and returned byte count will correspond to the amount of data returned IpOverlapped If hDevice was opened with the FILE FLAG OVERLAPPED flag IpOverlapped must point to a valid OVERLAPPED structure Under these conditions the operation is asynchronous i e overlapped operation If IpOverlapped is NULL under these conditions the function will fail If the FILE FLAG OVERLAPPED was not used to open hDevice IpOverlapped is ignored The operation must complete before DeviceloConttol will return DN6000K 10SC User Guide ww w dinigroup com 171 APPENDIX 2 12 5 Derived Functions The following functions are based on DeviceIoControl OL ConfigRead ConfigW rite OL ControlRead ControlWrite BAR Read QL BAR Writ OL MapBufferAddr QL_UnMapBufferAddr OL_GetBufferSize OL DMA Writ OL Map BAR OL UnMap and OL ResetDevice DN6000K10SC User Guide www dinigroup com 172 DN6000K10SC User Guide APPENDIX INDEX A About This Manual 1 AETEST 12 Bar Memory Addtess Data Bitwise Test 38 Bar Memory Display 36 Bar Memory Fill 34 BAR Memory Fill Write Display 25 Bar Memory Range Test 38 BAR Memory Range Tests 25 Bar Memory Write 35 BAR Number 32 Basic C Functions 26 158 Configure BAR from file 31 Daughter Board Menu 28 40 Daughter Card Test 25 DDR SDRAM
60. the provided URLs Resource Description URL User Manual This is the main source of technical information The manual should contain most of the answers to your questions DN6000K10SC User Guide www dinigroup com 1 ABOUT THIS MANUAL Resource Description URL Dini Group Web Site The web page will contain the latest manual application notes FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com Data Book Pages from The Programmable Logic Data Book which contains device specific information on Xilinx device characteristics including readback boundary scan configuration length count and debugging http suppott xilinx com partinfo databook htm E Mail You may direct questions and feedback to the Dini Group using this e mail address support dinigroup com Phone Support Call us at 858 454 3419 during the hours of 8 00am to 5 00pm Pacific Time FAQ The download section of the web page contains a document called DN6000K10SC Frequently Asked Questions FAQ This document is periodically updated with information that may not be in the User s Manual 3 Conventions This document uses the following conventions An example illustrates each convention 3 1 Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Courier font Messages prompts and Spee
61. will be introduced 4 8 1 Clocking Methodology At speeds of 2 5 Gbps or greater REFCLK configuration introduces more than the maximum allowable jitter to the RocketlO transceiver For these higher speeds BREFCLK configuration is required The BREFCLK configuration uses dedicated DN6000K 10SC User Guide www dinigroup com 91 BOARD HARDWARE routing resources that reduce jitter BREFCLK must enter the FPGA through dedicated clock I O BREFCLK can connect to the BREFCLK inputs of the transceiver and the CLKIN input of the DCM for creation of USRCLKs For more information refer to the Rocket IO User Guide available from the Xilinx website REF_CLK_V_SEL refclk2 refclk_out to PCS and PMA REFCLKSEL brefclk brefclk2 ug024_35_091802 Figure 39 REFCLK BREFCIK Selection Logic 4 8 2 Connections between FPGA and DDR PLL Clock Buffer The connection between the FPGA and the external oscillators are shown in Table 18 Table 18 Connections between FPGA and Rocket IO Oscillators Signal Name FPGA Pin OSCILLATOR 4 8 3 Reference Clocks A high degree of accuracy is required from the reference clock X2 For this reason it is required that one of the oscillators listed in this section be used The DN6000K10SC is shipped with the Pletronics parts Note the PCB footprint was designed to take either Epson EG 2121CA 2 5V LVPECL Outputs See the Epson Electronics America website for detailed
62. x 25 GND 22 26 CGND 5 CGND 2 4 SmartMedia F2 3 3V re POLYSWITCH 126 C127 O tuF 0 1uF Figure 29 SmartMedia Connector Note Do not press down on the top of the SmartMedia connector J1 if a SmartMedia card is not installed The metal case shorts 3 3V to GND 3 3 2 SmartMedia connection to CPLD MCU Table 11 shows the connection between the SmartMedia connector and the CPLD MCU Table 11 Connection between CPLD MCU CPLD MPU Connector U5 26 11 6 5 27 17 5 28 11 8 5 31 1 9 5 33 1143 5 34 1114 5 35 11 15 5 39 11 16 5 20 112 5 21 11 5 m Ue 5 22 1 4 DN6000K 10SC User Guide www dinigroup com 76 BOARD HARDWARE Signal Name CPLD MPU Connector SM RDYBUSYN U5 40 1 19 SM WPN 5 23 J1 5 SM_CEN 5 24 1 21 SM REN 5 25 j1 20 U U U U SM WPIN 3 61 J1 27 SM CDN 03 8 1 11 3 4 Boundary Scan J TAG IEEE 1532 Mode In boundary scan mode dedicated pins are used for configuring the Virtex II Pro device The configuration is done entirely through the IEEE 1149 1 Test Access Port TAP The FPGA JTAG interfaces to IO on the CPLD This allows manipulation of the data as requited by the application and allows the JTAG chain to become an address on the existing bus The processor can then read from or write to the address representing the
63. 0 13 451675 3 Sundar Rajan Essential VHDL RTL Synthesis Done Right DN6000K10SC User Guide www dinigroup com 4 ABOUT THIS MANUAL For those that like VHDL Edwin Breecher The Booster Improve Your Performance Dramatically John Morgan Improve Your Typing Speed and Accuracy DN6000K10SC User Guide www dinigroup com DESIGN CUSTOMIZATION Chapter Getting Started Congratulations your purchase of the DN6000K10 5C LOGIC Emulation Board You can begin by installing the software or by powering on your DN6000K10SC If you wish to begin installation please follow the installation instructions The remainder of this chapter describes the contents of the box and how to start using the DN6000K105C LOGIC Emulation Board l Precaution The DN6000K10SC is sensitive to static electricity so treat the PCB accordingly The target markets for this product are engineers that are familiar with FPGA s and circuit boards so a lecture in ESD really isn t appropriate and wouldn t be read anyway However the following web page has an excellent tutorial on the Fundamentals of ESD for those of you who are new to ESD sensitive products http www esda ote basics patt1 cfm The DN6000K10SC has been factory tested and pre programmed to ensure correct operation You do not need to alter any jumpers or program anything to see the board work A reference design is included on the enclosed CD Please verify that the b
64. 0 44 72 SRAM1 DQb2 SRAM1 A11 45 73 SRAM1 DQb3 SRAM1 A12 46 74 SRAM1 DQb4 SRAM1 A13 47 75 SRAM1 DQb5 SRAM1 A14 48 78 SRAM1_DQb6 SRAM1_A15 49 79 SRAM1_DQb7 SRAM1_A16 50 2 SRAM1 DQcO SRAM1 A17 43 3 SRAM1 DQc1 1 A18 42 6 1 DQc2 SRAM1 A19 39 7 SRAM1_DQc3 SRAM1_A20 38 8 SRAM1_DQc4 9 SRAM1_DQc5 SRAM1_ADVn 83 SRAM1_ADSPn 84 5 1 ADSCn 85 12 SRAM1 DQc6 13 SRAM1 DQc7 18 SRAM1 DQdO 19 SRAM1 DQd1 22 SRAM1 DQd2 23 SRAM1_DQd3 24 SRAM1_DQd4 25 1 DQd5 28 SRAM1 DQd6 29 SRAM1 DQd7 SRAM1 BWAn 93 SRAM1 BWBn 94 SRAM1_BWCn 95 SRAM1_BWDn 96 SRAM1 BWEn 87 SRAM1 GWn 88 51 SRAM1 DQPa SRAM1 LBOn 31 80 SRAM1 DQPb _DIV 89 SRAM1_DQPc 30 SRAM1_DQPd SRAM1 CEn 98 SRAM1 CE2 97 4 SRAM1 CE2n 92 6 66 SRAM1 OEn 86 SRAM1 ZZ 64 5 3 3V 4 2 5V 1 SIN ia NOP JoJo N CY7C1481V33 TQFP100 Figure 46 SSRAM Connection The SSRAM s can be stuffed with the following options Pipelined standard DN6000K10SC User Guide www dinigroup com 99 BOARD HARDWARE Flow through Pipelined with NoBL Flow through with NoBL e Pipelined Flow trough Syncburst Flow through Figure 47 is the most straightforward type of SSRAM Write data may be accepted on the same clock cycle as the activation signal and address and read data is returned one clock cycle after it is requested Syncburst is designed to allow two controllers to access the same
65. 0 9 90 BOARD HARDWARE 4 7 Power PC PPC Clock A 3 3 V half can oscillator X3 and the signal SYS CLK provide an external clock source for the PPC The oscillator is socketed and the DN6000K10SC is shipped with a 100MHz oscillator refer to Figure 38 3 3V O R30 22H C69 0 047uF us R29 Figure 38 PPC External Clock 4 7 1 Clocking Methodology Refer to the Xilinx application notes for more information on this subject 4 7 2 Connections between FPGA and DDR PLL Clock Buffer The connection between the FPGA and the external oscillator are shown in Table 17 Table 17 Connection between FPGA and External PPC Oscillator Signal Name FPGA Pin DDR PLL Clock Driver U20 SYS CLK U13 AH18 X33 4 8 Rocket IO Clocks The DN6000K10SC provides one oscillator for RocketIO X1 There are eight clock inputs into each RocketIO transceiver instantiation REFCLK and BREFCLK are reference clocks generated from an external sources and presented to the FPGA as differential inputs The reference clocks connect to the REFCLK or BREFCLK ports of the RocketIO multi gigabit transceiver MGT While only one of these reference clocks is needed to drive the MGT BREFCLK or BREFCLK2 must be used or serial speeds of 2 5 Gbps or greater The reference clock also locks a Digital Clock Manager DCM or a BUFG to generate all of the other clocks for the GT Never run a reference clock through a DCM since unwanted jitter
66. 13 AA29 Www dinigroup com Cue eC BOARD HARDWARE Signal Name FPGA Pin DDR 6A DATA14 U13 AB32 c DDR 6A DATA15 U13 AB31 DDR_FPGA_6A_UDQS U13 Y26 DDR_FPGA_6A_LDQS U13 V24 DDR_FPGA_6A_UDM U13 AC34 DDR_FPGA_6A_LDM U13 Y31 DDR FPGA 6A U13 AA33 DDR_FPGA_6A_BA1 U13 AB33 DDR_FPGA_6A_CASN U13 W32 DDR_FPGA_6A_CKE U13 AA28 DDR 6A CSN U13 V25 DDR_FPGA_6A_RASN U13 W31 DDR FPGA 6A WEN U13 V26 DDR FPGA 6B ADDO U13 AF28 DDR_FPGA_6B_ADD1 U13 AF27 DDR FPGA 6B ADD2 U13 AK34 DDR FPGA 6B ADD3 U13 AK33 DDR FPGA 6B ADD4 U13 AG29 DDR FPGA 6B ADD5 U13 AL34 DDR FPGA 6B ADD6 013 A133 DDR FPGA 6B ADD7 U13 AG28 DDR FPGA 6B ADDS U13 AH27 DDR_FPGA_6B_ADD9 U13 AH30 DDR_FPGA_6B_ADD10 U13 AH29 DDR FPGA 6B ADD11 U13 AK31 DDR_FPGA_6B_ADD12 U13 A 28 DDR FPGA 6B ADD13 013 27 G He hE E ere ape m EL es ae DDR 6B DATAO U13 AE33 DDR 6B DATA1 DN6000K10SC User Guide U13 AF33 Www dinigroup com 114 BOARD HARDWARE Signal Name FPGA Pin DDR SDRAM DDR_6B_DATA2 13 1 018 5 DDR 6B DATA3 13 AE30 018 7 DDR 6B DATA4 13 AC26 U18 8 DDR 6B DATA5 13 AC25 18 10 DDR 6B DATAG6 13 AF32 18 11 DDR
67. 130 5 _ TST HDRA18 31 Cisi TST_HDRA97 TST_HDRATY 32 132 HDHA98 GND 33 188 HDRA99 20 34 134 TST HDRAZT 35 7 135 TST 22 36 136 TST HDRA102 TST 23 3717 1837 HDHA103 TST HDHA24 38 138 TST HDRA104 TST HDRA25 39 139 5 5 _ 26 40 7 140 GND TST HDRA27 41 1141 5 _ 6 TST HDRA28 42 7 142 TST_HDRATO7 TST HDRAZS 43 143 GND 44 144 HDHATOS TST_HDRAGO 45 145 HDHATIO TST_HDRAST 46 146 TST TST HDHA32 47 7147 TST HDHAT12 HDHA33 48 148 TST_HDRATTS TST HDRAS 329 49 TST HDRATI4 ST HDHASS 50_ 7 150 ST HDRATTS _ 51 0 4 151 ST HDHA37 52 152 m ST 53 7 ST HDRATIT ST HDHASS 5417 154 ST GND 55 7 155 ST HDRATIS ST HDRA4U 56 7 156 5 _ 20 5717 157 ST 21 ST HDHA42 58 158 ST HDHAT22 ST HDRA43 59 159 ST HDRAT23 ST HDHA44 60 160 ST HDRAT24 ST HDRA4S 61 161 25 ST HDHRA46 62 162 GN 47 63 163 TST HDRAT26 TST HDRA48 64 164 HDHA127 TST_HDRA49 65 165 TST HDRA128 GND 66 166 129 TST_HDRASO 67 1167 TST HDRA130 TST_HDRAS1 68 16
68. 18 SmartMedia Connector 75 Interface 76 SSRAM Connection to FPGA 103 Termination 103 SSRAM Types 99 T Test Header 135 V V2PDK 22 Design Process 22 176 APPENDIX Virtex II FPGA Fabric Active Interconnect 19 Arithmetic 18 BGA 20 Clock management circuitry 19 DCI 19 DCM Modules 19 DES Support 20 Differential Signaling 19 Flexible logic resources 18 HyperTransport 19 IEEE1532 20 LVTTL LVCMOS sink source current 19 Noise Immunity 19 PCI PCI X 19 Select I O Ultra Technology 19 SelectLink 19 DN6000K10SC User Guide www dinigroup com SelectRAM 18 SRAM based configuration 19 User I O 19 VCCINT power supply 20 Virtex II Pro Active Interconnect 17 Clock Management Circuitry 17 DCI 17 Features 16 History 16 Logic resources 17 Multiplier Blocks 17 PowerPC Blocks 17 Rocket IO Trancievers 16 SelectIO Technology 17 SelectRAM 17 SRAM based configuration 17
69. 2 Class 2 termination is used for bi directional signaling such as data signals It is based on a 500 controlled impedance driver and a 500 parallel termination to VTT for the receiver at both ends connected through a 500 controlled impedance transmission line Figure 55 shows a basic SSTL2 Class 2 circuit The driver is brought to 500 by the addition of a 250 series resistor immediately adjacent to the driver Figure 55 SSTL2 Class 2 Termination Note DCI termination must be implemented in the DDR SDRAM controller design DN6000K10SC User Guide www dinigroup com 111 BOARD HARDWARE 6 3 5 SDRAM Power Supply The DATEL 2 5V module U25 is used to supply power to the 2 5V plane that supplies the VDDQ pins of the DDR SDRAM devices According to the JEDEC Specification Double Data Rate DDR SDRAM termination voltage VTT must track 50 of VDDQ over voltage temperature and noise A ML6554 U19 is used to provide a voltage source for DDR termination Connecting the pin to the 2 5V supply allows the regulator to track the VDDQ supply refer to Figure 56 A dedicated VREF output supplies the VREF pins on the FPGA as well as on the DDR SDRAM devices and maintains a less that 40mV offset from VTT DDR Switching Power Supply VTT 1 25V 3A 3 3V 4 4 1 C318 C61 C63 C70 C71 V N a 182 16 avec VDD 0 1uF 15 DD vcca PVDD1 x vngr IN 3 3V R145 A 12
70. 298e 808073d6b 9 3 4279 2f963die 836 1651 835ccaB88 38778ad8 3835a76c 1818b73f dfb687df 1f64338c 69ef92e1 400 6 ecdb4538 2604ed96 496 984 285d858a d66 f8334 a31b888f fd5f447b i1455afcf c87dB8ff3 52a892b4 dc2837f1 888 535 33 2 91cc8e9e be8f252a b9b5ebi2 93 4 1 3f32de24 974 79 878a678c bd3da721 ad919433 ef85e3c3 8080833cf 4b5fe21e 98 4 1 24 54503 lt back lt j ump 4050402 Quit Figure 13 Bar Memory Display The sample view shown in Figure 13 displays 160 DWORDs of SSRAM 2 data starting at address 0x200000 The data displays the results of the transactions shown in Figure 11 and Figure 12 For Figure 11 alternating DWORDS of Oxaaaaaaaa and 0x55555555 were written starting at address 0x200000 A total of 0x80 128 decimal bytes of data were written Then for Figure 12 the DWORD Oxabcdef45 was written to the address 0x200020 It is clear to see the results of the Bar Memory and Bat Memory Write transactions with the Bar Memory Display function SSRAM Memory Test Opt c f SSRAM Memory Test allows the user to test one of the four SSRAMs on the DN6000K108C DDR SDRAM Memory Test Opt h DDR SDRAM Memory Test allows the user to test all of the DDR SDRAMs on the DN6000K10SC Full Memory Test Opt 1 DN6000K 10SC User Guide ww w dinigroup com 37 INTRODUCTION TO THE SOFTWARE TOOLS Pull Memory Test tests each of the four SSRAMs and the Virtex II PRO Blo
71. 3 15 IP8 25 IST HDRA12 013 130 1 006 BP3N89 P3N89 3 17 P8 26 IST HDRA13 013 129 1 027 BP3N88 P3N88 73 19 IP8 27 IST HDRA14 013 128 1 028 BP3NS87 P3N87 3 21 IP8 28 IST HDRA15 U13 127 1 029 BP3N86 P3N86 13 23 IP8 29 IST HDRA16 013 133 1 030 BP3N83 P3N83 13 25 IP8 30 IST HDRA17 013 633 1 031 BP3N82 P3N82 J3 27 IP8 31 IST HDRA18 U13 R32 1 032 BP3NT77 P3NT77 3 29 IP8 32 IST HDRA19 1013 631 1 003 Connect 8 33 GND 013 85 1 034 BP3N76 P3N76 13 31 P8 34 IST HDRA20 U13 T26 1 005 BP3N75 P3N75 13 33 IP8 35 IST HDRA21 U13 125 1 006 BP3N74 P3N74 13 35 P8 36 IST HDRA22 U13 R34 1037 P3N69 2 42 IP8 37 IST HDRA23 U13 P34 1 088 P3N68 2 43 IP8 38 IST HDRA24 U13 R29 1 009 BP3NG67 P3N67 13 37 IP8 39 IST HDRA25 U13 R28 1 040 BP3N66 P3N66 13 39 IP8 40 IST HDRA26 013 024 1 041 BP3N63 P3N63 _ 3 41 IP8 41 IST HDRA27 U13 124 1 042 BP3N62 P3N62 13 43 8 42 IST HDRA28 U13 P32 1 043 BP3N57 P3N57 13 45 IP8 43 IST HDRA29 1013 31 1 044 Connect P8 44 GND U13 E5 1045 BP3N56 P3N56 13 47 IP8 45 IST HDRA30 U13 P30 1 006 Connect 8 46 IST HDRA31 U13 P29 1047 Connect 8 47 IST HDRA32 U13 R26 1 048 BP3N49 P3N49 IP8 48 IST HDRA33 U13 R25 1049 BP3N48 P3N48 4 3 IP8 49 IST HDRA34 U13 P33 1 050 P3N47 J2 19 IP8 50 IST HDRA35 U13 N33 DN6000K 10SC User Guide www dinigroup com 145 BOARD HARDWARE Daughter Card Connections DN6000K10SC IO Connections
72. 3 K34 1 077 Connect 8 77 GND U13 E5 DN6000K10SC User Guide www dinigroup com 146 BOARD HARDWARE Daughter Card Connections DN6000K10SC IO Connections Test Signal Name Connector Test Signal Name FPGA Pin Header 1 078 BP4N26 PAN26 4 43 IP8 78 IST HDRAG60 U13 L30 1 079 BP4N21 PAN21 14 45 IP8 79 IST HDRAG1 U13 L29 1 080 BP4N20 PAN20 14 47 IP8 80 IST HDRAG62 U13 L28 1081 Connect 8 81 IST HDRA63 U13 L27 1 082 Connect P8 82 5 64 U13 K33 1 083 Connect 8 83 IST HDRA65 U1333 1 004 Connect 8 84 IST HDRA66 1013 31 1 085 Connect P8 85 5 67 U13 K30 1 086 Connect 8 86 IST HDRA68 13 26 1 087 Connect 8 87 IST HDRA69 U13 M25 1 088 No Connect 8 88 GND U13 E5 1 089 Connect 8 89 IST HDRA70 U13 H34 1 000 Connect P8 90 5 71 U13 H33 1 091 Connect P8 91 IST HDRA72 U13 H32 1 092 Connect P8 92 5 73 U13 H31 1 003 Connect 8 93 1 5V U13 L11 1 004 Connect 8 94 IST HDRA74 U13 K28 1 095 P4NX7 7 45 IP8 95 IST HDRAT75 U13 K27 1 000 6 7 47 IP8 96 ISI 76 U13 32 1 007 Connect 8 97 IST HDRAT77 U13J31 1 098 Connect P8 98 TST_HDRA78 13 30 1 009 No Connect 8 99 GND U13 E5 1 100 Connect P8 100 12 No Pin 1101 Connect 8 101 U13 E5
73. 50 5 3051 0823 3051 4g DISS F Diss iva gt 69 REDET Lm mo 23 23 18 2080 rBi NU 100 222 t ie 2050 FB NU RIBS A 100 DE 34 2081 HUM CRUS a Disc Sr 2051 UT ERIS VA CR ar 38 iro 8 32181 xin 1060 24 ipso 35 85 YOON 32 voc 65 VON BS 85 42 VGCN 504 22 vccN 37 vcon 15 VCN TET vcon VGCN VGCN gi8 ROLKI 78 veca voca ROLK2 78 voca 28 TH 54 vcca 3 Veca vcca 32 voca veca 4571 voca CCQ 30 voca 20 veca 20 vcca veca Figure 34 Roboclock Schematic 4 4 Common Clock Source Selections The following configuration is the most common Configuration 1 CLOCKA gt PLL1A CLOCKB gt PLL2BN RoboClock 1 U22 is driven from oscillator X3 RoboClock 2 U21 is driven from oscillator X5 RoboClock 2 can also be driven from RoboClock 1 output DCLK3 if required see section 4 3 1 on JP4 4 5 RoboClock PLL Clock Buffers The CY7B994V 022 021 High Speed Multi Phase PLL Clock Buffers offer user selectable control over system clock functions Each RoboClock has an LED indicating a lock condition The lock condition of RoboClock1 U22 is DS13 and RoboClock2 021 is 0512 During normal operation these LED s should be ON Eighteen configurable outputs each driv
74. 6000K10SC offers one 200 pin test header P8 that allows the user connection to discrete FPGA pins refer to Figure 64 DN6000K10SC User Guide Www dinigroup com 135 BOARD HARDWARE 12V 1 101 GND GND 277 L102 ST HDHA Hos 15V lt 04 104 2 5V 5 7 105 3 35V 6 106 DCLKi 7 107 GND gt DCLKI 2 a 108 GND s 109 GND 10 L0 GND Pg gt emp 11 TST HDRA7S TST HDRAO iel 112 5 _ TST HDRAi 183 113 TST HDRABT TST HDRA2 141 114 TST HDRAE2 TST HDRA3 15 115 TST HDRA83 TST HDRA4 16 7 116 84 TST HDRA5 117 TST HDRA85 TST 18 7 gt 018 GND TST HDRA7 19 119 TST_HDRA86 TST_HDRAS 2017 120 TST 87 TST HDRAS 2117 121 TST_HDRA88 GND 2212 122 TST 0 28 128 TST 90 TST HDRATT 24 124 TST HDRAG1 TST HDRA12 25 125 TST HDRA92 TST HDRA13 26 126 TST HDRA93 TST 27 127 TST 94 TST_HDRATS 28 128 HDRAS5 TST_HDRAT6 29 gt 129 GND TST HDRAi7 30
75. 64 2 7 3 innen M A A ENAA E EE AE EE 164 2 7 4 Notes 164 28 165 2 8 1 165 2 8 2 Arguments 165 2 8 3 nami c 165 2 8 4 nn 165 2 9 write dword 166 2 9 1 Description 166 2 9 2 Arguments 166 2 9 3 T 166 2 9 4 166 2 10 read dword 167 2 10 1 Ip einn 167 2 10 2 t 167 2 10 3 Return Values 2 10 4 Notes 167 167 2 11 pci rdwr 168 2 11 1 168 2 11 2 Pirat 168 2 11 3 ReturnValues 168 2 11 4 NOES 169 242 2 12 1 2 12 2 PAP c 170 2 12 3 COGIT ND 170 2 12 4 171 2 12 5 Dernived P nctiolis e ciae tidie ta 172 List of Figures Figure T DN6000 amp 105C EOGIC Emulation Boatd 7 Figure 2 Default Jumper Setup Figure 3 DN6000K10SC Boa
76. 728 1 128 P3N85 5 35 IP8 128 IST HDRA95 13 27 1 129 No Connect 8 129 U13 E5 1 130 P3N84 5 37 IP8 130 IST HDRA96 U13 E34 DN6000K 10SC User Guide www dinigroup com 148 BOARD HARDWARE Daughter Card Connections DN26000K10SC IO Connections Test Signal Name Connector Test Signal Name FPGA Pin Header 1131 P3N81 5 39 IP8 131 IST HDRA97 U13 E33 1 132 P3N80 5 41 IP8 132 IST HDRA98 U13 E32 1 133 P3N79 2 3 8 133 IST HDRA99 U13 E31 1134 P3N78 J24 IP8 134 IST HDRA100 U13 F28 1135 P3N73 2 6 8 135 HDRA101 013 27 1136 72 p8 136 IST HDRA102 U13 H26 1137 2 33 8 137 IST HDRA103 1013 626 1 138 P3N70 2 34 8 138 IST HDRA104 U13 H25 1 139 P3N65 5 43 IP8 139 IST HDRA105 U13 G25 1140 Connect P8 140 U13 E5 1141 P3N64 5 45 8 141 TST_HDRA106 13 25 1 142 P3N61 5 47 8 142 IST HDRA107 U13 K24 1 143 P3N60 5 49 8 143 IST HDRA108 U13 J24 1 144 P3N59 6 1 8 144 HDRA109 U13 F26 1 145 P3N58 6 3 8 145 HDRA110 U13 E26 1146 53 6 5 IP8 146 IST HDRA111 U13 D30 1 0447 P3N52 6 7 8 147 IST HDRA112 1013 029 1148 5 2 17 8 148 TST_HDRA113 U13 K23 1 149 50 2 18 8 149 IST HDRA114 013 723 1150 P3N45 6 9 8 150 IST HDRA115 U13 H22 1151 Connect 8 151 U13 E5 1 152 P3N44 6 11 8 152 IST HDRA116 U13
77. 8 TST_HDRAT37 TST HDRA52 69 169 TST HDRA132 TST_HDRA53 70 170 TST HDRA133 TST HDRA54 72 171 HDRA134 TST 55 72 172 HDRA135 TST_HDRAS6 73 L173 GND TST_HDRA5S7 74 7 174 TST_HDRATS6 TST HDRA58 75 175 HDHA137 HDRA59 76 176 HDHA138 GND 7127 177 HDHA139 TST_HDRAGO 78 178 HDHA140 TST_HDRAG1 79 179 TST HDRA62 80 180 TST TST HDRA63 81 181 HDHA143 TST 64 82 182 TST_HDRAT44 TST HDRA65 83 188 145 HDRA66 84 184 GND TST HDRA67 85 185 TST HDHA146 TST HDRA68 86 186 TST HDRA147 HDRA69 8717 187 HDHA148 GND 88 188 HDHA149 TST_HDRA70 89 189 5 _ 50 HDRATT 90 190 5 HDRAIBi TST HDRA72 91 191 _TST_HDRAT52 TST HDRA73 92 i92 y T 5V 93 TST HDRA74 94 194 x TST_HDRA75 95 195 GND TST_HDRA76 96 7 196 x TST_HDRA77 97 197 x TST_HDRA78 98 198 x GND 99 MEL RO 12V 100 22005 E 203 201 204 54 202 205 200 DN6000K10SC User Guide www dinigroup com 136 BOARD HARDWARE Figure 64 Test Header 12 1 1 Test Header Connector Micropax connector 200 pin is used as a standard interface to all the Dini Group logic emulation boards This connector has a specified current rating of 0 5
78. 88B8 bytes Debug Options 62 Clear Status Flashi gt gt Main Menu Q gt Quit PCI BASE ADDRESS 8000008 1 20000088 Please select option Figure 16 Flash Menu The possible Flash Menu options and their descriptions are listed below Flash Display Opt 1 2 Displays Flash Memory content Flash Erase amp Program Test tests 0x10000 bytes Opt 3 4 DN6000K 10SC User Guide ww w dinigroup com 39 INTRODUCTION TO THE SOFTWARE TOOLS Erase and Test the first 0x10000 bytes of the flash Flash Erase amp Program Test tests entire flash bootblock Opt 5 6 Erase and Test the entire flash including boot block this test takes approximately 5 minutes Flash Erase 0x10000 bytes Opt 7 8 Erase the first 0x10000 bytes of the flash Clear Status Opt G H Clear error status bits in case any errors occurred 1 1 6 Daughter Board Menu Upon entering the Daughter Board Menu from the Main Menu AETEST will output a screen similar to the one shown in Figure 17 Command Prompt aetest_wdm exe Daughter Board Menu 1 DN3888K18SD with cables to test connections 2 DN3888K18SD without cables to test for shorts M gt Main Menu Please select option Figure 17 Daughter Board Menu The possible Daughter Board Menu options and a description can be found in Table 4 Table 4 Daughter Board Options Function Name Description DN3000K10SD w cables The
79. 89 U13 AG25 PCI_AD35 P2 B89 U13 AL27 PCI_AD36 P2 A88 U13 AH25 PCI AD37 P2 B87 U13 AJ24 PCI AD38 P2 A86 U13 AE24 PCI AD39 P2 B86 U13 AK24 PCI AD40 P2 A85 U13 AF24 PCI AD41 P2 B84 U13 AL24 PCI AD42 P2 A83 U13 AE22 PCI AD43 P2 B83 U13 AM24 PCI AD44 P2 A82 U13 AF22 PCI_AD45 P2 B81 U13 AL23 PCI_AD46 P2 A80 U13 AG22 PCI_AD47 P2 B80 U13 AJ22 PCI_AD48 2 79 U13 AH22 PCI_AD49 P2 B78 WITS AK 22 PCI_AD50 P2 A77 U13 AB21 PCI AD51 P2 B77 U13 AL22 PCI_AD52 P2 A76 U13 AF21 PCI_AD53 P2 B75 U13 AM22 PCI_AD54 P2 A74 U13 AG21 PCI AD55 P2 B74 U13 AJ21 PCI AD56 P2 A73 1713 21 PCI AD57 P2 B72 U13 AK21 PCI AD58 P2 A71 U13 AE20 PCI_AD59 DN6000K10SC User Guide P2 B71 Www dinigroup com U13 AL21 BOARD HARDWARE Signal Name Connector FPGA Pin PCI AD60 P2 A70 U13 AF20 PCI AD61 2 69 U13 AM21 PCI AD62 P2 A68 U13 AE19 PCI_AD63 P2 B68 U13 AJ20 PCI CBENO P2 A52 U13 AE17 PCI_CBEN1 P2 B44 U13 AM14 PCI_CBEN2 P2 B33 U13 AK13 PCI_CBEN3 P2 B26 U13 AK11 PCI_CBEN4 P2 B66 U13 AL20 PCI_CBEN5 P2 A65 13 19 PCI_CBEN6 P2 B65 13 AH19 PCI_CBEN7
80. A SMA f 7 gt gt a E 50 8 9 n 50 2 EUR Y B1 51 51 63 63 B0 51 51 63 63 2 5V 2 5V SDR SRAM 18Mb 27 DDR SDRAM 256Mb 512K x 32 36 1 71 2 82 102 16M x 16 coe 102 102 95 93 Eus lO 2 5V XILINX VIRTEX2P O SSTL2 A XC2VP 0 40 50 F115 B6 75 93 B3 82 102 93 93 102 102 a SDR SRAM 18Mb VO SSTL2 1 43 pon wn ise 2 32 136 4 71 1 2 5 TSOP66 TQFP100 4 47 47 59 59 B5 47 47 59 59 AP PCI PCI 5 A User IO s 852 PCI PCI X I O 91 Rocket IO s 8 12 Figure 25 Bankout Diagram DN6000K 10SC User Guide www dinigroup com 68 BOARD HARDWARE 3 FPGA Configuration The Dini Group developed the SmartMedia Configuration Environment to address the need for a space efficient pre engineered high density configuration solution for systems with single or multiple FPGA s The technology is a groundbreaking in system programmable configuration solution that provides substantial savings in development effort and cost per bit over traditional PROM and embedded solutions for high capacity FPGA systems Virtex II Pro devices are configured by loading application specific configuration data into internal memory Configuration is carried out using a subset of the device pins some of which are dedicated while others can be reused as general purpose inputs and outputs
81. AMS Xilinx ISE 6 Accessories iMPACT 4 Select the Configure Devices option and proceed by clicking the NEXT button DN6000K 10SC User Guide www dinigroup com 42 PROGRAMMING CONFIGURING THE HARDWARE Operation Mode Selection x What do you want do first C Prepare Configuration Files C Load Configuration File cdf 5 Select the Boundary Scan Mode option and proceed by clicking the NEXT button OOO wantto configure device via amp Boundary Scan Mode Slave Serial Mode C SelectMAP Mode Desktop Configuration Mode lt Back Cancel Help 6 Select the Automatically connect to cable and identify Boundary Scan chain option and proceed by clicking the NEXT button DN6000K 10SC User Guide ww w dinigroup com 43 PROGRAMMING CONFIGURING THE HARDWARE Boundary Scan Mode Selection 7 Ifthe process was successful the following window will appear Boundary Scan Chain Contents Summary o L 8 Click OK button 9 Enter the location of the CPLD JED file in the window prompting the file name and click OK The following window would be displayed DN6000K 10SC User Guide www dinigroup com 44 PROGRAMMING CONFIGURING THE HARDWARE 8 untitled Configuration Mode iMPACT File Edit View Mode Operations Output Help D s E E Boundary Scan Slave SelectMAP Desktop Configuration Right click
82. ASH1 ADDR12 U13 D9 FLASH1 ADDR13 U13 C9 FLASH1_ADDR14 U13 D6 FLASH1 ADDR15 U13 D5 FLASH1 ADDR16 U13 F13 FLASH1_ADDR17 U13 J11 FLASH1_ADDR18 U13 D11 FLASH1_ADDR19 U13 C11 FLASH1 ADDR20 U13 E10 FLASH1 ADDR 21 U13 D10 FLASH1 DATAO 013 016 FLASH1 DATA1 U13 J15 FLASH1_DATA2 U13 F15 FLASH1_DATA3 U13 K14 FLASH1 DATA4 U13 H14 FLASH1 DATA5 U13 F14 FLASH1 6 U13 D14 FLASH1 U13 H13 FLASH1_DATA8 U13 K15 U U FLASH1_DATA9 13 G15 FLASH1_DATA10 13 D15 FLASH1_DATA11 013 14 FLASH1 DATA12 U13 G14 FLASH1 DATA13 U13 E14 FLASH1 DATA14 U13 C14 FLASH1 DATA15 U13 G13 FLASH1_CEN U13 F16 FLASH1_OEN U13 E16 FLASH1_WEN U13 G10 eG e Ge e e C G DN6000K 10SC User Guide www dinigroup com 98 BOARD HARDWARE Signal Name FPGA Pin FLASH1 WPN 1713 710 6 2 Synchronous SRAM The Synchronous SRAM U8 U9 memory components on the DN6000K10SC can accommodate up to 2M x 36 devices refer to Figure 46 The DN6000k10SC in its standard configuration is stuffed with two pipelined 512k x 36 SSRAM s SRAM1 0 37 52 SRAM1_DQa0 SRAM1_A1 36 53 SRAM1 DQa1 SRAM1 2 35 56 SRAM1 DQa2 SRAM1 34 57 SRAM1 DQa3 SRAM1 A4 33 58 SRAM1 DQa4 SRAM1_A5 32 59 SRAM1 DQa5 SRAM1 A6 100 62 SRAM1 DQa6 SRAM1 A7 99 63 1 DQa7 1 A8 82 68 SRAM1 DQbO SRAM1 9 81 69 SRAM1_DQb1 SRAM1_A1
83. Copyright 1985 2000 Microsoft Corp gt 4 aetest_wdm aetest_wdm gt aetest_wdm exe ymbolic link is pcillven 17df amp deu 1685 amp subsus 9B8ab5678 amp reu 47138 amp 1435fed5 amp 08 amp 3 781 0b1da27 6ac 7 4d1f 9eb8 1daf1b7e71315 ound device 41605 name DN6888K18SC UirtexII Pro Single FPGA board ompiled on Jan 20 2804 at 11 05 29 ress any key Figure 3 DN6000K10SC Board Recognition Upon recognition AETEST will notify the user which device was found In certain implementations the entire configuration space and the configuration of the BARs is sent to the screen immediate following the board recognition notification If AETEST does not recognize the DN6000K10SC AETEST will alert the user See Figute 4 DN6000K 10SC User Guide ww w dinigroup com 26 INTRODUCTION TO THE SOFTWARE TOOLS WINNT System32 cmd exe aetest wdm exe icrosoft Windows 20808 Version 5 08 2195 lt C gt Copyright 1985 2088 Microsoft Corp gt aetest Naetest aetest wdm exe o SP INTERFACE DEUICE available for this GUID instance ould not find open DnDeu device Figure 4 DN6000K10SC Not Found AETEST will still run however several DN6000K10SC specific options will not be available 1 1 2 Main Menu Upon powering up and after board recognition the user must merely press a key to enter the Main Menu shown in Figure 5 AWINNT System32 cmd exe aetest_wdm ASIC Emulator PCI
84. DDR FPGA 6A BAO DORSA DO DDR FPGA 6A BA DDR_6A_UDM DDR CLK1p DDR 6A LDM DDR CLK1n DDR 6A UDQS DDR FPGA 6A CKE DDR LDQ DDR FPGA 6A RASn DDR FPGA 6A CASn DDR FPGA 6 WEn DDR FPGA 6A DDR VREF 2 5V MT46V64M16 TSOP66 Figure 53 DDR SDRAM Connection 6 3 3 DDR SDRAM Clocking Refer to the DDR Clocking Section 6 3 4 DDR SDRAM Termination DDR SDRAM is based on the SSTL2 JEDEC Standard Stub Series Terminated Logic for 2 5V signaling standard The SSTL2 termination model used for DDR SDRAM has two types of termination e Class 1 o Also called 55112 1 Used for unidirectional signaling Control signals Class 2 Also called 55112 II O Used for bi directional signaling Data signals DN6000K10SC User Guide www dinigroup com 110 BOARD HARDWARE Both Class 1 and Class 2 are based on a 50Q controlled impedance environment and termination to VTT a 1 25V power supply SSTL2 Class 1 termination is used for unidirectional signaling such as control signals It is based on a 50Q controlled impedance driver a 50Q controlled impedance transmission line and a 50Q parallel termination to VTT at the receiver Figure 54 shows a basic SSTL2 Class 1 circuit The driver is brought to 50 by the addition of a 25 series resistor immediately adjacent to the driver implemented using DCI thus no need for an external component Viz 0 5 X Figure 54 SSTL2 Class 1 Termination SSTL
85. DWARE The Intel Advanced Boot Block Flash Memory C3 device supports read array mode operations at various IO voltages 1 8V and 3V and erase and program operations at or 12V VPP On the DN6000K10SC VPP is 3 3V The DN6000K10SC interfaces to the FLASH at 2 5V levels This family of devices is capable of fast programming at 12V not utilized on the DN6000K108C The device features the following e Enhanced blocking for easy segmentation of code and data or additional design flexibility e Program Suspend to Read command e VCCQ input of 1 65V 2 5V or 2 7V 3 6V on all I Os e Maximum program and erase time specification for improved data storage For more information on this part please refer to the Intel P N TE28F640C3TC80 datasheet 6 1 1 FLASH Connection to the FPGA The FLASH memory components are connected to the FPGA on Bank 1 as listed in Table 21 The VCCO of the IO banks are connected to 2 5V Table 21 Connection between FPGA and FLASH Signal Name FPGA Pin FLASH1_ADDRO U13 G16 FLASH1 ADDR1 U13 E13 FLASH1 ADDR2 013 013 FLASH1 ADDR3 U13 C15 FLASH1 ADDR4 U13 K12 FLASH1 ADDR5 11312 FLASH1_ADDR6 U13 D12 C DG C FLASH1 ADDR7 U13 K 11 FLASH1 ADDRS8 U13 H9 FLASH1 ADDR9 U13 G9 FLASH1_ADDR10 U13 F9 FLASH1_ADDR11 U13 E9 DN6000K 10SC User Guide www dinigroup com 97 BOARD HARDWARE Signal Name FPGA Pin FL
86. DWARE active mode The DN3000K10SD has separate enable direction signals for each driver ls I ac E TE e LFES Coe 8L LIL IL 1 LI omn Rent hn 621 5 5 er E 35 3 2250 s i ooze 89 amp 2 z 4 e FIT Pp LET D nit nn m a a e a Figure 68 Assembly drawing for the DN3000K10SD NOTE Signals P4NX7 and P4NX6 are also used for direction select and output enable on U2 and U3 respectively 12 2 1 Daughter Card LED s The LED s act as visual indicators representing the presence of active power sources D1 LED indicating 3 3 V present e D2 LED indicating 5 0 V present D3 LED indicating 12 V present Under normal operating conditions all LED s should be ON DN6000K10SC User Guide Www dinigroup com 141 BOARD HARDWARE 12 2 2 Power Supply A linear power supply U4 is present to provide level shift translation functions when the board is populated with passive bus switches Resistors R10 and R11 can be used to select alternate voltage sources 5V or 3 3V respectively When used U4 must be removed in order to prevent contention The power supplies is rated as follows e 5 V power supply is rated for 1 A 3 3 V power supply is rated for 1 A 1 5 V power supply is rated for 1 A 12 V power supply is rated for 0 5 e 2 power supply is rated for 0 5 A NOTE N
87. Debug and Trace 117 CPU Trace 119 CPU Trace Connector 119 Debug modes 117 External Debug Resources 117 Resources 117 Trace Debug connection to FPGA 120 D Daughter Card 138 Buffered IO 143 Connection to FPGA through Headers 144 External Power Connector 142 IO 143 LEDs 141 LVDS IO 143 Power Supply 142 DDR Clocking 88 Methodology 89 DDR SDRAM Clocking 110 Configuration 109 FPGA Connection 112 Operation 109 Termination 110 112 Termination Class 1 110 Termination Class 2 110 Dini Group Web Site 2 DN6000K10SC User Guide www dinigroup com DN6000k10SC Configurable Clocking Scheme 66 CPU Debug and Trace Interfaces 67 DDR SDRAM 67 Flash 67 Functionality 66 Logic Slices 67 MGT 67 Multiplier Blocks 68 PowerPC Processor 67 SelectI O 67 SMA Interface 67 Test Header 67 Virtex II Pro Options 66 E Emulation Kit Features 6 ATAVRISP kit 8 Coax loop back cables 8 Daughter Card 8 DN6000K10SC development board 7 Documentation Reference CD 8 FlashPath Adapter 7 IDC 10 pin to DB 9 pin adaptor cable 7 JTAG cable 8 Jumpers 7 RS232 Serial cable 7 SmartMedia 7 Xilinx ISE software 8 ESD 6 F FLASH Pin Layout 97 FPGA Bankout 68 Configuring using SelectMAP 52 CPLD 71 Features 16 Implementation 67 MCU 69 RS232 Interface 70 Virtex II Pro 16 FPGA Configuration 69 Atmel ATmega128L 69 CPLD Function 71 MCU Functions 69 APPENDIX MCU Prog
88. F22 1 153 P3N41 J6 13 8 153 IST HDRA117 U13 E22 1 154 P3NA40 J6 15 8 154 IST HDRA118 U13 E25 1155 JDP3N57 6 17 8 155 IST 119 U13 D25 1 56 P3N36 6 19 8 156 IST HDRA120 1013 023 1 157 P3N33 16 21 8 157 IST HDRA121 U13 D24 DN6000K10SC User Guide www dinigroup com 149 BOARD HARDWARE Daughter Card Connections DN6000K10SC IO Connections Test Signal Name Connector Test Signal Name FPGA Pin Header 1 158 P3N32 6 23 8 158 IST HDRA122 U13 C24 1 159 P3N31 2 44 8 159 IST HDRA123 U13 F17 1 160 P3N30 2 45 8 160 IST HDRA124 1013 617 1161 P3N25 6 25 IP8 161 _ 125 U13 K17 1 162 Connect P8 162 GND U13 E5 1163 P3N24 6 27 8 163 IST HDRA126 1013 117 1 164 P3N21 6 29 8 164 IST HDRA127 U13 H16 1 165 P3N20 J6 31 IP8 165 TST_HDRA128 13 16 1166 P3N17 16 33 IP8 166 IST HDRA129 U13 K16 1167 P3N16 J6 35 IP8 167 IST HDRA130 U13 E2 1 68 P3N13 6 37 8 168 IST HDRA131 U13J2 1 469 P3N12 16 39 8 169 HDRA132 013 12 1 470 P3N11 2 47 8 170 IST HDRA133 U13 M1 1171 P3N10 2 48 8 171 HDRA134 1013 4 1 472 5 6 41 8 172 IST HDRA135 013 011 1 173 Connect P8 173 GND U13 E5 1 174 P3N4 6 43 8 174 IST HDRA136 913 10 1 475 6 45 8 175 HDRA137 U13 R2 1 176 6 47 IP8 176 IST HDRA138 013 010 1 177 P4N25 7 1
89. FPGA outputs a signal to the Daughter Board where it is sent driven back to the FPGA The data is compared for correctness This is repeated for all test header signals DN6000K10SC User Guide www dinigroup com 40 INTRODUCTION TO THE SOFTWARE TOOLS Function Name Desctiption DN3000K10SD w o cables All IO signals on the DN6000K10SC are driven to ground Then the option performs a walking 1s test for all of the test header signals test checks for shorts on the DN6000K10SC 1 2 GNU Tools GNU software is used to develop software for the Virtex II Pro family of FPGAs This includes the GNU C compiler GCC the GNU binary utilities binutils the GNU debugger GDB and the GNU make program From the GNU Project website http www gnu otg The GNU Project was launched in 1984 to develop a complete Unix like operating system which is free software the GNU system GNU is a recursive acronym for GNU s Not Unix it is pronounced guh NEW Variants of the GNU operating system that use the Linux kernel are now widely used though these systems are often referred to as Linux they ate more accurately called GNU Linux systems As a prerequisite for the development of the GNU system many different software packages compilers assemblers linkers debuggers libraries and other tools had to be programmed 2 Getting More Information 2 1 Printed Documentation The printed documentation as mentioned pr
90. G SRAM2_DQPC U13 AL1 SRAM2_DQPD U13 AD1 SRAM2_GWN U13 W8 SRAM2_LBON U13 AD2 SRAM2_OEN U13 W6 SRAM2 ZZ DN6000K10SC User Guide U13 AA6 Www dinigroup com 108 BOARD HARDWARE 6 3 DDR SDRAM Double Data Rate DDR SDRAM represents an enhancement to the traditional SDRAM Instead of data and control signals operating at the same frequency data operates at twice the clock frequency while address and control operate at the base clock frequency In other words the data is written or read from the part on every clock transition or twice per clock cycle This effectively doubles the throughput of the memoty device The trade off for such an improvement in throughput is increased complexity in interface logic to the DDR memoty as well as increased complexity in routing the DDR signals on the printed circuit board Additionally this memory has the same latencies as standard SDRAM so that while the data transfers are twice as fast the latencies associated with DDR SDRAM are on par with standard SDRAM 6 3 1 Basics of DDR Operation DDR SDRAM provides data capture at a rate of twice the clock frequency Therefore DDR SDRAM with a clock frequency of 100 MHz has a peak data transfer rate of 200 MHz or 6 4 Gigabits per second for a 16 bit interface In order to maintain high speed signal integrity and stringent timing goals a bi directional data strobe is
91. HyperTerminal Interactive Configuration Menu Options e 8 Sanity Check Command Line Options 9 FPGA Configuration Modes b b b b b b b b b b b b Tab b b b b b b b b b b b b Hd o Coe fo oo e e e e e 19 Connections between FPGA and 5 Connector CLK le 20 PPC Reset e 21 Connection between FPGA and FLASH e 22 Connection between FPGA and SRAM s e 23 Connection between FPGA and DDR SDRAM e 24 Connections between FPGA and SMA Connector 25 RocketIO e 26 CPU Debug connection to FPGA e 27 Combined CPU Trace Debug connection to FPGA le 28 GPIO LED s e 29 FPGA GPIO LED s e 30 PCI to FPGA Connections e 31 Present Signal Definition e 32 M66EN and PCIXCAP Encoding e 33 Voltage Indicators e 34 External Power Connections 35 Connection between FPGA and the Daughter Card Headers Table 36 bar write byte Arguments Table 37 bar write word Arguments Table 38 bar write dword Arguments Table 39 bar read byte Arguments Table 40 bar read word Arguments Table 41 read dword Arguments Table 42 dma buffer allocate Arguments Table 43 buffer free Arguments Table 44 write dword Arguments Table 45 read dword Arguments Table 46 pci rdwr Arguments Table 47 DeviceIloControl Arguments
92. IST HDRA CL 1 102 MBCK1 2 27 8 102 U13 AL18 1 103 Connect 8 103 1 5V U13 L11 DN6000K 10SC User Guide www dinigroup com 147 BOARD HARDWARE Daughter Card Connections DN6000K10SC IO Connections Test Signal Name Connector Test Signal Name FPGA Pin Header 1 104 MBCKO 2 28 8 104 GND U13 E5 1 105 Connect P8 105 3 3V No Pin 1 106 MBCK6 5 9 P8 106 DCLK1 No Pin 1107 Connect P8 107 GND U13 E5 1 108 5 7 8 108 U13 E5 1 1009 Connect P8 100 GND U13 E5 1110 Connect P8 110 U13 E5 1111 P2N5 5 15 IP8 111 IST 79 013 729 1 112 234 J5 17 P8 112 IST HDRA80 U13 G34 1113 P2NX11 J2 2 8 113 IST HDRA81 U13 G33 1 114 P2NX10 J2 1 IP8 114 IST HDRA82 U13 H30 1 115 P2NX9 5 19 8 115 IST HDRA83 U13 H29 1116 P2NX8 5 21 IP8 116 HDRA84 1013 126 1117 P2NX3 5 23 8 117 IST HDRA85 U13 L25 1 118 Connect 8 118 U13 E5 1 119 P2NX2 5 25 IP8 119 HDRA86 013 634 1120 P3NX11 2 29 8 120 IST HDRAS87 U13 F33 1 121 P3NX10 2 30 8 121 IST 88 013 630 1 122 P3NX7 2 31 IP8 122 IST HDRA89 1013 629 1 123 P3NX6 2 32 8 123 HDRA90 013 632 1 124 P3NX3 5 27 IP8 124 _ 91 U13 G31 1 125 P3NX2 5 29 8 125 IST HDRA92 U13 F31 1 126 P3NX1 5 31 8 126 IST HDRA93 113 230 1 127 P3NXO 5 33 8 127 IST HDRA94 013
93. JTAG chain 3 4 1 FPGA JTAG Connector Figure 30 shows P1 the JTAG connector used to download the configuration files to the FPGA The FPGA JTAG can be used for RTL source debuggers such as ChipScope and Synplicity Identify It is not necessary to configure the FPGA via JTAG to utilized ChipScope or Identify cFPGA_CCLK TCK cFPGA_DONE TDO cFPGA PROGn TMS cFPGA INITn cFPGA DIN TDI Figure 30 FPGA JTAG Connector 3 4 2 FPGA JTAG connection to CPLD Table 12 shows the connection between the FPGA JTAG connector and the CPLD DN6000K10SC User Guide www dinigroup com 77 BOARD HARDWARE Table 12 FPGA JTAG connection to CPLD Signal Name Connector FPGA_CCLK TCK DONE TDO P1 3 FPGA PROGn TMS PLS FPGA_INITn DIN TDI P1 9 4 Clock Generation 4 1 Clock Methodology The DN6000K10SC Logic Emulation board has a flexible and configurable clocking scheme Figure 31 is a block diagram showing the clocking resources and connections CLOCK DISTRIBUTION ASIC EMULATION BOARD DN6000k10SC RocketlO CLKOp osc DDR CLKOn EG212CA User GLK DDR CLKp DDR nonu DCLK3 x Aera FPGA GCLKOUT RoboClock osc cLocKa PLL2B CYB944V ECLK 0 3 y 5 DDR DDR CLKp ure oor
94. LLOCKn B40 LOCK 3 34 AD R84 5 1K 6 PERRn uc Bi PERR SMBCLK BR ETE PCI_SERRn Bag 23V SMBDAT PCI SERRn B43 SERR GND HMs 1 PCI CBEnt B44 3 3 PAR Add PCI ADiS POLPAR PCI 14 pas 015 A45 2 Bag 014 3 3 A46 PCI 013 PCI AD12 AD13 447 PCL ADI PCI 012 PCI M66EN B49 ADIO GND Fagg PCI AD9 Bon NESEN ADOS 550 PCI EA CN 2810 PCI 7 B53 008 CIBEO A53 Ve Vs B54 007 3 3 A54 PCI 06 PCI ADS B55 19 3V 006 555 PCI_AD4 B56 ADOS 004 6 57 003 GND A57 AD2 1 Beg GND 002 PCI AD1 B58 58 PCLADO Vio 3 B59 ADOI ADOD Vio 3 PCI ACK64n ECL B60 ACK64 489 POI PCI REQ64n t B62 5V 5 Taga 1 45V 45 64 bit Keyway RSVD GND PCI_CBEn6 GND PELCBERS PCI_CBEn4 PCI 64 lt gt PAR64 Pg6 CI64M EDGE PCI AD 0 63 Pg6 Figure 60 PCI Edge Connector 10 1 3 Connection between the PCI connector and the FPGA Table 30 shows the connection between the PCI Edge Connector and the FPGA The VCCO of the banks are connected to 3 0V Table 30 PCI to FPGA Connections Signal Name Connector FPGA Pin
95. Location DNsoo0106 CADN5000106 Selectthe type of Top Level module for the Project Top Level Module Type EDIF Y Cancel Help Figure 18 New Project Screen Shot Select the input files for the project refer to Figure 19 Selectthe Input File for the Project Input Design rce fpgacode FPGA_SYNTH rev_1 50001 06 edf Copy Input Design to the Project directory Select the Constraint File for the Project Constraint File Budice Jack DiniGroup 50001 06 Source fpgacc Copy Constraint file to the Project directory Back Next gt Cancel Help Figure 19 Input File Select the device and the design flow for the project The user must specify a project name and location The correct property values must be selected refer to Figure 20 DN6000K 10SC User Guide ww w dinigroup com 53 PROGRAMMING CONFIGURING THE HARDWARE Figure 20 New Project Dialog Box The Project Navigator will create a new project with the required files The DINI Group prefers to use Synplicitys Synplify for synthesis which is recommended for the user also Consequently edif files are used in the design flow described here Selecting the edif file in the Module View window the user s Project Navigator box should resemble Figure 21 DN6000K 10SC User Guide www dinigroup com 54 PROGRAMMING CONFIGURING THE HARDWARE 16 DN5000106 npl W
96. M2 ADVN U13 W3 SRAM2 BWAN U13 W10 SRAM2 BWBN U13 W11 SRAM2 BWCN 15 772 SRAM2 BWDN U13 V4 SRAM2 BWEN U13 W7 SRAM2 CE2N R183 2 SRAM2_CE2 R190 2 SRAM2_CEN U13 V6 SRAM2_DQA0 U13 AB8 SRAM2 DQA1 U13 AB9 SRAM2_DQA2 U13 AB10 SRAM2 DQA3 13 AA1 SRAM2_DQA4 13 2 SRAM2_DQA5 13 SRAM2 DQA6 13 AA4 SRAM2_DQA7 13 5 SRAM2 DQBO 13 AA7 SRAM2 DQB1 13 AA8 SRAM2 DQB2 U U U U U U U U 13 9 SRAM2 DQB3 U13 AA10 SRAM2_DQB4 Ut5 Y1 SRAM2 DQB5 U13 Y2 SRAM2_DQB6 U13 Y4 SRAM2_DQB7 U13 Y6 c cle cie Ga ere eee eb eje ee SRAM2_DQC0 DN6000K10SC User Guide U13 AL2 Www dinigroup com 107 BOARD HARDWARE Signal Name FPGA Pin SRAM2_DQC1 U13 AK4 c SRAM2 DQC2 U13 A 7 SRAM2 DQC3 U13 A 8 SRAM2_DQC4 13 AH5 SRAM2 DQC5 13 AH6 C LG CL GG SRAM2 DQC6 13 AH8 SRAM2 13 2 SRAM2_DQD0 13 AG7 SRAM2_DQD1 13 AF2 SRAM2_DQD2 13 AF3 SRAM2_DQD3 13 AF4 SRAM2_DQD4 13 AE1 SRAM2_DQD5 13 AE2 SRAM2_DQD6 13 4 SRAM2 DQD7 13 AEB5 SRAM2_DQPA e 15 SRAM2_DQPB U13 Y7 Glare e ee G
97. Memory Test 37 DEVICE_ID 12 26 Display all PCI devices 29 Display Vendor Device ID 29 Flash amp Program Test 40 Flash Display 39 Flash Menu 39 Flash Test 25 FPGA Revision Test 25 Getting Started 26 Installation 24 154 Memory Menu 13 28 Memory Test 25 Memory Tests On FPGA Block Memory 38 Operating System 12 PCI Menu 28 PCI Test 25 Read Config DWORD 30 Read DWORD 32 www dinigroup com Read FPGA Revision 28 Read Write DWORD 25 Recognize Board 25 Save BAR Configuration 31 Set PCI Device Number 25 28 Set PCI Function Number 29 SSRAM Memory Test 37 Tests 25 Using 24 Vendor Device ID Test 25 VENDOR_ID 13 26 Write Config DWORD 30 Write DWORD 32 Write Read DWORD 33 ASIC 16 Atmel AVR Studio 4 48 B Bitstream Encryption 64 DES 64 Boundary Scan 77 Clock 78 Clocking Methodology 89 Connection to FPGA 90 Connections between FPGA and DDR PLL Clock Buffer 92 Customizing the Oscillators 88 Default Failsafe Output 87 Digi Key 88 External 81 94 Jumper Header 87 Jumpers 83 173 APPENDIX Methodology 78 PLL Buffer 82 Reference Clocks 92 Roboclock 79 Rocket IO 91 Clock Source Selections 82 Conventions 2 Online Document 3 Typographical 2 CPLD Bitstream Encryption 64 Design Notes 72 Programming 42 Programming Connector 72 Sanity Check 58 Verbose Level 57 Verbose Level 0 57 Verbose Level 1 57 Verbose Level 2 58 CPU
98. OCK 2 Output Phase Function Select Controls the phase function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 3 in the datasheet ROBOCLOCK 2 Output Divider Function Select Controls the divider function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 4 in the datasheet DN6000K10SC User Guide www dinigroup com 86 BOARD HARDWARE Signal Name Description Connector EDS1 ROBOCLOCK 2 Output Divider Function JP8 B10 Select Controls the divider function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 4 in the datasheet 4 5 2 Clock Source J umper Header Figure 36 shows JP6 JP7 and JP8 the RoboClock configuration jumpers FBDS11 CON10X3 CON10X3 REFSEL1 REFSEL2 MODE1 MODE2 FBDIS1 FBDIS2 RBEFO RBEF1 EDSO EDS1 CON10X3 CON10X3 CON10X3 Figure 36 RoboClock Configuration Jumpers 4 5 3 Useful Notes and Hints The RoboClock consistently outputs 32 5MHz signals in cases of improper settings or unacceptable clock inputs This was observed when the CY7B994V part was DN6000K10SC User Guide www dinigroup com 87 BOARD HARDWARE operating at a nominal frequency o of 36 4MHz with FS set LOW Identical clocks were sent to PLL2B and PLL2BN For the CY7B994V part the operating frequency can reach up to 200 MHz Howevet the maximum output frequency is 185MHz This means when 185 MHz lt fNOM lt 200MHz the output divider must be set to
99. P8 A10 B10 ROBOCLOCK Z2 Output Divider Function Select Conttols the divider function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 4 in the datasheet 3 3 Powering ON the DN6000K 10SC This section describes what is necessary to power up the DN6000K10SC DN6000K 10SC User Guide ww w dinigroup com 11 ABOUT THIS MANUAL 1 Install the DN6000K10SC in the test PC Note The PCI interface is keyed so that it is not possible to mistakenly plug the board into a 5V PCI slot Do NOT grind out the key in the PCI host slot and do NOT modify the DN6000K10SC to get it to fit into the slot The DINI Group offers a PCI Extender P N DNPCIEXT S3 that can be used to interface the DN6000K10SC to the PC in case no 3 3V slots are available Please refer to the Dini Group website for more information 2 Install the SmartMedia catd containing the PCI reference design into the DN6000K10SC WARNING Do not use a separate ATX power supply with the board when itis plugged into a PCI slot 3 Powet ON the test PC and allow booting in DOS mode Note The FPGA programming will commence as soon as the DN6000K10SC is powered on if the SmartMedia card contains the necessary configuration file and bit files In general the FPGA will be programmed prior to the PCI devices being configured However some computers have a FastBoot or QuickBoot feature which speeds up the booting process of the PC These features are incomp
100. RAM1 DQD6 U13 L1 c ci c ci c c c c e Hue ee c eje ele mI DN6000K 10SC User Guide www dinigroup com 105 BOARD HARDWARE Signal Name FPGA Pin SSRAM SRAMI DQD7 U13 L3 U8 29 SRAM1_DQPA U13 N8 U8 51 SRAM1_DQPB U13 R10 U8 80 SRAM1_DQPC U13 B1 U8 1 SRAMI DQPD U13 L4 U8 30 SRAMI GWN U13 T9 U8 88 SRAM1_LBON U13 L5 U8 31 SRAM1 OEN U13 17 U8 86 SRAM1_ZZ U13 P8 U8 64 SRAM2_A0 U13 AC1 09 37 SRAM2 A1 U13 AD8 U9 36 SRAM2 A2 U13 AD7 U9 35 SRAM2 A3 U13 AD6 U9 34 SRAM2 A4 U13 AD5 119 33 SRAM2 A5 U13 AD4 U9 32 SRAM2 A6 U13 V8 U9 100 SRAM2 A7 U13 V7 19 99 SRAM2 8 U13 Y10 U9 82 SRAM2 A9 0713 79 09 81 SRAM2 A10 U13 AC9 U9 44 SRAM2 A11 U13 AC10 U9 45 SRAM2 A12 U13 AB2 U9 46 SRAM2 A13 U13 AB3 U9 47 SRAM2 A14 U13 AB4 U9 48 SRAM2 A15 U13 AB5 U9 49 SRAM2 A16 U13 AB6 109 50 SRAM2 A17 U9 43 SRAM2 A18 U13 AC6 U9 42 SRAM2_A19 U13 AC4 U9 39 DN6000K10SC User Guide www dinigroup com 106 BOARD HARDWARE Signal Name FPGA Pin SRAM2 A20 U13 AC3 SRAM2_ADSCN U13 W5 SRAM2 ADSPN U13 W4 SRA
101. ROBOCLOCK j SWITCHING 433V 10 ose pe Not avaiable on the 2VP20 4921910 I BF Lock i INDICATORS voLraGE d Pwarsta MONITOR REEL UN Primary 32 64 Bit 33 66MHz PCI Bus 133MHz PCI X Bus i Dres 28i pam RESET PROGRAMMABLE CLOCK SOURCE 8 SWITCH Figure 24 DN6000K10SC Block Diagram 1 1 DN6000K10SC Functionality The components and interfaces featured on the DN6000K10SC includes 2VP20 30 40 50 Virtex II Pro FPGA Options 5 6 7 speed grades Flexible and Configurable Clocking Scheme DN6000K10SC User Guide www dinigroup com 4 66 BOARD HARDWARE e SmartMedia Configuration DDRSDRAM 32M x 16 options for 64M x 16 e Synchronous SRAM 512K x 32 36 options for 1M 2M x 36 e FLASH 4M x 16 e Primary 32 64 Bit 33 66MHz PCI Bus 133MHz PCI X Bus Four Multi Gigabit Transceiver MGT channels SMA e One User Clock SMA Interface differential e 200 Pin Test Header e CPU Debug and Trace Interfaces in Berg and Mictor connectors NOTE RocketIO interface speed is directly affected by the speed grade of the part Please refer to the Xilinx data sheet 2 Virtex4l Pro FPGA The Virtex II Pro FPGA is situated on the topside of the board For a detailed description of the capabilities of the Virtex II Pro FPGA refer to the datasheet on the Xilinx website 2 1 FPGA 2VP20 Facts The Virtex II Pro Platform FPGA o
102. RoboClock 1 U25 JP6 A3 B3 JP6 A4 B4 ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 3 amp 4 CCLK of outputs Refer to Table 4 in the datasheet ROBOCLOCK 71 Output Divider Function Select Controls the divider function of bank 3 amp 4 CCLK of outputs Refer to Table 4 in the datasheet JP6 A7 B7 ROBOCLOCK 71 Output Divider Function Select Conttols the divider function of bank 1 amp 1 DCLK of outputs Refer to Table 4 in the datasheet JP6 A7 B8 ROBOCLOCK 71 Output Divider Function Select Conttols the divider function of bank 1 amp 1 DCLK of outputs Refer to Table 4 in the datasheet JP7 A1 B1 ROBOCLOCK 1 Frequency Select This input must be set according to the nominal frequency fNOM Refer to Table 1 in the datasheet JP7 A4 B4 FBDS11 ROBOCLOCK 1 Feedback Divider Function Select These inputs determine the function of the QFAO and 1 outputs Refer to Table 4 in the datasheet ROBOCLOCK 2 Frequency Select This input must be set according to the nominal frequency f NOM Refer to Table 1 in the datasheet FBDS02 ROBOCLOCK 2 Feedback Divider Function Select These inputs determine the function of the QFAO and QFA1 outputs Refer to Table 4 in the datasheet DN6000K10SC User Guide Enable for Oscillator A X4 www dinigroup com 10 ABOUT THIS MANUAL Jumper Signal Description Installed
103. Signals SM REn SM WEn SM ALE SM CLE SM CEn SM RDYBUSYn e FPGA Configuration Serial SelectMap Data Bus FPGA D O 7 DN6000K 10SC User Guide www dinigroup com 71 BOARD HARDWARE Control Signals FPPGA BUSY FPGA_RD WRn FPGA_CSn FPGA DONE FPGA INITn FPGA PROGn Clock DCLK e FPGA Configuration JTAG JTAG Signals FPPGA TDI FPGA DONE TDO FPGA_TMS e SRAM Chip Select Generation Signal SRAM_CSn e FPGA Configuration MODE Select DipSwitch Signals FRGA_MSEL 0 3 e LED Indicators Signals CPLD_LEDn 0 3 3 2 1 CPLD Programming Connector A programming cable for the XC95288XV is shipped with the DN6000K10SC The CPLD programming header P5 as shown in Figure 28 is used to download the files to the CPLD using the XILINX JTAG cable 3 3V CPLD JTAG 3 3V R66 1K JTAG_CPLD_TCK JTAG CPLD JTAG CPLD TMS JTAG CPLD TDI Figure 28 CPLD Programming Header 3 2 2 Design Notes on the CPLD Oscillator X1 is a 48 MHz oscillator used to clock the CPLD This part is soldered down to the PWB and is not intended to be user configurable The 48 MHz is divided down to 8 MHz in the CPLD to provide the clock for the micro controller U3 The clock signal is labeled MCU CLK on the schematic The 48 MHz is used directly for the state machines in the CPLD for controlling the interface to the SmartMedia card The frequency o
104. System32 cmd exe aetest Weite Read BAR Memory BAR Memory BAR Memory bar memory bar memory memory test memory test memory test memory test full memory Main Menu 8000000 889880008 Please select option word count 0x108 top if an error occurs or isplay any errors that occur ais 3H71 854i 001 1612181941 40150 in the PCI reference design Press any key to exit test The test should complete successfully as _wdm exe Dword Same fiddress Fill Write Display range test address data bitwise test on FPGA block memory on SSRAM 1 on SSRAM 2 on DDR test Cincluding blockram gt 02 Quit PCI BASE ADDRESS 1 fagga 2 98808008 66688000 5 96690000 c n noy 0116218412041228251127212953181433313573771140014174 m 8 Congratulations You have now programmed the DN6000K10SC and successfully executed our AETEST utility to exercise various features of the DN6000K10SC DN6000K10SC User Guide ww w dinigroup com 15 INTRODUCTION TO VIRTEX II PRO AAND ISE Chapter Introduction to Virtex l Pro and ISE l Virtex4l Pro The Virtex II Pro FPGA solution is the most technically sophisticated silicon and softwate product development in the history of the programmable logic industry The goal was to revolutionize system architecture from the ground up To achieve that objective the best circuit engineers and system architects from IBM Mindspeed and Xilinx co dev
105. T33V TP16 T25V 9 4 Heatsink Fan The DN6000k10SC supports a heatsink fan The connector 15 10 The heatsink fan can be enabled or disabled by the Atmel microprocessor The default configuration is FAN ON Cooling Fan 9 5 PowerPC RS232 Monitor Ports The DN6000k10SC has RS232 ports P7 and You must put a UART in the FPGA for each of these ports if you wish to use them These two RS232 ports are intended for monitoring of PowerPC activity in the FPGA UART examples and PowerPC interface code be found on CDROM supplied with the DN6000k10SC See section 3 for the HyperTerminal parameters To convert the 10 pin header to a DB9 RS232 connector the same adapter that is used on works fine These very cheap contact us if your want a few DN6000K10SC User Guide www dinigroup com 123 BOARD HARDWARE PPC1 RS232 Interface DCE 42 5V RS232 Port 1 014 P7 PPC_TXD1 7 21 RS232 TXD1 1 2 PPC TXD2 8 T1OUT 2g RS232_TXD2 3 4 PPC MON TeOUT rs 5 6 7N T3OUT 2 5 RXD1 13 18 RS232 RXD1 9 10 PPC HXD2 ROUT RAIN LPP EXUZ 2 PUN IS RS232 HXD2 ah ND 7 PEE RS232 Port 2 or 2 5V R105 10K 11 SWOUT SWIN 15 GND 24 P6 C264 __0 1uF SHDN 1 2 1 23 4 vec 5 461 14 7 8 2 9 10 X 2
106. THE DINI GROUP LOGIC Emulation Source User Guide DN6GOOOK10SC LOGIC EMULATION SOURCE DN6000K 10SC User Manual Version 1 1 The Dini Group 1010 Peatl Street Suite 6 La Jolla CA92037 Phone 858 454 3419 Fax 858 454 1279 support dinigroup com www dinigroup com Table of Contents ABOUT THIS 1 1 MANUAL CONTENTS 4 2 ADDITIONAL RESOURCES 41 3 dfe CARE TO NS PERENNE E id leh 3 1 bonae Ci 22 Online Document 4 RELEVANT INFORMATION 5 seco ESAE eere LEE 4 GETTING STAR PED D mem C M 6 1 PRECAUTION TT 6 2 THE DN6000K10SC LOGIC EMULATION KIT t RR e eo O RUE NR EUR e E EORR AOR ha aE Ens 6 3 INSTALLATION INSTRUCTIONS 259 1p COR DARE HR EERATIAREXORNECDANARERENIE ERANT ERE Ee E EEE Eep taan E SEEK OAR ELTA 8 3 1 Jumper Setup 3 2 Jumper EIFE 9 3 934 Powering ON the DN6000KTOSC e a t S COM FO UO 11 4 PLAYING WITH YOUR DN6000K TOSC Shaan ease aaa inka GaGa eS ARR
107. Trace The DN6000K10SC board includes two CPU debugging interfaces the CPU Debug JP1 is a vertical header and the Combined CPU Trace and Debug J4 is a vertical mictor connector These connectors can be used in conjunction with third party tools or in some cases the Xilinx Parallel Cable IV to debug software as it runs on the processor The PowerPCTM 405 CPU core includes dedicated debug resources that support a vatiety of debug modes for debugging duting hardware and software development These debug resources include e Internal debug mode for use by ROM monitors and software debuggers e External debug mode for use by JTAG debuggers e Debug wait mode which allows the servicing of interrupts while the processor appears to be stopped Real time trace mode which supports event triggering for real time tracing Debug modes and events are controlled using debug registers in the processor The debug registers are accessed either through software running on the processor or through the JTAG port The debug modes events controls and interfaces provide a powerful combination of debug resources for hardware and software development tools The JTAG port interface supports the attachment of external debug tools such as the ChipScope Integrated Logic Analyzer a powerful tool providing logic analyzer DN6000K10SC User Guide www dinigroup com 117 BOARD HARDWARE capabilities for signals inside an FPGA without the need for expe
108. aaaaaa 4 Oxffffffff fill all of the memory bits 5 Data Addtess fill each DWORD with its address inverted DN6000K 10SC User Guide ww w dinigroup com 34 INTRODUCTION TO THE SOFTWARE TOOLS C WINNT System32 cmd exe aetest_wdm Input bar number 5 gt Input starting address Chex and 32 bit aligned 818800808 Input number of bytes Chex and divisible by 45 88 Fill with 8 address data 0 55555555 Uxffffffff data address Figure 11 BAR Memory Fill As in previous function descriptions Figure 11 shows an access of SSRAM 2 Address 0x200000 is used as the starting address and 0x80 bytes are filled Data pattern option 3 is used See option Bar Memory Display for a view of the results of this transaction Bar Memory Write Opt 5 Memory Write enables to user to write a DWORD s to PCI memory space All 4 gigabytes of memory space is accessible Figure 12 shows a sample transaction Once the option is chosen the user must input the BAR Number followed by the address within the specified BAR Then the user needs to input the number of DWORDs to be written in decimal The data to be written must be entered for each DWORD DN6000K10SC User Guide www dinigroup com 35 INTRODUCTION TO THE SOFTWARE TOOLS ICA WINNTSystem32 cmd exe aetest_wdm exe AR 8 ffset Dword aligned gt 8x801808828 umber of Dwords 1 nter Dword Data xabcdef45_ Fig
109. adequate DCM resources ate available a third DCM can be used for better timing margins This DCM is used to generate WCLK a phase shifted version of the system clock WCLK is used to clock data at the DDR IOB registers during a Write DN6000K10SC User Guide www dinigroup com 89 BOARD HARDWARE IBUFG SSTL2 I user clk user rst DCM1 CLKO CLK90 BUFG clk dk90 CLKIN CLK180 CLK270 CLKDV CLK2X LOCKED DCM_CLK 4 6 2 DCM2_RECAPTURE BUFG ddr OBUF SSTL2 ddr clkb OBUF SSTL2 clkdv 16 CLKO CLKIN CLK90 CLKFB CLK180 CLK270 CLKDV CLK2X LOCKED DCM RCLK PHASE SHIFT optional CLKO CLKIN CLK90 CLKFB CLK180 CLK270 CLKDV CLK2X LOCKED RST DCM WCLK PHASE SHIFT gt locked wclk x253 04 070502 Figure 37 DDR DCM Implementation Connections between FPGA and DDR PLL Clock Buffer The connection between the FPGA and the DDR PLL Clock Driver U20 consists of a SSTL 2 differential pair DDR PLLO can be used as a feedback reference clock input The connections are shown in Table 16 Table 16 Connection between FPGA and DDR PLL Clock Driver Signal Name FPGA Pin DDR PLL Clock Driver U20 DDR_CLKP U13 D18 20 13 DDR CLKN U13 E18 U20 14 DDR CLKOP U13 H18 0120 10 DDR CLKON DN6000K10SC User Guide www dinigroup com U13J18 U2
110. after configuration is complete SmartMedia is the primary means of configuring the FPGA on the DN6000K10SC board Configuration of FPGA is accomplished using either Serial SelectMAP or the JTAG interface The remainder of this section describes the functional blocks that entail the FPGA configuration environment 3 1 Micro Controller Unit MCU The Atmel ATmega128L U3 micro controller is used to control the configuration process The ATmega128L provides the following features 128K bytes of In System Programmable Flash with Read While Write capabilities 4K bytes EEPROM 4K bytes SRAM 53 general purpose I O lines 32 general purpose working registers Real Time Counter RTO four flexible Timer Counters with compare modes and PWM 2 USARTS a byte oriented Two wire Serial Interface an 8 channel 10 bit ADC with optional differential input stage with programmable gain programmable Watchdog Timer with Internal Oscillator an SPI serial port IEEE std 1149 1 compliant JTAG test interface also used for accessing the On chip Debug system and programming and six software selectable power saving modes The micro controller interfaces to the CPLD U5 via an 8 bit bus and the SmartMedia interfaces to the CPLD via an 8 bit bus The FPGA interfaces to the CPLD via the JTAG interface and an 8 bit bus used during Serial and SelectMap programming of the FPGA The amount of internal SRAM 4 Kbytes is not large enough to hold the FAT needed for SmartMedia
111. ame place of main txt of the bit file to be used for configuration as well as options for the configuration process However a user can put several files that follow the format for main txt on the SmartMedia card that contain different options for the configuration process By selecting the main menu option 4 the user can select a file from a list of files that should be used in place of main txt After selecting a new file to use in place of main txt the user should select Main Menu option 1 to configure the FPGA s according to this new file If the power is turned off or the reset button S1 is pressed the configuration file is changed back to the default main txt List files on This option prints out a list of all the files found on the SmartMedia SmartMedia catd Select FPGA to This option allows the user to select an FPGA to configure via program via JTAG JTAG Display Contents ofa This option allows the use to list the contents of any text file on TXT File the Smart Media card Selecting Option 2 results in the following menu to be displayed refer to Figure 23 DN5000106 HyperTerminal 9 x Ele Edit View Call Transfer Help oel 5 sees ENTER SELECTION 2 INTERACTIVE CONFIGURATION MENU 1 Select bit files to configure FPGA s 2 Set verbose level current level 2 3 Disable sanity check for bit files M Main menu ENTER SELECTION Connected 1 13 25
112. amps per contact See datasheet for more information P N 91294 003 The mating connector number is P N 91403 003 This connector can be difficult to get we stock them at our massive warehouse facility in San Diego 12 1 2 Test Header Pin Numbering Figure 65 indicates the pin numbering scheme used on the test headers DN6000K10SC User Guide www dinigroup com 137 BOARD HARDWARE Mounting Holes Figure 65 Test Header Pin Numbering 12 2 DN3000K 10SD Daughter Card The Dini Group manufactures a daughter DN3000K10SD that allows the user connection to the FPGA IO pins The daughter card has the following features e Buffered I O Passive and Active Bus Drivers Unbuffered I O DN6000K10SC User Guide Www dinigroup com 138 BOARD HARDWARE e Differential LVDS pairs Note Not available on DN6000K10SC Logic Emulation board e Headers for Test Points The daughter card contains headers that may be useful with certain types of oscilloscope probes or when wiring pins to prototype areas Figure 66 15 a block diagram of the daughter card DIFFERENTIAL P CONNECTOR BCLK1 lt ECLKI 4 MBCK6 DIFF CLOCK J8 J4 J5 J6 J7 50 PIN IDC HEADER NRUEFERED OO UOI J2 Ah DIFF PAIR
113. atible with the FPGA programming sequence of the DN6000K10SC as the FPGA may not be configured prior to PCI bus activity As a result the computer will not recognize the DN6000K10SC Workaround If the computer has FastBoot or QuickBoot or similar feature it should be disabled Otherwise a soft reset should be performed by simultaneously pressing the CTRL ALT DELETE keys after the computer has completed the Power On Self Test POST This will allow the DN6000K10SC enough time to configure the FPGA so that the computer will recognize the DN6000K10SC device 4 Playing with your DN6000K 10SC At this point the DN6000K10SC should be powered on with the PC booted in DOS mode The FPGA should also be programmed with the PCI reference design supplied by The Dini Group The ASIC Emulator Test Utility AETEST can now be used in DOS to verify the functionality of the DN6000K10SC DN6000K 10SC User Guide ww w dinigroup com 12 ABOUT THIS MANUAL 1 If the AETEST utility is not yet installed refer to Appendix A for installation instructions 2 Runthe AETEST utility appropriate for the Operating System AETESTDJ EXE for Windows 95 98 ME using DPMI AETEST98 EXE for Windows 98 ME using VxD driver AETEST_WDM EXE for Windows 2000 3 AETEST utility should now recognize the DN6000K10SC with the DEVICE ID of 0x1605 standard configuration 0x1606 with 2vp20 loses one of the DDR s
114. ce Figure 43 LVDS Reference Clock Oscillator Interface DCI Figure 44 Reset Topology Block Diagram Figure 45 FLASH Connection Figure 46 SSRAM Connection Figure 47 SSRAM Flow trough Figure 48 SSRAM Pipeline Figure 49 SSRAM ZBT Flow trough Figure 50 SSRAM ZBT Pipeline Figure 51 Syncburst and ZBT SSRAM Timing Figure 52 Clock Level Translation Figure 53 DDR SDRAM Connection es Figure 54 SSTL2 Class T Termitiation Figure 55 SSTL2 Class 2 Termination Figure 56 DDR VTT Termination Regulator Figure 57 CPU Debug Figure 58 Combined Trace Debug Connector Pinout Figure 59 VirtexII Pro PCI VCCO Regulator Figure 60 PCI Edge Connector Figure 61 M66EN and PCIXCAP Jumper Figure 62 ATX Power 1 Figure 63 External Power Connection Figure 64 Test Header Figure 65 Test Header Pin Numbering Figure 66 DN3000K10SD Daughter Card Block Diagram Figure 67 DN3000K10S Daughter Card Figure 68 Assembly drawing for the DN3000K10SD List of Tables Table 1 Jumper Description e 2 Main Menu Options e 3 PCI Menu Options le 4 Daughter Board e 5 S2 Dipswitch Configuration Settings 6 HyperTerminal Main Menu Options 7
115. char word 2 5 3 Return Values A successful function call will return zeto The word of data read during the access is placed in the variable location pointed to by data 2 5 4 Notes The source code for bar read word is portable to each of the operating systems intended for AETEST usage DN6000K 10SC User Guide ww w dinigroup com 162 APPENDIX 2 6 bar read dword read dwotrd is a high level function C function which is recommended for development by users of the DN6000K10SC 2 6 1 Description bar read dword allows users of the DN6000K10SC to read dword of data from any location in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 6 2 Arguments The arguments for bar_read_dword are shown in Table 41 They are listed in order Table 41 bat_tead_dword Arguments Argument Desctiption Possible Values unsigned long barnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 BAR5 5 unsigned long byte offset Address Number of bytes to Ox0 bytes in mem space offset data dword data Pointer to a dword of data for the 0 00000000 read operation 32 bits Itypedef unsigned char dword 2 6 3 Return Values A successful function call will return zeto The dword of data read during the access is placed in the variable location pointed to by data 2 6 4 Notes The
116. ck Buffer 90 4 7 Power PC PPC Clock s 4 7 1 Clocking Re 91 4 7 2 Connections between FPGA and DDR PLL Clock 91 4 6 Rocket IO Clocks eee tees 4 8 1 Clocking Methodology 4 8 2 Connections between FPGA and DDR PLL Clock Buffer z 4 8 3 92 4 9 External User Clock SMA RUIN RR MERERI 4 9 1 FPGA to SMA Connector ns RESET TOPOLOGY 5 1 DR 5 2 PPC Reset OAS SOREN RUAN OE ERIS oL HON ER 6 1 pum 6 1 1 FLASH Connection to the FPGA 6 2 Synchronous SRAM 6 2 1 SSRAM Configuration 6 2 2 SSRAM 6 2 3 SRAM Terminato MERE EAR ATEM 6 2 4 SSRAM Connection to FPGA 6 33 D DIAY D t VY BERRE X 109 6 3 1 Basics of DDR Operation cesson 109 6 3 2 DDR IBS KS nITAM EINE 109 6 3 3 DDR SDRAM Clockin terrre etre EE e 110 6 3 4 DDR SDRAM Termination 6 3 5 DDR SDRAM Power Supply 6 3 6 DDR SDRAM Connection to the FPGA 7 ROCKET IO TRANSCEIVERS ii RUEDA ER RARE p 115 7 1 SMA WO OU c mtDNA 116 7 1 1 FPGA to SMA Conn
117. ckRAM on the DN6000K10SC Memory Tests On FPGA Block Memory Opt n Tests entire FPGA BlockRAM Bar Memory Range Test Opt p Bat Memory Range test is a generic memory test It verifies the functionality of a user selectable range of PCI memory First it prompts the user for a BAR number starting address offset a DWORD count and the number of iterations The user is also prompted if the program should stop if error occurs or if the program should display any errors that occur This allows for maximum flexibility when debugging a design with an oscilloscope or debugging any memories or memory locations on your PCI bus The memory test is very complete performing a write then a read to every location a read from every location and then a read wtite read test to every location All other memory test options listed in the memory menu are based on this generic memory test function e C WINNT System32 cmd exe aetest_wdm M gt Main Menu Q gt Quit PCI BASE ADDRESS 8 8600006 1 6600006 2 66600006 3 966080060 4 66600006 5 66600006 Please select option p test of a range within a bar ar lt 52 tarting address offset byte addr 6x1806000 word count 8x28 umber of Iterations for endless 1 top if an error occurs or 2 isplay any errors that occur or oing lt write read gt all read all lt data cpu_addr gt R oing lt read write read gt all
118. com 119 BOARD HARDWARE PPC TRC TCK PPC DBG HALTn PPC JTAG TDO PPC TRC VSENSE PPC JTAG TCK PPC TRC TS10 rH O 2 5 6 MICTOR38 gt Figure 58 Combined Trace Debug Connector Pinout 8 1 5 Combined CPU Trace Debug Connection to FPGA Table 27 shows the connection between the Combined CPU Trace and Debug Port J18 The connections to the FPGA are shared with the CPU Trace and CPU Debug interfaces discussed in previous sections Table 27 Combined CPU Trace Debug connection to FPGA Signal Name FPGA Pin Connector PPC TRC TCK U13 G20 4 6 HALTN U13 F20 4 7 TRC VSENSB N A 4 12 JTAG U13 D20 J4 11 PPC_JTAG_TCK U13 L19 4 15 JTAG TMS U13 K19 4 17 JTAG TDI U13 J19 J4 19 PPC_JTAG_TRSTN U12 79 J4 21 PPC TRC TS1O 018 019 4 24 1520 0713 919 J4 26 PPC_TRC_TS1E U13 E19 J4 28 PPC_TRC_TS2E 1713 019 153 U13 L18 DN6000K 10SC User Guide www dinigroup com 120 BOARD HARDWARE Signal Name FPGA Pin Connector PPC_TRC_TS4 U13 K18 4 34 155 U13 G18 J4 36 PPC_TRC_TS6 U13 F18 J4 38 9 GPIO LED s 9 1 Status Indicators The DN6000K10SC uses DS1 and DS2 to visually indicate the status of the board 051 is controller by MCU U3 and the CPLD U5 controls DS2 Table 28 lists the function of the GPIO LED s The LED
119. ction C function which is recommended for development by users of the DN6000K10SC 2 2 1 Description bar write word allows users of the DN6000K10SC to write a word of data to any location in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 2 2 Arguments The arguments for write word are shown in Table 37 They are listed in order Table 37 write word Arguments Argument Desctiption Possible Values unsigned long barnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 BAR5 5 unsigned long byte offset Address Number of bytes to bytes in mem space offset data wotd data A word of data for the write 0 0000 Oxffff operation 16 bits typedef unsigned char word 2 2 3 Return Values A successful function call will return zeto 2 2 4 Notes The source code for bar write word is portable to each of the operating systems intended for AETEST usage DN6000K 10SC User Guide ww w dinigroup com 159 APPENDIX 2 3 bar write dword bar write is a high level function C function which is recommended for development by users of the DN6000K10SC 2 3 1 Description bar write dword allows users of the DN6000K10SC to write a dword of data to any location in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 3 2 Arg
120. d grade program files that the system 100 displays Courier bold Garamond bold Literal commands that you ngdbuild enter in a syntactical statement design name Commands that you select File gt Open from a menu Keyboatd shortcuts Ctrl C DN6000K10SC User Guide www dinigroup com 2 ABOUT THIS MANUAL Convention Meaning or Use Example Variables in a syntax statement ngdbuild design_name fot which you must supply values References to other manuals See the Development System Reference Guide for more information Italic font ar 7 Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected An optional entry or ngdbuild opton_name parameter However in bus design name specifications such as bus 7 0 they are required Braces A list of items from which you lowpwr off must choose one ot more Vertical bar Separates items in a list of lowpwr on off choices Vertical ellipsis Repetitive material that has IOB 1 Name QOUT IOB 2 Name CLKIN Horizontal ellipsis Repetitive material that has allow block block_name been omitted loct loc2 locn Prefix or suffix Indicates hexadecimal notation Read from address 0 00110373 returned 4552494h 22 Letter P or n Signal is active low INTZ is active low inta is active low
121. d in the SmartMedia socket on the DN6000K108C and turn on the power NOTE the catd can only go in one way The SmartMedia catd is hotswappable and can be taken out or put into the socket even when the power is on Once the power has been turned on the configuration process will begin as long as there is a valid SmartMedia card inserted properly in the socket If there is not a valid SmartMedia card in the socket then 051 will be lit see Table 28 for GPIO and the Main Menu will appear from the serial port A SmartMedia is determined to be invalid if either the format of the card does not follow the SSFDC specifications or if it does not contain a file named main txt in the root directory If the configuration was successful a message stating so will appear and the Main Menu will come up Otherwise an error message will appear The LEDs on DS1 052 give feedback during and after the configuration process see Table 28 for GPIO LED s for further details After the FPGA has been configured the following Main Menu will appear via the serial port refer to Figure 22 DN6000K 10SC User Guide ww w dinigroup com 60 PROGRAMMING CONFIGURING THE HARDWARE DN5000106 HyperTerminal lal xl Ele Edit View Transfer Help MAIN MENU Aug 20 2003 12 33 48 Config LIB Revision 1 39 Configure FPGA s using MAIN TXT Interactive FPGA configuration menu Check configuration status Select f
122. data A dword 32 bit of data for the write operation typedef int dma_buffer_handle typedef unsigned char dword 2 9 3 Return Values A successful function call will return zero If 2 is returned DPMI implementation of AETEST is not being used See Notes 2 9 4 Notes The dma write dword code is wtitten for use in the DPMI DOS implementation of AETEST DN6000K 10SC User Guide ww w dinigroup com 166 APPENDIX 2 10 dma read dword dma read dword is a high level function C function which is recommended for development by users of the DN6000K10SC 2 10 1 Description dma_read_dwotd allows users of the DN6000K10SC to read a dword of data from any byte aligned location in a DMA buffer 2 10 2 Arguments The arguments for read dword are shown in Table 45 They listed in order Table 45 read dword Arguments Argument Description dma_buffer_handle hndl Handle for a DMA buffer int offset Offset in bytes of the write location in the DMA buffer dword data Pointer to a dword 32 bit of data for the read operation typedef int dma_buffer_handle typedef unsigned char dword 2 10 3 Return Values A successful function call will return zero If 2 is returned the DPMI implementation of AETEST is not being used See Notes 2 10 4 Notes The dma_read_dword code is written for use in the DPMI DOS implementation of AETESI DN6000K 10SC User Guide ww w dinigroup com 167
123. default verbose level will be 2 2 The second nonempty uncommented line in main txt tells whether or not to perform a sanity check on the bit files before configuring an FPGA Sanity check y DN6000K 10SC User Guide ww w dinigroup com 58 PROGRAMMING CONFIGURING THE HARDWARE 22 where stands for yes n for no If the line is missing or character after the 71 not or n then the sanity check will be enabled 3 For each FPGA that the user wants to configure there should be exactly one entty in the main txt file with the following format FPGA F example bit In the above format the F following FPGA is to signal that this entry is for FPGA and FPGA F would then be configured with the bit file example bit The DN6000K10SC only has one FPGA which is FPGA F There can be any number of spaces between the and the configuration file name but they need to be on the same line 4 Comments are allowed with the following rules All comments must start at the beginning of the line All comments must begin with Ifacomment spans multiple lines then each line should start with Commented lines will be ignored during configuration and are only for the uset s purpose 5 The file main txt is NOT case sensitive Example of main txt start of file main txt Verbose level 2 Sanity check y FPGA fpgaF bit the line above configures FPGA wit
124. device to select operations xc95288xv cpld jed For Help press F1 Configuration Mode Boundary Scan Parallel IV 4 Note The device selected should be XC95288XV 10 Select the device right click and select Program option 11 Select the Erase before programming and the Erase option before clicking the OK button DN6000K 10SC User Guide ww w dinigroup com 45 PROGRAMMING CONFIGURING THE HARDWARE Program Options On The Fly Program Load FPGA Secure Mode Parallel Mode Program Key F Use D4 for Usercode 8 Hex Digits PLA UES Enter up ta 12 The device will be programmed with the file selected If programming was successful the following window will appear DN6000K10SC User Guide www dinigroup com 46 PROGRAMMING CONFIGURING THE HARDWARE untitled Configuration Mode iMPACT File Edit View Mode Operations Output Help D s E amp Se E E EE 8 Boundary Scan Slave Serial SelectMAP Desktop Configuration xc95288xv cpld jed TDO Programming Succeeded PROGRESS END End Operation a Elapsed time 5 sec 4 For Help press F1 Configuration Mode Parallel IV 13 The CPLD is now programmed proceed with programming the MCU 2 Programming the MCU Code updates will be posted on the Dini Group website The user is requir
125. e terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews at LVTTL levels refer to Figure 35 The outputs arranged in five banks Banks 1 to 4 of four outputs allow a divide function of 1 to 12 while simultaneously allowing phase adjustments in 625 ps 1300 ps increments up to 10 4 ns One of the output banks also includes an independent clock invert function The feedback bank consists of two outputs which allows divide by functionality from 1 to 12 and limited phase adjustments Any one of these eighteen outputs can be connected to the feedback input as well as driving other inputs DN6000K10SC User Guide www dinigroup com 82 BOARD HARDWARE Selectable reference input is a fault tolerance feature which allows smooth change over to secondary clock source when the primary clock source is not in operation The reference inputs and feedback inputs are configurable to accommodate either LVTTL or Differential LVPECL inputs The completely integrated PLL reduces jitter Please refer to the datasheet for more detailed information 25H FBKB b LOCK FBKB Phase Control Logic FBSEL Freq vco Divide and Phase REFA D Detector REFA E REFB 5 REFB OUTPUT MODE REFSEL FBFO gt Ph Feedback Bank rBDso Soler QFA1 FBDS1 2 nits FBDIS Matrix AER 4QA0 gt gt Divide an 1 e Phase Bank4 PF
126. e two clocks are 180 out of phase from each other and their phase alignment must be tightly controlled In order to prevent signal integrity problems and timing differences from becoming an issue it is preferable for each device whether memory or register to have its own clock DN6000K 10SC User Guide www dinigroup com 88 BOARD HARDWARE While it is possible for each device to have a positive and negative clock generated by the FPGA this unnecessarily consumes pins that could be used elsewhere To save these pins an externally DDR SDRAM clock driver is used The clock is routed to the DDR PLL Clock Driver U20 that distributes the individual clocks to the separate DDR devices U17 and U18 4 6 1 Clocking Methodology This section describes the DDR clocking methodology implemented in the reference design refer to Figure 37 The first DCM generates CLKO and CLK90 CLKO directly follows the user supplied input clock one of the clock sources ECLK PCI CLK etc This DCM also supplies the CLKDV output which is the input clock divided by 16 used for the AUTO REFRESH counter The second DCM in the controller block DCM2_RECAPTURE generates a phase shifted version of the user input clock It is used to recapture data from the DOS clock domain during a memory Read Data recaptured in the rclk domain is then transferred to the system clock domain The phase shift value is specific to the system and must be programmed accordingly When
127. ead DN6000K10SC User Guide 168 ww w dinigroup com APPENDIX 2 11 4 Notes In a typical transaction the byte offset value will be a multiple of 4 resulting in a DWORD aligned read or write The PCI command will either be a Memory Read or a Memory Write where MEM READ and WRITE are define definitions used in AETEST BARx where x 0 5 are also define definitions in AETEST The byte enable be is often set to DWORD BYTE EN for 32 bit transactions dwordcount is either 1 or 2 indicating a 32 bit or a 64 bit transaction respectively Finally the parameter verify is set to TRUE when the access is to be verified If verification is not desired verify is set to FALSE DN6000K 10SC User Guide ww w dinigroup com 169 APPENDIX 2 12 DeviceloControl DeviceloControl is low level function Users of the DN6000K10SC advised to use higher level functions such as write dword and bat read dword for development 2 12 1 Description DeviceloControl is used to send commands and receive messages from a specified device on the PCI bus in a Windows environment The QL library is based upon this function A successful DeviceloControl operation will return zero A non zero value is returned if a failure occurs 2 12 2 Arguments The arguments for the DeviceIoControl method is listed in Table 47 They are listed in otder Table 47 DeviceloControl Arguments Argument Description HANDLE hDevice Handle to the d
128. ect sticker on the card The other SmartMedia card is empty and available for user applications To configure the FPGA with the reference design please skip to Starting Select MAP Configuration Status messages are reported by the MCU via the RS232 serial port during FPGA configuration It is INOT necessary to have the serial port connection in order to configure the FPGA in SeleccMAP mode However if an error occurs duting the configuration the user would be able to identify possible problems by viewing the configuration status messages See Configuring HyperTerminal on how to setup the serial port When the FPGA is properly configured LED DS3 will be ON 4 1 Bit File Generation for SelectMAP Configuration Configuring the DN6000K10SC Virtex II PRO FPGA requires the generation of bit files by the Xilinx ISE tools NOTE This user guide will not be updated for every revision of the Xilinx tools so please be aware of minor differences The Xilinx ISE 6 11 revision is used here The CPLD and MCU must be programmed before executing the following instructions First a project must be created Open the Xilinx ISE Project Navigator software package Go to the File menu and select New Project A New Project dialog box will pop up shown in Figure 20 DN6000K10SC User Guide www dinigroup com 52 PROGRAMMING CONFIGURING THE HARDWARE New Project E m Enter a Name and Location for the Project Project Name Project
129. ector 8 CPU DEBUG AND CPU TRACE 8 1 8 1 1 CPU Debug Connector 8 1 2 CPU D bug Connection to EPGA erret 119 8 1 3 M POR 119 8 1 4 CPU Trace 119 8 1 5 Combined CPU Trace Debug Connection to FPGA 120 9 GPIO LED Sise ain EE e terree e 121 9 1 Status Indicators ecciesie ie EREA THERE EEEO E EEEa AASR EASO e EA OR FERREA ARR EE E E EE eR 121 9 2 FEP GA GPIO LED T tsiera 122 9 3 Test Points 122 9 4 Heatsink Fan 123 9 5 REZ SD MONON Er S 123 10 PCI INTERFACE eene 124 10 1 Connection to the FPGA 124 10 1 1 PCI VCCO on the FPGA 125 10 1 2 Iu MIRIEG ITUR 125 10 1 3 Connection between the PCI connector and the 126 10 2 PCI PCI X Hardware Setup 10 2 1 130 10 2 2 M66EN and PEEX CAP Encoding 2 tii ripe OE ER DIETER TEE GEO HER ISTA UII E RAPERE 130 10 2 3 Further Information on PCI PCI X Signals 131 11 POWER SYSTEM tN LO D M Pte es 132 11 1 ITA METIDO 132 11 2 Stand Alone Operation 133 11 2 1 External Power Connector 134 11 2 2 Power Monit
130. ed to purchase the IAR Compiler if in house development is required The compiler is available http www iar com The part number is EWA90PCUBLV150 In order to program the MCU install AVR Studio 4 07 from Atmel http www atmel com This program is freeware and 15 also included on the CD ROM The CPLD must be programmed before the MCU can be programmed see Programming the CPLD This section lists detailed instructions for programming the MCU using the AVR tools Note This user guide will not be updated for every revision of the Atmel AVR tools so please be aware of minor differences 1 The DN6000K108C must be powered with the Atmel AVR cable connected to MCU ISP header P3 and the other end to a serial port on the PC DN6000K10SC User Guide www dinigroup com 47 PROGRAMMING CONFIGURING THE HARDWARE 2 MCU 5232 serial port is required to complete the initialization phase after the MCU has been programmed See Configuring HyperTerminal 3 Download and unzip the latest programming file for the MCU from the Dini Group website Processor and CPLD update http www dinigroup com 4 Run AVR Studio From the Windows START menu choose PROGRAMS Atmel AVR Studio 4 5 Cancel the Welcome to AVR Studio 4 window by clicking cancel button 6 Select TOOLS STK500 AVRISP JTAG ICE and a new window should appear 7 In the Device list select the Atmega128 and in Flash window p
131. eloped the world s most advanced FPGA silicon product Leading teams from top embedded systems companies worked together with Xilinx software teams to develop the systems software and IP solutions that enabled new system architecture paradigm The result is the first FPGA solution capable of implementing high performance system on a chip designs previously the exclusive domain of custom ASICs yet with the flexibility and low development cost of programmable logic The Virtex II Pro family marks the first paradigm change from programmable logic to programmable systems with profound implications for leading edge system architectures in networking applications deeply embedded systems and digital signal processing systems It allows custom user defined system architectures to be synthesized next generation connectivity standards to be seamlessly bridged and complex hardware and software systems to be codeveloped rapidly with in system debug at system speeds Together these capabilities usher in the next programmable logic revolution 1 1 Summary of Virtex Il Pro Features The Virtex II Pro has an impressive collection of both programmable logic and hard IP that has historically been the domain of the ASICs e High performance FPGA solution including o Up to twenty four RocketIO embedded multi gigabit transceiver blocks based on Mindspeed s SkyRail technology DN6000K10SC User Guide www dinigroup com 16 INTRODUCTION TO VIRTEX II
132. enerate little or no noise of their own while providing a low resistance path for an external driver The output enable OE input can be used to disable the device so that the busses ate effectively isolated 12 2 5 LVDS IO Low voltage differential signaling LVDS is a signaling method used for high speed transmission of binary data over copper It is well recognized that the benefits of balanced data transmission begin to outweigh the costs over single ended techniques when the signal transmission times approach 10 ns This represents signaling rates of about 30 Mbps or clock rates of 60 MHz in single edge clocking systems and above LVDS is defined in the TIA EIA 644 standards Connector J2 is a Mini D Ribbon MDR connector 50 pin manufactured by 3M used specifically for high speed LVDS signaling The connector mates with a standard off the shelf 3M cable assembly P N 14150 EZBB XXX 0LC where XXX is 050 0 5 m 150 1 5m 300 3 0 m 500 5 0 m Please contact for further details http www 3m com DN6000K10SC User Guide Www dinigroup com 143 BOARD HARDWARE 12 2 6 Connection between FPGA and the Daughter Card Headers Table 35 shows the IO connections between the DN3000K10SD headers and the FPGA IO pins The VCCO of the IO banks are connected to 2 5V Table 35 Connection between FPGA and the Daughter Card Headers
133. essages that Level 1 displays Options that are found in main txt Bit file names for each FPGA as entered in main txt Maker ID device ID and size of Smart Media card All files found on Smart Media card If sanity check is chosen the bit file attributes will be displayed part package date and time of the bit file During configuration will be printed out after each block 16 KB has successfully been transferred from the Smart Media to the current FPGA 4 2 2 Sanity Check The Sanity Check if enabled verifies that the bit file was created for the right part the right version of Xilinx was used and the bitgen options were set correctly If any of the settings found in the bit file are not compatible with the FPGA a message will appear from the serial port and the user will be asked whether or not they want to continue with the bit file Please see the section Bit File Generation for SelectMAP Configuration for details on which bitgen options need to be changed from the default settings A PC version of the sanity check can be run on your bit files before copying them onto the Smart Media card see section PC Bit File Sanity Check for more details 4 2 3 Format of main txt The format of the main txt file is as follows 1 The first nonempty uncommented line main txt should be Verbose level X where X can be 0 1 or 2 If this line is missing or X is an invalid level then the
134. essary to make some hardware changes The connections between the FPGA and various clocking resources are documented in Table 13 covering the clocking inputs and outputs respectively DN6000K10SC User Guide www dinigroup com 79 BOARD HARDWARE Table 13 Clocking inputs to the FPGA Signal Name FPGA Pin Clock Refdes and Pin CLK_USERn D17 J13 CLK_USERp E17 J7 RocketIO_OSCn H17 X2 RocketIO_OSCp J17 X2 DDR_CLKn E18 U20 DDR_CLKp D18 U20 CCLKO 17 U13 DCLKO AK18 U13 ECLKO U20 PCI CLK AK17 P2 SYS CLK AH18 X3 FPGA GCLKOUT AH17 U21 4 2 Clock Source J umpers The clock source grid JP5 gives the user the ability to customize the clock scheme on the DN6000K10SC A brief description of each pin is given in Table 14 Table 14 Clock Source Signals Signal Name Desctiption Connector CPLD CLKOUT Clock signal from the CPLD JP5 A3 CLOCKA CLOCKB Clock signal from oscillator X4 Clock signal from oscillator X5 JP5 A1 PLL1B Secondary clock input to RoboClock differential pair with PLLIBN PLLIBN Secondary clock input to RoboClock differential pair with PLL1B PLL2B Secondary clock input to RoboClock differential pair with PLL2BN PLL2BN DN6000K10SC User Guide Secondary clock input to RoboClock differential pair with PLL2BN Www dinigroup com 80 BOARD HARDWARE Description Connector Provides
135. ever populate R10 R11 simultaneously this will result in a shorting the 3 3V and 5V power supplies This would be BAD Header J8 allows external connection to the Power Sources refer to Table 34 for connection details Table 34 External Power Connections Function i Function GND GND TOV 1 5V GND GND 5V 12V GND GND 3 3V 12V GND GND 3 3V 12V GND GND 1 5V 12V DN6000K10SC User Guide www dinigroup com 142 BOARD HARDWARE 12 2 3 Unbuffered IO The DN3000k10SD Daughter Card provides 66 unbuffered 1 O signals including 5 single ended clock signals available on headers J5 J6 and J7 The function of these signals is position dependent 12 2 4 Buffered IO The DN3000k10SD Daughter Card provides 48 buffered I O signals available on headers J3 and J4 The function of these signals is position dependent U1 U2 and U3 allow for different populating options and devices can be active or passive Active The LCV162245A is used for asynchronous communication between data buses It allows data transmission from the A to the B or from the B to the A bus depending on the logic level at the direction control DIR input The output enable OE input can be used to disable the device so that the busses are effectively isolated Passive The FST163245 bus switches are used to connect or isolate two ports without providing any current sink or source capabilities Thus they g
136. evice for operation DWORD dwloControlCode Control code for the operation LPVOID IpInBuffer Pointer to a buffer containing data necessary for operation DWORD nInBufferSize Specifies the size in bytes of the buffer pointed to by IpInBuffer LPVOID IpOutBuffer Pointer to a buffer that receives the operation s output data DWORD nOutBufferSize Specifies the size in bytes of the buffer pointed to by IpOutBuffer LPDWORD IpBytesRetutned Pointer to a variable that receives the size in bytes of the data stored into the buffer pointed to by IpOutBuffer LPOVERLAPPED IpOverlapped Pointer to an OVERLAPPED structure 2 12 3 Return Values A successful DeviceloControl operation will return zero A non zero value is tetutned if a failure occuts DN6000K 10SC User Guide ww w dinigroup com 170 APPENDIX 2 12 4 Notes hDevice CreateFile function should be used to rettieve a handle dwloControlCode See include glentlcodes h which is included with the AETEST source code for example control codes IpInBuffer This parameter can be set to NULL if no input data is required for the operation nInBuffetSize N A IpOutBuffer This parameter can be set to NULL if operation does not produce any output data NOutBufferSize N A IpBytesReturned If the output buffer is too small the call function fails and the returned byte count is zero If the output buffer is full prior to operation completion
137. eviously takes the form of a Virtex II Pro datasheet and a DN6000K10SC User Guide 2 2 Electronic Documentation Multiple documents and datasheets have been included on the CD 2 3 Online Documentation There is a public access site that can be found on the Dini Group web site at http www dinigroup com DN6000K 10SC User Guide ww w dinigroup com 41 PROGRAMMING CONFIGURING THE HARDWARE Chapter Programming Configuring the Hardware This chapter details the programming and configuration instructions for the DN6000K105C 1 Programming the CPLD Code updates will be posted on the Dini Group website The user is required to purchase the Xilinx Development Tools if in house development is required The tools are available from Xilinx http www xilinx com This section lists detailed instructions for programming the CPLD using the Xilinx ISE 6 11 tools It is very unlikely that you will have to do this CPLD is configured at the factory and the function is quite mature Note This user guide will not be updated for every revision of the Xilinx tools so please be awate of minor differences 1 The DN6000K10SC must be powered with the Xilinx JTAG cable connected to header P5 and the other end to a serial port on the PC 2 Download the latest programming file for the CPLD from the Dini Group website filename CPLD JED http www dinigroup com 3 RuniMPACT From the Windows START menu choose PROGR
138. f 48 MHz is interesting because it is the closest frequency to 50 MHz that can be divided by an integer to get 8 MHz The DN6000K 10SC User Guide www dinigroup com 72 BOARD HARDWARE frequency 50 MHz is the fastest that the Virtex II Pro parts can be configured with SelectMap without wait states So FPGA configuration using SelectMap occuts at very nearly the fastest theoretical speed Serial and JTAG configuration of the Virtex II Pro FPGA s are back off positions only The 48 MHz clock can be divided down in the CPLD and used as a clock source to the PWB clock network CPLD_CLKOUT ROBO LOCK 1 2 Indicates that the RoboClock U22 U21 PLL s are locked MSEL 0 3 selects the configuration mode of the FPGA refer to Table 9 Table 9 FPGA Configuration Modes Configuration Mode CLK Direction Master Serial Out Slave Setial In Master SelectMAP Slave SeleccMAP Boundary Scan Note Grayed options not supported by this design 3 3 SmartMedia The configuration bit file for the FPGA is copied to a SmartMedia card using the SmartDisk FlashPath Floppy Disk Adapter The approximate file size for each possible FPGA option is shown below in DN6000K10SC User Guide www dinigroup com 73 BOARD HARDWARE Table 10 Note that several BIT files can be put on a 32MB card The DN6000K10SC is shipped with two 32 megabyte 3 3V SmartMedia cards The DN6000K10SC supports card densit
139. for direct connection of an external differential clock to the FPGA 4 9 1 FPGA to SMA Connector The connection between the FPGA and the SMA connectors is fairly simple involving only one wire per connector as well as a few resistors to AC couple and terminate the signals The connections are also shown in Table 19 Table 19 Connections between FPGA and SMA Connector CLK Signal Name FPGA Pin Connector CLK_USERp U13 E17 J7 CLK_USERn U13 D17 J13 5 Reset Topology 5 1 DN6000K10SC Reset The voltage monitor devices from Linear Technology P N LTC1326 U4 U5 allow a push button reset function that is used to reset the DN6000K108SC Figure 44 shows the distribution of the reset signal PWRRSTn In addition to controlling the reset the power supplies rails 1 5V 2 5V 3 3V and 5V are monitored for under voltage conditions that will cause the assertion of the PWRRSTn signal Momentarily depressing the RESET push button S1 causes a narrow 100us soft reset pulse on the signal PWRRSTn If the reset push button S1 is depressed for more than 2 seconds and held PWRRSTn will be asserted continuously LED DS2 2 when lit means that reset is asserted refer the section describing the GPIO DN6000K10SC User Guide www dinigroup com 94 BOARD HARDWARE 3 3V 5 0 1 5V PCI PCI X Interface PCI Reset Circuit PWRRSTn
140. gers The PCI 3 3V is not used and the user should not connect this supply to the power grid During in system operation the DN6000K10SC has the following power supplies 1 5V 25 3 3V e 5V 12 e 12V The 1 5V 2 5V and 3 3V power supplies are generated from the 5V supply using the DATEL power modules U23 U25 024 These modules are non isolated DN6000K10SC User Guide Www dinigroup com 132 BOARD HARDWARE 300kHz switching regulators rated for 10A and provide clean power to the DN6000K10SC please refer to datasheet for more information The 5V rated for 25W as per PCI Specification 12V and 12V is obtained from the PCI fingers 11 2 Stand Alone Operation The DN6000K10SC can be used standalone meaning it doesn t have to be plugged into a PCI slot An external ATX power supply is used to supply power to the DN6000K10SC in this configuration refer to Figure 62 The external power supply connects to header P9 a Tyco disk drive type of connector During standalone operation the DN6000K10SC has the following power supplies 1 5V 2 5V 3 3V 5V 12V The 1 5V 2 5V and 3 3V power supplies are generated from the 5V supply using the External ATX power supply Figure 62 ATX Power Supply DN6000K10SC User Guide www dinigroup com 133 BOARD HARDWARE Any ATX type power supply is adequate The Dini Group recommends a power supply rated for 250W Note The switching
141. h resolution phase shifting o 16 global clock multiplexer buffers in all parts e Active Interconnect technology Fourth generation segmented routing structure Fast predictable routing delay independent of fanout o Deep sub micron noise immunity benefits Select I O Ultra technology o Up to 852 user I Os o Twenty two single ended standards and five differential standards Programmable LVTTL LVCMOS sink source current 2 mA to 24 mA per I O o Digitally Controlled Impedance DCI I O on chip termination resistors for single ended I O standards PCI and PCI X support 1 o Differential signaling 840 Mb s Low Voltage Differential Signaling I O LVDS with current mode drivers Bus LVDS I O HyperTransport I O with current driver buffers Built in DDR input and output registers Proprietary high performance technology for communications between Xilinx devices High bandwidth data path Double Data Rate DDR link Web based HDL generation methodology e SRAM based in system configuration Fast SelectMAP configuration DN6000K10SC User Guide www dinigroup com 19 INTRODUCTION TO VIRTEX II PRO AAND ISE o Triple Data Encryption Standard DES security option bitstream encryption o 1532 support O Partial reconfiguration o Unlimited reprogrammability o Readback capability e Supported by Xilinx Foundation and Alliance series development sy
142. h the bit file fpgaF bit end of main txt Given the above example file Verbose level is set to 2 a sanity check on the bit files will be performed and FPGA will be configured with file fpgaF bit NOTE All configuration file names have a maximum length of eight 8 characters with an additional three for the extension Do not name your configuration bit files with long file names In addition all file names should be located in the root directory of the Smart Media card no subdirectories folders are allowed Since the main txt file controls which bit file is used to configure the FPGA the Smart Media card can contain other bit files DN6000K10SC User Guide www dinigroup com 59 PROGRAMMING CONFIGURING THE HARDWARE 4 3 Starting SelectMAP Configuration If using the reference design SmartMedia card that came with the DN6000K10SC then no files need to be copied to the card Otherwise copy your bit file and main txt to the root directory of the SmartMedia card using the FlashPath floppy adapter or some other means Make sure the dipswitch 52 is set for SeleccMAP as shown in Table 5 Table 5 S2 Dipswitch Configuration Settings Signal Name Pins Status FPGA_MSELO Pins 1 amp 8 Closed FPGA_MSEL1 Pins 2 amp 7 Open FPGA_MSEL2 Pins 3 amp 6 Open DIP_SW3 Pins 4 amp 5 X Set up the serial port connection as described above in Configuring HyperTerminal Next place the SmartMedia car
143. he DWORD stored at the specified address and display it 2 Sameasoption 1 however the transaction is repeated indefinitely 3 AETEST will repeatedly write then read the DWORD stored at the specified address DN6000K10SC User Guide www dinigroup com 33 INTRODUCTION TO THE SOFTWARE TOOLS IC WINNTSystem32 cmd exe aetest_wdm Bar Number 5 gt 8 Address Chex gt 8188080808 umbers of long words to write Cin decimal 1 long word to write hex 54fedcha 1 Display result 2 Display result and loop indefinitely 3 Don t display result and loop indefinitely lease select 1 S4fedcha 54fedcha it a key to continue Figure 10 Memory W rite Read DWORD Figure 10 shows a wtite read of the DWORD 0x54fedcba from address 0x200000 of SSRAM 2 Bar Memory Fill Opt 4 Memory Fill enables to user to fill a region of PCI memory space with a data selectable pattern All 4 gigabytes of memory space is accessible Figure 11 shows a sample transaction Using Bar Memory Fill the user must first enter the BAR Number to be accessed Then the starting address must be entered in hex and the number of bytes the user wishes to fill in hex and divisible by 4 Finally the user must choose from a selection data patterns 1 Fill with 0 fill all the locations with 0x00000000 clear the memory 2 Data Address fill each DWORD with its address 3 Alternating 0x55555555 and Oxaa
144. ied address and display it 2 Same as option 1 however the transaction is repeated indefinitely 3 AETEST will read the DWORD stored at the specified address repeatedly DN6000K10SC User Guide www dinigroup com 32 INTRODUCTION TO THE SOFTWARE TOOLS Options 2 and 3 are useful for debugging read transactions FIC WINNT System32 cmd exe aetest_wdm Bar Number 5 gt 8 Address Chex 1000000 1 Display result 2 Display result and loop indefinitely 3 Don t display result and loop indefinitely lease select 1 esult abcdef45 it a key to continue Figure 9 Memory Read DWORD Figure 9 shows a read of the DWORD from address 0x200000 of SSRAM 2 This read retrieves the data Oxabcdef45 written in the Write DWORD section See Figure 8 Write Read DWORD Opt 3 Write Read DWORD allows the user to write a DWORD to any location in the Base Address Registers BAR Then the function read back the data stored from the same address Akin to the previous DWORD operation all 4 gigabytes of PCI memory can be accessed Figure 10 shows a typical memory write read operation The user will be prompted once the option is chosen for the BAR to be accessed Then the memory location in hex is required AETEST will prompt the user for the number of DWORDs to write in decimal Each DWORD must be individually entered Finally the user must choose a display option 1 Following the write AETEST will read t
145. ies up to 128MB DN6000K 10SC User Guide www dinigroup com 74 BOARD HARDWARE Table 10 FPGA configuration file sizes Virtex II Pro Bitstream Device Length bits XC2VP20 8 214 624 XC2VP30 11 589 984 XC2VP40 15 868 256 XC2VP50 19 021 408 SmartMedia Cards are available from www computers4sure com Please note that a polyswitch resetable fuse has been placed in series with the SmartMedia power supply We found that pressure on the top of the SmartMedia connector shorted the 3 3V power to the case which is connected to ground This is BAD The polyswitch should protect your DN6000k10SC from damaged If the polyswitch opens it takes a few minutes for the fuse reset The DINI Group recommends surfing the Internet for a few minutes The following are our favorite sites http www drudgereport com news and gossip http www ebay com big garage sale http www weather com weather http www 6speedonline com forums fast car discussion forum 3 3 1 SmartMedia Connector Figure 29 shows J1 the SmartMedia connector used to download the configuration files to the FPGA DN6000K10SC User Guide www dinigroup com 75 BOARD HARDWARE SmartMedia Interface SM D 0 7 Ji SM CLE 2 SM ALE 3 CLE SM WEn 4J ALE SM WPn 59 WE SM CEn 219 WE SM 200 SMOCDn 27 WP CARD INS H3 WP CARD INS HE 16 GND R B 19 Ja GND
146. ile to use for configuration 5 List files on Smart Media 6 Select FPGA to program via JTAG 8 Display Contents of a TXT file ENTER SELECTION Connected 1 06 47 Auto detect amp N 1 SCROLL CAPS NUM capture Print echo Figure 22 Main Menu The HyperTerminal interface gives the user an easy method for handling and monitoring the DN6000K10SC FPGA configuration 4 3 1 Description of Main Menu Options Table 6 describes the Main Menu options found on the HyperTerminal interface Table 6 HyperTerminal Main Menu Options Option Function Description 1 Configure FPGA sin The FPGA will configure in Select MAP mode You can also Using main txt as press the reset button S1 to reconfigure the FPGA in Select the Configuration File MAP mode 2 Interactive FPGA This option takes you to a menu titled Interactive configuration menu Configuration Menu and allows the FPGA to be configured through a set of menu options instead of using the main txt file The menu options are described 3 Check Configuration This option checks the status of the DONE pin and prints out Status whether or not the FPGA s have been configured along with the file name that was used for configuration DN6000K 10SC User Guide ww w dinigroup com 61 PROGRAMMING CONFIGURING THE HARDWARE Function Description Select file to use in By default the processor uses the file main txt to get the n
147. imum 1 2 PRSNT1 HSA 4 PRSNT2 The DN6000K10SC is factory configured for 25W power setting JP1 1 2 installed and JP1 3 4 left open 10 2 2 M66EN and PCIXCAP Encoding The 66MHZ ENABLE pin indicates to a device whether the bus segment is operating at 66 or 33 MHz Add in cards indicate whether they support PCI X and if so which frequency by the way they connect one pin called PCIXCAP refer to Figure 61 DN6000K 10SC User Guide www dinigroup com 130 BOARD HARDWARE R69 C157 10K 0 01uF C150 5 Figure 61 M66EN and PCIXCAP Jumper If the card s maximum frequency is 133 MHz it leaves this pin unconnected except for a decoupling capacitor If the card s maximum frequency is 66 MHz it connects PCIXCAP to ground through a resistor and decoupling capacitor Conventional catds connect this pin to ground An add in card indicates its capability with one of the combinations of the M66EN and PCIXCAP pins listed in Table 32 Table 32 M66EN and PCIXCAP Encoding PCIXCAP Conventional PCI X Device Device Frequency Frequency Capability Capabilit Ground 33 MHz Not 66 MHz Not capable connected Ground Pull down 33 MHz PCI X 66 MHz connected connected connected connected The DN6000K10SC is factory configured to operate in PCI mode at 33MHz JP2 5 6 and JP2 9 10 jumpers installed 10 2 3 Further Information on PCI PCI X Signals The following signals have pull up resistors IM on the DN6000K10SC
148. indow tHe meme aaao Creete New Source Design Entry User Constraints Implement Design Generate Programming File Figure 21 Project Navigator In the Process for Source window a process is signified by the icon In the Process for Source window the user must right click on the Generate Programming File process and select properties The default settings are correct The user should verify a couple important options right click and selecting properties options Configuration Options Tab Configuration Pin Powerdown Pull Up DN6000K10SC User Guide www dinigroup com 55 PROGRAMMING CONFIGURING THE HARDWARE Process Properties EU I a CCL Default 4 Default 5 Default 6 Default NoWait Default NoWait Readback Options Tab Security Enable Readback and Reconfiguration www dinigroup com 56 DN6000K10SC User Guide PROGRAMMING CONFIGURING THE HARDWARE Process Properties x General Options Configuration Options Startup Options Readback Options Encryption Options Value able Readback and E gt Property Name Create ReadBack Data Files Allow SelectMAP Pins to Persist Create Logic Allocation File Create Mask File INIA TN The user can now generate the bit file In the Process for Source window the user must right click on the
149. inigroup com 31 INTRODUCTION TO THE SOFTWARE TOOLS Write DWORD Opt 1 Write DWORD allows the user to write to any location in the Base Address Registers BAR All 4 gigabytes of PCI memory can be accessed A minimum of 1 to a maximum of 1024 DWORDs can be written in sequential order to the same address Figure 8 shows a typical memory write Once the option is chosen the user must input the BAR Number followed by the address within the specified BAR Then the user needs to input the number of DWORDs to be written in decimal The data to be written must be entered for each DWORD Finally the user must choose to repeat the write access indefinitely or not Pressing any key will stop a looping write FS C INNT System32 cmd exe aetest_wdm Bar Number 5 gt 8 Address Chex gt 8188080808 umbers of long words to write decimal 1 long word to write Cin hex abcdef45 oop indefinitely or n gt it a key to continue Figure 8 Memory Write DWORD The transaction shown in Figure 8 writes the DWORD Oxabcdef45 to address 0x200000 of SSRAM 2 Read DWORD Opt 2 Read DWORD allows the user to read DWORD from any location in the Base Address Registers BAR Figure 9 shows a typical memory read Once the option is chosen the user must input the Bar Number followed by the address location Then the user is given three options 1 AETEST will read DWORD stored at the specif
150. ise test memory test on FPGA block memory memory test on 1 memory test on memory test on full memory test Cincluding blockram gt Main Menu 9 gt Quit PCI BASE ADDRESS 8600600 2 66800006 66680686 5 66060000 Please select option 6 The DN6000K10SC features DDR SDRAM SRAM and Flash memory devices The DN6000K10SC specific memory tests are designed to exercise and verify the functionality of those features Select one of the memory devices to be tested DN6000K10SC User Guide www dinigroup com 14 ABOUT THIS MANUAL es WINNT System32 cmd exe aetest _wdm exe Write Dword Same Address 22 Read Duord Same Address gt Write Read BAR Memory BAR Memory BAR Memory bar memory bar memory memory test memory test memory test memory test Dword Same fiddress Fill Write Display range test address data bitwise test on FPGA block memory on SSRAM 1 on SSRAM 2 on DDR full memory test including blockram Main Menu 9 3 88900008 Please select option word count 8x1808 top if an error occurs or isplay any errors that occur Q gt Quit PCI BASE ADDRESS 1 6600000 2 96880000 4 96600000 5 88888888 c or 7 The AETEST Test utility will now test the selected memory device using the memory controllers available the selected memory device indicated by the dots 5 C WINNT
151. karea dn3000K10 uPXDN 11 After programming the processor close all AVR Studio windows and open the HyperTerminal Window Press ENTER to display the first initialization instruction 12 Enter number of FPGAS on board 1 6 1 13 Please select the first FPGA on the board F A E B or D F 14 Please enter selection 1 6 for FPGA F 9 15 The initialization process will then be completed and present the user with the FPGA configuration main menu The FPGA is now ready to be configured see Configuring the FPGA using SelectMap DN6000K10SC User Guide www dinigroup com 50 PROGRAMMING CONFIGURING THE HARDWARE 3 Configuring HyperTerminal A terminal emulator is required to monitor MCU transactions The DINI Group suggests using the Windows based program HyperTerminal Hypertrm exe The configuration file for HyperTerminal DN6000K10SC ht is supplied on the CD ROM or can be downloaded from The DINI Group website The RS232 port is configured with the following parameters e Bits per second 9600 e Data bits 8 Parity None e Stop Bits 1 e Flow control None Terminal Emulation VT100 A cable that converts the 5 x 2 header to a is shipped with the DN6000K10SC Insert the 5 x 2 header into the MCU RS232 header P4 P4 is not keyed ensure correct pin orientation Note MCU RS232 Header P4 is not keyed Ensure correct pin orientation Pin 1 is indicated with a letter 1 on the board
152. n board the DN6000K10SC is a FPGA in the FF1152 package The capabilities of the 2VP20 base model include 2 PowerPC 405 processor 8 Multi Gigabit Transceivers 564 SelectI O e 8 Digital Clock Managers DCMs 9000 logic slices making up 10 000 LUTs e 1500 Kbits of block SelectRAM BRAM DN6000K10SC User Guide www dinigroup com 67 BOARD HARDWARE e 88 18 x 18 bit multiplier blocks The FF1152 package for the FPGA that is used on the DN6000K10SC is a 1 0mm 35 x 33mm fully populated with four corner balls removed flip chip BGA The PowerPC 405 is capable of operation at 300 MHz and is capable of 420 Dhrystone MIPs dependend on the speed grade of the part Each of the MGTs are capable of 3 125 Gigabits per second in both directions for an aggregate bandwidth of 50 Gigabits per second from the 25 Gbps transmit and 25 Gbps receive The SelectIO are capable of supporting multiple high speed I O standards from LVDS to SSTL2 to PCI The DCMs are capable of 24 MHz to 420 MHz operation and provide for clock deskew frequency synthesis and fine phase shifting 2 2 FPGA Bankout Diagram The FPGA is connected directly or indirectly to all other devices on the board Figure 25 shows the connections to the FPGA on a per bank basis Bankout Diagram Top View DN6000108 SMA SMA SM
153. ng byte offset Address Number of bytes to bytes in mem space offset data byte data Pointer to a byte of data for the 0x00 Oxff read operation 8 bits Itypedef unsigned char byte 2 4 3 Return Values A successful function call will return zeto The byte of data read during the access is placed in the variable location pointed to by data 2 4 4 Notes The source code for bar read byte is portable to each of the operating systems intended for AETEST usage DN6000K 10SC User Guide ww w dinigroup com 161 APPENDIX 2 5 bar read word read word is a high level function C function which is recommended for development by users of the DN6000K10SC 2 5 1 Description bar read word allows users of the DN6000K10SC to read word of data from any location in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 5 2 Arguments The arguments for read word are shown in Table 40 They are listed in order Table 40 bar read word Arguments Argument Desctiption Possible Values unsigned long barnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 BAR5 5 unsigned long byte offset Address Number of bytes to bytes in mem space offset data wotd data Pointer to a wotd of data for the 0 0000 Oxffff read operation 16 bits Itypedef unsigned
154. nkout FPGA CONFIGURATION M RR 3 1 Micro Controller Unit MCU s 3 1 1 MCU Programming reete UR REESE 3 12 RS232 Interface 3 2 siii ether tete 3 2 1 CPLD Programming Connector 3 22 Design Notes the CPLD m 3 3 E 3 3 1 SmartMedia Connector SE 3 3 2 SmartMedia connection to CPLD MCU 3 4 Boundary Scan JTAG IEEE 1532 Mode seite n Re eR ER 3 4 1 FPGA JTAG Gomme tot dE 342 FPGA JTAG connection to CPLD CLOCK 4 1 Clock Methodology 5 4 2 Clock Source 4 2 1 Clock Source Jumper Header eter reet RR 4 3 External Clocks esee eene 4 4 3 1 Running The Whole Board Synchrono sly ttti eee ee NEE 81 4 4 Common Clock Source Selections 5 e tiis 82 4 5 RoboClock PLL Clock Buffers gt 4 5 1 RoboClock Configuration 83 4 5 2 Clock Source Jumper Header zioni tee 87 4 5 3 Useful Notes and Hints 4 5 4 Customizing the Oscillators 46 DDR Clocking 4 6 1 Clocking Methodology 4 6 2 Connections between FPGA and DDR PLL Clo
155. ns ISE s Architecture Wizards allow easy access to device features like the Digital Clock Manager and Multi Gigabit I O technology ISE also includes a tool called PACE Pinout Area Constraint Editor which includes a front end pin assignment editor a DN6000K10SC User Guide www dinigroup com 20 INTRODUCTION TO VIRTEX II PRO AAND ISE design hierarchy browser and an area constraint editor By using PACE designers are able to observe and describe information regarding the connectivity and resource requirements of a design resource layout of a target FPGA and the mapping of the design onto the FPGA via location atea This rich mixture of design entry capabilities provides the easiest to use design environment available today for your logic design 2 1 2 Synthesis Synthesis is one of the most essential steps in your design methodology It takes your conceptual Hardware Description Language HDL design definition and generates the logical or physical representation for the targeted silicon device A state of the art synthesis engine is required to produce highly optimized results with a fast compile and turnaround time To meet this requirement the synthesis engine needs to be tightly integrated with the physical implementation tool and have the ability to proactively meet the design timing requirements by driving the placement in the physical device In addition cross probing between the physical design report and the HDL design code
156. nsive external instrumentation Using the JTAG test access port a debug tool can single step the processor and examine the internal processor state to facilitate software debugging This capability complies with the IEEE 1149 1 specification for vendor specific extensions and is therefore compatible with standard JTAG hardware for boundary scan system testing 8 1 CPU Debug External debug mode can be used to alter normal program execution It provides the ability to debug system hardware as well as software The mode supports multiple functions starting and stopping the processor single stepping instruction execution setting breakpoints as well as monitoring processor status Access to processor resoutces is provided through the CPU Debug port The PPC405 JTAG Joint Test Action Group Debug port complies with IEEE standard 1149 1 1990 IEEE Standard Test Access Port and Boundary Scan Architecture This standard describes a method for accessing internal chip resources using a four signal or five signal interface The PPC405 JTAG Debug port supports scan based board testing and is further enhanced to support the attachment of debug tools These enhancements comply with the IEEE 1149 1 specifications for vendor specific extensions and are compatible with standard JTAG hardware for boundary scan system testing The PPC405 JTAG debug port supports the four required JTAG signals TMS TDI and TDO It also implements the optional TRST
157. nsures data bits are read correctly even at maximum cable lengths between DTE and DCE specified as 50 feet The RS 232 standard has two primaty modes of operation Data Terminal Equipment and Data Communication Equipment DCE These can be thought of as host ot PC for D TE and as petipheral for DCE The DN6000K10SC operates in the DCE mode only Figure 27 shows the implementation of the serial port on the DN6000K10SC DN6000K 10SC User Guide www dinigroup com 70 BOARD HARDWARE MCU TXD MCU 65232 Interface U6 THIN T1OUT R1OUT e BXD EN FORCEOFF FORCEON INVALID cg 0 1 Figure 27 MCU Serial Port There ate two signals attached to the MCU e Transmit Data e Receive Data TXD and RXD provide bi directional transmission of transmit and receive data No hardware handshaking is supported 3 2 CPLD The Xilinx XC95288XV U5 CPLD is needed to handle the counters and state machines associated with the high speed interface to the SmartMedia card Approximately 90 of the resources of this device are utilized so 10 are available to the user The Verilog source code for the CPLD CPLD V is provided on the CD ROM The CPLD performs the following functions e Interface to the Micro Controller Data Bus MCU_ADJO 7 Control Signals MCU RDn MCU_WRn MCU ALE Clock MCU CLK e Interface to the SmartMedia Data Bus SM DJ 0 7 Control
158. nx understands the critical issues such as complex board layout signal integrity high speed bus interface high performance I O bandwidth and electromagnetic interference for system level designers To ease the system level designers challenge ISE provides support to all Xilinx leading FPGA technologies e System IO XCITE e Digital clock management for system timing control management for electromagnetic interference To really help you ensure your programmable logic design works in context of your entire system Xilinx provides complete pin configurations packaging information tips on signal integration and various simulation models for your board level verification including e BIS models HSPICE models e STAMP models 3 Virtex4l Pro Developer s Kit V2PDK is the Virtex II Pro Developer s Kit and is included to provide an existing framework of hardware and software code to explore the capabilities of the Virtex II Pro as well as a basis to build new systems A wide variety of software and hardware tools used to build a ProTM design V2PDK The design flow is a tool chain methodology that exists to simplify the entire design process by providing integration between the tools and automating tasks The main focus of the design flow is integrating the programs with each other to accomplish the system design The system design process can be loosely divided into the following tasks e Build
159. oard is in working order by following the steps below 2 The DN6000K 10SC LOGIC Emulation Kit The DN6000K10SC LOGIC Emulation Kit provides a complete development platform for designing and verifying applications based on the Xilinx Virtex II Pro FPGA family The DN6000K10SC can be hosted in a 3 3V 32 64 bit PCI PCI X slot or can be used in a stand alone application The DN6000K10SC enables designers to implement embedded processor based applications with extreme flexibility using IP ABOUT THIS MANUAL cores and customized modules The Virtex II Pro FPGA with its integrated PowerPC processor and powerful Rocket I O Multi Gigabit Transceivers MGT make it possible to develop highly flexible and high speed serial transcetver applications The DN6000K10SC includes 64 bit PCI PCI X interface 512K x 36 SSRAM 2 32M x 16 DDR SDRAM 2 4M x 16 FLASH 1 an RS232 port for monitor and a SmartMedia interface for configuration There are 9 low skew clock sources that are distributed to the FPGA and the test header A 200 pin test header allows for connection to individual FPGA s IO banks using a custom daughter card Figure 1 shows the DN6000K10SC Logic Emulation Board Figure 1 DN6000K10SC LOGIC Emulation Board The DN6000K10SC LOGIC Emulation Kit includes the following DN6000K10SC development board 2VP20 30 40 50 5 6 7 in the FF1152 package Note Specific speed grade parts required for various RocketIO Power PC operating s
160. oint to the location of the MCU programming file DN6000K10SC A90 LI 8 Program Fuses LockBits Advanced Board Auto Device Erase Device Programming mode ISP Erase Device Before Programming Parallel Hiah Voltage Serial Verify Device After Programming Input HEX File data workarea dn3000K Program Verify Read EEPROM Use Curent Simulator Emulator EEPROM Memory Input HEX File a Program Verify Read Flash Use Current Simulator Emulator FLASH Memory Getting revisions Hw 0x01 SW Major 0x01 SW Minor OK Getting oscillator parameters P 0 01 0 00 50 0 01 OK 8 Select the Advanced tab and read the device signature by selecting the Read Signature button DN6000K10SC User Guide www dinigroup com 48 PROGRAMMING CONFIGURING THE HARDWARE Head Wal Byte Flash Eeprom Write to Memory 9 Select the Program tab and program the device by selecting the Program button in the Flash window 10 The device is now programmed and the status window should report the following DN6000K10SC User Guide www dinigroup com 49 PROGRAMMING CONFIGURING THE HARDWARE Fuses Leckie Advanced Bond Ado es m arallel High Voltage Serial f Use Current Simulator Emulator FLASH Memory Karl F data wor
161. onnection to FPGA 125 Edge Connector 125 PCI Connector Pin Layout 126 VCCO 125 PCI Interface 124 Connection to FPGA 124 Further Infornation 131 Hardware Setup 130 Present Signals 130 Pletronics LV1145B LVDS Outputs 93 Polyswitch Resetable Fuse 75 Power 132 External Power Connector 134 Indicators 134 In System Operation 132 Monitors 134 Standalone 133 Powering ON the DN6000k10SC FastBoot 12 Powering ON the DN6000K108C 11 PowerPC 405 Data Cache 17 Data Pipeline 17 Debug Trace 17 Embedded cote 17 General Purpose Registers 17 Hardware arithmetic unit 17 IBM CoreConnect 17 Instruction Cache 17 MMU 17 Power Consumption 17 Time 17 PowerPC 405 Core 17 PowerPC Clock 91 Methodology 91 Precautions 6 R Relevant Information 4 Reset DN6000K10SC User Guide ww w dinigroup com Boatd 94 PPC 96 Rocket IO 17 CDR 18 Channel Bonding Support 18 Comma Detection 18 Data Rate 17 Encoder Decoder 18 Internal Interface 18 Levels of output differential voltage 18 On chip Terminations 18 Per channel internal loopback modes 18 Power Supply Voltage 18 Rate matching 18 Selectable Pre emphasis 18 SERDES 17 Trancievers 18 RocketIO Clocking Methodology 91 S Sanity Check 58 63 Command Line Options 63 SelectMAP 52 DIP_SW3 60 DS1 DS2 LEDs 60 FPGA MSELO 60 MSELA 60 FPGA_MSEL2 60 Starting SelecMAP Configuration 60 SMA 116 Connection to FPGA 116 CPU Debug 1
162. ord 2 2 1 Description 2 2 2 Pru m 159 2 2 3 159 2 2 4 INO LE LA Cuv SENN CRE 159 2 3 bar write 2 3 1 Description 160 2 3 2 Arguments 160 2 3 3 160 2 3 4 nol 2 4 bar read byte 2 4 1 Description 2 4 2 Dus IM E 2 4 3 Return Values 2 4 4 INGLES Asc 161 2 5 DOT read WOT 162 2 5 1 Description 162 2 52 Arguments 162 2 5 3 Return Values 162 2 5 4 162 2 6 bar 1AM AWOTE 163 2 6 1 Description 2 6 2 Pun 1 ER 163 2 6 3 Return e P RR cin 163 2 6 4 Notes 163 27 buffer allocate 164 2 7 1 Description 164 2 7 2 1
163. ors 11 2 3 Power Indicators 12 TEST HEADER amp DAUGHTER CARD CONNECTIONS ce EE REPE BR Nae TENER NUES 135 12 1 Test Header 12 1 1 Test Header Connector 137 12 1 2 Test Header Pino Nu mbefing ete oe te ent E t ORTI Ie edet 137 12 2 DN3000K10SD Daughter Card 12 2 1 Daughter Card LED s 12 2 2 Power Supply 142 12 2 3 Unbuffered riana EE ENAA SEA ANE 143 12 2 4 Buffered IOn 143 12 2 5 LVDS IO 12 2 6 Connection between FPGA and the Daughter Card 4 1 144 13 MECHANICA T 151 IbqeemU E 154 1 APPENDIX AETEST INSTALLATION 5 8 154 1 1 DOS and Windows 95 98 ME using DPMI eee Ape S R 154 1 2 Windows 98 ME using a VxD driver 1 3 Windows 2000 XP 1 4 ric 1 5 1 6 Solaris 2 APPENDIX B AETEST BASIC CHF FUNCTIONS 158 2 1 bar write byte nosses 2 1 1 Description 2 1 2 Arguments 2 1 3 inam me 158 2 1 4 in c M M M 2 2 bar write w
164. peeds refer to Xilinx datasheet 32MB SmartMedia Card with reference design and main txt 32M B SmartMedia Card for customer use blank FlashPath Adapter to copy bit files to the SmartMedia Card s RS232 Serial cable female to female 6ft IDC 10 pin to DB 9 pin adaptor cable Jumpers 0 1 10 5 lt 5 5 Documentation Reference CD DN6000K 10SC User Guide ww w dinigroup com 7 ABOUT THIS MANUAL Optional items that support development efforts not provided Xilinx ISE software cable Coax loop back cables Daughter Card ATAVRISP kit for MCU reprogramming 3 Installation Instructions 3 1 J umper Setup Figure 2 indicates the factory jumper configuration of the DN6000K10SC DN6000K 10SC User Guide ww w dinigroup com ABOUT THIS MANUAL Lem Eu DS 1 oie ww w dinigroup com Figure 2 Default Jumper Setup describes the functionality of the installed jumpers on the DN6000K10SC 3 2 J umper Description Table 1 DN6000K10SC User Guide ABOUT THIS MANUAL Table 1 Jumper Desctiption Jumper Installed Signal Name Description JP1 1 2 PRSNT1 Configured for 25W power setting JP2 1 2 JP2 7 8 PCIXCAP PCI M66EN PCI interface configured for conventional PCI at 33MHz JP5 A1 B1 CLOCKA CLOCKB Oscillator X4 connected to RoboClock 2 U26 Oscillator X5 connected to
165. ple channels allowing for even higher data transfer rates For additional information on RocketIO transceivers see the RocketlO Transceiver User Guideon the Xilinx website The DN6000K10SC board has 4 RocketIO transceivers available on the top side of the FPGA that are routed to discrete SMA connectors 7 1 SMA Connectors The SMA connectors allow for direct connection the FPGA MGT interfaces 7 1 1 FPGA to SMA Connector The DN6000K10SC board provides four discrete MGT channels The connection between the FPGA and the SMA connectors is fairly simple involving only one wire per connector as well as a few capacitors and resistors to AC couple the signals These connections are also shown in Table 24 Table 24 Connections between FPGA and SMA Connectors Signal Name Connector SMA1_TXP 19 SMA1 TXN 21 SMA1 18 SMA1 RXN 20 SMA2 TXP 115 SMA2 TXN 17 SMA2 RXP J14 SMA2_RXN 116 SMA3 TXP jo SMA3 TXN j12 SMA3 J8 GIGI EIGE Gre UE UG SMA3 RXN 111 4_ 3 SMA4_TXN 16 SMA4 jp DN6000K 10SC User Guide www dinigroup com 116 BOARD HARDWARE Signal Name i Connector SMA4 RXN 15 Please note the RocketIO Transceiver performance in Table 25 Table 25 RocketIO Performance Grade RoicketIO Tranceiver FF 25 2 0 PowerPC Processor Block 400 350 300 8 CPU Debug and CPU
166. press b e Jump View a newly specified location press The user will be prompted for the new address in hex e Goto Return to the original address specified at the beginning press 0 e Quit Return to Memory Menu press q MWINNTSystem32 cmd exe aetest_wdm 2 4 8 18 14 18 ic 55555555 aaaaaaaa 55555555 aaaaaaaa 55555555 aaaaaaaa 55555555 aaaaaaaa abcdef45 aaaaaaaa 55555555 aaaaaaaa 55555555 55555555 55555555 aaaaaaaa 55555555 aaaaaaaa 55555555 aaaaaaaa 55555555 aaaaaaaa 55555555 aaaaaaaa 55555555 aaaaaaaa 55555555 aaaaaaaa 55555555 aaaaaaaa 83a62e16 14739147 17084 26 ifc98ebi 0648 bfa398cb 98 f51e88b2 54434c6e a2b 851ec 8ab932ae 769e4068 485699 f85d79e5 40d9e9ad 42 2 9 86680d7da eGf4cfdb 94309255 ee988827 2165bb 7f 006648 Sd ddbbS 548284 9c1466d6 ff81f215 487946e4 d63b768e 602446a5 b9bfeb2e cOBcc8he dee75c77 2 498 4 0321004 58f52258 197ac416 41 5 14dbfGeb b3e81569 562adf3f 299 063 8 4 92 5e868b55 2 90 4 2 755eci35 4 2 99 866 8465 2847a72b 95263291 8224db6d fie3 cO1 719422c2 76794186 8cia6925 9ff3bbii 542874dc 7aabb7ac 73d22a8d f5f8f140 1923 98 3ib6fc3e 2034 2 47388 cU9873e6 36 24318 81914fbe f737ae23 47c3ce2b cf6d9591 5451440 bd57458b b44df 9c 4416 61 12 6367 67b699c5 113869dc 14937 1 8 4 4 1448 28 880025 ba3eb8ci 26885 49833020 6081d5ba d895f 88a 6659c3ce 1d6d95c6 a4caBd8f dcbb
167. ps and are bi directional The data strobe signals are responsible for actual clocking in the data on rising and falling edges of the clock Finally the data mask signals can be used to enable or disable the reading and writing of some of the bytes in a 16 bit word transaction DN6000K10SC User Guide Www dinigroup com 112 BOARD HARDWARE Table 23 Connection between FPGA and DDR SDRAM Signal Name FPGA Pin DDR FPGA 6A ADDO U13 AA27 DDR FPGA 6A ADD1 U13 AB30 C DDR FPGA 6A ADD2 U13 AB29 DDR FPGA 6A ADD3 13 AD33 DDR FPGA 6A ADD4 13 AA26 C DDR FPGA 6A ADD5 13 25 G DDR_FPGA_6A_ADD6 13 AC32 DDR FPGA 6A ADD7 13 AC31 C DDR FPGA 6A ADDS8 U U U U U U 13 AD34 C DDR FPGA 6A ADD9 U13 AE34 DDR FPGA 6A ADD10 U13 AB28 ci DDR FPGA 6A ADD11 U13 AB27 ci DDR FPGA 6A ADD12 U13 AC29 c DDR FPGA 6A ADD13 U13 AC28 C DDR 6A DATAO U13 Y34 DDR 6A DATA1 U13 AA34 DDR 6A DATA2 U13 W30 DDR 6A DATA3 U13 W29 DDR 6A DATA4 U13 W28 DDR 6A DATA5 U13 W27 DDR 6A DATA6 U15 Y29 DDR 6A DATA7 U13 Y28 DDR 6A DATAS8 U13 W26 DDR_6A_DATA9 U13 W25 DDR_6A_DATA10 113 532 DDR 6A DATA11 U13 AA31 DDR 6A DATA12 U13 AA30 DDR 6A DATA13 DN6000K10SC User Guide U
168. ramming Connector 70 Oscillator X1 72 RS232 Interface 70 RS232 modes of operation 70 Serial and JTAG Configuration 73 G Getting Started 6 GNU Tools 41 H HyperTerminal 51 Interactive Configuration Menu 63 Main menu Options 61 RS232 Port Configuration 51 I iMPACT 42 ISE 20 place and route 21 Architecture Wizards 20 Boundary Scan Mode 43 EMI Management 22 HSPICE Models 22 IBIS Models 22 Incremental Design 21 PACE 20 ProActive Timing Closure 20 STAMP Models 22 Synplicity 21 System IO 22 22 JTAG 42 Connection to CPLD 77 Schematic 77 Jumpers 8 CDS0 10 CDS1 10 84 50 84 CLOCKA 9 CLOCKB 10 0050 10 84 DDS1 10 84 Description 9 DN6000K10SC User Guide www dinigroup com EDSO 11 86 EDS1 11 87 FBDIS1 86 FBDIS2 86 FBDS01 84 FBDS02 10 85 FBDS11 10 85 FBDS12 85 01 84 2 85 FS1 10 84 FS2 10 85 MODEF1 11 86 MODE 11 86 OSCA 10 85 OSCB 10 85 PCIXCAP 9 PRSNT1 9 RBCFO 84 RBCF1 84 RBDFO 84 RBDF1 84 RBEFO 86 RBEF1 86 REFSEL1 10 85 REFSEL2 10 85 LEDs 121 GPIO 122 HSF 123 Status 121 Test Points 122 LOGIC Emulation Kit 6 M MCU Atmel AVR Cable 47 AVR Studio 48 IAR Compiler 47 Programming 47 RS232 Port 48 Mechanical 152 Memory 96 DDR Power Supply 112 DDR SDRAM 109 APPENDIX Flash 96 SSRAM 99 SSRAM Configuration 102 SSTL2 Termination 111 P PCI C
169. rd Recognition Figure 4 DN6000K10SC Not Found Figure 5 Main Menu Figure 6 PCI Menu Figure 7 Memory Menu Figure 8 Memory Write DWORD Figure 9 Memory Read DWORD Figure 10 Memory Write Read DWORD Figure 11 BAR Memory Fill Figure 12 Bar Memory Write Figure 13 Bar Memory Display Figure 14 Bar Memory Range Test Figure 15 Bar Memory Address Data Bitwise Test Figure 16 Flash Menu Figure 17 Daughter Board Menu Figure 18 New Project Screen Shot Figure 19 Input File Figure 20 New Project Dialog Box Figure 21 Project Navigator Figure 22 Main Menu Figure 23 Interactive Configuration Option Menu Figure 24 DN6000K10SC Block Diagram Figure 25 Bankout Diagram Figure 26 MCU Programming Connector Figure 27 MCU Serial Port Figure 28 CPLD Programming Header Figure 29 SmartMedia Connector Figure 30 FPGA JTAG Connector Figure 31 Clocking Block Diagram Figure 32 LVPECL Clock Input and Termination Figure 33 Clock Source Jumper Figure 34 Roboclock Schematic Figure 35 RoboClock Functional Block Diagram Figure 36 RoboClock Configuration Jumpers Figure 37 DDR DCM Implementation Figure 38 PPC External Clock Figure 39 REFCLK BREFCLK Selection Logic Figure 40 LVPECL Reference Clock Oscillator Interface Figure 41 LVPECL Reference Clock Oscillator Interface DCI Figure 42 LVDS Reference Clock Oscillator Interfa
170. regulators in the Power Supply may require an external load to operate within specifications since the DN6000K10SC may not meet the minimum load requirements The Dini Group recommends attaching an old disk drive to one of the spare connectors 11 2 1 External Power Connector Figure 63 indicates the connections to the external power connector This header is fully polarized to prevent reverse connection and is rated for 250VAC at 13A 5V 12V Figure 63 External Power Connection Note Header P9 is not hot plug able Do not attach power while power supply is ON 11 2 2 Power Monitors Two triple supply monitors U4 U2 are used to monitor the 1 5V 2 5V and 3 3V supplies for more information on these devices please refer to the datasheet for the LT1326 from Lineat Technology These power supply monitors also provide a push button reset input that is utilized to reset the various sub circuits of the DN6000K10SC After power up PWRRSTn remains asserted for approximately 200ms 11 2 3 Power Indicators There are six LED s on the DN6000K10SC used to indicates the presence of the following voltage sources refer to Table 33 Table 33 Voltage Indicators Voltage Source 2 5V 3 0V used for PCI only 3 3V 5V DN6000K10SC User Guide Www dinigroup com 134 BOARD HARDWARE Voltage Source 12V 12V 12 Test Header amp Daughter Card Connections 12 1 Test Header The DN
171. roup com 164 APPENDIX 2 8 dma buffer free dma buffer free is a high level function C function which is recommended for development by users of the DN6000K10SC 2 8 1 Description buffer free allows users of the DN6000K10SC to free memory associated with a previously allocated DMA buffer 2 8 2 Arguments The argument s for dma_buffer_free are shown in Table 43 They are listed in order Table 43 dma_buffer_free Arguments Argument Description dma_buffer_handle hndl Handle for a DMA buffer typedef int dma_buffer_handle 2 8 3 Return Values A successful function call will return zero If 2 is returned the DPMI implementation of AETEST is not being used See Notes 2 8 4 Notes The dma_buffer_free code is written for use in the DPMI DOS implementation of AE TEST DN6000K10SC User Guide www dinigroup com 165 APPENDIX 2 9 dma write dword dma write dword is a high level function C function which is recommended for development by users of the DN6000K10SC 2 9 1 Description dma write dword allows users of the DN6000K10SC to write a dword of data to any byte aligned location in a DMA buffer 2 9 2 Arguments The arguments for dma write dword are shown in Table 44 They are listed in order Table 44 dma_write_dword Arguments Argument Description dma_buffer_handle hndl Handle for a DMA buffer int offset Offset in bytes of the write location in the DMA buffer dword
172. s the software application DN6000K10SC User Guide www dinigroup com 22 INTRODUCTION TO VIRTEX II PRO AAND ISE e Simulates the hardware description e Simulates the hardware with the software application e Simulates the hardware into the FPGA using the software application in on chip memory e Runs timing simulation e Configures the bitstream for the FPGA DN6000K10SC User Guide www dinigroup com 23 INTRODUCTION TO THE SOFTWARE TOOLS Chapter Introduction to the Software Tools This chapter introduces the software tools as well as references to more information 1 Exploring the Software Tools 1 1 AETEST AETEST utility program is used primarily to test and verify the functionality of the DN6000K10SC Logic Emulation board All AETEST source code is included on the CD ROM shipped with your DN6000K10SC Logic Emulation kit AETEST can be installed on a variety of operating systems including DOS and Windows 95 98 ME using DPMI DOS Protected Mode Interface e Windows 98 ME using a VxD driver Windows 2000 XP Windows WDM e Windows NT Linux e Solaris Detailed installation instructions for each version may be found in Appendix Appendix A AETEST Installation Instructions DN6000K10SC User Guide www dinigroup com 24 INTRODUCTION TO THE SOFTWARE TOOLS The AETEST utility program contains the following tests PCI Test Memory Tests SRAM amp DDR FLASH Test Daughter Card Test with or witho
173. signal The frequency of the JTAG clock signal can range from 0 MHz DC to one half of the processor clock frequency The JTAG debug port logic is reset at the same time the system is reset using TRST When TRST is asserted the JTAG TAP controller returns to the test logic reset state Refer to the PPC405 Processor Block Manual for more information on the JTAG debug port signals Information on JTAG is found in the IEEE standard 1149 1 1990 8 1 1 CPU Debug Connector Figure 57 shows JP3 the vertical header used to debug the operation of software in the CPU This is done using debug tools such as Parallel Cable IV or third party tools This connector cannot be used when the Mictor connector is in use PPC JTAG TDO D PPC JTAG TRSTn HEADER 8X2 DN6000K10SC User Guide Www dinigroup com 118 BOARD HARDWARE Figure 57 CPU Debug Connector 8 1 2 CPU Debug Connection to FPGA The connection between the CPU debug connector and the FPGA are shown in Table 26 These signals are attached to the PowerPC 405 JT AG debug resources using normal FPGA routing resources The JTAG debug resources are not hard wired to particular pins and are available for attachment in the FPGA fabric making it is possible to route these signals to whichever FPGA pins the user would prefer to use Table 26 CPU Debug connection to FPGA Signal Name FPGA Pin Connector 013 020 TDI 01319
174. stems o Integrated VHDL and Verilog design flows ChipScope Pro Integrated Logic Analyzer 0 13 um nine layer copper process with 90 nm high speed transistors 1 5V VCCINT core power supply dedicated 2 5V VCCAUX auxiliary and VCCO powet supplies e IEEE 1149 1 compatible boundary scan logic support Hip Chip and Wire Bond Ball Grid Array BGA packages in standard 1 00 mm pitch e Each device 100 factory tested 2 Foundation ISE 6 1i ISE Foundation is the industrys most complete programmable logic design environment ISE Foundation includes the industry s most advanced timing driven implementation tools available for programmable logic design along with design entry synthesis and verification capabilities With its ultra fast runtimes ProActive Timing Closure technologies and seamless integration with the industry s most advanced verification products ISE Foundation offers a great design environment for anyone looking for a complete programmable logic design solution 2 1 Foundation Features 2 1 1 Design Entry ISE greatly improves your Time to Market productivity and design quality with robust design entry features ISE provides support for today s most popular methods for design capture including HDL and schematic entry integration of IP cores as well as robust support for reuse of your own IP ISE even includes technology called IP Builder which allows you to capture your own IP and reuse it in other desig
175. uments The arguments for write dword are shown in Table 38 They are listed in order Table 38 bar write dword Arguments Argument Desctiption Possible Values unsigned long barnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 BAR5 5 unsigned long byte offset Address Number of bytes to Ox0 bytes in mem space offset data dword data A dword of data for the write 0 00000000 operation 32 bits Itypedef unsigned char dword 2 3 3 Return Values A successful function call will return zeto 2 3 4 Notes The source code for bar write dword is portable to each of the operating systems intended for AETEST usage DN6000K 10SC User Guide ww w dinigroup com 160 APPENDIX 2 4 bar read byte read byte is a high level function C function which is recommended for development by users of the DN6000K10SC 2 4 1 Description bar read byte allows users of the DN6000K10SC to read a byte of data from any location in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 4 2 Arguments The arguments for bar read byte are shown in Table 39 They are listed in order Table 39 bar read byte Arguments Argument Desctiption Possible Values unsigned long barnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 or BAR5 5 unsigned lo
176. unction is useful when the user is debugging Device ID configuration accesses 5 Progressive loop on all PCI Loops on device number 0 reading the Vendor ID and device numbers with Device ID function moves onto the next device display Vendor and Device number 1 when the user presses a key The function ID moves all the way through device number 0 to device number Ox7F in case there are any bridges on your PCI bus 5 Display all PCI information Reads and displays all of the configuration space for the for PCI device function 7F 0 active device and function number Use options S and F to change the active device and function numbers respectively Then use this option to view the entire configuration space DN6000K10SC User Guide ww w dinigroup com 29 INTRODUCTION TO THE SOFTWARE TOOLS Option Function Name Desctiption 6 Write Config DWORD Allows the user to write to configuration space The following text will appear to remind the user what is in configuration space for a PCI device PCI CS VENDOR ID 00 PCI CS DEVICE ID 0x02 PCI 5 COMMAND x04 PCI CS STATUS 0 06 PCI CS REVISION ID x08 PCI CS CLASS CODE 0x09 PCI CS CACHE LINE SIZE 0 0 PCI CS MASTER LATENCY PCI CS HEADER TYPE PCI CS BIST OxOf PCI CS BASE ADDRESS 0 0x10 PCI CS BASE ADDRESS 1 X14 PCI CS BASE ADDRESS 2 0x18 PCI CS BASE ADDRESS 3 lc PCI CS BASE ADDRESS 4 0x20 PCI CS BASE
177. ure 12 Bar Memory Write The transaction shown in Figure 12 writes the DWORD Oxabcdef45 to address 0x200020 of SSRAM 2 See option Bar Memory Display for a view of the results of this transaction Bar Memory Display Opt 8 Bat Memory Display enables to user to view 160 DWORDS of PCI memory space All 4 gigabytes of memory space is accessible Figure 13 shows a sample view The user will be prompted to choose a starting address upon selecting the Bar Memory Display function Input starting address hex 32 bit aligned The address must be in hexadecimal and 32 bit aligned A screen similar to the one shown in Figure 13 will be outputted to the screen after entering the starting address The screen will contain 20 lines of which each line lists 8 DWORDs of data Combining the very first line and the first column on the screen specifies the corresponding address of each DWORD For example the DWORD of data 0x1663669b in column 5 row 6 is associated with 0x200080 column 1 and c row 1 Consequently the address is 0x20008c Some viewing options are listed in the final line of the screen To select an option the user needs to press the key corresponding to the letter number contained in the parentheses The options are Forward View the next 160 DWORDS of data press f DN6000K 10SC User Guide ww w dinigroup com 36 INTRODUCTION TO THE SOFTWARE TOOLS e Back View the previous 160 DWORDs of data
178. ure the FPGA in SeleccMAP mode 4 5 Bitstream Encryption Virtex II Pro devices have an on chip decryptor using one or two sets of three keys for triple key Data Encryption Standard DES operation Xilinx software tools offer an optional encryption of the configuration data bitstream with a triple key DES DN6000K 10SC User Guide ww w dinigroup com 64 PROGRAMMING CONFIGURING THE HARDWARE determined by the designer The keys are stored in the FPGA by JTAG instruction and retained by a battery connected to the VBATT pin when the device is not powered Virtex II Pro devices can be configured with the corresponding encrypted bitstream using any of the configuration modes described previously A detailed description of how to use bitstream encryption is provided in the Vrfex I Pro Platform FPGA User Guide DN6000K 10SC User Guide ww w dinigroup com 65 BOARD HARDWARE Chapter Board Hardware l Introduction to the Board DN6000K10SC Logic Emulation board provides for a comprehensive collection of peripherals to use in creating a system around the Virtex II Pro FPGA Figure 24 is a block diagram of the DN6000K10SC Logic Emulation board 7 T ROCKET 10 INTERFACES E DN6000K10SC
179. used in conjunction with SSTL 2 signaling standard as well as differential clocks DDR SDRAM operates as a source synchronous system in which data is captured twice per clock cycle using a bi directional data strobe to clock the data The DDR SDRAM control bus consists of a clock enable chip select row and column addresses bank address and a write enable Commands are entered on the positive edges of the clock and data occurs for both positive and negative edges of the clock The double data rate memory utilizes a differential pair for the system clock and therefore has both a true clock CK and complementary clock CK signal 6 3 2 DDR SDRAM Configuration The DDR SDRAM memory components on the DN6000K10SC are arranged as a 16 bit mode refer to Figure 53 Made up of two discrete parts U17 and U18 the standard components used are 32Mb x 16 parts organized as 8 million deep by 16 bits wide and 4 banks This provides for a total capacity of 128 Mbytes for the system for more information refer to Micron s datasheet PN MT46V64M106 The larger 64Mb x 16 parts are available and the DN6000k10SC can support these larger devices DN6000K10SC User Guide www dinigroup com 109 BOARD HARDWARE DDR FPGA 6A_ADDO DDR ADD ADD ADD ADD4 ADD _ ADD6 A A A A A A 007 A A A A A DDR 6A DQO 6 ADDIO 0010 ADDIT DDR 6A ADD DDR 6A DQ12 ADD DDR 6A DDR 6A 0014
180. ut cables BAR Memory Range Tests AETEST also provides the user with the following abilities Recognize the DN6000K10SC Read FPGA F Revision Display Vendor and Device ID Set PCI Device and Function Number Display all configured PCI devices Various loops for PCI device function and ID numbers Write and Read Configuration DWORD Write DWORD Read DWORD and Write Read DWORD Same Address BAR Memory Fill Write and Display Configure Save BAR s from to a file All of AETEST s tests and functionality are based upon simple C functions Descriptions of variety of functions may be found in DN6000K10SC User Guide www dinigroup com 25 INTRODUCTION TO THE SOFTWARE TOOLS Appendix B AETEST Basic C Functions NOTE All of the screen captures are taken from the aetest wdm exe implementation of the AETEST utility program unless otherwise noted Certain functions may be missing from the figures However all functions will be discussed in their proper context 1 1 1 Getting Started with AETEST Once AETEST is installed and the DN6000K10SC board is powered on the user can execute his her incarnation of AETEST The DN6000K10SC is defined by its DEVICE ID of 0x1600 or 0x1605 0x1606 0x1607 and its VENDOR ID of 0x17df AETEST should immediately recognize the DN6000K10SC Logic Emulation board shown in Figure 3 CA WINNT System32 cmd exe aetest_wdm exe E nj xj icrosoft Windows 2000 Version 5 88 2195 lt C gt

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