Home

PCF50633

1. PCF50633 Power supply and battery management controller Rev 06 05 March 2008 User manual Document information Info Content Keywords PCF50633 PMU I2C bus USB charger DC to DC converter Abstract This document introduces and describes the features and operation of the PCF50633 power supply and battery management controller founded by Philips NXP Semiconductors PC F50633 PCF50633 User Manual Revision history Rev Date Description 06 20080305 Supersedes PCF50633 5 Modifications File prepared for worldwide distribution 05 20080128 Supersedes PCF50633 4 Modifications e Min value for AUTO parameter Vo changed from Vo prog 3 to Vo prog 5 Table 47 04 20071127 Supersedes PCF50633 3 Modifications Application diagram revised Figure 61 HCLDO min programmable o p voltage value changed from 1 0 V to 0 9 V Table 2 Table 75 and Table 88 USB current limit lim us8x min typ values changed from 900 950 to 800 900 respectively when limit set to 1000 mA and from 425 462 to 400 450 respectively when limit set to 500 mA Table 91 e Voltage drop across the USB SYS FET AVysg svs changed from 200 mV to 235 mV Table 91 03 20070720 Supersedes PCF50633 2 Modifications e HUQFN68 and HUQFN88 packages discontinued Error in package layout drawing corrected B1 0 20 0 16 Figure 62 Parameter values updated e Soldering guidelines updated
2. Pc Software Control sysok Fig 18 SVM block diagram PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 36 of 125 NXP Semiconductors PC F50633 8 4 4 8 4 5 8 4 6 PCF50633UM 6 PCF50633 User Manual Hardware interface Table 34 SVM characteristics Vss REFGND GND O V Tamp 40 to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Vith sysok system OK threshold range 28 34 V voltagel programmable in 100 mV steps accuracy 2 Vim sysk 2 Vin sysok ys hysteresis of system OK 0 04 x V threshold voltage Vih sysok tdeb SVM debounce time for low system 5 62 4596 ms voltage condition rising edge only 1 If the system voltage drops below Vin sysok a lowsys interrupt is generated and the sysok status bit is reset see Table 14 and Table 20 Software interface Table 35 SVMCTL SVM control register address 19h bit description Bit Symbol Access Reset Description 0 svmlow R 0 SYS pin voltage is higher than the programmed threshold 1 SYS pin voltage is lower than the programmed threshold 3 1 svmlvi R W 21 Vin sysok threshold level 000 n a 100 3 10 V 001 2 80 V 101 3 20 V 010 2 90 V 110 3 30 V 011 3 00 V 111 3 40 V 4 svmdisdb R W 0 0 enable 62 ms debounce filter 1 disable 62 ms debounce filter 7 5 reserved 1 This register is reset in NoPower state
3. i INTC h N thermsistor Mein battery i Lj aaa aaa REFGND Fig 44 Battery temperature measurement circuit around the MBC 8 13 Backup Battery Charger BBC 8 13 1 Introduction The BBC module charges a backup battery cell from the SYSx node A constant current algorithm is implemented 8 13 2 Features PCF50633UM 6 Voltage limited current source Output resistor to reduce the current at higher voltages Four programmable charge currents Two programmable maximum limiting voltages The BBC can only be enabled in the Active state NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 93 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 8 13 3 Block diagram SYSx 2c Software Control Fig 45 BBC block diagram 8 13 4 Hardware interface Table 104 BBC characteristics Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit VBUBAT backup battery supply voltage 1 6 3 V leguBATr Charge current on pin BUBAT bbcc 00 35 50 65 uA bbcc 01 70 100 130 uA bbcc 10 130 200 270 uA bbcc 11 250 400 550 uA Vim guBAT limiting voltage on pin BUBAT bbcv 0 2 37 2 50 2 63 V bbcv 1 2 85 3 00 3 15 V bbcv 0 Tamb 25 C 2 42 2 50 2 58 V bbcv 1 Tamb 25 C 2 91 3 00 3 09 V VDELTA voltage range where output curre
4. Bit Symbol Access Description 0 led on R W if set LED converter is ON led_pic R W if set LED is ON when GPIO1 1 led_p2c R W if set LED is ON when GPIO2 1 led_p3c R W if set LED is ON when GPIO3 1 5 4 led_ena_act R W selects activation phase 00 ACTPH1 01 ACTPH2 10 ACTPH3 11 ACTPH4 7 6 reserved 1 This register is reset at each transition to Standby state PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 60 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 10 6 8 10 6 1 PCF50633 User Manual Table 69 LEDCTL LED control register address 2Ah bit description Bit Symbol Access Reset Description 0 led ovpon R W 1 0 overvoltage protection disabled 1 overvoltage protection enabled 1 led_ovprstl2l R W 0 0 no action 1 resets overvoltage protection 2 led_ocp R W 0 0 OCP limit is 1000 mA 1 OCP limit is 500 mA 7 3 reserved 1 This register is reset at each transition to Standby state 2 This control bit is not automatically cleared Table 70 LEDDIM LED ramp control register address 2Bh bit description Bit Symbol Access Reset Description 7T 0 led dimstep R W 00000001 binary coded step time for dimming curve tdimstep 16 x led dimstep 32768 1 This register is reset at each transition to Standby state Table 71 ALMGAIN Ambient lighting gain factor register address 4Fh bit description Bit Symbol Access Reset
5. The default reset KEEPACT mode is variant dependent see Table 7 Debounce filters Many control signals in the PCF50633 can be debounced to avoid responding to signal spikes Debounce filters are enabled in all states Debounce times are programmable The timing diagram in Figure 14 applies to all debounce filters in the PCF50633 undebounced i A ia tdebounce tdebounce A A debounced interrupts falling edge rising edge The debounced signal retains its original value until the new value has been stable for at least the selected debounce time A spike gt 30 ms in the original signal will reset the debounce timer The filter suppresses all signal activity shorter than the debounce time Fig 14 Definition of debounce filter COLDBOOT flag The coldboot flag indicates that the PCF50633 has been in NoPower state before entering Active state NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 26 of 125 NXP Semiconductors PC F50633 8 1 6 14 8 2 8 2 1 8 2 2 8 2 3 PCF50633UM 6 PCF50633 User Manual The status of the colaboot flag can be determined by reading bit 3 of the OOCSHDWN control register see Table 8 The host controller should read the coldboot flag once the PCF50633 enters the Active state The only way to clear the colaboot flag is by programming it to 0 via the I C bus serial interface It is not possible to set the coldb
6. 61 Control functionality 61 Ramp control 2 veces ed gx RE 62 Overvoltage protection 62 Overcurrent protection 62 Inrush current limiting 62 Generating output voltages over Vo LED maxy 63 Generating a 5V USB supply 64 Ambient light monitor 65 Linear regulators AA 66 Introduction 66 Dl UA 66 Block diagram a 66 Hardware interface 67 Software interface 69 Functional description 73 LDO1 to LDOG 0na naaa e Rn s 73 BOlDQ 2o aes PRA ANNA EYE Ren EE 73 Output pull down aana 74 Switch mode vied cs cee ssw ARKADA ANG 74 Main Battery Charger MBC 74 Introduction 74 CU AA 74 Block diagram a 75 Hardware interface 75 Software interface 77 Functional description 81 Charger circuit arrangement 81 USB input zz secedere En Dh REG 81 Adapter input 0 eee 82 Current definition pin CHGCUR 82 Functional description of charger controller 82 MBC operating modes 85 Charging phases 04 89 Precharge phases 89 Fast charge phases 91 Die Temperature control during charging 92 Battery temperature detection circuit 92 Backup B
7. Battery not fully charged The USB SYS FET will be conducting as long as the USB can deliver the current needed by the system If the USB current budget is greater than that required by the system plus the battery charger the excess will be used to charge the battery This situation is illustrated in Figure 40 below External Adapt SYS PFET Adapter 1 h System USB Errare uem M TATA KANTA KATANA n USB to SYS path USB SYS FET tu 1 ra CORE d 1 charger 1I pa i gt 7 USB charger a aaa Pale man USB to BAT path battery USB BAT FET 77 Fig 40 Current flow during USB charging system takes less than USB budget If the requirements of the system plus the battery charger exceed the USB current budget the USB BAT FET current limiter will be activated At the same time the usblim chg bit in the MBCS3 control register see Table 102 will be set indicating that the charge current is no longer equal to the programmed value If the current in the USB BAT FET falls to zero the USB SYS FET current limiter will be activated and the usblim play bit in the MBCS3 register will be set A usblimon interrupt will be generated signalling that current limiting has been activated in the USB to SYS path The USB SYS FET will act as a current source Since the system now requires more current than the USB SYS FET can deliver Vsys will begin to fall When Vsys drops below Vppr the idea
8. Description 4 0 alm gain R W 00000 ambient light processing gain factor 7 5 reserved 1 This register is reset at each transition to Standby state Table 72 ALMDATA Ambient light intensity data register address 50h bit description Bit Symbol Access Reset Description 7 0 alm data R 00000000 ambient light intensity data 1 This register is reset at each transition to Standby state Functional description Control functionality The LED converter employs a pulse frequency mode control scheme which regulates the voltage between the LEDFB and LEDFBGND pins Vj gprp This voltage which determines the dimming level is set via the ed out control bits in the LEDOUT register see Table 67 The sense resistor connecting these pins transforms this voltage into a current in the LED string The maximum and default LED current through the sense resistor is defined by the formula liep L25 Rsgygg A 1 The default value for led out 111111 is assumed in the above equation A lower continuous current level can be set by changing the value of led out see Table 67 The voltage across Rsense is determined by the formula NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 61 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 10 6 2 8 10 6 3 8 10 6 4 8 10 6 5 PCF50633 User Manual eled out 20 ViEDFB aag SOM V 2 Ramp control The ramp controll
9. 2 Reset values are determined by the IC variant see Table 7 Functional description Figure 19 illustrates the behavior of the SVM NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 37 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 5 8 5 1 8 5 2 PCF50633 User Manual V Vsys Vih sysok i Vih sysok hys sysok status tdeb SVM tdeb SVM lowsys interrupt Fig 19 Functional behavior of the SVM module The SVM monitors the system voltage Vsys the voltage on pins SYS1 and SYS2 at all times As long as Vsys remains above Vin sysok the sysok status bit in the OOCSTAT control register will be 1 see Table 14 If the system voltage drops below Vin sysok a owsys interrupt is generated and the sysok status bit is set to 0 The threshold voltage Vinsysok is determined by the svmlvi control bits in the SVMCTL register see Table 35 When a low system voltage is detected in Active state the host controller should initiate a transition to Save If this doesn t happen within 8 seconds of a lowsys interrupt being generated the OOC will force the PCF50633 to the Save state to prevent the battery becoming excessively discharged A hysteresis and debounce filter is built in to prevent rapid cycling of the lowsys interrupt signal The rising edge of the SVM low voltage signal is debounced with a debounce time of 62 ms The falli
10. 1 0 9 x Votprog 60 350 1 2 0 8 Max 200 5 5 5 5 3 6 42 5 Unit mA mV 96 9o mA mV V V dB mV kQ mA Q Q 1 AVio is defined as the voltage difference between input and output when the output is 1 below a reference voltage Vref and is the minimum voltage drop required to ensure reliable operation Vpep is the voltage measured at the output with V set to Vo prog 1 V 2 Input to output resistance in Switch mode PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 68 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 8 11 5 Software interface Table 76 LDO1OUT LDO1 output voltage select register address 2Dh bit descriptionl Bit Symbol Access Description 4 0 ldo1 out R W Votprog 0 9 ldo1 outx 0 1 V max 3 6V e g 00000 0 9 V 00001 1 0 V 11000 3 3 V 11011 3 6 V 11111 3 6 V 5 ldo1 swnod R W 0 linear regulator mode 1 switch mode 7 6 reserved 1 This register is reset at each transition to Standby state Reset values are determined by the IC variant see Table 7 Table 77 LDO1ENA LDO1 output enable register address 2Eh bit description Bit Symbol Access Description 0 Ido1_on R W if set LDO is ON Ido1_pic R W if set LDO is ON when GPIO1 1 Ido1_p2c R W if set LDO is ON when GPIO2 1 Ido1 p3c R W if set LDO is ON when GPIO3 1 5 4 ldot1 ena act R W selects activatio
11. 7 5 reserved 2 1 This register is reset in NoPower state 2 Reserved bits should be written 0 return values are not defined Table 128 RTCYRA RTC year alarm BCD value register address 66h bit description Bit Symbol Access Reset Description 7 0 yeara R W 11111111 year alarm value 00 to 99 coded in BCD format 1 This register is reset in NoPower state Functional description The RTC module is supplied from the internal supply VyisA and is active in all activity states except NoPower see Table 15 The RTC time date registers are reset to zero when the PCF50633 is in the NoPower state The time date registers can be programmed to any start time once in Active state It is recommended that the RTC interrupts second rtcalarm be masked before writing a new value to the time date registers to avoid interrupts being generated during the write cycles up to 7 register write cycles may be required to update the time date The PCF50633 compensates for leap years by adding a 29th day to February if the year counter contains a value exactly divisible by 4 The RTC unit contains an alarm function The alarm registers can be individually enabled by writing a value different from the reset value When one or more of the alarm registers is loaded with a valid time and or date the alarm register contents will be compared with the current time and date When all enabled comparisons match an rtcalarm interrupt is gene
12. Adapter 1 SYSx USB ob ntt Power management 5 9 USB Adapter Ideal charger Q charger iO diode AN Output control 2 Supplies lt ADC etc Charger BATx BUBAT Main 7 Backup battery T battery Fig 4 Charger and power management partitioning The power management unit features 4 activity states NoPower In the NoPower state both the system and the backup battery voltages are below their presence threshold levels Vsys lt Vih syspres and VeuBat lt Vth bubpres See Figure 6 There is insufficient energy available to power any of the internal circuits The system will change state from NoPower to Save when Vsys rises above Vin sysmin e Save In the Save state the power management section is supplied from either the system voltage if Vsys gt Vih syspres Or the backup battery if Vsys lt Vih syspres and VBUBAT gt Vih bubpres See Figure 6 Only the internal supplies the 32 kHz oscillator and the real time clock will be active The GPIOs will maintain their state If both the system and the backup battery voltages fall below there presence threshold levels Vsys Vih syspres and VBUBAT Vih bubpres the PCF50633 will revert to the NoPower state Standby In Standby state the power management section is supplied by the system voltage which will be above its OK threshold level Vinsysok is specified by the svmivi bits in the S
13. C a 7 OwM C i 18 34 TL UUU UUU 135 Lo 1 c ry C C Sa x LI e 4 a I 4 Eh EL e2 m EI Ee LIII Ei Ld gg i LIlv oa LLLA D Cj C LO Sm Y 51 NAM MNN termina 68 52 index area E Dn L3 0 3p ges scale DIMENSIONS mm are the original dimensions 1 UNIT aa A1 b by c DO Dp EQ En e e1 e2 L2 L3 v y yi 0 05 0 25 0 20 8 1 4 95 8 1 4 45 05 1 65 1 4 mm 1 o0 o15 016 79 465 79 415 04 64 9 o3 145 12 1 005 005 0 1 Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION ISSUE DATE 05 04 21 SOT852 2 id UU Eo CI 05 05 23 Fig 62 HVQFN68 package outline Note that the diepad is NOT square PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 120 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 14 Soldering Soldering guidelines for package HVQFN68 can be found in Application Note AN10365 Surface mount reflow soldering description PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 121 of 125 NXP Semiconductors PCF50633 15 Legal information PCF50633 User Manual 15 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval
14. LDO3 and LDO6 or 150 mA LDO4 and LDO5 In order to minimize pin count the LDO inputs are connected internally in pairs as follows LDO1 to LDO2 pin LDO12IN LDO3 to LDO4 pin LDO34IN and LDO5 to LDO6 pin LDO56 HCLDO This high current 200 mA linear regulator is equipped with current limiting capability This makes it suitable for powering an external slot sensitive to short circuit conditions or overload The current limit is set at 17596 of the maximum output current or 350 mA If the output current reaches this level the HCLDO will enter constant current mode and will generate a hcldoov interrupt after a programmable debounce time determined by the hcldo debovi bits in control register HCLDOOVL see Table 90 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 73 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 11 6 3 8 11 6 4 8 12 8 12 1 8 12 2 PCF50633 User Manual Output pull down An internal switch pulls down an LDO output when that LDO is disabled It will discharge the external output capacitor connected to the output pin through a resistor Rpa ext See Table 73 Switch mode An LDO will act as low ohmic switch if its associated dox swmod bit is set see Table 76 to Table 88 Output voltage control is disabled resulting in low power consumption To enable switch mode the regulator must be activated as described in Section 8 8 6 2 Two options are
15. Note that if the ONKEY push button is held down for more than one second during the ONKEY wake up transition an Active to Standby transition is not initiated the time out timer is not set and an onkey1s interrupt is not generated PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 22 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 1 6 5 8 1 6 6 8 1 6 7 PCF50633 User Manual EXTON control inputs Three inputs are provided to facilitate external activation The EXTONx inputs are intended to be connected to a variety of wake up sources such as an active user interface or external connectors They can be configured to initiate either wake up or shutdown transitions via the extonx mode control bits in the OOCMODE register see Table 12 Each of the extonx wake control bits bits 3 1 in control register OOCWAKE see Table 9 enables disables its respective EXTONXx input The inputs EXTON1 EXTON2 and EXTONS are functionally identical Programmable debounce filters are incorporated into the EXTONXx inputs The debounce time is determined by the setting of the extonx deb control bits bits 5 0 in control register OOCTIM1 see Table 10 The status of the EXTONx pins HIGH or LOW can be determined by reading bits 3 1 of the OOCSTAT control register see Table 14 Two interrupts extonxr and extonxf see Table 18 are generated in response to activity on each of the EXTONx inp
16. Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information founded by NXP B V 2008 All rights reserved For more information please visit http Awww nxp com For sales office addresses please send an email to sales addresses www nxp com Date of release 05 March 2008 Document identifier PCF50633UM_6
17. States Activation Phases gt CLK32K RSTHC NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 11 of 125 NXP Semiconductors PC F50633 8 1 4 PCF50633 User Manual Hardware interface Table 5 OOC characteristics Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Vsvs system supply voltage Active mode 2 8 5 3 V lii input leakage current on EXTONx KEEPACT and 1 1 uA SHUTDOWN pins on ONKEY pin when input HIGH 1 uA on ONKEY pin when input LOW 15 10 5 uA Vit LOW level input voltage on ONKEY EXTONx KEEPACT and 0 a 0 5 V Vin HIGH level input voltage SHUTDOWN pins 0 8 5 5 V Rowint internal pull up resistance on ONKEY pin 300 KQ VoL LOW level output voltage on CLK32K and RSTHC pins pull up 0 2 0 4 V resistance gt 10 kQ lot LOW level output current on RSTHC and CLK32K pins 1 5 mA Tih die die threshold temperature 125 C Vih sysmin minimum system ON threshold 25 V voltage Vin syspes system threshold voltage for save no backup battery 1 7 2 2 3 V statel2 Vihbubpresy backup battery threshold voltage for 1 1 3 1 6 V save statel3 Vvisa voltage on pin VISA 24 V VREFC voltage on pin REFCHI 0 9 V IDD tot total supply current in Save state Vgar 2 5 V no USB 50 uA or adapter present in Standby state all supplies disabled 60 uA Ve
18. The delay between steps can be specified for each converter individually by means of the x dvmstep control bit bits 4 1 in the DOWNxCTL control registers see Table 56 and Table 60 The x dvmstep bit value specifies the number of 32768 Hz clock cycles between each 25 mV step When this value is set to 0000 the transition between current and target voltages will be immediate The duty cycle of both converters can reach 100 in which case the input voltage will approach the value of the target output voltage A pull down switch on the output of DOWN1 guarantees an output voltage of O V when the converter is switched off A pull down switch on the output of DOWN2 guarantees an output voltage of 0 V when both DOWN2 and MEMLDO are switched off NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 56 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 8 9 6 3 AUTO configuration The auto step up step down converter can be configured as a regular step down converter This facilitates the optimal use of all power switches for maximum efficiency The auto mod bit in the converter control register which is mask programmable determines the operating mode auto step up step down or down only mode see Table 52 AUTO can be configured to deliver a maximum output current of either 500 mA or 1100 mA Reducing the current capability from 1100 mA to 500 mA makes it possible to use smaller externa
19. Vo SHUTDOWN DOWN2LX MM Tu i KEEPACT DOWN2EB 22 uF TE 0805 ser ONKEY Em ga EXTON1 EESIN Eo gt o F 4 7 uF 253 EXTON2 LEDLX 3 EY o YIN o 52 EXTON3 474H po yp 2L 63V 2g Lo LEDOUT 0805 GPIO1 10uF XR5 g f GPIO2 LEDFB Tav A 4 S o A iea Dcos DP BOL o GPIO3 LEDFBGND XR5 White LED String oo GPO 519 Sal VSS LEDAMB 1nF S EN H7 1 6 3 V 0603 XR5 2 6 3 V 0402 XR5 3 Power inductors with sufficiently high current saturation ratings such as the TDK VLF3012 series should be used 4 Vsys is typically used as an input voltage for the AUTO DOWN converters and LDOs For greater LDO efficiency the outputs of the AUTO and DOWN converters can be used as inputs to the LDOs Fig 61 Typical application PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 119 of 125 NXP Semiconductors PCF50633 13 Package outline PCF50633 User Manual terminal 1 index area gt gt HVQFN68 plastic thermal enhanced very thin quad flat package no leads 68 terminals body 8 x 8 x 0 85 mm detail X A1 i J ant SOT852 2 C 4 1 NON posse HOvM C A Y1
20. bubpres 0 the system will return to the NoPower state when the system voltage falls below Vin syspres If a backup battery is present bubpres 1 the system will return to NoPower when the backup battery voltage falls below Vitn bubpres Transition from Save to Standby The PCF50633 will change state from Save to Standby when Vsys is greater than Vih sysok specified by the svmlvi control bits in register SVMCTL see Table 35 and the die temperature is below the maximum temperature threshold Tin die see Section 8 6 An additional condition may be imposed if a USB supply is connected In this case if bit usbbatchk in control register OOCCTL see Table 13 is set the PCF50633 will only change state from Save to Standby if Vgar is greater than Vin batok Transition from Standby to Save The PCF50633 will revert to the Save state if the system voltage drops below Vir sysok or the die temperature is above the maximum temperature threshold Tthdie see Section 8 6 If a USB supply is connected and bit usbbatchk in control register OOCCTL see Table 13 is set the PCF50633 will also revert to the Save state if Vgar falls below Vih batok NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 19 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual Transition from Standby to Active Several wake up events will cause the PCF50633 to switch from Standby to the Active state Note that t
21. synchronized with one of the activity phases discussed above in Section 8 1 6 8 and then released pulled HIGH after a pre determined period t sqe1 of between 3 and 26 ms trsdel allows time for the supply to the host controller to stabilize before the reset signal is released The activity phase is selected by the actphrst control bits bits 1 0 in register OOCCTL see Table 13 and the delay trsaei by the herstdel control bits bits 6 5 in register OOCTIM2 see Table 11 The RSTHC output pin is open drain requiring an external pull up resistor The synchronization and timing of the RSTHC signal is illustrated in the bottom trace of Figure 11 actphrst 10 When the voltage on the SYS pin drops below Vinsysmin emergency shutdown RSTHC goes LOW immediately in order to shut down the host controller CLK32K output A 32 678 Hz system clock is available on the CLK32K pin when activated The clock can be activated in Standby or Active states by setting stbclk32on or actclk32on respectively in the OOCCTL control register see Table 13 In the Active state the activation of the clock is synchronized with ACTPH1 as shown in Figure 11 The CLK32K pin has an open drain output allowing the appropriate voltage swing to be generated externally A typical value for an external pull up resistor is 100 kO KEEPACT input The KEEPACT input is intended to ensure that the host controller remains active while the PCF50633 is in Active sta
22. 0 CLK32K output disabled in Standby state CLK32K output enabled in Standby state 1 This register is reset in NoPower state Reset values are determined by the IC variant see Table 7 Table 14 OOCSTAT OCC status register address 12h bit description Bit Symbol 0 onkey 1 exton1 2 exton2 3 exton3 4 bubpres 5 sysok 6 batok 7 tmpok Access Description R R o ONKEY voltage is below threshold ONKEY voltage is above threshold EXTON1 voltage is below threshold EXTON1 voltage is above threshold EXTON2 voltage is below threshold EXTON2 voltage is above threshold EXTONG voltage is below threshold EXTONG voltage is above threshold VBUBAT lt Vth bubpres VBUBAT gt Vih bubpres Vevs lt Vih sysok Vsys gt Vih sysok VBAT lt Vih batok Vgar gt Vih batok die temperature gt Tthdie die temperature lt Tthdie TO STO XO TO TO TO O Functional description Activity states From the perspective of on off control the PCF50633 is composed of a charger and a power management unit The charger operates autonomously it charges the battery when necessary provided charging is possible It also delivers the system voltage required by the power management unit NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 15 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual External Adapt SYS PFET J
23. 2 Bits are cleared when action finished Functional description Current limiting All three DC to DC converters feature built in programmable peak current limiting This makes it possible to control converter inrush currents at start up and optionally during the entire activation period The maximum peak current is set via x maxc bits in the AUTOMXC and DOWNxMXC control registers see Table 53 Table 57 and Table 61 If the x maxcmod bit is set the current limit will be imposed at all times Otherwise the inrush current will be limited from start up until the converter output reaches its target level Note that the programmed current limit represents the inductor peak current Since the current waveform will be triangular in shape the average value will be somewhat lower Further inrush current control can be achieved by spreading the start up events over time by assigning the converters to different activation phases see Section 8 1 6 8 Dynamic voltage management DOWN1 and DOWN2 Both step down converters offer dynamic voltage management DVM in order to ensure smooth transitions between operating voltages The DVM implemented In the PCF50633 does not require additional output voltage registers It functions as follows When a new down outor down2 out output voltage is set see Table 54 and Table 58 the digital controller will increase or decrease the output voltage in 25 mV steps until the target voltage has been achieved
24. 85 C unless otherwise specified Symbol PSRR AV ol Fipa ext Rpson Parameter Conditions Min Typ power supply rejection ratio f 100kHz voltage drop value of the pull down resistor LDO is disabled connected to the output drain source on state resistancel2 Vis2 7V z Vi 5V 60 0 8 1 2 0 8 Unit dB mV Q Q Q 1 AVio is defined as the voltage difference between input and output when the output is 1 below a reference voltage Vnge and is the minimum voltage drop required to ensure reliable operation Vpep is the voltage measured at the output with Vi set to Vo prog 1 V 2 Input to output resistance in Switch mode Table 75 HCLDO characteristics Vss REFGND GND O V Tamb 40 to 85 C unless otherwise specified Symbol lo Vi Votprog Vo step Vo AVo Al AVo AV Vpwrok PSRR Rpa ext lim Rpson Parameter Conditions Min output current input voltage LDO operated as 2 7 regulator LDO operated as low 1 8 ohmic switch programmable output voltage programmed via 0 9 hcldo out bits output voltage step size output voltage 2 5 load regulation line regulation i power OK level power supply rejection ratio f 100 kHz voltage drop value of the pull down resistor LDO is disabled connected to the output current limit drain source on state resistancel2 Vi 2 7V Vi 5V Typ 100 Vojprog 0 01
25. BATTEMP conversion is stored in ADCS1 ADCS3 bit 1 0 status registers and the result of the ADCIN1 conversion is stored in the ADCS1 ADCS3 bit 3 2 status resisters Table 109 ADCC3 A D converter control register 3 address 52h bit description Bit Symbol Access Resetl Description 0 accswen R W 0 enables biasing for ratiometric measurement on ADCIN1 pin reserved 2 ntcswen R W 0 enables biasing for ratiometric measurement on BATTEMP pin 3 reserved 4 adcdivsel R W 0 resistive divider type selection 0 divide by 3 1 divide by 2 7 5 reserved 1 This register is reset in NoPower state Table 110 ADCS1 A D converter status register 1 address 55h bit descriptionl Bit Symbol Access Description 7 0 adcdatih R 8 most significant bits of the first ADC result 1 This register is reset in NoPower state Table 111 ADCS2 A D converter status register 2 address 56h bit descriptionl Bit Symbol Access Description 7 0 adcdat2h R 8 most significant bits of the second ADC conversion of an ADC measurement sequence 1 This register is reset in NoPower state PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 99 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 14 6 8 14 6 1 8 14 6 2 PCF50633 User Manual Table 112 ADCS3 A D converter status register 3 address 57h bit description Bit Symbol Access Reset Description 1 0 adcdattl
26. C masks hightmp interrupt when set NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 30 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 2 6 PCF50633 User Manual Table 25 INT4MASK Interrupt mask register 4 address OAh bit descriptionl continued Bit Symbol Access Description 3 autopwrfailm R amp C masks autopwrfail interrupt when set 4 dwnipwrfailm R amp C masks dwn1pwrfail interrupt when set 5 dwn2pwrfailm R amp C masks dwn2pwrfail interrupt when set 6 ledpwrfailm R amp C masks edpwrfail interrupt when set 7 ledovpm R amp C masks edovp interrupt when set 1 This register is reset in NoPower state all bits set to 0 Table 26 INT5MASK Interrupt mask register 5 address OBh bit description Bit Symbol Access Description 0 Ido1pwrfailm R amp C masks do1pwrfail interrupt when set 1 Ido2pwrfailm R amp C masks do2pwrfail interrupt when set 2 Ido3pwrfailm R amp C masks do3pwrfail interrupt when set 3 Ido4pwrfailm R amp C masks do4pwrfail interrupt when set 4 ldo5pwrfailm R amp C masks do5pwrfail interrupt when set 5 Ido6pwrfailm R amp C masks do6pwrfail interrupt when set 6 hcldopwrfailm R amp C masks hcldopwrfail interrupt when set 7 hcldoovim R amp C masks hcldoovl interrupt when set 1 This register is reset in NoPower state all bits set to 0 Functional description The PCF50633 uses the interrupt controller to signal to the host controller tha
27. NXP Semiconductors PCF50633 PCF50633 User Manual 12 Application information cx ee ACCSW LDO1OUT o 1 R acc 100 kQ ADCIN1 O f LDO12IN 77 t ADCIN2 E 9 LDO2OUT T 1 uF o NTCSW a 1 pre nte i BATTEMP LDO3OUT 77 Main i BATSNS Lure Battery 7 LDO34IN Fe 1 A MEME CC 039 BAT1 7 1 uF Mm ur BAT LDO4OUT mm 47h LDOSOUT 1yF 0 30 m USB1 I 15 1 pF iced USB2 LDOSeN 77 7 uF T o LDO60UT 1 uF Adaptis ADAPTSNS T 1 wr 1 uF T ADAPTCTRL HCLDOIN t SYS1 o HCLDOOUT 1 uF Vsv 0 pY32 1 uF o 6 3V 22 22 uF 12 4kQ CHGCUR AUTOIN1 By 0805 777 L o XR5 1 VVISA o VISA PCF50633 AUTOIN2 FOUR a 109nF MEG AUTOLXA1 T 100 nF REFC 10nF AUTOLXA2 T REFGND 032 Sui rh BUBAT AUTOLXB1 ees OSCI AUTOLXB2 T L L m 32 768 kHz T 19 AUTOOUT1 o T OSCO A7 up zz 63V AUTOOUT2 H 1206 18 pF XR5 o4 ERBEN DOWNTIN PH 100 ka SCL TY uF 3 Q DDO i DOWN1LX a AH ia 2 2 KQ PENES DOWN1FB ee RSTHC XR5 100 k MS INESSE NES oe HL Q Ba DOWN2IN z e 100 kQ 3
28. Name VERSION VARIANT INT1 INT2 INT3 INT4 INT5 INTIMASK INT2MASK INT3MASK INTAMASK INTBMASK OOCSHDWN OOCWAKE OOCTIM1 OOCTIM2 OOCMODE OOCCTL OOCSTAT GPIOCTL GPIO1CFG GPIO2CFG GPIOSCFG GPOCFG BVMCTL SVMCTL AUTOOUT AUTOENA AUTOCTL Mode R W R W R W R W R W R W R W R W R W R W Reset Bit7 11 NA NA NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP STBY NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP STBY STBY NOP version variant second exton3f onkey1s ledovp hcldoovl secondm exton3fm onkey1sm ledovpm hcldoovim reserved adp_wake shdwn_deb almon onkey_mode reserved tmpok reserved reserved reserved reserved reserved reserved reserved auto_out reserved reserved Bit 6 rtcalarm exton3r adcrdy ledpwrfail hcldopwrfail rtcalarmm exton3rm adcrdym ledpwrfailm hcldopwrfailm usb wake hcrstdel stbclk320n batok Bit 5 reserved exton2f usblimoff dwn2pwrfail Ido6pwrfail reserved exton2fm usblimoffm dwn2pwrfailm Ido6pwrfailm reserved exton3 deb exton3 mode reserved Sysok auto ena act Bit 4 exton2r usblimon dwn1pwrfail ldo5pwrfail exton2rm usblimonm dwn1pwrfailm ldo5pwrfailm rtc wake actphdel usbbatchk bubpres bvmdisdb svmdisdb Bit 3 usbrem exton1f thlimoff autopwrfail Ido4pwrfail usbremm exton1fm thlimoffm autopwrfailm Ido4pwrfailm coldboot exton3 wake exton2 deb exton
29. Parameter Conditions Min Typ Max Unit VoL LOW level output voltage on IRQ pin Pull up resistance gt 10 KQ 0 2 0 4 V lot LOW level output current on IRQ pin 1 5 mA 8 2 5 Software interface INT1 Interrupt register 1 address 02h bit description Table 17 Bit Symbol 0 adpins 1 adprem 2 usbins 3 usbrem 4 reserved 5 reserved 6 rtcalarm 7 second Access Description R amp C ADAPTSNS pin voltage has risen above Vin adaptpres See Section 8 12 6 3 R amp C ADAPTSNS pin voltage has dropped below Vinadaptpres SEE Section 8 12 6 3 R amp C USBx pin voltage has risen above Vthiusbpres see Section 8 12 6 2 R amp C USBx pin voltage has dropped below Vin usbpres see Section 8 12 6 2 R amp C RTC alarm time expired see Section 8 15 7 R amp C RTC periodic one second interrupt see Section 8 15 7 1 This register is reset in NoPower state This column describes the events that cause the corresponding interrupt bits to be set to logic 1 INT2 Interrupt register 2 address 03h bit descriptionl Access Description R amp C R amp C R amp C R amp C R amp C R amp C R amp C R amp C rising edge detected on ONKEY pin see Section 8 1 6 4 falling edge detected on ONKEY pin see Section 8 1 6 4 rising edge detected on EXTON1 pin see Section 8 1 6 5 falling edge detected on EXTON1 pin see Section 8 1 6 5 rising edge detected on EXTON2 pin see Section 8 1 6 5 falli
30. R 2 least significant bits of the first ADC result 3 2 adcdat2l R 2 least significant bits of the second ADC conversion of an ADC measurement sequence 6 4 adcrefmux R 111 ADC Reference selection VREF 000 NTCSW 001 ACCSW 010 2 0 V 011 VISA 100 110 reserved 111 2 0V 7 adcrdy R 0 ADC status 0 ADC is disabled or conversion is in progress 1 ADC conversion is completed 1 This register is reset in NoPower state Functional description Overview The ADC module consists of a 10 bit Analog to Digital converter with internal sample and hold and an input multiplexer offering 4 separate input channels pins ADCIN1 ADCIN2 BATTEMP and BATSNS Two of these inputs ADCIN2 and BATSNS can be preprocessed using either a voltage divider or a subtraction circuit facilitating an extended input range The input source is selected by means of the adcinmux bits in the ADCC1 register see Table 107 A conversion is initiated by setting bit adcstart The resolution 8 or 10 bit is determined by the setting of bit adcres When the conversion is complete the adcrdy status bit is set and an adcrdy interrupt generated The measurement results can then be retrieved from the ADC status registers Table 110 to Table 112 A single sample can be taken or the measured data can be averaged over 4 8 or 16 samples as determined by the setting of bit adc av The ADC supports ratiometric measurements High voltage ADC inputs and
31. Rev 06 05 March 2008 79 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual Table 99 MBCC8 MBC charger control register 8 address 4Ah bit description Bit Symbol Access Description 3 0 ntclvt R W defines the NTC voltage level for battery high temperature threshold in 50 mV steps 0000 0 60 V 0001 0 65 V 1110 1 30 V 1111 1 35 V 4 usbenasus R W 0 USB SYS switch is not conducting in USB suspend mode ideal diode is enabled 1 USB SYS switch is conducting in USB suspend mode ideal diode is disabled 7 5 reserved 1 This register is reset in NoPower state Reset values are determined by the IC variant see Table 7 Table 100 MBCS1 MBC charger status register 1 address 4Bh bit description Bit Symbol Access Description 0 usbpres R USB presence indication on pin USBx 0 VusB lt Vih usbpres 1 VusB gt Vih usbpres 1 usbok R USB voltage indication on pin USBx 0 Vusg lt Vear AVusgok 1 Vusa gt Vegar AVusBok 2 adaptpres R adapter presence indication on pin ADAPTSNS 0 VADAPTSNS lt Vih adaptpres 1 VADAPTSNS gt Vih adaptpres 3 adaptok R SYS voltage indication on pin SYSx 0 Vsys lt Vaar AVapaptok 1 Vsys gt Veat AVADAPTOK 5 4 tbatstat R battery temperature status indication 00 temperature within window 01 temperature above window 10 temperature below window 11 temperature is undefined 6 prewdtexp R watchdog timer status indication during pre charge 0
32. USB charging Current limiting is guaranteed at the USB input even though the USB path is split between 2 power components The current limit level can be set to 100 mA 500 mA or 1 A by means of the usbdevstat bits in register MBCC7 see Table 98 USB presence detection is debounced by 62 ms A usbins interrupt is generated when the USB voltage exceeds Vihusbpres for longer than 62 ms A usbrem interrupt is generated when the USB voltage drops below Vin usbpres for longer than 62 ms The charge current during USB operation is the maximum available current less the current required by the system If the system draws more current that the USB source can deliver the ideal diode will begin conducting and current will flow from the battery to the system via the BAT to SYS path see Figure 41 When no USB presence is detected the path from BAT to USB is blocked in order to prevent battery discharge in the event of short circuits at the USB connector Adapter input When an external power source is present charging will be via the SYS to BAT path only see Figure 43 The USB to SYS path will be blocked to prevent current flow in the USB cable An external PFET must be connected between the adapter and the SYSx pins see Figure 38 The PFET can be driven by the ADAPTCTRL output Adapter presence detection is debounced by 62 ms An adpins interrupt is generated when the voltage on ADAPTSNS exceeds Vih adaptpres for longer than 62 ms An adpre
33. alarm registers software interface Fig 50 RTC block diagram Hardware interface There is no hardware interface associated with the RTC Software interface RTC time registers Table 113 RTCSC RTC second value register address 59h bit description Bit Symbol Access Reset Description 6 0 sec Rw Bl 0000000 current seconds value 00 to 59 coded in BCD format example sec 0001 1001 represents a value 19 s 7 reserved 2 1 This register is reset in NoPower state 2 Counting proceeds after this register has been updated The software should take this into account and ensure that a full RTC update up to 7 registers is completed before the seconds counter reaches 59 To avail of the maximum available update time the software should initiate an update immediately after a one second interrupt has been generated 2 Reserved bits should be written 0 return values are not defined Table 114 RTCMN RTC minute value register address 5Ah bit description Bit Symbol Access Reset Description 6 0 min R W 0000000 current minutes value 00 to 59 coded in BCD format 7 reserved 21 1 This register is reset in NoPower state 2 Reserved bits should be written 0 return values are not defined NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 103 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 15 5 2 PCF50633 User Manual Table 115 RT
34. block Block diagram General Purpose Memory R W MEMBYTEO MEMBYTE7 Fig 51 GPM block diagram 8 16 3 Software interface Table 129 MEMBYTEO General purpose memory byte 0 address 67h bit description Bit Symbol Access Reset Description 7 0 membyte0 R W 00000000 byte O of 8 byte general purpose memory Table 130 MEMBYTE1 General purpose memory byte 1 address 68h bit description Bit Symbol Access Reset Description 7 0 membytet R W 00000000 byte 1 of 8 byte general purpose memory NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 107 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual Table 131 MEMBYTE2 General purpose memory byte 2 address 69h bit description Bit Symbol Access Reset Description 7 0 membyte2 R W 00000000 byte 2 of 8 byte general purpose memory Table 132 MEMBYTE3 General purpose memory byte 3 address 6Ah bit description Bit Symbol Access Reset Description 7 0 membyte3 R W 00000000 byte 3 of 8 byte general purpose memory Table 133 MEMBYTE4 General purpose memory byte 4 address 6Bh bit description Bit Symbol Access Reset Description 7 0 membyte4 R W 00000000 byte 4 of 8 byte general purpose memory Table 134 MEMBYTES General purpose memory byte 5 address 6Ch bit description Bit Symbol Access Reset Description 7 0 membyte5 R W 00000000 byte 5 of 8 byte general purpose memor
35. enters Standby after 8 seconds providing the host controller doesn t intervene in the meantime A direct and immediate transition is initiated in the event of one of the following error conditions e The go stby bit in control register OOCSHDWN see Table 8 is set This allows the host controller approximately 2 ms to shut down before the PCF50633 enters Standby state Absence of a valid KEEPACT signal see Section 8 1 6 11 ALOW to HIGH transition on the SHUTDOWN pin An 8 second time out timer is initiated in the event of one of the following conditions After 8 seconds the PCF50633 enters Standby mode if no action is taken by the host controller in the meantime e The ONKEY pin is LOW for longer than 1 second if onkey mode control bits configured accordingly see Table 12 Rising edge on ONKEY if onkey mode control bits configured accordingly see Table 12 Rising or falling edge on EXTONx if extonx mode control bits configured accordingly see Table 12 and Section 8 1 6 5 PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 20 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 1 6 3 8 1 6 4 PCF50633 User Manual Transitions from Active to Save Transitions from Active to Save can be direct and immediate or can occur after a 1 second or an 8 second delay In the later case a time out timer is initiated and the system enters Save state after respecti
36. ko PCF50633 H four sil LEDFB IN HO RsENsE LEDFBGND Ll Fig 33 LED circuit arrangement for output voltages gt Vo rgp max With output disconnected from input when converter is off Generating a 5V USB supply A 5 V 100 mA USB supply source can be generated by configuring the LED supply module as a boost converter The LED chain and the current sense resistor are replaced with a regular voltage divider as illustrated in Figure 34 LEDOUT USB E gt VBUS I 5V E PCF50633 Rip1 s LEDFB Riba LEDFBGND Ke ETE Rip1 3x Ripe Fig 34 USB 5V 100mA supply using the LED module The formula R 3x R5 in Figure 34 assumes the default output voltage Vi gprg 1 25 V has been selected led out 111111 see Table 67 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 64 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 8 10 6 8 Ambient light monitor The ambient light monitor can be used to adjust the LED current in response to changes in ambient light levels The current through an external photodiode is measured and stored in the ALMDATA register see Table 72 The host controller can adjust the ed out bit settings in response to changes in this value l t converter alm data ALMGAIN Calibration Fig 35 ALM control circuit The ambient light level is measured by an
37. ldo1 p2c Ido2_p2c Ido3_p2c Ido4_p2c Ido5_p2c Bit 1 down1 pic down2 pic memldo pic led pic led ovprst ldo1 pic ldo2 pic ld03 pic ld04 pic ld05 pic Bit 0 down1 on down1pwmon ly down2 on down2pwmon ly memldo on led on led ovpon Ido1 on Ido2 on Ido3 on ldo4 on Ido5 on Ref Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 67 Table 68 Table 69 Table 70 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Jenue y 4esf 90SA9Dd 90S8dO0d S10 INPU0I1W3S dXN jenuew ssn 8002 421e SO 90 9H SZL 40 SLL 9 Wnee90940d panlasal syu Iv B002 5 8 dXN Table 138 PCF50633 register overview continued HEX Addr 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 Register Name LDO6ENA HCLDOOUT HCLDOENA STBYCTL1 STBYCTL2 DEBPF1 DEBPF2 DEBPF3 HCLDOOVL DCDCSTAT LDOSTAT MBCC1 MBCC2 MBCC3 MBCC4 MBCC5 MBCC6 MBCC7 MBCC8 MBCS1 MBCS2 MBCS3 BBCCTL ALMGAIN ALMDATA RESERVED ADCC3 ADCC2 Mode R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Reset Bit 7 Bit 6 nl STBY reserved STBY reserved STBY reserved NOP reserved Ido4_ena_stb NOP res
38. lowbat interrupt is generated and the batok status bit is set to O The threshold voltage Vin patok is determined by the bvmlvl control bits in the BVMCTL register see Table 37 Note that the BVM output signal will only affect state transitions if the usbbatchk bit in control register OOCCTL is 1 see Table 13 A hysteresis and debounce filter is built in to prevent rapid cycling of the lowbat interrupt signal The rising edge of the BVM low battery signal is debounced with a debounce time of 62 ms The falling edge is not debounced The debounce filter can be disabled by setting the bvmdisdb control bit in the BVMCTL register see Table 37 Temperature High Sensor THS Introduction The Temperature High Sensor monitors the junction temperature of the PCF50633 Features e Fixed temperature threshold Tin die Built in hysteresis and debounce filter minimizes system oscillations NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 40 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 8 6 3 Block diagram 8 6 4 8 6 5 8 6 6 PCF50633UM 6 THS internal temperature hightemp interrupt Tih die temperature comparator 12C Software Interface Fig 22 THS block diagram Hardware interface Table 38 THS characteristics Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified Symbol Symbol C
39. output when switching an inductive load In this case a free wheel diode or capacitance should be connected across GPIOx and ground to eliminate the spikes The limiting values must be respected under all conditions see Section 10 Limiting values Table 28 GPO characteristics Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit lo output current 10 10 mA Vou HIGH level output voltage lou 10 mA 0 8Vi EpiN a VLEDIN V VoL LOW level output voltage lo 2 10 mA 0 3 0 35 V PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 33 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 8 3 5 Software interface Table 29 GPIOCTL GPIO I O mode control register address 13h bit description Bit Symbol Access Reset Description 0 gpio1dir R W 2 GPIO1 O mode 0 output 1 input gpio2dir R W 2 GPIO2 I O mode 0 output 1 input gpio3dir R W B GPIO3 I O mode 0 output 1 input 7 3 reserved 1 Reset values are determined by the IC variant see Table 7 2 Reset in NoPower state 3 Reset in Standby state Table 30 GPIO1CFG GPIO1 signal selection register address 14h bit description Bit Symbol Access Description 2 0 gpio1sel R W GPIO1 output signal selection 000 fixed 0 001 reserved 010 SYSx pin voltage gt Vih sysok 011 battery charging in progress 100 mob
40. temperature a decoupling capacitor for VISC and an external PFET for supplying adapter voltage e Thermal regulation loop Charging resumed automatically when battery is discharged to a predefined level Single cell Li ion batteries are supported with a capacitance ranging up to approximately 3000 mAh maximum charge current of 1 A NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 74 of 125 NXP Semiconductors PCF50633 8 12 3 Block diagram PCF50633 User Manual Adapter External PFET ADAPTSNS HI ADAPTCTRL USB SYS switch USBx v SYSx N charger charger diode ZN BATX Charger NTCSW BATTEMP Hardware P ieee t Control charger Main interrupts ip _ battery CHGCUR Software VISC Rext CHGCUR T I 100 nF Fig 38 MBC block diagram 8 12 4 Hardware interface Table 91 MBC characteristics Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit USB input related VusB USB supply voltage 4 0 5 3 V Vih usbpres USB adapter presence rising edge 3 25 3 6 3 95 V threshold voltage falling edge 3 15 3 5 3 85 VUSBMIN USB voltage required for USB Vhat tloatjprog 4 2 V 4 5 V charging vmax 1010 AVysBok difference between USB and 50 mV battery voltages for charging VusB gt Vegart AVusBok lim U
41. wake up the system whenever an Adapter is connected The USB voltage presence detector in order to detect when the USB supply has been removed Theoretically the CPU core and its I O supply needs to remain active in order to be able to respond if the USB host issues a resume notification and to ensure it doesn t loose the connection to the USB host The CPU can be supplied via the USB or the battery If the usbenasus bit is set see Table 99 the USB SYS FET will be fully conducting no current limiting in suspend mode The host controller will be responsible for ensuring that the total current drawn from the USB supply is less than the USB budget The SYS BAT FET and the USB BAT FET will be disabled and the ideal diode will not be conducting If the usbenasus bit is not set the USB SYS FET will be off while the ideal diode will be conducting The host controller will be powered from the battery The USB connection will be lost in this case if the battery is allowed to run down Adapter Charge and Play mode Battery not fully charged As long as the adapter is capable of delivering the required system current under all conditions and is capable of charging the battery the arrangement depicted in Figure 43 will apply Adapt to SYS path Adapter 1 Lal External Adapt SYS PFET oe 4 gt USB gt M gt i System N USB SYS FET 1 tu rE Ideal Adapter e q 8 charger i ba m
42. 0 1 V max 3 6 V e g 00000 0 9 V 00001 1 0 V 11011 3 6 V 11111 3 6 V 5 hcldo swmod R W 0 linear regulator mode 1 switch mode 7 6 reserved NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 72 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 11 6 8 11 6 1 8 11 6 2 PCF50633 User Manual 1 This register is reset at each transition to Standby state Reset values are determined by the IC variant see Table 7 Table 89 HCLDOENA HCLDO output enable register address 3Ah bit description Bit Symbol Access Description 0 hcldo on RAN if set LDO is ON 1 hcldo pic R W if set LDO is ON when GPIO1 1 hcldo p2c R W if set LDO is ON when GPIO2 1 hcldo_p3c R W if set LDO is ON when GPIOS 1 5 4 hcldo ena act R W selects activation phase 00 ACTPH1 01 ACTPH2 10 ACTPH3 11 ACTPH4 7 6 reserved 1 This register is reset at each transition to Standby state Reset values are determined by the IC variant see Table 7 Table 90 HCLDOOVL HCLDO overload protection register address 40h bit description Bit Mode Symbol Reset Description 1 0 RAW HCLDO DEBOVL 11 Overload detection debounce time 00 none 01 1 ms 10 10 ms 11 100 ms 7 2 reserved 1 This register is reset at each transition to Standby state Functional description LDO1 to LDO6 LDO1 to LDO6 can deliver a maximum output current of either 50 mA LDO1 LDO2
43. 0 variant R xxxxxxxx ROM number to distinguish PCF50633 variants with different reset values Table 8 OOCSHDWN OOC shutdown register address OCh bit description Bit Symbol Access Reset Description 0 go stby Rw 0 0 no action 1 initiates a transition to Standby reserved 2 totrst Rw o 0 no action 1 resets time out timer 3 coldboot R W 1 0 no coldboot condition 1 coldboot device has been in NoPower state 7 4 reserved 1 Register is reset in NoPower state 2 Bitis cleared after transition Table 9 OOCWAKE OCC wake up register address ODh bit description Bit Symbol Access Reset Description 0 onkey wake R 1 0 ONKEY functionality disabled 1 ONKEY functionality enabled 1 extont wake R 1 0 EXTON1 functionality disabled 1 EXTON1 functionality enabled 2 exton2 wake R W 1 0 EXTON functionality disabled 1 EXTON2 functionality enabled 3 exton3 wake R W 1 0 EXTONS functionality disabled 1 EXTONS functionality enabled 4 rtc wake R W 1 0 wake up by RTC alarm disabled 1 wake up by RTC alarm enabled 5 reserved 6 usb wake R W 1 0 wake up by USB insert disabled 1 wake up by USB insert enabled 7 adp wake R W 1 0 wake up by adapter insert disabled 1 wake up by adapter insert enabled 1 Register is reset in NoPower state Table 10 OOCTIM1 OOC debounce register 1 address OEh bit description Bit Symbol Access Reset Description 1 0 exton1 deb R W 10 debounce time for EXTON1 00 non
44. 02 20061030 Supersedes PCF50633 1 Modifications The format of this user manual has been redesigned to comply with the new identity guidelines of NXP Semiconductors Legal texts have been adapted to the new company name where appropriate Updated to incorporate changes since initial release HUQFN68 and HUQFN88 packages added 01 20051214 Initial version Contact information For additional information please visit http www nxp com For sales office addresses please send an email to sales addresses www nxp com PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 2 of 125 NXP Semiconductors PC F50633 1 Introduction PCF50633 User Manual 2 Features The PCF50633 is a highly integrated solution providing power supply generation and battery management for mobile devices such as portable media players It contains linear and switching regulators including an automatic up down converter for hard disk supply Other features include a complete USB compliant battery charger system control functions and a multi purpose Analog to Digital Converter ADC The device can be controlled by a host controller via an I2C bus serial interface This document describes the features and operation of the PCF50633 and contains all the information including interface and connection details required to integrate the IC into a mobile device PCF50633UM 6 2 1 System control I2C bus
45. 1 This register is reset at each transition to Standby state 2 Reset values are determined by the IC variant see Table 7 Table 60 DOWN2CTL DOWN control register address 24h bit description Bit Symbol Access Reset Description 0 down2pwmonly R W 0 0 automatic PFM PWM selection 1 converter operates in PWM mode 4 31 down dvmstep R W 0000 DVM step time defines number of 32768 Hz clock cycles between each step e g 0000 no DVM 0001 30 us 1111 458 us 7 5 reserved 1 This register is reset at each transition to Standby state PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 54 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual Table 61 DOWN2MXC DOWN maximum current register address 25h bit descriptionl Bit Symbol Access Description 5 0 down2 maxc R W sets current limit of DOWN2 converter limax down2 maxc x 15 mA e g 01101 2 195 mA 6 down2 maxcmod R W current limit mode 0 limiting at start up only 1 limiting always active 7 reserved 1 This register is reset at each transition to Standby state Reset values are determined by the IC variant see Table 7 Table 62 MEMLDOOUT MEMLDO o p voltage select reg address 26h bit description Bit Symbol Access Description 4 0 memldo out R W Votprog 0 9 memldo out x 0 1 V e g 00000 0 9 V 00001 1 0 V 11000 3 3 V 11011 3 6 V 11111 3 6 V 5 memldo swmod R W 0 line
46. 1Bh bit description Bit Symbol Access Reset Description 0 auto on R W 2 if set converter is ON auto pic R W 2 if set converter is ON when GPIO1 1 auto p2c R W 21 if set converter is ON when GPIO2 1 auto p3c R W 2 if set converter is ON when GPIO3 1 5 4 auto ena act R W selects activation phase 00 ACTPH1 01 ACTPH2 10 ACTPH3 11 ACTPH4 7 6 reserved 1 This register is reset at each transition to Standby state 2 Reset values are determined by the IC variant see Table 7 Table 52 AUTOCTL AUTO control register address 1Ch bit description Bit Symbol Access Reset Description 0 autopwmonly R W 0 0 automatic PFM PWM selection 1 converter operates in PWM mode 1 auto mod R W 0 selects regulator type 0 auto up down 1 down only 7 2 reserved 1 This register is reset at each transition to Standby state PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 52 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 PCF50633 User Manual Table 53 AUTOMXC AUTO maximum current register address 1Dh bit description Bit Symbol Access Description 5 0 auto maxc R W sets current limit of AUTO converter I max auto maxc x 40 mA e g 000101 200 mA 6 auto maxcmod R W current limit mode 0 limiting at start up only 1 limiting always active 7 reserved 1 This register is reset at each transition to Standby state Reset va
47. 2 R W fast charge current level in USB Fast Charge phase settings same as for prechgcur in Table 94 1 This register is reset in NoPower state Reset values are determined by the IC variant see Table 7 Table 97 MBCC6 MBC charger control register 6 address 48h bit description Bit Symbol Access Description 4 0 cutoffcur RAN cutoff current level used for battery full detection in CV mode 00000 1 32 x leg 00001 2 32 x Icua 11110 31 32 XCHG 11111 32 32 x lcu 7 5 reserved 1 This register is reset in NoPower state Reset values are determined by the IC variant see Table 7 2 lcua is the programmed charge current The value is defined by either the prechgcur fstchgcur1 or fstchgcur2 control bits depending on the operating mode Table 98 MBCC7 MBC charger control register 7 address 49h bit description Bit Symbol Access Reset Description 1 0 usbdevstat RAW 2 USB device status setting 00 configured for 100 mA 01 configured for 500 mA 10 configured for 1000 mA 11 suspend 2 battempena R W B if set battery temperature is measured and impacts the MBC state machine 5 3 reserved 7 6 batsysimax R W IIS maximum BAT SYS current when ideal diode is conducting 00 1 6A 01 1 8A 10 2 0A 11 2 2A 1 Reset values are determined by the IC variant see Table 7 2 Reset in Standby state 3 Reset in NoPower state NXP B V 2008 All rights reserved User manual
48. 2 mode heartbeat exton3 gpio1pol gpio2pol gpio3pol gpopol bvmivi svmlvl auto p3c Bit 2 usbins extonir thlimon hightmp Ido3pwrfail usbinsm extonirm thlimonm hightmpm Ido3pwrfailm totrst exton2 wake onkey deb actclk32on exton2 gpio3dir gpio1sel gpio2sel gpio3sel gposel auto p2c Bit 1 adprem onkeyf chghalt lowbat Ido2pwrfail adpremm onkeyfm chghaltm lowbatm Ido2pwrfailm reserved exton1 wake exton1 deb exton1 mode actphrst exton1 gpio2dir auto pic auto mod Bit 0 adpins onkeyr batfull lowsys Ido1pwrfail adpinsm onkeyrm batfullm lowsysm ldo1pwrfailm go stby onkey wake onkey gpio 1dir bvmlow svmlow auto on autopwmonly Ref Table 6 Table 7 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 29 Table 30 Table 31 Table 32 Table 33 Table 37 Table 35 Table 50 Table 51 Table 52 enuen 1951 90SA9d 90S40d S10 INPU0I1W3S dXN jenuew sn 8002 YEN SO 90 9H SZL Jo VLL 9 Wnee90940d pe ueseu syu Iv B002 5 8 dXN O Table 138 PCF50633 register overview continued HEX Addr 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 Register Name AUTOMXC DOWN1OUT DOWN1ENA DOWNICTL DOWN1MXC DOWN2OUT DO
49. 3 NOP membyte4 NOP membyte5 NOP membyte6 NOP membyte7 NOP reserved NOP reserved Bit 6 adcrefmux Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 adc av adcres adcstart adcdat2l adcdat1 sec min hour wkday day month year seca mina houra wkdaya daya montha yeara down2pfm down1pfm autopfm Ref Table 107 Table 110 Table 111 Table 112 Table 113 Table 114 Table 115 Table 116 Table 118 Table 119 Table 120 Table 122 Table 123 Table 124 Table 125 Table 126 Table 127 Table 128 Table 129 Table 130 Table 131 Table 132 Table 133 Table 134 Table 135 Table 136 Table 64 1 NA register content is fixed NOP register is reset in NoPower state STBY register is reset at each transition to Standby state enuen 4esf 90SA9d 90S40d S10 INPU0I1W3S dXN NXP Semiconductors PCF50633 9 Quality specification PCF50633 User Manual In accordance with SNW FQ 611 The numbers of the quality specification can be found in the Quality Reference Handbook This handbook can be ordered using the code 9397 750 00192 10 Limiting values Table 139 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter VBAT battery supply voltage VauBAT backup battery supply voltage Vsys system supply voltage VusB USB supply voltage Vi input voltage li input current lo output current Prot total power dissipation Tamb ambient temper
50. 5 March 2008 50 of 125 NXP Semiconductors PCF50633 PCF50633UM 6 8 9 4 Hardware interface Table 47 AUTO characteristics Vss REFGND GND 0 V Tamb 40 to 85 C unless otherwise specified PCF50633 User Manual Symbol lo VI Votprog Vo step Vo Vo rppi sw PWM Fipd ext Parameter output current input voltage programmable output voltage output voltage step size output voltage output voltage ripple PWM switching frequency internal pull down resistor connected to the output Conditions Min Typ Max Unit 1 1 A configuration 7 1100 mA 500 mA configuration 5001 mA 27 5 8 V programmed via 1 8 3 8 V auto out bits 5 25 mV 5 Vo prog 3 Yo 15 mV 1 7 MHz AUTO is disabled 80 Q 1 Smaller external components can be used in the 500 mA configuration The AUTOLXA2 and AUTOLXB1 pins must be left floating in this configuration see Section 8 9 6 3 Table 48 DOWN1 and DOWN2 characteristics Vss REFGND GND O V Tamb 40 to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit lo output current 500 mA VI input voltage 27 5 3 V Vo prog programmable output programmed via 0 625 3 0 V voltage downx out bits Vo step output voltage step size 25 mV Vo output voltage 3 Votprogy 3 Yo Vovrppl output voltage ripple 15 mV fsw PWM PWM switching frequency 1 7 MHz Fipa ext internal pull
51. 7 Table 41 STBYCTL2 LDO Standby control register address 3Ch bit descriptionl Bit Symbol Access Description 0 ld05 ena stb R W if set LDO5 is ON in Standby state 1 reserved 2 ld06 ena stb R W if set LDO6 is ON in Standby state 3 reserved 4 hcldo ena stb R W if set HCLDO is ON in Standby state 5 reserved 6 memldo ena stb R W if set MEMLDO is ON in Standby state 7 reserved 1 This register is reset in NoPower state Reset values are determined by the IC variant see Table 7 Table 42 DEBPF1 Power fail debounce register 1 address 3Dh bit description Bit Symbol Access Reset Description 1 0 auto debpf R W 11 AUTO power failure debounce time 00 none 01 1 ms 10 10 ms 11 100 ms 3 2 down debpf R W 11 DOWN power failure debounce time settings like auto debpf 5 4 down2 debpf R W 11 DOWN power failure debounce time settings like auto debpf 7 6 led debpf R W 11 LED power failure debounce time settings like auto debpf 1 This register is reset in NoPower state Table 43 DEBPF2 Power fail debounce register 2 address 3Eh bit description Bit Symbol Access Reset Description 1 0 ldo1 debpf R W 11 LDO1 power failure debounce time 00 none 01 1 ms 10 10 ms 11 100 ms PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 45 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual Table 43 DEBPF2 Power fail debounce regi
52. A Fig 52 I C block diagram 8 17 4 Hardware interface Table 137 I C bus characteristics Vss REFGND GND O V Tamb 40 to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Vit LOW level input voltage on 0 0 5 V SDA SCL pins Vin HIGH level input voltage on 0 8 5 5 V SDA SCL pins VoL LOW level output voltage Pull up resistance 0 2 0 4 V on SDA pin gt 1kQ fse I C bus clock frequency 400 kHz 8 17 5 Functional description The I C bus is used for bidirectional two line communication between ICs or modules The two lines are a serial data line SDA and a serial clock line SCL Both lines must be connected to a positive supply via a pull up resistor Data transfer may be initiated only when the bus is not busy In bus configurations where ICs are on different supply voltages the pull up resistors should be connected to the highest supply voltage The I2C bus supports incremental addressing This enables the host controller to read or write to multiple registers in a single I2C bus action The PCF50633 supports I C bus communications up to 400 kbit s 8 17 5 1 I C bus configuration The I C bus system configuration is shown in Figure 53 The device generating the message is the transmitter while the receiving device is the receiver The device controlling the operation is the master while the device or devices being controlled by the master are the
53. Adapter Fast Charge Wait phase When battempena 0 it is assumed that the application does not include an NTC for measuring battery temperature In this situation all restrictions in the state diagram Figure 39 relating to battery temperature are ignored Charging stops if chgena is reset see Table 92 or if a watchdog timer time out is generated When a watchdog timer time out is generated bit wdtexp in register MBCS7 is set see Table 100 Die Temperature control during charging The thermal regulation loop is an analog loop that compares the junction temperature of the pass device with a predefined fixed temperature When the junction temperature approaches this threshold the loop will automatically reduce the charging current in order to ensure the temperature never exceeds the specified threshold Tiim usg gar for the USB BAT FET and Tiim USB SYS for the USB SYS FET see Table 91 When the thermal regulation loop reduces the USB SYS FET current bits tlim play and usblim play in the MBCS3 register are set see Table 102 and thlimon and usblimon interrupts are generated thlimoff and usblimoff interrupts are generated when the thermal regulation loop stops limiting the charge current When the thermal regulation loop reduces the charge current through the SYS BAT FET or the USB BAT FET bits tlim chg and usblim chg are set see Table 102 tlim chg and usblim chg are reset when the thermal regulation loop stops limiting the charg
54. B V 2008 All rights reserved User manual Rev 06 05 March 2008 10 of 125 NXP Semiconductors PCF50633 PCF50633 User Manual 2 Forthe AUTO converter in the 1 1 A configuration the following pin pairs must be connected on the PCB AUTOLXA1 to AUTOLXA2 AUTOLXB1 to AUTOLXB2 The AUTOLXA2 and AUTOLXB1 pins must remain unconnected in the 500 mA configuration see Section 8 9 6 3 These pins are all power pins They must be connected via a low ohmic connection 8 Functional description PCF50633UM 6 8 1 8 1 1 On Off Control OOC Introduction The OCC controls the activity states of the PCF50633 It also provides sequencing for the host controller clock CLK32K and reset RSTHC signals Four programmable start up phases facilitate the sequential start up of the supplies Features Finite state machine supporting Save Standby and Active states Programmable wake up condition for ONKEY and EXTONx inputs Wake up condition for RTC alarm Programmable sequencing for host controller clock CLK32K and reset RSTHC Four separate activity phases for power supply sequencing Programmable debounce for ONKEY EXTONx and SHUTDOWN inputs Block diagram EXTONx Sysok gt batok tmpok 5 ON OFF State Machine RTC alarm ONKEY SHUTDOWN KEEPACT 12C Software Control Fig 3 OOC block diagram Interrupts Operating
55. CHR RTC hour value register address 5Bh bit description Bit Symbol Access Reset Description 5 0 hour R W 000000 current hours value 00 to 23 coded in BCD format 7 6 reserved 2 1 This register is reset in NoPower state 2 Reserved bits should be written 0 return values are not defined RTC date registers Table 116 RTCWD RTC day of week value register address 5Ch bit description Bit Symbol Access Reset Description 2 0 wkday R W 000 current day of week value 0 to 6 see Table 117 7 3 reserved 2 1 This register is reset in NoPower state 2 Reserved bits should be written 0 the return values are not defined Table 117 WKDAY assignment Day Bit Bit 1 Bit 0 Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday 1 1 0 Table 118 RTCDT RTC day value in BCD format register address 5Dh bit description Bit Symbol Access Reset Description 5 0 day R W 000001 current day value 01 to 31 coded in BCD format 7 6 reserved 21 1 This register is reset in NoPower state 2 Reserved bits should be written 0 return values are not defined Table 119 RTCMT RTC month value in BCD format register address 5Eh bit description Bit Symbol Access Reset Description 4 0 month R W 000001 current month value 01 to 12 coded in BCD format see Table 121 7 5 reserved 2 1 This register is reset in NoPowe
56. E O X 0 USB charger A a SvStobar pan AE van id pa 7 battery USB BAT FET 77 Fig 43 Current flow during adapter charging system takes less than adapter budget NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 87 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 PCF50633 User Manual Battery fully charged There will be no charge current if the battery is fully charged Battery Full mode A battery full condition is detected when the following conditions are satisfied Battery charge current falls below the cutoffcur setting Vear has reached the specified vmax value USB BAT FET current limiting is not active usblim chg 0 Temperature limiting loops in USB to BAT and SYS to BAT paths not active tlim chg 0 A OO N A batfull interrupt is generated when all the above conditions are satisfied A transition to Battery Full mode will occur automatically if autostop is set see Table 92 Note that the charger will not initiate a transition to Battery Full mode if autostop 0 a batfull interrupt will still be generated In this situation the current charge mode will be retained The state machine goes from Battery Full to Play Only mode whenever the battery voltage drops below the resume level Vin ngs for a period longer than the debounce time defined by control bit vresdebtime in register MBCC2 see Table 93 and autores is set to 4 P When char
57. E ADDRESS 0 WORD ADDRESS SLAVE ADDRESS 1 DATA uw RAV RAV n bytes at this moment master transmitter auto increment becomes master receiver and memory word address the device slave receiver becomes slave transmitter no acknowledgement from master u last byte auto increment memory word address Fig 59 Master reads after setting word address write word address read data acknowledgement acknowledgement no acknowledgement from slave from master from master T T T 1 T T T i T T T T T T T i T T T T T T T i S SLAVE ADDRESS 1 A DATA A DATA 1 P L L L L L L 1 i L L L L L L L L L L L L L L RW n bytes last byte auto increment auto increment word address word address mgl665 Fig 60 Master reads slave immediately after first byte read mode 8 17 11 De activation of the I2C bus module The I2C bus module is only enabled in the Active state when the reset for the host controller is released RSTHC is HIGH It only consumes power during data communications NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 112 of 125 jenuew ssn 8002 421e SO 90 9H SZL 40 ELL 9 WNEEIOSAId panlasal syfu Iv 8002 5 8 dXN 8 18 Register map Table 138 PCF50633 register overview HEX Addr 00 01 02 03 04 05 06 07 08 09 0A 0B 0C oD 0E OF 10 11 12 13 14 15 16 17 18 19 1A 1B 1C Register
58. If charging is via the USB connector bits fstchgcur2 determine the fast charge current For a Li lon battery the fast charge current is typically between 0 7 C and 1 0 C Fast charging with a constant fast charge current continues until the battery voltage reaches the programmed float level vmax For a Li lon battery vmax is typically 4 2 V When the battery voltage reaches the float level vmax vlim is set in register MBCS3 see Table 102 and charging continues at a constant voltage CV mode During this phase the charger keeps the battery voltage constant at the specified float level The charge current will gradually decline as the battery charge level increases When the charge current drops below the cutoff point as specified via the cutoffcur bits in register MBCC46 see Table 95 the ilim bit is reset to O in register MBCS3 see Table 102 When ilim 0 and neither the thermal limiting loop nor the USB current limiting loop is active a batfull interrupt is generated to indicate that the battery is fully charged If autostop is set see Table 92 charging stops and the MBC enters Battery Full mode Otherwise charging continues and the control software will be responsible for deciding what action to take If the battery temperature rises above the high temperature threshold in Fast Charge phase the MBC will enter Fast Charge Wait phase and charging will stop Charging will resume once the battery temperature falls below the high t
59. LDO1 to LDO6 and HCLDO 8 11 2 Features Low drop out voltage Low quiescent current at no load in normal operating mode eliminating the need for special power saving modes Programmable output voltage in 100 mV steps Power fail detection at 9096 of the target output voltage resulting in an interrupt see Section 8 8 6 3 Switch mode resulting in a low resistive path between input and output at minimum quiescent current 8 11 3 Block diagram xpwrfail Interrupt LDOXxIN HCLDOIN LDOxOUT HCLDOOUT d GPIOx Hardware Control Software Control Status Fig 37 LDO1 to LDO6 HCLDO block diagram NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 66 of 125 NXP Semiconductors PCF50633 PCF50633UM 6 8 11 4 Hardware interface PCF50633 User Manual Min 2 7 1 8 Table 73 LDO1 LDO2 LDO3 and LDO6 characteristics Vss REFGND GND O V Tamo 40 to 85 C unless otherwise specified Symbol Parameter Conditions lo output current Vi input voltage LDO operated as regulator LDO operated as low ohmic switch Vo prog programmable output voltage programmed via dox out bits Vo sep Output voltage step size Vo output voltage AVo Al load regulation AVOo AM line regulation Vpwrok power OK level PSRR power supply rejection ratio f 100 kHz AV oll voltage drop from input to output Rpaex value of the pull down LDO is disabled res
60. RT and STOP conditions Each byte 8 bits is followed by an acknowledge bit The acknowledge bit is a HIGH level signal on the SDA line for which the receiver generates an extra acknowledge related clock pulse NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 110 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 17 9 8 17 10 PCF50633 User Manual The transmitter releases the SDA line HIGH during the acknowledge clock pulse The slave receiver must generate an acknowledge signal by pulling the SDA line LOW It must remain stable LOW while the acknowledge clock pulse is HIGH setup and hold times must be taken into consideration A master receiver must also generate an acknowledge signal after receiving each byte clocked out of the slave transmitter A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte to be clocked out of the slave The slave transmitter must then release the data line HIGH to allow the master to generate a STOP condition data output 3 by transmitter NG not acknowledge EY a data output by receiver acknowledge Pal SCL from s clock pulse for START acknowledgement condition mbc602 Fig 56 Acknowledge on the I C bus Internal timing of a write sequence Data written to the PCF50633 will become valid on the falling edge of the associated SCL acknowledge signa
61. SBx current limit on pin USBx limit set to 1000 mA 800 900 1000 mA limit set to 500 mA 400 450 500 mA limit set to 100 mA 80 90 100 mA RowusB svs USB SYS FET ON resistance 7 0 20 5 Q AV ysp sys voltage drop across USB SYS no USB current limiting 235 mV FET PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 75 of 125 NXP Semiconductors PCF50633 Table 91 MBC characteristics continued Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified PCF50633 User Manual Symbol Parameter Conditions Min Typ Max Unit Adapter input related VADAPTSNS voltage on pin ADAPTSNS 4 0 5 3 V Vih adaptpres adapter presence threshold rising edge 3 25 3 6 3 95 V voltage falling edge 3 15 3 5 3 85 VADAPTMIN minimum SYS voltage required Vpartioatjprog 4 2 V 4 5 V for adapter charging vmax 1010 AV ADAPTOK difference between system and for charging Vsys gt 50 mV battery voltages Veat AVADAPTOK lim BAT SYS BAT to SYS current limit ideal diode conducting 2 2 A RoN BAT SYS BAT to SYS switch ON 7 0 10 0 15 Q resistance Charger related VBAT battery supply voltage Active mode 2 8 5 0 V Vbatcond battery conditioning voltage vbatcond 00H 2 70 V vbatcond 01 2 85 V vbatcond 10 s 3 00 V vbatcond 11 3 15 V Vvisc voltage on pin VISCI2 2 4 V Vbat float prog programmable battery float programmable in 4 0 4 3 V voltage 20 mV steps via vm
62. Suspend No Yes Adapter Yes n a Charge amp Play Halt No Yes No Yes Yes n a Batfull No Yes No Yes Yes n a Isys gt ILim usB n a No Yes n a n a No Yes n a No Yes n a Adapt SYS USB SYS ext FET OFF OFF OFF OFF ON OFF OFF ON OFF OFF ON FETISI OFF CLIM CLIM ON OFFISI OFF CLIM CLIM OFF CLIM CLIM OFF USB BAT SYS BATcharger Ideal diode charger Vsys gt VBati4l OFF CHGBI CHG OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF CHG OFF OFF OFF OFF OFF OFF Vsys lt VBar ON OFF ON ON OFFISI OFF OFF ON OFF OFF ON OFF 1 2 3 4 5 6 Adapter presence is detected at the ADAPTSNS input USB presence is detected by a voltage comparator at the USBx inputs CLIM indicates current limiting mode resulting in a drop in Vsys when in Isys gt luiw usa as set via usbdevstat see Table 98 CHG means charging mode current controlled by charger Effectively no charging because all USB current is required by the system ON OFF status depends on the setting of the usbenasus bit the MBCC8 control register see Table 99 PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 83 of 125 jenuew Jes 8002 u24 N GO 90 9H SZL 40 v8 9 Wnee90940d p m sa syfu Iv 8002 NA dXN adaptpres 1 usbdevstat 11 or adaptpres 1
63. USB Precharge Wait Phase usbdevstat 11 amp usbpres 1 amp adaptpres 0 USB Suspend Mode usbdevstat 11 amp usbpres 1 amp adaptpres 0 usbdevstat 11 amp usbpres 1 amp adaptpres 0 USB Fast Charge Wait Phase usbpres 1 adaptpres usbdevstat 11 amp usbpres 1 amp adaptpres 0 Fig 39 Charger state diagram adaptpres 1 EIE Zv a9 Pre WDT expires or 86 58 usbpres 1 amp usbok 0 Eg za 25 SE Sg So nG YO EG a2 58 Ez 25 5 usbdevstat 11 amp Global condition for idle state chgena 0 or usbpres 0 amp adaptpres 0 usbpres 1 amp adaptpres 0 amp usbok 1 amp chgena 1 adaptpres 1 Battery temp OK amp usblim play 0 USB Precharge Battery temp too high or usbim_pay 1 Piese Battery temp OK amp usblim_play 0 USB Battery temp too high amp usblm play 1 Phase autostop 1 ICHG lt cutoffcur amp VBAT gt Vmax amp amp usblim_chg 0 amp 0 tim chg 0 amp autostop 1 WDT expires or usbpres 1 amp usbok 0 adaptpres 1 ICHG lt cutoffcur amp Vbat gt Vmax amp usblim_chg Fast Charge tim chg 0 amp adaptpres 1 amp adaptok 1 amp chgena 1 adaptpres 0 adaptpres 0 Battery temp Adapter too high Adapter Precharge Precharge Phase Battery temp Wait Phase OK o5 adaptpres 0 a os z a9 OX Z
64. UTOLXB2 AUTOOUT1 AUTOOUT2 DOWN1LX DOWN1IN DOWN1FB DOWN2LX DOWN2IN DOWN2FB LEDIN LEDLX LEDOUT LEDFB LEDFBGND LEDAMB NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 7 of 125 NXP Semiconductors PCF50633 PCF50633 User Manual 7 Pinning Information PCF50633UM 6 7 1 Pinning 1 2 3 4 Fig 2 ER 2 E EE E song Sym ae wee O QO TOON O Fis9ogREtERPDIBBOOBA lt A QALIL q0 terminal 1 eeo E e 5 999999 index area LO C1 NN O N 10 soc gg NENE 3 8 8 5 8 8 3 8 33 BATSNS Osc NTCSW OSCO HCLDOOUT BUBAT HCLDOIN AUTOLXA1 LDOSOUT AUTOIN1 LDO56IN AUTOIN2 LDO6OUT AUTOLXA2 ACCSW AUTOLXB1 ADCIN1 PCF50633 AUTOOUT1 ADCIN2 AUTOOUT2 VISA AUTOLXB2 REFGND ONKEY REFC SHUTDOWN GPIO3 KEEPACT GPIO2 EXTON3 GPIO1 EXTON2 iRQ EXTON1 amp fA ed aj e e At Ql oo SonLPESSERQES5SASR 3 Soee ooSES 222226098258 o 2555085 ee RE adb ano a m Transparent top view The VSS terminal is connected to the package exposed diepad and must be connected to ground This diagram is a top view The exposed diepad is visible from the bottom only Pin 1 is indicated with a dot in the upper left corner See Section 13 for a mechanical specification the HVQFN68 package Pin configuration for HVQFN68 package 7 2 Pin description Table 4 Pin description Symbol Pin Description Control inter
65. VMCTL control register see Table 35 All monitoring and internal control functions in the PCF50633 are activated Most power supplies remain off but all LDOs LDO1 through LDO6 MEMLDO and HCLDO may be enabled if required see Table 15 and Section 8 8 5 If Vsys falls below Vih sysok the PCF50633 will revert to the Save state Active The PCF50633 is fully functional in the Active state The host controller has full control through the serial I C bus interface Table 15 describes module activity in each state while Figure 5 illustrates the PCF50633 state diagram PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 16 of 125 NXP Semiconductors PCF50633 PCF50633UM 6 Table 15 Activity states and module activity PCF50633 User Manual Device state NoPower Save Standby Active Modules always on None OSC32 RTC INT GPIO OSC32 RTC INT GPIO SVM OSC32 RTC INT GPIO SVM BVM 12C THS Modules programmable ON or OFF None None LDO1 LDO6 HCLDO MEMLDO BVM CLK32K Others Modules always off All Others Others None NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 17 of 125 NXP Semiconductors PCF50633 PCF50633 User Manual Vsyg not OK Wake up by EXTONx ONKEY RTC alarm Vsys present USB or adapter connect Fig 5 PCF50633 power management state dia
66. W 0 automatic charge termination disabled charging is stopped by setting chgena 0 or when a watchdog timer time out occurs 1 automatic charge termination enabled charging stops when the charge current falls below the cutoffcur threshold see Table 97 or when a watchdog timer time out occurs 2 autores R W when set charging resumes automatically if the battery voltage falls below Vinres or 96 of the float voltage specified by vmax see Table 93 3 resumel l R W charging resumes when set and charger is in Battery Full mode see Figure 39 has no effect when autores 1 PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 77 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 PCF50633 User Manual Table 92 MBCC1 MBC charger control register 1 address 43h bit description Bit Symbol Access Description 4 restartl2 R W charging restarts when set and charger is in Halt mode see Figure 39 5 prewdtime R W maximum charging time during Precharge phase 0 30 minutes 1 60 minutes 7 6 wdtime R W maximum charging time after Precharge phase 00 1 hour 01 2 hours 10 4 hours 11 6 hours 1 This register is reset in NoPower state Reset values are determined by the IC variant see Table 7 2 Bit cleared once action completed Table 93 MBCC2 MBC charger control register 2 address 44h bit description Bit Symbol Access Description 1 0 vbatcond R W Vbatcona leve
67. WN2ENA DOWN2CTL DOWN2MXC MEMLDOOUT MEMLDOENA LEDOUT LEDENA LEDCTL LEDDIM RESERVED LDO1OUT LDO1ENA LDO2OUT LDO2ENA LDOSOUT LDOSENA LDO4OUT LDO4ENA LDOSOUT LDO5ENA LDO6OUT Mode R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Reset 11 STBY STBY STBY NOP STBY STBY STBY NOP NOP STBY STBY STBY STBY NOP STBY NOP STBY STBY STBY STBY STBY STBY STBY STBY STBY STBY STBY Bit 7 Bit 6 reserved auto maxcmod down1 out reserved reserved reserved downi maxcm od down2 out reserved reserved reserved down2 maxcm od reserved reserved reserved reserved reserved led dimstep reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Bit 5 auto maxc down1 ena act downi maxc down2 ena act down2 maxc memldo swm memldo out od Bit 4 down1 dvmstep down2 dvmstep memldo ena act led out led ena act ldo1 swmod ldo1 ena act Ido2 swmod ldo2 ena act ld03 swmod Ido3 ena act ld04 swmod ldo04 ena act ld05 swmod ldo5 ena act ld06 swmod ldo1 out ldo2 out Ido3 out Ido4 out Ido5 out Ido6 out Bit 3 down1 p3c down2 p3c memldo p3c led p3c ldo1 p3c Ido2_p3c Ido3_p3c Ido4_p3c Ido5_p3c Bit 2 down1 p2c down2 p2c memldo p2c led p2c led ocp
68. al description 47 Power supply sequencing 47 Supply module activation 47 Power failure detection 48 AUTO DOWN and DOWN converters 48 Introduction 000 eee eee eee 48 FeatureS 2 ce eee 48 Block diagrams 2 2 200 5 49 Hardware interface 51 Software interface 52 Functional description 56 continued 55 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 123 of 125 NXP Semiconductors PCF50633 8 9 6 1 8 9 6 2 8 9 6 3 8 10 8 10 1 8 10 2 8 10 3 8 10 4 8 10 5 8 10 6 8 10 6 1 8 10 6 2 8 10 6 3 8 10 6 4 8 10 6 5 8 10 6 6 8 10 6 7 8 10 6 8 8 11 8 11 1 8 11 2 8 11 3 8 11 4 8 11 5 8 11 6 8 11 6 1 8 11 6 2 8 11 6 3 8 11 6 4 8 12 8 12 1 8 12 2 8 12 3 8 12 4 8 12 5 8 12 6 8 12 6 1 8 12 6 2 8 12 6 3 8 12 6 4 8 12 6 5 8 12 6 6 8 12 6 7 8 12 6 8 8 12 6 9 8 12 6 10 8 12 6 11 8 13 8 13 1 PCF50633UM 6 Current limiting a 56 Dynamic voltage management DOWN1 and DOWN a rene NAG i hehe 56 AUTO configuration 005 57 LED boost converter amp Ambient Light Monitor ALM isse ri RR KANG eve 58 Introduction 58 CUA AA 58 Block diagram a 59 Hardware interface 59 Software interface 60 Functional description
69. ale mode divide by 2 or3 high voltage ADCIN2 and BATSNS 1 0 1 0 LSB inputs subtraction mode PCF50633UM_6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 97 of 125 NXP Semiconductors PCF50633 Table 106 ADC characteristics continued Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified PCF50633 User Manual Symbol INL Egain l Euttot towrup tconv tstRM Rntcsw Raccsw Z IL Parameter Conditions Min Typ Max Unit integral non linearity ADCIN1 and BATTEMP inputs 40 4 0 LSB high voltage ADCIN2 and BATSNS 4 0 4 0 LSB inputs full scale mode divide by 2 high voltage ADCIN2 and BATSNS 4 0 4 0 LSB inputs full scale mode divide by 3 high voltage ADCIN2 and BATSNS 12 0 412 0 LSB inputs subtraction mode gain error for ADCIN1 and BATTEMP inputs 1 0 41 0 96 total unadjusted error for ADCIN1 and 10 10 LSB BATTEMP inputs power up time 7 S us conversion time adcres 0 10 bit 28 us adcres 1 8 bit 23 us ratiometric settling time adcratioset 0 10 us adcratioset 1 100 us resistance of the VISA to NTC switch ntcswen 1 switch is closed 120 175 225 Q resistance of the VISA to ACC switch accswen 1 switch is closed 120 175 225 Q input impedance of the high voltage ADCIN2 250 360 kQ input during conversion leakage current on ADC inputs no 1 uA conversion in progress PCF50633UM_6 8 14 5 Softwar
70. analog preprocessing The BATSNS and the ADCIN2 inputs are high voltage terminals that can be used to measure voltages higher than the standard 2 0 V ADC range These higher voltages can be measured either by subtracting a reference voltage or by dividing the voltage by a specified factor Divider mode A resistive divider is used to divide the input voltage by a factor of 2 or 3 depending on the setting of bit adcdivsel in register ADCC3 see Table 109 This makes it possible to measure input voltages up to 5 5 V Bit adcinmux is set to 0000 or 0010 to measure a voltage on respectively BATSNS or ADCIN via the resistive divider see Table 107 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 100 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 14 6 3 PCF50633 User Manual The resistive divider is activated only during the ADC tracking and conversion phases It is kept floating at all other times resulting in negligible input currents The voltage on the BATSNS input in divide by two mode can be calculated using the following formula _ ACHT GUTEN S quis VBATSNS m 1023 6 where ADCDAT parsws is the 8 or 10 bit result stored in the status registers Subtraction mode The input voltage is processed by a subtraction circuit that allows for an ADC input range of 2 25 V to 4 25 V The subtraction process provides enhanced resolution in the fully charged battery voltage range This m
71. ar regulator mode 1 switch mode 7 6 reserved 1 This register is reset at each transition to Standby state Reset values are determined by the IC variant see Table 7 Table 63 MEMLDOENA MEMLDO output enable register address 27h bit description Bit Symbol Access Description 0 memldo on R W if set LDO is ON memldo pic RAN if set LDO is ON when GPIO1 1 memldo p2c RAN if set LDO is ON when GPIO2 1 memldo p3c R W if set LDO is ON when GPIO3 1 5 4 memldo ena act R W selects activation phase 00 ACTPH1 01 ACTPH2 10 ACTPHS 11 ACTPH4 7 6 reserved 1 This register is reset at each transition to Standby state Reset values are determined by the IC variant see Table 7 Table 64 DCDCPFM DCDC force PFM control address 84h bit description Bit Symbol Access Description 0 autopfm2 R W if set the AUTO converter is temporarily forced to PFM mode PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 55 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 9 6 8 9 6 1 8 9 6 2 PCF50633 User Manual Table 64 DCDCPFM DCDC force PFM control address 84h bit description continued Bit Symbol Access Description 1 down1pfml l R W if set the DOWN1 converter is temporarily forced to PFM mode 2 down2pfml2 R W if set the DOWN converter is temporarily forced to PFM mode 7 3 reserved 1 Register is reset in NoPower state
72. are interface 12 BG i 8 6 3 8 1 5 Software interface a 12 i aa 8 6 4 8 1 6 Functional description 15 86 5 8 1 6 1 Activity states 15 8 6 6 8 1 6 2 Transitions between activity states 18 87 8 1 6 3 Time out timer a 21 87 1 8 1 6 4 ONKEY control input 21 872 8 1 6 5 EXTON control inputs 23 873 8 1 6 6 SHUTDOWN control input 23 874 8 1 6 7 go stbybit a 23 87 5 8 1 6 8 Activity phases aa 24 87 6 8 1 6 9 Resetoutputs 00 eee ee 25 88 8 1 6 10 CLK32K output 2005 25 8 8 1 8 1 6 11 KEEPACT input 0 25 882 8 1 6 12 Debounce filters 26 88 3 8 1 6 13 COLDBOOT flag 26 884 8 1 6 14 Types of control register 27 8 8 5 8 2 Interrupt Controller INT 27 8 8 6 8 2 1 Introduction 27 88 6 1 8 2 2 Features 2 cds sc ses br PRSE 27 88 62 8 2 3 Block diagram eee eee eee 27 8863 8 2 4 Hardware interface 28 89 8 2 5 Software interface 0000 28 89 1 8 2 6 Functional description 31 892 8 3 General Purpose Input Output GPIO GPO 32 89 3 8 3 1 Introduction 32 894 8 3 2 Feat res ak pA Aha na spere pie Pepe 32 895 8 3 3 Block diagram aa 33 896 PCF50633UM 6 Hardwa
73. attery Charger BBC 93 Introduction 93 8 13 2 8 13 3 8 13 4 8 13 5 8 13 6 8 14 8 14 1 8 14 2 8 14 3 8 14 4 8 14 5 8 14 6 8 14 6 1 8 14 6 2 8 14 6 3 8 14 6 4 8 15 8 15 1 8 15 2 8 15 3 8 15 4 8 15 5 8 15 5 1 8 15 5 2 8 15 6 8 15 7 8 16 8 16 1 8 16 2 8 16 3 8 16 4 8 17 8 17 1 8 17 2 8 17 3 8 17 4 8 17 5 8 17 5 1 8 17 6 8 17 7 8 17 8 8 17 9 8 17 10 8 17 11 8 18 9 10 11 PCF50633 User Manual Features ues Rada arg ka 93 Block diagram a 94 Hardware interface 94 Software interface 95 Functional description 95 10 bit Analog to Digital Converter ADC 96 Introduction e na ann aana 96 FeatureS i2 264 maha a bk da aba haahaha 96 Block diagram a 97 Hardware interface 97 Software interface 98 Functional description 100 Overview eee 100 High voltage ADC inputs and analog preprocessing aa 100 Low voltage ADC inputs and ratiometric measurement esras aa e eee 101 ADC conversion control 102 Real time clock RTC 102 Introduction a 102 SEA AA 102 Block diagrams a 103 Hardware interface 103 Software interface 103 RTC time registers 103 RTC date registers 104 RTC alarm register
74. attery programmable in 0 6 1 35 V high temperature threshold 50 mV steps using ntclvt bits twDT pre precharge Watchdog Timer prewatime 0 30 min WDT time out time prewatime 1 60 m tWDT ist fast charge watchdog timer watime 00 1 hour time out time watime 01 2 hour watime 10 4 hour watime 11 6 hour Ci BAT input capacitance on BATx 116 uF pins Cisys input capacitance on SYSx 2216 uF pins Tlim USB BAT temperature limit for USB BAT 108 C FET Tim usB sys temperature limit for USB SYS 118 C FET 1 See register MBCC2 Table 93 for detailsof vbatcond control bits 2 Note that Vyisc is an internal signal Pin VISC is provided to allow an external decoupling capacitor to be connected Decoupling is necessary to ensure stable operation 3 lch rer is defined as 12500 RcuHa where Rere is the value of an external resistor connected between pin CHGCUR and ground 4 lcua leh ret x prechgcur 255 To select the maximum charge current of 1 A a 12500 W resistor should be connected and bits prechgcur 11111111 see Table 94 5 Absolute minimum with guaranteed performance is 50 mA 6 Typical value of assume X5R X7R type capacitors 8 12 5 Software interface Table 92 MBCC1 MBC charger control register 1 address 43h bit description Bit Symbol Access Description 0 chgena R W 0 charger is disabled charger detection still active 1 charger enabled 1 autostop R
75. attery temperature and identification measurement ADC conversion control The ADC module can be configured as an 8 or 10 bit converter via the adcres control bit in the ADCC1 register see Table 107 8 bit is faster than 10 bit conversion and may be preferred when the digital resolution is not critical 8 bit conversion is completed a full 2 clock cycles faster than the equivalent 10 bit conversion In addition the 8 bit result can be read in a single I C bus read cycle considerably reducing data communication times A power up and conversion sequence at 8 bit resolution typically takes 30 us The conversion can be performed and the results read back in the space of two sequential I2C bus access cycles it will take at least 40 us at a 400 kbit s I2C bus speed Real time clock RTC Introduction The RTC module provides timing information for the application based on a 1 Hz clock frequency It contains a calendar function that automatically takes account of differing month lengths and leap years Features Periodic second interrupt Enabled in all states except NoPower NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 102 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 15 3 8 15 4 8 15 5 8 15 5 1 PCF50633 User Manual Alarm wake up function Automatic leap year correction Block diagrams i second interrupt time registers i alarm interrupt
76. ature Tstg storage temperature Vesd electrostatic discharge voltage Conditions on any pin with respect to REFGND DC at any control input DC at any control output HBMI MME CDMEl 2 3 2 3 Min 0 5 0 5 0 5 0 5 0 5 10 10 Max 5 5 5 5 5 5 5 5 5 5 10 10 2000 85 150 1000 2000 100 200 500 Unit lt lt lt lt mA mA mW C lt lt lt lt lt 1 Human Body Model equivalent to discharging a 100 pF capacitor via a 1 5 kQ resistor 2 Pins AUTOIN1 AUTOIN2 AUTOLXA1 AUTOLXA2 AUTOLXB1 AUTOLXB2 AUTOOUT1 AUTOOUT2 DOWN1IN DOWNZIN DOWN1LX DOWN2LX LEDIN LEDLX and LEDOUT 3 Pins other than those listed in Table note 2 above 4 Machine Model equivalent to discharging a 200 pF capacitor via a O Q resistor 5 Charge Device Model PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 117 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 11 Thermal characteristics Table 140 Thermal characteristics Symbol Parameter Package Typ Unit Rth j a inf Thermal resistance from junction to ambient in free air HVQFN68 10 K W mounted on infinite heatsink Rth j a pcb Thermal resistance from junction to ambient typical 40 K W PCB situation PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 118 of 125
77. available for using HCLDO as a switch 1 Switch with minimum quiescent current and no current limiting This mode is selected by setting the hcldo swmod bit in the HCLDOOUT control register see Table 88 2 Switch with current limiting This mode is selected by programming the HCLDO output voltage to a higher level than its input voltage Main Battery Charger MBC Introduction The MBC is a constant current constant voltage CCCV charger It has separate inputs for USB and adapter power sources USB current limiting is supported Features Operates independently of the PCF50633 power management unit Separate power inputs for adapter and USB including presence detectors which can wake up the PCF50633 and generate interrupts Controlled system supply output obtained from one of the inputs and or the battery USB input current limiter with programmable current limit Reverse current blocking from battery to USB input USB suspend mode support Automatic switch to battery when input supply is not capable of supplying required system power ideal diode functionality Current limiting in the ideal diode Constant Current Constant Voltage CCCV charger Programmable precharge and fast charge current levels for both USB and adapter Programmable float voltage Only 4 external components required a resistor to set the fast charge CC current a Negative Temperature Coefficient NTC bridge for measuring battery
78. ax Vbat float battery float voltage single cell Li lon Voat float prog Vbat loa prog Vbat float prog V Li Pol 196 196 Ich ref charger reference currenti defined as 0 1000 mA 12500 RexicHGCUR excluding tolerance of 0 95 x leh ref 1 05 x mA external resistor len ret 3 len ref 3 RexcHacur external resistor connected between pin 12 5 kQ CHGCUR and ground lon Batx 4 charge current on pin BATx precharge phase 0 s 255 25bx mA defined as Ich ref x Ich ref prechgcur 255 excluding tolerance of 0 9 x Ich BATx 1 1x mA external resistor lch BATx 361 len BATX 3 adapter fast charge 0 255 255 x mA phase defined as loh ref lentret X fstchgcur1 255 excluding tolerance of 0 9 x lch BATx 1 1x mA external resistor Ich BATx 35 lch BATx 3 USB fast charge 0 255 255 x mA phase defined as lch ref len ret X fstchgcur1 255 excluding tolerance of 0 9 x Ich BATx 1 1x mA external resistor loh BATx 3B Ich BATx 3 Vih RES charge resume threshold 0 96Vpattioa V voltage t prog PCF50633UM_6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 76 of 125 NXP Semiconductors PCF50633 PCF50633 User Manual Table 91 MBC characteristics continued Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Vih TBATMIN battery low temperature 1 9 2 0 2 1 V threshold voltage Vih TBATMAX NTC voltage level for b
79. battery voltage Vaugar gt Vsys Charging will resume automatically when neither of these conditions applies If the output resistor is active bit bbcr 0 the charge current will gradually ramp down as illustrated in Figure 46 lBBC IBBC gt prog value BBCC 11 400 uA SO0UA BBCC 10 dV dl Rout 400 ua BECC BBCC 00 50 uA VBUBAT te VDELTA VLiM 2 5 V 3 0 V VTH LIM Fig 46 BBC characteristics with output resistor bbcr 0 If the output resistor has been bypassed bit bbcr 1 the charge current will abruptly drop to zero as illustrated in Figure 47 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 95 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 14 8 14 1 8 14 2 PCF50633 User Manual lBBC IBBC gt prog value bbcc 11 400 uA 200 uA bbcc 2 10 100 uA bbcc 01 bbcc 00 50 uA VBUBAT VLiM 2 5 V 3 0 V Fig 47 BBC characteristic without output resistor bbcr 1 10 bit Analog to Digital Converter ADC Introduction The ADC is a 10 bit successive approximation converter Voltage division and subtraction functionality is incorporated for high voltage measurements Features Selectable 8 or 10 bit resolution Measurement averaging is programmable Selectable battery voltage measurement Selectable battery temperature measurement Selectable NTC meas
80. by state Reset values are determined by the IC variant see Table 7 Table 83 LDO4ENA LDO4 output enable register address 34h bit description Bit Symbol Access Description 0 ldo4 on R W if set LDO is ON Ido4_pic R W if set LDO is ON when GPIO1 1 2 ldo4 p2c R W if set LDO is ON when GPIO2 1 3 Ido4_p3c R W if set LDO is ON when GPIO3 1 5 4 do4 ena act R W selects activation phase 00 ACTPH1 01 ACTPH2 10 ACTPH3 11 ACTPH4 7 6 reserved 1 This register is reset at each transition to Standby state Reset values are determined by the IC variant see Table 7 Table 84 LDO5OUT LDO5 output voltage select register address 35h bit descriptionl Bit Symbol Access Description 4 0 ldo5 out R W Votprog 0 9 do5 outx 0 1V max 3 6 V eg 00000 0 9 V 00001 1 0 V 11011 3 6 V 11111 3 6 V 5 ld05 swmod R W 0 linear regulator mode 1 switch mode 7 6 reserved 1 This register is reset at each transition to Standby state Reset values are determined by the IC variant see Table 7 Table 85 LDO5ENA LDO5 output enable register address 36h bit description Bit Symbol Access Description 0 Ido5_on R W if set LDO is ON Ido5_pic R W if set LDO is ON when GPIO1 1 2 Ido5_p2c R W if set LDO is ON when GPIO2 1 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 71 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 PCF50633 User Man
81. ced very thin quad flat package no leads 8SOT852 2 68 terminals body 8 x 8 x 0 85 mm 1 xx indicates the IC variant PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 6 of 125 NXP Semiconductors PCF50633 6 Functional Diagram PCF50633 User Manual PCF50633UM 6 ADCIN1 ADCIN2 ACCSW NTCSW BATSNS BATTEMP ADAPTCTRL ADAPTSNS CHGCUR USB1 USB2 BAT1 BAT2 SYS1 SYS2 VISC VISA REFC BUBAT OSCI OSCO CLK32K SCL SDA RSTHC IRQ SHUTDOWN KEEPACT ONKEY EXTON1 EXTON2 EXTON3 GPIO1 GPIO2 GPIO3 GPO REFGND vss Fig 1 a 1a la Q o o o IN o o N j a N o 10 bit ADC Main Battery Charger MBC a um o m2 gt Ss lo JO o j j j AQ O IN a a O o N Internal Supply amp Reference Backup Battery Charger 32 kHz Oscillator PCF50633 memory Reset Generator Interrupt Control Parallel IF Functional diagram of the PCF50633 System HDD Auto Up Down Converter AUTO Core Buck Converter DOWN1 Memory Buck Converter DOWN2 MEMLDO LED Boost Converter LED Ambient Light Monitor eB o QO Bo m eB a jo N OD oO t1 gt N a B aja je la O j gt o A m 32 LDO1OUT LDO12IN LDO2OUT LDOSOUT LDO34IN LDOA4OUT LDOSOUT LDO56IN LDO60UT HCLDOIN HCLDOOUT AUTOIN1 AUTOIN2 AUTOLXA1 AUTOLXA2 AUTOLXB1 A
82. cess Description 4 0 4do3 out R W Vo prog 0 9 do3 outx 0 1 V max 3 6 V eg 00000 0 9 V 00001 1 0 V 11000 3 3 V 11011 3 6 V 11111 3 6 V 5 ld03 swmod R W 0 linear regulator mode 1 switch mode 7 6 reserved 1 This register is reset at each transition to Standby state Reset values are determined by the IC variant see Table 7 Table 81 LDO3ENA LDO3 output enable register address 32h bit description Bit Symbol Access Description 0 Ido3_on R W if set LDO is ON Ido3_pic R W if set LDO is ON when GPIO1 1 2 Ido3_p2c R W if set LDO is ON when GPIO2 1 3 ld03 p3c R W if set LDO is ON when GPIO3 1 5 4 do3 ena act R W selects activation phase 00 ACTPH1 01 ACTPH2 10 ACTPH3 11 ACTPH4 7 6 reserved 1 This register is reset at each transition to Standby state Reset values are determined by the IC variant see Table 7 PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 70 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 PCF50633 User Manual Table 82 LDO4OUT LDO4 output voltage select register address 33h bit descriptionl Bit 8 Symbol Access Description 4 0 ldo4 out R W Vo prog 0 9 do4 outx 0 1 V max 3 6 V eg 00000 0 9 V 00001 1 0V 11011 3 6 V 11111 3 6 V 5 ld04 swmod R W 0 linear regulator mode 1 switch mode 7 6 reserved 1 This register is reset at each transition to Stand
83. ch supply module can be activated deactivated individually according to the settings of the following control bits e The x_ena_act control bits which determine which activation phase is associated with the module see for example auto_ena_act which when 00 selects activation phase 1 for the Auto converter see Table 51 The x pxc control bits When an x pxc control bit is set the module is activated if the associated GPIOx pin goes HIGH see for example auto p1c which when set turns the AUTO converter on when GPIO1 1 see Table 51 e The x_on control bit which when set activates the module during the assigned activity phase regardless of the state of the GPIOx pins see for example auto on which when set turns the AUTO converter ON ignoring the state of the GPIOx pins For each supply module there is an associated control register containing these control bits see for example register AUTOENA for AUTO Table 51 Their reset values are mask programmable All LDOs can be enabled in Standby state as well as in Active state Control bit x ena stb determines whether an LDO will be on or off in Standby state see Table 40 and Table 41 The volatile memory is intended to be supplied by DOWN in Active state and by MEMLDO in non active states e DOWN is enabled in Active state if down2 onis set or if one of the down2 pxc bits is set and the associated GPIOx pin is HIGH DOWN cannot be active in any other state s
84. down resistor DOWNX is disabled 120 Q connected to the output Table 49 MEMLDO characteristics Vss REFGND GND O V Tamp 40 to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit lo output current a 1 mA VI input voltage LDO operated as regulator 2 7 55 V LDO operated as low 18 55 V ohmic switch Vovprog programmable output programmed via 09 3 6 V voltage memldo out bits Vo step output voltage step size 100 mV Vo output voltage 3 0 Vofprogy 3 Yo AVo Al load regulation 1 0 9o mA AVo AV line regulation 1 2 mvV V NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 51 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 1 MEMLDO shares input DOWN2IN and output DOWN2FB pins with DOWN2 MEMLDO is automatically disabled if DOWNe is enabled 8 9 5 Software interface Table 50 AUTOOUT AUTO output voltage select register address 1Ah bit description Bit Symbol Access Description 7 0 auto out R W Vo prog 0 625 auto out x 0 025 V eg 00000000 to 00101110 reserved 00101111 1 8 V min 01010011 2 7 V 01101010 3 275 V 01101011 3 300 V 01101100 3 325 V 01111111 3 800 V max 11111110 3 800 V 11111111 3 800 V 1 This register is reset at each transition to Standby state Reset value is determined by the IC variant see Table 7 Table 51 AUTOENA AUTO output enable register address
85. e 01 5 ms 10 14 ms 11 62 ms 3 2 exton2 deb R W 10 debounce time for EXTON2 timing same as for bits 1 0 5 4 exton3 deb R W 10 debounce time for EXTON3 timing same as for bits 1 0 7 6 shdwn deb R W 10 debounce time for SHUTDOWN timing same as for bits 1 0 1 Register is reset in NoPower state NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 13 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual Table 11 OOCTIM2 OOC debounce register 2 address OFh bit description Bit Symbol Access Reset Description 2 0 onkey deb R W 010 debounce time for ONKEY 000 none 001 5 ms 010 14 ms 011 62 ms 100 200 ms 101 500 ms 110 1000 ms 111 2000 ms 4 3 actphdel R W 01 delay between activation phases 00 5 ms 01 10ms 10 15 ms 11 20ms 6 5 horstdel R W 10 delay between selected activation phase and host controller reset 00 3ms 01 6ms 10 13ms 11 26ms 7 almon R W 0 0 ambient light monitor disabled 1 ambient light monitor enabled 1 This register is reset at each transition to Standby state Table 12 OOCMODE OOC mode register address 10h bit descriptionl Bit Symbol Access Description 1 0 exton mode R W EXTON1 mode selection 00 wake up on falling edge only 01 wake up on rising edge only 10 wake up on falling edge only rising edge sets the time out timer to 8 seconds 11 wake up on rising edge only falling edge sets the time out timer
86. e 93 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 89 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 PCF50633 User Manual When the battery voltage reaches Vpatcond the MBC enters the Fast Charge phase provided if battempena is set the battery temperature is within a specified temperature window see Table 98 A constant fast charge current CC mode is applied until the battery voltage reaches the specified float level bits vmax in register MBCC2 see Table 93 If the battery voltage reaches Vpatcond but the battery temperature is not within the specified temperature window with battempena enabled precharging continues until the battery voltage reaches the specified float level vmax If the battery temperature rises above the high temperature threshold in Precharge phase the MBC will enter Precharge Wait phase and charging will stop Charging will resume once the battery temperature falls below the high temperature limit The charger will also enter the Precharge Wait phase if USB SYS FET current limiting is activated usb play 1 Charging will resume when USB SYS FET current limiting is deactivated When the battery voltage reaches the float level vmax vlim is set in register MBCS3 see Table 102 and charging continues at a constant voltage CV mode During this phase the charger keeps the battery voltage constant at the specified float level The charge current wil
87. e current no interrupts are generated when the thermal regulation loop starts or stops limiting the charge current Battery temperature detection circuit The VISA to NTC switch in the on chip A D Converter which can be used to accurately measure battery temperature is also controlled by the MBC The equivalent circuit is illustrated in Figure 44 The following steps should be followed to configure the PCF50633 for battery temperature detection Determine the NTC resistance at low temperature threshold specified for battery Calculate Rrixep such that the voltage on BATTEMP equals Vin rBATMIN Determine the NTC resistance at high temperature threshold specified for battery Calculate the voltage on BATTEMP at the high temperature threshold ar UO N gt Set VinrBATMAx to the calculated value via bits ntclvt programmable in 50 mV see Table 91 and Table 99 The battery temperature status whether it is above below or within the temperature window defined by the low and high temperature thresholds can be obtained by reading the tbatstat status bits in Table 100 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 92 of 125 NXP Semiconductors PCF50633 PCF50633 User Manual BATx VISA to NTC switch visa Nrcsw BATTEMP RrixED MBC Vih TBATMIN mintemp maxtemp lt Vih TBATMAX
88. e in response to 1 being written to go stby Activity State ACTPH4 Y acrPHs X ACTPH2 ACTPH1 x STANDBY Programming go_stby control bit T 2ms Fig 10 GO STBY timing 8 1 6 8 Activity phases There are 4 distinct phases involved in a state transition to or from the Active state see Figure 10 above This is necessary to enable power supply and reset signal sequencing The actphdel control bits bits 4 3 in control register OOCTIM2 see Table 11 set the delay between the phases The ACTPH1 to ACTPHA signals are available as GPIO or GPO outputs The sequence is followed for all shutdown conditions with the exception of an emergency shutdown Vsys lt Vih sysmin in which case there is an immediate transition to the Save state Wake up 1 event Shutdown 4 event ACTPH1 pe ACTPH2 ACTPH3 ACTPH4 tphdel ha tphdel gt a tphidel lg tphdel ha tphdel lt ta tphdel clk32k RSTHC kx trstdel Fig 11 Activity phases during transition to and from the Active state PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 24 of 125 NXP Semiconductors PC F50633 8 1 6 9 8 1 6 10 8 1 6 11 PCF50633UM 6 PCF50633 User Manual Reset outputs The RSTHC output signal is intended to drive the reset input of the host controller It is
89. e interface Table 107 ADCC1 A D converter control register 1 address 54h bit description Bit Symbol Access Reset 0 adcstart R W 0 1 adcres R W 0 3 2 adc av R W 00 7 4 adcinmux R W 0000 Description ADC conversion start command starts when set ADC resolution selection 0 10 bit resolution 1 8 bit resolution measurement averaging 00 no averaging single sample 01 averaging over 4 samples 10 averaging over 8 samples 11 averaging over 16 samples ADC input selection 0000 BATSNS pin via resistive divider 0001 BATSNS pin via subtractor 0010 ADCIN via resistive divider 0011 ADCIN2 via subtractor 0100 reserved 0101 reserved 0110 BATTEMP 0111 ADCIN1 1000 1111 reserved 1 This register is reset in NoPower state NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 98 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual Table 108 ADCC2 A D converter control register 2 address 53h bit description Bit Symbol Access Resetl Description 1 0 adcratioen R W 00 ratiometric measurement selection 00 no ratiometric mode measurement 01 ratiometric mode for BATTEMP only 10 ratiometric mode for ADCIN1 only 11 ratiometric mode for BATTEMP and ADCIN1 2 2 adcratioset R W 0 ratiometric settling time 0 2 10us 1 100 us 7 3 reserved 1 This register is reset in NoPower state 2 If adcratioen is set to 11 the result of the
90. ected and USBBATCHK 1 a transition from Save to Standby will only occur if Vgat gt Vinbatok and Vsys gt Vih sysok A transition from Standby to Save will occur if Vgat lt Vin batok OF Vsys lt Vih sysok 3 If the system voltage drops below Vin sysok a lowsys interrupt is generated and the time out timer is started The SYSOK status bit is reset see Table 14 and Table 20 4 If the system voltage drops below Vinsysmin an emergency shutdown is initiated and the system transitions to the Save state 5 If the system voltage drops below Vin syspres and no backup battery is present bubpres 0 see Table 14 the system will be reset and enter the NoPower state If a backup battery is connected Vgusat gt VinguBPREs the PCF50633 will continue in Save mode powered by the backup battery 6 If the system voltage is below Vin syspres the system will continue to operate in the Save state as long as bubpres 1 Vausar gt Vih bubpres See Table 14 If bubpres changes to O the system will be reset and enter the NoPower state PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 5 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual Table 2 Overview power supplies Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified Supply Maximum Minimum Maximum Output Switching Quiescent PSRRI Output Inductor Name output output output voltage fre
91. ee Table 59 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 47 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 8 6 3 8 9 8 9 1 8 9 2 PCF50633 User Manual MEMLDO can be enabled in Active and Standby states according to the settings of memldo ena act memldo ena stb and memildo pxc see Table 41 and Table 63 Note however that MEMLDO is automatically disabled if DOWN is enabled The LDOs can be enabled in the Standby state as well as in the Active state The DC to DC converters can only be enabled in the Active state Since converters are more efficient than LDOs they are usually employed in preference to LDOs in the Active state when possible MEMLDO and DOWN will normally be programmed to deliver the same output voltage DOWN will be employed in the Active state while MEMLDO will be enabled when the PCF50633 is in Standby Power failure detection Power failure detection is implemented for all regulators except MEMLDO A power failure is detected when the module is enabled and its output voltage is lower than 90 of the target value for a period longer than the power failure detection debounce time The power failure detection debounce time can be set to any of 4 values via the x debpf control bits see Table 42 Table 43 and Table 44 Both falling and rising edges of the power failure signal are debounced When a supply module is switched on the associated x pwro
92. emperature limit The charger will also enter the Fast Charge Wait phase if USB SYS FET current limiting is activated usb play 1 Charging will resume when USB SYS FET current limiting is deactivated If the battery temperature falls below the low temperature threshold in either USB or Adapter Fast Charge phase the MBC will enter Precharge Wait phase The tbatstat status bits in register MBCS1 see Table 100 indicate whether the battery temperature is within above or below the valid temperature window As a safety precaution a watchdog timer is started from zero when the MBC enters Fast Charge phase If the watchdog timer expires after twpr s minutes charging stops and the MBC enters Halt mode twp1 isy is specified via the watime bits in the MBCC7 register see Table 92 The watime control bits are updated in all charger modes If autores 0 the MBC will remain in Halt mode until the restart bit in the MBCC7 control register is set If autores 1 the MBC will return to the Play Only mode when the battery voltage falls below the resume threshold Vgar lt Vin ngs see Table 92 and Figure 39 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 91 of 125 NXP Semiconductors PC F50633 8 12 6 10 8 12 6 11 PCF50633UM 6 PCF50633 User Manual Note that the watchdog timer only counts down while the charger is in USB Adapter Fast Charge phase It is halted when the charger is in USB
93. ent push pull output GPO GPIOx signal direction input or output is determined by the bit settings in control register GPIOCTL see Table 29 8 3 2 Features PCF50633UM 6 e GPO has a high current push pull output GPIOs have high current open drain outputs GPIOs are input output configurable Selectable output functions Selectable output inversion The GPO can be configured in conjunction with the LED converter and an external FET to generate output voltages in excess of Vo LED max see Table 66 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 32 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 8 3 3 Block diagram GPIO GPO LEDIN GPO GPIOx internal GPIOxCFG internal Software Interface signals to be output Fig 17 GPIO GPO block diagram 8 3 4 Hardware interface Table 27 GPIO characteristics Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Vit LOW level input voltage GPIO is set to input 0 0 5 V Vig HIGH level input voltage GPIO is set to input 1 0 5 5 V Vn maxHl maximum voltage on all pins 5 5 V sink sink current active low ON mode switch 0 100 mA closed IL leakage current 3 state mode switch open 5 uA VoL LOW level output voltage lo 100 mA 0 3 0 35 V 1 High voltage spikes could occur on the GPIOx
94. er creates a smooth semi logarithmic ramp up or ramp down of the LED current when the LED module is switched on or off The maximum value is determined by the settings of the led out control bits The ramp time is set by the led dimstep control bits in the LEDDIM register see Table 70 intensity time Fig 31 Ramp curve of LED converter Overvoltage protection The overvoltage protection circuit checks for an overvoltage condition on the output of the LED converter The overvoltage protection limit is set to Voi gpymax Overvoltage protection can be disabled by clearing the led ovpon bit in the LEDCTL register see Table 69 When an overvoltage is detected an edovp interrupt is generated and the LED module is shut down The module can be restarted by setting the led ovprst bit in the LEDCTL register Overcurrent protection Overcurrent protection is implemented to avoid saturation of the external coil The overcurrent protection limit is programmable to 500 mA or 1000 mA via the led ocp control bit in the LEDCTL register see Table 69 The circuit measures the current through the primary switch and disables the switch as soon as the current exceeds the OCP limit Current limiting is performed cycle by cycle and no signalling to the interrupt generator or to the OOC block is implemented Inrush current limiting At start up the output node is raised to the input voltage level using a small current Thereafter regula
95. er state all bits set to 0 Table 23 INT2MASK Interrupt mask register 2 address 08h bit description Bit Symbol Access Description 0 onkeyrm R amp C masks onkeyr interrupt when set 1 onkeyfm R amp C masks onkeyf interrupt when set 2 extonirm R amp C masks extonfr interrupt when set 3 exton1fm R amp C masks exton7f interrupt when set 4 exton2rm R amp C masks exton2r interrupt when set 5 exton2fm R amp C masks exton2f interrupt when set 6 exton3rm R amp C masks exton3r interrupt when set T exton3fm R amp C masks exton3f interrupt when set 1 This register is reset in NoPower state all bits set to 0 Table 24 INT3MASK Interrupt mask register 3 address 09h bit description Bit Symbol Access Description 0 batfullm R amp C masks batfull interrupt when set 1 chghaltm R amp C masks chghalt interrupt when set 2 thlimonm R amp C masks thlimon interrupt when set 3 thlimoffm R amp C masks thlimoff interrupt when set 4 usblimonm R amp C masks usblimon interrupt when set 5 usblimoffm R amp C masks usblimoff interrupt when set 6 adcrdym R amp C masks adcrdy interrupt when set 7 onkey1sm R amp C masks onkey1s interrupt when set 1 This register is reset in NoPower state all bits set to 0 Table 25 INTAMASK Interrupt mask register 4 address OAh bit description Bit Symbol Access Description 0 lowsysm R amp C masks owsys interrupt when set lowbatm R amp C masks lowbat interrupt when set 2 hightmpm R amp
96. erved memldo ena s tb NOP led debpf NOP Ido4 debpf NOP reserved NOP reserved NOP reserved NOP hcldo ovi hcldo pwrok NOP wdtime NOP vresdebtim reserved e NOP prechgcur NOP fstchgcur1t NOP fstchgcur2 NOP reserved NOP batsysimax NOP reserved NOP wdtexp prewdtexp NOP reserved resstat NOP vres vbatcond NOP reserved NOP reserved NOP alm data alm_data NOP reserved NOP reserved NOP reserved Bit 5 Ido6 ena act hcldo swmod hcldo ena act reserved reserved down2 debpf ld03 debpf hcldo debpf ld06 pwrok prewdtime vmax reserved tbatstat chgstat vlim alm data Bit 4 hcldo out ld03 ena stb hcldo ena stb ld05 pwrok restart cutoffcur usbenasus ilim bbcv alm gain alm data adcdivsel Bit 3 ld06 p3c hcldo p3c reserved reserved down1 debpf Ido2 debpf ld06 debpf led pwrok ld04 pwrok resume ntclvt adaptok mbcmod tlim chg bbcc alm data reserved Bit 2 ld06 p2c hcldo p2c ldo2 ena stb ld06 ena stb down2 pwrok ld03 pwrok autores battempena adaptpres tlim play alm data ntcswen adcratioset Bit 1 ld06 pic hcldo pic reserved reserved auto debpf ldo1 debpf Ido5_debpf hcldo debovl down1 pwro k ld02 pwrok autostop vbatcond usbdevstat usbok usblim chg bbcr alm data reserved adcratioen Bit 0 ld06 on hcldo on ldo1 ena stb Ido5 ena stb aut
97. ery management Battery charge and play system Supports single cell Li lon batteries Separate adapter and current limited USB inputs Application can operate from external source when battery is low or not connected Battery remains fully charged after charging as long as an external power supply is connected Programmable precharge and fast charge currents Integrated power transistors Thermal regulation loop controls charge rate at maximum device temperature Undervoltage lockout detectors with programmable thresholds Backup battery input for RTC supply when main battery is empty e Backup battery charger 2 4 ADC 10 bit resolution e 4 input pins Analog preprocessor offering input voltage division and subtraction Direct and ratiometric measurement modes 3 Applications e Hard disk based portable media players e Flash based portable media players PDAs e Smartphones PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 4 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 4 Quick reference data Table 1 Quick reference data Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Vsys system supply voltage Active mode 2 8 53 V VBAT battery supply voltage Active mode 28 5 V VBUBAT backup battery supply voltage 1 6 3 V VapaPrTsNs Voltage on pin ADAPTSNS
98. et 1 ld02 pwrok R 0 LDO2 Vo 909 of target 1 LDO2 VVo gt 90 of target 2 ld03 pwrok R 0 LDO3 Vo 90 of target 1 LDO3 Vo gt 90 of target 3 Ido4_pwrok R 0 LDO4 Vo lt 90 of target 1 LDO4 Vo gt 90 of target PCF50633UM_6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 46 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 8 6 8 8 6 1 8 8 6 2 PCF50633 User Manual Table 46 LDOSTAT LDO status register address 42h bit description continued Bit Symbol Access Description 4 ld05 pwrok R 0 LDO5 Vo 90 of target 1 LDO5 Vo gt 90 of target 5 ld06 pwrok R 0 LDO6 Vo 90 of target 1 LDO6 Vo gt 90 of target 6 hcldo_pwrok R 0 HCLDO Vo lt 90 of target 1 HCLDO Vo gt 90 of target 7 hcldo_ovl R 0 HCLDO is not in overload mode 1 HCLDO is in overload mode Functional description Power supply sequencing The supply modules can be activated or deactivated during any of the four phases involved in a transition to or from the Active state see Section 8 1 6 8 This makes it possible to satisfy supply sequence requirements and reduces battery load by spreading inrush current peaks over time Each supply is assigned to one of the four phases by means of the associated x_ena_act control bits in the relevant control register See for example control bits auto_ena_act in Table 51 Supply module activation When the PCF50633 is in Active state ea
99. external photodiode connected between the VISA and LEDAMB pins using a current to time converter circuit which provides at least a 3 decade photo current range The full scale setting is determined by the value of the capacitor connected between the LEDAMB and REFGND pins and the a m gain gain bits in the ALMGAIN control register see Table 71 The value of the capacitor is determined by the equation Carm IDmax X 76 us 3 where lp max represents the photodiode current under maximum ambient lighting conditions The alm gain control bits make it possible to adjust the ambient light control loop for variations in the sensitivity of the photodiode The ambient light measurement is repeated every 20 ms A low pass filter removes high frequency disturbances from the ambient light control loop The LEDAMB pin can be grounded or left open if the ambient light monitor is not being used PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 65 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 PCF50633 User Manual VLEDIN Vvisa kaaa 1V x alm gain 76 us kac 310 ms 310 ms repeating 310 ms repeating max blot kg ht Bis max MA kg ht AN Fig 36 Timing diagram of the ambient light measurement sequence 8 11 Linear regulators 8 11 1 Introduction The PCF50633 contains 7 general purpose regulators
100. faces ONKEY 40 active LOW on key input with internal pull up resistor EXTON1 35 external activation wake up input EXTON2 36 external activation wake up input EXTON3 37 external activation wake up input NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 8 of 125 NXP Semiconductors PCF50633 PCF50633UM 6 PCF50633 User Manual Table 4 Pin description continued Symbol Pin Description RSTHC 21 active L OW reset output for host controller open drain output CLK32K 20 32 768 kHz digital clock output open drain output GPIO1 16 input mode control signal inputs with programmable impact on activity GPIO2 15 of regulators GPIO3 a output mode general purpose open drain outputs GPO 28 general purpose push pull output SHUTDOWN 39 shuts down the PCF50633 when a LOW to HIGH transition is detected IRQ 17 interrupt request to host controller this active LOW signal has an open drain output KEEPACT 38 Active state continuation input SCL 19 12C bus interface clock SDA 18 I2C bus interface data Linear and switching regulators AUTOIN1I 47 DC to DC auto up down converter input 1 AUTOIN2 46 DC to DC auto up down converter input 2 AUTOLXA1HI 48 inductor connection 1 to buck part of DC to DC auto up down converter AUTOLXA2I2 45 inductor connection 2 to buck part of DC to DC auto up down converter AUTOLXB1I2 44 inductor connection 1 to boost part of DC to DC auto up down conve
101. g and disabling of the LDOs and converters Features Power supply sequencing using 4 different activation and deactivation phases Supply module activation via the appropriate x on control bit Direct control via the GPIO inputs LDOs can be activated in Active and Standby states converters can only be activated in Active state Power failure detection for all supplies other than MEMLDO 8 8 3 Block diagram Fig 25 PSM block diagram activation sequence xpwrfail interrupt Supply x Software Control GPIOx enable x pwrok 8 8 4 Hardware interface 8 8 5 There is no hardware interface associated with the PSM Software interface Table 40 STBYCTL1 LDO Standby control register address 3Bh bit description Bit NON O Symbol Access Description ldo1 ena stb R W if set LDO1 is ON in Standby state reserved ldo2 ena stb R W if set LDO2 is ON in Standby state reserved ld03 ena stb R W if set LDO3 is ON in Standby state NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 44 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual Table 40 STBYCTL1 LDO Standby control register address 3Bh bit descriptionl Bit Symbol Access Description reserved ld04 ena stb R W if set LDO4 is ON in Standby state reserved 1 This register is reset in NoPower state Reset values are determined by the IC variant see Table
102. gart 3 6 V no USB or adapter present in Active state all supplies enabled 1 mA no load 1 If the system voltage drops below Vinsysmin an emergency shutdown is initiated and the system transitions to the Save state 2 If the system voltage drops below Vin syspres and no backup battery is present bubpres 0 see Table 14 the system will be reset and enter the NoPower state If a backup battery is connected Vaugar gt VinguBPREs the PCF50633 will continue in Save mode powered by the backup battery 3 If the system voltage is below Vinsyspres the system will continue to operate in the Save state as long as bubpres 1 Vausar gt Vin BUBPRES See Table 14 If bubpres is reset to O the system will be reset and will enter the NoPower state 4 Note that Vyjsa and Vperc are internal signals Pins VISA and REFC are provided to allow external decoupling capacitors to be connected Decoupling is necessary to ensure stable operation 8 1 5 PCF50633UM 6 Software interface Table 6 VERSION Version ID register address 00h bit description Bit Symbol Access Value Description 7 0 version R XXXXXXXX IC version number NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 12 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 PCF50633 User Manual Table 7 VARIANT Version ID register address 01h bit description Bit Symbol Access Value Description 7
103. ging resumes and the MBC mode changes from Battery Full to Play Only mode the resstat status bit which is O by default see Table 101 is set and the watchdog timers are reset The resstat bit will be reset when Battery Full mode is resumed When autores is set to O the MBC remains in Battery Full mode In this situation there is a risk of the battery becoming completely discharged if the system is drawing more current than the main charge device can supply and the ideal diode is active It is possible to initiate a restart of the charging process by setting the resume bit in register MBCC1 see Table 92 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 88 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 12 6 7 8 12 6 8 PCF50633 User Manual Halt mode The MBC enters Halt mode in response to a watchdog timer time out event or a charge supply fault condition as described below A charge supply fault condition is assumed when the charger supply level is lower then the battery voltage in which case the charge source is no longer able to charge the battery When Halt mode is entered a chghalt interrupt is generated and charging stops The state machine goes from the Halt mode to Play Only mode ifthe main charge supply USB or adaptor or both if USB and adapter are connected is removed e if the restart bit is set to begin a new charge cycle see Table 92 if the battery v
104. gnal 111 fixed 1 3 gpio3pol R W GPIO3 output signal polarity 0 no inversion 1 inversion 7 4 reserved 1 This register is reset in NoPower state Reset values are determined by the IC variant see Table 7 Table 33 GPOCFG GPO signal selection register address 17h bit descriptionl Bit Symbol Access Description 2 0 gposel R W GPO output signal selection 000 fixed 0 001 LED external NFET drive signal see Section 8 10 6 6 010 SYSx pin voltage gt Vin sysok 011 CLK32K 100 mobile mode adapter amp USB absent 101 USBx pin voltage gt Vin usbpres 110 ACTPH4 signal 111 fixed 1 3 gpopol R W GPO output signal polarity 0 no inversion 1 inversion 7 4 reserved 1 This register is reset in NoPower state Reset values are determined by the IC variant see Table 7 Functional description The GPIO inputs can be configured as power supply enable inputs see Section 8 8 When the GPIOx pins are configured as inputs the settings in the GPIOxCFG registers have no effect see Table 30 and Table 31 The GPIOx outputs are all high current 100 mA open drain outputs The output voltage can be set to any value 5 5 V The GPO output is driven by a push pull stage which is powered by the voltage on the LEDIN pin It can be used in conjunction with the LED converter to generate output voltages gt Vo LED max for details see Section 8 10 6 6 The GPIO and GPO pins can output different sig
105. gram NOPOWER No valid energy source available Vsys and Veupat absent SAVE Powered from SYS if voltage high enough otherwise from backup battery Vsys not OK STANDBY Powered from SYS Shutdown by ONKEY SHUTDOWN missing KEEPACT go_stby bit or error conditions ACTIVE Powered from SYS 8 1 6 2 Transitions between activity states The OOC controls the transitions between the activity states of the power management section of the PCF50633 PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 18 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 PCF50633 User Manual Active For USB supply when usbbatchk is set Standby transition to Standby only if VBAT gt Vih batok t Vsys Vih sysok 2 8 V V V J E keya kira mm D kas on transition to Save if VBAT lt Vth batok Vth sysmin 2 5V l Emergency shutdiown Immediate transition to Save Vsys No Interrupt Save Vih syspres 2 0V bubpres 0 bubpres 1 VBUBAT lt Vth bubpres VBUBAT gt Vih bubpres VBUBAT Vih bubpres 1 3 V NoPower Fig 6 State transitions and threshold voltages Transition from NoPower to Save The system will change state from NoPower to Save when the system voltage Vsys rises above Vih sysmin Transition from Save to NoPower In the absence of a charged backup battery
106. gt Vih batok and Vsys gt Vin sysok A transition from Standby to Save will occur if Var lt Vin batek OF Vsys lt Vih sysok Software interface Table 37 BVMCTL BVM control register address 18h bit description Bit Symbol Access Reset Description 0 bvmiow R 0 BATSNS pin voltage is higher than the programmed threshold 1 BATSNS pin voltage is lower than the programmed threshold 3 1 bvmlvl R W 21 Vih batok threshold level 000 n a 100 3 10 V 001 2 80 V 101 3 20 V 010 2 90 V 110 3 30 V 011 3 00 V 111 3 40 V 4 bvmdisdb R W 0 0 enable 62 ms debounce filter 1 disable 62 ms debounce filter 7 5 reserved 1 This register is reset in NoPower state 2 Reset values are determined by the IC variant see Table 7 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 39 of 125 NXP Semiconductors PC F50633 8 5 6 8 6 8 6 1 8 6 2 PCF50633UM 6 PCF50633 User Manual Functional description Figure 21 illustrates the behavior of the BVM V VBATSNS Vih batok i Vih batok hys batok status tdeb BVM tdeb BVM lowbat interrupt Fig 21 Functional behavior of the BVM module The BVM monitors the voltage on the BATSNS pin As long as this voltage remains remains above Vin patok the batok status bit in the OOCSTAT control register will be 1 see Table 14 If the BATSNS pin voltage drops below Vin patok a
107. he response to these events is edge sensitive The user presses the ONKEY ONKEY falling edge see Section 8 1 6 4 e One of the EXTONx inputs goes HIGH or LOW depending on the configuration of the extonx mode control bits see Table 12 and Section 8 1 6 5 If a fault condition prevents the transition to Active state triggered by any of these events the wake up event will be lost The following wake up events will continue to be asserted as long as the event remains active level sensitive An RTC alarm interrupt Ahigh enough voltage is detected on either the USBx or ADAPTSNS pin to indicate that a USB device or an adapter has been connected The RTC alarm and external power connection events remain valid as long as the corresponding interrupt bits are set in the INT module The interrupt bits are cleared by a read access to the INT register All wake up events can be disabled by clearing the corresponding wake control bits in the OOCWAKE register see Table 9 Note that interrupts are still generated In the Active state a subset dependant on the reset values of the IC variant of the power supplies is switched on After the supplies have become stabilized the RSTHC output is released allowing the host controller to start up Transition from Active to Standby Transitions from Active to Standby can be direct and immediate or can occur after an 8 second delay In the later case a time out timer is initiated and the system
108. her than an inductor and an output capacitor NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 48 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual High output voltage accuracy Programmable internal feedback divider with output voltage programmable in 25 mV steps Primary peak current limiting Programmable inrush current limiting 8 9 3 Block diagrams 2 2 uH LYN Y N e y I Ed m m x x x x E E E a O O O E E E E 5 5 x x Ed x AUTOOUT2 AUTOIN1 d AUTOIN2 AUTOOUT1 47uF 77 GPIOx d interrupt Control n DC to DC step up step down 1100 mA configuration see Section 8 9 6 3 Fig 26 AUTO block diagram PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 49 of 125 NXP Semiconductors PCF50633 PCF50633UM 6 PCF50633 User Manual L 4 7 uH DOWNILX TL output T 22ur JTI DOWN1IN down 1pwrfail interrupt GPIOx Control DOWN1FB Software Control DC to DC step down Fig 27 DOWN1 block diagram L 4 7 uH output DOWN2LX 1 J Bia 22yF T7 DOWN2IN down2pwrfail interrupt GPIOx Control DOWN2FB Software Control MEMLDO i DC to DC step down Fig 28 DOWN block diagram NXP B V 2008 All rights reserved User manual Rev 06 0
109. ile mode adapter amp USB absent 101 USBx pin voltage gt Vin usbpres 110 ACTPH1 signal 111 fixed 1 3 gpio1pol R W GPIO1 output signal polarity 0 no inversion 1 inversion 7 4 reserved 1 This register is reset in NoPower state Reset values are determined by the IC variant see Table 7 Table 31 GPIO2CFG GPIO2 signal selection register address 15h bit description Bit Symbol Access Description 2 0 gpio2sel R W GPIO2 output signal selection 000 fixed 0 001 reserved 010 SYSx pin voltage gt Vin sysok 011 battery charging in progress 100 mobile mode adapter amp USB absent 101 USBx pin voltage gt Vin usbpres 110 ACTPH2 signal 111 fixed 1 3 gpio2pol R W GPIO2 output signal polarity 0 no inversion 1 inversion 7 4 reserved 1 This register is reset in NoPower state Reset values are determined by the IC variant see Table 7 PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 34 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 3 6 PCF50633 User Manual Table 32 GPIO3CFG GPIO3 signal selection register address 16h bit description Bit Symbol Access Description 2 0 gpio3sel R W GPIO3 output signal selection 000 fixed 0 001 reserved 010 SYSx pin voltage gt Vin sysok 011 battery charging in progress 100 mobile mode adapter amp USB absent 101 USBx pin voltage gt Vih usbpres 110 ACTPH3 si
110. ime that interrupt is generated NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 31 of 125 NXP Semiconductors PC F50633 8 3 8 3 1 PCF50633 User Manual The host controller should read all interrupt registers in a single I C bus read action This ensures that all active interrupts are cleared The IRQ signal will go HIGH as soon at the read cycle to the last register containing an active interrupt has begun see Figure 16 All interrupts can be masked the IRQ signal does not go LOW when a masked interrupt is generated For each interrupt register there is a corresponding mask register Masking is implemented by setting the appropriate mask bits in the relevant mask registers When an interrupt is generated the appropriate interrupt status bit is set whether the interrupt is masked or not This allows the host controller to accurately determine interrupt status at any time by polling the interrupt registers a read request read read read read read FC amp address INT INT2 INT3 INT4 INT5 IRQ goes inactive HIGH as soon as the read cycle of the last NTx register containing an active interrupt begins Read access may or may not use incremental addressing Fig 16 Interrupt timing General Purpose Input Output GPIO GPO Introduction The PCF50633 contains three general purpose open drain input output pins GPIO1 GPIO2 and GPIO3 and one high curr
111. interface enabling extended control over all modules State machine ensuring optimal activity in each device state Programmable start up and shutdown sequencer Real Time Clock including 32768 Hz oscillator and alarms Interrupt controller Wake up possibilities at 6 pins allowing wake up by push button slide switch and adapter USB insertion Three General Purpose I Os GPIO and one high current General Purpose Output GPO 8 byte general purpose memory Ambient light sensor Thermal protection 2 2 Supplies Auto step up step down converter 1 1 A 1 7 MHz internal switches for a hard disk Step down converter 500 mA 1 7 MHz internal switches for a CPU Step down converter 500 mA 1 7 MHz internal switches for memory plus parallel Low Dropout Regulator LDO for standby mode Backlight boost converter incorporating intensity and on off ramp control Seven linear regulators 4 x 50 mA 2 x 150 mA 1 x 200 mA with current limiting Dynamic voltage management on both step down converters Programmable inrush current on all switching regulators On off and output voltage control by software 12C and via control pins GPIOs Power failure detection on most outputs Outputs pulled down to ground when supplies are off except LED converter Linear regulators can be used as switches NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 3 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 2 3 Batt
112. istor connected to the output Rpson drain source on state Vi 2 7 V i 2 resistance Vi 5V Typ Max 50 5 5 5 5 3 6 100 Vovprog 2 5 0 03 1 2 0 9 x Votprog 60 250 2 3 Unit mA mV 96 9o mA mV V dB mV kQ Q Q 1 AVio is defined as the voltage difference between input and output when the output is 1 below a reference voltage Vrer and is the minimum voltage drop required to ensure reliable operation Vpep is the voltage measured at the output with V set to Vo prog 1 V 2 Input to output resistance in Switch mode Table 74 LDO4 and LDO5 characteristics Vss REFGND GND O V Tamp 40 to 85 C unless otherwise specified Symbol lo Vi Vojprog Vo step Vo AVO AIL AVo AV Vpwrok Parameter Conditions output current input voltage LDO operated as regulator LDO operated as low ohmic switch programmable output voltage programmed via Idox out bits output voltage step size output voltage load regulation line regulation power OK level Min 2 7 1 8 0 9 Typ Max Unit 150 mA 55 V 55 V 3 6 V 100 mV Vo prog 42 5 96 0 01 9o mA 1 2 mV V 0 9 x V Vo prog NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 67 of 125 NXP Semiconductors PCF50633 Table 74 PCF50633 User Manual LDO4 and LDO5 characteristics continued Vss REFGND GND 0 V Tamp 40 to
113. k control bit see Table 45 and Table 46 is masked for a period of 100 ms This is to ensure a power failure is not erroneously detected at start up A power failure condition is signaled to the interrupt module which then generates an xpwrfail interrupt The supply module will not be switched off The Host controller should take appropriate action AUTO DOWN1 and DOWN converters Introduction The PCF50633 contains two inductive step down converters DOWN1 and DOWN2 capable of delivering output currents up to 500 mA and one inductive auto step up step down converter AUTO capable of delivering an output current of 1 1 A DOWNe incorporates a parallel linear regulator MEML DO for use in Standby state All the converters can be switched on or off under software control either directly via the I2C bus or by configuring the GPIOx pins as power supply enable inputs Note that AUTO DOWN and DOWN can only be enabled in the Active state Features Digital control with automatic changeover between PWM and PFM modes High switching frequency 1 7 MHz allowing the use of small value inductors and output capacitors No adjustments of dynamic response required the digital control technology ensures stable operation under all conditions Suitable for low ESR output capacitors thanks to current mode control Elcos or tantalum capacitors cannot be used Power stage with synchronous rectification No external components required ot
114. k diagram 8 7 4 Hardware interface Table 39 OSC32 characteristics Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit gm oscillator transconductance 8 14 20 uS tSTARTUP total start up time until CLK32 System is forced to go to Active state 400 500 ms signal active when charged main battery is connected while ONKEY is LOW Ci Input capacitance between 5 z pF OSCI and OSCO pins 8 7 5 Software interface There are no registers associated with the OSC32 8 7 6 Functional description The 32 kHz oscillator module can be used without a crystal by connecting a 32 768 kHz signal to the OSC32I pin The OSC320 pin should be left floating in this configuration The PCF50633 can also be used without a 32 kHz crystal or external 32 kHz clock input In this case a 32 kHz clock signal will be generated internally However the clock will be less accurate in this situation and there will be a increase in power consumption particularly in Save and Standby states Both the OSC321 and OSC320 pins must be grounded when using the PCF50633 without a 32 kHz crystal or external clock signal PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 43 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 8 8 8 1 8 8 2 PCF50633 User Manual Power Supply Module PSM Introduction The power supply module controls the enablin
115. l I C bus protocol Addressing The first byte of any data transmission on the I C bus contains the address of the target device The address of the PCF50633 is 1110011R W The least significant bit is the read write indicator The PCF50633 acts as a slave receiver or slave transmitter Therefore the SCL clock signal is a unidirectional input signal The data line SDA is bidirectional The PCF50633 slave address is illustrated in Figure 57 111 1 0 0 1 1 IRAN lt group 1 ma group 2 gt Fig 57 Slave address Read write cycles The I2C bus configurations for the PCF50633 read and write cycles are illustrated in Figure 58 to Figure 60 The word address is an 8 bit value indicating which register is being accessed NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 111 of 125 NXP Semiconductors PCF50633 PCF50633UM 6 PCF50633 User Manual acknowledgement acknowledgement acknowledgement from slave from slave from slave T T T T T T i T T T T T T T T T T T T T T i S SLAVE ADDRESS 0 A WORD ADDRESS JA DATA A P 1 1 1 1 1 i 1 1 1 1 1 1 1 1 1 1 1 1 RW n bytes auto increment memory word address mbd822 Fig 58 Master transmits to slave receiver write mode acknowledgement acknowledgement acknowledgement acknowledgement from slave from slave from slave from master s SLAV
116. l components see Table 2 4 7 uH Peer N N g g m m Xx x x lt x J J J zi o o o O E E E E 2 2 2 2 lt lt lt lt AUTOOUT2 AUTOIN1 DR AUTOIN2 l AUTOOUT1 22 uF 77 GPIOx autopwrfail interrupt Pc Software Control DC to DC step up step down Fig 29 Application diagram showing 500 mA configuration The pin configuration depends on the selected operating mode and the required current capability as illustrated in Table 65 Table 65 AUTO pin configuration Mode AUTO MOD bit AUTOIN1 2 AUTOLXA1 AUTOLXA2 AUTOLXB1 AUTOLXB2 AUTOOUT1 2 Auto 1 1A 0 input LXALI LXALI LXBLU LXBU output Auto 500mA 0 input LXALI floating floating LXBI output Down only 1 1A 1 input LXALI LXALI floating floating output 1 LXA and LXB are the inductor nodes on the PCB PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 57 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 PCF50633 User Manual The 500 mA configuration is depicted in Figure 29 see Figure 26 for an illustration of the 1100 mA configuration Pull down switches on the outputs guarantees an output voltage of 0 V when the converter is switched off 8 10 LED boost converter amp Ambient Light Monitor ALM 8 10 1 Introduction The LED converter is a dedicated boost converter capable of driving a chain of LEDs 8 10 2 Features LED curren
117. l diode will start conducting This situation is illustrated in Figure 41 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 85 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual External Adapt SYS PFET Adapter HI USB to SYS path System USB foy ea FEE a KN Wn apu L T i 1 je i USB SYS FET uu i 1 E i Ideal Adapt er Iba AN diode charger eo D PA o USB charger E BAT t0 SYS path E Main J battery USB BAT FET D Fig 41 Current flow during USB charging system takes more than USB budget Note that if this situation persists the battery will discharge over time The battery will continue to deliver power to the system even as it is discharging If system current requirements fall or if the USB current budget is increased and Isys becomes less than li iw usg Vsys Will steadily rise A usblimoff interrupt will be generated signalling that current limiting has been deactivated in the USB to SYS path Once Vsys gt Vear the ideal diode will block current flow from the battery Battery fully charged When the battery is fully charged and the charger is in Battery Full mode the charge path is disabled the USB BAT FET is off As long as the USB can deliver the current needed by the system the USB SYS FET will be conducting see Figure 42 External Adapt SYS PFET Adapter gt 1 Sys
118. l gradually decline as the battery charge level increases When the charge current drops below the cutoff point as specified via the cutoffcur bits in register MBCCE6 see Table 97 the ilim bit is reset to O in register MBCS3 see Table 102 When ilim 0 and neither the thermal limiting loop nor the USB current limiting loop is active a batfull interrupt is generated to indicate that the battery is fully charged If autostop is set see Table 92 charging stops and the MBC enters Battery Full mode Otherwise charging continues and the control software will be responsible for deciding what action to take As a safety precaution a watchdog timer is started from zero when the MBC enters Precharge phase If the watchdog timer expires after twpr pre minutes before the battery reaches Vpatcong precharging stops and the MBC enters Halt mode twpr pre is specified via the prewatime bit in the MBCC7 register see Table 92 The prewatime control bit is only updated when the charger is in Play Only mode Note that the watchdog timer only counts down while the charger is in USB Adapter Precharge phase It is halted when the charger is in USB Adapter Precharge Wait phase When battempena 0 it is assumed that the application does not include an NTC for measuring battery temperature In this situation all restrictions in the state diagram Figure 39 relating to battery temperature are ignored Charging stops if chgena is reset see Table 92 o
119. l setting 00 2 7 V 012 2 85 V 102 3 0 V 11 2 3 15 V 5 2 vmax R W programmable battery float voltage Vbat fioat prog 0000 4 00 V 0001 4 02 V 0010 4 04 V 0011 4 06 V 1010 4 20 V 1011 4 22 V 1111 4 30 V 6 reserved 7 vresdebtime R W debounce time for Vin REs 0 32 seconds 1 64 seconds 1 This register is reset in NoPower state Reset values are determined by the IC variant see Table 7 Table 94 MBCC3 MBC charger control register 3 address 45h bit description Bit Symbol Access Description 7 0 prechgcur R W pre charge current level 0000 0000 0 255 x lcn ret 0000 0001 1 255 x lcn ret 1111 1110 254 255 x leen 1111 1111 255 255 x leniret 1 This register is reset in NoPower state Reset values are determined by the IC variant see Table 7 Table 95 MBCC4 MBC charger control register 4 address 46h bit description Bit Symbol Access Description 7T 0 fstchgcur1 R W fast charge current level in adapter Fast Charge phase settings same as for prechgcur in Table 94 1 This register is reset in NoPower state Reset values are determined by the IC variant see Table 7 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 78 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 PCF50633 User Manual Table 96 MBCC5 MBC charger control register 5 address 47h bit description Bit Symbol Access Description 7T 0 fstchgcur
120. lue is determined by the IC variant see Table 7 Table 54 DOWN10OUT DOWNI o p voltage select register address 1Eh bit description Bit Symbol Access Description 7 0 downl out R W Vo prog 0 625 down out x 0 025 V e g 00000000 0 625 V min 00010111 1 200 V 00101111 1 800 V 01011111 3 000 V max 11111110 3 000 V 11111111 3 000 V 1 This register is reset at each transition to Standby state Reset value is determined by the IC variant see Table 7 Table 55 DOWN1ENA DOWN1 output enable register address 1Fh bit descriptionl Bit Symbol Access Reset Description 0 downi on R W 2 if set converter is ON downi pic R W 2 if set converter is ON when GPIO1 1 downt p2c R W 2 if set converter is ON when GPIO2 1 down1_p3c R W 2 if set converter is ON when GPIO3 1 5 4 downi ena act R W 21 selects activation phase 00 ACTPH1 01 ACTPH2 10 ACTPH3 11 ACTPH4 7 6 reserved 1 This register is reset at each transition to Standby state 2 Reset values are determined by the IC variant see Table 7 Table 56 DOWNICTL DOWN1 control register address 20h bit description Bit Symbol Access Reset Description 0 downipwmonly R W 0 0 automatic PFM PWM selection 1 converter operates in PWM mode 4 1 downi dvmstep R W 0000 DVM step time defines number of 32768 Hz clock cycles between each step e g 0000 no DVM 0001 30 us 1111 458 us 7 5 reserved 1 This
121. m interrupt is generated when the voltage on ADAPTSNS drops below Vir adaptpres for longer than 62 ms The presence of the external adapter must be signalled to the PCF50633 at the ADAPTSNS input as the SYSx pins cannot be used for adapter detection Current definition pin CHGCUR An external resistor Rena connected between the CHGCUR pin and ground defines the charge current and current limit levels The resistance value must be 12500 Q in order to select the maximum charge current of 1 A and the USB current limit levels to 100 mA and 500 mA If a different resistance value is used the maximum charge current and USB current limit levels will be scaled accordingly The value of Rcug defines a reference current Ich ref referred to in later sections NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 82 of 125 NXP Semiconductors PCF50633 8 12 6 5 Functional description of charger controller PCF50633 User Manual The charger control flow is fully autonomous requiring no software intervention to fully charge a battery The following table shows the component states in different operating modes A charger state diagram is shown in Figure 39 Circuit configurations operating modes and charging phases are discussed in the following sections Table 103 Charger modes and component states MBC mode Adapter USB present present Play Only No No USB Charge amp No Yes Play No Yes USB
122. n HIGH or LOW can be determined by reading bit O of the OOCSTAT control register see Table 14 ONKEY ONKEY debounced tdebounce L Z x i onkeyf interrupt jam tdebounce onkeyr interrupt onkey1s interrupt system state Standby Active The debounced signal retains its original value until the new value has been stable for at least the selected debounce time A spike gt 30 us in the original signal will reset the debounce timer The filter suppresses all signal activity shorter than the debounce time A Standby to Active transition is initiated by pressing the ONKEY Fig 7 ONKEY behavior when push button pressed in Standby state SNKEY HITA T i a lieta ONKEY NU ONKEY debounced ldebounce L L _ onkeyf interrupt Te tdebounce onkeyr interrupt Lu 1s A onkey1s interrupt ta 8 second timeout Active Standby System state The debounced signal retains its original value until the new value has been stable for at least the selected debounce time A spike gt 30 us in the original signal will reset the debounce timer The filter suppresses all signal activity shorter than the debounce time An Active to Standby transition is initiated when the ONKEY push button is held down for 1 second Fig 8 ONKEY behavior when push button pressed in Active state
123. n USB Charge and Play mode on page 85 6 adcrdy R amp C ADC conversion completed see Section 8 14 6 1 7 onkeyis R amp C ONKEY LOW for at least 1 second see Section 8 1 6 4 1 This register is reset in NoPower state all bits set to 0 2 This column describes the events that cause the corresponding interrupt bits to be set to logic 1 Table 20 INT4 Interrupt register 4 address 05h bit description Bit Symbol Access Descriptionl O lowsys R amp C SYS voltage fallen below Vir sysok see Section 8 4 6 1 lowbat R amp C BAT voltage fallen below Vinpatok see Section 8 5 6 2 hightmp R amp C die temperature threshold Tin aie exceeded see Section 8 6 6 3 autopwrfail R amp C AUTO output voltage below 90 of target see Section 8 8 6 3 4 dwnipwrfail R amp C DOWN output voltage below 90 of target see Section 8 8 6 3 5 dwn2pwrfail R amp C DOWN output voltage below 90 of target see Section 8 8 6 3 6 ledpwrfail R amp C LED output current below 90 of target see Section 8 8 6 3 7 ledovp R amp C overvoltage detected at output of LED converter see Section 8 10 6 3 1 This register is reset in NoPower state all bits set to 0 2 This column describes the events that cause the corresponding interrupt bits to be set to logic 1 Table 21 INT5 Interrupt register 5 address 06h bit description Bit Symbol Access Description O Idotipwrfail R amp C LDO 1 output voltage below 90 of target
124. n 0 return values are not defined Table 124 RTCHRA RTC hour alarm value register address 62h bit description Bit Symbol Access Reset Description 5 0 houra R W 111111 hour alarm value 00 to 23 coded in BCD format 7 6 reserved 21 1 This register is reset in NoPower state 2 Reserved bits should be written 0 return values are not defined Table 125 RTCWDA RTC weekday alarm value e register address 63h bit description Bit Symbol Access Reset Description 2 0 wkdaya R W 411 day of week alarm value 0 to 6 see Table 117 7 3 reserved 2 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 105 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 15 7 PCF50633 User Manual 1 This register is reset in NoPower state 2 Reserved bits should be written 0 return values are not defined Table 126 RTCDTA RTC weekday alarm BCD value register address 64h bit description Bit Symbol Access Reset Description 5 0 daya R W 111111 day alarm value 00 to 31 coded in BCD format 7 6 reserved 21 1 This register is reset in NoPower state 2 Reserved bits should be written 0 return values are not defined Table 127 RTCMTA RTC month alarm BCD value register address 65h bit description Bit Symbol Access Reset Description 4 0 montha R W 11111 month alarm value 01 to 12 coded in BCD format see Table 121
125. n phase 00 ACTPH1 01 ACTPH2 10 ACTPH3 11 ACTPH4 7 6 reserved 1 This register is reset at each transition to Standby state Reset values are determined by the IC variant see Table 7 Table 78 LDO2OUT LDO2 output voltage select register address 2Fh bit descriptionl Bit Symbol Access Description 4 0 ldo2 out R W Votprog 0 9 do2 outx 0 1V max 3 6 V eg 00000 0 9 V 00001 1 0 V 11000 3 3 V 11011 3 6 V 11111 3 6 V 5 ldo2 swmod R W 0 linear regulator mode 1 switch mode 7 6 reserved 1 This register is reset at each transition to Standby state Reset values are determined by the IC variant see Table 7 PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 69 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual Table 79 LDO2ENA LDO2 output enable register address 30h bit descriptionl Bit Symbol Access Description 0 Ido2_on R W if set LDO is ON Ido2_pic R W if set LDO is ON when GPIO1 1 2 ldo2 p2c RAN if set LDO is ON when GPIO2 1 3 ldo2 p3c R W if set LDO is ON when GPIO3 1 5 4 l do2 ena act R W selects activation phase 00 ACTPH1 01 ACTPH2 10 ACTPH3 11 ACTPH4 7 6 reserved 1 This register is reset at each transition to Standby state Reset values are determined by the IC variant see Table 7 Table 80 LDO3OUT LDO3 output voltage select register address 31h bit description Bit Symbol Ac
126. nals concurrently as detailed in the GPIOxCFG and GPOCFG control registers see Table 30 to Table 33 The gpioxsel and gposelbits are used to select the output signal The gpioxpol and gpopol bits offer optional inversion GPIOx GPO outputs signals are available in Active Standby and Save modes NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 35 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual When any of these pins is configured as an output input functionality is disabled Any GPIOx pin configured as a power supply enable input will not function as such see Section 8 8 8 4 System Voltage Monitor SVM 8 4 1 Introduction The PCF50633 contains two voltage monitors with programmable threshold levels used to affect state transitions This section describes the System Voltage Monitor SVM which monitors the voltage on pins SYS1 and SYS2 The next section describes the Battery Voltage Monitor BVM 8 4 2 Features The SVM is automatically activated by the On Off Control OOC logic see Section 8 1 6 1 e Programmable threshold Vth sysok e A lowsys interrupt is generated when the voltage on SYSx drops below the specified threshold Built in hysteresis and programmable debounce filter to minimize system oscillations e The OOC initiates state transitions in response to a owsys interrupt see Section 8 1 6 1 8 4 3 Block diagram lowsys Interrupt SYSx
127. ng edge detected on EXTON pin see Section 8 1 6 5 rising edge detected on EXTONS pin see Section 8 1 6 5 falling edge detected on EXTONS pin see Section 8 1 6 5 2 Table 18 Bit Symbol 0 onkeyr 1 onkeyf 2 extonfr 3 extontf 4 exton2r 5 exton2f 6 exton3r 7 exton3f 1 2 PCF50633UM 6 This register is reset in NoPower state all bits set to O This column describes the events that cause the corresponding interrupt bits to be set to logic 1 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 28 of 125 NXP Semiconductors PCF50633 PCF50633UM 6 PCF50633 User Manual Table 19 INT3 Interrupt register 3 address 04h bit descriptionl Bit Symbol Access Description O batfull R amp C battery is fully charged charger has entered Battery Full mode see Section Battery Full mode on page 88 1 chghalt R8C charger has entered HALT mode see Section Halt mode on page 89 2 thlimn R amp C charger has activated thermal loop current limiting in the USB to SYS path see Section 8 12 6 10 3 thlimoff R amp C charger has deactivated thermal loop current limiting in the USB to SYS path see Section 8 12 6 10 4 usblimon R amp C charger has activated USB current limiting in the USB to SYS path see Section USB Charge and Play mode on page 85 5 usblimoff R amp C charger has deactivated USB current limiting in the USB to SYS path see Sectio
128. ng edge is not debounced The debounce filter can be disabled by setting the svmdisdb control bit in the SVMCTL register see Table 35 Battery Voltage Monitor BVM Introduction The BVM monitors the voltage on the BATSNS pin Features The BVM is automatically activated by OOC logic e Programmable threshold Vin batok A lowbat interrupt is generated when the voltage on BATSNS drops below the specified threshold Built in hysteresis and programmable debounce filter to minimize system oscillations A lowbat interrupt can affect state transitions see Section 8 1 6 2 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 38 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 5 3 8 5 4 8 5 5 PCF50633 User Manual Block diagram lowbat Interrupt BATSNS Pc Software Control batok Fig 20 BVM block diagram Hardware interface Table 36 BVM characteristics Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Vih batok battery OK threshold voltage range 2 8 3 4 V accuracy 2 Vih batok 2 96 Vth batok hys hysteresis of battery OK threshold 0 04 x V voltage Vih batok tdeb BVM debounce time for low battery 5 62 5 ms condition rising edge only 1 If a USB supply is connected and usbbatchk 1 a transition from Save to Standby will only occur if Vpar
129. nt is limited bbcr 1 160 220 280 mV IDD tot total supply current excluding charge ON mode charging 30 50 uA current ON mode stopped 15 25 uA OFF mode 1 uA PCF50633UM_6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 94 of 125 NXP Semiconductors PCF50633 PCF50633 User Manual 8 13 5 Software interface 8 13 6 PCF50633UM 6 Table 105 BBCCTL Backup battery charger control register address 4Eh bit description Bit Symbol Reset 0 bbce ol2 Access R W Description enable backup battery charger 0 charger OFF 1 charger ON this bit is automatically cleared in Standby state 1 bbcr R W 0 bypass output resistor 0 output resistor active 1 resistor bypassed 3 2 bbcc R W 00 select backup battery charge current lcnguBar 00 50 uA 01 100 uA 10 200 uA 11 400 uA select limiting voltage for backup battery charger Viim BUBAT 0 2 5 V 1 3 0V 4 bbcv R W 0 7 5 reserved 1 This register is reset in NoPower state 2 Reset in Standby state Functional description The backup battery charger is enabled in the Active state by writing 1 to control bit bbce see Table 105 In Standby state bbce is cleared automatically The backup battery is charged from the system voltage Vsys Charging stops when the backup battery reaches the programmed maximum voltage VsausAr gt Viim BUBAT Or when the system voltage drops below the backup
130. o oO 08 to PT PreWDT expires or GE qe So mE adaptpres 1 amp adaptok 0 An 22 adaptpres 0 BS Ve 55 52 ro 8 ICHG cutoffcur amp Battery VBAT Vmax amp Adapter temp Adapter De due Fast Charge too high Fast Charge yu rdc Phase Battery Wait Phase temp OK ICHG lt cutoffcur amp VBAT Vmax amp tim chg 0 amp autostop 1 WDT e pires or adaptpres 1 amp adaptok 0 Battery Full Mode Halt Mode Vear lt Vth RES amp autores 1 or restart 1 VBAT lt Vih RES amp autores 1 or resume 1 enuen 19S 90S49d 90S490d SJOJONPUODIWISS dXN NXP Semiconductors PC F50633 PCF50633UM 6 PCF50633 User Manual 8 12 6 6 MBC operating modes Play Only mode The MBC operating mode charge phase can be determined by reading the mbcmod bits in the MBCS2 status register see Table 101 In Play Only or Idle mode most of the circuits of the MBC are disabled when no external power source USB or adapter is available Programming the chgena control bit to 0 while an external power source is available will result in a transition to the Play Only mode In this case the USB BAT and SYS BAT FETs will be OFF USB Charge and Play mode In this mode the CPU specifies the USB current budget via the usbdevstat bits in register MBCC7 see Table 98 How the charger behaves in this mode is determined by the battery state and required system current
131. o pwrok ldo1 pwrok chgena usbpres usblim play bbce alm data accswen adcratioen Ref Table 87 Table 88 Table 89 Table 40 Table 41 Table 42 Table 43 Table 44 Table 90 Table 45 Table 46 Table 92 Table 93 Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 Table 100 Table 101 Table 102 Table 105 Table 71 Table 72 Table 109 Table 108 enuen 4esf 90SA9Dd 90S40d S10 INPU0I1W3S dXN jenuew sn 8002 421e SO 90 9H SZL 40 OLL 9 Wnee90940d pe uesei syfu Iv B002 5 8 dXN Table 138 PCF50633 register overview continued HEX Addr 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A eB ec eD eE 6F 83 84 Register Name ADCC1 ADCS1 ADCS2 ADCS3 RESERVED RTCSC RTCMN RTCHR RTCWD RTCDT RTCMT RTCYR RTCSCA RTCMNA RTCHRA RTCWDA RTCDTA RTCMTA RTCYRA MEMBYTEO MEMBYTE1 MEMBYTE2 MEMBYTE3 MEMBYTE4 MEMBYTE5 MEMBYTE6 MEMBYTE7 RESERVED DCDCPFM Mode R W DDD R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Reset Bit 7 nl NOP adcinmux NOP adcdatih NOP adcdat2h NOP adcrdy NOP reserved NOP reserved NOP reserved NOP reserved NOP reserved NOP reserved NOP reserved NOP NOP reserved NOP reserved NOP reserved NOP reserved NOP reserved NOP reserved NOP NOP membyte0 NOP membyte1 NOP membyte2 NOP membyte
132. ode is selected by setting the adcinmux control bits to 0001 when using the BATSNS input or to 0011 for the ADCIN2 input see Table 107 The voltage on BATSNS is determined by the following formula ADCDAT BATSNS VsarsNS 1523 2X2 225V 7 Low voltage ADC inputs and ratiometric measurement The ADCIN1 and BATTEMP inputs can be used to measure voltages within the standard ADC module input voltage range of O V to 2 0 V The adcinmux control bits in register ADCC are set to 0111 to select ADCIN1 and to 0110 to select BATTEMP The battery temperature is typically measured using an external NTC bridge placed close to the battery see Section 8 12 6 11 The ADC and the MBC Main Battery Charger modules share the NTC circuit which contains a known fixed resistance in series with the NTC thermistor The NTC circuit is configured as a half bridge connected between the NTCSW pin and the PCB ground The internal node of the half bridge is connected to the BATTEMP input of the ADC module The BATTEMP and ADCIN1 inputs support ratiometric measurement the ratiometric mode is determined by the settings of the adcratioen control bits see Table 108 In this mode the ADC results reflect the ratio of the external fixed resistance to the NTC resistor value R ADCDAT garremp xR NTC 1023 ADCDAT g rrEMP EP 8 If adcratioen 11 the ADC will perform sequential conversions on both the BATTEMP and ADCIN1 inputs The result of
133. oltage drops below the resume level Vins for a period longer than the debounce time defined by control bit vresdebtime in register MBCC2 see Table 93 and autores is set to 1 Charging phases There are four charge phases associated with USB Charge and Play mode and Adapter Charge and Play mode The charge phases apply to Li ion batteries Precharge phase conditioning phase Precharge Wait phase e Fast Charge phase Fast Charge Wait phase Once charging is complete the MBC will enter either Battery Full or Halt mode Charging begins when a valid adapter or USB supply is detected see Section 8 12 6 3 or Section 8 12 6 2 The charger will then enter the USB or Adapter Precharge phase as appropriate Precharge phases When a suitable adapter or USB supply is detected the battery is charged with a constant precharge current CC mode The constant current is selected via the prechgcur bits in the MBCC3 register see Table 94 Ion lengre X prechgcur 255 4 len retj IS defined in section Section 8 12 6 4 For a Li ion battery the precharge current is typically 0 1C C charge rate the charge current which will fully charge the battery in one hour Precharging with a constant current continues until the battery voltage reaches the conditioned voltage level Vbpatcond For a Li lon battery Vpatcond is typically 2 7 V This level can be set via the vbatcond control bits in the MBCC2 control register see Tabl
134. onditions Min Typ Max Unit Tih die die threshold temperature 125 C Tih die hys hysteresis of die threshold 15 20 25 C temperature tdeb debounce time 62 ms 1 If the die temperature exceeds Tih die Thys die a hightmp interrupt is generated and the tmpok status bit is set to 0 see Table 14 Table 20 and Figure 23 Software interface The interrupt hightmp associated with the THS can be found in register NT4 see Table 20 The status bit mpok associated with the THS is located in the OOCSTAT register see Table 14 Functional description Figure 23 illustrates the behavior of the THS and the hightmp interrupt NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 41 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual o Tj C Tih die Pa tdeb hightmp mg interrupt tmpok status T lil A Fig 23 THS and hightmp interrupt behavior A hightmp interrupt is generated when the temperature threshold has been exceeded for more than 62 ms debounce time When a hightmp interrupt is generated the host controller should initiate a transition to Save If this doesn t happen within 1 seconds of a hightmp interrupt being generated the OOC will force the PCF50633 to the Save state to prevent the circuit getting damaged Note that if the PCF50633 goes to Save state in response to a hightmp interrupt the appropriate interrupt register mu
135. oot flag via I2C bus programming Types of control register The PCF50633 contains several types of control register which are automatically reset under different conditions Registers which are reset at initial start up only and which retain their data in all states except NoPower These are largely on off control interrupt charger and RTC registers Registers which are reset at each transition to Standby state These are mostly supply control registers Registers with fixed contents such as device identifiers These are never reset Interrupt Controller INT Introduction The interrupt controller captures and masks interrupts and generates a signal IRQ goes LOW to indicate to the host that an interrupt has been generated Interrupts indicate to the host that the PCF50633 has changed status and that some action is required The host determines interrupt priority Features All interrupts are Read and Clear R amp C All interrupts to IRQ can be masked Block diagram INT function function function 1 2 X Interrupt Module Software Control Fig 15 INT block diagram NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 27 of 125 NXP Semiconductors PCF50633 PCF50633 User Manual 8 2 4 Hardware interface Table 16 Interrupt controller characteristics Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified Symbol
136. path is active if set USB current limiting loop in USB to BAT path is active if set temperature limiting loop in USB to SYS path is active if set temperature limiting loop in USB to BAT or SYS BAT path is active if set battery charge current cutoffcur level battery charge current cutoffcur level battery voltage vmax level battery voltage equals vmax level battery voltage lt Vpatcond battery voltage gt Vpatcond battery voltage lt Vih RES battery voltage gt Vin aes mO O Ha O o 8 12 6 Functional description 8 12 6 1 Charger circuit arrangement The charging system is characterized by USB SYS switch A current limited path from the USB input to the system supply output USB charger a charge path from the USB input to the battery PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 81 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 12 6 2 8 12 6 3 8 12 6 4 PCF50633 User Manual Adapter charger a charge path from the system supply node to the battery intended to be supplied from an external adapter switched to the SYSx pin by a discrete P type FET Ideal diode a path for supplying system operation from the battery and for when the system requires more power than the USB path can deliver Refer to the MBC block diagram Figure 38 for details USB input A dedicated USB input is available to support
137. pply REFC 13 VISA 11 VISC 64 Battery charger USB1l 60 USB2I 61 BATIL1 62 BAT2U 63 BATSNS 1 sysill 58 Sysalt 59 ADAPTSNS 66 ADAPTCTRL 67 BATTEMP 68 CHGCUR 65 BUBAT 49 ADC ADCIN1 9 ADCIN2 10 NTCSW ACCSW Ground REFGND 12 Description LDOA linear regulator output shared input for LDO5 and LDO6 linear regulators LDOS5 linear regulator output LDO6 linear regulator output high current linear regulator input high current linear regulator output 32 768 kHz oscillator input 32 768 kHz oscillator output reference voltage bypass capacitor connection internal analog supply voltage decoupling node internal analog supply voltage decoupling node USB power input 1 USB power input 2 battery terminal 1 battery terminal 2 battery voltage sense input system and adapter connection terminal 1 system and adapter connection terminal 2 adapter sense input adapter switch gate drive output battery temperature sense input charger current reference resistor connection backup battery connection ADC channel 1 input ADC channel 2 input battery temperature resistor bridge connection accessory resistor bridge connection reference ground VSS backplane power ground connection 1 The following pin pairs must be connected on the PCB AUTOIN1 to AUTOIN2 AUTOOUT1 to AUTOOUT2 USB1 to USB2 BAT1 to BAT2 SYS1 to SYS2 These pins are all power pins They must be connected via a low ohmic connection NXP
138. pru PFM switching frequency 1 MHz 1 A5V 100 mA USB supply source can be generated by configuring the LED supply module as a boost converter see Section 8 10 6 7 PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 59 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 8 10 5 Software interface Table 67 LEDOUT LED output voltage select register address 28h bit description Bit Symbol Access Reset Description 5 0 led out R W 1111112 output current setting Zp en VLEpFB SENSE examples from the 6 bit semi logarithmic range Code Viepra mV 000000 reserved 000001 2 000011 10 001000 27 001010 37 001110 56 010010 81 010110 113 011010 149 011110 196 100010 250 100110 318 101010 401 101110 501 110010 626 110110 778 111010 961 111111 1250 7 6 reserved 1 This register is reset at each transition to Standby state 2 led out should never be set to 000000 as this would result in a deadlock making it impossible to program another value If led out should be inadvertently set to 000000 the LEDOUT register can be reset by disabling and enabling the LED converter via control bit led on in the LEDENA register see Table 68 led out 20 63 20 3 Vjgpre the voltage across Rsense e I e 1 x 1 25 V see Section 8 10 6 1 Table 68 LEDENA LED output enable register address 29h bit description
139. quency current capacitor 2 current voltage voltage step size Programmable power supplies DOWN1 500mA 0 625V 300V 25mV 1 7 MHz 22 uF 4 7 uH DOWN 500mA 0 625V 300V 25mV 1 7 MHz 22 uF 4 7 uH AUTO 500mAB 1 80V 380V 25mV 1 7 MHz 22 uF 4 7 uH 1100mA 1 80V 380V 25mV 1 7 MHz 47 uF 2 2 uH LED 25mA 50V 180V 1mA 1MHz 10 uF 2 2 uH LDO1 50mA 090V 360V 100mV 25uA 2 60dB 470nF LDO3 of load LDO4 150mA 090V 360V 100mV 70uA 2 60dB 470nF LDO5 150mA 0 90V 360V 100 mV of load 60dB 470nF LDO6 50mA 0 90V 360V 100mV 25uA 2 60dB 470nF of load HCLDO 200 mAM l 0 900V 3 60V 100mV 70uA 2 60dB 470nF of load MEMLDO 1mA 090V 360V 100mV 5 uA 60dB Bl 1 Typical values assuming 100 Hz lt f lt 1000 Hz 2 Typical values assuming X7R type ceramic capacitor 3 Smaller external components can be used in the 500 mA configuration the AUTOLXA2 and AUTOLXB1 pins must remain unconnected in this configuration see Section 8 9 6 3 4 Current limited output limited to 175 of the max current or 350 mA module is switched off after a programmable debounce time when current exceeds specified limit afterwards the On Off Controller will regularly try to power up the module again see Section 8 11 6 2 5 Output available at the DOWN2FB pin 5 Ordering information Table3 Ordering information Type number Package Name Description Version PCF50633HN xx N3 HVQFN68 plastic thermal enhan
140. r control of the converter is asserted Consequently inrush currents will never exceed the normal input current at full load NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 62 of 125 PCF50633 PCF50633 User Manual NXP Semiconductors 8 10 6 6 Generating output voltages over Vo LED ymax The controller can generate output voltages in excess of Voi gp max With the aid of additional discrete components The GPO output can drive a discrete N type FET when the gposel bits in register GPOCFG are set to 001 see Table 33 A discrete diode is required to create a path to the output The arrangement is shown below in Figure 32 LEDLX Wo AT 18V H ja p cro PCF50633 NET L Ki 77 77 Fig 32 LED circuit arrangement for output voltages gt Vo LED ymax If required the input voltage can be prevented from being transferred to the output when the LED module is disabled This can be achieved with the addition of a PFET controlled by the GPIO output configured to ensure the PFET is active only while the LED module is enabled This arrangement is shown below in Figure 33 NXP B V 2008 All rights reserved Rev 06 05 March 2008 63 of 125 PCF50633UM 6 User manual NXP Semiconductors PCF50633 PCF50633UM 6 8 10 6 7 PCF50633 User Manual LEDOUT VBAT 4L 1717 NN Bak GPIO
141. r if a watchdog timer time out is generated When a watchdog timer time out is generated bit prewdtexp in register MBCS1 is set see Table 100 and the charger enters Halt mode If autores 0 the MBC will remain in Halt mode until the restart bit in the MBCC1 control register is set If autores 1 the MBC will return to the Play Only mode when the battery voltage falls below the resume threshold Vgar lt Vin ngs see Table 92 and Figure 39 Note Well conditioned Li ion batteries will register a voltage above 2 7 Volt within 60 minutes of precharging NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 90 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 PCF50633 User Manual 8 12 6 9 Fast charge phases Fast charging of a battery is only permitted within a certain temperature window typically between 0 and 50 C When the battery voltage reaches Vpatcong the MBC enters the Fast Charge phase provided if battempena is set the battery temperature is within a specified temperature window see Table 98 and charging continues with a constant fast charge current CC mode The fast charge current is selected via the fstchgcurx bits in control registers MBCC4 and MBCC5 see Table 95 and Table 96 Len lae Xfstchgcurx 255 5 len retj is defined in section Section 8 12 6 4 If charging is via the adapter the fast charge current is determined by the fstchgcur1 bit settings
142. r state 2 Reserved bits should be written 0 return values are not defined Table 120 RTCYR RTC year value in BCD format register address 5Fh bit description Bit Symbol Access Reset Description 7 0 year R W 00000000 current year value 00 to 99 coded in BCD format NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 104 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 15 6 PCF50633 User Manual 1 This register is reset in NoPower state Table 121 MONTH assignment Day Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 January 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April 0 0 1 0 0 May 0 0 1 0 1 June 0 0 1 1 0 July 0 0 1 1 1 August 0 1 0 0 0 September 0 1 0 0 1 October 1 0 0 0 0 November 1 0 0 0 1 December 1 0 0 1 0 RTC alarm registers Table 122 RTCSCA RTC second alarm value register address 60h bit description Bit Symbol Access Reset Description 6 0 seca R W 1111111 second alarm value 00 to 59 coded in BCD format 7 reserved 2 1 This register is reset in NoPower state 2 Reserved bits should be written 0 return values are not defined Table 123 RTCMNA RTC minute alarm value register address 61h bit description Bit Symbol Access Reset Description 6 0 mina R W 1111111 minute alarm value 00 to 59 coded in BCD format 7 reserved 2 1 This register is reset in NoPower state 2 Reserved bits should be writte
143. rated The alarm registers are preset to 1 which disables the alarm It is recommended that the rtcalarm interrupt be masked before writing a new value to the alarm registers to avoid interrupts being generated during the write cycles up to 7 register write cycles may be required to update the alarm A second interrupt is generated as its name implies every second NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 106 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 16 8 16 1 8 16 2 PCF50633 User Manual If the PCF50633 is in Standby state when an RTC alarm occurs a state transition to Active will be initiated as soon as the start up conditions are met see Section 8 1 6 2 Transitions between activity states The RTC time date registers may be updated only once per second There are no restrictions imposed when writing to the alarm registers or when reading from any of the registers Values written to the RTC registers become effective at the next 1 Hz clock pulse It can therefore take up to 1 second for new values to become active To obtain an accurate RTC a 32 kHz crystal oscillator or an external 32 kHz signal needs to be connected to the PCF50633 When an accurate 32 kHz signal is not available the clock for the RTC is derived from the integrated free running oscillator General Purpose Memory GPM Introduction The PCF50633 contains an 8 byte general purpose memory
144. re interface 33 Software interface 34 Functional description 35 System Voltage Monitor SVM 36 Introduction 2 0 eee ee eee 36 FeatlleS ua anb VEA EET up 36 Block diagram a 36 Hardware interface 37 Software interface 37 Functional description 37 Battery Voltage Monitor BVM 38 Introduction a 38 Features 0 a 38 Block diagram 0 0002 eee ee eee 39 Hardware interface 39 Software interface 39 Functional description 40 Temperature High Sensor THS 40 Introduction a 40 Fealll6S 42iutkr aera E EE od 40 Block diagram a 41 Hardware interface 41 Software interface 41 Functional description 41 32 kHz oscillator 0S5C32 42 Introduction a 42 Features as waa ba a LNAG bs 42 Block diagram a 43 Hardward interface 43 Software interface 43 Functional description 43 Power Supply Module PSM 44 Introduction a 44 Features ee eee 44 Block diagram 0 0002 ee eee eee 44 Hardware interface 44 Software interface 44 Function
145. register is reset at each transition to Standby state NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 53 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual Table 57 DOWN1MXC DOWN1 maximum current register address 21h bit descriptionl Bit Symbol Access Description 5 0 down1_maxc R W sets current limit of DOWN1 converter limax down maxc x 15 mA e g 01101 195 mA 6 downi maxcmod R W current limit mode 0 limiting at start up only 1 limiting always active 7 reserved 1 This register is reset at each transition to Standby state Reset values are determined by the IC variant see Table 7 Table 58 DOWN2OUT DOWN o p voltage select register address 22h bit description Bit Symbol Access Description 7 0 down out R W output voltage setting same as for down1 out see Table 54 1 This register is reset at each transition to Standby state Reset value is determined by the IC variant see Table 7 Table 59 DOWN2ENA DOWN output enable register address 23h bit descriptioni Bit Symbol Access Reset Description 0 down2 on R W 2 if set converter is ON down2 pic R W 2 if set converter is ON when GPIO1 1 down2_p2c R W 2 if set converter is ON when GPIO2 1 down2_p3c R W 2 if set converter is ON when GPIO3 1 5 4 down2 ena act R W BI selects activation phase 00 ACTPH1 01 ACTPH2 10 ACTPH3 11 ACTPH4 7 6 reserved
146. rter AUTOLXB2P 41 inductor connection 2 to boost part of DC to DC auto up down converter AUTOOUT1 43 DC to DC auto up down converter output 1 AUTOOUT2 42 DC to DC auto up down converter output 2 DOWN1IN 26 DC to DC step down converter 1 input DOWN1FB 27 DC to DC step down converter 1 feedback input DOWN1LX 25 inductor connection to DC to DC step down converter 1 DOWN2IN 23 DC to DC step down converter 2 input DOWN2FB 22 DC to DC step down converter 2 feedback input and MEMLDO output DOWN2LX 24 inductor connection to DC to DC step down converter 2 LEDIN 29 LED boost converter input LEDLX 31 inductor connection to LED boost converter LEDOUT 30 current controlled output of LED boost converter LEDFB 33 feedback for current loop of LED boost converter LEDFBGND 34 feedback ground sense input to LED boost converter LEDAMB 32 ambient light sensor input LDO12IN 53 shared input for LDO1 and LDC2 linear regulators LDO10UT 52 LDO1 linear regulator output LDO2OUT 54 LDO2 linear regulator output LDO34IN 56 shared input for LDO3 and LDOA linear regulators LDOSOUT 55 LDO3 linear regulator output NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 9 of 125 NXP Semiconductors PCF50633 PCF50633UM 6 PCF50633 User Manual Table 4 Pin description continued Symbol Pin LDO4OUT 57 LDO56IN 6 LDO5OUT 5 LDO6QOUT 7 HCLDOIN 4 HCLDOOUT 3 32 768 kHz oscillator OSCI 51 OSCO 50 Internal su
147. s 105 Functional description 106 General Purpose Memory GPM 107 Introduction 00 2000e 107 Block diagram a 107 Software interface 107 Functional description 108 Serial interface I2C 108 Introduction 1 2 0 cee eee ee eee 108 Features 2000s 108 Block diagrams lessen 109 Hardware interface 109 Functional description 109 I2C bus configuration 109 START and STOP conditions 110 Bit transfer 110 Acknowledge a 110 Internal timing of a write sequence 111 I2C bus protocol 111 De activation of the IC bus module 112 Register map a 113 Quality specification 117 Limiting values 00 cece eee eee 117 Thermal characteristics 118 continued 55 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 124 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 12 Application information 119 13 Package outline 120 14 Soldering eene 121 15 Legal information LL 122 15 1 Definitions 220000 eae 122 15 2 Disclaimers eee eee 122 15 3 Trademarks eee eee 122 16 Contents 2 cece ecc i RR 123
148. see Section 8 8 6 3 1 ldo2pwrfail R amp C LDO2 output voltage below 90 of target see Section 8 8 6 3 2 ldo3pwrfail R amp C LDO3 output voltage below 90 of target see Section 8 8 6 3 3 ldo4pwrfail R amp C LDOA output voltage below 90 of target see Section 8 8 6 3 4 Ido5pwrfail R amp C LDO5 output voltage below 90 of target see Section 8 8 6 3 5 Ido6pwrfail R amp C LDO6 output voltage below 90 of target see Section 8 8 6 3 6 hcldopwrfail R amp C HCLDO output voltage below 90 of target see Section 8 8 6 3 7 hcldoovl R amp C overload lo 350 mA detected in HCLDO regulator see Section 8 11 6 2 pure This register is reset in NoPower state all bits set to O NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 29 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 PCF50633 User Manual 2 This column describes the events that cause the corresponding interrupt bits to be set to logic 1 Table 22 INT1MASK Interrupt mask register 1 address 07h bit descriptionl Bit Symbol Access Description 0 adpinsm R amp C masks aapins interrupt when set 1 adpremm R amp C masks adprem interrupt when set 2 usbinsm R amp C masks usbins interrupt when set 3 usbremm R amp C masks usbrem interrupt when set 4 reserved 5 reserved 6 rtcalarmm R amp C masks rtcalarm interrupt when set 7 secondm R amp C masks second interrupt when set 1 This register is reset in NoPow
149. slaves The PCF50633 is a slave only device PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 109 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual SDA SCL MASTER TRANSMITTER RECEIVER Fig 53 I2C bus system configuration MASTER TRANSMITTER SLAVE TRANSMITTER RECEIVER mba605 RECEIVER 8 17 6 8 17 7 8 17 8 PCF50633UM 6 START and STOP conditions Both data and clock lines remain HIGH when the bus is not active A HIGH to LOW transition on the data line while the clock is HIGH is defined as the START condition S When this occurs the bus becomes busy A LOW to HIGH transition on the data line while the clock is HIGH is defined as the STOP condition P This terminates data transfer and frees up the bus see Figure 54 START condition STOP condition mbc622 Fig 54 START and STOP conditions on the I2C bus Bit transfer A single data bit is transferred during each clock pulse The data on the SDA line must remain stable while the clock pulse is HIGH as state transitions that occur on the data line while the clock is HIGH are interpreted as control signals see Figure 55 puo c UN data line change stable of data data valid allowed mbc621 Fig 55 Bit transfer on the I2C bus Acknowledge There is no limit to the amount of data that can be transmitted between the STA
150. st be read the next time the chip starts up in order to clear the hightmp interrupt If this is not done the hightmp interrupt will remain active Built in hysteresis and debounce filter prevent rapid cycling of the hightmp signal The THS cannot be disabled via I2C bus interface The high temperature status can be determined by sampling status bit tmpok in the OOCSTAT register see Table 14 8 7 32 kHz oscillator OSC32 8 7 1 Introduction The 32 768 kHz crystal oscillator provides an accurate low frequency clock signal for the PCF50633 and external circuitry 8 7 2 Features An accurate low frequency clock for internal timing An external 32 kHz clock via the CLK32K pin which is an open drain output that becomes active as soon as the PCF50633 enters Active or Standby state depending on the settings of the xxxclk32on bits in the OOCCTL register see Table 13 Provides a reference for internal clocks e g switching regulators PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 42 of 125 NXP Semiconductors PCF50633 8 7 3 Block diagram PCF50633 User Manual Clocking module OSC321 gt Circuit clocks T 32 kHz internal 32 768 kHz BN Oscillator 32 kHz clk Y OSC32 T Clock OSC320 pi En gt CLK32K Note that 2 external capacitors must be connected as illustrated Fig 24 OSC32 bloc
151. ster 2 address 3Eh bit description continued Bit Symbol Access Reset Description 3 2 Ido2 debpf R W 11 LDO2 power failure debounce time settings like do1 debpf 5 4 Ido3 debpf R W 11 LDOS power failure debounce time settings like do1 debpf 7 6 Ido4 debpf R W 11 LDO4 power failure debounce time settings like do1 debpf 1 This register is reset in NoPower state Table 44 DEBPF3 Power fail debounce register 3 address 3Fh bit description Bit Symbol Access Reset Description 1 0 Ido5 debpf R W 11 LDO5 power failure debounce time 00 none 01 1 ms 10 10 ms 11 100 ms 3 2 ld06 debpf R W 11 LDO6 power failure debounce time settings like do5 debpf 5 4 hcldo debpf R W 11 HCLDO power failure debounce time settings like do5 debpf 7 6 reserved 1 This register is reset in NoPower state Table 45 DCDCSTAT DC to DC converter status register address 41h bit description Bit Symbol Access Description 0 auto pwrok R 0 AUTO Vo lt 90 of target 1 AUTO Vo gt 90 of target 1 down1_pwrok R 0 DOWN1 Vo lt 90 of target 1 DOWN1 Vo gt 90 of target 2 down2_pwrok R 0 DOWN2 Vo lt 90 of target 1 DOWN2 Vo gt 90 of target 3 led_pwrok R 0 LED lo lt 90 of target 1 LED lo gt 90 of target 7 4 reserved Table 46 LDOSTAT LDO status register address 42h bit description Bit Symbol Access Description 0 ldo1 pwrok R 0 LDO1 Vo 90 of target 1 LDO1 Vo gt 90 of targ
152. t an event has occurred that may require it to take some action Interrupts can be generated by a number of modules The interrupt controller does not prioritize interrupts This is the responsibility of the host controller There are no timing restrictions relating to interrupt processing All events demanding immediate action are processed by the PCF50633 without requiring action from the host controller The interrupt controller captures and masks interrupt signals generated in the relevant modules When an interrupt is generated the interrupt controller signals the event to the host controller by forcing IRQ low and setting the relevant bit in the appropriate interrupt register IRQ is implemented as an open drain output The interrupt controller is active in all states with the exception of the NoPower state Events that occur in the Standby state are captured and stored so that they can be processed by the host controller once the system returns to the Active state Interrupt registers 8 bit are cleared once they have been read via the I C bus interface Interrupts generated while a read and clear R amp C operation is being performed are still captured Note that when the PCF50633 shuts down in response to an interrupt lowsys onkey1s hightmp etc the appropriate interrupt register must be read when the chip starts up again in order to clear the interrupt If this is not done the PCF50633 will not shut down as expected the next t
153. t control by means of an external sense resistor Digitally controlled Pulse Frequency Modulation PFM Bus controlled dimming by logarithmic scaling of the LED current Digital ramp up and ramp down control for smooth on off transitions using the logarithmic dimming scale Ambient light sensor Inrush current limiting Overcurrent protection Overvoltage protection Maximum output voltage of Vo Epy max using internal switch or greater using additional discrete components Output disconnected from input when switched off Module can also be used to create a 5 V 100 mA USB supply NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 58 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 8 10 3 Block diagram LEDLX HH LEDOUT 7 10 uF xS LEDFB Ve CEDIN US Hardware B GPIOx ER Control SENSE LEDFBGND Software Control Fig 30 LED block diagram 8 10 4 Hardware interface Table 66 LED characteristics Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Voen LED output voltage 5 18 V loep LED output current Vo LED 18 V 25 mA Voen 5 VI 100 mA Vigprae Voltage on pin LEDFB 1 512 1 25 V x 1 25 Vi ow Over voltage protection threshold 18 19 20 V voltage Vinocp Over current protection threshold led ocp 0 1000 mA voltage led ocp 1 500 mA fsw
154. t the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification 15 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners 12C bus logo is a trademark of NXP B V NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 122 of 125 NXP Semiconductors PCF50633 16 Contents PCF50633 User Manual 1 Introduction lesen 3 8 3 4 2 Features esI REUS mE 3 835 2 1 System control eee ee eee 3 8 3 6 2 2 Supplies cece eee 3 8 4 2 3 Battery management usus 4 8 4 1 24 POG PERIERE 4 842 3 ApplicationS 00 cece eee eee 4 4 Quick reference data 5 845 5 Ordering information 6 8 4 6 6 Functional Diagram se 7 8 5 7 Pinning Information a 8 8 5 1 74 Pinning PAPA re mE Ds 8 8 5 2 7 2 Pin description 0 00 e eee eee 8 8 5 3 8 Functional description 11 aaa 8 1 On Off Control OOC A 11 85 6 8 1 1 Introduction 11 86 8 1 2 Features i eieaa See Ua x RES 11 8 6 1 8 1 3 Block diagram aa 11 86 2 8 1 4 Hardw
155. te However it can also be used by an external circuit to force a transition from Active to Standby KEEPACT supports two modes Keepact mode after a transition from Standby to Active the PCF50633 expects the KEEPACT input to be forced HIGH by the host controller If this does not happen within 100 ms of RSTHC going HIGH the PCF50633 reverts to Standby Heartbeat mode after a transition from Standby to Active the PCF50633 expects the KEEPACT signal to toggle at least every 500 ms If this does not happen the PCF50633 reverts to Standby Regular Keepact mode is selected by default Heartbeat mode is selected when the heartbeat control bit in the OOCCTL register is set see Table 13 KEEPACT timing is illustrated in Figure 12 and Figure 13 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 25 of 125 NXP Semiconductors PCF50633 8 1 6 12 8 1 6 13 PCF50633UM 6 PCF50633 User Manual System n state Standby Active standby i RSTHC KEEPACT z o 100 ms se 1 The KEEPACT signal must be set in this interval to maintain the Active state Fig 12 KEEPACT timing Keepact mode System etate Active Standby Standby RSTHC KEEPACT 500 ms 1 The KEEPACT signal must toggle in this interval to maintain the Active state Fig 13 KEEPACT timing Heartbeat mode
156. tem USB gt zn HE MARET UVP AH eee gt gt T USB to SYS path USB SYS FET Im Adapter I K Ideal charger NG q diode 2 ao USB charger IM Main battery USB BAT FET 777 Fig 42 Current flow from USB without charging system takes less than USB budget If the requirements of the system exceed the USB current budget the USB SYS FET current limiter will be activated and the usblim play bit set The USB SYS FET will then act as a current source PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 86 of 125 NXP Semiconductors PCF50633 PCF50633UM 6 PCF50633 User Manual Since the system now requires more current than the USB SYS FET can deliver Vsys will begin to fall When Vsys lt Vegar the ideal diode will start to conduct The situation depicted in Figure 41 recurs If the autores bit in control register MBCC7 is set charging will resume Otherwise the battery will gradually run down in this situation If system current requirements fall or if the USB current budget is increased and Isys falls until it is lt li iwusg Vsvs Will steadily rise Once Vsys gt Vpar the ideal diode will block current flow from the battery USB suspend mode The host controller can suspend the USB by writing 11 to the usbdevstat control bits in the MBCC7 register see Table 98 All MBC circuits will be disabled with the exception of The Adapter presence detector in order to
157. the BATTEMP conversion is stored in the ADCS1 ADCS3 bit 1 0 status registers and the result of the ADCIN1 conversion is stored in the ADCS1 ADCS3 bit 3 2 status resisters Before starting a ratiometric measurement a settling period determined by the adcratioset bit should be specified see Table 108 The NTCSW and ACCSW pins provide biasing for the half bridge when measuring voltages on BATTEMP and ADCIN1 respectively Biasing should be activated bits ntcswen or accswen set to 1 see Table 109 before initiating the ADC conversion sequence Biasing is automatically disabled ntcswen or accswen set to 0 when the conversion is complete to conserve power NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 101 of 125 NXP Semiconductors PC F50633 PCF50633UM 6 8 14 6 4 8 15 8 15 1 8 15 2 PCF50633 User Manual The ADCIN1 and BATTEMP inputs can be used as normal ADC inputs if a ratiometric mode is not selected adcratioen 0 Ratiometric measurements can be used for determining the value of id resistors found in some battery packs see Figure 49 l BATx J VISA ACCSW t i VISA to ACC biasing switch ACCIN1 NTCSW VISA to NTC biasing switch h BATTEMP ld resistor SSS ae pet ccc NTC 7T mE thermistor Main T battery i Shs gna sac dl ee nig td AA GAO AO Fig 49 Typical application diagram for b
158. to 8 seconds 3 2 exton2 mode R W EXTON2 mode selection behavior like exton1 mode 5 4 exton3 mode R W EXTON3 mode selection behavior like exton1 mode 7 6 onkey mode R ONKEY mode selection 00 wake up on falling edge only 01 wake up on falling edge sets the time out timer to 8 seconds if held LOW for 1 second 10 wake up on falling edge only rising edge sets the time out timer to 8 seconds 11 reserved 1 This register is reset in NoPower state Reset values are determined by the IC variant see Table 7 PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 14 of 125 NXP Semiconductors PCF50633 PCF50633UM 6 8 1 6 8 1 6 1 PCF50633 User Manual Table 13 OOCCTL OOC control register address 11h bit description Bit Symbol 1 0 actphrst 2 actclk32on 3 heartbeat 4 usbbatchk 5 reserved 6 stbclk32on 7 reserved Access Description R W R W R W R W R W selects activity phase to which host controller reset is related 00 related to activation phase 1 01 related to activation phase 2 10 related to activation phase 3 11 related to activation phase 4 CLK32K output disabled in Active state CLK32K output enabled in Active state KEEPACT input requires DC HIGH KEEPACT input requires toggling input to retain Active state Vpar status has no effect on state machine Vpat must be gt Vin batok to go to Standby state SO O o0
159. trol input The ONKEY input is intended to be connected to a push button which when pressed connects the input to ground The ONKEY input has an internal pull up resistor to ensure the input is HIGH by default However it can also be used as a regular control input The onkey wake control bit bit O in register OOCWAKE see Table 9 enables disables the ONKEY function A programmable debounce filter is incorporated into the ONKEY input The debounce time is determined by the setting of control bits onkey deb bits 2 0 in control register OOCTIM2 see Table 11 The ONKEY mode which determines how the PCF50633 responds when the push button is pressed is selected via the onkey mode control bits bits 7 6 in control register OOCMODE see Table 12 Three interrupts onkeyf onkeyr and onkey1s are generated when the push button is pressed and released as illustrated in Figure 7 and Figure 8 A transition from Active to Standby in response to an ONKEY event is interrupt driven NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 21 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual Note that if the PCF50633 goes to Standby in response to an onkey1s interrupt the interrupt register must be read the next time the chip starts up in order to clear the onkey1s interrupt If this is not done the next onkey7s interrupt driven transition to Standby will fail The status of the ONKEY pi
160. ual Table 85 LDO5ENA LDO5 output enable register address 36h bit descriptionl Bit Symbol Access Description 3 Ido5_p3c R W if set LDO is ON when GPIOS 1 5 4 do5 ena act R W selects activation phase 00 ACTPH1 01 ACTPH2 10 ACTPH3 11 ACTPH4 7 6 reserved 1 This register is reset at each transition to Standby state Reset values are determined by the IC variant see Table 7 Table 86 LDO6OUT LDO6 output voltage select register address 37h bit description Bit Symbol Access Description 4 0 ldo6 out R W Vo prog 0 9 do6 outx 0 1 V max 3 6 V e g 00000 0 9 V 00001 1 0 V 11000 3 3 V 11011 3 6 V 11111 3 6 V 5 ld06 swmod R W 0 linear regulator mode 1 switch mode 7 6 reserved 1 Reset values are determined by the IC variant see Table 7 Table 87 LDO6ENA LDO6 output enable register address 38h bit descriptionl Bit Symbol Access Description 0 Ido6_on R W if set LDO is ON 1 Ido6_pic R W if set LDO is ON when GPIO1 1 Ido6_p2c R W if set LDO is ON when GPIO2 1 ld06 p3c R W if set LDO is ON when GPIOS 1 5 4 l do6 ena act R W selects activation phase 00 ACTPH1 01 ACTPH2 10 ACTPH3 11 ACTPH4 7 6 reserved 1 Reset values are determined by the IC variant see Table 7 Table 88 HCLDOOUT HCLDO output voltage select register addr 39h bit descriptionl Bit Symbol Access Description 4 0 hcldo out R W Vojprog 0 9 hcldo outx
161. urement Two independent analog inputs ADCIN1 and ADCIN2 e Selectable and programmable voltage divider functionality BATSNS and ADCIN2 for high voltage low resolution measurements Selectable voltage subtractor functionality BATSNS and ADCIN2 for high voltage high resolution measurements NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 96 of 125 NXP Semiconductors PCF50633 8 14 3 Block diagram PCF50633 User Manual BATSNS BATTEMP ADCIN1 ADCIN2 successive appriximation comparator VISA NTCSW ACCSW Fig 48 ADC block diagram adcrdy interrupt 8 14 4 Hardware interface Table 106 ADC characteristics Vss REFGND GND 0 V Tamp 40 to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Vancen input voltage on pin ADCIN1 0 2 0 V VigarrEMP input voltage on pin BATTEMP 0 7 2 0 V ViApciNo input voltage on pin ADCIN2 full scale mode divide by 2 0 4 0 V full scale mode divide by 3 0 5 5 V subtraction mode 2 25 425 V ViBArsNs input voltage on pin BATSNS full scale mode divide by 2 0 4 0 V full scale mode divide by 3 0 5 5 V subtraction mode 2 25 425 V RES resolution adcres 0 10 bits adcres 1 8 bits DNL differential non linearity ADCIN1 and BATTEMP inputs 0 7 0 7 LSB high voltage ADCIN2 and BATSNS 0 8 0 8 LSB inputs full sc
162. uts as illustrated in Figure 9 EXTONx Mi in 4 tdebounce A EXTONx debounced E extonxr interrupt qe tdebounce extonxf interrupt system state Standby Active The debounced signal retains its original value until the new value has been stable for at least the selected debounce time A spike gt 30 us in the original signal will reset the debounce timer The filter suppresses all signal activity shorter than the debounce time wake up on rising edge of EXTONx input extonx mode 01 Fig 9 EXTON behavior SHUTDOWN control input When a positive edge is detected on the SHUTDOWN input a transition from Active to Standby is initiated The SHUTDOWN input features a programmable debounce filter The debounce time is determined by the setting of control bits shdwn deb bits 7 6 in control register OOCTIM 1 see Table 10 go stby bit Writing 1 to the go stby control bit initiates a transition from Active to Standby state bit 0 in control register OOCSHDWN Table 8 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 23 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual A 2 ms delay is inserted between the write operation and the disabling of activation phase 4 ACTPH4 see Section 8 1 6 8 below This allows the host controller to perform any necessary housekeeping tasks Figure 10 shows a timing diagram for a shutdown sequenc
163. vely 1 or 8 seconds if the host controller doesn t intervene in the meantime A direct and immediate transition occurs when Vsys falls below the Vih sysmin The following conditions initiate the time out timer e lowsys interrupt when the system voltage drops below Vir sysok specified by the svmlvl control bits in register SVMCTL see Table 35 8 second time out e hightmp interrupt when the die temperature exceeds the maximum temperature threshold Tih die 1 second time out Time out timer PCF50633 on off control uses a time out timer to set up delays before responding to several events as discussed above in Section 8 1 6 2 The timer is set to 8 seconds for all events other than a high die temperature event when the timer is set to 1 second These delays are inserted to allow the host controller time to poll interrupts and respond to events The fotrst bit in control register OOCSHDWN can be used to extend the delay if necessary or to ignore the event see Table 8 When totrst is set to 1 e f no timer related interrupts interrupts that would cause the timer to be initiated have been generated the timer is stopped In this case the PCF50633 remains in the Active state f one or more timer related interrupts have been generated but have not been read by the host controller the timer is reset The delay is set to 1 or 8 seconds as appropriate allowing the host controller time to poll the remaining interrupts ONKEY con
164. voltage on pin ADAPTSNS 4 53 V VusB USB supply voltage 4 53 V Vvisa voltage on pin VISAI 24 V Vvisc voltage on pin VISCHI 24 V VREFC voltage on pin REFCI 09 V Vo LED LED output voltage 5 18 V sw PWM PWM switching frequency for DOWN1 DOWN and AUTO 1 7 MHz converters sw PFM PFM switching frequency for LED boost converter 1 MHz Tih die die threshold temperature 125 C Vih batok battery OK threshold voltagel l range programmable in 100 mV steps 2 8 3 4 V Vih sysok system OK threshold voltage 3l range programmable in 100 mV steps 2 8 34 V Vih sysmin minimum system ON threshold voltage 25 V Vih syspres system threshold voltage for save state no backup battery 1 7 2 23 V Vih bubpres backup battery threshold voltage for save 1 13 16 V statel l Vih adaptpres adapter presence threshold voltage 3 25 36 3 95 V Vih usbpres USB adapter presence threshold voltage 3 25 36 3 95 V IpD tot total supply current in Save state Vgar 2 5 V no USBor 50 UA adapter present in Standby state all supplies disabled 60 UA Vear 3 6 V no USB or adapter present in Active state all supplies enabled 1 mA no load Vgar 3 6 V no USB or adapter present 1 Note that Vyjsa Vvisc and Vrerc are internal signals Pins VISA VISC and REFC are provided to allow external decoupling capacitors to be connected Decoupling is necessary to ensure stable operation 2 If a USB supply is conn
165. watchdog timer not expired 1 watchdog timer expired 7 wdtexp R watchdog timer status indication after pre charge 0 watchdog timer not expired 1 2 watchdog timer expired PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 80 of 125 NXP Semiconductors PCF50633 PCF50633 User Manual Table 101 MBCS2 MBC charger status register 2 address 4Ch bit description Bit 3 0 5 4 Symbol mbcmod chgstat resstat reserved Access Description R R main MBC operating modes and charge phases 0000 Play Only mode 0001 USB Precharge phase 0010 USB Precharge Wait phase 0011 USB Fast Charge phase 0100 USB Fast Charge wait phase 0101 USB suspend mode 0110 adapter Precharge phase 0111 adapter Precharge Wait phase 1000 adapter Fast Charge phase 1001 adapter Fast Charge wait phase 1010 Battery Full mode 1011 Halt mode 1100 1111 reserved charger connection status 00 no charger detected 01 adapter voltage detected 10 USB voltage detected 11 adapter and USB voltage detected Automatic Resume status indication 0 charging has not resumed automatically 1 charging has resumed automatically Table 102 MBCS3 MBC charger status register 3 address 4Dh bit description Symbol usblim play usblim chg tlim play tlim chg ilim vlim vbatstat vres Access Description R R R R USB current limiting loop in USB to SYS
166. which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 15 2 Disclaimers General Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof PCF50633UM 6 Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is a
167. y Table 135 MEMBYTE6 General purpose memory byte 6 address 6Dh bit description Bit Symbol Access Reset Description 7 0 membyte6 R W 00000000 byte 6 of 8 byte general purpose memory Table 136 MEMBYTE7 General purpose memory byte 7 address 6Eh bit description Bit Symbol Access Reset Description 7 0 membyte7 R W 00000000 byte 7 of 8 byte general purpose memory 8 16 4 Functional description The PCF50633 includes an 8 byte general purpose memory block which can be used to support sleep states for RTC encryption or for any other purpose required by the application R W operations to the general purpose memory registers are via the I2C bus interface Data is retained as long as the device does not enter the NoPower state even when the backup battery is the only valid power source 8 17 Serial interface 12C 8 17 1 Introduction The serial interface of the PCF50633 uses the I C bus A detailed description of the I2C bus specification including applications is provided in The C bus and how to use it brochure order no 9398 393 40011 or in the PC Peripherals Data Handbook IC12 8 17 2 Features Data transfer speed up to 400 kHz Slave device PCF50633UM 6 NXP B V 2008 All rights reserved User manual Rev 06 05 March 2008 108 of 125 NXP Semiconductors PC F50633 PCF50633 User Manual 8 17 3 Block diagrams SCL 12C interface 12C data SD

Download Pdf Manuals

Related Search

PCF50633 pcf50633 pcf50606hn

PCF50633

Contents

Download Pdf Manuals

Related Search

Related Contents