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FIPSOC User Manual

1. 48H Return ends with RET instead of LJMP Codes 80H to FFH are used for command set extension DATABUF DS 40H Data buffer checksum STACK DS 1 Where the stack pointer should initially point to SFMDCOD EQU FFFDH This is the self modifying code location for SFR indirect access EXT CMD EQU FF2BH Code for extending the HEX command set COLONVAL EQU Constant value for the colon character FIRSTDEV EQU AH Ihe first I2C device to be probed Chapter 9 FIPSOC Boot Program 9 au Ck ck ck ck ck ck ck ck Ck Ck Ck Ck 0k Kk kk kk kk kk kk kk kk 0k 0k 00k Sk Sk kx Sk kx ko ko kockckckckckck CODE IDSA Interrupt pseudovectors pointing to upper RAM Linked to INIT program RESET VEC IEO NIT VEC TFO VEC_IE1 VEC_TF1 INIT3 VEC_RITI KKKKKKKKKK KKK KKK KKK KKK KK KK KKK KKK KKK KKK ck ck ck kk kk kv ko ko ko kckckckckck Off we KKKKKKKKKK Sk ke ke ke kk kk kk CCS Sk e ke ke KKK KKK ck ck ck kk kk ko kokok kk ko kckck INIT4 ORG 00 MOV R3 A SUMP INIT LJMP FFO3H SJMP INIT LJMP FFOBH MOV DPTR SJMP INIT2 LJMP FF13H MOV A 02H SJMP INIT3 nop MOV SP STACK EXT_CMD LUMP FF1BH MOV RG2 A MOVX DPTR A SJMP INIT4 LJMP FF23H go INC DPTR MOV A ERROR 100H MOVX DPTR A INC DPTR This clears This should This should This should Op code for Empty byte This should this is quite tricky Semiconductor Desig
2. 3 Uncomment the following if the next routine is not SENDCMD ACALL SENDCMD RET Tk kk Routine SENDCMD Inputs R2 is used to specify the command use XXXX XX11b for START and RESTART x use XXXX_XX10b for STOP Outputs None Modifies A R2 Used for sending a STOP START or RESTART command to the I2C interface CC CK CK ke Sk kk kk ke kk kk kk kk S Sk e ke ke kk kk ck ck ck kk Ck kk Mk kv kv ko ko kockckckckckock SENDCMD MOV A SCREG ID S A Semiconductor Design Solutions Chapter 9 FIPSOC Boot Program 16 ud S ID S A Semiconductor Design Solutions ANL A FCH ORL A R2 MOV SCREG A CMDLOOP MOV A SCREG JB A CMD CMDLOOP RET end Chapter 9 FIPSOC Boot Program 17
3. OEEH OEFH OF1H OF2H OF3H OF4H OF5H OF 6H OF7H Chapter 9 FIPSOC Boot Program ud ID S A Semiconductor Design Solutions ROWL EQU OF8H ROWH EQU OF9H COLL EQU OFAH COLH EQU OFBH RG1 EQU OFCH RG2 EQU OFDH RGTX EQU OFEH outCOMP EQU OFFH PAGE TITLE boot asm Constants for bit addressing the accumulator BOOT1 EQU 7 These three flags store the boot mode BOOTO EQU 6 MASTER EQU 5 BAUD EQU 0 Baud rate when booting from SCI Constants for bit addressing the accumulator CCF EQU 7 Comunicaci n complete flag I2CMAST EQU 6 Sets to one when we are master SDRC EQU 5 l Send O receive CKO EQU 4 1 100KHz 0 1MHz ID EQU 3 To see if we have been addressed slave ERR EQU 2 Sets to one when we don t get an acknowledge CMD EQU 1 Write this bit to send commands BBUSY EQU 0 Bus Busy also used to send commands KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK DATA ORG 7BH This is located here so the data buffer starts on 80H COLON DS 1 Dummy buffer to store the frame start a colon LENGTH DS 1 Number of bytes in DATABUF ADD H DS 1 Address high byte ADD L DS 1 Address low byte REC T DS 1 00 Write to external mem 08H Read from external data mem 0CH Read from external program mem 7108 Indirectly write to internal mem 7 18H Indirectly read from internal mem 7 20H Directly write to internal mem 7 28H Directly read from internal mem 40H Jump to address LJMP
4. SIDSA CK1 CK2 SPI clock frequency for frequenc f L716MHz 0 0 f5 8 2 MHz 0 1 foso 16 1 MHz 1 0 15 32 500 KHz 1 1 fosc 64 250 KHz Table 2 SPI clock frequencies upon reset OD bit 2 Bit lines will be open drain if OD is set to 1 normal CMOS outputs otherwise Bits1 and 0 not sampled upon reset If configured as master the initialization sequence goes as follows step 1 bit 0 of the general purpose register is driven low and the corresponding bit of the data direction register is set to output to select a slave through the slave select line typically the serial memory step 2 Command 03H is sent through the line which is interpreted by a serial SPI memory as a read command step 3 Two zero bytes are sent through the line which is interpreted by a serial SPI memory as a the initial memory location to start reading from step 4 dummy FFH byte is sent through the line which provokes the first real data byte to be obtained from the serial memory After initialization the boot program keeps reading the incoming bytes and interpreting extended HEX records as the are completed Once a byte has been received the same byte is echoed back through the line to trigger the next read in the memory When a JUMP instruction is found record type 40H bit O of the general purpose port is released and configured again as input and the SPI communications system is switched off b
5. Sk Sk kx kk ko kc kc kckckckok ID S A Semiconductor Design Solutions Chapter 9 FIPSOC Boot Program 15 Routine WAITAIT Inputs None Outputs A stores bits CCF and ERR H R5 stores SCREG but bits SDRC and CKO Modifies A R5 Waits for a transmission to be completed CCF or ERR KKKKKKKKKKKKKKKKKKKKK Sk Sk kk kk ck kc ko kk ck kk kk kk kk Sk Sk Sk ke Sk kc kc ko kckckckckckok WAITAIT MOV A SCREG Wait for a serial byte to be transmitted ANL A CFH Bits 5 and 4 are not interesting MOV R5 A Save SCREG in R5 ANL A 84H Wait for CCF or ERR JZ WAITAIT RET Ck ck ck ck ck ck ck ck ck kk kk 0k kk kk Sk Sk kk kk kk kk Ck 0k 0k 0k Sk Sk Sk kx Sk kk ko ko kckckckckckok Routine I2CSTOP Inputs None Outputs None Modifies A and R2 calls SENDCMD Sends a STOP command to the I2C interface using SENDCMD ck ck ck ck ck ck ck ck ck ck ck kk Ck kk kk Sk Sk kk Sk kk kk kk ck ck ck ck kk kk kk Sk Sk Sk Sk kx kk ko kckckckckckok I2CSTOP MOV R2 2 ACALL SENDCMD RET Ck ck ck ck ck ck ck ck ck Ck Ck Ck kk kk ek kk kk kk kk kk 0k 0k 0k 0k kk kk Sk Sk Sk kx kx ko ko kockckckckckckok Routine START RESTART Inputs None Outputs None Modifies A R2 calls SENDCMD Sends a START command to the I2C interface using SENDCMD Kock ck ck ck ck ke ck ck ck ck ck ck ck ck ck ck koc koc kk ke ck ee ck ck ckockckckckockckckckckokckokckokckckckokckckckckok START RESTART MOV R2
6. the STOP command is issued before returning If configured as a slave the program waits to be addressed a WRITE command is received with the appropriate device address and then sends a dummy FFH to acknowledge the reception After that the program keeps receiving bytes through the 2 wire line and interpreting extended HEX records as they SIDSA are completed When a JUMP instruction is found record type 40H the 2 wire communications system is switched off before actually executing the jump It is important to note that record types 08H OCH 18H and 28H used for memory reading are not supported in 2 wire boot modes A program extension has to be loaded somewhere else for example in the auxiliary upper RAM located in FF00 to FFFF to extend the supported record type set 1 25 Booting from SCI When bootl is 1 and bootO is O during the reset sequence the extended HEX records are fetched from the RS232 serial port Bit 48 of the address port AD 8 is latched upon reset into the BAUD bit of the BTREG register and is used to determine the initial baud rate of the incoming bytes if set f 5 4992 is selected 3205 1 baud if a typical 16 MHz xtal is used f 1536 otherwise 10416 6 baud if a typical 16 MHz xtal is used After initialization the boot program keeps reading the incoming bytes from the serial line and interpreting extended HEX records as the are completed Once a byte has been received the same byte
7. ERROR SJMP GET FRAM ACALL PROGMEM JZ GET FRAM IDSA CINE RO COLONVAL ERROR Semiconductor Design Solutions Check if the colon was OK We limit the number of bytes to 3F Get a byte and bring it in A Total number of bytes R2 is used as a down length 4 counter Sum of al bytes checksum 0 This is going to be used in the three commands Jump if REC T 40H Return if REC T 48H Do not stop if this is a subroutine SREC T gt 80H Extended command in SFF2B Uncomment the following if the next label is not ERROR ERROR SJMP ERROR ANL BTREG F7H SJMP ERROR We reset GOE CK CK CK CK Ck kk kk kk ke kk kk kk kk kk Sk kk Sk Sk Sk Sk kx Sk ko ko kockockckckockok End communications ck ck ck ck ck ck ck kk kk kc ke ck ck kk ck ck ck koc kk kk ock ck ck ck ko ko ko ko ko ko ko kckokok ENDCOMS ENDSL ENDSCI MOV A BTREG JNB A BOOT1 ENDSCI JNB A BOOTO ENDSL JNB A MASTER ENDSL ACALL I2CSTOP MOV MOV ANL RET PORT1 FFH DDRP FFH BTREG 7FH JNB TI ENDSCI If SCI wait for TI clear it and bail out IF SPI just switch the system off and bail out Otherwise it s I2C If we re master then stop the communication Otherwise switch off the coms system Chapter 9 FIPSOC Boot Program 12 IDSA CLR TI RET Semiconductor Design Solutions Ck ck ck ck ck ck ck ck ck Ck Ck Ck 0k kk kk kk kk kk kk kk kk Ck 0k 0k 0k Sk k
8. KKKKKKKKK Routine GET BYTE inputs None Outputs A stores bits CCF and ERR R3 stores the recevied byte R5 stores SCREG but bits SDRC and CKO Modifies A R3 R5 WAITAIT is called afterwards Gets a byte no matter where from and echoes it afterwards CK CK CK OK ke e kk Sk kk kk kk kk Sk e ke Sk ke ke kk kk ck ck ck kk kk ko ko ko ko kockckckckck ck GET BYTE MOV A BTREG Get a byte no matter where from result in R3 JNB A BOOT1 GB SCI GB SCOM ACALL WAIT4IT Get a byte from I2C or SPI master or slave CINE A 80H RETERR MOV R3 CMBUF MOV CMBUF R3 CLR A No error RET GB SCI JNB RI GB SCI Get a byte from the serial port CLR RI MOV R3 SBUF CLR TI MOV SBUF R3 Echo the received byte CLR A No error RET KKKKKKKKKKK kk kk kk kk Sk S ke ke ke kk kk ck ck ck ck Ck kk ko kv kv ko ko kckckckckckck Routine TXBYTE Inputs R3 is the byte to send Outputs A stores bits CCF and ERR E R5 stores SCREG but bits SDRC and CKO Modifies A R5 WAITAIT is called afterwards Transmits a byte trough the I2C or SPI line and waits until transmission is finished Kk ck ck kc ke ck ck ck ck ck ck ck ck ck ck koc ckock kk ck ck ck ckckckckckckckck ckckckckckckckckokckokckokckckckokckck ck ckok TXBYTE MOV CMBUF R3 Send a serial byte stored in R3 Uncomment the following if the next routine is not WAITAIT E ACALL WAITAIT F RET KKKKKKKKKKKKKKKKKKKKK kk Sk kk kk ck ck ck ck ck ck kk Sk kk kk Sk Sk
9. OM supporting SPI or 2 wire protocols RS 232 and SPI modes also support reading so the whole chip can be controlled programmed and read using a single serial link typically from a PC 1 Boot modes FIPSOC provides four boot modes which are selected from external pins boot and boot2 The address port AD 15 8 is sampled during reset to provide extra configuration information Table 1 shows the four boot modes Chapter 9 FIPSOC Boot Program Semiconductor Design Solutions boot1 boot Boot mode 0 0 2 wire 0 1 SPI 1 0 SCI 1 1 External parallel ROM Table 1 FIPSOC boot modes The last FIPSOC boot mode can be read with the special function register SFR SBCR located at address 9D 7 6 5 4 3 2 1 0 SCEN SCSL Master SCIE GOE OD IREN BAUD SCEN bit 7 Serial Communication Enable The serial communication system which can be configured either as 2 wire or SPI is enabled if this bit is high Its value upon reset is the inverted value of the external BOOT pin SCSL bit 6 Serial Communication Select The serial communication system is configured as 2 wire if this bit is set SPI otherwise Its value upon reset is the inverted value of the external BOOTO pin Master bit 5 Boot Master This bit stores the serial communication mode master or slave upon reset Its value is the inverted value of bit 415 of the address port AD 15 and is latched d
10. Rs The number of bytes that can be written is limited to 63 and an attempt to write more than that will in general cause a checksum error Record type 18H Indirectly Read from internal memory The general syntax for this record is the following 01H add H add L 18H number of bytes checksum Interpretation of this command reads number of bytes bytes from sequential memory locations of the internal data RAM memory starting from address add L using indirect addressing the add H field is ignored but used in the checksum This implies that reads from addresses ranging from 80H to FFH will be done on data memory rather than SFRs Data is sent trough the serial link sequentially as it is read This record is not supported if 2 wire communication mode is selected Record type 20H Directly write to internal memory The general syntax for this record is the following number of bytes add H add L 20H byte lt checksum gt Interpretation of this command writes number of bytes bytes specified in the byte fields in sequential memory locations of the internal data RAM memory starting from address add L using direct addressing the add H field is ignored but used in the checksum This implies that writes to addresses ranging from 80H to FFH will be done on SFRs rather than data memory The number of bytes that can be written is limited to 63 and an attempt to write more than that will in general c
11. ZG SIDSA Chapter 9 FIPSOC Boot Program FIPSOC User s Manual FIPSOC Boot Program Overview The Field Programmable System On Chip FIPSOC constitutes a new concept in system integration It provides the user with the possibility of integrating a microprocessor core along with programmable digital and analog cells within the same integrated circuit This chip can be considered as a large granularity FPGA with a FPAA Field Programmable Analog Array and a built in microprocessor core that does not only act as a general purpose processing element but also configures the programmable cells and their interconnections Therefore there is a strong interaction between hardware and software as long as signal values and configuration data within the programmable cells are accessible from microprocessor programs This chapter describes the program stored in internal ROM used to boot the device from a serial stream The program interprets in real time an extension of Intel s HEX records Commands are provided for programming internal both directly and indirectly and external RAM reading internal both directly and indirectly and external RAM and code ROM and program branching and returning SFRs can then be accessed this way as long as direct writes to the internal memory can be done The extended HEX records are taken either from the RS 232 serial port typically coming from a PC or from a serial memory typically flash or E PR
12. ally suffice to trick the assembler into believing that these symbols will be placed in legal direct memory locations lower than 7FH although the linker could object if it notices the final memory locations which is not usual as the linker does not use to perform any consistency check WDOG RG3 SCREG I2CREG SPIREG BTREG DDRP CMBUF VPLLL VPLLH VHW1L VHW1H VCLKL VCLKH VHW2L VHW2H VDBGL VDBGH VHW3L VHW3H VHW4L VHW4H VANAL VANAH EIMRO EIMRI SGNIO SGNI1 IRS IRSCKDB DANA1 DANA2 DANA3 DANA4 DANAS DANA6 DANA7 DANA8 ANAST DBGCNF DBGMSK DBGOL DBGOH DBG1L DBG1H DBG2L DBG2H DBG3L DBG3H DBG4L DBG4H DBG5L DBGSH CKCONF CKCNTL CKCNTH CKDMC2 CKDMC1 CKANA CK8051 EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ EQ G OG O G G G G GaaGa i Cu uu eu O G i c uu tu D G GOG G G G GAGGGG GG SS G G GG O G G G GOG GO G E G RE O E 9AH 9BH 9CH 9CH 9CH 9DH 9EH 9FH OA4H OA5H 0A6H OA7H OACH OADH OAEH OAFH OB4H OB5H OB6H OB7H OBCH OBDH OBEH OBFH OCOH OC1H OC2H O0C3H OC4H OCSH OD8H OD9H ODAH ODBH ODCH ODDH ODEH ODFH OE1H OE2H 0E3H OEAH OES5H 0E6H OE7H 0E8H OE9H OEAH OEBH OECH OEDH
13. ause a checksum error Record type 28H Directly Read from internal memory The general syntax for this record is the following 01H add H add L 28H number of bytes checksum Interpretation of this command reads number of bytes bytes from sequential memory locations of the internal data RAM memory starting from address add L using direct addressing the add H field is ignored but used in the checksum This implies that reads from addresses ranging from 80H to FFH will be done on SFRs rather than data memory Data is sent trough the serial link sequentially as it is read This record is not supported if 2 wire communication mode is selected Chapter 9 FIPSOC Boot Program Semiconductor Design Solutions Record type 40H Jump to address The general syntax for this record is the following 00H add H add L gt 40H lt checksum gt Interpretation of this command produces a direct jump to address add H 256 add LL Depending on the booting mode parts of the serial link circuitry may be powered down prior to jumping Record type 48H Return from subroutine The general syntax for this record is the following 00H add H add L 48H checksum Interpretation of this command executes a RET instruction which pops the address to jump to from the stack It is used when the record parsing program is used as a subroutine from an user application program fields add H and add L are ignore
14. d but used in the checksum 1 2 2 Extended record types and errors Record types 80H to FFH are available for command set extension If such a record type is parsed the program jumps to address FF2B where an appropriate parsing routine should be found Upon initialization a default error routine is written there This error routine is entered whenever a colon is not found at the begining of an HEX record a checksum is incorrect a record type is not recognized or any other parsing problem is detected This routine resets the GOE bit to place the whole programmable logic are in an idle mode and then keeps branching to the same address 1 2 8 Booting from SPI When boot is 0 and bootO is 1 during the reset sequence the extended HEX records are fetched from the SPI serial link The address port AD is also sampled upon reset and automatically configures several features of the SPI interface according to external user defined hardware settings 7 6 5 4 3 2 1 0 Master CPOL CPHA CK1 CKO OD Master bit 7 FIPSOC will act as an SPI master if this bit is set slave otherwise CPOL bit 6 Selects the SPI clock polarity refer to the SPI section of this user s manual CPHA bit 5 Selects the SPI clock phase refer to the SPI section of this user s manual CK1 and CKO bits 4 and 3 Select the SPI clock frequency as shown in table 2 refer to the SPI section of this user s manual
15. efore actually executing the jump If configured as a slave the program does the same except for that no initialization is performed other than placing an initial FFH in the outgoing shift register Bytes are echoed back as they arrive which can be checked out by the master to validate transfers 1 2 4 Booting from 2 wire When boot and bootO are both O during the reset sequence the extended HEX records are fetched from the 2 wire serial link The general purpose port GPORT is also sampled upon reset and automatically configures several features of the 2 wire interface according to external user defined hardware settings 7 6 5 4 3 2 1 0 Master Major device address Minor device address Master bit 7 FIPSOC will act as an 2 wire master if this bit is set slave otherwise Chapter 9 FIPSOC Boot Program Semiconductor Design Solutions Bits 6 0 These bits set the 7 bit logical device address The four most significant ones are said to be the major device address which is only dependent on the nature of the device itself The three least significant ones are the minor device address and are the ones that change among instances of the same device Bit 0 also configures the clock rate upon reset refer to the 2 wire section of this user s manual GPORT 0 2 wire clock frequency for frequency foc 16MHZz 0 fosc 16 1 MHz 1 fose 160 100 KHz Table 3 2 wire clock frequencies upon r
16. eset If configured as master the initialization sequence goes as follows step 1 The device waits until the 2 wire line is free and then it sends a START command to grab the line step 2 Once the line has been taken a WRITE command is sent to a device with address 1010000 If no acknowldege is received then FIPSOC sends a RESTART command without releasing the line and sends a WRITE command to the next device address 1010001 It keeps restarting and trying until a device answers step 3 Once a device answers by acknowledging the ninth bit two consecutive zeroes are sent to the line to specify the address to start reading from step 4 If no error is detected otherwise a STOP command is issued and the program goes back to step 1 a RESTART command is issued and a READ command is sent to the device address that answered before step 5 dummy FFH byte is sent through the line which provokes the first real data byte to be obtained from the serial memory After initialization the boot program keeps reading the incoming bytes and interpreting extended HEX records as the are completed Once a byte has been received the same byte is echoed back through the line to trigger the next read in the memory When a JUMP instruction is found record type 40H a STOP command is issued and the 2 wire communications system is switched off before actually executing the jump When a RETURN instruction is found record type 48H only
17. f a typical 16 MHz xtal is used Its reset state is latched during reset from bit 8 of the address port AD 8 Bits 7 6 4 3 2 and 1 keep their meaning after reset and are use to control their corresponding specific FIPSOC features at any time In particular the SPI or 2 wire interface could be independently used regardless of the boot mode 1 1 Booting from external parallel ROM This mode is entered when external pins boot and bootO are both tied to 1 during the reset sequence In this mode the 8051 is booted from a external parallel ROM as the 8051 standard device starting execution at position 0000 1 2 Booting from a serial link FIPSOC boots from a serial link when external pins boot and bootO are not both tied to 1 during the reset sequence In these three modes a boot program stored in a 512 byte internal ROM located at address 0000H is executed upon reset The program is essentially the same for the three modes except for the source the data is fetched from which is configured after sampling external pins boot and boot0 upon reset In mode 10 bootl 1 and boot0 0 data is received from the serial port typically from a PC in modes 00 booti 0 and boot0 0 and 01 bootl 0 and boot0 1 data is fetched from an 2 wire or SPI interface respectively typically from a serial flash or EEPROM 1 2 4 Extended HEX records After initialization the boot program keeps interpreting in real time configuration commands
18. for a previous transmission to be completed H f SCI is used then it waits for a serial byte to come prior to send R3 E If SPI is used then it waits for SPIF to be up If we are slave they should provoke a dummy transmission E before we send R3 if we are master we should provoke a dummy transmission before calling SENDBYTE This is E normally used for sending a group of bytes so each transmission is used to trigger the following Obviously the first transmission has to be provoked manually ck ckckck ck ck ck ck ck ck Ck Ck Ck kk kk Sk Sk kk kk kk ck ck ck ck kk kk kk kk Sk Sk Sk Sk Sk kc kc ko ko ckckckckcko k SENDBYTE MOV A BTREG JNB A BOOT1 SB SCI JNB A BOOTO SB SPI MOV A FFH 12C reads not supported RET SB SPI ACALL WAITAIT We wait for the previous transmission to end CINE A 80H RETERR Maybe we shouldn t check this out MOV CMBUF R3 We send R3 CLR A No error occurred RET SB SCI JNB RI SB SCI We wait for the previous transmission to end CLR RI We assume nothing is left CLR TI MOV SBUF R3 We send R3 Chapter 9 FIPSOC Boot Program 14 CLR A No error occurred RET Ck ck ck ck ck ck ck ck Ck Ck CK Ck Ok 0k ek kk kk kk kk kk kk kk Mk ke kk ko k ko kok ok Return with A FF error ck ck ck ck ck ce ke ck ke ck ck ke ck ck ck ck kk ck ck ck ck ck ck ck ck ck kk ck ck ck kk ko ko ck ko ko kc Mk ko ko RETERR MOV A FFH RET KKKKKKKKKKKKKKKKKKKKKK KK KK KKK KK KKK KKK KK KKKKKKKK
19. is echoed back through the line 1 3 The internal boot ROM and the auxiliary upper RAM When booting from a serial link is selected the internal boot ROM which stores the boot program that configures the serial link and parses the extended HEX records is enabled It is mapped at locations 0000 to 01FF and if enabled overwrites any other Chapter 9 FIPSOC Boot Program Semiconductor Design Solutions program memory that could mapped at these locations In these modes the auxiliary 256 bytes RAM block mapped at addresses FFOO to FFFF is also enabled bit 1 in RG2 set to one Locations FFFD through FFFF of this RAM block are modified by the direct read and write commands over the internal memory These commands are especially provided to dynamically read and write SFRs and use self modifying code to do direct accesses rather than indirect ones The normal interrupt vectors located at addresses 0003 000B and so on are also stored in ROM and permanently point to the upper auxiliary RAM to locations FF03 FFOB and so on No initialization is performed to these RAM locations Address FF2B is used for HEX command extension The program branches to this address when a record type between 80H and FFH is parsed This address is initialized with a jump to an error routine in case an extended record arrives before the extension code is downloaded This error routine is entered whenever a colon is not found at the begini
20. k Sk Sk kx Sk kx ko ko kockckckckckcko k Routine PROGMEM Inputs DPTR is ADD H ADD L A RO points to the first data byte in the buffer R1 is ADD L n R2 has the number of bytes to write H R4 is the record type Outputs A 0 if no error FF otherwise Modifies A R0 R1 R2 DPTR Programs any kind of memory CK CK CK CK Ok ke e kk ke kk ke kk kk CCS Sk ke ke Sk ke ke ke kk kk ck ck ck ck kk kk kv kv ko ko kckck kckckck PROGMEM CINE R2 0 PROGLOOP RET PROGLOOP MOV A RO CJNE R4 00H PROG1 Program external memory MOVX DPTR A SJMP GOPROG PROGI CINE R4 10H PROG2 Indirectly program internal memory MOV R1 A SJMP GOPROG PROG2 CINE R4 20H RETERR Directly program internal memory MOV DPTR SFMDCOD This is the self modifying code location MOV A 86H Hex code for MOV direct RO MOVX DPTR A NC DPTR MOV A R1 MOVX DPTR A Modify the code with the direct address NC DPTR MOV A 22H Hex code for MOVX DPTR A LCALL SFMDCOD GOPROG NC DPTR NC RO NC R1 DJNZ R2 PROGLOOP CLR A No error occurred RET KKKKKKKKKKKKKKKKKKKKKKKK kk kk kk kk ck kk kk kk kk Sk Sk Sk ke Sk ko k ko kckckckckckok Routine READMEM Inputs DPTR is ADD H ADD L RO points to the number of bytes to read R1 is ADD L R2 has the number of bytes to write E R4 is the record type Outputs A 0 if no error FF otherwise Modifies A R0 R1 R3 DPTR Reads any kind of memo
21. kk kk kk ke ke ko ko kokckck ok INIT SPI Uncomment GO ON ANL JNB MOV SCREG 4F3 A MASTER PORT1 FE MOV DDRP FEH MOV R3 3 ACALL TXBYTE MOV R3 0 ACALL TXBYTE ACALL TXBYTE SJMP GO_ON MOV CMBUF FF H GO_ON H H Clears dummy flags No more initialization required if slave Select First SPI device Bit 0 of general port as output the following if the next label is not GO ON CK CK CK CK kk ke kk kk ke kk ek kk kk kk kk kk kk Sk Sk Sk kx kx kx ko ko kockckoc ko kk Main loop for frame fetching and parsing CK CK CK CK Ck Seek Sk kk kk kk kk kk kk kk kk Sk Sk Sk Sk Sk kx Sk ko ko ck ck ck EEE EX GET FRAM Chapter 9 FIPSOC Boot Program MOV RO COLON ACALL GET BYTE JNZ ERROR MOV A R3 This is the main loop fetching records 11 i GF_LOOP CHKSUM CHKLOOP GOONT GOON2 GOON3 GOON4 MOV RO A INC RO ACALL GET_BYTE JNZ ERROR MOV A R3 ANL A 3FH MOV RO A ADD A 4 MOV R2 A INC RO ACALL GET_BYTE JNZ ERROR MOV A R3 MOV RO A DJNZ R2 GF LOOP MOV RO LENGTH MOV A 4 ADD A RO MOV R2 A MOV A RO INC RO ADD A RO DJNZ R2 CHKLOOP JNZ ERROR MOV MOV MOV MOV MOV MOV DPH ADD H DPL ADD L RO DATABUF R1 ADD L R2 LENGTH R4 REC_T MOV A R4 CJNE A 40H GOON1 ACALL ENDCOMS CLR A JMP A DPTR CJNE A 48H GOON2 ACALL ENDCOMS RET JNB A 7 GOON3 LJMP EXT CMD JNB A 3 GOON4 ACALL READMEM JNZ
22. ko XXE ko INIT I2C I2CLOOP I2CFOUND MOV A SCREG JB A BBUSY W4 ACALL START MOV R3 FIRST ACALL TXBYTE JNB A CCF IN JNB A ERR I2C INC R3 INC R3 ACALL RESTART SJMP I2CLOOP MOV A R3 ANL A FEH MOV R3 A MOV CMBUF 0 ACALL WAIT4IT BUSFRE DEV T I2C FOUND We probe the first device Next device R3 has now the device that answered We prepare for a READ command We send two zeroes as a 16 bit address CJNE R5 C9H STOPNGO MOV CMBUF 0 ACALL WAIT4IT CJNE R5 C9H STOPNGO ACALL RESTART ACALL TXBYTE We left the device address in R3 CJNE R5 C9H STOPNGO SJMP GO_ON ck ck ck ck ck ck ck ck kk Ck Ck 0k kk kk kk kk KKK KKK KKKKKKKKKKKKKKK RS232 Serial interface configuration ck ck ck ke ck ce ck ck kk ck Sk ck ke ck ck ke ck ck ck ck ck cock ck ck kk ck ck ck kk ck ko ck ko ko ke Mk ko ko INIT SCI MOV MOV MOV MOV MOV SCON 50H PCON 480H TCON 40H TMOD 420H TH1 F3H JB A BAUD GET_FRAM MOV TH1 FCH SJMP GET FRAM Mode 010 REN enable clear flags Double baud rate clear flags Start the Timer 1 Sets timer 41 in 8 bits reload mode 7243 for 3205 baud with a 16 MHz xtal 3205 baud if GPORT 0 is 1 10416 baud otherwise 252 for 10416 baud with a 16 MHz xtal ck ck ck ck ck ck ck ck ck ck ck kk kk kk Sk Sk kk Sk ke Sk kk kk ck ck ck ck ck ko ko ko kockck ck ko kk SPI configuration Ck ck ck ck ck ck ck ck Ck Ck CK CK Ck 0k kk kk kk kk Sk kk
23. mory The general syntax for this record is the following 01H add H add L 08H number of bytes checksum Interpretation of this command reads number of bytes bytes from sequential memory locations of the external data RAM memory starting from address add H 256 add L Data is sent trough the serial link sequentially as it is read This record is not supported if 2 wire communication mode is selected Record type OCH Read from code memory The general syntax for this record is the following 01H add H add L OCH number of bytes checksum Interpretation of this command reads number of bytes bytes from sequential memory locations of the external code ROM memory starting from address add H 256 add L Data is sent trough the serial link sequentially as it is read This record is not supported if 2 wire communication mode is selected Record type 10H Indirectly write to internal memory The general syntax for this record is the following number of bytes add H add L 10H byte lt checksum gt Interpretation of this command writes number of bytes bytes specified in the byte fields in SIDSA sequential memory locations of the internal data RAM memory starting from address add L using indirect addressing the add H field is ignored but used in the checksum This implies that writes to addresses ranging from 80H to FFH will be done on data memory rather than SF
24. n Solutions R3 for the first TXBYTE be 03 be 0B be 13 LJMP be 1B Maps the aux RAM memory for program and data This should MOV A ERROR ERROR 100H 100H MOVX DPTR A MOV A SCREG MOV A BTREG JNB A BOOT1 INIT_SCI JNB A BOOTO INIT_SPI JB A MASTER INIT I2C Strongly recommended Select the subsystem to If booti 0 then we are If boot0 0 then we are If we are I2C master be 23 KKEKKKKKKKKKKK KKK KKK KKK KK KK KKK KK KKK KKKKKKKKKK I2C configuration as slave KKKKKKKKKKKKKKKKKKKKKK KK KKK KKK ck ck ckckckckckckck ck ck ko kk INI2C SL MOV A SCREG Chapter 9 FIPSOC Boot Program ANL A 9 CONE A 9 INI2C_SL ACALL TXBY MOV A R5 CJNE A 89 INI2C_SL MOV CMBUF SJMP GET F TE FFH RAM Wait for BBUSY ID This is the acknowledge initialize booting from SCI booting from SPI 10 IDSA Semiconductor Design Solutions ck ck ck ck ck ck ck ck ck ck kk kk kk kk Sk kk kk kk kk ck ck ck ck ck ck ck ko kckck ck ck ko kck Send an STOP command and start again ck ck ck ck ck ck ck ck ck ck Ck Ck kk kk kk ke kk kk kk kk kk ck ck ck ck ckckckckck ck ko ko kk STOPNGO Uncommen ACALL I2CSTOP t the following if the next label is not INIT I2C SJMP INIT I2C KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK I2C configuration as master ck ck ck ck ck ce ck ck ck ck kk ke ck ck kk ck ck ck ck ck ck kk ck ckck ck ck ck ck ck ko ck ko
25. ng of an HEX record a checksum is incorrect a record type is not recognized or any other parsing problem is detected This routine resets the GOE bit to place the whole programmable logic are in an idle mode and then keeps branching to the same address 2 Boot program listing We provide here a complete assemble listing of the boot program IDSA ck ck ck ck ck ck ck ck ck ck ck Ck kk kk Sk kk kk kk kk ck ck ck ck ck ck kk ko ko ko ko ko k ck ck kckok KKEKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK KKKKKKKKKK FIPSOC boot program KKEKKKKKKKKKK KKKKKKKKKK KKKKKKKKKKKK KKKKKKKKKK By Julio Faura and KKKKKKKKKKKK KKKKKKKKKK Ignacio Lacadena KKEKKKKKKKKKK KKKKKKKKKK KKKKKKKKKKKK KR KKK KEK C SIDSA 1998 ck ck ck ck ck ck ck ck ck ck Ck kk kk kk kk kk kk KKKKKKKKKKKKKKKKKKKKKK ck ck ck ck ck ck ck ck ck kk KKEKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK Semiconductor Design Solutions Ck ck ck ck ck ck ck ck Ck Ck CK CK Ck kk kk kk kk kk kk KKK KKK KKK KKK KKK KKK KKK KKK KKK KKKKKKKKKKK Kk Rooke ka FIPSOC SFRs symbol definition KKKKKKKKKKKKKKKKK KKKKKKKKKKKKKKKKKKKKKKK KKK KKK KKK KKK Sk Sk e Sk kk ke KKK KK KK KKKKKKKKKKKKKK SFRS in the standard 8051 xeeee SP EQU 081H DPL EQU 082H DPH EQU 083H PCON EQU 087H TCON EQU 088H TMOD EQU 089H TLO EQU 08AH TLI EQU 08BH THO EQU 08CH THI EQU 08DH SCON EQU 098H SBUF EQU 099H E EQU 0A8H P EQU OB8H PSW EQU ODOH Definitions for bi
26. ry Kk ck ck ck ck ke kk ck ck ck ck eee ee ee ee kk ck ck ck ckockckckckckckockckckckockckckckckokckockckockckckckokckck kckok READMEM MOV R2 RO CLR A CINE R2 0 READLOOP RET READLOOP XCH A R3 CINE R4 08H READ1 Read external memory MOVX A DPTR SJMP GOREAD RO equals DATABUF Chapter 9 FIPSOC Boot Program 13 ID S A Semiconductor Design Solutions READ1 CINE R4 0CH READ2 Read code CLR A MOVC A A DPTR SJMP GOREAD READ2 CINE R4 18H READ3 Indirectly read internal memory MOV A R1 SJMP GOREAD READ3 CJNE R4 28H RETERR Directly read internal memory MOV DPTR SFMDCOD MOV A E5H Hex code for MOV A direct MOVX DPTR A NC DPTR MOV A R1 MOVX DPTR A NC DPTR MOV A 22H Hex code for RET MOVX DPTR A LCALL SFMDCOD Now the data is in A GOREAD XCH A R3 ADD A R3 PUSH A We save the sum ACALL SENDBYTE We send R3 JNZ RETERR POP A We restore the sum INC DPTR INC R1 DJNZ R2 READLOOP Now has the sum and we must calculate and send the checksum CPL A Calculate checksum INC A twas 2 s complement MOV R3 A Uncomment the following if the next routine is not SENDBYTE E ACALL SENDBYTE Send checksum RET CCS ek Sk Sk kk ke kk kk kk S e ke ke kk kk kk kk ck kk kk Mk kv kv ko ko kockck ck EEK Routine SENDBYTE Inputs R3 is the byte to send Outputs A 0 if no error FF otherwise Modifies A R5 Sends a byte no matter where thru It waits
27. similar to Intel s HEX records The syntax of these records is as follows number of bytes address low data byte checksum address high record type Each field in a record is a single byte including a leading 3AH the ASCII code of the colon The number of bytes field only refer to the data bytes represented in brackets in the syntax above This Chapter 9 FIPSOC Boot Program Semiconductor Design Solutions way a zero number of bytes field is possible and the checksum field will closely follow the record type field The checksum field is a byte such as the following formula is satisfied number of bytes address high address low record type data byte mod 256 checksum 0 Note that the leading colon ASCII 3AH is not included in the checksum calculation Up to nine record types are currently supported They are explained below Record type 00H Write to external memory The general syntax for this record is the following number of bytes add H add L 00H byte lt checksum gt Interpretation of this command writes number of bytes bytes specified in the byte fields in sequential memory locations of the external data RAM memory starting from address add H 256 add L The number of bytes that can be written is limited to 63 and an attempt to write more than that will in general cause a checksum error Record type OSH Read from external me
28. t addressing RI EQU 098H Receiver interrupt flag TI EQU 099H Transmitter interrupt flag RB8 EQU 09AH 9th bit received TB8 EQU 09BH 9th bit sent REN EQU 09CH Reception Enable SM2 EQU 09DH SM lt 2 0 gt Mode specifier SM1 EQU 09EH SMO EQU 09FH KKKKKKKKKKKKKKKKK Internal ports definitions ckckckckckckckckckckckck kc k kk kk PORTO EQU 80H PORT1 EQU 90H PORT2 EQU OAOH PORT3 EQU OBOH Definitions for bit addressing RXD EQU OBOH USART Receiver TXD EQU OB1H USART Transmitter NINTO EQU OB2H External interrupt input 0 NINT1 EQU OB3H External interrupt input 1 TO EQU OB4H Timer 0 external input TA EQU OB5H Timer 1 external input NWR EQU OB6H External data memory write strobe NRD EQU 0B7H External data memory read strobe active low active low active low active low KKKKKKKKKKKKKKK FIPSOC specific SFRs definitions KKKKKKKKKKKKKKKKKK The following registers are not present in the standard 8051 Therefore some most macro assemblers and compilers may not admit them as they are not legal direct memory locations special function registers in the standard device To avoid this problem they should be assembled as an external module and exported with Chapter 9 FIPSOC Boot Program eu GLOBAL clauses from the main module IDSA Semiconductor Design Solutions while they should be imported with EXTERNAL clauses This norm
29. uring the reset sequence SCIE bit 4 Serial Communication Interrupt Enable It enables the interrupt of the serial communication system Its reset value is zero GOE bit 3 Global Output Enable When reset it disables every output of every DMC and places all the IO pads in input state Its reset value is zero OD bit 2 Open Drain The general purpose port GPORT pins behave as open drain when configured as outputs when this bit is set as normal CMOS outputs otherwise Its reset state depends on the boot mode if booting from SPI BOOTI1 0 and BOOTO 1 then OD is initialized from bit 10 of the address port AD 10 if booting from 2 wire BOOTIZBOOTO 0 OD is initialized to 1 otherwise OD is initialized to zero normal CMOS outputs although all bits in the data direction register DDRP are initialized to 1 thus configuring all port pins as inputs SIDSA IREN bit 1 Internal ROM Enable When set the internal ROM where the boot program is located is mapped at locations 0000 to 001FF The reset state of this bit is the OR function of the external BOOT mode pins that is the internal boot ROM is enabled when booting from a serial link and disabled if booting from external parallel ROM Baud bit 0 SCI boot baud rate This bit selects the initial baud rate of the SCI port when booting from it if set f 4992 is selected 3205 1 baud if a typical 16 MHz xtal is used f 1536 otherwise 10416 6 baud i

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