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MPC850SARDB User`s Manual

1. gen 021 MOTA 031 M SNIH2 lt Y ven lt T 1 TA aM B MOTA 037 vL A 9 dE Fas 5031 N LLV Ee n T JT ms HS le G mr RI d g k re Z0Xu 5 u 00 L in 7 8 For 5 135 YIU3A 2228 Im SUL HE NET R UMdeSn la gsn T AC Dr lt yolx3 i d v E L m t oxa d zin az 044515 L AS AENIONI A z ik 2 gt 4 mm mm td z Ln Y N Q 5 dv s L 9 dxugsr 7 N39 3000 H T 8 4401 92 8D 1 g NO 8S male ES C y r rt 013 D Gel L 114851108 Go to www freescale com For More Information On This Product N 64 FreagscalsoSgmieonductgr na MPC850SARDB Schematics 2 C CR x did2S3 MHI 541 1114 Say ONL1300230 33018 33138 AN UNN DN 8 40 E 133 5 9N3 A20 80S0Y4058JdW EE JNI V DND 20 2 01 02 EN 3110 1 224 300188 UND 20 anto mp 180 IES IO d32vdS AA 3002 Nd 2009 ONI E dm Y JON puodo 96 20019 ND m Ant ANTO EEA 9 0S8JdW UND EEJ T e an Jnro 3070 2 Wa 7 2
2. Release 0 1 For More information On This Product Go to www freescale com CO MPC850SARDB Schematics fr FreagscalsoSgmieonductgr doa URU DI up e E 2 OUVOS U3HIOA 00078 INJ KC 40 7 LHS DNJ AH 13r0td ont gr DR GA eel ser JNI Y 108010W EL eer be Fu Release 0 1 For More Information On This Product Go to www freescale com UNS a 4 e 8 1 4 IND oe a u ES 7 ZI a L J gt a ng 9 59 gert rv ia 0 Ly 19 od H s 09 6 SY 86 za A worm C 96 SEN s s 4 05 10A88 97 gay TI zone z SE SE 5122 bi EE 553 1E 5222 lt gt ha 52 18 u 12 Es 283 2 1 a G 2 a 8 LT i 9l ST dag m E ES 4 ZL T 0050 yasa 01 9m 6 T s ge t m 9 B 7 E E T d ZTA 2 T Wt Sa AC 2 ESER 2 3 55 00 66 x diuJS3 NHI
3. S d 133NN02 QHVOS H3HLOW 219 13138 AN UNN ONS mp 40 d 33HS 9N3 A20 SOSCV 40592d N Jdf td lt I 67 MO MPC850SARDB Schematics Y Frere sesh ROHS Rata MO lt gt Wa Gre Ef t E 3 Es LC 1684 52 GE lt Sid GE P 91 6184 D 11 zax ES 3 CO or 6 pn T e o 2 S mw Peay 2o Ud La K L 2 T DL 1 E 2 g For More Information On This Product Go to www freescale com N Release 0 1 FreagscalsoSgmieonduictgr na MPC850SARDB Schematics un MOTOROLA REV ENG RESET 7 PCMCIA amp H TN U Z 5 E leF lefelzil a e simin le lolo lalo ls ela en ln e is lola la ls le eir e Je e Q Z salto 4 Ele el el Ll 2266 kalel fele el il ISIS lol alo E Ek D I SEE kl ca EL EI Ol BBs ReB56BEEEEDEEIERSS SE Sole o l le F n le k lE k n leck B az ini iin boEEBEERBIABEGO Selz SIR SS l B ES EP IP a B fe ea B ls sz e Liz G s es z 15 B BIB EN B
4. PA9 PA9 E1 T1 L1TXDA PA8 PA8 E1 T1 L1RXDA C13 VO X PC13 SAR PHY READ PA7 VO X PA7 E1 T1 LTRCLKA PB31 E1 T1 Chip Select 26 P PC14 SAR PHY WRITE PC12 SAR PHY UTOPIA TXCAV PA5 E1 T1 L1TCLKA ETHTCK 1 0 X PA4 ETHTCK TOUT2 52 Release 0 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonductgr dna Support Information TABLE 5 14 PX3 PM3 Interconnect Signals Differences Pin No Signal Name Attribute Description E TENA PB18 E TENA PB19 PB19 SAR PHY ADO PC4 PC4 E1 T1 L1RSYNCA C5 P 1 0 X PC5 E1 T1 L1TSYNCA 100 USBTXN 1 0 X PC6 USBTXN SAR PHY AD6 TABLE 5 15 PX4 PM4 Interconnect Signals Difference 5 1 5 MPC8XXFADS s P8 Serial Ports Expansion Connector P8 is a 96 pin 90 DIN 41612 connector which allows for convenient expansion of the MPC s serial ports Although this connector resides on the mother board it is documented here this since it s signal assign ment is unique per each MPC8XX Release O 1 53 For More information On This Product Go to www freescale com 54 FreagscalsoSgmieonductgr dna Support Information Note The contents of TABLE 5 16 MPC8XXFADS s P8 Inter connect Signals below might conflict with MPCSXXFADS s schematic page 14 This since that the schematic page is named in MPC821 860 terms In such case this table overrides TABLE 5 1
5. Not Connected Release O 1 For More Information On This Product Go to www freescale com Frodo ae gia Support Information TABLE 5 16 MPC8XXFADS s P8 Interconnect Signals Pin No Signal Name Attribute Description C25 VCC C26 PD3 1 0 PD3 UTOPIA SOC See PM3 103 1 0 C27 VPPIN 12V input for PCMCIA flash programming Parallel to P7 of the ES MPC8XXFADS C28 C29 GND C30 PD4 PD4 UTOPIA Data bit 7 See PM3 106 C31 GND C32 PD5 PD5 UTOPIA Data bit 6 See PM3 107 a When connected to this board the MPC850SARDB TABLE 5 17 MPC850SARDB Connections to the SAR PHY Tool on page 57 bellow shows the connec tions paths from P8 on the MPC8xxFADS M B to the MPC850SAR D B TABLE 5 17 MPC850SARDB Connections to the SAR PHY Tool E AY EE Lm ees H T ECH Pes TERN H T ET p Lees EIER T Lee v 3 LL me p INN ET PA12 PX3 11 PM3 11 A4 InfraRed TxD2 on MB 5 11 42 PMS PD3 42 B11 RS232 2 TxD2 on MB 5 11 42 PMS PD3 5 A2 Ethernet TxD2 on MB 5 11 42 Release O 1 57 For More Information On This Product Go to www freescale com 58 FreagscalsoSgmieonduictgr na Support Information TABLE 5 17 MPC850SARDB Connections to the SAR PHY Tool LL ees recs ne Troc PORT B 22 44 10 RS232 2 DTR2 SAR PHY ALE 44 97 44 97 220 5 PORT C a 2
6. Release 0 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonductgr na Support Information TABLE 5 8 PM1 Interconnect Signals Pin No Signal Name Attribute Description SDRMCS UO L In fact MPC s chip select line 4 Used as chip select for the Synchronous Dram Pulled up on the M B When the SDRAM is disabled via BCSR may be used off board via the expansion connectors GPL3 O D GN GPL2 General Purpose Line 2 for UPMA or UPMB Used with the SDRAM as a CAS signal GND BSWE3 UPM Byte Select 3 or GPCM Write Enable 3 or PCMCIA WE Selects the LSB within a word for the SDRAM EDO DRAM and Flash Simm or qualifies Writes for the PC Card UPM Byte Select 2 GPCM Write Enable 2 or PCMCIA OE Selects the offset 2 Byte within a word for the SDRAM EDO DRAM and Flash Simm or open data buffers for read from PC Card UPM Byte Select 1 or GPCM Write Enable1 or PCMCIA UO Write Selects the offset 1 Byte within a word for the SDRAM EDO DRAM and Flash Simm or functions as I O Write for the PCMCIA channel See pin 55 The duality due to separation of BS 0 3 A from VVE 0 3 BS 0 3 B with other members of the 8xx family UPM Byte Select or GPCM Write Enable or PCMCIA I O Read Selects the offset 0 Byte within a word for the SDRAM EDO DRAM and Flash Simm or functions as I O Reads from PC Card 64 GND 65 EDOOE O L n fact UPMA
7. Release 0 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr na Support Information TABLE 5 17 MPC850SARDB Connections to the SAR PHY Tool v s necne me ne rons a7 Tura 1 roe necne e om urormes 522 MPC850SARDB Part List In this section the MPC850SARDB bill of material is listed according to their reference designation TABLE 5 18 MPC850SARDB Part List C1 C2 C3 C4 C5 C8 C9 C10 Capacitor 0 1uF 16V 10 SMD AVX 0603YC104KAT2A C11 C13 C15 C16 C17 C19 C20 0603 Ceramic C21 C22 C23 C24 C25 C30 C32 C33 C7 C29 C31 Capacitor 10uF 20V 10 SMD SIEMENS B45196 H5106 K309 Size C Tantalum C12 Capacitor 100uF 10V 10 SMD SIEMENS B45196 H2107 K10 Size D Tantalum C14 Capacitor 1uF 25V 10 SMD SIEMENS B45196 H5105 K109 Size A Tantalum C18 C26 Capacitor 10pF 50V 10 COG AVX AV12065A100KATOOJ SMD 1206 Ceramic C27 Capacitor 4700pF 50V 10 AVX AV12065C 472K A700J SMD 1206 Ceramic C28 Capacitor 0 68uF 20V 10 SIEMENS B45196 E4684 K109 SMD Size A Tantalum Release O 1 59 For More Information On This Product Go to www freescale com gia Support Information TABLE 5 18 MPC850SARDB Part List Reference Designation Part Description Manufacturer Part D1D2 Diode SMD Motorola LL4004G H1 H2 H3 Gnd Bridge Gold Plated PRECIDIP
8. FreagscalsoSgmieonduictgr dna Support Information TABLE 5 18 MPC850SARDB Part List Reference Designation Part Description Manufacturer Part RN1 RN2 RN3 RN4 RN5 Resistor Network 75 Q 596 4 DALE CRA06S0803750JR resistors 8 pin T1 T2 T8 T4 T5 Transistor TMOS Dual 3A Motorola MMDFSNOSHD U1 4 MHz Clock generator 3 3V M TRON MH14FAD 3 3V 4 00MHz CMOS levels U2 MPC850 16 X 16 256 pin BGA Motorola XPC850SRZT50A U3 Quad Low Voltage CMOS AND Motorola 74LCX08D Gate U6 U9 U7 8 gt 1 Mux with tri state output Motorola 74ACT251D USB transceiver PHILIPS PDIUSBP11AD Quad CMOS buffer with individual Motorola 74ACT125D Output Enable Voltage level detector Range Seiko S 8051HN CD X 1 795V to 2 005V O D output High Speed CMOS QuickSwitch Quality QS3244D 8 bit Bus Switches SOIC Semiconductor Crystal resonator 32 768 KHz RALTRON RSM 200 32 768 KHZ Frequency tolerance 30 ppm Drive level 10uW Max Shunt capacitance 2pF Max Load capacitance 12 5pF Max Equivalent Series Resistance 35 KO Max 14 pin PC Socket SMD PRECIDIP 110 91 314 41 105 256 pin 16 X 16 BGA ZIF Socket ENPLUS BGA256 441 1 27 05 Release O 1 61 For More Information On This Product Go to www freescale com 62 FreagscalsoSgmieonductgr na MPC850SARDB Schematics 6 MPC850SARDB Schematics The schematics of the MPC850SARDB are shown bellow Fo
9. MPC850SAR 50 MHz 4 GBytes Internal 64 MByte External Operating temperature Storage temperature Relative humidity Dimensions Length Width Thickness 09C 30 C 25 C to 85 C 5 to 90 non condensing 5 87 149 mm 4 37 111 mm 0 063 1 6 mm a This is the maximum contiguous block of memory that may be accessed It may reside however anywhere within the 4 GBytes of addressing space 1 5 MPC850SARDB Features MPC850 running upto 50 MHz USB Port with shutdown option BCSR controlled Support for both type A and Type B USB connectors USB Port Speed control BCSR driven UA 5V supply for USB port BCSR controlled O Selectable KAPWR source 3 3V or externally supplied 4 Selectable clock source 32768Hz crystal resonator or 4 MHz Clock generator On Board Expansion connectors including all MPC pins and MPC8XXFADS control sta tus signals 4 On Board High Density Logic Analyzer connectors supporting fast connection to HP 16500 logic analyzer SAR PHY Tool Support A May be easily changed to any 3 3V powered oscillator oscillating in 3 5 MHz frequency range 2 Release O 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonductgr dna General Information FIGURE 1 1 MPC850SARDB Block Diagram Logic Analyzer Conn MOTHER BOARD amp EXPANSION CONN USB Type B USB Type A 5V to 3 3V Converter
10. PD11 1 0 X MPC s PD11 Appears also at P8 of the M B as UTOPIA RXENB for the SAR PHY tool PD12 1 0 X MPC850 s PD12 Appears also at P8 of the M B as UTOPIA Data Bus bit 3 for the SAR PHY tool PD13 1 0 X MPC850 s PD13 Appears also at P8 of the M B as UTOPIA Data Bus bit 2 for the SAR PHY tool PD14 1 0 X MPC850 s PD14 Appears also at P8 of the M B as UTOPIA Data Bus bit 1 for the SAR PHY tool PD15 1 0 X MPC850 s PD15 Appears also at P8 of the M B as UTOPIA Data Bus bit 0 for the SAR PHY tool GND 124 ETHLOOP LH Ethernet Transceiver Diagnostic Loop Back Control Generated by BCSR4 See TABLE 4 23 BCSR4 Description on page 57 of the MPC8XXFADS User s Manual Not used on this D B just passed on to the expansion connectors Release 0 1 43 For More Information On This Product Go to www freescale com 44 Support Information TABLE 5 10 PM3 Interconnect Signals Pin No Signal Name Attribute Description TPFLDL Twisted Pair Full Duplex Allows for full duplex operation over the Ethernet Twisted Pair channel See TABLE 4 23 BCSR4 Description on page 57 of the MPC8XXFADS User s Manual Not used on this D B just passed on to the expansion connectors TPSQEL Twisted Pair Signal Quality Error Test Enable See TABLE 4 23 BCSR4 Description on page 57 of the MPC8XXFADS User s Manual Not used on this D B just passed on to the expansion conne
11. MPC850SARDB Connections to the SAR PHY Tool MPC850SARDB Part List For More Information On This Product Go to www freescale com FIGURE 1 1 FIGURE 2 1 FIGURE 2 2 FIGURE 2 3 FIGURE 2 4 FIGURE 2 5 FIGURE 4 1 FIGURE 5 2 Frere sesh ROHS Ma na LIST OF FIGURES MPC850SARDB Block Diagram MPC850SARDB Top Side Part Location diagram U1 Power Sources Power On Reset Source Selection Keep Alive Power Source Selection PA4 Function Selection SCC2 Connection Scheme Expansion Connectors Mechanical Assembly For More Information On This Product Go to www freescale com CO NNO O10 N Release 0 1 FreagscalsoSgmieonduictgr dna General Information 1 General Information 1 1 Introduction This document is the operation guide for the MPC8XXFADS Daughter Board for the MPC850 named the MPC850SARDB The daughter board holds the evaluated MPC850SAR along with some necessary logic which is required to be in the nearest vicinity of the MPC850SAR as well as peripherals that are dedicated to the MPC850SAR and are not required for any other member of the MPC8XX family The daughter board has 2 sets of matching connectors one on the print side and one on the component side Those on the print side connect to a matching set found on the MPC8XXFADS while those on the component side are to serve hardware expansion via a dedicated adaptor In addition a set of logic analyzer connector is featured matchin
12. data line USB positive differential data line 2 850DB Ground plane 5e1 3 PM1 PM4 Mother Board Connectors These connectors which connect to their mates on the motherboard hence their name are 140 pin inter board male connectors made by Molex These connectors are arranged in a quadratic shape this to provide the shortest PCB routes as possible As can be seen from their mechanical assembly shown in FIGURE 5 1 Motherboard Connectors Mechanical Assembly below the connectors are not set in a perfect symmetric shape this to prevent the possibility of daughter board s miss insertion Release O 1 23 For More Information On This Product Go to www freescale com FreagscalsoSgmieonductgr dna Support Information FIGURE 5 1 Motherboard Connectors Mechanical AssembiyA B 46 3 a RR dl Ke K PM4 i z bis vss Uc 17 49 zi 30 19 R l 93 98 The motherboard connectors s signals are described in TABLE 5 8 PM1 Interconnect Signals on page 25 TABLE 5 9 PM2 Interconnect Signals on page 30 TABLE 5 10 PM3 Interconnect Signals on page A Top View from Component side B All measures are in mm 24 Release O 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr dna Support Information 38 and TABLE 5 11 PM4 Interconnect Signals on page 45 TABLE 5 8 PM1 Interconnect Si
13. on page 49 of the MPC8XXFADS User s Manual 83 N C Release O 1 41 For More Information On This Product Go to www freescale com 42 FreagscalsoSgmieonductgr dna Support Information TABLE 5 10 PM3 Interconnect Signals Pin No Signal Name Attribute Description USBTXP X Infra Red Enable Connected to BCSR1 See TABLE 4 10 BCSR1 Description on page 49 of the MPC8XXFADS User s Manual USBTXP SAR PHY AD2 USB Positive transmit signal differential also MPC PI O port C 7 Appears also at P8 of the M B as SAR PHY Address Data Line 2 to support the SAR PHY tool MPC PI O port A 5 SAR PHY L1TCLKA Appears also at P8 as E1 T1 L1TCLKA JTAG port Test Mode Select input Used to select test through the JTAG port Pulled up on the M B but otherwise not used on the FADS MPC port B 16 SAR PHY AD4 Appears also at P8 of the Mi B as SAR PHY Address Data Line 4 for the SAR PHY tool JTAG port Reset Pulled down on the M B with a zero ohm resistor so that the JTAG logic is constantly reset Otherwise unused on the FADS MPC PI O port C 12 SAR PHY TXCAV Appears also at P8 of the M B as UTOPIA TXCAV for the SAR PHY tool RSDTR2 RS232 port 1 Enable Connected to BCSR1 See TABLE 4 10 BCSR1 Description on page 49 in the MPC8XXFADS User s Manual MPC PI O port B 22 SAR PHY ALE Appears also at P8 of the M B as ALE for the SAR PHY tool see pin no 44 MPC PI
14. 29 For More information On This Product Go to www freescale com FreagscalsoSgmieonduictgr dna Support Information TABLE 5 8 PM1 Interconnect Signals Attribute Description MPCs Address line 22 MPCs Address line 23 Signal Name TABLE 5 9 Attribute PM2 Interconnect Signals Description 10V output from voltage doubler Used to switch TMOS gates on both mother and daughter boards Should not be used for any other purpose DSDI DSDI TDI Debug Port Serial Data Input or JTAG port serial Data Input Used on the FADS as debug port serial data driven by the debug port controller If the ADI bundle is not connected to the FADS may be driven by external debug JTAG port controller 8 GND 30 Release O 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr dna Support Information TABLE 5 9 PM2 Interconnect Signals Pin No Signal Name Attribute Description DSCK TCK Debug Port Serial Clock input or JTAG port serial clock input Used on the FADS as debug port serial clock driven by the debug port controller If the ADI bundle is not connected to the FADS may be driven by an external debug JTAG port controller DSDO TDO Debug Port Serial Data Output or JTAG port Data Output Used on the FADS as debug port serial data If the ADI bundle is not connected to the FADS may be used by an
15. For More Information On This Product Go to www freescale com 34 FreagscalsoSgmieonduictgr dna Support Information TABLE 5 9 PM2 Interconnect Signals Pin No Signal Name Attribute Description MPC Timer Expired Not used on the FADS This signal is PCMCIA slot B wait signal Pulled up but otherwise not used on the FADS MODCK2 See pin 48 The duality since the MPC850 s PCMCIA port B is connected to PCMCIA port on the M B normally residing on PCMCIA port A of the MPC8XXs SRESET MPC Soft Reset Driven by M B logic and may be driven by off board logic with Open Drain gate only Power On reset for the MPC Not used on the FADS HRESET MPC Hard Reset Driven by M B logic and may be driven by off board logic vvith Open Drain gate only GND RSTCNF Hard Reset Configuration input Driven by M B logic during Hard Reset to the MPC to signal the MPC that it should sample Hard Reset configuration from the data bus Main battery power on reset Generated by M B logic as a result of main 3 3V bus going through power up or power down Drives M B s logic as well either HARD RESET or Power On reset to the MPC 89 GND 90 91 92 WAIT UO L See pin 70 The duality since the MPC850 s PCMCIA port B is connected to PCMCIA port on the M B normally residing on PCMCIA port A of the MPC8XXs Release O 1 For More Information On This Product Go
16. IRD EN bitin BCSRT is asserted and both ETH EN and RS ENZ bits in the same register are inactive See 4 9 2 Infra Red Port on page 41 and TABLE 4 10 BCSR1 Description on page 49 of MPC8XXFADS User s Manual 4 5 4 RS232 Ports There may be 2 RS232 ports with this application RS232 Port 1 of the MPC8XXFADS is connected to SMC1 of the MPC850 while RS232 Port 2 of the FADS is optionally connected to SCC2 of the MPC850 this when the RS_EN2 bit in BCSRT is asserted while both ETH EN and IRD EN bits in the same register are inactive Both ports may be enabled disabled at any time via BCSR1 See 4 9 3 RS232 Ports on page 42 and TABLE 4 10 BCSR1 Description on page 49 of the MPC8XXFADS NOTE RS232 Port 2 DTR signal is used as an ALE signal on the SAR PHY board see table 4 1 so when the user con figures one of the ATM modules on the SAR PHY board RS232 Port 2 must be disabled After configuration is done the port can be used concurrently vvith the SAR PHY board 4 6 E1 T1 Port An E1 T1 channel can be implemented when using the SAR PHY board The channel is implemented with the serial interface TDM channel of the MPC850x The E1 T1 channel on the SAR PHY board is config ured using the SPI Port NOTE Release 0 1 13 For More Information On This Product Go to www freescale com 14 FreagscalsoSgmieonduictgr dna Functional Description One of the options when using the E1 T1 port on the SAR PHY board is to
17. Infra Red RS232 1 RS232 2 PCMCIA UTOPIA Sum RxD2 TxD2 L1TxDA L1RxDA L1RCLKA L1TCLKA TOUT2 E1 T1CS SPI CLK SPI IN SPI OUT miz x x ULU a a ES To BINPAK RxCAV PHYWR 16 Release O 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr Functional Description TABLE 4 1 UO Signals Functionality Assignments with the SAR PHY Board PCMCIA UTOPIA E1 T1 Infra Red L1TSYNCA L1RSYNCA Release O 1 For More Information On This Product Go to www freescale com 17 FreagscalsoSgmieonduictgr dna Support Information 5 Support Information In this chapter all information needed for support maintenance and connectivity to the MPC850SARDB is provided 5 1 Interconnect Signals The MPC850SARDB interconnects with external devices via the following set of connectors 1 P1 P2 P5 P6 P7 and P8 Logic Analyzer connectors 2 P3 and P4 USB connectors 3 PM1 PM2 PM3 and PM4 Mother Board Connectors 4 PX1 PX2 PX3 8 PX4 Expansion Connectors 5 MPCEXXFADS s P8 Serial Ports Expansion Connector 5 1 1 P1 P2 P5 P6 P7 and P8 Logic Analyzer Connectors These connectors are 38 pin receptacle MICTOR connectors made by AMP Each connector connects to a dedicated adaptor for HP 16500 series of logic analyzer which interconnects to two
18. P port C 4 SAR PHY L1RSYNCA Appears also at P8 of the M B as E1 T1 L1RSYNCA for the SAR PHY tool RS232 port 2 Enable Generated by BCSR1 Used in conjunction with IRD EN and ETH EN to select and enable a multiplexer over RXD2 signal See TABLE 4 10 BCSR1 Description on page 49 of the M B and FIGURE 4 1 SCC2 Connection Scheme on page 12 Release O 1 For More Information On This Product Go to www freescale com Support Information TABLE 5 10 PM3 Interconnect Signals Pin No Signal Name Attribute Description MPC s PD3 Appears also at P8 of the M B as UTOPIA SOC for the SAR PHY tool 103 104 105 106 MPC850 s PD4 Appears also at P8 of the M B as UTOPIA Data Bus bit 7 for the SAR PHY tool 107 MPC850 s PD5 Appears also at P8 of the M B as UTOPIA Data Bus bit 6 for the SAR PHY tool 108 PD6 VDOEXTCK 1 0 X MPC850 s PD6 Appears also at P8 of the M B as UTOPIA Data Bus bit 5 for the SAR PHY tool VDORST LX Reserved Unused with this daughter board X Reserved Unused with this daughter board PD7 1 0 X MPC850 s PD7 Appears also at P8 of the M B as UTOPIA Data Bus bit 4 for the SAR PHY tool PD8 1 0 X See pin no 8 PD9 1 0 X MPC s PD9 Appears also at P8 of the M B as UTOPIA CLOCK for the SAR PHY tool PD10 1 0 X MPC s PD10 Appears also at P8 of the M B as UTOPIA TXENB for the SAR PHY tool
19. Pin No Signal Name Attribute Description IP B7 PTR AT3 PCMCIA slot B Input Port 7 or Program Trace instruction fetch indication or Address Type 3 Configured as IP B7 to function as PC Card Ready indication If the PCMCIA channel is disabled may be configured to alternate function IP BO IWPO VFLSO PCMCIA slot B Input Port O or Instruction VVatchpoint 0 or Visible history Flushes Status 0 Configured as IP BO to function as PC Card s Voltage Sense 1 If the PCMCIA channel is disabled may be configured to alternate function SPKROUT KR IRQ4 SPKROUT Kill Reservation input or Interrupt Request 4 input or PCMCIA Speaker Output Configured SPKROUT If the PCMCIA channel is disabled may be configured to alternate function IP B1 IWP1 VFLS1 PCMCIA slot B Input Port 1 or Instruction Watchpoint 1 or Visible history Flushes Status 1 Configured as IP B1 to function as PC Card Voltage Sense 2 If the PCMCIA channel is disabled may be configured to alternate function IP B5 LWP1 VF1 PCMCIA slot B Input Port 5 or Load Store Watch Point 1 or Visible Instruction Queue Flushes Status 1 Configured as IP B5 to function as Battery Voltage Detect 2 If the PCMCIA channel is disabled may be configured to alternate function 45 GND ALE B DSCK AT1 Address Latch Enable for PCMCIA slot B or Debug Serial Clock or Address Type 1 Configured as ALE B If the PCMCIA channel is disabled may be
20. Signals SCC2 Rx CLOCKS Ethernet Rx Infra Red Rx 1 6 MPC850SARDB Rev ENG to MPC850FADSDB Rev PILOT Changes Changes were made to support the SAR PHY tool board on P8 on the MPC8xxFADS board Due to these changes the DB no longer supports any other tool which was previously used with earlier revisions This is due to re routing of the I O signals on the DB Release 0 1 For More information On This Product Go to www freescale com FreagscalsoSgmieonductgr Hardware Preparation and Installation 2 Hardware Preparation and Installation 201 INTRODUCTION This chapter provides unpacking instructions hardware preparation and installation instructions for the MPC850SARDB 2 2 UNPACKING INSTRUCTIONS NOTE If the shipping carton is damaged upon receipt request carrier s agent to be present during unpacking and in spection of equipment Unpack equipment from shipping carton Refer to packing list and verify that all items are present Save packing material for storing and reshipping of equipment CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUIT RY STATIC DISCHARGE CAN DAMAGE CIRCUITS 2 3 HARDWARE PREPARATION To select the desired configuration and ensure proper operation of the MPC850SARDB board changes of the jumpers settings may be required before installation The location of the jumpers LEDs and connectors is illustrated in FIGURE 2 1 MPC850SARDB Top Side Part Location dia
21. external debug JTAG port controllers In fact IP B2 IOIS16 AT2 PCMCIA slot B Input Port 2 or PCMCIA 16 bit I O capability indication or Address Type 2 Configured as IP B2 and functions as PC Card s Write Protect signal If the PCMCIA channel is disabled may be configured to alternate function IP B3 IVVP2 VF2 PCMCIA slot B Input Port 3 or Instruction Watch Point 2 or Visible Instruction Queue Flushes Status 2 Configured as IP B3 to function as PC Card Detect 2 signal If the PCMCIA channel is disabled may be configured to alternate function IP B4 LVVPO VFO PCMCIA slot B Input Port 4 or Data Watch Point 0 or Visible Instruction Queue Flushes Status 0 Configured as IP B4 to function as PC Card Detect 1 signal If the PCMCIA channel is disabled may be configured to alternate function 19 GND 20 21 22 N C 23 GND 24 FRZ UO X Freeze IRQ6 MPC debug state indication or Interrupt request line 6 Used by the debug port controller as debug state indication May be configured to alternate function provided that VFLS 0 1 function as VFLS and J1 is moved to position 1 2 25 GND 26 IRQ2 VO L RSV IRQ2 Reservation or Interrupt Request 2 Pulled up on the M B but otherwise unused on the FADS Release 0 1 31 For More Information On This Product Go to www freescale com 32 FreagscalsoSgmieonduictgr dna Support Information TABLE 5 9 PM2 Interconnect Signals
22. or UPMB General Purpose Line 1 Used for Output Enable vvith EDO Dram simms vvhich have this input most of them don t Used also as RAS signal for the SDRAM 66 GND Release 0 1 27 For More information On This Product Go to www freescale com 28 FreagscalsoSgmieonductgr dna Support Information TABLE 5 8 PM1 Interconnect Signals Signal Name Attribute Description See pin 61 The duality due to separation of BS 0 3 A from VVE 0 3 BS 0 3 B with other members of the 8xx family See pin 53 The duality due to separation of BS 0 3 A from WE 0 3 BS 0 3 B with other members of the 8xx family MPCs Address line 31 See pin 57 The duality due to separation of BS 0 3 A from VVE 0 3 BS 0 3 B with other members of the 8xx family Transfer Size 1 Used in conjunction with TSIZO to indicate the number of bytes remaining in an operand transfer Not used on the FADS In fact TSIZO REG Transfer Size 0 or PCMCIA REG Used with the PCMCIA port as Attribute memory select or I O space select Release O 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonductgr dna Support Information TABLE 5 8 PM1 Interconnect Signals Pin No Signal Name Attribute Description MPCs Address line 12 MPCs Address line 11 123 A24 T S MPC s Address line 24 124 GND Release 0 1
23. to the PX4 See TABLE 4 23 BCSR4 Description on page 57 of the MPC8XXFADS User s Manual X DBREVO O Daughter Board Revision Code Signal 0 The MSB of the D B revision Code Available also on PX4 see TABLE 4 13 BCSR2 Description on page 52 of the MPC8XXFADS User s Manual EXTOLI1 External Tool Identification 1 Connected to BCSR2 Not used on this board just passed from PX4 See TABLE 4 13 BCSR2 Description on page 52 of the MPC8XXFADS User s Manual DBREV2 Daughter Board Revision Code Signal 2 The LMSB of the D B revision Code Available also on PX4 See TABLE 4 13 BCSR2 Description on page 52 of the MPC8XXFADS User s Manual Release O 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr dna Support Information TABLE 5 11 PM4 Interconnect Signals Pin No Signal Name Attribute Description EXTOLI3 O X External Tool Identification 3 Connected to BCSR2 Not used on this board just passed from PX4 See TABLE 4 13 BCSR2 Description on page 52 of the MPC8XXFADS User s Manual BCSR R1 O X Reserved signal 1 in BCSR3 Available also on PX4 See TABLE 4 19 BCSR3 Description on page 55 of the MPC8XXFADS User s Manual O X X DBREV1 Daughter Board Revision Code Signal 1 Available also on PX4 See TABLE 4 13 BCSR2 Description on page 52 of the MPC8XXFADS User s Manual O Daughter Board ID Code 1 Part of the field which designates the type of daug
24. 1 Receive Data When RS232 port 1 is disabled via BCSR1 tri stated and may be used for any alternate function Appears also at P8 of the M B In fact PB23 SDACK1 RS232 port 1 DTR signal When RS232 port 1 is disabled via BCSR1 tri stated and may be used for any alternate function Appears also at P8 of the M B See pins 5 amp 11 RSRXD2 RSDTR2 I O L Rs232 port 2 Receive Data When the IRS232 port is disabled via BCSR1 tri stated Appears also at P8 of the M B as PA13 when RS232 port 2 is selected PB22 RS232 port 2 DTR signal When RS232 port 2 is disabled via BCSR1 tri stated and may be used for any alternate function Appears also at P8 of the M B N N G G PB27 1 0 X PB28 1 0 X PC14 1 0 X PB26 1 0 X Appears also at P8 of the M B as PHYCS for the SAR PHY tool MPC PI O port B 28 Appears also at P8 of the M B as E1 T1 SPI OUT for the SAR PHY tool MPC PI O port C 14 Appears also at P8 of the M B as PHYWR for the SAR PHY tool Also MPC PI O port B 26 Appears also at P8 of the M B as RST BRD for the SAR PHY tool C ND C ND ND C ND G N G TOUT2 1 0 X E CLSN 1 0 H 42 43 46 47 48 56 57 58 61 MPC PI O port A 4 Appears also at P8 of the M B as TOUT2 for the SAR PHY tool Selected with J3 Ethernet Port Collision indication signal Also PC9 CTS2 Connected to the SCC2 s CTS signal When the Ethernet port is disabled via BCSR1 may be
25. 16 bit pods Since all the signals that appear on these connectors appear also on the mother board connectors and on TABLE 5 1 P1 Interconnect Signals Pin Signal Name Pin Z Signal Name 1 N C 2 N C 3 GND 4 5 N C 6 7 SDRMCS 8 BSWEO 9 CS5 10 BSWE1 11 CE1B 12 BSWE2 13 CE2B 14 BSWES 15 BR 16 DRM VV 17 BG 18 EDOOE 19 BB 20 GPL2 21 BI 22 GPL3 23 BURST 24 GPL4A 25 N C 26 GPL4B 27 28 GPL5A 29 BVS2 30 GPL5B A This connector is located on the Mother Board It is documented here since its contents depends on the Daughter Board Release 0 1 For More Information On This Product Go to www freescale com Release 0 1 FreagscalsoSgmieonductgr dna Support Information TABLE 5 1 P1 Interconnect Signals Pin Signal Name Pin Z Signal Name 31 BVS1 32 F_CS 33 BWP 34 BCSRCS 35 BCD2 36 DRMCS1 37 BCD1 38 DRMCS2 TABLE 5 2 P2 Interconnect Signals Pin Z Signal Name Pin Z Signal Name 1 N C 2 N C 3 GND 4 5 N C 6 7 TA 8 A16 9 TS 10 A17 11 TEA 12 A18 13 R W 14 A19 15 REG A 16 A20 17 TSIZ1 18 A21 19 A6 20 A22 21 A7 22 A23 23 A8 24 A24 25 A9 26 A25 27 A10 28 A26 29 A11 30 A27 31 A12 32 A28 33 A13 34 A29 35 A14 36 A30 37 A15 38 A31 For More Information On This Product Go to www freescale com 19 FreagscalsoSgmieonduictgr na the expansion connect
26. 6 MPC8XXFADS s P8 Interconnect Signals A2 ETHTX Ethernet Port transmit data See PM3 5 11 42 A3 IRDRXD IrDA port receive data See PM3 9 A4 IRDTXD IrDA port transmit data See PM3 5 11 42 A5 UTOPIA RXENB UTOPIA RXENABLE See PM3 117 A8 PD8 PD8 SAR PHY AD1 See PM3 114 A9 ETHTCK Ethernet port transmit clock See PM3 27 A10 ETHRCK Ethernet port receive clock See PM3 29 A11 N C A14 PA7 PA7 E1 T1 L1RCLKA See PM3 74 A15 USBTXP PC7 USBTXP SAR PHY AD2 See PM 85 A16 PA5 PA5 E1 T1 L1TCLKA See PM 89 A17 VCC A20 USBRXP PC11 USBRXP SAR PHY AD7 See PM3 21 A21 USBTXN PC6 USBTXN SAR PHY ADG See PM3 23 A22 GND A23 GND A25 FRZ 1 0 H See PM2 24 A26 ETHEN O L See PM3 82 Release 0 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonductgr dna Support Information TABLE 5 16 MPC8XXFADS s P8 Interconnect Signals A28 IRQ2 IL RSV IRQ2 See PM2 26 A29 IRQ1 IL See PM2 126 A30 NMI See PM2 134 A31 RS EN1 See PM3 96 A32 GND B1 N C B2 PB30 PB30 E1 T1 SPI_CLOCK See PM3 35 B4 PB28 PB28 E1 T1 SPI OUT See PM3 51 B5 PB27 PB27 SAR PHY CS See PM3 50 B6 PB26 PB26 SAR PHY RESET_BOARD See PM3 54 B7 RSTXD1 PB25 RS232 port 1 TXD See PM3 38 B8 RSRXD1 PB24 RS232 port 1 RXD See PM3 39 B10 RSDTR2 PB22 RS232 port 2 DTR SAR PHY A
27. 999 11 112 10 J1 J2 J3 Jumper Header 3 Pole with Fabricated Jumper MOLEX 87156 0303 J4 Jumper Soldered Inductor 8 2 mHy BOURNS PT12133 PRECIDIP 999 19 310 00 LD1 Led Green SMD SIEMENS LG T670 HK LD2 LD3 Led Yellow SMD SIEMENS LY T670 HK P1 P2 P5 P6 P7 P8 Connector 38 pin Receptacle AMP 2 767004 2 MICTOR P3 Connector 4 pin Female USB AMP 787780 1 Type B P4 Connector 4 pin Female USB AMP 787616 1 type A PM1 PM2 PM3 PM4 Connector Inter board 7mm MOLEX 53481 1409 Height 140 pin Plug SMD PX1 PX2 PX3 PX4 Connector Inter board 140 pin MOLEX 52760 1409 Receptacle SMD R1 R2 Resistor 1 5 KQ 1 SMD 1206 RODERSTEIN D25 01K5 FCS 1 8W R3 R4 R5 R23 Resistor 124 KQ 5 SMD 1206 RODERSTEIN D25 124K FCS 1 8W R6 R7 Resistor 150 Q 5 SMD 1206 1 RODERSTEIN D25 150RFCS BW R8 Resistor 75 O 595 SMD 1206 1 RODERSTEIN D25075RJCS BW R9 Resistor 47 KO 1 SMD 1206 RODERSTEIN D25047KFCS 1 8W R10 R13 Resistor 10 KO 1 SMD 1206 RODERSTEIN D25010KFCS 1 8W R11 R22 Resistor 0 1 SMD 0603 RODERSTEIN D11 000RFCS 0 1VV R12 R14 R15 R16 R17 R20 R21 Resistor 390 Q 1 SMD 0603 RODERSTEIN D11 390RFCS R18 Resistor 200 KO 1 SMD 1206 RODERSTEIN D25 200K FCS 1 8W R19 Resistor 20 MO 596 SMD 1206 RODERSTEIN D25 020MJCS 1 4W Release O 1 60 For More Information On This Product Go to www freescale com
28. ARE3 MPCs spare line 3 Pulled up but otherwise unused on the FADS V3 3 130 IRQ7 VO L Interrupt Request 7 The lowest priority interrupt request line Pulled up but otherwise not used on the FADS 131 V3 3 132 N C 133 V3 3 Release 0 1 For More Information On This Product Go to www freescale com Pren eneng irin Support Information TABLE 5 9 PM2 Interconnect Signals Pin No Signal Name Attribute Description Non Makable Interrupt In fact IRQO of the MPC Driven by M B logic by O D gate Pulled up May be driven off board by O D gate only a Be aware that TRST is connected to GND with a zero ohm resistor Release O 1 37 For More Information On This Product Go to www freescale com FreagscalsoSgmieonductgr dna Support Information TABLE 5 10 PM3 Interconnect Signals ETHRX O X Ethernet port Receive Data When the ethernet port is disabled via BCSR1 tri stated Appears also at P8 of the M B as PA13 when Ethernet port is selected O L Usb Port Enable Generated by BCSR4 on the M B See TABLE 4 23 BCSR4 Description on page 57 O X SCC2 s TXD output Connected to the Ethernet IrDA and RS232 2 ports on the M B Appears also at P8 of the M B as PA12 when Ethernet or RS232 2 or InfraRed port is selected LX O GND GND PD8 UO X MPC port D 8 SAR PHY Address Data line 1 Appears twice at P8 of the M B first place as PD8 and second
29. Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr dna Functional Description 3 and by MPC850 internal sources When Soft reset is generated to the MPC850 Soft Reset configuration is made available to the MPC by logic residing over the motherboard See 4 1 6 3 Soft Reset Configuration on page 29 on MPC8XXFADS User s Manual 4 2 Interrupts The two external interrupts which are applied to the MPC via its interrupt controller is the ABORT NMI which is generated by a push button amp logic residing over the motherboard and the IRQ2 which is gener ated by the SAR PHY board 4 3 Clock Generator Although most of clock generator logic is found on this board it is documented within the motherboard User s Manual since it is common to all daughter boards See 4 3 Clock Generator on page 30 of the MPC8XXFADS User s Manual 4 4 PCMCIA Port The MPC850 has only one PCMCIA port which resides on PCMCIA port B pins It is routed to the PCMCIA port on the MPC8XXFADS The default Hard Reset Configuration of the FADS sets these pins as PCMCIA port B pins The PCMCIA port on the FADS is meant to reside on PCMCIA port A of the MPCs Therefore there is a cross between PCMCIA ports A and B on the mother board connectors i e port B s signals are connect ed also over places reserved for PCMCIA port A pins For further information see 4 10 PCMCIA Port on page 43 of the MPC8XXFADS User s Manual NOTE
30. J8 is used on the SAR PHY board For a detailed explanation on the option look at the SAR PHY board User Manual e When configuring the SAR PHY board RS232 Port2 and the USB port must be disabled since they share UO pins with the SAR PHY board Those pins are used only for configuring the Release O 1 For More Information On This Product Go to www freescale com Pren enega gia Functional Description SAR PHY board so after the configuration is done it should be a one time process those pins can take the appropriate functionality to serve for the USB and RS232 port2 Because of the above I O pins PB27 and PB26 SAR PHY board Chip Select and Reset respectively must be disabled after the configuration of the SAR PHY board is over in order to avoid contention problems When activating the ATM channel on the SAR PHY tool 1 O pin PC15 functions as RXCAV of the UTOPIA port and therefore it can t function as BINPAK for the PCMCIA port The PCMCIA port must be disabled when operating the ATM channel on the SAR PHY tool tshould be noted that the assignments of the I O pins for the Ethernet port is different than the assignments on the previous revision of the Daughter Board For the new assignments Release O 1 15 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr dna Functional Description see table 4 1 below TABLE 4 1 UO Signals Functionality Assignments with the SAR PHY Board
31. LE See PM3 44 B11 TXD2 PA12 RS232 port 2 TXD See PM3 5 11 42 B12 RSRXD2 RS232 port 2 RXD See PM3 43 B13 E TENA PB18 Ethernet TENA See PM3 77 B16 PB16 PB16 SAR PHY AD4 See PM3 93 B17 PC12 PC12 UTOPIA TXCAV See PM 95 B18 RSDTR2 PB22 RS232 port 2 DTR SAR PHY ALE See PM3 97 B19 GND B22 PB31 PB31 E1 T1 Chip Select See PM3 26 B23 PC14 PC14 SAR PHY WRITE See PM3 53 B24 E CLSN PC9 Ethernet CLSN See PM3 61 B25 E RENA PC8 Ethernet RENA See PM3 62 Release 0 1 55 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr na Support Information TABLE 5 16 MPC8XXFADS s P8 Interconnect Signals Pin No Signal Name Attribute Description B26 PD8 PD8 SAR PHY AD1 See PM3 8 B27 PB19 PB19 SAR PHY ADO See PM3 14 B28 PC5 PC5 L1TSYNCA See PM3 20 B29 PC4 PC4 L1RSYNCA See PM3 100 B30 See PM3 99 B31 N C See PM3 98 B32 GND Ci VCC C2 C3 C4 C5 C6 RS EN2 See PM3 102 C7 GND C8 C9 C10 C11 C12 C13 C14 C15 PD15 PD15 UTOPIA Data bit 0 See PM3 121 16 14 PD14 UTOPIA Data bit 1 See PM3 120 C17 PD13 PD13 UTOPIA Data bit 2 See PM3 119 C18 PD12 PD12 UTOPIA Data bit 3 See PM3 118 C19 PD7 PD7 UTOPIA Data bit 4 See PM3 113 C20 PD6 PD6 UTOPIA Data bit 5 See PM3 110 C21 VCC C22 HRESET See PM2 84 C23 SRESET 2 80 24
32. MOTOROLA scale Semicenducterlnr cor israel Ltd MICROPROCESSOR amp MEMORY TECHNOLOGIES GROUP MPCS50SARDB Revision ENG Ulser s Manual AUTHOR AMITAY BELER MSIL ISSUE 1 Release 0 1 For More information On This Product Go to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com 1 1 1 1 2 1 3 1 4 1 5 1 6 2 1 222 2 3 Release O 1 FreagscalsoSgmieonduictgr na TABLE OF CONTENTS General Information Introduction Abbreviations List Related Documentation SPECIFICATIONS MPC850SARDB Features MPC850SARDB Rev ENG to MPC850FADSDB Rev PILOT Changes Hardware Preparation and Installation INTRODUCTION UNPACKING INSTRUCTIONS HARDWARE PREPARATION Clock Generator Replacement U1 Power On Reset Source Selection Keep Alive Power Source Selection Port A Pin 4 Function Selection INSTALLATION INSTRUCTIONS OPERATING INSTRUCTIONS INTRODUCTION CONTROLS AND INDICATORS GND Bridges 3 3V Indicator LD1 USB On Indicator LD2 USB PWR LD3 MEMORY MAP MPC Registers Programming Functional Description Reset amp Reset Configuration Power On Reset Hard Reset Soft Reset Interrupts Clock Generator PCMCIA Port Communication Ports USB Port Ethernet Port Infra Red Port RS232 Ports E1 T1 Port Board Control amp Status Register BCSR Debug Port Communication Ports Expansion Special Considerations Support Informa
33. OOP 24 PD9 25 TPFLDL 26 PD10 27 E RENA 28 PD11 29 E CLSN 30 PD12 31 PB16 32 PD13 33 PB17 34 PD14 35 E TENA 36 PD15 For More Information On This Product Go to www freescale com 21 Frodo ae gia Support Information TABLE 5 5 P7 Interconnect Signals Pin Z Signal Name Pin Z Signal Name 37 PB19 38 SPARE3 TABLE 5 6 P8 Interconnect Signals Pin 4 Signal Name Pin Signal Name 1 N C 2 N C 3 GND 4 5 N C 6 7 DO 8 D16 9 D1 10 D17 11 D2 12 D18 13 D3 14 D19 15 D4 16 D20 17 D5 18 D21 19 D6 20 D22 21 D7 22 D23 23 D8 24 D24 25 D9 26 D25 27 D10 28 D26 29 D11 30 D27 31 D12 32 D28 33 D13 34 D29 35 D14 36 D30 37 D15 38 D31 5 1 2 P3 amp P4 USB connectors The 850SARDB supports both Type A and Type B USB connectors P3 is Type B P4 is Type A both made by AMP Their pinto is identical Their signals are described in TABLE 5 7 P3 amp P4 Interconnect 22 Release O 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonductgr dna Support Information Signal below TABLE 5 7 P3 amp P4 Interconnect Signal USBPWR USB Power To support USB Host function this pin may be driven with 5V BCSR controlled See TABLE 4 23 BCSR4 Description on page 57 in the FADS User s Manual When the 850DB is configured as a USB Slave power should be turned off for that pin USB negative differential
34. On Reset is generated i e PORESET input of the MPC is asserted for a period of approximately 4 sec When option 2 above is selected the power on reset is generated by a dedicated voltage detector made by Seiko the S 8052ANY NH X with detection voltage range of 2 595V to 2 805V During MAIN 3 3V bus power on or when there is a voltage drop of that input into the above range Power On Reset is generated Le PORESET input of the MPC is asserted for a period of approximately 4 sec The MAIN power on reset also generates power on reset to all logic located on the motherboard When PORESET is asserted to the MPC the Power On reset configuration is made available to MPC See 4 1 6 1 Power On Reset Configuration on page 29 of MPC8XXFADS User s Manual 4 1 2 Hard Reset Hard Reset is generated to the MPC850 by the following sources 1 The MAIN power on reset 2 Manual Hard Reset generated on the mother board 3 The debug port Hard reset 4 and by MPC850 s internal sources When the open drain signal Hard Reset is asserted Hard reset configuration is driven on the data bus by logic on the motherboard See 4 1 6 2 Hard Reset Configuration on page 29 on MPC8XXFADS User s Manual 4 1 3 Soft Reset Soft Reset is generated to the MPC850 by the follovving sources 1 The debug port controller located on the motherboard 2 Manual Soft Reset generated on the motherboard A In fact generated on the daughter board Release O 1 For More
35. R led is lit it indicates that 5V povver is driven to pin 1 of the USB connectors P3 amp P4 When darkened it indicates that pin 1 of these connectors is floating and the MPC850SARDB may be connected to external USB Master See also TABLE 4 23 BCSR4 Description on page 57 of the MPC8XXFADS User s Manual 333 MEMORY MAP The memory map is identical to all daughter boards therefore described in the MPC8XXFADS User s Manual section 3 3 MEMORY MAP on page 16 3 4 MPC Registers Programming See 3 4 MPC Registers Programming on page 9 of the MPC8XXFADS User s Manual Release O 1 9 For More Information On This Product Go to www freescale com aer ina Functional Description 4 Functional Description In this chapter the various modules combining the MPC850SARDB are described to their design details 4 1 Reset amp Reset Configuration There are 3 reset sources for the MPC 1 Power On Reset 2 Hard Reset 3 Soft Reset EDD Power On Heset The Power On Reset on the MPC850SARDB is generated out of 2 alternative power buses 1 The keep alive power bus 2 The MAIN power bus Selection between the 2 options is done by means of jumper When option 1 above is selected the power on reset is generated by a dedicated voltage detector made by Seiko the S 8051HN CD X with detection voltage range of 1 795 to 2 005V During keep alive power on or when there is a voltage drop of that input into the above range Power
36. RER lee eye 68 Release O 1 For More Information On This Product Go to www freescale com MO MPC850SARDB Schematics FreagscalsoSgmieonductgr na N DEEN e yax 30078 83138 AVIIAY ONG 1 1 8 40 L 133HS ON3 A3H 10S0v40982dA 1337084 Y A e IM e JNI ae j 961 5104 Et d il c 0104 608 804 Ld 321X300 1SuOQA 9c S d gt Edd 918d 574 axiesn NXugsn ASAS 65 Fi 14 i 55 DI 55 4 M 2104 lt t 9790 3 la 39H13 LVd 874 674 69 For More Information On This Product Go to www freescale com N Release 0 1 FreagscalsoSgmieonduictgr na MPC850SARDB Schematics A 4 H V dl s30 YHJ SHO123NNOJ H3ZATYNY 1501 2018 83138 AVLIAY ER 8 10 8 9N3 g0S0V40582d4 1237084 X v ub IN 5d 5040 DIR T N ES 200 ipte 24 TON 2042 F N m TOND yu lu ur WK 9 5 E 5 S OND L ONO 7 0S Hie 7
37. Signal Name Attribute Description 7 5 D7 1 0 X MPC s Data line 7 C 1 MPCs Data line 6 MPCs Data line 5 D4 1 0 X MPCs Data line 4 MPCs Data line 3 woo RE D1 MPC s Data line 1 GND DO MPC s Data line 0 Dram Half Word Sets the Dram to 16 bit data bus width Not used on this D B just passed on to the expansion connectors See TABLE 4 10 BCSR1 Description on page 49 of the MPC8XXFADS User s Manual DRAMEN Dram Enable Enables Dram to the FADS memory map Not used on this D B just passed on to the expansion connectors See TABLE 4 10 BCSR1 Description on page 49 of the MPC8XXFADS User s Manual FCFGEN Flash Configuration Enable Allows for Hard Reset Configuration to be obtained from the Flash memory provided that this option is supported by the MPC Not used on this D B just passed on to the expansion connectors See TABLE 4 10 BCSR1 Description on page 49 of the MPC8XXFADS User s Manual 64 65 66 67 71 72 73 D2 X MPC s Data line 2 76 77 78 79 81 82 83 Release O 1 47 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr dna Support Information TABLE 5 11 PM4 Interconnect Signals Pin No Signal Name Attribute Description Flash Enable Enables the Flash memory to the FADS memory map Not used on this board just passed on to PX4 See TABLE 4 10 BCSR1 Description on pa
38. UO pin PC15 which is used as BINPAK is also used as RXCAC for the UTOPIA port When the ATM channel on the SAR PHY tool is active the PCMCIA port can t be used and therefore must be disabled 4 5 Communication Ports The MPC850 has the following communication ports 1 USB Port which is connected on board to a USB transceiver 2 SCC2 which may be operated either as an Ethernet port or as an Infra Red port or as RS232 Port 2 3 SMC1 which is connected to RS232 Port 1 of the MPC8XXFADS 4 SMC2 which supports TDM only and will not be used on board 5 SPI which is used for programming the E1 T1 Framer on the SAR PHY board All communication ports may be enabled disabled by S W via BCSR1 or BCSR4 See TABLE 4 10 BCSR1 Description on page 49 and TABLE 4 23 BCSR4 Description on page 57 both in MPC8XXFADS User s Manual To protect against possible contention the RxD lines of the Ethernet port IrDA port and RS232 Port 2 of the MPC8XXFADS are multiplexed to RXD2 input The selection between the 3 RxD lines is done accord ing to their respective enable bits in BCSR1 When ETH EN IRD EN or RS EN2 bits in BCSR1 are A In MPC821 Terms Release O 1 11 For More Information On This Product Go to www freescale com 12 Functional Description mutually exclusive enabled their respective comm port RxD line is driven to RXD2 of the MPC If 2 or more of these lines are simultaneously enabled 0 is d
39. X MPC PI O port A 4 E1 T1 L1TSYNCA Ethernet port Transmit Clock Appears also at P8 of the M B E1 T1 L1TSYNCA TOUT2 signal 59 22 23 29 ETHRCK O X MPC PI O port A 6 Ethernet port Receive Clock When the ethernet port is disabled via BCSR1 tri stated Appears also at P8 of the M B 31 32 USBSPD LX Usb port Speed control Controls the speed of the USB transceiver while changing pull up resistors between USB D and D lines See also TABLE 4 23 BCSR4 Description on page 57 of the MPC8XXFADS User s Manual ND C a ND G N BINPAK 1 0 X PC15 BINPAK RXCAV PCMCIA port Input Port Acknowledge When the PCMCIA port is disabled via BCSR1 it may be used as RXCAV for the UTOPIA port or off board for any alternate function PB30 1 0 X MPC PI O port B 30 Appears also at P8 of the M B as E1 T1 SPI CLOCK for the SAR PHY tool LONE MEN RESP PB29 1 0 X MPC PI O port B 29 Appears also at P8 of the M B as E1 T1 SPI IN for the SAR PHY tool 1 0 X In fact PB25 SMTXD1 RS232 Port 1 Transmit Data When RS232 port 1 is disabled via BCSR1 may be used for any alternate function Appears also at P8 of the M B Release O 1 39 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr dna Support Information TABLE 5 10 PM3 Interconnect Signals Pin No Signal Name Attribute Description RSRXD1 1 0 X RSDTR1 I O L TXD2 In fact PB24 SMRXD1 RS232 Port
40. Xp 001 101 201 01 E 9 801 6 0101 noi 2 1 n OND II 8d SOND SOND Fe 200 zl ND 200 L mu mn 10 07 DA sel H WE zi HIH 1 vas ND 7 US 20 10X1S8 E x 7 gt U J g V C a Release 0 1 For More information On This Product Go to www freescale com
41. act IP Used in conjunction with BBVD2 to determine the battery status of a PC Card In case of MPC850 or MPC850 daughter boards connected to IP B6 signal of the MPC Release O 1 35 For More Information On This Product Go to www freescale com Pren eneng irin Support Information TABLE 5 9 PM2 Interconnect Signals Pin No Signal Name Attribute Description See pin 16 The duality since the MPC850 s PCMCIA port B is connected to PCMCIA port on the M B normally residing on PCMCIA port A of the MPC8XXs See pin 42 The duality since the MPC850 s PCMCIA port B is connected to PCMCIA port on the M B normally residing on PCMCIA port A of the MPC8XXs DPO IRQ3 Data Parity line 0 or Interrupt Request 3 May generate and receive parity data for D 0 7 bits connected to the DRAM SIMM May be configured as IRQ3 only if the DRAM is disabled on the M B DP2 IRQ5 Data Parity line 2 or Interrupt Request 5 May generate and receive parity data for D 16 23 bits connected to the DRAM SIMM May be configured as IRQ5 only if the DRAM is disabled on the M B DP1 IRQ4 Data Parity line1 or Interrupt Request 4 May generate and receive parity data for D 8 15 bits connected to the DRAM SIMM May be configured as IRQ4 only if the DRAM is disabled on the M B 123 V 3 3 N C V3 3 IRQ1 nterrupt Request 1 Pulled up on the M B but othervvise not used on the FADS V3 3 SP
42. and partial comm ports the pin assign ment of this connector P8 is different and any tool made for this connector should be examined carefully prior to being connected to the MPCSXXFADS having the MPC850SARDB connected to it 4 10 Special Considerations Special care must be observed when configuring the MPC850SAR Some of the I O pins have dual func tionality See table 4 1 and the correct functionality has to be according to the desired configuration The details are as followed Ethernet InfraRed and RS232 Port2 are multiplexed Only one can be functional at a given time The selection is done with the BCSR When using the E1 T1 port there is an option on the SAR PHY board to generate L1TSYNCA and L1TCLKA locally using the U12 clock generator see the SAR PHY user manual In this case U12 generates L1TCLKA and L1TSYNCA is generated internally by the MPC850 and output through TOUT2 which is PA4 This I O pin is also used as the ETHTCK so the Ethernet port must be disabled when utilizing this option Pay attention that this is different than how it was done in the previous revision of the DaughterBoard In the previous revision U12 clock was inserted to the MPC850 through a dedicated I O pin TIN2 PA5 and it was used to generate TOUT2 That would require the use of jumpers J8 and J9 on the SAR PHY board In this revision the option of TIN2 is not available so L1TCLKA or L1RCLKA are used to generate TOUT2 Therefor only jumper
43. cillators may be used with 8 pins only form factor WARNING IF A 14 Pin Form Factor 3 3V Clock Generator is insert ed to U1 PERMANENT DAMAGE Might Be Inflicted To The Device WARNING Since the MPC clock input is NOT 5V TOLERANT any clock generator inserted to U1 MUST HAVE 3 3V com patible output If a 5V output clock generator is inserted to U1 PERMANENT DAMAGE might be inflicted to the MPC 2 3 2 Power On Reset Source Selection As there are differences between MPC revisions regarding the functionality of the Power On Reset logic it is therefore necessary to select different sources for Power ON reset generation J1 on the 850DB is used to select Power On Reset source when a jumper is placed between positions 1 2 of J1 Power On reset to the MPC is generated by the Keep Alive power rail Le When KAPWR goes below 2 005V Power On reset is generated When a jumper is place between position 2 3 of J1 Power On reset to the MPC is generated from the MAIN 3 3V power rail Le when the MAIN 3 3V power rail goes below 2 805V Power On reset is generated Release O 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonductgr na Hardware Preparation and Installation FIGURE 2 3 Power On Reset Source Selection J1 J1 4 7 x X S 2 KA Power Rail MAIN Power Rail 2 3 3 Keep Alive Povver Source Selection J2 selects the Keep Alive power source of the MPC When a jumper is placed be
44. configured to alternate function Release O 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr dna Support Information TABLE 5 9 PM2 Interconnect Signals Pin No Signal Name Attribute Description IP_B6 DSDI ATO Input Port B 6 or Debug Serial Data Input or Address Type 0 Configured as IP B6 to function as PC Card s Battery Voltage Detect 1 May be used for alternate function If the PCMCIA channel is disabled may be configured to alternate function MODCK 2 MODCK2 OP1 Upon Power On reset determines along with 1 the clock operation mode for the MPC After PON reset serves as OE for the PCMCIA port See pin 44 The duality since the MPC850 s PCMCIA port B is connected to PCMCIA port on the M B normally residing on PCMCIA port A of the MPC8XXs Asynchronous external master Address Strobe signal When asserted L by the external master the MPC recognizes an asynchronous cycle in progress Pulled up but otherwise unused on the FADS MODCK1 OP2 MODCK1 STS PCMCIA Output Port 2 or Mode Clock 1 input or Special Transfer Start output Used at Power On reset as MODCK1 Configured afterwards as a OP2 to function as PC Card Reset GND MODCK1 See pin 60 The duality since the MPC850 s PCMCIA port B is connected to PCMCIA port on the M B normally residing on PCMCIA port A of the MPC8XXs 67 GND Release O 1 33
45. ctors 126 127 MDM AUD LL Not used on this board L MODEMEN Not used on this board 130 131 132 N C GND N C VCC Release 0 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonductgr na Support Information TABLE 5 11 PM4 Interconnect Signals Data line 31 MPCs Data line 30 1 0 X MPCs Data line 29 MPCs Data line28 10 1 12 13 14 1 0 X MPCs Data line 27 MPCs Data line 26 15 MPCs Data line 25 1 0 X MPCs Data line 24 MPCs Data line 23 1 0 X MPCs Data line 22 26 D21 1 0 X MPCs Data line 21 27 GND 28 D20 1 0 X MPC s Data line 20 Release 0 1 45 For More information On This Product Go to www freescale com FreagscalsoSgmieonduictgr dna Support Information TABLE 5 11 PM4 Interconnect Signals Attribute Description 32 D19 1 0 X GND 157117 EY 38 41 1 0 X MPCs Data line 15 43 44 ee TT GND D14 1 0 X GND MPCs Data line 13 MPCs Data line 12 D11 MPCs Data line 11 GND D10 MPCs Data line 10 E NL E 2 58 GND GND D8 1 0 X MPC s Data line 8 46 Release O 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr dna Support Information TABLE 5 11 PM4 Interconnect Signals Pin No
46. g the new high density HP16500 logic analyzer adaptors in order to provide fast connection to logic analyzer while saving on board s space and reducing EMI 1 2 Abbreviations List FADSC the MPC8XXFADS to which this board connects UPM User Programmable Machine General Purpose Chip select Machine GPL General Purpose Line associated with the UPM I R Infra Red D B or 850SARDB the MPC850SARDB the subject of this document e MPC8xxFADS Mother Board e BSCR Board Control amp Status Register Z F Zero Input Force e BGA Ball Grid Array Spec engineering Specification Document e MPC850 Refers to either MPC850 or MPC850SAR e SAR PHY Refers to the ATM E1 T1 Tool board made for the MPC860 850SAR 1 3 Related Documentation MPC850 User s Manual ADI Board Specification e MPCEXXFADS Engineering Specification e PHILIPS s PDIUSBP 1 1 Data Sheet May be obtained from http www semiconductors philips com acrobat 4417 pdf A Board s bottom B Board s top C Not to be mistaken for the M683XX Family Ads Release O 1 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr dna General Information 1 4 SPECIFICATIONS The MPC850SARDB specifications are given in TABLE 1 1 TABLE 1 1 MPC850SARDB Specifications CHARACTERISTICS SPECIFICATIONS Microprocessor Addressing Total address range
47. ge 49 of the MPC8XXFADS User s Manual SDRAMEN Sdram Enable Enables the Synchronous Dram to the FADS memory map Not used on this board just passed on to PX4 See TABLE 4 10 BCSR1 Description on page 49 of the MPC8XXFADS User s Manual BCSREN BCSR Enable Enables the BCSR to the FADS memory map Not used on this board just passed on to the PX4 See TABLE 4 10 BCSR1 Description on page 49 of the MPC8XXFADS User s Manual USBVCCO USB Power Drives VCC on the USB bus when the MPC850 functions as USB host Available also on PX4 See TABLE 4 23 BCSR4 Description on page 57 of the MPC8XXFADS User s Manual PC Card Enable Enables the PC Card to be accessed by the FADS Available also on PX4 See TABLE 4 10 BCSR1 Description on page 49 of the MPC8XXFADS User s Manual EXTOLIO External Tool Identification 0 Connected to BCSR2 Not used on this board just passed from PX4 See TABLE 4 13 BCSR2 Description on page 52 of the MPC8XXFADS User s Manual SGLAMP Signaling Lamp Used for misc s w signaling purpose Not used on this board just passed on to the PX4 See TABLE 4 23 BCSR4 Description on page 57 of the MPC8XXFADS User s Manual EXTOLI2 External Tool Identification 2 Connected to BCSR2 Not used on this board just passed from PX4 See TABLE 4 13 BCSR2 Description on page 52 of the MPC8XXFADS User s Manual USBVCC1 O X Reserved Signal for USB Power control Not used on this board just passed on
48. generate L1TCLKA and L1TSYNCA locally using U12 see the SAR PHY User Manual In this case PA4 is used as TOUT2 and therefor the Ether net port must be disabled 4 7 Board Control amp Status Register BCSR Most BCSR control signals and some of BCSR s status signals are available on the motherboard connec tors and on the expansion connectors The BCSR control most of the functions available on the MPC850DB and on the MPC8XXFADS See 4 11 Board Control amp Status Register BCSR on page 45 of MPC8XXFADS User s Manual 4 6 Debug Port The MPC850 is connected to the FADS s debug port controller through the mother board connectors See 4 12 Debug Port Controller on page 58 of the MPC8XXFADS User s Manual The debug Port on the DB resides over the MPC850 JTAG port No support is given for debug port to reside over PCMCIA port B pins Since VFLS 0 1 that are usually required by the debug port controller to monitor for Run Debug Mode status are being used for PCMCIA port B use is done with the FRZ signal which is connected to debug port controller on the MPC8XXFADS 4 9 Communication Ports Expansion On the MPC821 860ADS all MPC821 or MPC860 communication ports pins were available on a 96 pins DIN 41612 connector designated as P13 Connector P8 of the MPC8XXFADS is compatible with this con nector when MPC821FADSDB or MPC860FADSDB daughter boards are connected to the MPC8XXFADS With the MPC850 however which has different
49. gnals VOL L MPC Bus Busy signal Pulled up on the FADS Bus Busy signal Pulled up on the FADS VCC MPC s GPLO lines used as R W signal for the DRAM simm or as A10 line for the SDRAM 5V Bus Transfer Error Acknowledge Pulled up not driven on board MPC s Bus Request signal Pulled up on the FADS but otherwise unused BURST UO L MPCss Burst indication Pulled up on the FADS but otherwise unused 5 UPMA general purpose line 4 Not used on the FADS MPC s transfer Acknowledge signal Indicates end of bus cycle used with FADS logic 14 15 MPC s Transfer Start indication Pulled up but otherwise unused on the FADS 16 General Line 5 of UPMB Not used on the FADS 7 5 L 5550 Bus grant signal Pulled up on the FADS but othervvise unused 2 ME O L Purpose Line 4 of UPMB Not used on the FADS 22 VCC 23 R W UO L MPC s Read Write indication Pulled up on the FADS and used by FADS logic 24 VCC 25 BCSRCS UO L In fact CS1 of the MPC Used as chip select for the BCSRs Pulled up When BCSR is removed from the local map may be used off board via the expansion connectors Release O 1 25 For More Information On This Product Go to www freescale com FreagscalsoSgmieonductgr dna Support Information TABLE 5 8 PM1 Interconnect Signals Pin No Signal Name Attribute Descrip
50. gram on page 5 The board has been factory tested and is shipped with settings as described in the following paragraphs Parameters can be changed for the following conditions e Clock generator e Power On Reset Source Keep Alive Power Source Release O 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr dna Hardware Preparation and Installation FIGURE 2 1 MPC850SARDB Top Side Part Location diagram Release O 1 3 ott 1 2 3 3V USB ON USB PWR 1 2 PX uses P3 JPP a gt aan e ADDRESS 8 STROBES pg GND GND 2 3 Ut PX2 B B M un E m m 1 J3 5 x E 3 1 L a GND z DATA amp CONI 28 E P lL Px4 b NAF d E N GND MOTOROLA IN 084 00129 PS MPC85 SAR REV ENG C 49 998 2 2 3 1 Clock Generator Replacement 11 When replacing U1 with another clock generator it should be noticed that there are 2 supply level available at U1 1 2 5V supply at pin 14 3 3V supply available at pin 11 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr Hardware Preparation and Installation FIGURE 2 2 U1 Power Sources 5V 3 3V From looking at FIGURE 2 2 U1 Power Sources above we see that 5V with 3 3V output only oscillator may be used with 14 pins only form factor while 3 3V os
51. hter board connected Available also on PX4 See TABLE 4 19 BCSR3 Description on page 55 of the MPC8XXFADS User s Manual BCSR3RO Reserved signal 0 in BCSR3 Available also on PX4 See TABLE 4 19 BCSR3 Description on page 55 of the MPC8XXFADS User s Manual Daughter Board ID Code 3 Part of the field which designates the type of daughter board connected Available also on PX4 See TABLE 4 19 BCSR3 Description on page 55 of the MPC8XXFADS User s Manual Daughter Board ID Code 0 Part of the field which designates the type of daughter board connected Available also on PX4 See TABLE 4 19 BCSR3 Description on page 55 of the MPC8XXFADS User s Manual Daughter Board ID Code 5 Part of the field which designates the type of daughter board connected Available also on PX4 See TABLE 4 19 BCSR3 Description on page 55 of the MPC8XXFADS User s Manual Daughter Board ID Code 2 Part of the field which designates the type of daughter board connected Available also on PX4 See TABLE 4 19 BCSR3 Description on page 55 of the MPC8XXFADS User s Manual BCSR3R13 Reserved signal 13 in BCSR3 Available also on PX4 See TABLE 4 19 BCSR3 Description on page 55 of the MPC8XXFADS User s Manual Daughter Board ID Code 4 Part of the field which designates the type of daughter board connected Available also on PX4 See TABLE 4 19 BCSR3 Description on page 55 of the MPC8XXFADS User s Manual Chip In Socket When
52. ical form so miss insertion is not possible Release O 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonductgr dna OPERATING INSTRUCTIONS 3 OPERATING INSTRUCTIONS 3 1 INTRODUCTION This chapter provides necessary information to use the MPC850SARDB 3 2 CONTROLS AND INDICATORS The MPC850SARDB does not have any switches but has few indicators described below 3 2 1 GND Bridges There are 3 GND bridges on the MPC850SARDB They are meant to assist general measurements and logic analyzer connection Warning The GND bridges on board physically resemble J4 Do not mistake J4 to be a GND jumper otherwise perma nent damage might be inflicted to the MPC850SARDB and or to the MPC8XXFADS Warning When connecting to a GND bridge use only INSULATED GND clips Failure in doing so might result in perma nent damage to the MPC850SARDB 3 2 2 3 3V Indicator LD1 The yellow 3 3V led LD1 indicates that the 3 3V power bus is powered from the MPC8XXFADS 3 2 3 USB On Indicator LD2 When the yellow USB ON indicator led LD2 is lit it designates that the USB transceiver is enabled for USB reception i e the receive buffer is driven towards the MPC When it is darkened the receive buffer is tri stated and the USB pins may be used for any alternate function See also TABLE 4 23 BCSR4 Description on page 57 of the MPC8XXFADS User s Manual 3 24 USB PVVR LD3 VVhen the yellovv USB PVV
53. inly between PM3 and PX3 resulting from the difference between the various members of the 8XX family Therefore in the following tables only the differences are docu Release O 1 51 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr na Support Information mented per each connector pair PM1 PX1 TABLE 5 12 PX1 PM1 Interconnect Signals Differences No Difference TABLE 5 13 PX2 PM2 Interconnect Signals Differences EXTCLK O X External Clock 4MHz clock generator output the input clock to the MPC TABLE 5 14 PX3 PM3 Interconnect Signals Differences USBRXD USB port receive data PA15 USBRXD This place on the connectors is reserved for SCC1 s RXD line which is this signal for MPC850 When the USB port is disabled via BCSR4 may be used for any alternate function USB Port Output Enable PC14 USBOE This place is reserved for SCC1 s TXD output normally residing on PA14 When this signal is active low the USB transceiver is open to the USB bus When inactive the transceiver is in receive mode One of the USB receive lines PC11 USBRXP SAR PHY AD 7 PA13 RXD2 SCC2 receive data Mux ed between the Ethernet InfraRed and RS232 Port 2 When neither of these port is enabled via BCSR1 may be used for any alternate function USBRXN One of the USB receive lines PC10 USBRXP SAR PHY AD3 USBTXP One of the USB transmit lines PC7 USBTXP SAR PHY AD 2
54. ors they are described there Support Information TABLE 5 3 P5 Interconnect Signals Pin Z Signal Name Pin Signal Name 1 N C 2 N C 3 GND 4 5 N C 6 7 DSCK 8 DSDI 9 BBVD2 10 N C 11 BBVD1 12 DSDO 13 BRDY 14 FRZ 15 ALE B 16 NMI 17 SPKROUT 18 IRQ1 19 MODCK1 20 IRQ2 21 MODCK2 22 IRQ7 23 WAIT 24 N C 25 RSTCNF 26 EXTCLK 27 TEXP 28 N C 29 HRESET 30 DPO 31 SRESET 32 DP1 33 PORST 34 DP2 35 N C 36 DP3 37 38 V3 3 TABLE 5 4 P6 Interconnect Signals Pin Z Signal Name Pin Z Signal Name 1 N C 2 N C 3 GND 4 5 N C 6 7 USBRXD 8 SYSCLK 9 USBOE 10 N C 11 USBRXP 12 13 USBRXN 14 15 USBTXP 16 PC12 20 For More Information On This Product Go to www freescale com Release O 1 Release 0 1 FreagscalsoSgmieonductgr dna Support Information TABLE 5 4 P6 Interconnect Signals Pin Z Signal Name Pin Z Signal Name 17 USBTXN 18 TPSQEL 19 TXD2 20 PC14 21 RXD2 22 BINPAK 23 TMS 24 N C 25 PB27 26 SPARE2 27 PB26 28 N C 29 PB28 30 RSDTR1 31 PB29 32 N C 33 PB30 34 RSDTR2 35 PB31 36 RSRXD1 37 TRST 38 RSTXD1 TABLE 5 5 P7 In terconnect Signals Pin Z Signal Name Pin Z Signal Name 1 N C 2 N C 3 GND 4 5 N C 6 7 8 PD3 9 TOUT2 10 N C 11 ETHTCK 12 13 PA5 14 PD4 15 ETHRCK 16 PD5 17 PA7 18 PD6 19 DAG 20 PD7 21 PA9 22 PD8 23 ETHL
55. place as SAR PHY Address Data line 1 IRDRXD InfraRed Port Receive Data When the I R port is disabled via BCSR1 tri stated Appears also at P8 of the M B as PA13 when InfraRed port is selected 59 X See pin 5 Appears on 3 different pins since for the 850DB the Ethernet IrDA and RS232 port 2 are connected to the same SCC 2 SAR PHY tool Address Data line 0 Appears also as L1TXDA at P8 of the M B to support the E1 T1 Port on the SAR PHY Tool Appears also as L1RXDA at P8 of the M B to support the E1 T1 Port on the SAR PHY Tool X Appears also as L1TSYNCA at P8 of the M B to support the E1 T1 Port on the SAR PHY Tool Release O 1 For More Information On This Product Go to www freescale com Support Information TABLE 5 10 PM3 Interconnect Signals Pin No Signal Name Attribute Description USBRXP MPC850 s PC 11 USBRXP SAR PHY AD7 One of USB transceiver s receive signals Appears also at P8 of the M B as SAR PHY Address Data Line 7 as support to the SAR PHY tool GND USBTXN MPC PC6 When the USB port is enabled serves as negative differential transmit data Appears also at P8 of the M B as SAR PHY Address Data Line 6 as support to the SAR PHY tool When the USB port is disabled via BCSR1 may used for any alternate function Il PB31 1 0 X MPC PI O port B 31 Appears also at P8 of the M B as E1 T1 Chip Select for the SAR PHY Tool ETHTCK 1 0
56. r More Information On This Product Go to www freescale com Release 0 1 FreagscalsoSgmieonduictgr na MPC850SARDB Schematics CN MO oz x x ES 3 N oen TIE 03x ei T AE T SrckRt Bb T ce E T 6 SS n Pi 25 E Els la s s s S B T tie 8 mea x lalala E z 8 ZIODBBD 3 8 izi 5 B g 2999229 SIS 2 H 5 5 a 08 E c b ES E SE ES 2223338 S SHEHE 6 S gm ER so 4 D 218 ei gt goz Xos mi BESA NX88sn oly NST 3 615 VN3H 3 dx18Sn L3c 4 185 SL NX18Sh 92d VII ER C3 T ad VJNASAT 2 IVJNASHT1 72d 7Jd 41 9041 7893 f J 9DHI EAC 096 7626 o6E g oead E 7 Ide OO ag 062 1 040 LNOMdS 7 DAI 3 ASH Z DUI Y LL m EN O ce LJ 423 a mn 9 9 22 SEEZS Z r Lo s s 2 2 g ra er LA xo co Release 0 1 For More Information On This Product Go to www freescale com 63 MPC850SARDB Schematics FreagscalsoSgmieonductgr doa 13739 AVIV 1050V40582d44 DECH HWZ 8 co Release 0 1
57. riven to RXD2 When neither of them is asserted the output of the mux is tri stated and RXD2 line of the MPC may be used for any alternate function The connection scheme of the Ethernet IrDA and Serial Port 2 to SCC2 is shown in FIGURE 4 1 SCC2 Connection Scheme below FIGURE 4 1 SCC2 Connection Scheme MPC850x a A Ar 6 e 4 5 1 USB Port The USB port resides on the MPC850SARDB and is driven by the USB port of the MPC850 A dedicated USB transceiver the PDIUSBP11 by PHILIPS is provided along with a tri state buffer separating this port from the MPC s USB port this to allow Port disable option and off board use of MPC USB pins To correctly support the 2 speed modes of the USB detachable pull up resistors 3 3V are provided over D and D lines of the USB controlled by the USB SPD bit of BCSR4 When USB SPD is in low speed level low D is pulled up while D remains floating When USB SPD bit is in high speed level D is being pulled up and D floats USB SPD is connected to the SPEED input of the USB transceiver setting it to the desired operation range Also 5V power is optionally provided for the USB connector controlled by USB VCCO in BCSR4 When USB VCOO is driven low a 5V supply is connected to pin 1 of the USB connectors To support both ph
58. this signal is active low FADS logic is being noticed that the evaluated MPC8XX resides in its socket If inactive either the MPC is out of socket or a daughter board is not connected in which case the FADS becomes a debug station Available also on PX4 Release O 1 49 For More Information On This Product Go to www freescale com FreagscalsoSgmieonductgr dna Support Information TABLE 5 11 PM4 Interconnect Signals Pin No Signal Name Attribute Description 50 Release O 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr dna Support Information TABLE 5 11 PM4 Interconnect Signals Pin No Signal Name Attribute Description 5 1 4 PX1 PX4 Hardware Expansion Connectors These connectors are receptacle inter board connectors made by Molex They are identical to those exist on the MPC8XXFADS mother board Their mechanical assembly is similar as well and is shown in FIGURE 5 2 Expansion Connectors Mechanical Assembly below FIGURE 5 2 Expansion Connectors Mechanical Assembly PX1 i Ke o x m co A oi Y PXO PX3 gt B lt X PX4 iso Qe x 109 S 29 79 D T 93 98 In principle the expansion connectors are identical in signals assignment to the mother boards connec tors However there is a difference ma
59. tion 5V Bus UPMA general purpose line 5 Not used on the FADS 5V Bus VO L MPC s Burst Inhibit input Pulled up but otherwise unused on the FADS Not Connected Reserved MPC850 s PC Card Enable 2 Enables ODD address bytes Connected to the FADS PC Card control logic S FADS Ground plane MPC s Chip Select line 5 Unused on the FADS PC Card Enable 1 for PCMCIA slot B Enables the EVEN address bytes Connected to the FADS s PC Card control logic In fact MPC s chip select line 0 Used as chip select for the Flash Simm on FADS Pulled up on the M B When the Flash is disabled via BCSR may be used off board via the expansion connectors See pin 35 Duality exists since the MPC850 uses slot B controls for the FADS s PC Card originally residing over slot A See pin 31 Duality exists since the MPC850 uses slot B controls for the FADS s PC Card originally residing over slot A DRMCS2 In fact MPC s chip select line 3 Used as chip select line for the 2 nd bank of the Dram Simm Pulled up on the M B When the Dram is disabled via BCSR or when a single bank Dram Simm is being used may be used off board via the expansion connectors GND DRMCS1 In fact MPC s chip select line 2 Used as chip select line for the 1 st bank of the Dram Simm Pulled up on the M B When the Dram is disabled via BCSR may be used off board via the expansion connectors 46 GND
60. tion Interconnect Signals P1 P2 P5 P6 P7 and P8 Logic Analyzer Connectors P3 amp P4 USB connectors PM1 PM4 Mother Board Connectors PX1 PX4 Hardware Expansion Connectors MPC8XXFADS s P8 Serial Ports Expansion Connector For More Information On This Product Go to www freescale com KO KO OO CO cO cO cO OQ 00 4 J OQ SS GMM HHH ech 592 gia TABLE OF CONTENTS MPC850SARDB Part List MPC850SARDB Schematics For More Information On This Product Go to www freescale com 59 62 Release 0 1 TABLE 1 1 TABLE 4 1 TABLE 5 1 TABLE 5 2 TABLE 5 3 TABLE 5 4 TABLE 5 5 TABLE 5 6 TABLE 5 7 TABLE 5 8 TABLE 5 9 TABLE 5 10 TABLE 5 11 TABLE 5 12 TABLE 5 13 TABLE 5 14 TABLE 5 15 TABLE 5 16 TABLE 5 17 TABLE 5 18 Release O 1 FreagscalsoSgmieonduictgr dna LIST OF TABLES MPC850SARDB Specifications VO Signals Functionality Assignments with the SAR PHY Board P1 Interconnect Signals P2 Interconnect Signals P5 Interconnect Signals P6 Interconnect Signals P7 Interconnect Signals P8 Interconnect Signals P3 amp P4 Interconnect Signal PM1 Interconnect Signals PM2 Interconnect Signals PM3 Interconnect Signals PM4 Interconnect Signals PX1 PM1 Interconnect Signals Differences PX2 PM2 Interconnect Signals Differences PX3 PM3 Interconnect Signals Differences 4 PM4 Interconnect Signals Difference MPC8XXFADS s P8 Interconnect Signals
61. to www freescale com FreagscalsoSgmieonduictgr dna Support Information TABLE 5 9 PM2 Interconnect Signals Pin No Signal Name Attribute Description See pin 14 The duality since the MPC850 s PCMCIA port B is connected to PCMCIA port on the M B normally residing on PCMCIA port A of the MPC8XXs See pin 34 The duality since the MPC850 s PCMCIA port B is connected to PCMCIA port on the M B normally residing on PCMCIA port A of the MPC8XXs See pin 30 The duality since the MPC850 s PCMCIA port B is connected to PCMCIA port on the M B normally residing on PCMCIA port A of the MPC8XXs DP3 IRQ6 Data Parity line 3 or Interrupt Request 6 May generate and receive parity data for D 24 31 bits connected to the DRAM SIMM May be configured as IRQ6 input for the MPC only if the DRAM is disabled on the M B See pin 38 The duality since the MPC850 s PCMCIA port B is connected to PCMCIA port on the M B normally residing on PCMCIA port A of the MPC8XXs See pin 18 The duality since the MPC850 s PCMCIA port B is connected to PCMCIA port on the M B normally residing on PCMCIA port A of the MPC8XXs This signal selects between clock generator and the 32768 Hz crystal as clock sources for the MPC Its is driven by DS2 4 of the M B See 2 3 2 Clock Source Selection on page 7 of the MPC8XXFADS User s Manual 111 GND Buffered PCMCIA slot A Battery Voltage Detect 1 In f
62. tween positions 1 2 of J2 the Keep Alive power is fed from the main 3 3V bus When an external power source is to be connect ed to the Keep Alive power rail it should be connected between positions 2 the positive pole and position 3 GND of J2 FIGURE 2 4 Keep Alive Power Source Selection J2 J2 33V 1 bd 33V 1 x x i KAPWR From 3 3V KAPWR From Ext Ext Power Supply Power Supply 2 3 4 Port A Pin 4 Function Selection J3 selects the functionality that pin PA4 takes In normal operation it should be connected to ETHTCK pins 1 2 of jumper J3 The jumper should be placed on pins 2 3 only when the E1 T1 channel is tested with an external loop see the SAR PHY User Manual for more details A E g a battery Release 0 1 7 For More Information On This Product Go to www freescale com Pren enega gia Hardware Preparation and Installation FIGURE 2 5 PA4 Function Selection J3 J3 ETHTCK 1 ETHTCK 24 PA4 ES PA4 ES TOUT2 24 TOUT 2 24 Normal Operation E1 T1 Test 2 4 INSTALLATION INSTRUCTIONS The MPC850SARDB should be plugged into the MPC8XXFADS Mother Board This should be done when the FADS is disconnected from any power supply The 850DB should be placed over the mother board connectors in a way that the mother board connectors of the 850DB PM1 PM4 match the daughter connectors of the FADS and than pressed gently into position The connectors are arranged in a non symmetr
63. used off board for any alternate function Appears also on P8 of the M B 40 Release O 1 For More Information On This Product Go to www freescale com Support Information TABLE 5 10 PM3 Interconnect Signals Attribute Description Ethernet Receive Enable Also PC8 CD2 Connected to the SCC2 s CD signal Active when there is network activity When the Ethernet port is disabled via BCSR1 may be used off board for any alternate function Appears also on P8 of the M B Reserved Not used with this board System Clock In fact the CLKOUT of the MPC MPC850 s PC 10 USBRXN SAR PHY ADS One of USB transceiver s receive signals Appears also at P8 of the M B as Address Data Line 3 for the SAR PHY tool MPC850 port a 7 L1RCLKA Appears also at P8 of the M B as E1 T1 L1RCLKA for the SAR PHY tool MPC850 s PB17 SAR PHY AD 5 Appears also at P8 of the M B as Address Data Line 5 for the SAR PHY tool MPC850 PC13 SAR PHY READ Appears also at P8 of the M B as SAR PHY READ as support to the SAR PHY tool Ethernet port Transmit Enable Also PB18 RTS2 Connected to the SCC2 s RTS signal When active transmit is enabled via the MC68160 EEST on the M B When the ethernet port is disabled via BCSR1 may be used off board for any alternate function Appears also at P8 of the M B 82 ETHEN O L Ethernet Port Enable Connected to BCSR1 See TABLE 4 10 BCSR1 Description
64. ysical connection types two USB connectors are provided in parallel one of Type A and the other of Type B For additional information on USB port control see TABLE 4 23 BCSR4 Description on page 57 of the MPC8XXFADS User s Manual NOTE Release O 1 For More Information On This Product Go to www freescale com FreagscalsoSgmieonduictgr dna Functional Description In order to configure the devices on the SAR PHY board the USB port should be disabled due to dual functional ity of I O pins see table 4 1 After the configuration is done USB can be enabled and operated concurrently with the SAR PHY board 4 5 2 Ethernet Port SCC2 of the MPC may be operated as an Ethernet port Its may be connected to the ethernet transceiver on the MPC8XXFADS provided that the ETH EN bit in BCSRT is asserted and both IRD EN and RS EN2 bits in the same register are inactive See 4 9 1 Ethernet Port on page 41 and TABLE 4 10 BCSR1 De scription on page 49 of MPC8XXFADS User s Manual NOTE VO pin PA4 which is used as ETHTCK is also used as TOUT2 for the E1 T1 port in a specific configuration This is when L1TCLKA and L1TSYNCA are generated lo cally on the SAR PHY board see the SAR PHY User manual In this case the Ethernet port can t be used and therefore must be disabled 45 3 Infra Red Port SCC2 of the MPC may be operated as Fast IrDA port Its may be connected to the Fast IrDA transceiver on the MPC8XXFADS provided that the

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