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USER`S MANUAL

1. 20 11 UART Timing Characteristics in Mode 0 10MH2 a 20 12 A D Converter Electrical Characteristics 20 13 LVR Circuit Characteristics L 20 15 AC Electrical Characteristics for Internal Flash 20 15 Power Selection Settings for TB84NB sse enne 22 4 The SMDS2 Tool Selection 5 5 22 4 Using Single Header Pins to Select Operation Mode 22 5 Using Single Header Pins as The Input Path for External Trigger Sources 22 5 S3F84NB UM REV1 00 MICROCONTROLLER List of Programming Tips Description Page Number Chapter 2 Address Spaces Using the Page Pointer for RAM clear Page 0 Page 1 a u 2 7 Setting the Register Pointers esee enne nnnr nennen entes nnns sinn isis 2 11 Using the RPs to Calculate the Sum of a Series of Registers 2 12 Addressing the Common Working Register Area eee enne 2 16 Standard Stack Operations Using PUSH and POP I n n u 2 21 Chapter 11 8 Bit Timer A B C 0 1 To Generate 38kHz 1 3 duty Signal through P2 4 n nennen nns 11 9 To G
2. 14 5 UART Baud Rate Data Register BRDATAHO BRDATALO BRDATAH1 BRDATAL1 14 6 Band Rate calc latlons iie eie ehem rh onte RU Ik ERREUR ERRARE nU 14 6 Block Diagram reed need Ducem ceder alitum ied eats 14 8 UART Mode 0 Function u Sus nennen 14 9 UART Mode 1 Function Description U U enne 14 10 UART Mode 2 Function Description niic tci centre tret DERI be 14 11 Serial Communication For Multiprocessor Configrations a 14 13 Chapter 15 A D Converter OVOIVIOW cnt dit Hed dt Hg ree Ha de d a Ht au Hendin o e e Et Lg S 15 1 Funcion Descriptio REP 15 1 A D Converter Control Register ADCCON 15 2 Internal Reference Voltage 15 4 Conversion Time ide i Er ex a c qt Hr HL de a de ey Eee il cae eae 15 4 Internal A D Conversion Procedure 15 5 Chapter 16 Watch Timer OVEIVICW ziehe dta it ed ham Sum ants uq Lot ee LA 16 1 Watch Timer Control Register WTCON R W 16 2 Watch Timer Circuit Diagram L paai iath a 16 3 Chapter 17 Pattern Generation Module COVEN
3. a 17 2 17 3 Pattern Generation Circuit Diagram sse 17 2 18 1 Low Voltage Reset Circuit sss enne enne 18 2 19 1 Program Memory Address Space aaa 19 3 19 2 ER 19 4 19 3 Flash Memory Control Register FMCONJ aaa 19 6 19 4 Flash Memory User Programming Enable Register FMUSR 19 6 19 5 Flash Memory Sector Address Register FMSECH 19 7 19 6 Flash Memory Sector Address Register 19 7 19 7 Sector Configrations in User Program Mode sse 19 8 19 8 Sector Erase FlowChart in User Program Mode 19 9 19 9 Byte Program FlowChart in User Program Mode 19 13 19 10 Program FlowChart in a User Program Mode 19 14 20 1 Input Timing for External Interrupts Port4 and 6 20 5 20 2 Input Timing for 20 5 20 3 Operating Voltage Range U nennen nennt nnns 20 7 20 4 Schmitt Trigger Input Characteristics Diagram 20 7 2
4. 4 21 P3CONH Port Control Register High Byte 4 22 P3CONL Port 3 Control Register Low Byte a 4 23 P4CONH Port 4 Control Register High Byte 4 24 P4CONL Port 4 Control Register LOW Byte 4 25 P4INT Port 4 Interrupt Control Register a 4 26 P4INTPND Port 4 Interrupt Pending Register nennen 4 27 P5CONH Port 5 Control Register High Byte 4 28 P5CONL Port 5 Control Register LOW Byte a 4 29 P6CONH Port 6 Control Register High Byte 4 30 P6CONL Port 6 Control Register LOW Byte 4 31 P6INT Port 6 Interrupt Control Register a 4 32 P6INTPND Port 6 Interrupt Pending Register nennen 4 33 xviii S3F84NB_UM_REV1 00 MICROCONTROLLER List of Register Descriptions Register Full Register Name Page Identifier Number PGCON Pattern Generation Control Register 4 34 PP Register Page S a SS n Sua pana Sua Wai aa tnn 4 35 RP0 Register Poiniter 1 a u su suqu ep etre u t enu eet ae 4 36 RP1 Hegister Polnter oet idet Rn ei ea e En dai 4 36 SIOCON SIO Control Register tot em te ea ong 4 37 SIOPS SIO Pre scaler Register
5. tac oa Re INC Incremento gi INCW nereme nt Word tiet nette er eee Tout IRET Interrupt Return ty odo c nei de dua cea Eu ded JP Jump icis d a E rag dete ee E uto eg E JR Jump Helallve ice o iid Sk Sas I e ee E LD rr ED Mr EP ER T E LDB or Tool ERN EE S3F84NB UM REV1 00 MICROCONTROLLER xxi List of Instruction Descriptions Continued Instruction Full Register Name Page Mnemonic Number LDC LDE Load Ts 6 52 LDCD LDED Load Memory and Decrement sse nennen nennen nns 6 54 LDCI LDEI Load Memory and 6 55 LDCPD LDEPD Load Memory with Pre Decrement 6 56 LDCPI LDEPI Load Memory with Pre Increment 6 57 LDW LGC WOK 6 58 MULT Multiply Unsigned s y a Le ene IR ined 6 59 NEXT Nex a haapa aa ny et i 6 60 No Operation ee nd te A eee 6 61 OR P DEA 6 62 Pop ttomietaek sitse ote tute o tatu t 6 63 POPUD Pop User Stack Decrementing sse enne 6 64 POPUI Pop User Stack Incrementing essen 6 65 PUSH Push to Stack u iet tend eme te au d ER ER ee A 6 66 PUSHUD Push User Stack Decrementing
6. VO pins active Output Current Low One I O pin active Total pin current for ports 2 4 and 5 Total pin current for ports 0 1 and 6 Operating _ 40 to 85 Temperature Storage Temperature _ 6510 150 to 6510 150 150 Table 20 2 Input Output Capacitance TA 40 C to 85 C Vpp 0 V Parameter Symboi Conditions min Unit Input Capacitance f 1 MHz unmeasured pins 10 pF are tied to Vss Output Capacitance I O Capacitance 20 2 ELECTRONICS S3F84NB_UM_REV1 00 ELECTRICAL DATA Table 20 3 D C Electrical Characteristics Ta 40 C to 85 C Vpp 2 0 V to 5 5 V Parameter Symbo Conditions Wm T Mex Unit Operation Voltage Vpp Fx 21 4MHz fxt 2 32 8 kHz LVR off Fx21 4MHz fxt 32 8 kHz LVR on Fx21 10MHz 3 0 All Port and nRESET and XT All Ports and nRESET Vpp 2 0 V to 5 5 V Xin and XTN Output High Voltage Vpp 5 5 V 1 mA All Ports Output Low Voltage Vpp 5 5 V lop 15 mA Ports 0 1 and 6 Vpp 5 5 V lg 4 mA Ports 2 3 4 and 5 Input High Leakage Vin Vpp Current All input pins except ijo lude Vpp Xin and XTour Input Low Leakage ViN 0 V Current All input pins except and Vin OV Xin and XTn XTour Leakage Current All output pins Output Low Leakage lot Vour 0V Current All output pins Er d ELE
7. a 6 67 PUSHUI Push User Stack Incrementing r 6 68 RCF Reset Carry Flag aede e fe En d dao ta ed cds 6 69 RET nen tate net tate a tate nsa e bisects e ite Pu 6 70 RL Rotate Eelb on onn uapa nu Ton dod uid coe diste Dre 6 71 RLC Rotate Left through 6 72 RR Rotate Right 4i t ER CE o tp iei d 6 73 RRC Rotate Righitithrougli Garry te ath ee de D e teer t Des cte en 6 74 SBO Select Bank 0 8s re ate be eee alt 6 75 SB1 Select Bank ls a s Rete ee ee eee o ae dE ee raa ed dae des 6 76 SBC Subtract with Camry isis ir cie ee oreste Hed i de edet d oe dno P eerie 6 77 SCF SEL Canny aste totu uris 6 78 SRA Shift Aight Arithmetica e th e uet terae tet ud 6 79 SRP SRPO SRP1 Set Register PONTE u aun entren nennen 6 80 STOP Stop OPSTAUOM adeo Tes d casei 6 81 SUB SUB ACE ate tatto ua una qha ar ok 6 82 SWAP SWap NIDBIOS AEE detto dite re e ug ceste vie 6 83 TCM Test Complement under Mask ara enne 6 84 Test under Mask uite deed eie de Ale dedi ceil are E 6 85 WFI Walt for Interruplt sete tote ate te Ded a n t 6 86 XOR Eogical Exclusive Bid u ates e 6 87 xxii SSF84NB UM
8. 2 16 Stack Operation S naiinitan apaiia asii ags 3 1 Register Addressing eaii 3 2 Working Register 55 3 3 Indirect Register Addressing to Register File 3 4 Indirect Register Addressing to Program 3 5 Indirect Working Register Addressing to Register File 3 6 Indirect Working Register Addressing to Program or Data Memory 3 7 Indexed Addressing to Register File 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 9 Indexed Addressing to Program or Data Memory 3 10 Direct Addressing for Load Instructions 3 11 Direct Addressing for Call and Jump Instructions 3 12 Indirect Addressing u uu 3 13 Relative Addressing 3 14 Immediate Addressing u uu S3F84NB_UM_REV1 00 MICROCONTROLLER xi List of Figures Concluded Figure Title Page Number Number 4 1 Register Description 4 5 5 1 S3C8 Series Interrupt Types U 5 2 5 2 S3F84NB Interrupt Structure n nan 5 4 5 3 ROM Vector Address Area
9. a 19 17 Fard Lock Protection mieu ce 19 18 The Program Procedure In User Program Mode U 19 18 Chapter 20 Electrical Data Overview yat aceti odd er del tage a t dp 20 1 Chapter 21 Mechanical Data eate tene dasererat i a tad hav d a ua usa odes 21 1 Chapter 22 Development Tools TTA IL MP MT 22 1 SHINE ttr e anan o aetate i e la che oben 22 1 tis E 22 1 SAMA ASSORmDIOE iioii teach re P e ben 22 1 2 n EE 22 1 Target Boards innt ete na ed aa etie E itty tee t 22 2 IB84NB Target Board ge a s RR eee 22 3 JajBzg cp H RMR A 22 5 STOP EEDS mmt 22 5 OTP MTP Programmer Writer uu e tiit cercate niet tend eed eet 22 10 x S3F84NB_UM_REV1 00 MICROCONTROLLER List of Figures Figure Title Number 1 1 S3F84NB Block Diagram eene 1 2 SSF84NB Pin Assignment 64 pin 0 1 3 SSF84NB Pin Assignment 64 1 4 Pin Circuit Type B nRESET sse 1 5 Pin Circuit Type G ead 1 6 Pin Circuit Type D Port 0 2 3
10. 0 0 Inputmode o O 0 1 Inputmode pukuy _ K EJ Push pull output Alternative output mode T1OUT0 4 22 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER P3CONL Port 3 Control Register Low Byte F5H Set 1 Bank 0 Bit Identifier 7 6 5 A 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 3 T1CAP1 o Input mode TICAP1 1 Input mode pull up 1 1 5 4 P3 2 TICAPO 0 0 Input mode 0 1 Input mode pull up TI CAPO Push pull output 3 3 P3 1 T1CK1 o 0 Input mode T1CK1 1 Input mode pull up T1CK1 Push pull output 1 0 P3 0 T1CKO o o Input mode T1CK0 EXER Input mode pull up T1CKO ELECTRONICS 4 23 CONTROL REGISTERS S3F84NB_UM_REV1 00 PACONH Port 4 Control Register High Byte F6H Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P4 7 INT7 Fo Input mode falling edge interrupt oja Input mode rising edge interrupt K EJ Input mode pull up falling edge interrupt Push pull output 5 4 P4 6 INT6 Lo Fo t Input mode sing edge 0 input mode pul up tating edoe 3 2 P4 5 INT5 o o inputmode faling edge interu
11. De vex SiO dataregister SIODATA za o o o o o o o SOCowgrmgse zs em o o o o o o o o ARTO contol register UARTCOND 227 aH o o o o o UARTO baud rate data register igh BROATAHO 228 Ear 1 1 1 1 1 11 1 UARTO baud rate data register BRDATALO 220 X 1 1 1 1 1 1 1 Timer 10 data register byte TrDaTAHO zo E 1 1 1 1 1 1 Timer 1 0 deta register ow byte TiATA 231 Em 1 3 1 3 3 Timer 101 data register high byte TIDATAHT 22 Em 1 i Timer 10 data register dow oye HIDATALI Em r Timer 0 contol register 2 ean o o o o o o o Timer 101 contol register 23s EH o o o o o o v Timer 0 counter bve THONTHO zoe EcH o o o o 0 o o Timer 0 counter registertow bye Tiento 2a7 o o o o o o o o Timer t comer egstertah menten 2e o o fo Timer oa counter e Fr Timer C t detaregister 1 Timer 0 Tocono z EM o of ofofo TmerGtpcwweregser 24s o o o S10 prescaler control register SoPS 244 Wach merc
12. sowce paet 1 osoen ofofo ilse Prof ro Fo r t e semepxes ofii sowce pae7 Other values Don t care NOTES 1 In the S3F84NB microcontroller the internal register file is configured as eight pages Pages 0 7 The pages 0 1 are used for the general purpose register file and page 2 7 is used for data register or general purpose registers 2 When you used the SK 1000 SK 8xx MDS The BRDATAH1 BRDATAL1 of mnemonic isn t showed on the system register window of MDS application program Because the BRDATAHT1 BRDATAL is located on the general register page 8 ELECTRONICS 4 35 CONTROL REGISTERS S3F84NB_UM_REV1 00 RPO Register Pointer 0 D6H Set 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value 1 1 0 0 0 _ _ _ Read Write R W R W R W R W R W _ _ _ Addressing Mode Register addressing only 7 3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RP0 and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP0 points to address C0H in register set 1 selecting the 8 byte working register slice COH C7H 2 0 Not used for the S3F84NB RP1 Register Pointer 1 D7H Set 1 RESET Value 1 1 0 0 1 Read Write R
13. src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4 SPH 00H and SPL 00H PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register 4FH OAAH stack register OFFH OAAH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value 0000H and general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of register 40H into location OFFFFH and adds this new value to the top of the stack ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET PUSHUD Push User Stack Decrementing PUSHUD Operation Flags Format Example dst src IR IR 1 dst lt src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 3 8 82 IR R Given Register 00H 03H register 01H 05H and register 02H 1AH PUSHUD 00H 01H Register OOH 02H register 01H 05H register 02H 05H If the user stack pointer register OOH for example contains the value 03H the statement PUSHUD 00H 01H decrements the us
14. 6 233 0 O J O 1 1 1 1 1 Timer A control register TACON 234 EAH 0 0 O 0 0 O O ojo Port 0 control register POCON 239 0 0 0 0 0 0 0 Port 2 control register low byte Port 3 control register low byte PSCONL 245 F5H O JO JO O For Gio register inene SPROOMH 246 9 0 0 5 6 Port 4 control register low byte 247 5 control register high byte PSCONH 248 o o o o Port 5 control register low byte PSCONL 249 FH O O JO o Port 4 interrupt control register paint 250 FAH o o Port 4interruptipending register PAINTPND 251 0 O O JO JO o O EFH EN ro 0 0 Peat v Fas 0 c Location FCH is factory use only Basio timer data register BTCNT 253 0 0 o of o Location FEH is not mapped erup piony esr wm re xIxIx I 1 I D T ELECTRONICS 8 3 RESET POWER DOWN S3F84NB_UM_REV1 00 Table 8 3 S3F84NB Set 1 Bank 1 Register values after RESET
15. 11 5 11 4 Timer B Control Register TBCONJ U nennen nennen 11 6 11 5 Timer B Data Registers TBDATAH TBDATAL 11 6 11 6 Timer B Output Flip Flop Waveforms in Repeat Mode 11 8 11 7 Timer C1 Control Register TCCONO 11 12 11 8 Timer Functional Block Diagram 7 11 13 12 1 Timer 1 0 1 Control Register T1 CONO 1 12 4 12 2 Timer A Timer1 0 1 Pending Register TINTPND 12 5 12 3 Timer 1 0 1 Functional Block Diagram 12 6 13 1 Serial Module Control Register SIOCON seen 13 2 13 2 SIO Prescaler Register SIOPS enne nnns 13 3 13 3 SIO Functional Block Diagram nnns 13 4 13 4 SIO Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 13 5 13 5 SIO Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 13 5 13 6 SIO Timing in Receive Only Mode Rising edge 13 6 14 1 UART Control Registers UARTCONO 14 3 14 2 UART Interrupt Pending Regist
16. ELECTRONICS 19 9 EMBEDDED FLASH MEMORY INTERFACE PROGRAMMING Sector Erase Case1 Erase one sector ERASE ONESECTOR ERASE STOP 88 FMUSR 0A5H FMSECH 40H FMSECL 00H FMCON 10100001B FMUSR 00H PP 00H S3F84NB_UM_REV1 00 User program mode enable Set sector address 4000H sector 128 among sector 0 511 Select erase mode enable amp Start sector erase User program mode disable Case2 Erase flash memory space from Sector n to Sector n m 5 Pre define the number of sector to erase ERASE_LOOP 19 10 LD SecNumH 00H LD SecNumL 128 LD R6 01H LD R7 7DH LD R2 SecNumH LD R8 SecNumL CALL SECTOR_ERASE XOR P4 4H1111111B INCW RR2 LD SecNumH R2 LD SecNumL R3 DECW RR6 LD R8 R6 OR R8 R7 CP R8 00H JP NZ ERASE_LOOP Set sector number Selection the sector128 base address 4000H Set the sector range m to erase into High byte R6 and Low byte R7 Display ERASE_LOOP cycle ELECTRONICS S3F84NB_UM_REV1 00 SECTOR_ERASE NOCARRY ERASE_START ERASE_STOP ELECTRONICS R12 SecNumH R14 SecNumL RR12 80H RR14 80H R13 R14 R10 R13 R11 R15 PP 88H FMUSR 0A5H FMSECH R10 FMSECL R11 FMCON 10100001B FMUSR 00H PP 00H EMBEDDED FLASH MEMORY INTERFACE Calculation the base address of a target sector The size of one sector is 128 bytes FLAGS 7 NOCARRY INC R12 User program mode enable
17. Register Page Pointer PP Working eglsters ee e e eet epe eeu Rent epe see eta Using The Register Points Hegister Addressing uo ea hot RETI Common Working Register Area COH CFH 4 Bit Working Register Addressing 8 Bit Working Register Addressing System and User Chapter 3 Addressing Modes Overview Register Addressing Mode HR nennen enn en nnn Indirect Register Addressing Mode IR Indexed Addressing Mode X Direct Address Mode DA Indirect Address Mode nennen entren nennen Relative Address Mode RA Immediate Mode IM 53 84 UM REV1 00 MICROCONTROLLER Chapter 4 Control Registers MIRI Chapter 5 Interrupt Structure Ce eW a m ut auc E hd tate ta aed ed arn Mc E Table of Contents Continued S3F84NB Interrupt Srtucture Interrupt Vector Addresses Enable Disable Interrupt Instructions El Dl System Level Interrupt Control Registers Interrupt Processing Control Points Peripheral Interrupt Control Registers System Mode Register SYM Interrupt Mask Register IMR Interrupt Priority Register IPR Interrupt Request Register IRQ Interrupt Pending Function Types U Interrupt Source Polling Sequen
18. The following sample program structure shows the sequence of operations that follow a WFI statement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed ELECTRONICS S3F84NB_UM_REV1 00 XOR Logical Exclusive OR XOR Operation Flags Format Examples dst src dst lt dst XOR src INSTRUCTION SET The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different otherwise a bit is stored Unaffected Always reset to 0 Unaffected Unaffected IO cONO opc src dst opc dst src Set if the result is 0 cleared otherwise Set if the result bit 7 is set cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst src 2 4 B2 r r 6 B3 r Ir 3 B4 R R B5 R IR 3 6 B6 R IM Given RO 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H XOR RO R1 XOR RO R1 XOR 00H 01H XOR 00H 01H XOR OOH 54H gt EN RO 0C5H R1 02H RO OE4H R1 02H register 02H 23H Register 00H 29H register 01H 02H Register 00H 08H register 01H 02H register 02H 23H Register OOH 7FH In the first example
19. The instruction RCF clears the carry flag C to logic zero ELECTRONICS 6 69 INSTRUCTION SET S3F84NB_UM_REV1 00 RET Return RET Operation Flags Format Example PC SP SP e SP 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement that is executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex opc 1 8 internal stack AF 10 internal stack Given SP OOFCH SP 101AH and 1234 RET gt 101AH SP OOFEH The statement RET pops the contents of stack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in location OOFEH 1AH into the PC s low byte and the instruction at location 101AH is executed The stack pointer now points to memory location OOFEH ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET RL Rotate Left RL Operation dst C lt dst 7 dst 0 lt dst 7 dst n 1 lt dst n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag Flags Format Examples C Setif the bit rot
20. Flash ROM Configuration The S3F84NB flash memory consists of 512sectors Each sector consists of 128bytes So the total size of flash memory is 512x128 bytes 64KB User can erase the flash memory by a sector unit at a time and write the data into the flash memory by a byte unit at a time e 64Kbyte Internal flash memory e Sector size 128 Bytes e 10years data retention e Fast programming Time Sector Erase 10ms min Byte Program 32us min e Byte programmable e User programmable by LDC instruction e Sector 128 Bytes erase available e External serial programming support e Endurance 10 000 Erase Program cycles min e Expandable OBPTM On Board Program ELECTRONICS 19 1 EMBEDDED FLASH MEMORY INTERFACE S3F84NB_UM_REV1 00 User Program Mode This mode supports sector erase byte programming byte read and one protection mode Hard Lock Protection The SSF84NB has the internal pumping circuit to generate high voltage Therefore 12 5V into Vpp TEST pin is not needed To program a flash memory in this mode several control registers will be used There are four kind functions in user program mode programming reading sector erase and one protection mode Hard lock protection Tool Program Mode This mode is for erasing and programming full area of flash memory by external programming tools The 6 pins of S3F84NB are connected to a programming tool and then internal flash memory of 53 84 can be program
21. Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise Always set to 1 Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow lt Bytes Cycles Opcode Addr Mode Hex dst src dst 2 4 22 r r src 6 23 r Ir src dst 3 6 24 R R 25 R IR dst src 3 6 26 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register O3H OAH SUB R1 R2 gt R1 OFH R2 03H SUB R1 R2 gt R1 08H R2 03H SUB 01H 02H gt Register 01H 1EH register 02H 03H gt gt SUB 01H 02H Register 01H 17H register 02H SUB 01H 90H Register 01H 91H C S and V 1 SUB 01H 465H gt Register 01H OBCH C S 1 0 In the first example if working register R1 contains the value 12H and if register R2 contains the value 03H the statement SUB R1 R2 subtracts the source value 03H from the destination value 12H and stores the result OFH in destination register R1 ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET SWAP Swap Nibbles SWAP Operation Flags Format Examples dst dst 0 3 dst 4 7 The contents of the
22. Stand alone mode C amp A Technology TEL 82 2 2612 9027 FAX 82 2 2612 9044 E mail caat unitel co kr URL http www cnatech com International Sale SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail cindy seminix com e URL http Awww seminix com 22 10 ELECTRONICS
23. TTTTTT T INT13 INT12 INT111NT10 INT9 INT8 Not used must keep always 0 P6INT Bit Configuration Settings 0 Interrupt disable 1 Interrupt enable Figure 9 16 Port 6 Interrupt Control Register P6INT Port 6 Interrupt Pending Register P6INTPND EEH Set 1 Bank 0 R W TTITTTT T PND13 PND12 PND11PND10 PND9 PND8 Not used must keep always 0 P6INTPND Bit Configuration Settings 0 Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending Figure 9 17 Port 6 Interrupt Pending Register P6INTPND 9 24 ELECTRONICS S3F84NB_UM_REV1 00 BASIC TIMER BASIC TIMER OVERVIEW BASIC TIMER BT You can use the basic timer BT in two different ways e Asa watchdog timer to provide an automatic reset mechanism in the event of a system malfunction e Tosignal the end of the required oscillation stabilization interval after a reset or a Stop mode release The functional components of the basic timer block are e Clock frequency divider fxx divided by 4096 1024 128 or 16 with multiplexer 8 bit basic timer counter BTCNT set 1 bank 0 read only e Basic timer control register BTCON set 1 D3H read write BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 addr
24. idea ite pta str ne d fL Ea dC aaa Rae E ete LE a du 4 38 SPH Stack Pointer High Byte U nnne 4 38 SPL Stack Pointer Low Byte L L L nnne nenas 4 38 STPCON Stop Control Registe nsir Mane ea elated 4 39 SYM System Mode Register dct e tet ite ed e cre 4 40 T1CONO Timer 1 0 Control enne 4 41 T1CON1 Timer 1 1 Control Register entrent 4 42 TACON Timer A Control Register eene nnne enn nnns nnne 4 43 TBCON Timer B Control Register 4 44 TCCONO Timer C 0 Control Register sess enne nnne nens 4 45 TCCON1 Timer C 1 Control Register 4 46 TINTPND Timer A Timer 1 Interrupt Pending 4 47 UARTCONO UART 0 Control R gist ru s suls ua Qua nus nu q au usnu nia qunas humulus 4 48 UARTCON1 UART 1 Go ntrol Hegistet x c ea ian ten aet ane 4 50 UARTPND UART 0 1 Pending and Parity Control Register 4 52 WTCON Watch Timer Control Register enne enn nnne 4 54 S3F84NB UM REV1 00 MICROCONTROLLER xix List of Instruction Descriptions Instruction Full Register Name Mnemonic ADC Add with aiios Ali eae edle apis th aed A
25. 03H R1 1BH R2 03H Register 01H 24H register 02H 03H Register 01H 2BH register 02H 03H Register 01H 32H m 4 In the first example destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value 03H The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in register R1 ELECTRONICS S3F84NB_UM_REV1 00 ADD Add ADD Operation Flags Format Examples dst src dst lt dst src INSTRUCTION SET The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise Always cleared to H Set if a carry from the low order nibble occurred Bytes Cycles Opcode Addr Mode Hex dst src 6 03 r Ir opc src dst 3 6 04 R R 05 R IR opc dst src 3 6 06 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH ADD R1 R2 gt R1 15H R2 03H ADD R1 R2 gt R1 1CH R2 03H ADD 01H 02H g
26. PORTS S3F84NB UM REV1 00 Port 1 Control Register High Byte P1 CONH FOH Set 1 Bank 0 R W TECCO P1 5 ADC5 P1 6 ADC6 P1 7 ADC7 7 6 P1 7 ADC7 Input mode Input mode pull up Push pull output Alternative function ADC7 5 4 bit P1 6 ADC6 Input mode Input mode pull up Push pull output Alternative function ADC6 3 2 bit P1 5 ADC5 Input mode Input mode pull up Push pull output Alternative function ADC5 1 0 bit P1 4 ADC4 Input mode Input mode pull up Push pull output Alternative function ADC4 NOTE When use this port 1 user must be care of the pull up resistance status Figure 9 2 Port 1 High Byte Control Register PI CONH 9 6 ELECTRONICS S3F84NB_UM_REV1 00 PORTS Port 1 Control Register Low Byte P1CONL F1H Set 1 Bank 0 R W el Peel P1 1 ADC1 P1 2 ADC2 P1 3 ADC3 7 6 bit P1 3 ADC3 Input mode Input mode pull up Push pull output Alternative function ADC3 5 4 P1 2 ADC2 Input mode Input mode pull up Push pull output Alternative function ADC2 3 2 bit P1 1 ADC1 Input mode Input mode pull up Push pull output Alternative function ADC1 1 0 bit P1 0 ADCO Input mode Input mode pull up Push pull output Alternative function ADCO NOTE When use this port 1 user must be care of the pull up resistance status Figure 9 3 Port 1 Low Byte Control Register P1CONL ELECTRONICS 9 7 P
27. RPO COH C7H RP1 C8H CFH This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages Following a hardware reset register pointers RPO and RP1 point to the common working register area locations COH CFH oo T3995 oo 1998 Figure 2 11 Common Working Register Area ELECTRONICS 2 15 ADDRESS SPACES S3F84NB_UM_REV1 00 PROGRAMMING TIP Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations COH CFH using working register addressing mode only Examples 1 1 LD 0C2H 40H Invalid addressing mode Use working register addressing instead SRP 0COH LD R2 40H R2 C2H lt the value in location 40H Example 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead SRP 0COH ADD R3 45H R3 45H 4 BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8 byte slice of working register space The address information stored in a register pointer serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an instruction addresses a locat
28. S3F84NB_UM_REV1 00 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system on a turnkey basis The development support system is composed of a host system debugging tools and supporting software For a host system any standard computer that employs Win95 98 2000 as its operating system can be used A sophisticated debugging tool is provided both in hardware and software the powerful in circuit emulator SMDS2 or SK 1000 for the S3C7 S3C9 and S3C8 microcontroller families SMDS2 is a newly improved version of SMDS2 and SK 1000 is supported by a third party tool vendor Samsung also offers supporting software that includes debugger an assembler and a program for setting options SHINE Samsung Host Interface for In Circuit Emulator SHINE is a multi window based debugger for SMDS2 SHINE provides pull down and pop up menus mouse support function hot keys and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be easily sized moved scrolled highlighted added or removed SASM The SASM is a re locatable assembler for Samsung s S3C8 series microcontrollers The SASM takes a source file containing assembly language statements and translates them into a corresponding source code an object code and comments The SASM supports macros and conditional assembly It runs on the MS DOS o
29. Set sector address Select erase mode enable amp Start sector erase User program mode disable 19 11 EMBEDDED FLASH MEMORY INTERFACE S3F84NB_UM_REV1 00 PROGRAMMING A flash memory is programmed in one byte unit after sector erase The write operation of programming starts by LDC instruction The program procedure in user program mode 1 Boom Must erase target sectors before programming Set Flash Memory User Programming Enable Register FMUSR to 10100101B Set Flash Memory Control Register FMCON to 0101000 Set Flash Memory Sector Address Register FMSECH and FMSECL to the sector base address of destination address to write data Load a transmission data into a working register Load a flash memory upper address into upper register of pair working register Load a flash memory lower address into lower register of pair working register Load transmission data to flash memory location area on LDC instruction by indirectly addressing mode Set Flash Memory User Programming Enable Register FMUSR to 00000000B NOTE In programming mode it doesn t care whether FMCON O s value is 0 or 1 19 12 ELECTRONICS S3F84NB_UM_REV1 00 FMSECH lt High Address of Sector FMSECL lt Low Address of Sector High Address to Write lt Low Address to Write 8 bit Data FMUSR 5 FMCON lt 01010000B LDC 4 RR n R data FMUSR 00H Finish 1 BYTE Wri
30. System Probe Adapter gt Trace Timer Unit TB84NB gt SAM8 Base Unit Target Board EVA 4 Power Supply Unit Chip Figure 22 1 SMDS or SK 1000 Product Configuration 22 2 ELECTRONICS S3F84NB_UM_REV1 00 DEVELOPMENT TOOLS TB84NB TARGET BOARD The TB84NB target board is used for the S3F84NB microcontroller It is supported by the SMDS2 or SK 1000 development system In Circuit Emulator Figure 22 2 TB84NB Target Board Configuration TB84NB To User_Vcc Idle Stop a 74HC11 gt d 2 144 QFP S3E8480 EVA Chip xs e g o c c o oa 40 Pin Connector 40 Pin Connector External CH1 Triggers X al 32kHz TEST MODE CH2 ON ON RUN MODE SMDS2 SMDS2 SM13XXA Figure 22 2 S3F84NB Target Board Configuration NOTE Thecircle or rectangle filled in black means the default position of jumpers or switches ELECTRONICS 22 3 DEVELOPMENT TOOLS S3F84NB_UM_REV1 00 Table 22 1 Power Selection Settings for TB84NB To User_Vcc Settings Operating Mode Comments SMDS2 or SK 1000 supplies TB84NB Vpp to the target board Target i T evaluation chip and the target system To User_VDD SMDS2 or SK 1000 supplies External Vpp only to the target board VDD gt ed evaluation chip The target Vss gt system must have a power supply of its own To User_VDD SMDS2 or SK 1000 NOTE The following symbol in
31. 1 r2 RR RR LDCD LDCI LD LD LD LDC R1 IR1 r1 Irr2 R2 R1 R2 IR1 R1 IM r1 Irr2 xs F SWAP SWAP LDCPD LDCPI CALL LD CALL LDC R1 IR1 r2 lrr1 IRR1 IR2 R1 DA1 r2 Irr1 xs 6 10 ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET Table 6 5 Opcode Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX L 9 a p E F U LD LD DJNZ JR LD JP INC r1 R2 r2 R1 r1 RA cc RA r1 IM cc DA i J E WEI R SBO SB1 l pes iR L RET B ELECTRONICS 6 11 INSTRUCTION SET S3F84NB_UM_REV1 00 CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes mamami 0000 Always false 1000 T Always true 0111 1111 note Carry note No carry I 0110 note 1110 note Not zero 1101 Plus 0101 Minus 0100 Overflow 1100 No overflow 0110 note Equal 1110 note Not equal 1001 Greater than or equal 0001 Less than Zero N II ll O O O O a S S V V
32. 1 x 4 LD SIOCON 2CH Internal clock MSB first transmit receive mode Select falling edges to start shift operation Clear 3 bit counter and start shifting Disable SIO interrupt El SIOtest LD R6 SIOCON To check whether transmit and receive is finished BTJRF SlOtest R6 0 Check pending bit NOP AND SIOCON 0FEH Pending clear by software LD RDATA SIODATA Load received data to RDATA SBO ELECTRONICS 13 7 S3F84NB_UM_REV1 00 UART O 1 UART 0 1 OVERVIEW The UART block has a full duplex serial port with programmable operating modes There is one synchronous mode and three UART Universal Asynchronous Receiver Transmitter modes e Serial with baud rate of fxx 16 x 16bit BRDATA 1 e 8 bit UART mode variable baud rate fxx 16 x 16bit BRDATA 1 e 9 bit UART mode variable baud rate fxx 16 x 16bit BRDATA 1 e 9 bit UART mode variable baud rate fxx 16 x 16bit BRDATA 1 UART receive and transmit buffers are both accessed via the data register is set 1 bank 1 at address E2H UDATAMt is set 1 bank 1 at address FAH Writing to the UART data register loads the transmit buffer reading the UART data register accesses a physically separate receive buffer When accessing a receive data buffer shift register reception of the next byte can begin before the previously received byte has been read from the receive register However if the first byte has not been read by the time the n
33. 2 N gt lt OR 0 1 1010 0010 1111 note 0111 note 1011 0011 5 Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than Unsigned less than or equal NN 0 gt V 0 V 1 O O C 0 AND Z 0 1 C OR Z 1 1 It indicates condition codes that are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used after a CP instruction however EQ would probably be used 2 Foroperations involving unsigned numbers the special condition codes UGE ULT UGT and ULE must be used ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set Information is arranged in a consistent format for improved readability and for fast referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s form
34. 4 24 A D converter data register High Byte 24 A D converter data register Low Byte 249 ELECTRONICS 4 3 CONTROL REGISTERS S3F84NB_UM_REV1 00 Table 4 4 Page 8 Registers Register Name Mnemonic Decimal Hex R W UART1 baud rate data register BRDATAH1 o RW UART1 baud rate data register BRDATAL1 RAN Flash memory sector address register High byte FMSECH AN Flash memory sector address register Low byte FMSECL Flash memory user programming enable register FMUSR Flash memory control register FMCON NOTE When you use the SK 1000 SK 8xx MDS The BRDATAH BRDATAL of mnemonic isn t showed on the system register window of MDS application program Because the BRDATAH BRDATAL is located on the general register page 8 4 4 ELECTRONICS S3F84NB_UM_REV1 00 Bit number s that is are appended to the register name for bit addressing Register ID FLAGS System Flags Register Bit Identifier RESET Value Read Write Bit Addressing Mode 7 R Read only W Write only R W Read write Not used Type of addressing that must be used to address the bit 1 bit 4 bit or 8 bit ELECTRONICS CONTROL REGISTER Name of individual bit or related bits Register location Register address in the internal Register name hexadecimal register file D5H Set 1 y s s 4 3 2 3 9 x x x x x x 0 0 R W R W R W R W R W R R W Register addressing modd only R W Carry Flag C ES
35. Input mode TACK Input mode pull up TACK Push pull output Alternative function Not used 1 0 P2 4 TBPWM Input mode Input mode pull up Push pull output Alternative function TBPWM NOTE When use this port 2 user must be care of the pull up resistance status Figure 9 4 Port 2 High Byte Control Register P2CONH ELECTRONICS 9 9 PORTS S3F84NB UM REV1 00 Port 2 Control Register Low Byte P2CONL F3H Set 1 Bank 0 R W TL 2 1 51 2 2 5 P2 3 BUZOUT 7 6 bit P2 3 BZOUT Input mode Input mode pull up Push pull output Alternative output mode BZOUT 5 4 bit P2 2 SCK Input mode SCK input Input mode pull up SCK input Push pull output Alternative output mode SCK output 3 2 bit P2 1 SI Input mode SI Input mode pull up Sl Push pull output Alternative output mode Not used 1 0 bit P2 0 SO Input mode Input mode pull up Push pull output Alternative output mode SO NOTE When use this port 2 user must be care of the pull up resistance status Figure 9 5 Port 2 Low Byte Control Register P2CONL 9 10 ELECTRONICS S3F84NB_UM_REV1 00 PORTS PORT 3 Port is an 8 bit I O port that can be used for general purpose digital I O The pins are accessed directly by writing or reading the port data register at location E3H in set 1 bank 0 P3 7 P3 0 can serve as inputs outputs push pull or you c
36. Interrupt pending 2 Timer 1 0 Match Capture Interrupt Pending Bit EN No interrupt pending ES Clear pending bit when write Interrupt pending 1 Timer A Overflow Interrupt Pending Bit EN No interrupt pending EJ Clear pending bit when write Interrupt pending 0 Timer A Match Capture Interrupt Pending Bit ES No interrupt pending EJ Clear pending bit when write Interrupt pending ELECTRONICS 4 47 CONTROL REGISTERS UARTCONO Bit Identifier RESET Value Read Write Addressing Mode 7 6 4 48 S3F84NB UM REV1 00 UARTO Control Register ESH Set 1 Bank 1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only Operating Mode and Baud Rate Selection Bits 0 o Mode 0 Shite register fxx 16 16bit BRDATA 1 1 Mode 1 8 bit UART fxx 16 x 16bit BRDATA 1 1 Mode 2 9 bit UART fxx 16 x 16bit BRDATA 1 Mode 3 9 bit UART fxx 16 x 16bit BRDATA 1 Multiprocessor Communication Enable Bit for modes 2 and 3 only O Serial Data Receive Enable Bit If Parity disable mode 0 location of the 9th data bit to be transmitted in UARTO mode 2 or 3 0 or 1 If Parity enable mode PENO 1 even odd parity selection bit for transmit data in UARTO mode 2 or 3 0 Even parity bit generation for transmit data 1 Odd parity bit generation for transmit data If Parity disable PEN
37. No error Parity error 5 UARTO Parity Enable Disable PENO Disable Enable 1 4 UARTO Receive Parity Error RPEO No error 1 Parity error 3 UART1 Receive Interrupt Pending Flag Not pending Clear pending bit when write Interrupt pending Not pending Clear pending bit when write Interrupt pending 4 52 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER UARTPND UARTO 1 Pending and parity control Continued FCH Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 0 UARTO Transmit Interrupt Pending Flag Not pending EN Clear pending bit when write Interrupt pending NOTES 1 In order to clear a data transmit or receive interrupt pending flag you must write a 0 to the appropriate pending bit 2 To avoid programming errors we recommend using load instruction except for LDB when manipulating UARTPND values 3 Parity enable and parity error check can be available in 9 bit UART mode Mode 2 3 only 4 Parity error bit RPEO RPE1 will be refreshed whenever 8th receive data bit has been shifted ELECTRONICS 4 53 CONTROL REGISTERS S3F84NB_UM_REV1 00 WTCON Watch Timer Control Register F5H Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Watc
38. UARTO parity enable disable 1 Interrupt pending 0 Disable 1 Enable UART1 transmit interrupt pending flag 0 Not pending 0 Clear pending bit when write 1 Interrupt pending UARTO receive parity error 0 No error 1 Parity error UART1 receive interrupt pending flag 0 Not pending 0 Clear pending bit when write 1 Interrupt pending NOTES 1 In order to clear a data transmit or receive interrupt pendingflag you must write a to the appropriate pending bit A 0 has no effect To avoid errors we recommend using load instruction except for LDB when manipulating UARTPND values Parity enable and parity error check can be available in 9 bit UART mode Mode 2 3 only Parity error bit RPEO RPE1 will be refreshed whenever 8th receive data bit has been shifted Figure 14 2 UART Interrupt Pending Register UARTPND 14 4 ELECTRONICS S3F84NB_UM_REV1 00 UART O 1 In mode 2 and 3 9 bit UART data by setting the parity enable bit PENO PEN1 of UARTPND register to 1 the 9 data bit of transmit data will be an automatically generated parity bit Also the 9 data bit of the received data will be treated as a parity bit for checking the received data In parity enable mode PENO 1 UARTCONO 3 TB8 UARTCONO 2 RB8 will be a parity selection bit for transmit and receive data respectively The UARTCONO 3 8 is for settings of the even parity generation TB8 0 or the odd parity g
39. address added to offset Value used in Instruction The values in the program address RR2 1000H Identical operation to LDC example except that external program memory is accessed Figure 3 9 Indexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES S3F84NB_UM_REV1 00 DIRECT ADDRESS MODE DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Used Upper Address Byte Lower Address Byte O or 1 lt _ LSB Selects Program OPCODE Memory or Data Memory 0 Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H ldentical operation to LDC example except that external program memory is accessed Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS S3F84NB_UM_REV1 00 ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Memory Address Used Up
40. cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 AO RR Al IR Given RO 1AH R1 02H register 02H OFH and register 03H OFFH INCW RRO gt RO 1AH R1 03H INCW R1 gt Register 02H 10H register O3H 00H In the first example the working register pair RRO contains the value 1AH in register RO and 02H in register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value in register R1 In the second example the statement NCW R1 uses Indirect Register IR addressing mode to increment the contents of general register from OFFH to 00H and register 02H from OFH to 10H A system malfunction may occur if you use a Zero Z flag FLAGS 6 result together with an INCW instruction To avoid this problem we recommend that you use INCW as shown in the following example LOOP INCW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS 6 45 INSTRUCTION SET S3F84NB_UM_REV1 00 IRET Interrupt Return IRET Operation Flags Format Example IRET Normal IRET Fast FLAGS lt SP PC lt IP SP lt SP 1 FLAGS lt FLAGS PC lt SP FIS 0 SP SP 2 SYM 0 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one
41. dst dst 1 The contents of the destination operand are incremented by one Unaffected Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Set if arithmetic overflow occurred cleared otherwise Unaffected Unaffected TOSONO Bytes Cycles Opcode r 0toF Hex dst opc 1 4 rE opc dst 2 4 20 21 Given RO 1BH register and register 1BH OFH INC RO gt RO 1CH INC 00H gt Register OOH ODH INC RO gt RO 1BH register 01H 10H S3F84NB_UM_REV1 00 Addr Mode dst r In the first example if destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register OOH assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of register 1BH from OFH to 10H ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET INCW Increment Word INCW Operation Flags Format Examples NOTE dst dst lt dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred
42. if working register RO contains the value 0C7H and if register R1 contains the value 02H the statement XOR RO R1 logically exclusive ORs the R1 value with the RO value and stores the result 0C5H in the destination register RO ELECTRONICS 6 87 S3F84NB_UM_REV1 00 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The clock frequency generated for the Main clock of 53 84 by an external crystal can range from 1 MHz to 12 MHz The maximum CPU clock frequency is 12 MHz The Xi and pins connect the external oscillator or clock source to the on chip clock circuit Also the subsystem clock frequency for the Watch timer by an external crystal can range from 30 kHz to 35 kHz The and XTour pins connect the external oscillator or clock source to the on chip clock circuit The sub system oscillation pins XT and can be used for normal digital I O pins P6 0 P6 1 if they are not used for oscillation pins SYSTEM CLOCK CIRCUIT The system clock circuit has the following components e External crystal or ceramic resonator oscillation source or an external clock source e Oscillator stop and wake up functions e Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 e System clock control register CLKCON e Oscillator control register OSCCON and STOP control register STPCON XTIN P6 0 S3F84NB XTouT P6 1 32 768 kHz Figure 7 1 Main Oscillator Circuit Figure 7 2 Sub System Oscillato
43. lt dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC Flags No flags are affected Format 1 Bytes Cycles Opcode Addr Mode 2 Hex dst dst 3 8 ccD DA cc 0to F dst 2 8 30 IRR NOTES 1 The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 Inthe first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL W LABEL 1000H PC 1000H JP 00H gt PC 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement JP C LABEL_W replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement JP 00 replaces the contents of the PC with the contents of the register pair 00 and 01H leaving the value 0120H ELECTRONICS 6 47 INSTRUCT
44. operating modes Interval mode capture mode and PWM mode e 8 bit timer counter Timer B could also be used as a carrier frequency or PWM generator S3F84NB UM REV1 00 e 8 bit timer counter timer C 0 1 with two operating modes interval mode and PWM mode e 16 bit timer counter Timer 1 0 1 with three operating modes Interval mode Capture mode and PWM mode Watch timer Interval Time 3 19ms 0 255 0 55 1 0s at 32 768 kHz 0 5 1 2 4 kHz buzzer output selectable A D Converter e Eight analog input channels 10 bit conversion resolution e 20us conversion speed at 10MHz clock Asynchronous UART Programmable baud rate generator Supports serial data transmit receive operations with 8 bit 9 bit in UART module Synchronous SIO 8 bit transmit receive mode 8 bit receive mode e Selectable baud rate or external clock source Pattern Generation Module Pattern generation module triggered by timer match signal and Software Built in RESET circuit LVR Low Voltage detector for safe reset Operating Temperature Range e 407C to 85 C Operating Voltage Range e 2 0 V to 5 5 V 1 4MHz LVR disabled e LVRto5 5V 1 4MHz LVR enabled 8 01055V 1 10MHz Package Type e 64 pin QFP 64 pin SDIP ELECTRONICS S3F84NB_UM_REV1 00 PRODUCT OVERVIEW BLOCK DIAGRAM ADCO ADC7 PO O P0 7 AVss P1 0 P1J7 Xin XTin gt Xout XTout OSC nRES
45. 0 to 1 This allows interrupts to be serviced as they occur assuming they have highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the El instruction No flags are affected Bytes Cycles Opcode Hex 1 4 9F Given SYM 00H El Ifthe SYM register contains the value 00H that is if interrupts are currently disabled the statement El sets the SYM register to 01H enabling all interrupts is the enable bit for global interrupt processing ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET ENTER Enter ENTER Operation SP lt SP 2 SP lt IP IP lt lt IP IP lt IP 2 This instruction is useful when implementing threaded code languages The contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows one example of how to use an ENTER statement Before After Address IP Address Data PC Enter Enter 1F Address H Address H 01 Address L Address L 10 SP 0022 Address H Address H Routine Memory Memory 22 Data T
46. 1 4 read write 3 bit serial clock counter Serial data I O pins P2 0 P2 1 SO SI External clock input output pin P2 2 SCK The SIO module can transmit or receive 8 bit serial data at a frequency determined by its corresponding control register settings To ensure flexible data transmission rates you can select an internal or external clock source PROGRAMMING PROCEDURE To program the SIO modules follow these basic steps 1 Configure P2 1 P2 0 and P2 2 to alternative function 51 SO SCK for interfacing SIO module by setting the P2CONL register to appropriately value Load an 8 bit value to the SIOCON control register to properly configure the serial module In this operation SIOCON 2 must be set to 1 to enable the data shifter For interrupt generation set the serial I O interrupt enable bit SIOCON 1 to 1 To transmit data to the serial buffer write data to SIODATA and set SIOCON 3 to 1 then the shift operation starts When the shift operation transmit receive is completed the SIO pending bit SIOCON 0 is set to 1 and an SIO interrupt request is generated ELECTRONICS 13 1 SERIAL I O PORT S3F84NB_UM_REV1 00 SIO CONTROL REGISTER SIOCON The control register for the serial I O interface module SIOCON is located in set 1 bank 1 at address E1H It has the control settings for SIO module Clock source selection internal or external for shift clock Interrupt enable Edge selection
47. 1 Bank 0 Bit Identifier 7 6 5 A 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P5 3 RxD0 Input mode RxD0 input Input mode pull up RxDO input Ears Push pull output Alternative output RxDO output 5 4 P5 2 TxDO oo fmm o i a o fP 3 2 P5 1 RxD1 mamo or Fo putru Dime 1 0 P5 0 TxD1 ofo mame Fo K EJ Push pull output Alternative output TxD1 output ELECTRONICS 4 29 CONTROL REGISTERS S3F84NB_UM_REV1 00 P6CONH Port 6 control Register High Byte E8H Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 6 4 30 Register addressing mode only P6 7 INT13 Lo Input mode falling edge interrupt Input mode rising edge interrupt KE EJ Input mode pull up falling edge interrupt Push pull output P6 6 INT12 Lo inpatmode faling edge nian 1 Input mode sing edge intorupt 0 input mode pukun tating edge P6 5 INT11 o o inputmode faling edge interupt ooo i Input mode rising edge interrupt 1 0 input mode pul up faling edge interupt P6 4 INT10 ajo Input mode falling edge interrupt oj
48. 39 40 Figure 22 6 TB84NB Adapter Cable for 64 SDIP Package ELECTRONICS S3F84NB_UM_REV1 00 DEVELOPMENT TOOLS SAMSUNG provides a complete line of development tools for SAMSUNG s microcontroller With long experience in developing MCU systems our third parties are leading companies in the tool s technology SAMSUNG In circuit emulator solution covers a wide range of capabilities and prices from a low cost ICE to a complete system with an OTP MTP programmer Series In Circuit Emulator e OPENice i500 e SMART Kit OTP MTP Programmer e SPW 2 e BlueChips Combi e GW PRO2 Development Tools Suppliers Please contact our local sales offices on how to get MDS tools Or contact the 3rd party tool suppliers directly as shown below 8 bit In Circuit Emulator OPENice i500 AlJI System TEL 82 31 223 6611 e FAX 82 331 223 6613 e E mail openice aijisystem com URL http Awww aijisystem com SMART Kit amp Technology e TEL 82 2 2612 9027 e FAX 82 2 2612 9044 e E mail caat unitel co kr URL http www cnatech com ELECTRONICS 22 9 DEVELOPMENT TOOLS OTP MTP PROGRAMMER WRITER S3F84NB_UM_REV1 00 SPW2 Single PROM OTP FLASH MTO Programmer e Download Upload and data edit function e PC based operation with RS232C port e Full function regarding OTP programmer Read Program Verify Blank Protection Fast programming speed 1Kbyte sec Support all of
49. 8 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 _ _ 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Flash Memory Mode Selection Bits 0101 Programming mode 0110 Hard Lock mode Others Not used for S3F84NB 3 Not used for S3F84NB 0 Flash operation Start Bit available for Erase and Hard Lock mode only Operation stop bit Operation start bit auto cleared FMSECH Fiash Memory Sector Address Register High byte 02H Page 8 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory Sector Address High Byte Note The high byte flash memory sector address pointer value is the higher eight bits of the 16 bit pointer address 4 10 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER FMSECL Flash Memory Sector Address Register Low byte 03H Page 8 Bit Identifier 7 6 5 A 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory Sector Address Low Byte Note The low byte flash memory sector address pointer value is the lower eight bits of the 16 bit pointer address FMUSR Flash Memory User Programming Enable Register 04H Page 8 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Register addressing mode only Addressing Mode 7 0 Flash Memor
50. 8 1 S3F84NB Set 1 Register values after RESET MERA BT ME Dec Hx 7 6 5 4 3 2 1 0 Hmeenmiegse econ ze o o o o o Basic imer convoi register eroon o o o o o o o Cock me oaa o o o o o o o o system fags register 2 osa x x x x x o 0 me aa memepomri me ais om 1 o ols mteruptrequestregiser ma zm o System mode register Sw ze oo x x o 9 Register page porter Fe 8 2 ELECTRONICS S3F84NB_UM_REV1 00 RESET and POWER DOWN Table 8 2 S3F84NB Set 1 Bank 0 Register values after RESET ee ME 7 1 9 Port 0 data register Po 224 EH 0 ojo o Portidaargister P 1225 EH 0 Port 2 data register 1226 EH 0 0 oO PPot3daaregister Pa 227 EH PPot4dataregister P4 228 EH 0 0 ojo o PPotSdaaregister Ps 1229 EH 0 0 o TINTPND Port 6 data register Pe 230 0 TINTPND 231 0 o Port 6 control register high byte PECONH 232 EH 0 o o o Port 6 control register low byte
51. Addressing RPO RP1 orria Selects RPO R6 OPCODE Register nemici 01110 110 address 0140 76H Figure 2 13 4 Bit Working Register Addressing Example ELECTRONICS 2 17 ADDRESS SPACES S3F84NB_UM_REV1 00 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100B This 4 bit value 1100B indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 14 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address The three low order bits of the complete address are provided by the original instruction Figure 2 15 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 3 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three
52. Always Logic 0 Start or Enable bit 0 Disable Operation 1 Start Operation A D Input Pin S election bits A D Input pin Clock Selection bit Conversion Clock End of Conversion bit realy only 0 Conversion not complete 1 Conversion complete Figure 15 1 A D Converter Control Register ADCON 15 2 ELECTRONICS S3F84NB_UM_REV1 00 A D CONVERTER Conversion Data Register High Byte ADDATAH F8H Set 1 Bank 1 Read only 5 4 2 1 Conversion Data Register Low Byte ADDATAL F9H Set 1 Bank 1 Read only 1 Figure 15 2 A D Converter Data Register ADDATAH ADDATAL ADCON 4 6 Select one input pin of the assigned T To ADCON 3 EOC Flag Clock M fxx 4 Selector fxx ADCON O ADC Enable Analog Comparator Successive Approximation Logic Input Pins ADC0 ADC7 P1 0 P1 7 ADCON 0 A D Conversion enable 10 bit result is loaded into A D Conversion Data Register 0oxo o c hi Conversion Result 10 bit D A ADDATAH Converter ADDATAL To Data bus Figure 15 3 A D Converter Circuit Diagram ELECTRONICS 15 3 A D CONVERTER S3F84NB_UM_REV1 00 INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain within the range AVss to Vpop Different refe
53. B interrupt at programmed time intervals e Togenerate a programmable carrier pulse for a remote control signal at P2 4 BLOCK DIAGRAM TBCON 6 7 TBCON 2 PG trigger signal TBCON 0 f xx 4 gt M b CLK 8 Bit TBPWM P2 4 f 64 Down Counter I Underflow fxx 256 gt TBUF TBCON 1 Repeat Control TBCON 3 TBCON 4 5 Timer B Data Timer B Data Low Byte Register High Byte Register Data Bus Data Bus NOTE In case of setting TBCON 5 4 at 10 the value of the TBDATAL register is loaded into the 8 bit counter when the operation of the timer B starts And then if a underflow occurs in the counter the value of the TBDATAH register is loaded into the value of the 8 bit counter However if the next borrow occurs the value of the TBDATAL register is loaded into the value of the 8 bit counter To output TBPWM as carrier wave you have to set 2 1 0 as 11 Figure 11 3 Timer B Functional Block Diagram ELECTRONICS 11 5 8 BIT TIMER A B C 0 1 S3F84NB_UM_REV1 00 TIMER B CONTROL REGISTER TBCON Timer B Control Register TBCON DOH Set 1 Bank 0 R W gt Timer input clock selection bit Timer B output flip flop 00 fxx 4 control bit 01 fxx 8 0 T FF is low 10 fxx 64 1 T FF is high 11 fxx 256 Timer B mode selection bit Timer B interrupt time selection bit 0 One shot mode 00 Elapsed time for low data value 1 Repeating mode 01 Elapsed time
54. Data Bus NOTES 1 When PWM mode match signal cannot clear 2 Pending bit is located at TINTPND register 16 bit Timer Buffer S3F84NB UM REV1 00 T1CON 0 Overflow TINTPND Clear T1CON 2 T1CON 1 TINTPND T1OUT T1PWM M U X T1CON 4 3 PG output signal Timer 1 0 only counter Figure 12 3 Timer 1 0 1 Functional Block Diagram ELECTRONICS S3F84NB_UM_REV1 00 16 BIT TIMER 1 0 1 PROGRAMMING TIP Using the Timer 1 0 ORG 0000h VECTOR 0C8h TIM1 INT ORG 0100h INITIAL LD SYM 00h Disable Global Fast interrupt LD IMR 00001000b Enable IRQ3 interrupt LD SPH 00000000b Set stack area LD SPL 00000000b LD BTCON 10100011b Disable Watch dog SB1 LD T1CONO 01000110b Enable interrupt fxx 64 Interval Interval 1 536 ms 10 MHz x tal LDW T1DATAHO 00FO0h T1IDATAHO 00h T1DATALO FOh SBO EI MAIN MAIN ROUTINE JR T MAIN TIM1_INT e e Interrupt service routine IRET END ELECTRONICS 12 7 S3F84NB_UM_REV1 00 SERIAL I O PORT SERIAL I O PORT OVERVIEW Serial module SIO can interface with various types of external devices that require serial data transfer SIO has the following functional components SIO data receive transmit interrupt IRQ4 vector DOH generation 8 bit control register SIOCON set 1 bank 1 E1H read write Clock selection logic 8 bit data buffer SIODATA set 1 bank 1 EOH read write 8 bit prescaler SIOPS set 1 bank
55. H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 63 r Ir src dst 3 6 64 R R 65 R IR dst src 3 6 66 R IM Given RO 0C7H R1 02H R2 12H register 2BH register 01H 02H and register 02H 23H TCM RO R1 TCM R0 R1 TCM 00H 01H TCM 00H 01H RO 0C7H R1 02H Z 1 RO 0C7H R1 02H register 02 23H Z 0 Register 00H 2BH register 01H 02H Z 1 Register 2BH register 01H 02H register 02H 23H Z 1 TCM 00H 34 gt Register 00H 2BH Z 0 5 E 5 E In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TCM RO0 R1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET TM Test Under Mask TM Operation Flags Format Examples dst src dst AND src This instruction tests selected bits in the destination operand for a logic zero value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Set if the result
56. Les ace 9 2 go 9 3 EH 9 5 PO aaa kunay CENE ine fe LI o 9 8 POE rei cit dedi te te aaa AA 9 11 PORA 9 14 mlt ECC 9 18 Port 6242 inta ee p a tatus adieu eet terae een e t top Ai He RU ade 9 21 53 84 UM REV1 00 MICROCONTROLLER vii Table of Contents Concluded Chapter 10 Basic Timer OVOIVIOW t feti ion hte A al o dte tai Conte 10 1 Basic Timer Duy sa op uses PR e 10 1 Basic Timer Control Register BTCONJ aa 10 1 Basic Timer Function Description u a 10 3 Chapter 11 8 Bit Timer A B C 0 1 8 bit Timer A iunii ovt e eH ed aaa a d Hd ae dee eet eek 11 1 OI A RET 11 1 Function DescriptlODo Site tl e du 11 2 Timer A Control Register TACON 11 3 Block Diagram file 11 4 So MEINTE uu ua OE 11 5 OVOIVIOW Edge aac ed e edv le e aa eg ee aqu a e dea dede 11 5 Block Di gra z us aun any y hate a cibi eta 11 5 Timer B Control Register TBCON 0 c cecsceceeeeeeeeeeeeeeeeeeeeeceaeeeeaaeeseeeeecaaeeesaaesee
57. Low voltage reset VLVR MAX VLVR VLVR MIN Figure 20 11 LVR Reset Timing Table 20 14 AC Electrical Characteristics for Internal Flash ROM TA 25 C to 85 Programming Time Ftp 6 uS o Fe 099 Times te 6 les NOTES 1 The programming time is the time during which one byte 8 bit is programmed 2 The Sector erasing time is the time during which all 128 bytes of one sector block is erased 3 Inthe case of S3F84NB the chip erasing is available in Tool Program Mode only ELECTRONICS 20 15 S3F84NB_UM_REV1 00 MECHANICAL DATA 2 1 MECHANICAL DATA OVERVIEW The S3F84NB microcontrollers are available in a 64 SDIP 750 64 QFP 1420F package 64 SDIP 750 17 00 0 20 58 20 MAX 57 80 0 20 1 778 lcm 5 08 MAX V MT 1 34 0 51 MIN NOTE Dimensions in millimeters Figure 21 1 64 SDIP 750 Package Dimensions ELECTRONICS 21 1 MECHANICAL DATA S3F84NB_UM_REV1 00 23 90 0 30 20 00 0 20 0 10 64 QFP 1420F a 0 10 MAX 17 90 0 30 14 00 0 20 Ri 0 05 MIN H 2 65 x 0 10 3 00 MAX 0 80 0 20 gt NOTE Dimensions are in millimeters Figure 21 2 64 QFP 1420F Package Dimensions ELECTRONICS
58. Mode Hex dst src opc dst 3 6 47 Rb ro NOTE In the second byte of the instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given RO 06H and general register 05H LDB RO 00H 2 gt RO 07H register 00H 05H LDB 00H 0 R0 gt RO 06H register 00H 04H In the first example destination working register RO contains the value 06H and the source general register 00H the value 05H The statement LD R0 00H 2 loads the bit two value of the OOH register into bit zero of the RO register leaving the value 07H in register RO In the second example is the destination register The statement LD 00H 0 RO loads bit zero of register RO to the specified bit bit zero of the destination register leaving 04H in general register OOH ELECTRONICS 6 51 INSTRUCTION SET LDC LDE Load Memory LDC LDE dst src Operation dst lt src S3F84NB_UM_REV1 00 This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes or values an even number for program memory and odd an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 1 opc dst src 2 10 C3 r Irr 2 src dst 2 10 D3 Irr r 3 dst src 3 12 E7 r XS
59. R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP Control Bits 10100101 Enable stop instruction Other values Disable stop instruction NOTE Before execute the STOP instruction You must set this STPCON register as 10100101b Otherwise the STOP instruction will not be executed ELECTRONICS 4 39 CONTROL REGISTERS S3F84NB_UM_REV1 00 SYM System Mode Register DEH Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 _ _ x x x 0 0 Read Write _ _ _ R W R W R W R W R W Addressing Mode Register addressing mode only 7 Not used But you must keep always 0 6 and 5 Not used for S8F84NB 4 2 Fast Interrupt Level Selection Bits 1 Fast Interrupt Enable Bit ES Disable fast interrupt processing Enable fast interrupt processing 0 Global Interrupt Enable Bit note Disable global interrupt processing Enable global interrupt processing NOTE Following a reset you enable global interrupt processing by executing an El instruction not by writing a 1 to SYM 0 4 40 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER T1CONO Timer 1 0 Control Register EAH Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer 1 0 Input Clock Selection Bits ofo ws Fo r o mem o i ije S SOS 1 0 1 extem
60. RAM clear Page 0 Page 1 LD PP 00H Destination 0 Source lt 0 SRP 0COH LD RO 0FFH Page 0 RAM clear starts RAMCLO CLR RO DJNZ RO RAMCLO CLR RO RO 00H LD PP 10H Destination 1 Source lt 0 LD RO 0FFH Page 1 RAM clear starts RAMCL1 CLR ORO DJNZ RO RAMCL1 CLR ORO RO 00H ELECTRONICS 2 7 ADDRESS SPACES S3F84NB_UM_REV1 00 REGISTER SET 1 The term set 7 refers to the upper 64 bytes of the register file locations COH FFH The upper 32 byte area of this 64 byte space EOH FFH is expanded two 32 byte register banks bank 0 and bank 1 The set register bank instructions SBO or SB1 are used to address one bank or the other A hardware reset operation always selects bank 0 addressing The upper two 32 byte areas bank 0 and bank 1 of set 1 EOH FFH contain 64 mapped system and peripheral control registers The lower 32 byte area contains 16 system registers DOH DFH and a 16 byte common working register area COH CFH You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that i
61. REV1 00 MICROCONTROLLER S3F84NB_UM_REV1 00 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 SERIES MICROCONTROLLERS Samsung s S3C8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes The major CPU features are e Efficient register oriented architecture e Selectable CPU clock sources e Idle and Stop power down mode released by interrupt or reset e Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum of four CPU clocks can be assigned to specific interrupt levels S3F84NB MICROCONTROLLER The S3F84NB single chip CMOS microcontrollers are fabricated using the highly advanced CMOS process technology based on Samsung s latest CPU architecture The SSF84NB is a microcontroller with 64K byte flash memory embedded Using a proven modular design approach Samsung engineers have successfully developed the SSF84NB by integrating the following peripheral modules with the powerful SAM8 core e Seven programmable I O ports including seven 8 bit ports for a total of 56 pins e Fourteen bit programmable pins for external interrupt e One 8 bit basic timer for oscillation stabilization and watchdog function system reset e Four 8 bit timer counter and two 16 bit time
62. about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack operations Chapter 3 Addressing Modes contains detailed descriptions of the addressing modes that are supported by the SSF8 series CPU Chapter 4 Control Registers contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the S3F84NB interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S8F8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descr
63. all logic ones are changed to logic zeros and vice versa leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of destination register 07H 11110001B leaving the new value OEH 00001 110B ELECTRONICS 6 29 INSTRUCTION SET S3F84NB_UM_REV1 00 CP Compare CP dst src Operation dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison Flags C Setif a borrow occurred src dst cleared otherwise Z Set if the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src 6 A3 r Ir opc src dst 3 6 A4 R R 6 A5 R IR opc dst src 3 6 A6 R IM Examples 1 Given R1 02H and R2 CP R1 R2 9 Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 1 E 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example destination working register R1 contains the va
64. bit UART mode Mode 2 3 only ELECTRONICS 4 49 CONTROL REGISTERS S3F84NB_UM_REV1 00 UARTCON1 UART1 Control Register FBH Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Operating Mode and Baud Rate Selection Bits 0 Mode 0 Shift Register fxx 16 x 16bit BRDATA 1 0 1 Mode 1 8 bit UART fxx 16 x 16bit BRDATA 1 1 0 Mode 2 9 bit UART fxx 16 x 16bit BRDATA 1 Mode 3 9 bit UART fxx 16 16bit BRDATA 1 5 Multiprocessor Communication Enable Bit for modes 2 and 3 only 4 Serial Data Receive Enable Bit 3 If Parity disable mode PEN1 0 location of the 9th data bit to be transmitted in UART1 mode 2 or 3 or 1 If Parity enable mode PEN1 1 even odd parity selection bit for transmit data in UART1 mode 2 or 3 0 Even parity bit generation for transmit data 1 Odd parity bit generation for transmit data 2 If Parity disable PEN1 0 location of the 9 data bit that was received in UART1 mode 2 or 3 0 or 1 If Parity enable mode PEN1 1 even odd parity selection bit for receive data in UART1 mode 2 or 3 0 Even parity check for the received data 1 Odd parity check for the received data A result of parity error will be saved in PER1 bit of the UARTPND register after parity checking of the received d
65. by value After the main oscillator is activated and the fxx 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed fxx 8 fxx 2 or fxx 1 System Clock Control Register CLKCON D4H Set 1 R W wel 5 Not used must keep always 0 Not used must keep always 0 Divide by selection bits for CPU clock frequency 00 fxx 16 01 fxx 8 10 fxx 2 11 fxx 1 non divided NOTE The fxx can be generated by both main system and sub system oscillator therefore while main system stops peripherals can be operated by sub system Figure 7 4 System Clock Control Register CLKCON ELECTRONICS 7 3 CLOCK CIRCUIT S3F84NB_UM_REV1 00 Oscillator Control Register OSCCON F6H Set 1 bank 1 R W we CE IA TIAS e Not used System clock selection bit 0 Main oscillator select Not used 1 Subsystem oscillator select Subsystem oscillator control bit 0 Subsystem oscillator RUN 1 Subsystem oscillator STOP Mainsystem oscillator control bit 0 Mainsystem oscillator RUN 1 Mainsystem oscillator STOP When the CPU is operated with fxt sub oscillation clock it is possible to use the stop instruction but in this case before using stop instruction you must select fxx 128 for basic timer counter clock input Then the oscillation stabilization time is 62 5 1 32768 x 128 x 16 ms 100 ms Here the warm up time is from the time th
66. called level 0 level 7 Each interrupt level directly corresponds to an interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3F84NB interrupt structure recognizes eight interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S3C8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware S3F84NB uses twenty nine vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each vector can have several interrupt sources In the S3F84NB interrupt structure there are twenty nine possible interrupt sources When service routine starts the respective pending bit should be either cleared aut
67. cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 DO R D1 IR Given Register 9AH register 02H register OBCH and C 1 SRA 00H gt Register 00H OCD C 0 SRA 02H gt Register 02H 03H register 03H 0 In the first example if general register contains the value 9AH 10011010B the statement SRA 00H shifts the bit values in register OOH right one bit position Bit zero 0 clears the flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value OCDH 11001101B in destination register OOH ELECTRONICS 6 79 INSTRUCTION SET S3F84NB_UM_REV1 00 SRP SRPO SRP1 Set Register Pointer SRP SRPO SRP1 Operation Flags Format Examples 6 80 SIC SIC SIC If src 1 1 and src 0 Othen RPO 3 7 lt src 3 7 If src 1 src 0 1then RP1 3 7 lt src 3 7 If src 1 Oand src 0 Othen RPO 4 7 lt src 4 7 RPO 3 lt 0 RP1 4 7 src 4 7 RP1 3 lt 1 The source data bits one and zero LSB determine whether to write one or both of the register pointers RPO and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected RPO 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mo
68. contents of RO is loaded into external data memory location 0104H RR2 working registers RO R3 no change LDC RO 01H RR2 RO lt contents of program memory location 0105H 01H RR2 RO 6DH R2 01H 04H LDE RO 01H RR2 RO lt contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H R3 04H LDC note 01H RR2 RO 11H contents of RO is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 RO 11H contents of RO is loaded into external data memory location 0105H 01H 0104H LDC RO 1000H RR2 RO lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H R3 04H LDE RO 1000H RR2 RO lt contents of external data memory location 1104H 1000 0104H RO 98H R2 01H 04H LDC R0 1104H RO lt contents of program memory location 1104H RO 88H LDE R0 1104H RO lt contents of external data memory location 1104H R0 98H LDC note 1105H RO 11H contents of RO is loaded into program memory location 1105H 1105H lt 11H LDE 1105H RO 11H contents of RO is loaded into external data memory location 1105H 1105H lt 11H NOTE These instructions are not supported by masked ROM type devices ELECTRONICS 6 53 INSTRUCTION SET S3F84NB_UM_REV1 00 LDCD LDED Load Memory and Decrement LDCD LDED dst src Operation Flags Format Examples dst lt src
69. control register for the UARTO and UART1 is called UARTCONO in set 1 bank 1 at address E3H UARTCON1 in set 1 bank 1 at address It has the following control functions e Operating mode and baud rate selection e Multiprocessor communication and interrupt control e Serial receive enable disable control e 9th data bit location for transmit and receive operations modes 2 and only e Parity generation and check for transmit and receive operations modes 2 and 3 only e UART transmit and receive interrupt control A reset clears the UARTCONO UARTCON t value to So if you want to use UARTO or UART1 module you must write appropriate value to UARTCONO UARTCON1 14 2 ELECTRONICS S3F84NB_UM_REV1 00 UART O 1 UART Control Register UARTCONO E3H Set 1 Bank 1 R W UARTCON 1 Set 1 Bank 1 R W ws rus we ve To eee e s Operating mode and Transmit interrupt enable bit baud rate selection bits 0 Disable see table below 1 Enable Multiprocessor communication Received interrupt enable bit enable bit for modes 2 and 3 only 0 Disable 0 Disable 1 Enable 1 Enable If parity disable mode PENO 1 0 Serial data receive enable bit location of the 9th data bit that was received in 0 Disable UART mode 2 or 3 0 or 1 1 Enable If parity enable mode PENO 1 1 If parity disable mode PENO 1 0 ven odd parity selection bit for receive data in
70. conversion has been completed 50 clocks have elapsed the EOC ADCON 3 flag is set to 1 so that a check can be made to verify that the conversion was successful 5 The converted digital value is loaded to the output register ADDATAH 8 bit and ADDATAL 2 bit then the ADC module enters an idle state 6 The digital conversion result can now be read from the ADDATAH and ADDATAL register Reference Voltage Input Analog Input Pin ADCO ADC7 S3F84NB NOTE The symbol R signifies an offset resistor with a value of from 50 to 100Q Figure 15 5 Recommended A D Converter Circuit for Highest Absolute Accuracy ELECTRONICS 15 5 S3F84NB_UM_REV1 00 PROGRAMMING TIP Configuring A D Converter ADO CHK ADS SB1 TM JR LD SBO SB1 TM JR LD SBO P1CONH 11111111 P1CONL 11111111 ADCON 00000001B ADCON 00001000 Z ADO_CHK ADOBUFH ADDATAH ADOBUFL ADDATAL ADCON 00110001B ADCON 00001000B Z AD3 CHK ADSBUFH ADDATAH ADSBUFL ADDATAL P1 7 P1 4 A D Input MODE 1 3 1 0 A D Input MODE Channel ADCO fxx Conversion start A D conversion end EOC check No 8 bit Conversion data 2 bit Conversion data Channel ADC3 fxx Conversion start A D conversion end EOC check No 8 bit Conversion data 2 bit Conversion data ELECTRONICS S3F84NB_UM_REV1 00 WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions includ
71. current counter value into the Timer A data register You can select rising or falling edges to trigger this operation Timer A also gives you capture input source the signal edge at the TACAP pin You select the capture input by setting the value of the Timer A capture input selection bit in the port 2 control register 2 set 1 bank 0 F2H When P2CONH 5 4 is 00 the TACAP input or normal input is selected When P2CONH 5 4 is set to 10 normal output is selected Both kinds of timer A interrupts can be used in capture mode the timer A overflow interrupt is generated whenever a counter overflow occurs the timer A match capture interrupt is generated whenever the counter value is loaded into the Timer A data register By reading the captured data value in TADATA and assuming a specific value for the timer A clock frequency you can calculate the pulse width duration of the signal that is being input at the TACAP pin 11 2 ELECTRONICS S3F84NB_UM_REV1 00 8 BIT TIMER A B C 0 1 TIMER A CONTROL REGISTER TACON You use the timer A control register TACON to e Select the timer A operating mode interval timer capture mode and PWM mode e Select the timer A input clock frequency e Clear the timer A counter TACNT e Enable the timer A overflow interrupt or timer A match capture interrupt e Clear timer A match capture interrupt pending conditions TACON is located in set 1 Bank 0 at address EAH and is read write addr
72. data memory The assembler makes an even number for program memory and odd number for external data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 14 2 Irr r Given R0 77H R6 30H and R7 00H LDCPD RR 6 RO RR6 RR6 1 77H contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 LDEPD RR6 RO RR6 RR6 1 77H contents of RO is loaded into external data memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment LDCPI LDEPI Operation Flags Format Examples dst src r r 1 dst lt src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 14 Irr r Given RO 7FH R6 21H and R7 0FFH LDCPI RR6 RO RR6 RR6 1 con
73. for high data value 10 Elapsed time for low and high data value Timer B start stop bit 11 Invaild setting 0 Stop timer B 1 Start timer B Timer B interrupt enable bit 0 Disable interrupt 1 Enable interrupt Figure 11 4 Timer B Control Register TBCON Timer B Data High Byte Register TBDATAH D1H Set 1 Bank 0 R W Reset Value FFh Timer B Data Low Byte Register TBDATAL D2H Set 1 Bank 0 R W Reset Value FFh Figure 11 5 Timer B Data Registers TBDATAH TBDATAL 11 6 ELECTRONICS S3F84NB_UM_REV1 00 8 BIT TIMER A B C 0 1 TIMER B PULSE WIDTH CALCULATIONS tHIGH tLOW tLow To generate the above repeated waveform consisted of low period time t and high period time When T FF 0 tLow TBDATAL 1 x 1 fx lt TBDATAL lt 100H where fx The selected clock TBDATAH 1 x 1 fx lt TBDATAH lt 100H where fx The selected clock When T FF 1 ti ow TBDATAH 1 x 1 fx lt TBDATAH lt 100H where fx The selected clock TBDATAL 1 x 1 fx OH lt TBDATAL lt 100H where fx The selected clock To make ti ow 24 us and tyigy 15 us fosc 4 MHz fx 4 MHz 4 1 MHz When T FF 0 li ow 24 us TBDATAL 1 fx TBDATAL 1 x 1us TBDATAL 23 ligu 15 us TBDATAH 1 fx TBDATAH 1 x 1us TBDATAH 14 When T FF 1 15 us TBDATAL 1 TBDATAL 1 x tus TBDATAL 14
74. fosc2 TA 40 85 C Vpp 2 0 V to 5 5 V oscilator Clock Creu Test Condition min Max Unit Crystal XTN XTouT Crystal oscillation frequency XT n and XTour are connected with R and C by soldering Table 20 8 Subsystem Oscillator crystal Stabilization Time TA 25 C Crystal Vpp 4 5 V to 5 5 V E 800 ms Vpp 20V to 3 3 V 2000 400 NOTE Oscillation stabilization time is the time required for the oscillator to it s normal oscillation when stop mode is released by interrupts The value Typ and Max are measured by buzzer output signal after stop release For example in voltage range of 4 5 V to 5 5 V of normal mode we can see the buzzer output signal within 400 ms at our test condition 20 8 ELECTRONICS S3F84NB_UM_REV1 00 ELECTRICAL DATA Table 20 9 Data Retention Supply Voltage in Stop Mode TA 40 to 85 C Vpp 2 0 V to 5 5 V Parameter Symbo Conditions Wm Tp Mac Um Data Retention Stop mode 2 5 5 V Supply Voltage Data Retention IpppR Stop mode VDDDR 2 0 V uA Supply Current NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads RESET Oscillation occurs Stabilzation lt _2r Stop Mode 4 Data Retention Mode VDDDR Execution of STOP Instrction nRESET NOTE twarr is the same as
75. has the vector address CAH And the timer 1 1 overflow interrupt T1OVF1 is interrupt level IRQ3 and has the vector address To generate the exact time interval you should write 1 to T1CON 0 1 2 and clear appropriate pending bits of the TINTPND register To detect a match capture or overflow interrupt pending condition when T1INTO T1INT1 or TTOVFO T1OVF1 is disabled the application program should poll the pending bit TINTPND register bank 0 address E9H When a 1 is detected a timer 1 0 1 match capture or overflow interrupt is pending When the sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the interrupt pending bit If interrupts match capture or overflow are enabled the pending bit is cleared automatically by hardware ELECTRONICS 12 3 16 BIT TIMER 1 0 1 Timer 1 Control Register S3F84NB_UM_REV1 00 T1CONO EAH Set 1 Bank 1 R W T1CON1 EBH Set 1 Bank 1 R W ois Timer 1 clock source selection bit 000 fxx 1024 001 fxx 256 010 fxx 64 011 fxx 8 T Timer 1 overflow interrupt enable bi 0 Disable overflow interrupt 1 Enable overflow interrrupt 100 fxx Timer 1 match capture interrupt enable bit 101 External clock falling edge 0 Disable interrupt 110 External clock rising edge 1 Enable interrrupt 111 Counter stop 0 No effect Timer 1 operating mode selection bit 00 Inter
76. in the even numbered register and the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space LSB n Even address Rn 1 Figure 2 9 16 Bit Register Pair ELECTRONICS 2 13 ADDRESS SPACES S3F84NB_UM_REV1 00 Special P urpose Registers General P urpose Register Bank 1 Bank 0 Control Registers System Registers CFH Register Pointers Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RPO points to locations COH C7H and RP1 to locations C8H CFH thatis to the common working register area NOTE S3F84NB microcontroller pages 0 8 are implemented Pages 0 8 contain all of the addressable registers in the internal register file Page 0 8 Page 0 8 Register Addressing Only All Indirect Register Addressing Indexed Addressing Modes Modes Can be pointed by Register P ointer Figure 2 10 Register File Addressing 2 14 ELECTRONICS S3F84NB_UM_REV1 00 ADDRESS SPACES COMMON WORKING REGISTER AREA COH CFH After a reset register pointers RPO and RP1 automatically select two 8 byte register slices in set 1 locations COH CFH as the active 16 byte working register block
77. is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement NOTE Incase of using DJNZ instruction the working register being used as a counter should be set at the one of location to OCFH with SRP SRPO or SRP1 instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 jump taken 8 r OtoF Given R1 02H and LOOP is the label of a relative address SRP 0COH DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In the example working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION SET S3F84NB_UM_REV1 00 El Enable Interrupts El Operation Flags Format Example SYM 0 lt 1 An El instruction sets bit zero of the system mode register SYM
78. li ow 24 us TBDATAH 1 fx TBDATAH 1 x 1us TBDATAH 23 ELECTRONICS 8 BIT TIMER A B C 0 1 S3F84NB_UM_REV1 00 Timer B Clock T FF 0 TBDATAL 01 TBDATAH 00H T FF 0 TBDATAL 00H TBDATAH 01 FFH T FF 0 TBDATAL 00H TBDATAH 00H T FF 1 TBDATAL 00H TBDATAH 00H Timer B Clock T FF 1 TBDATAL DFH TBDATAH 1FH T FF 0 TBDATAL DFH TBDATAH 1FH T FF 1 TBDATAL 7FH TBDATAH 7FH T FF 0 TBDATAL 7FH TBDATAH 7FH Figure 11 6 Timer B Output Flip Flop Waveforms in Repeat Mode 11 8 ELECTRONICS S3F84NB_UM_REV1 00 8 BIT TIMER A B C 0 1 PROGRAMMING TIP To generate 38 kHz 1 3duty signal through P2 4 This example sets Timer B to the repeat mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 38 kHz 1 3 Duty carrier frequency The program parameters are 8 795 us 17 59 us 4 37 9 kHz 1 3 Duty e Timer B is used in repeat mode e Oscillation frequency is 16 MHz 0 0625 us fx fxx 4 4MHz 0 25 us e TBDATAH 8 795 us 0 25 us 35 18 TBDATAL 17 59 us 0 25 us 70 36 e Set P2 4 to TBPWM mode ORG 0100H Reset address START DI LD TBDATAL 35 1 Set 17 5 us LD TBDATAH 70 1 Set 8 75 us LD TBCON 00100111B Clock Source lt fxx 4 Disable Timer B interrupt Select repeat mode for Timer B Start Timer B operation Set Timer B Outp
79. location of the 9th data bit to be transmitted in UART mode 2 or 3 VART MOOS zor 3 0 DI T 0 Even parity check for the received data If parity enable mode PEN0 1 1 1 Odd parity check for the received data Even odd parity selection bit for transmit data in UART mode 2 or 3 0 Even parity bit generation for transmit data 1 Odd parity bit generation for transmit data MS1 MSO0 Mode Description Baud Rate Shift register fxx 16 x 16bit BRDATA 1 8 bit UART fxx 16 x 16bit BRDATA 1 9 bit UART fxx 16 x 16bit BRDATA 1 9 bit UART fxx 16 x 16bit BRDATA 1 NOTES 1 In mode 2 or 3 if the UARTCON 5 bit is set to 1 then the receive interrupt will not be activated if the received 9th data bit is 0 In mode 1 if UARTCON 5 1 then the receive interrut will not be activated if a valid stop bit was not received The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit Parity enable bits PENO and PEN1 are located in the UARTPND register at address FCH Bank 1 Parity enable and parity error check can be available in 9 bit UART mode Mode 2 3 only Figure 14 1 UART Control Register UARTCONO UARTCON 1 ELECTRONICS 14 3 UART O 1 S3F84NB UM REV1 00 UART INTERRUPT PENDING REGISTER UARTPND The UARTO and UART1 interrupt pending register UARTPND is located in set 1 bank 1 at address FCH It contains the UARTO data t
80. of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is the settings before the interrupt occurred IRET Bytes Cycles Opcode Normal Hex opc 1 10 internal stack BF 12 internal stack IRET Bytes Cycles Opcode Fast Hex opc 1 6 BF In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally is a jump to IRET at address FFH This causes the instruction pointer to be loaded with 100H again and the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H OH FFH 100H Interrupt Service Routine JP to FFH FFFFH NOTE In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last two instructions The IRET cannot be immediately proceeded by a clearing of the interrupt status as with a reset of the IPR register ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET JP Jump JP cc dst Conditional JP dst Unconditional Operation If cc is true PC
81. register ADCON set 1 bank 1 F7H read write but ADCON 3 is read only e Eight multiplexed analog data input pins ADCO ADC7 e 10 bit A D conversion data output register ADDATAH ADDATAL e Internal and AVss FUNCTION DESCRIPTION To initiate an analog to digital conversion procedure at first you must configure 1 0 1 7 to analog input before A D conversions because the P1 0 P1 7 pins can be used alternatively as normal data I O or analog input pins To do this you load the appropriate value to the P1CONH and P1CONL for ADCO ADC7 register And you write the channel selection data in the A D converter control register ADCON to select one of the eight analog input pins ADCn n 0 7 and set the conversion start or enable bit ADCON 0 A 10 bit conversion operation can be performed for only one analog input channel at a time The read write ADCON register is located in set 1 bank 1 at address F7H During a normal conversion ADC logic initially sets the successive approximation register to 200H the approximate half way point of an 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 6 4 in the ADCON register To start the A D conversion you should set the enable bit ADCON 0 When a co
82. rr 4 src dst 3 12 F7 XS rr r 5 Opc dst src XLL 4 14 7 r XL rr 6 opc src dst XLL XLH 4 14 B7 XL rr r 7 dst 0000 DAL DAH 4 14 A7 r DA 8 src 0000 DAL DAH 4 14 B7 DA r 9 dst 0001 DAL DAH 4 14 A7 r DA 10 opc src 0001 DAL DAH 4 14 B7 DA r NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats 3 and 4 the destination address XS rr and the source address XS rr are each one byte 3 For formats 5 and 6 the destination address XL rr and the source address XL rr are each two bytes 4 The DA and r source values for formats 7 and 8 are used to address program memory the second set of values used in formats 9 and 10 are used to address data memory 6 52 ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET LDC LDE Load Memory LDC LDE Continued Examples Given RO 11H R1 34H R2 01H 04H Program memory locations 0103H 4FH 0104H 1A 0105H 6DH and 1104H 88H External data memory locations 0103H 5FH 0104H 2AH 0105H 7DH and 1104H 98H LDC RO RR2 RO lt contents of program memory location 0104H RO 1AH R2 01H 04H LDE RO RR2 RO lt contents of external data memory location 0104H RO 2AH R2 01H 04H LDC note RR2 RO 11H contents of RO is loaded into program memory location 0104H RR2 working registers RO R2 R3 no change LDE RR2 RO 11H
83. select rising or falling edges to trigger this operation The timer 1 1 also gives you capture input source the signal edge at the T1CAP1 pin You select the capture input by setting the value of the timer 1 1 capture input selection bit in the port control register low PSCONL set 1 bank 0 F5H Both kinds of timer 1 1 interrupts T1OVF1 T1INT1 can be used in capture mode the timer 1 1 overflow 12 2 ELECTRONICS S3F84NB_UM_REV1 00 16 BIT TIMER 1 0 1 interrupt is generated whenever a counter overflow occurs the timer 1 1 capture interrupt is generated whenever the counter value is loaded into the timer 1 data register By reading the captured data value in T1DATAH1 T1DATAL1 and assuming a specific value for the timer 1 1 clock frequency you can calculate the pulse width duration of the signal that is being input at the T1CAP1 pin PWM Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the T1OUTO T1OUT1 pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 1 0 1 data registers In PWM mode however the match signal does not clear the counter but can generate a match interrupt Instead it runs continuously overflowing at FFFFH and then continuous increasing from OOOOH Whenever an overflow occur an overflow T1OVFO 1 interrupt can be generated Although you can use the match or overfl
84. the To User_Vcc Setting column indicates the electrical short off configuration SMDS2 Selection SAM8 In order to write data into program memory that is available in SMDS2 the target board should be selected to be for SMDS2 through a switch as follows Otherwise the program memory writing function is not available Table 22 2 The SMDS2 Tool Selection Setting 1 Setting Operating Mode Target SMDS2 Board 22 4 ELECTRONICS S3F84NB_UM_REV1 00 DEVELOPMENT TOOLS Table 22 3 Using Single Header Pins to Select Operation Mode TEST MODE Run Mode RUN MODE JP2 TEST MODE Test Mode RUN MODE JP2 Table 22 4 Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments External i Connector from Triggers External Trigger Sources of the Application System You can connect an external trigger source to one of the two external trigger channels CH1 or CH2 for the SMDS2 breakpoint and trace functions IDLE LED This LED is ON when the evaluation chip S3E84N0 is in idle mode STOP LED This LED is ON when the evaluation chip S3E84N0 is in stop mode ELECTRONICS 22 5 DEVELOPMENT TOOLS S3F84NB_UM_REV1 00 Iu 5 6 3E 7 Ju 5 6 7 NOTE There is no ROM in the EVAchip So smart option is not determined by software but DIP switch Figure 22 3 DIP Switch for Smart Option ON OFF swt XTI
85. therefore be read or written by application software In the SSF84NB interrupt structure the timer B underflow interrupt IRQ1 belongs to this category of interrupts in which pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register In the SSF84NB interrupt structure pending conditions for IRQ4 IRQ5 IRQ6 and IRQ7 must be cleared in the interrupt service routine ELECTRONICS 5 15 INTERRUPT STRUCTURE S3F84NB_UM_REV1 00 INTERRUPT SOURCE POLLING SEQUENCE The gt dme interrupt request polling and servicing sequence is as follows A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks the source s interrupt level The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is se
86. value in the SPL register will overflow or underflow to the SPH register overwriting any other data that is currently stored there To avoid overwriting data in the SPH register you can initialize the SPL value to FFH instead of 00H 2 20 ELECTRONICS S3F84NB_UM_REV1 00 ADDRESS SPACES PROGRAMMING TIP Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD SPL 0FFH SPL lt FFH Normally the SPL is set to OFFH by the initialization routine PUSH PP Stack address OFEH lt PP PUSH RPO Stack address OFDH RPO PUSH RP1 Stack address OFCH lt RP1 PUSH R3 Stack address OFBH lt R3 POP R3 lt Stack address OFBH POP RP1 RP1 lt Stack address OFCH POP RPO RPO lt Stack address OFDH POP PP PP lt Stack address OFEH ELECTRONICS 2 21 S3F84NB_UM_REV1 00 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in SAM88RC instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressi
87. 0 5 Stop Mode Release Timing initiated by 20 9 20 6 Stop Mode Main Release Timing Initiated by Interrupts 20 9 20 7 Stop Mode Sub Release Timing Initiated by Interrupts 20 10 20 8 Serial Data Transfer Timing U entren 20 11 20 9 Waveform for UART Timing Characteristics eene eee nenn rsrn rsen resrn nee 20 12 20 10 Definition of DLE and ILE fia enie ea aa aa ad aaa a 20 14 20 11 LVR Reset Timing ici e en e got cete debe i a Heated Hec so ertt 20 15 21 1 64 SDIP 750 Package Dimensions 21 1 21 2 64 QFP 1420F TQFP Package Dimensions sse 21 2 22 1 SMDS or SK 1000 Product Configuration 22 2 22 2 TB84NB Target Board 22 3 22 3 DIP Switch for Smart Option 22 6 22 4 DIP Switch for Port 6 Sub Oscillator or Normal I O 22 6 22 5 40 Pin Connectors Pin Assignment for 4 22 7 22 6 TB84NB Adapter Cables for 64 SDIP Package 22 8 xiv S3F84NB UM REV1 00 MICROCONTROLLER Table Number 4 4
88. 0 5 kHz buzzer BZOUT signal output 1 1 kHz buzzer BZOUT signal output 1 0 2kHz buzzer BZOUT signal output 4 kHz buzzer BZOUT signal output WTCON 3 2 Set watch timer interrupt 0 5 5 oji Set watch timer interrupt to 0 25 s Set watch timer interrupt 0 125 5 Set watch timer interrupt to 1 955 ms WTCON 1 Disable watch timer clear frequency dividing circuits Enable watch timer WTCON O EM Interrupt is not pending clear pending bit when write Interrupt is pending NOTE Main system clock frequency fx is assumed to be 8MHz 16 2 ELECTRONICS S3F84NB_UM_REV1 00 WATCH TIMER CIRCUIT DIAGRAM Enable Disable Clock WICON 7 Selector fx 256 32768 Hz Frequency Dividing Circuit fx 2 Main System Clock 8MHz fxr 2 Subsystem Clock 32768 Hz fw Watch timer WATCH TIMER BUZZER Output BZOUT WTINT Figure 16 1 Watch Timer Circuit Diagram ELECTRONICS WATCH TIMER PROGRAMMING TIP Using the Watch Timer INITIAL MAIN WT_INT ORG 0000h VECTOR 0D2h WT_INT ORG 0100h LD SYM 00h LD IMR 00010000b LD SPH 00000000b LD SPL 0FFh LD BTCON 10100011b 5 1 LD WTCON 11001110b SBO El MAIN ROUTINE JR T MAIN AND WTCON 11111110b S3F84NB_UM_REV1 00 Disable Global Fast interrupt Enable IRQ4 interrupt Set stack area Disable Watch dog 0 5 kHz buzzer 1 955ms duration interrupt Interrupt enable
89. 000001 1B The statement BXOR R1 01H 1 exclusive ORs bit one of register 01H source with bit zero of R1 destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of source register 01H is unaffected ELECTRONICS 6 25 INSTRUCTION SET S3F84NB_UM_REV1 00 CALL CALL Operation Flags Format Examples Call Procedure dst SP lt SP 1 QSP lt PCL SP lt SP 1 SP lt PCH PG lt dst The current contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode EN Hex dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR dst 2 14 D4 IA Given RO 35H R1 21H PC 1A47H and SP 0002H CALL 3521H gt SP 0000H Memory locations 0000H 1AH 0001H where 4AH is the address that follows the instruction CALL RRO gt SP 0000H 0000H 1AH 0001H 49H CALL 40H gt SP 0000H 0000H 1AH 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer
90. 01H 02H gt SBC 01H 02H gt SBC OIH 8AH gt R1 OCH R2 03H R1 05H R2 03H register O3H OAH Register 01H 1CH register 02H 03H Register 01H 15H register 02H 03H register O3H 0AH Register 01H 95H C S and V 1 In the first example if working register R1 contains the value 10H and register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in register R1 ELECTRONICS 6 77 INSTRUCTION SET S3F84NB_UM_REV1 00 SCF Set Carry Flag SCF Operation Flags Format Example lt 1 The carry flag is set to logic one regardless of its previous value C Setto 1 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 DF The statement SCF sets the carry flag to logic one ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET SRA Shift Right Arithmetic SRA Operation dst dst 7 lt dst 7 lt dst 0 dst n lt dst n 1 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into bit position 6 Flags Format Examples C Set if the bit shifted from the LSB position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result is negative
91. 1 Overflow Interrupt Enable Disable overflow interrupt 1 Enable overflow interrupt 4 42 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER TACON Timer A Control Register EAH Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer A Input Clock Selection Bits 5 4 Timer A Operating Mode Selection Bits 0 Interval mode TAOUT mode Fold Capture mode capture on rising edge counter running OVF can occur Capture mode capture on falling edge counter running OVF can occur PWM mode OVF interrupt can occur 3 Timer A Counter Clear Bit No effect 1 Clear the timer A counter Auto clear bit 2 Ti 3 er A Overflow Interrupt Enable Bit Disable overflow interrupt 1 Enable overflow interrupt Ti 3 er A Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer Start Stop Bit Stop Timer A 1 Start Timer A ELECTRONICS 4 4 CONTROL REGISTERS S3F84NB_UM_REV1 00 TBCON Timer B Control Register DOH Set 1 Bank 0 Bit Identifier A 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer B Input Clock Selection Bits NOTE 4 44 ojoj SSCS oppe Timer Interrupt Time Selectio
92. 11 1 These instructions are used for user stacks or block transfers of data from program data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD references program memory and LDED references external data memory The assembler makes an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory location 1033H OCDH and external data memory location 1033H ODDH LDCD R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is decremented by one R8 R6 10H R7 32H RR6 lt RR6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 32H ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET LDCI LDEI Load Memory and Increment LDCI LDEI Operation Flags Format Examples dst src dst lt src rr 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of th
93. 14 1 16 1 19 1 19 2 19 3 List of Tables Title Page Number SSF84NB Pin Descriptions cece eee aeeeeeaeeeeeeeeseaeeeeaaeeeeeeeseaeeesaeeseneeeeeas 1 7 Register Type Summary U U 2 5 Set tr Bedisters usa ee eh Weasel quie eae ce aa u da 4 1 Set 1 Bank 0 Registers a 4 2 Set 1 Bank 1 Registers He ee dare dd dn 4 3 Page 8 Hegisters n SR Gak akay ERR MARRE RAE 4 4 Interr pt Vecto S iust ipe petu eet ipea seth adven e 5 6 Interrupt Control Register Overview L 5 7 Interrupt Source Control and Data Registers 5 9 Instruction Group Summary U ener enne enne 6 2 Flag Notation Conventions ener 6 8 Instruction Set Symbols sss eene 6 8 Instruction Notation Conventions sess nnne 6 9 Quick Reference uc rdi ede tent shia Re 6 10 Condition CodeS RR 6 12 S3F84NB Set 1 Register Values after 8 2 S3F84NB Set 1 Bank 0 Register Values after RESET 8 3 SSF84NB Set 1 Bank 1 Register Values after RESET 8 4 SSF84NB Page 8 Regi
94. 2 P0 1 P0 0 PGOUT 7 4 PGOUT 3 2 PGOUT 1 PGOUT O0 7 6 bit PO 7 P0 6 P0 5 P0 4 Input mode Input mode pull up Push pull output Alternative function mode PGOUT 7 4 5 4 bit 2 Input mode Input mode pull up Push pull output Alternative function mode PGOUT 3 2 3 2 bit PO 1 Input mode Input mode pull up Push pull output Alternative function mode PGOUTT1 1 0 bit PO 0 Input mode Input mode pull up Push pull output Alternative function mode PGOUTT 0 Figure 9 1 Port 0 Control Register POCON 9 4 ELECTRONICS S3F84NB_UM_REV1 00 PORTS PORT 1 Port 1 is an 8 bit I O port with individually configurable pins that you can use two ways e General purpose digital I O e Alternative function ADCO ADC7 Port 1 is accessed directly by writing or reading the port 1 data register P1 at location E1H in set 1 bank 0 Port 1 Control Register P1CONH P1CONL Port 1 has two 8 bit control registers P1CONH for P1 4 P1 7 and P1CONL for P1 0 P1 3 A reset clears the P1CONH and P1CONL registers to OOH configuring all pins to input modes You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 1 control registers must also be enabled in the associated peripheral module ELECTRONICS 9 5
95. 2H The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI Operation Flags Format Example dst src dst lt src IR IR 1 The POPUI instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 93 R IR Given Register 00H 01H and register 01H 70H POPUI 02H 9800H gt Register OOH 02H register 01H 70H register 02H 70H If general register 00H contains the value 01H and register 01H the value 70H the statement POPUI 02 00 loads the value 70H into the destination general register 02H The user stack pointer register OOH is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET S3F84NB_UM_REV1 00 PUSH Push To Stack PUSH Operation Flags Format Examples src SP SP 1 SP lt src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst
96. 4096 x 16 x 1 f OSC Figure 20 5 Stop Mode Release Timing initiated by nRESET Oscillation Stabilization Time Y 1 Stop Mode Ile Mode Data Retention Mode Normal Execution of Operating Mode STOP Instruction Interrupt NOTE twaris the same as 4096 x 16 x BT clock Figure 20 6 Stop Mode Main Release Timing Initiated by Interrupts ELECTRONICS 20 9 ELECTRICAL DATA S3F84NB_UM_REV1 00 Oscillation Stabilization Time 3 Stop Mode 7 PEE 209 Idle Mode lt Data Retention Mode Normal Execution of Operating Mode STOP Instruction Interrupt NOTE When the case of select the fxx 128 for basic timer input clock before enter the stop mode 128 x 16 x 1 32768 62 5 ms Figure 20 7 Stop Mode Sub Release Timing Initiated by Interrupts 20 10 ELECTRONICS S3F84NB_UM_REV1 00 ELECTRICAL DATA Table 20 10 Serial I O Timing Characteristics TA 40 C to 85 C Vpp 2 0 V to 5 5 V SCK Cycle Time SCK High Low Width fk a oo SI Setup Time to SCK Low tsik SI Hold Time to SCK High kei ld Output Delay for SCK to SO lkso External SCK source Internal SCK source NOTE SCK means serial I O clock frequency SI means serial data input and SO means serial data output Output Data Figure 20 8 Serial Data Transfer Timing ELECTRONICS 20 11 ELECTRICAL DATA
97. 4INTPND To process external interrupts at the port 4 pins two additional control registers are provided the port 4 interrupt enable register PAINT FAH set 1 bank 0 and the port 4 interrupt pending register P4INTPND FBH set 1 bank 0 The port 4 interrupt pending register P4INTPND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the P4INTPND register at regular intervals When the interrupt enable bit of any port 4 pin is 1 a rising or falling signal edge at that pin will generate an interrupt request The corresponding P4INTPND bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must clear the pending condition by writing a 0 to the corresponding P4INTPND bit 9 14 ELECTRONICS S3F84NB_UM_REV1 00 PORTS Port 4 Control Register High Byte PACONH F6H Set 1 Bank 0 R W TEOCOLI P4 7 P4 6 P4 5 P4 4 INT7 INT6 INT5 INT4 7 6 bit P4 7 INT7 Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output 5 4 bit P4 6 INT6 Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull
98. Bit 3EH 7 is 0 user must change ISP reset vector address from 0100H to some address which user want to set reset address 0200H 0300H 0500H or 0900H If the reset vector address is 0200H the ISP area can be assigned from 0100H to 01 256bytes If 0300H the ISP area can be assigned from 0100H to 2 512bytes If 0500H the ISP area can be assigned from 0100H to 04FFH 1024bytes If 0900H the ISP area can be assigned from 0100H to 08FFH 2048bytes If ISP Protection Enable Disable Bit is 0 user can t erase or program the ISP area selected by 3EH 1 and 3EH 0 in flash memory User can select suitable ISP protection size by 3EH 1 and 3EH O If ISP Protection Enable Disable Bit SEH 2 is 1 1 and 3EH 0 are meaningless Although user can write any value in the not used bits of 3CH and we recommend the value of not used bits is 1 ELECTRONICS S3F84NB_UM_REV1 00 ADDRESS SPACES REGISTER ARCHITECTURE In the SSF84NB implementation the upper 64 byte area of register files is expanded two 64 byte areas called set 1 and set 2 The upper 32 byte area of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and the lower 32 byte area is a single 32 byte common area Set 2 is logically expanded 8 separately addressable register pages page 0 page 8 Only page 8 is 6byte In case of SSF84NB the total number of addressable 8 bit registers is 2 150 O
99. CL Flash Memory Sector Address Register Low Byte indicates the low byte of sector address and FMSECH Flash Memory Address Sector Register High Byte indicates the high byte of sector address The FMSECH is needed for S3F84NB because it has 512 sectors One sector consists of 128 bytes Each sector s address starts XXOOH or XX80H that is a base address of sector is XX00H or XX80H So bit 6 0 of FMSECL don t mean whether the value is 1 or 0 We recommend that itis the simplest way to load the sector base address into FMSECH and FMSECL register When programming the flash memory user should program after loading a sector base address which is located in the destination address to write data into FMSECH and FMSECL register If the next operation is also to write one byte data user should check whether next destination address is located in the same sector or not In case of other sectors user should load sector address to FMSECH and FMSECL Register according to the sector Refer to page 15 16 PROGRAMMING TIP Programming Flash Memory Sector Address Register FMSECH ECH Page 8 R W Flash Memory Sector Address High Byte NOTE The High Byte flash memory sector address pointer value is the higher eight bits of the 16 bit pointer address Figure 19 5 Flash Memory Sector Address Register FMSECH Flash Memory Sector Address Register FMSECL EDH Page 8 R W Don t Care Flash Memory Sector Address Low Byte N
100. CON t setting e Interval timer mode Toggle output at TCOUTO TCOUT1 pin only match interrupt occurs e PWM mode TCOUTO TCOUT1 pin match and overflow interrupt can occur Timer C 0 1 has the following functional components e Clock frequency divider with multiplexer e 8 bit counter 8 bit comparator 8 bit reference data register TCDATAO TCDATA1 e PWM or match output TCOUTO TCOUT1 e Timer C 0 match overflow interrupt IRQ2 vector C4H generation e Timer C 1 match overflow interrupt IRQ2 vector C6H generation e Timer C 0 control register TCCONO set 1 bank1 F2H read write e Timer C 1 control register TCCON1 set 1 bank1 F3H read write ELECTRONICS 11 11 8 BIT TIMER A B C 0 1 S3F84NB_UM_REV1 00 TIMER C 0 1 CONTROL REGISTER TCCONO TCCON1 11 12 Timer C Control Register TCCONO F2H Set 1 Bank 1 R W Reset 00H TCCON1 F3H Set 1 Bank 1 R W Reset 00H LIJEAEXEREREREREREXA Timer C E bit 0 Stop timer 1 Start timer C Timer C pending bit 0 No interrupt pending Timer C 3 bits prescaler bits 1 Interrupt pending 000 Non devided 001 Devided by 2 010 Devided by 3 011 Devided by 4 100 Devided by 5 101 Devided by 6 Timer C mode selection bit 110 Devided by 7 0 fxx 1 amp PWM mode 111 Devided by 8 1 fxx 64 amp Interval mode Timer C interrupt enable bit 0 Disable interrupt 1 Enable interrrupt Timer C counter clear bit 0 No eff
101. CS S3F84NB_UM_REV1 00 PRODUCT OVERVIEW PIN ASSIGNMENT 64 1 P2 5 TACK 63 1 2 6 62 P2 7 TAOUT 61 PO 0 PGO 60 P0 1 PG1 59 P0 2 PG2 58 3 P0 3 PG3 57 1 P0 4 PG4 56 P0 5 PG5 55 P0 6 PG6 53 P1 0 ADC0 52 1 P1 1 ADC1 P1 2 ADC2 P1 3 ADC3 AVss AVref P1 4 ADC4 P1 5 ADC5 P1 6 ADC6 P1 7 ADC7 P6 0 XTin P2 4 TBPWM P2 3 BZOUT P2 2 SCK P2 1 SI P2 0 SO 5 7 SDAT P5 6 SCLK P5 5 VDD O vss S3F84NB P6 1 XTout Xout P6 2 INT8 Xin P6 3 INT9 VPP TEST 64 QFP 1420F P6 4 INT10 P5 3 RxD0 P6 6 INT12 nRESET P6 7 INT13 P5 2 TxDO P4 0 INTO P5 1 RxD1 P4 1 INT1 P5 0 TxD1 P4 2 INT2 P4 4 P4 3 P3 0 T1CKO C3 27 P4 7 P4 6 P3 7 TCOUT1 C 20 P3 6 TCOUTO C3 21 P3 5 T10UT1 22 P3 4 TAOUTO C3 23 P3 3 T1CAP1 4 24 P3 2 T1CAPO C 25 P3 1 T1CK1 C3 26 Figure 1 3 S3F84NB Pin Assignment 64 QFP ELECTRONICS 1 5 PRODUCT OVERVIEW S3F84NB_UM_REV1 00 PIN DESCRIPTIONS Table 1 1 S3F84NB Pin Descriptions Pin Pin Circuit Type Description Type P0 0 P0 7 1 Bit programmable port input or output mode 1 4 64 61 PGO0 PG7 selected by software input or push pull output Software assignable pull up Alternately PO 0 PO0 7 can be used as the PG output port PGO PG7 P1 0 P1 7 Bit programmable port input or output mode 60 57 54 51 ADCO ADC7 selected by software input or push pull output 53 50 47 44 Software assignable p
102. CTRONICS 20 3 ELECTRICAL DATA S3F84NB_UM_REV1 00 Table 20 3 D C Electrical Characteristics Continued TA 40 to 85 C Vpp 2 0 V to 5 5 V Conditions Pull up Resistor Vpp 5 5 V Vin 0 V Port 0 6 Supply Current lpp1 2 Vpp 2 0V to 5 5V 1 RUN mode 10 MHz CPU clock Idle mode 10 MHz CPU clock Sub operating main osc stop 480 960 uA Vpp 2 0 V to 5 5 V 32 768 kHz crystal oscillator Sub idle mode main osc stop 420 840 32 768 KHz crystal oscillator Ibos Vpp 20V to 5 5 V 200 400 Stop mode NOTES 1 Supply current does not include current drawn through internal pull up resistors or external output current loads 2 and Ippo include a power consumption of subsystem oscillator 3 and are the current when the main system clock oscillation stop and the subsystem clock is used 4 lppsisthe current when the main and subsystem clock oscillation stop 5 All currents 1 5 include the current consumption of LVR circuit 20 4 ELECTRONICS S3F84NB_UM_REV1 00 ELECTRICAL DATA Table 20 4 A C Electrical Characteristics 40 to 85 TE 2 0 V to 5 5 V Parameter Symbol bol Conditions s CIT Interrupt Input tiNTH 5 V High Low Width tINTL Ports 4 and 6 nRESET Input tRsL Input Low Width NOTE User must keep more large value then min value tint tINTH _ g
103. DD Fac MN eer reer cee AND Logra AND x23 a usc com rere orsa Irt edat qi mL eae a uti BITC Bit Gomplement te eet e b qud BITR Bit Rea eae ta aene BITS slm E BOR Bit OB anie ite aa Meet dte HD des BTJRF Bit Test Jump Relative on False BTJRT Bit Test Jump Relative on BXOR BIEXOR3 uin ste oi eite itte tedio t ez CALL Gall edrojo io y ERE ES CCF Complement Carry CLR ClO An S asha ap eite t uan ieu COM Complement inanuia ep ue eet d et Hide Ld died CP eeu Lr CPIJE Compare Increment and Jump on Equal CPIJNE Compare Increment and Jump on Non Equal DA Decimal AdJUst u der dg dne re t eati ere enia t o pe diae DEC Decremoert 1 EU eive DECW Decremoent Wema ictor ier rete e td RE DI Disable Interrupts tert tibt etes DIV Divide Unsigned esee cd tee drag eite dah ne dne dde DJNZ Decrement and Jump if El Enable ime rapi 3 uio EE eee eR ENTER asa nisu eer e cence rere eee oer Eee cere A dE EXIT Exit ennan ae IDLE Idle Operation et
104. ELECTRONICS USER S MANUAL S3F84NB 8 BIT CMOS MICROCONTROLLERS Dec 2007 REV 1 00 Confidential Proprietary of Samsung Electronics Co Ltd Copyright 2007 Samsung Electronics Inc All Rights Reserved Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3F84NB 8 Bit CMOS Microcontrollers User s Manual Revision 1 Publication Number 21 S3 F84NB 122007 Copyright 2006 2007 Samsung Electronics Co Ltd Typical parameters can and do vary in di
105. ET nRESET P2 0 P2 7 8 Bit I O Port and Interrupt Control Basic Timer P2 7 TAOUT E P2 6 TACAP lt 2 5 p gt Counter P2 4 TBPWM P3 0 P3 7 SET SAM8RC CPU P3 7 TCOUTI Timer Counter P3 6 TCOUTO P3 4 T10UTO P3 2 T1CAPO 16 Bit a P3 0 T1CKO P3 5 T10UT1 P3 3 T1CAP1 P3 1 TICK1 P2 2 SCK 2 1 51 P2 0 SO P5 3 RxDO P5 2 TxDO P5 1 RxD1 P5 0 TxD1 P0 0 P0 7 PGO PG7 P4 0 P4 7 INTO INT7 Timer Counter 1 0 1 P5 0 P5 7 64K Byte 2064 Byte FLASH RAM SIO UARTO 1 P6 0 P6 7 INT8 13 14 144 44144 OW ERE HERE HH Figure 1 1 S3F84NB Block Diagram ELECTRONICS 1 3 PRODUCT OVERVIEW S3F84NB_UM_REV1 00 PIN ASSIGNMENT P0 4 PG4 P0 5 PG5 P0 6 PG6 P0 7 PG7 P1 0 ADCO P1 1 ADC1 P1 2 ADC2 P0 3 PG3 P0 2 PG2 P0 1 PG1 P0 0 PG0 P2 7 TAOUT P2 6 TACAP P2 5 TACK P2 4 TBPWM P1 3 ADC3 P2 3 BZOUT AVss P2 2 SCK AVref P2 1 SI P1 4 ADC4 P2 0 SO P1 5 ADC5 P5 7 P1 6 ADC6 P1 7 ADC7 KE S3F84NB P6 0 XTin VDD P6 1 XTout vss 64 SDIP 750 P6 2 INT8 Xout 4 P6 3 INT9 Xin i P6 4 INT10 VPP TEST P6 5 INT11 P5 4 P6 6 INT12 P5 3 RxDO P6 7 INT13 nRESET P4 0 INTO P5 2 TxDO P4 1 INT1 P5 1 RxD1 P4 2 INT2 P5 0 TxD1 P4 3 INT3 P3 7 TCOUT1 P4 4 INT4 P3 6 TCOUTO P4 5 INTS P3 5 T10UT1 P4 6 INT6 P3 4 T10UTO P4 7 INT7 P3 3 T1CAP1 P3 0 T1CKO P3 2 T1CAPO P3 1 T1CK1 Figure 1 2 5 8 Pin Assignment 64 SDIP 1 4 ELECTRONI
106. F5H Set 1 Bank 0 R W a Ce Cae x P3 0 T1CK0 P3 1 T1CK1 P3 2 T1CAPO P3 3 T1CAP1 7 6 bit P3 3 T1CAP1 Input mode T1CAP1 Input mode pull up T1CAP1 Push pull output 5 4 bit P3 2 T1CAPO Input mode T1CAPO Input mode pull up T1 CAPO Push pull output 3 2 bit P3 1 T1CK1 Input mode T1CK1 Input mode pull up T1CK1 Push pull output 1 0 bit P3 0 T1CKO Input mode T1CKO Input mode pull up T1CKO Push pull output Figure 9 7 Port 3 Low Byte Control Register P3CONL ELECTRONICS 9 13 PORTS S3F84NB_UM_REV1 00 PORT 4 Port 4 is an 8 bit I O port that you can use two ways e General purpose digital I O e External interrupt inputs for INTO INT7 Port 4 is accessed directly by writing or reading the port 4 data register P4 at location E4H in set 1 bank 0 Port 4 Control Register P4CONH P4CONL Port 4 pins are configured individually by bit pair settings in two control registers located in set 1 bank 0 PACONL low byte F7H and PACONH high byte F6H When you select output mode a push pull circuit is configured In input mode three different selections are available e Schmitt trigger input and interrupt generation on falling signal edges e Schmitt trigger input and interrupt generation on rising signal edges e Schmitt trigger input with pull up resister and interrupt generation on falling signal edges Port 4 Interrupt Enable and Pending Registers PAINT P
107. H 7 is 1 3EH 6 and 3EH 5 are meaningless 2 If ISP Reset Vector Change Selection Bit 7 is 0 user must change ISP reset vector address from 0100H to some address which user want to set reset address 0200H 0300H 0500H or 0900H If the reset vector address is 0200H the ISP area can be assigned from 0100H to 01 256bytes If 0300H the ISP area can be assigned from 0100H to O2FFH 512bytes If 0500H the ISP area can be from 0100H to 1024bytes If 0900H the ISP area can be from 0100H to 08FFH 2048bytes 3 If ISP Protection Enable Disable Bit is 0 user can t erase or program the ISP area selected by 3EH 1 and 3EH 0 in flash memory 4 User can select suitable ISP protection size by 3EH 1 and SEH O If ISP Protection Enable Disable Bit SEH 2 is 1 1 and 3EH 0 are meaningless Table 19 2 ISP Sector Size Smart Option 003EH ISP Size Selection Bit Area of ISP Sector ISP Sector Size a eee L0 o 0 100H FH 256 Bytes 256 Bytes o 1 f00H 2FFH 512 Bytes 512 Bytes 1 0 100 4FFH 1024 Bytes 1024 Bytes 1 t 00H BSFFH 2048 Bytes 2048 Bytes NOTE The area of the ISP sector selected by smart option bit 2 3EH 0 can t be erased and programmed by LDC instruction in user program mode ISP RESET VECTOR AND ISP SECTOR SIZE If you use ISP sectors by setting the ISP enable disable bit to 0 an
108. INSTRUCTION SET Opcode Addr Mode Hex dst 00 R 01 IR In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value 10H contained in the destination register by one leaving the value OFH ELECTRONICS 6 35 INSTRUCTION SET S3F84NB_UM_REV1 00 DECW Decrement Word DECW Operation Flags Format Examples NOTE dst dst dst 1 The contents of the destination location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one C Unaffected Z Setif the result is cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 80 RR 8 81 IR Given RO 12H R1 34H R2 30H register 30H and register 31H 21H DECW RRO gt RO 12H R1 33H DECW R2 gt Register 30H OFH register 31H 20H In the first example destination register RO contains the value 12H and register R1 the value 34H The statement DECW RRO addresses RO and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag F
109. ION SET S3F84NB_UM_REV1 00 JR Jump Relative JR Operation Flags Format Example cc dst If cc is true PC lt PC dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See list of condition codes The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mode 1 Hex dst dst 2 6 ccB RA cc 0 to F NOTE Inthe first byte of the two byte instruction format the condition code and the opcode are each four bits Given The carry flag 1 and LABEL_X 1FF7H JR C LABELX PC 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL_X will pass control to the statement whose address is now in the PC Otherwise the program instruction following the JR would be executed ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET LD Load LD dst src Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src dst opc src 2 4 rC
110. LAGS 6 result together with a DECW instruction To avoid this problem we recommend that you use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET DI Disable Interrupts DI Operation Flags Format Example SYM 0 0 Bit zero of the system mode control register SYM 0 is cleared to globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled No flags are affected Bytes Cycles Opcode Hex opc 1 4 8F Given SYM 01 DI Ifthe value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt source control register be sure DI state ELECTRONICS 6 37 INSTRUCTION SET S3F84NB_UM_REV1 00 DIV Divide Unsigned DIV dst src Operation dst src dst UPPER lt REMAINDER dst LOWER QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remai
111. LDED LDCD LDEI LDCI LDEPD LDCPD LDEPI LDCPI LDW POP POPUD POPUI PUSH PUSHUD PUSHUI Operands dst dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst dst src dst src src dst src dst src S3F84NB_UM_REV1 00 Table 6 1 Instruction Group Summary Instruction Clear Load Load bit Load external data memory Load program memory Load external data memory and decrement Load program memory and decrement Load external data memory and increment Load program memory and increment Load external data memory with pre decrement Load program memory with pre decrement Load external data memory with pre increment Load program memory with pre increment Load word Pop from stack Pop user stack decrementing Pop user stack incrementing Push to stack Push user stack decrementing Push user stack incrementing ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical ex
112. Memory User Programming Enable Register FMUSR to 00000000B lt 88H SelectPage 8 FMUSR lt 0A5H User Programimg Mode Enable FMSECH lt High Address of Sector FMSECL lt Low Address of Sector FMCON lt 10100001 Mode Select amp Start Erase FMUSR lt 00H User Prgramming Mode Disable Select Page 0 Set Sector Base Address Finish One Sector Erase Figure 19 8 Sector Erase Flowchart in User Program Mode NOTES 1 If user erases a sector selected by Flash Memory Sector Address Register FMSECH and FMSECL FMUSR should be enabled just before starting sector erase operation And to erase a sector Flash Operation Start Bit of FMCON register is written from operation stop 0 to operation start 1 That bit will be cleared automatically just after the corresponding operation completed In other words when S3F84NB is in the condition that flash memory user programming enable bits is enabled and executes start operation of sector erase it will get the result of erasing selected sector as user s a purpose and Flash Operation Start Bit of FMCON register is also clear automatically 2 If user executes sector erase operation with FMUSR disabled bit Flash Operation Start Bit remains high which means start operation and is not cleared even though next instruction is executed So user should be careful to set FMUSR when executing sector erase for no effect on other flash sectors
113. N XTOUT Figure 22 4 DIP Switch for Port 6 Sub Oscillator or normal I O SWITCH e SW1 1 Connection to XTin enable Connection to XTin disable SW1 2 Connection to XTout enable Connection to XTout disable eio 22 6 ELECTRONICS S3F84NB_UM_REV1 00 P2 4 TBPWM P2 2 SCK P2 0 SO P5 6 VDD N C TEST P5 3 RxDO P5 2 TxDO P5 0 TxD1 P3 6 TCOUTO P3 4 T1OUTO P3 2 T1CAPO P3 0 T1CKO P4 6 INT6 P4 4 INT4 NC NC NC NC ELECTRONICS IA 9 3 0 o2 Sg 9 5 Figure 22 5 P2 3 BUZOUT P2 1 SI 5 7 5 5 nRESET P5 1 RxD1 P3 7 TCOUT1 P3 5 T1OUT1 P3 3 T1CAP1 P3 1 T1CK1 P4 7 INT7 P4 5 INTS P4 3 INT3 NC NC NC NC NOTE N C means No Connection P4 2 INT2 P4 0 INTO P6 6 INT12 P6 4 INT10 P6 2 INT8 P6 0 XTin P1 6 ADC6 P1 4 ADC4 AVss P1 2 ADC2 P1 0 ADCO P0 6 PG6 P0 4 PG4 P0 2 PG2 P0 0 PGO P2 6 TACAP NC NC NC NC 10129uu02 u d 0r 40 Pin Connector Pin Assignment for TB84NB DEVELOPMENT TOOLS P4 1 INT1 P6 7 INT13 P6 5 INT1 1 P6 3 INT9 P6 1 XTouT P1 7 ADC7 P1 5 ADC5 AVREF P1 3 ADC3 P1 1 ADC1 P0 7 PG7 P0 5 PG5 P0 1 PG1 P2 7 TAOUT P2 5 TACK NC NC NC NC 22 7 DEVELOPMENT TOOLS S3F84NB_UM_REV1 00 Target Board Target System J102 J101 J101 J102 2 1 2 Target Cable for 40 Pin Connector 7 Part AP64SD C Order Code SM6532 A e V 5 gt UO 0 3 D Q O 39 40 39 40 39 40
114. N register setting divided by 4096 as the BT clock The CPU is reset whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occurring To do this the BTCNT value must be cleared by writing a 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during the normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter BTCNT is always broken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt In Stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of fxx 4096 for reset or at the rate of the preset clock source for an external interrupt When BTCNT 4 overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summary the following events occur when st
115. NTO INT7 and P6 2 P6 7 INT8 INT13 Please note the following conditions for Stop mode release e f you release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged e f you use an external interrupt for Stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the appropriate control and clock settings before entering Stop mode e When the Stop mode is released by external interrupt the CLKCON 4 and CLKCON 3 bit pair setting remains unchanged and the currently selected clock value is used e The external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed Using an internal Interrupt to Release Stop Mode Activate any enabled interrupt causing stop mode to be released Other things are same as using external interrupt How to Enter into Stop Mode There are two ways to enter into Stop mode 1 Handling OSCCON register 2 Handling STPCON register then writing Stop instruction keep the order 8 6 ELECTRONICS S3F84NB_UM_REV1 00 RESET and POWER DOWN IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6FH In idle mode CPU operations are halted while some peripherals remain active During idle mode the internal clock signal is gated away from the CPU but a
116. O 0 location of the 9 data bit that was received in UARTO mode 2 or 3 0 or 1 If Parity enable mode PENO 1 even odd parity selection bit for receive data in UARTO mode 2 or 3 0 Even parity check for the received data 1 Odd parity check for the received data A result of parity error will be saved in PERO bit of the UARTPND register after parity checking of the received data ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER UARTCONO UARTO Control Register Continued E3H Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 1 Receive Interrupt Enable Bit E Disable Receive interrupt Enable Receive interrupt 0 Transmit Interrupt Enable Bit Disable Transmit interrupt Enable Transmit Interrupt NOTES 1 In mode 2 or 3 if the MCE UARTCON 5 bit is set to 1 then the receive interrupt will not be activated if the received gth qata bit is 0 In mode 1 if 1 then the receive interrupt will not be activated if a valid stop bit was not received In mode 0 the MCE UARTCON 5 bit should be 0 2 The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit 3 Parity enable bits PENO and PEN1 are located in the UARTPND register at address FCH Bank 1 4 Parity enable and parity error check can be available in 9
117. ON ELECTRONICS S3F84NB_UM_REV1 00 SERIAL I O PORT SIO PRESCALER REGISTER SIOPS The control register for the serial I O interface module SIOPS is located in set 1 bank 1 at address The value stored in the SIO prescaler registers SIOPS lets you determine the SIO clock rate baud rate as follows Baud rate Input clock fxx SIOPS value 1 x 4 or SCK input clock SIO Pre Scaler Register SIOPS F4H Set 1 Bank 1 R W SIOPS Data Value Baud rate Input clock fxx SIOPS 1 x 4 or SCK input clock Figure 13 2 SIO Prescaler Register SIOPS ELECTRONICS 13 3 SERIAL I O PORT BLOCK DIAGRAM SIOCON 7 Shift Clock Source Select SCK P2 2 Prescaled Value 1 SIOPS 1 S3F84NB_UM_REV1 00 3 Bit Counter SIO INT SIOCON 1 SIOCON 3 Interrupt Enable SIOCON 4 Shift Clock Edge Select SIOCON 2 Shift Enable SIOCON 5 Mode Select CLK g Bit SIO Shift Buffer SIODATA t SIOCON 6 LSB MSB First Mode Select Data BUS Figure 13 3 SIO Functional Block Diagram ELECTRONICS S3F84NB_UM_REV1 00 SERIAL I O PORT SERIAL I O TIMING DIAGRAMS Shift Clock Sl Data Input Data Sica or X os X 9 X IRQ4 Transmit Complete SET SIOCON 3 Figure 13 4 SIO Timing in Transmit Receive Mode Tx at falling edge SIOCON 4z0 m PP LILI LILI LI L SI D6 D5 D3 D0 SO Data Output Transm
118. ORTS S3F84NB_UM_REV1 00 PORT 2 Port 2 is an 8 bit I O port with individually configurable pins Port 2 pins are accessed directly by writing or reading the port 2 data register P2 at location E2H in set 1 bank 0 P2 0 P2 7 can serve as digital inputs outputs push pull or you can configure the following alternative functions e Low byte pins 2 0 2 3 BZOUT SCK SI SO e High byte pins P2 4 P2 7 TAOUT TACAP TACK TBPWM Port 2 Control Register P2CONH P2CONL Port 2 has two 8 bit control registers 2 for P2 4 P2 7 and P2CONL for 2 0 2 3 A reset clears the P2CONH and P2CONL registers to OOH configuring all pins to input mode You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 2 control registers must also be enabled in the associated peripheral module 9 8 ELECTRONICS S3F84NB_UM_REV1 00 PORTS Port 2 Control Register High Byte P2CONH F2H Set 1 Bank 0 R W P2 4 TBPWM P2 5 TACK P2 6 TACAP P2 7 TAOUT 7 6 bit P2 7 TAOUT 00 Input mode 01 Input mode pull up 10 Push pull output 11 Alternative function TAOUT 5 4 bit P2 6 TACAP 00 Input mode TACAP 01 Input mode pull up TACAP 10 Push pull output 11 Alternative function Not used 3 2 bit P2 5 TACK
119. OTE The Low Byte flash memory sector address pointer value is the lower eight bits of the 16 bit pointer address Figure 19 6 Flash Memory Sector Address Register FMSECL ELECTRONICS 19 7 EMBEDDED FLASH MEMORY INTERFACE S3F84NB_UM_REV1 00 SECTOR ERASE User can erase a flash memory partially by using sector erase function only in user program mode The only unit of flash memory to be erased in the user program mode is a sector The program memory of S3F84NB 64Kbytes flash memory is divided into 512 sectors Every sector has all 128 byte sizes So the sector to be located destination address should be erased first to program a new data one byte into flash memory Minimum 10ms delay time for the erase is required after setting sector address and triggering erase start bit FMCON 0 Sector erase is not supported in tool program modes MDS mode tool or programming tool Sector 511 128 byte Sector 510 128 byte Sector 127 128 byte Sector 11 128 byte Sector 10 128 byte Sector 0 9 128 byte x 10 Figure 19 7 Sector Configurations in User Program Mode 19 8 ELECTRONICS S3F84NB_UM_REV1 00 EMBEDDED FLASH MEMORY INTERFACE The Sector Erase Procedure in User Program Mode 1 2 3 4 Set Flash Memory User Programming Enable Register FMUSR to 10100101B Set Flash Memory Sector Address Register FMSECH and FMSECL Set Flash Memory Control Register FMCON to 10100001B Set Flash
120. OUTO Timer C 8 bit PWM mode output or counter 28 27 P3 6 P3 7 TCOUT1 match toggle output pins 21 20 T1CKO External clock input pins for timer 1 34 33 P3 0 P3 1 T1CK1 27 26 RxD0 RxD1 lO Serial data RxD pin for receive input and G 22 25 P5 3 P5 1 transmit output mode 0 15 18 4 3 2 2 es T1CAPO Capture input pins for timer 1 32 31 P3 2 P3 3 T1CAP1 25 24 T1OUTO Timer 1 16 bit PWM mode output or counter 30 29 P3 4 P3 5 T1OUT1 match toggle output pins 23 22 SI SO SCK lO Synchronous SIO pins 11 12 10 P2 1 P2 0 4 5 3 P2 2 dm a9 TEST Vpp mM Pull down resistor connected internally 2003 XTn XTout Subsystem oscillator pins F 2 E P6 0 P6 1 Ld Main oscillator pins 1 3 nRESET System reset pin pull up resistor 240kQ 23 16 20 13 NGUY 19 18 12 11 NOTE Pin numbers shown in parentheses are for the 64 pin QFP package 1 8 ELECTRONICS S3F84NB_UM_REV1 00 PIN CIRCUITS ELECTRONICS Pull Up Resistor Schmitt Trigger Figure 1 4 Pin Circuit Type B nRESET P Channel Data Out Output N Channel Disable Figure 1 5 Pin Circuit Type C PRODUCT OVERVIEW 1 9 PRODUCT OVERVIEW Pull up Enable Data Pin Circuit Output Type C Disable Figure 1 6 Pin Circuit Type D Port 0 2 3 and P5 0 P5 3 lt Pull up Data Pin Circuit Enable in Circu o VO Output Disable Noise Ext INT Input Norm
121. Operation does not generate a carry or borrow conditidn EN Operation generates carry out or borrow into high ord drbit7 Zero Flag Z EN Operation result is a non zero value an Operation result is zero Sign Flag 5 Operation generates positive number MSB 0 Operation generates negative number MSB 1 Description of the effect of specific bit settings RESETvalue notation Not used Undetermined value 0 2 Logic zero 1 Logic one Bit number MSB Bit 7 LSB Bit 0 Figure 4 1 Register Description Format 4 5 CONTROL REGISTERS S3F84NB_UM_REV1 00 ADCON A D Converter Control Register F7H Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value 0 0 0 0 0 0 0 Read Write _ R W R W R W R R W R W R W Addressing Mode Register addressing mode only 7 Not used for the S3F84NB must keep always 0 6 4 A D Input Pin Selection Bits 3 End of Conversion Bit Read only EN A D conversion opration is in progress A D conversion opration is complete 2 Clock Source Selection Bits ojoje of es 0 Start or Enable Bit EN Disable operation Start operation 4 6 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER BTCON Basic Timer Control Register D3H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Watchd
122. PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Next OPCODE PX Program Memory Address Used PC Value Current Instruction OPCODE Signed U UV M n Displacement Value Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELECTRONICS 3 13 ADDRESSING MODES S3F84NB_UM_REV1 00 IMMEDIATE MODE IM In Immediate IM addressing mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD RO0 0AAH Figure 3 14 Immediate Addressing 3 14 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER CONTROL REGISTERS OVERVIEW Control register descriptions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of th
123. Q register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Set 1 R wo 5 IRQO IRQ2 IRQ3 IRQ5 IRQ4 Interrupt level request pending bit 0 IRQ interrupt is not pending 1 IRQ interrupt is pending Figure 5 9 Interrupt Request Register IRQ 5 14 ELECTRONICS S3F84NB_UM_REV1 00 INTERRUPT STRUCTURE INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared in the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot
124. R The interrupt mask register IMR set 1 DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W RQ3 IR IRQ6 ER IRQ7 Interrupt level enable bits 0 Disable mask interrupt level 1 Enable un mask interrupt level NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended Figure 5 6 Interrupt Mask Register IMR ELECTRONICS 5 11 INTERRUPT STRUCTURE S3F84NB_UM_REV1 00 INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR set 1 bank 0 FFH is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the ini
125. R ELECTRONICS 6 33 INSTRUCTION SET S3F84NB_UM_REV1 00 DA Decimal Adjust DA Example Continued Given Working register RO contains the value 15 BCD working register R1 contains 27 BCD and address 27H contains 46 BCD ADD R1 R0 i C H lt 0 Bits 4 7 3 bits 0 3 C R1 lt 3CH DA R1 R1 lt 3CH 06 If addition is performed using the BCD values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H RO i C lt H lt 0 Bits 4 7 3 bits 0 3 1 DA R1 R1 lt 31 0 leave the value 31 BCD in address 27H 1 ELECTRONICS S3F84NB_UM_REV1 00 DEC Decrement DEC Operation Flags Format Examples dst dst lt dst 1 The contents of the destination operand are decremented by one Unaffected Set if the result is 0 cleared otherwise Set if result is negative cleared otherwise Set if arithmetic overflow occurred cleared otherwise Unaffected Unaffected TOSONO Bytes Cycles Given R1 and register 03H 10H DEC R1 gt R1 02H DEC R1 gt Register 03H OFH
126. R E1 IR Given Register 00H 31H register 01H 02H and register 02H 17H RR 00H gt Register 00H 98H C 1 RR gt Register 01H 02H register 02H 8BH C 1 In the first example if general register contains the value 31H 001 10001 the statement RR rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and overflow flag are also set to 1 ELECTRONICS 6 73 INSTRUCTION SET S3F84NB_UM_REV1 00 RRC Rotate Right Through Carry RRC Operation Flags Format Examples dst dst 7 lt C lt dst 0 dst n dst n 1 n 0 6 The contents of the destination operand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag the initial value of the carry flag replaces bit 7 MSB C Set if the bit rotated from the least significant bit position bit zero was 1 Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 CO R 4 C1 IR Given Register 00H 55H register 01H 02H regist
127. Register FLAGS 6 6 ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET FLAG DESCRIPTIONS FIS BA Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero For operations that test register bits and for shift and rotate operations the Z flag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever
128. S3F84NB_UM_REV1 00 Table 20 11 UART Timing Characteristics in Mode 0 TA 40 C to 85 C Vpp 2 0 V to 5 5 V Load capacitance 80 pF Serial port clock High Low level width NOTES 1 All timings are in nanoseconds ns and assume 10 MHz CPU clock frequency 2 The unit tcpy means one CPU clock period Figure 20 9 Waveform for UART Timing Characteristics 20 12 ELECTRONICS S3F84NB_UM_REV1 00 ELECTRICAL DATA Table 20 12 A D Converter Electrical Characteristics TA 40 to 85 Vpp 2 0 V to 5 5 V Vgs 2 Integral linearity ILE CPU clock 10 MHz error AVnge 5 12 V Differential DLE AVss OV linearity error Offset error of EOT top Offset error of EOB bottom Conversion tcon 10 bit conversion Analog input VIAN voltage Analog input Ran impedance Analog reference voltage Analog input lADIN Vpp 5V current Analog block lADC Vpp 5V current 2 NOTES 1 Conversion time is the time required from the moment a conversion operation starts until it ends 2 lapc is operating current during A D conversion 3 fggc is the main oscillator clock ELECTRONICS 20 13 ELECTRICAL DATA S3F84NB_UM_REV1 00 Digital Output Analog Input AVss VEOB V2 VEOT AVREF Figure 20 10 Definition of DLE and ILE 20 14 ELECTRONICS S3F84NB_UM_REV1 00 ELECTRICAL DATA Table 20 13 LVR Circuit Characteristics Ta 25 C
129. SAMSUNG OTP devices Low cost Download the files from the 3rd party link shown below C amp A Technology TEL 82 2 2612 9027 FAX 82 2 2612 9044 E mail caat unitel co kr URL http Awww cnatech com International Sale SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail cindy seminix com e URL http Awww seminix com Jui 2002 USER s Manual a Rev 0 aij i ALII Syston Lid BlueChips Combi BlueChips combi is a programmer for all Samsung MCU It can program not only all Samsung OTP MTP Flash MCU but also the popular E E PROMs New devices will be supported just by adding device files or upgrading the software It is connected to host PC s serial port and controlled by the software System TEL 82 31 223 6611 FAX 82 31 223 6613 e E mail openice aijisystem com e URL http www aijisystem com p N f W sae GW PRO2 Gang Programmer for One time PROM device e 8 devices programming at one time e Fast programming speed 1 2Kbyte sec e PC based control operation mode e Full Function regarding OTP program Read Program Vertify Protection blank e Data back up even at power break After setup in Desgin Lab it can be moved to the factory site Key Lock protecting operator s mistake Good Fail quantity displayed and memorized Buzzer sounds after programming User friendly single menu operation PC Operation mode displayed in LCD pannel
130. Stack ELECTRONICS 6 41 INSTRUCTION SET EXIT Exit S3F84NB_UM_REV1 00 EXIT Operation IP lt SP SP lt SP 2 lt IP IP lt 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 internal stack 2F 16 internal stack Example The diagram below shows one example of how to use an EXIT statement Before After Address Data Address Data P 0050 Address Data Address Data 50 PCL old 60 Main 51 PCH se se 0022 140 Exit 20 IPH 00 21 IPL J 50 22 Data Memory 22 Data Memory Stack Stack 6 42 ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET IDLE Idle Operation IDLE Operation The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 6F _ Example The instruction IDLE stops the CPU clock but not the system clock ELECTRONICS 6 43 INSTRUCTION SET INC Increment INC Operation Flags Format Examples dst
131. T P4INTPND UARTCONO UARTCON1 UDATAO UDATA1 UARTPND E1H EOH bank1 F5H bank1 E8H bankO E9H EDH bankO F6H bank 0 F7H bank 0 FAH bank 0 FBH bank 0 E3H bank 1 FBH bank 1 E2H FAH bank 1 E5H bank 1 5 9 INTERRUPT STRUCTURE S3F84NB_UM_REV1 00 SYSTEM MODE REGISTER SYM The system mode register SYM set 1 DEH is used to globally enable and disable interrupt processing see Figure 5 5 A reset clears SYM 0 to 0 The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate SYM 0 directly to enable and disable interrupts during the normal operation it is recommended to use the El and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W Global interrupt enable bit 0 Disable all interrupts processing 1 Enable all interrupts processing Not used for the SSF84NB Fast interrupt level selection bits Fast interrupt enable bit 0 Disable fast interrupts processing 1 Enable fast interrupts processing 5 GOOO O O O O Figure 5 5 System Mode Register SYM 5 10 ELECTRONICS S3F84NB_UM_REV1 00 INTERRUPT STRUCTURE INTERRUPT MASK REGISTER IM
132. TBUN INT ORG 0100h LD SYM 00h LD IMR 00000001b LD SPH 00000000b LD SPL 00000000b LD BTCON 1010001 1b LD P2CONH 0000001 1b LD TBDATAH 80h LD TBDATAL 80h LD TBCON 11101110b El MAIN ROUTINE JR T MAIN Interrupt service routine IRET END ELECTRONICS 8 BIT TIMER A B C 0 1 Disable Global Fast interrupt Enable IRQO interrupt Set stack area Disable Watch dog Enable TBPWM output Enable interrupt fxx 256 Repeat Duration 6 605ms 10 MHz x tal 11 15 8 BIT TIMER A B C 0 1 S3F84NB_UM_REV1 00 PROGRAMMING TIP Using the Timer C 0 ORG 0000h VECTOR 0C4h TCUN INT ORG 0100h INITIAL LD SYM 00h Disable Global Fast interrupt LD IMR 00000100b Enable IRQ2 interrupt LD SPH 00000000b Set stack area LD SPL 00000000b LD BTCON 1010001 1b Disable Watch dog LD P3CONH 00110000b Enable TCOUTO output SB1 LD TCDATAO 80h LD TCCONO 10001110b Enable interrupt non div fxx 64 Duration 1 638ms 10 MHz x tal SBO El MAIN MAIN ROUTINE JR T MAIN TCUN_INT e e Interrupt service routine IRET END 11 16 ELECTRONICS S3F84NB_UM_REV1 00 16 BIT TIMER 1 0 1 16 BIT TIMER 1 0 1 OVERVIEW The S3F84NB has two 16 bit timer counters The 16 bit timer 1 0 1 is an 16 bit general purpose timer counter Timer 1 0 1 has three operating modes one of which you select using the appropriate T1CONO T1CON1 setting is e Interval timer mode Toggle o
133. TERRUPT STRUCTURE Interrupt Priority Register IPR FEH Set 1 Bank 0 R W ve 5 s 2 s I 0 IRQ0 gt IRQ1 1 IRQ1 gt IRQ0 Group priority D7 D4 D1 Undefined B gt C gt A Group B A gt B gt C 0 IRQ2 gt IRQ3 IRQ4 gt gt 1 IRQ3 IRQ4 gt IRQ2 C gt A gt B Subgroup B gt gt 0 IRQ3 gt IRQ4 A gt C gt B 1 IRQ4 gt IRQ3 Undefined 0 0 0 0 1 1 1 1 k OO Group 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 Figure 5 8 Interrupt Priority Register IPR ELECTRONICS 5 13 INTERRUPT STRUCTURE S3F84NB_UM_REV1 00 INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ set 1 DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to IRQ1 and so on A 0 indicates that no interrupt request is currently being issued for that level A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IR
134. TRUCTURE The S3F84NB microcontroller supports twenty nine interrupt sources All of the interrupt sources have a corresponding interrupt vector address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed ELECTRONICS 5 3 INTERRUPT STRUCTURE S3F84NB_UM_REV1 00 Levels Vectors Sources Reset Clear IRQ0 Timer B underflow HAN Timer A match capture H W S W C2H Timer A overflow H W S W IRQ1 C4H Timer C 0 match overflow H W S W C6H _ Timer 1 match overflow H W S W C8H t Timer 1 0 match capture S
135. Timer A overflow interrupt enable bit counter running OVF can occur 0 Disable overflow interrupt 11 PWM mode OVF interrupt and match 1 Enable overflow interrrupt interrupt can occur Timer A counter clear bit 0 No effect 1 Clear the timer A counter when write When th counter clear bit 3 is set the 8 bit counter is cleared and it also is cleared automatically Figure 11 1 Timer A Control Register TACON ELECTRONICS 11 3 8 BIT TIMER A B C 0 1 S3F84NB_UM_REV1 00 BLOCK DIAGRAM TACON 2 I Overflow TACON 7 6 DERBI TINTPND 1 8 bit Up Counter Clear a TACON 3 Read Only TACON 1 Match TAINT 8 bit Comparator U X Timer A Data Register TACON 5 4 Read Write Data Bus a TEN TINTPND O PG output signal NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bit is located at TINTPND register Figure 11 2 Timer A Functional Block Diagram 11 4 ELECTRONICS S3F84NB_UM_REV1 00 8 BIT TIMER A B C 0 1 8 BIT TIMER B OVERVIEW The S3F84NB micro controller has an 8 bit timer called timer B Timer B which can be used to generate the carrier frequency of a remote controller signal Also it can be used as the programmable buzz signal generator that makes a sound with a various frequency from 200Hz to 20kHz These various frequencies can be used to generate a melody sound Timer B has two functions e Asanormal interval timer generating a timer
136. User program mode enable LD FMCON 01010000B Selection programming mode and Start programming LD FMSECH 01H Set the base address of sector located in target address to write data LD FMSECL 00H The sector 2 s base address is 100H LD R9 0CCH Load data to write LD R10 01H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register CALL WR_BYTE LD RO 40H WR INSECTOR50 LD FMSECH 19H Set the base address of sector located in target address to write data LD FMSECL 00H The sector 50 s base address is 1900H LD R9 55H Load data 55H to write LD R10 19H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register CALL WR_BYTE WR_INSECTOR128 LD FMSECH 40H Set the base address of sector located in target address to write data LD FMSECL 00H The sector 128 s base address is 4000H LD R9 0A3H Load data to write LD R10 40H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register WR_BYTE1 LDC RR10 R9 Write data A3H at flash memory location INC R11 DJNZ R1 WR BYTE1 LD FMUSR 00H User Program mode disable LD PP 00H WR_BYTE LDC QRR10 R9 Writ
137. VIC Wises toro critt etos cosa eset pet es ces Soe IL e m EM 17 1 Pattern Generation itp edo cet eh ere mre i eter deeem ae ieee 17 1 Chapter 18 Low Voltage Reset OVENVIOW E aE 18 1 53 84 UM REV1 00 MICROCONTROLLER ix Table of Contents Concluded Chapter 19 Embedded Flash Memory Interface MUNERE LT 19 1 Flash ROM Configurations accented din dta Ae en Mina dias 19 1 User Program Mode tite var Erbe aper ieget deeds 19 2 Tool Program iisti urani eene trita ade He e dex tx asia alee d ae i addat 19 2 ISP On Board Programming Sector ciis asit catre tein hace edt ceste aci ete ad ruga 19 3 SMart Option EE 19 4 Flash Memory Control Registers User Program Mode a 19 6 Flash Memory Control Register FMCON 19 6 Flash Memory User Programming Enable Register FMUSR sse 19 6 Flash Memory Sector Address enne 19 7 Sector Era Se EU 19 8 The Sector Erase Procedure In User Program Mode sse 19 9 Prograrni i ooe aa i EE 19 12 The Program Procedure In User Program 19 12 Reading 19 17 The Program Procedure In User Program Mode
138. W Brud rate data Figure 14 4 UART Baud Rate Data Register BRDATAHO BRDATALO BRDATAH1 BRDATAL1 BAUD RATE CALCULATIONS Mode 0 Baud Rate Calculation In mode 0 the baud rate is determined by the baud rate data register 16bit BRDATA Mode 0 baud rate fxx 16 x 16Bit BRDATA 1 Mode 2 Baud Rate Calculation In mode 2 the baud rate is determined by the baud rate data register 16bit BRDATA Mode 2 baud rate fxx 16 x 16Bit BRDATA 1 Modes 1 and 3 Baud Rate Calculation In modes 1 and 3 the baud rate is determined by the baud rate data register 16bit BRDATA Mode 1 and 3 baud rate fxx 16 x 16Bit BRDATA 1 14 6 ELECTRONICS S3F84NB_UM_REV1 00 UART O 1 Table 14 1 Commonly Used Baud Rates Generated by BRDATAO BRDATA1 mam wwe o mw m m om ewe mw os rm pemom o w 3 m eson wwe o m mson fom w ws on hm o o m o mson o o 9 m emo o o m sesm we o mw 25 9 ELECTRONICS 14 7 UART O 1 S3F84NB UM REV1 00 BLOCK DIAGRAM SAM8 Internal Data Bus 16BIT G BRDATA Baud Rate Generator Zero Detector Write to UDATA Start Shift Tx Control Tx Clock TIP P5 2 P5 0 IRQ7 Interrupt RIP Receive Rx Control Shift 1 to 0 Transition Detector hift SAM8 Internal Data Bu
139. W CAH Timer 1 0 overflow H W S W IRQ2 CCH Timer 1 1 match capture S W CEH Timer 1 1 overflow H W S W DOH s SIO receive transmit S W Watch timer S W D4H P6 2 external interrupt S W D6H P6 3 external interrupt S W D8H _ P6 4 external interrupt S W DAH P6 5 external interrupt S W DCH P6 6 external interrupt S W DEH P6 7 external interrupt SAN P4 0 external interrupt S W E2H P4 1 external interrupt S W E4H P4 2 external interrupt S W E6H P4 3 external interrupt S W v P4 4 external interrupt S W EAH P4 5 external interrupt S W P4 6 external interrupt S W P P4 7 external interrupt S W FOH data receive S W F2H data transmit H W S W F4H UART1 data receive S W F6H UART1 data transmit H W S W NOTES 1 Within a given interrupt level the lower vector address has high priority For example DCH has higher priority than DEH within the level IRQ5 the priorities within each level are set at the factory 2 External i
140. W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RP0 and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP1 points to address C8H in register set 1 selecting the 8 byte working register slice 2 0 Not used for the SSF84NB 4 36 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER SIOCON sio Control Register E1H Set 1 Bank 1 Bit Identifier 7 6 5 4 33 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 SIO Shift Clock Selection Bit Internal clock P S clock 1 External clock SCK 6 Data Direction Control Bit MSB first mode LSB first mode le 5 SIO Mode Selection Bit Receive only mode 1 Transmit receive mode 4 Shift Start Edge Selection Bit Tx at falling edges Rx at rising edges le Tx at rising edges Rx at falling edges 3 SIO Counter Clear and Shift Start Bit No action 1 Clear 3 bit counter and start shifting Auto clear bit 2 SIO Shift Operation Enable Bit Disable shifter and clock counter 1 Enable shifter and clock counter 1 SIO Interrupt Enable Bit Disable SIO interrupt 1 Enable SIO interrupt 0 SIO Interrupt Pending Bit No interrupt pendin
141. a 5 5 5 4 Interrupt Function Diagrami oraire E E E E DENERA 5 8 5 5 System Mode Register SYM n 5 10 5 6 Interrupt Mask Register 5 11 5 7 Interrupt Request Priority Groups a 5 12 5 8 Interrupt Priority Register IPR 5 13 5 9 Interrupt Request Register IRQ 5 14 6 1 System Flags Register FLAGS sse rennen nennen 6 6 7 1 Main Oscillator Circuit Crystal or Ceramic Oscillator 7 1 7 2 Sub System Oscillator Circuit Crystal Oscillator 7 1 7 3 System Clock Circuit Diagram L 7 2 7 4 System Clock Control Register 1 7 3 7 5 Oscillator Control Register 7 4 7 6 STOP Control Register STOPCONJ U 7 4 9 1 Port 0 Control Register POCON sse ennt entren enne 9 4 9 2 Port 1 High Byte Control Register P1CONH a 9 6 9 3 Port 1 Low Byte Control Register 1 9 7 9 4 Port 2 High Byte Control Register 2 9 9 9 5 Port 2 Low Byte Control Register P2CONL seen 9 10 9 6 Port High Byte Con
142. a Input mode rising edge interrupt K EJ Input mode pull up falling edge interrupt Push pull output ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER P6CONL Port 6 Control Register Low Byte E9H Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 1 1 1 1 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 6 ELECTRONICS Register addressing mode only P6 3 INT9 Input mode falling edge interrupt ESEE Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output P6 2 INT8 Lo O t Input mode sing edge intorupt 0 input moge pulp tating edge P6 1 XToyt ro o iremos a o Push pullout P6 0 XT in roo mame o iromo po _ EJEA Push pull output Alternative function Sub Clock Oscillator Input v CONTROL REGISTERS P6INT Port 6 Interrupt Control Register Bit Identifier RESET Value Read Write Addressing Mode 4 32 S3F84NB_UM_REV1 00 EDH Set 1 Bank 0 7 6 5 4 3 2 0 0 0 0 0 0 0 0 R W R W R W R W R W R W _ _ Register addressing mode only P6 7 External Interrupt INT13 Enable Bit Disable interrupt Enable interrupt P6 6 External Interrupt INT12 Enable Bit Disable interrupt Enable interrupt P6 5 External Interrupt INT11 Enable Bit Disable int
143. a bit or parity bit e Stop bit 1 lt In parity disable mode PENO 0 or PEN1 0 gt The 9th data bit to be transmitted can be assigned a value of 0 or 1 by writing the TB8 bit UARTCONO 3 When receiving the 9th data bit that is received is written to the RB8 bit UARTCONO 2 while the stop bit is ignored The baud rate for mode 2 amp 3 is fosc 16 x 16bit BRDATA 1 clock frequency lt In parity enable mode PENO 1 or 1 gt The 9th data bit to be transmitted can be an automatically generated parity of 0 or 1 depending on a parity generation by means of TB8 bit UARTCONO 3 When receiving the received 9th data bit is treated as a parity for checking receive data by means of the RB8 bit UARTCONO 2 while the stop bit is ignored The baud rate for mode 2 amp 3 is fosc 16 x 16bit BRDATA 1 clock frequency Mode 2 amp 3 Transmit Procedure 1 Select the baud rate generated by 16bit BRDATA 2 Select mode 2 amp 3 9 bit UARTO by setting UARTCONO bits 6 and 7 to 10B Also select the 9th data bit to be transmitted by writing TB8 to 0 or 1 and set PENO PEN1 bit of UARTPND register to 0 if you don t use a parity mode If you want to use the parity enable mode select the parity bit to be transmitted by writing TB8 to 0 or 1 and set PEN1 bit of UARTPND register to 1 3 Write transmission data to the shift register UDATAO E2H set 1 bank 1 to start the transmi
144. address bits from the instruction are concatenated to form the complete register address OABH 10101011B Selects RPO or RP1 Address These address POT bits indicate 8 bit 8 bit logical working register address addressing Register pointer Three low order bits provides five high order bits HHH 8 bit physical address Figure 2 14 8 Bit Working Register Addressing 2 18 ELECTRONICS S3F84NB_UM_REV1 00 Selects RP1 R11 8 bit address 1100 01 1 form instruction LD R11 L Specifies working register addressing ADDRESS SPACES RP1 Register OABH Figure 2 15 8 Bit Working Register Addressing Example ELECTRONICS 2 19 ADDRESS SPACES S3F84NB_UM_REV1 00 SYSTEM AND USER STACK The S3C8 series microcontrollers use the system stack for data storage subroutine calls and returns The PUSH and POP instructions are used to control system stack operations The S8F84NB architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAGS register are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push ope
145. ain an El instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing e interrupt mask register IMR enables un masks or disables masks interrupt levels e The interrupt priority register IPR controls the relative priorities of interrupt levels e interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source e The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register i RW Function Description Interrupt mask register IMR R W Bitsettings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels IRQO IRQ 7 Interrupt priority register R W _ Controls the relative processing priorities of the interrupt levels The seven levels of S3F84NB are organized into three groups A B and C Group A is IRQO and IRQ1 group B is IRQ2 and IRQ4 and g
146. al Figure 1 7 Pin Circuit Type D 1 Port 4 and P6 2 P6 7 S3F84NB_UM_REV1 00 ELECTRONICS S3F84NB_UM_REV1 00 ELECTRONICS Pull up Enable Output Disable Normal Input Analog Input Pull up Resistor Typical Value 47kQ In Out Figure 1 8 Pin Circuit Type E Port 1 PRODUCT OVERVIEW PRODUCT OVERVIEW S3F84NB_UM_REV1 00 Pull up enable Output Data o Output Disable Input Mode Digital Input Alternative I O Enable XTin XTout Oscillation circuit Figure 1 9 Pin Circuit Type F P6 0 P6 1 Open Drain q P Channel Pull up Data Enable Output N Channel Disable Figure 1 10 Pin Circuit Type G P5 4 P5 7 1 12 ELECTRONICS S3F84NB_UM_REV1 00 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3F84NB microcontroller has two types of address space e Internal program memory Flash memory e Internal register file A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the register file The S3F84NB has a programmable internal 64 Kbytes Flash ROM An external memory interface is not implemented ELECTRONICS 2 1 ADDRESS SPACES S3F84NB_UM_REV1 00 PROGRAM MEMORY Program memory Flash memory stores program code or table data The S8F84NB has 64 Kbyte of internal programmable Flash memory The program memory address range is therefore 0000H FFFFH of Flash memory See Figu
147. al the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET S3F84NB_UM_REV1 00 CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example dst src RA If dst src 0 RA Ir lt Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 3 12 D2 ro dr NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 and register 03H 04H CPIJNE R1 R2 SKIP gt R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value 03H and general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the
148. alclockfalingedge o 1 i 0 Extemal clock risingedoe o 4 8 Timer 1 0 Operating Mode Selection Bits 0 0 Interval mode oja Capture mode Capture on rising edge OVF can occur PWM mode KE fo Capture mode Capture on falling edge OVF can occur 2 Ti 3 er 1 0 Counter Enable Bit No effect 1 Clear the timer 1 0 counter Auto clear bit 1 Timer 1 0 Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer 1 0 Overflow Interrupt Enable Disable overflow interrupt 1 Enable overflow interrupt ELECTRONICS 4 41 CONTROL REGISTERS S3F84NB_UM_REV1 00 T1CON1 Timer 1 1 Control Register EBH Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer 1 1 Input Clock Selection Bits ofo ws Fo r o me 1 0 1 extemalclockfalingedge o 1 1 0 Exemalcockrsingedge _ U 4 8 Timer 1 1 Operating Mode Selection Bits 0 0 Interval mode oja Capture mode Capture on rising edge OVF can occur PWM mode EEA Capture mode Capture on falling edge OVF can occur 2 3 er 1 1 Counter Enable Bit No effect 1 Clear the timer 1 1 counter Auto clear bit 1 Timer 1 1 Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer 1
149. ammable port input or XTn output mode selected by software input or push pull output Software assignable pull up P6 0 and P6 1 can alternately be used for subsystem oscillator in out mode selected by software P6 2 P6 7 are bit programmable port input or INT8 INT13 output mode selected by software input or push pull output Software assignable pull up P6 2 P6 7 can alternately be used as inputs for external interrupts INT8 INT13 respectively with noise filters and interrupt controller NOTE Pin numbers shown in parentheses are for the 64 pin QFP package ELECTRONICS 1 7 PRODUCT OVERVIEW S3F84NB_UM_REV1 00 Table 1 1 S3F84NB Pin Descriptions Continued Pin Pin Pin Circuit Pin Share Name Type Description Type Number Pins Alternatively used as general purpose digital ADCO ADC7 60 57 54 51 P1 0 P1 7 53 50 47 44 input output port 1 PGO PG7 Pattern generator Output Alternatively used 4 1 64 61 P0 0 P0 7 as general purpose digital input output port 0 61 54 AVREF A D converter reference voltage and ground 55 56 AVSS 48 49 Analog input pins for A D converter module Serial data TxD pin for transmit output and TxDO TxD1 TACK cde External clock input pins for timer A TACAP E Capture input pins for timer A 24 26 P5 2 P5 0 17 19 6 shift clock input mode 0 TAOUT Pulse width modulation output pins for timer A Carrier frequency output pins for timer B 8 TC
150. an addition generates a carry out of bit 3 or when a subtraction borrows Out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is seldom accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when you execute the SBO instruction and is set to 1 select bank 1 when you execute the SB1 instruction ELECTRONICS 6 7 INSTRUCTION SET INSTRUCTION SET NOTATION S3F84NB_UM_REV1 00 Table 6 2 Flag Notation Conventions 2 5 V D H 0 1 Carry flag Zero flag Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register D5H Register pointer Immediate operand or registe
151. an configure the following alternative functions e Low byte pins P3 0 P3 3 T1CAP1 TICAP0 T1CK1 T1CKO High byte pins P3 4 P3 7 TCOUT1 TCOUTO T1OUT1 T1OUTO To individually configure the port 3 pins 0 7 you make bit pair settings in two control registers located in set 1 bank 0 PSCONL low byte F5H and PSCONH high byte F4H Port 3 Control Registers P3CONL Two 8 bit control registers are used to configure port 3 pins PSCONL F5H set 1 Bank 0 for pins P3 0 P3 3 and P3CONH F4H set 1 Bank 0 for pins 4 7 Each byte contains four bit pairs and each bit pair configures one pin of port 3 ELECTRONICS 9 11 PORTS S3F84NB UM REV1 00 Port 3 Control Register High Byte F4H Set 1 Bank 0 R W 5 o e P3 4 T1OUTO P3 5 T1OUT1 P3 6 TCOUTO P3 7 TCOUT1 7 6 bit P3 7 TCOUT1 Input mode Input mode pull up Push pull output Alternative function TCOUT1 5 4 bit P3 6 TCOUTO Input mode Input mode pull up Push pull output Alternative function TCOUTO 3 2 bit P3 5 T1OUT1 Input mode Input mode pull up Push pull output Alternative function T1OUT1 1 0 bit P3 4 T10UTO Input mode Input mode pull up Push pull output Alternative function T1OUTO Figure 9 6 Port 3 High Byte Control Register 9 12 ELECTRONICS S3F84NB_UM_REV1 00 PORTS Port 3 Control Register Low Byte P3CONL
152. and 5 0 5 3 1 7 Pin Circuit Type D 1 Port 4 and 6 2 6 7 1 8 Pin Circuit Type E Port 1 sse 1 9 Pin Circuit Type F P6 0 6 1 1 10 Pin Circuit Type G 5 4 5 7 2 1 Program Memory Address Space 2 2 Smart ODptlOn u he eh ah ea a eins 2 3 Internal Register File Organization 2 4 Register Page Pointer 2 5 Set1 Set2 Primer Aera Register 2 6 8 Byte Working Register Areas Slices 2 7 Contiguous 16 Byte Working Register Block 2 8 Non Contiguous 16 Byte Working Register Block 2 9 16 Bit Register Pair entren 2 10 Register File Addressing uu u 2 11 Common Working Register Area 2 12 4 Bit Working Register Addressing a 2 13 4 Bit Working Register Addressing Example 2 14 8 Bit Working Register Addressing 2 15 8 Bit Working Register Addressing Example
153. at execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS 6 13 INSTRUCTION SET S3F84NB_UM_REV1 00 ADC Add with carry ADC Operation Flags Format Examples dst src dst lt dst src c The source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction permits the carry from the addition of low order operands to be carried into the addition of high order operands C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise Always cleared to H Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst src 2 4 12 root 6 13 r Ir opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Given R1 10H R2 C flag 1 register 01H 20H register 02H and register OAH ADC R1 R2 ADC R1 R2 ADC 01H 02H ADC 01H 02H ADC O1H 11H R1 14H R2
154. at the stop release signal activates to the time that basic timer starts counting Figure 7 5 Oscillator Control Register OSCCON STOP Control Register STPCON FDH Set 1 Bank 1 R W STOP Control bits Other values Disable STOP instruction 10100101 Enable STOP instruction 7 4 Figure 7 6 STOP Conirol Register 6 ELECTRONICS S3F84NB_UM_REV1 00 RESET and POWER DOWN RESET and POWER DOWN SYSTEM RESET OVERVIEW During a power on reset the voltage at Vpp goes to High level and the nRESET pin is forced to Low level The RESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This procedure brings S38F84NB into a known operating status To allow time for internal CPU clock oscillation to stabilize the nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance The minimum required oscillation stabilization time for a reset operation is 1 millisecond Whenever a reset occurs during normal operation that is when both Vpp and nRESET are High level the nRESET pin is forced Low and the reset operation starts All system and peripheral control registers are then reset to their default hardware values In summary the following sequence of events occurs during a reset operation e Interrupt is disabled e The watchdog function basic timer is enabled e Ports 0 6 are set to input mode P6 0 and P6 1 a
155. ata 4 50 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER UARTCONT1 UART 1 Control Register Continued FBH Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 1 Receive Interrupt Enable Bit E Disable receive interrupt Enable receive interrupt 0 Transmit Interrupt Enable Bit EN Disable transmit interrupt Enable transmit Interrupt NOTES 1 In mode 2 or 3 if the MCE UARTCON 5 bit is set to 1 then the receive interrupt will not be activated if the received gth data bit is 0 In mode 1 if MCE 1 then the receive interrupt will not be activated if a valid stop bit was not received In mode 0 the MCE UARTCON 5 bit should be 2 The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit 3 Parity enable bits PENO and PEN1 are located in the UARTPND register at address FCH Bank 1 4 Parity enable and parity error check can be available in 9 bit UART mode Mode 2 3 only ELECTRONICS 4 51 CONTROL REGISTERS S3F84NB_UM_REV1 00 UARTPND UARTO 1 Pending and parity control FCH Set 1 Bank 1 Bit Identifier 7 6 5 E 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 UART1 Parity Enable Disable PEN1 E Disable Enable 6 UART1 Receive Parity Error RPE1
156. ated from the most significant bit position bit 7 was 1 Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 90 R 91 IR Given Register OAAH register 01H 02H and register 02H 17H RL 00H gt Register OOH 55H C 1 RL gt Register 01H 02H register 02H 2EH C In the first example if general register contains the value OAAH 10101010B the statement RL 00H rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and overflow flags ELECTRONICS 6 71 INSTRUCTION SET S3F84NB_UM_REV1 00 RLC Rotate Left Through Carry RLC Operation Flags Format Examples dst dst 0 C C dst 7 dst 1 dst n n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C the initial value of the carry flag replaces bit zero C Setif the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaf
157. bank 1 register addressing if implemented 6 76 ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET SBC Subtract With Carry SBC Operation Flags Format Examples dst src dst lt dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands C Set if a borrow occurred src gt dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opcode Addr Mode Hex dst src 6 33 r Ir opc src dst 3 6 34 R R 35 R IR dst src 3 6 36 R IM Given R1 10H R2 03H 1 register 01H 20H register 02H 03H and register 03H OAH SBC R1 R2 gt SBC R1 R2 gt SBC
158. ce Interrupt Service Routines U n aa Generating interrupt Vector Addresses Nesting of Vectored Chapter 6 Instruction Set Overview vi Flags Register FLAGS Flag Descriptions u deen u Hd etit dade ha de dels Instruction Set Notation Instruction Descriptions S3F84NB_UM_REV1 00 MICROCONTROLLER Table of Contents Continued Part Il Hardware Descriptions Chapter 7 Clock Circuit iM D IEEE 7 1 System Clock a n Sun tete d te E Re Sat pus eee ies edt aec RE eda neath 7 1 Clock Status During Power Down Modes sse enne n nnns enne nns 7 2 System Clock Control Register CLKCONJ a nennen 7 8 Chapter 8 RESET and Power Down System RESEN cesta oes eet eae ut e ne Ln sd D S ces kc 8 1 NI m 8 1 Normal Mode Reset 8 1 Hardware spa a ste eate kiku wayay 8 2 Power Down MOod s u eni ae eed eua 8 6 8 6 tdle Mode 3 vi taii teri ico ea exea tt ESI LER LUCR O dain ceed sinbeene e RUNE sins 8 7 Chapter 9 I O Ports OVGIVIOW ted oa deed t e e ott ot de ete 9 1 Pon Data Rogiers oce ecd tace t dn bn
159. clears bit one of the destination register R1 leaving the value 05H 00000101B ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET BITS Bit Set BITS Operation Flags Format Example dst b dst b lt 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 O7H BITS R1 3 gt R1 OFH If working register R1 contains the value 07H 000001 11B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001111B ELECTRONICS 6 21 INSTRUCTION SET S3F84NB_UM_REV1 00 BOR Bit OR BOR BOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 OR src b or dst b lt dst b OR src 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected TOSONO Bytes Cycles Opcode Addr Mode He
160. cles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA rb NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRF SKIP R1 3 gt PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3 tests bit 3 Because it is 0 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET S3F84NB_UM_REV1 00 BTJRT Bit Test Jump Relative on True BTJRT Operation Flags Format Example dst src b If src b is 1 then PC lt PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA rb NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 00000111B th
161. clusive OR ELECTRONICS 6 3 INSTRUCTION SET S3F84NB_UM_REV1 00 Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src Bit XOR TCM dst src Test complement under mask dst src Test under mask 6 4 ELECTRONICS S3F84NB_UM_REV1 00 Mnemonic Rotate and Shift Instructions RL dst RLC dst RR dst RRC dst SRA dst SWAP dst CPU Control Instructions CCF DI El IDLE NOP RCF SB0 SB1 SCF SRP src SRP0 src SRP1 src STOP ELECTRONICS INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Instruction Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles Complement carry flag Disable interrupts Enable interrupts Ente
162. contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location OOOOH The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and stack pointer are the same as in the first example the statement CALL RRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and stack pointer are the same as in the first example if program address 0040H contains 35H and program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET CCF Complement Carry Flag CCF Operation Flags Format Example C NOT C The carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero if C 0 the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex ope 1 4 Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register OD5H changing its valu
163. ctor 4000H FMSECL 00H R9 0AAH Load data AA to write R10 40H Load flash memory upper address into upper register of pair working register R11 10H Load flash memory lower address into lower register of pair working register RR10 R9 Write data AAH at flash memory location 4010H FMUSR 00H User program mode disable PP 00H Case2 Programming in the same sector WR_INSECTOR RR10 gt Address copy R10 high address R11 low address LD RO 40H LD PP 88H LD FMUSR 0A5H User program mode enable LD FMCON 01010000B Selection programming mode and Start programming LD FMSECH 40H Set the base address of sector located in target address to write data LD FMSECL 00H The sector 128 s base address is 4000H LD R9 33H Load data 33H to write LD R10 40H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register WR_BYTE LDC RR10 R9 Write data 33H at flash memory location INC R11 Reset address in the same sector by INC instruction DJNZ RO WR_BYTE Check whether the end address for programming reach 407FH or not LD FMUSR 00H User Program mode disable LD PP 00H ELECTRONICS 19 15 EMBEDDED FLASH MEMORY INTERFACE S3F84NB_UM_REV1 00 Case3 Programming to the flash memory space located in other sectors WR_INSECTOR2 LD RO 40H LD R1 40H LD PP 88H LD FMUSR 0A5H
164. d X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory Please note however that you cannot access locations COH FFH in set 1 using indexed addressing mode In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support indexed addressing mode for internal program memory and for external data memory when implemented Register File RPO or RP1 Value used in a points to Instruction OPERAND start of working register block Program Memory usas Base Address wo Operan dsi src X gt INDEX Instruction Point to One of the Example Woking Register 1 of 8 Sample Instructio
165. d the reset vector selection bit to 0 at the smart option you can choose the reset vector address of CPU as shown in Table 19 3 by setting the ISP reset vector address selection bits Refer to Figure 2 2 Smart Option Table 19 3 Reset Vector Address Smart Option 003EH Reset Vector Usable Area for ISP Sector Size ISP Reset Vector Address Selection Bit Address after POR ISP Sector Bit 7 100H 1FFH 256 Bytes 100H 2FFH 512 Bytes 100H 4FFH 1024 Bytes NOTE The selection of the ISP reset vector address by Smart Option 7 003EH 5 is not dependent of the selection of ISP sector size by Smart Option 003EH 2 003EH 0 ELECTRONICS 19 5 EMBEDDED FLASH MEMORY INTERFACE S3F84NB_UM_REV1 00 FLASH MEMORY CONTROL REGISTERS USER PROGRAM MODE FLASH MEMORY CONTROL REGISTER FMCON FMCON register is available only in user program mode to select the flash memory operation mode sector erase byte programming and to make the flash memory into a hard lock protection Flash Memory Control Register FMCON EFH Page 8 Flash Memory Mode Selection Bits Flash Erase or Hard Lock Protection 0101 Programming mode Operation Start Bit 1010 Erase mode 0 Operation stop 0110 Hard lock mode 1 Operation start others Not used for S3F 84NB This bit will be cleared automatically just after erase operation Not used for S3F84NB Figure 19 3 Flash Memory Control Register FMCON The bit 0 of FMCON
166. ddressing mode addr addr number in the range 127 to 128 that is an offset relative to the address of the next instruction IM Immediate addressing mode data data 0 255 IML Immediate long addressing mode data data range 0 65535 ELECTRONICS 6 9 INSTRUCTION SET S3F84NB_UM_REV1 00 Table 6 5 Opcode Quick Reference OPCODE MAP LOWER NIBBLE HEX DEC DEC ADD ADD ADD ADD ADD BOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb RLC RLC ADC ADC ADC ADC ADC BCP R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b R2 INC INC SUB SUB SUB SUB SUB BXOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb BTJR r2 b RA DA DA OR OR OR OR OR LDB R1 IR1 r1 r2 R2 R1 IR2 R1 R1 IM AND AND AND AND BITC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b COM COM TCM TCM TCM TCM TCM BAND R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM PUSH PUSH BIT R2 IR2 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b DECW DECW PUSHUD PUSHUI MULT MULT MULT LD RR1 IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 r1 x r2 RL RL POPUD POPUI DIV DIV DIV LD R1 IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 r2 x r1 A INCW INCW CP CP CP CP CP LDC RR1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 RAUM 1 12 xL CLR CLR XOR XOR XOR XOR XOR LDC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 Irr2 xL RRC RRC CPIJE LDC LDW LDW LDW LD R1 IR1 Ir r2 RA r1 Irr2 RR2 RR1 IRZ RR1 RR1 IML r1 Ir2 SRA SRA CPIJNE LDC CALL LD LD R1 IR1 Irr r2 RA r2 lrr1 IA1 IR1 IM 1
167. de Hex src src 2 4 31 IM The statement SRP 40H sets register pointer 0 RPO at location OD6H to 40H and register pointer 1 RP1 at location OD7H to 48H The statement SRPO 50H sets RPO to 50H and the statement SRP1 68H sets RP1 to 68H ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET STOP Stop Operation STOP Operation The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 7F The statement STOP halts all microcontroller operations ELECTRONICS 6 81 INSTRUCTION SET S3F84NB_UM_REV1 00 SUB Subtract SUB Operation Flags Format Examples dst src dst lt dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand Set if a borrow occurred cleared otherwise
168. dst b NOT dst b This instruction complements the specified bit within the destination without affecting any other bits in the destination Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected TOSONO Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITC R1 1 gt 05H If working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101B in register R1 Because the result of the complement is not the zero flag Z in the FLAGS register OD5H is cleared ELECTRONICS 6 19 INSTRUCTION SET S3F84NB_UM_REV1 00 BITR Bit Reset BITR Operation Flags Format Example dst b dst b lt 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 O7H BITR R1 1 gt 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1
169. e In these modes 2 and 3 9 data bits are received The 9th bit value is written to RB8 UARTCONO 2 or UARTCON 1 2 The data receive operation is concluded with a stop bit You can program this function so that when the stop bit is received the serial interrupt will be generated only if RB8 1 To enable this feature you set the MCE bit in the UARTCON registers When the MCE bit is 1 serial data frames that are received with the 9th bit 0 do not generate an interrupt In this case the 9th bit simply separates the address from the serial data Sample Protocol for Master Slave Interaction When the master device wants to transmit a block of data to one of several slaves on a serial line it first sends out an address byte to identify the target slave Note that in this case an address byte differs from a data byte In an address byte the 9th bit is 1 and in a data byte it is O The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave then clears its MCE bit and prepares to receive incoming data bytes The MCE bits of slaves that were not addressed remain set and they continue operating normally while ignoring the incoming data bytes While the MCE bit setting has no effect in mode 0 it can be used in mode 1 to check the validity of the stop bit For mode 1 reception if MCE is 1 the receive interrupt will be issue unless a valid stop bit is
170. e data written by R9 at flash memory location INC R11 DJNZ RO WR BYTE RET 19 16 ELECTRONICS S3F84NB_UM_REV1 00 EMBEDDED FLASH MEMORY INTERFACE READING The read operation starts by LDC instruction The program procedure in user program mode 1 Load a flash memory upper address into upper register of pair working register 2 Load a flash memory lower address into lower register of pair working register 3 Load receive data from flash memory location area on LDC instruction by indirectly addressing mode PROGRAMMING TIP Reading LD R2 03H Load flash memory s upper address to upper register of pair working register LD R3 00H Load flash memory s lower address to lower register of pair working register LOOP LDC RO RR2 Read data from flash memory location Between 300H and 3FFH INC R3 CP R3 0FFH JP NZ LOOP ELECTRONICS 19 17 EMBEDDED FLASH MEMORY INTERFACE S3F84NB_UM_REV1 00 HARD LOCK PROTECTION User can set Hard Lock Protection by writing 0110B in FMCON7 4 This function prevents the changes of data in a flash memory area If this function is enabled the user cannot write or erase the data in a flash memory area This protection can be released by the chip erase execution in the tool program mode In terms of user program mode the procedure of setting Hard Lock Protection is following that In tool mode the manufacturer of serial tool writer could support Hardware Protection Please refer t
171. e from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET S3F84NB_UM_REV1 00 CLR Clear CLR dst Operation dst 0 The destination location is cleared to O Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 BO R 1 IR Examples Given Register 4FH register 01H 02H and register 02H CLR 00H gt Register OOH 00H CLR gt Register 01H 02H register 02H OOH In Register R addressing mode the statement CLR OOH clears the destination register OOH value to OOH In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to OOH 6 28 ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET COM Complement COM dst Operation dst NOT dst The contents of the destination location are complemented one s complement all 1s are changed to Os and vice versa Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst Opc dst 2 4 60 R 61 IR Examples Given R1 07H and register 07H OF1H COM R1 gt R1 OF8H COM R1 gt R1 07H register 07H OEH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1
172. e real time and watch time measurement and interval timing for the system clock To start watch timer operation set biti and bit 6 of the watch timer mode register WTCON 1and 6 to 1 After the watch timer starts and elapses a time the watch timer interrupt is automatically set to 1 and interrupt requests commence in 1 955 ms or 0 125 0 25 and 0 5 second intervals The watch timer can generate a steady 0 5 kHz 1 kHz 2 kHz or 4 kHz signal to the BUZZER output BZOUT pin By setting WTCON 3 WTCON 2 to 11b the watch timer will function in high speed mode generating an interrupt every 1 955 ms High speed mode is useful for timing events for program debugging sequences Watch timer has the following functional components e Real time and Watch time measurement e Using a main system or subsystem clock source e Buzzer output frequency generator e Timing tests in high speed mode ELECTRONICS 16 1 WATCH TIMER S3F84NB_UM_REV1 00 WATCH TIMER CONTROL REGISTER WTCON R W WTCONT wrcons WTCONS WTCONA wrcon WTCON2 WTCONA v v v v j v v v Table 16 1 Watch Timer Control Register WTCON Set 1 Bank 1 F5H R W Bit Name Values Function Address WTCON 7 0 Select fx 256 as the watch timer clock fx Main clock F5H Select subsystem clock as watch timer clock WTCON 6 Fd Disable watch timer interrupt Enable watch timer interrupt WTCON 5 4
173. e source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes even for program memory and odd for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory locations 1033H OCDH and 1034H OC5H external data memory locations 1033H ODDH and 1034H OD5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 RR6 1 R8 OCDH R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 RR6 1 R8 ODDH R6 10H R7 34H ELECTRONICS 6 55 INSTRUCTION SET S3F84NB_UM_REV1 00 LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD Operation Flags Format Examples dst src rr rr 1 dst lt src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external
174. e specific peripheral hardware descriptions in Part Il of this manual The locations and read write characteristics of all mapped registers in the S3F84NB register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Registers Register Name Mnemonic Decimal Hex AW FP 24 nw Imempreesngse ma DH R Register page poime om nw ELECTRONICS 4 1 CONTROL REGISTERS S3F84NB_UM_REV1 00 Table 4 2 Set 1 Bank 0 Registers Register Name Mnemonic Decimal Hex R W Port 6 control register High Byte Port 6 control register Low Byte Timer A control register Timer A data register Timer A counter register Port 6 interrupt control register Port 6 interrupt pending register Port 0 control register Port 1 control register High Byte Port 1 control register Low Byte 4 Port 2 control register High Byte 4 2 Port 3 control register High Byte Port 5 control register High Byte Port 5 control register Low Byte Location FCH is factory use only Basic timer counter data register BTCNT 23 FH R Location is not mapped 4 2 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER Table 4 3 Set 1 Bank 1 Registers Register Name Mnemonic Decimal Hex R W Timer 1 0 data register High Byte 230 3 Timer C 1 control register 4
175. e statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET BXOR Bit XOR BXOR BXOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 src b or dst b lt dst b src 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected TOSONO Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 27 Rb ro NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 gt R1 06H register 01H BXOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example destination working register R1 has the value 07H 00000111B and source register 01H has the value 03H 0
176. ect 1 Clear the timer C counter when write NOTE When th counter clear bit 3 is set the 8 bit counter is cleared and it also is cleared automatically Figure 11 7 Timer CO C1 Control Register TCCONO TCCON1 ELECTRONICS S3F84NB_UM_REV1 00 8 BIT TIMER A B C 0 1 BLOCK DIAGRAM TCCON 1 Overflow TCCON 6 4 Data Bus Pending TCCON 7 TCCON 0 3 bit 8 bit Up Counter ce TCCON 3 Pre Read Only scaler TCCON 1 8 bit Comparator TCCON 0 TCCON 2 Timer C Buffer Reg TCOUT TCPWM fxx 1 fxx 64 Timer C Data Register Read Write TCCON 2 Data Bus NOTE When PWM mode match signal cannot clear counter Figure 11 8 Timer C0 C1 Functional Block Diagram ELECTRONICS 11 13 8 BIT TIMER A B C 0 1 S3F84NB_UM_REV1 00 PROGRAMMING TIP Using the Timer ORG 0000h VECTOR INT VECTOR 0C2h TAOV INT ORG 0100h INITIAL LD SYM 00h Disable Global Fast interrupt gt SYM LD IMR 0000001 0b Enable IRQ1 interrupt LD SPH 00000000b Set stack area LD SPL 00000000b LD BTCON 1010001 1b Disable watch dog LD TADATA 80h LD TACON 0100101 0b Match interrupt enable 6 55 ms duration 10 MHz x tal EI MAIN MAIN ROUTINE JR T MAIN TAMC_INT Interrupt service routine IRET TAOV INT Interrupt service routine IRET END 11 14 ELECTRONICS S3F84NB_UM_REV1 00 PROGRAMMING TIP Using the Timer B INITIAL MAIN TBUN_INT ORG 0000h VECTOR OBEh
177. egisters RO R7 Figure 2 6 8 Byte Working Register Areas Slices 2 10 ELECTRONICS S3F84NB_UM_REV1 00 ADDRESS SPACES USING THE REGISTER POINTERS Register pointers RPO and RP1 mapped to addresses D6H and D7H in set 1 are used to select two movable 8 byte working register slices in the register file After a reset RP point to the working register common area RPO points to addresses COH C7H and RP1 points to addresses C8H CFH To change register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction See Figures 2 7 and 2 8 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RPO point to the lower slice and RP1 point to the upper slice see Figure 2 7 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 8 RPO points to the upper slice and RP1 to the lower slice Because a register pointer can point to either of the two 8 byte slices in the working register bloc
178. ember that any alternative peripheral I O function you configure using the port 5 control registers must also be enabled in the associated peripheral module 9 18 ELECTRONICS S3F84NB_UM_REV1 00 PORTS Port 5 Control Register High Byte PSCONH F8H Set 1 Bank 0 R W ell P5 4 P5 5 P5 6 7 6 bit P5 7 P5 7 Input mode Input mode pull up Push pull output Open drain output mode 5 4 bit P5 6 Input mode Input mode pull up Push pull output Open drain ouput mode 3 2 bit P5 5 Input mode Input mode pull up Push pull output Open drain output mode 1 0 P5 4 Input mode Input mode pull up Push pull output Open drain output mode Figure 9 12 Port 5 High Byte Control Register P5CONH ELECTRONICS 9 19 PORTS S3F84NB UM REV1 00 Port 5 Control Register Low Byte PSCONL F9H Set 1 Bank 0 R W sO EEE T5 T2 TT P5 1 TxD1 P5 2 RxD1 P5 3 TxbO RxDO 7 6 bit P5 3 RxDO Input mode RxDO input Input mode pull up RxDO input Push pull output Alternative output mode RxDO output 5 4 bit P5 2 TxDO Input mode Input mode pull up Push pull output Alternative output mode TxDO output 3 2 bit P5 1 RxD1 Input mode RxD1 input Input mode pull up RxD1 input Push pull output Alternative output mode RxD1 output 1 0 bit P5 0 TxD1 Input mode Input mode pull up Push pull output Alternative output mode TxD1 output Figu
179. enerate one Pulse Signal through 11 10 Using the Timer A iiia t rtr E ede ae Sed Eh te E ied E aide dere cR als 11 14 Wsing the bebe vt e aer eti e en cet aids 11 15 Using thie 11 16 Chapter12 16 Bit Timer 1 0 1 Using the Timer 1 0 Uu n ial c nda ane ipea e nuda ad 12 7 Chapter 13 Serial Port Use Internal Clock to Transfer and Receive Serial Data sse 13 6 Chapter 15 Converter Configuring A D Converter nennen L n nn rennen nennen 15 6 Chapter 16 Watch Timer Using the Watch TImier u tte era ata 16 4 Chapter 17 Pattern Generation Module Using the Pattern Generation isst 17 3 Chapter 19 Embedded Flash Memory Interface sty EE 19 10 Programming citis utes en o FUP ae uk MAR LUI DURER AERE RA Ra ee S a Ra ena xa RARE DURER 19 15 E E LAEE 19 17 Hard LOCK nis kuya a oe aec 19 18 S3F84NB_UM_REV1 00 MICROCONTROLLER xvii List of Register Descriptions Register Full Register Name Page Identifier Number ADCON A D Converter Control Regi
180. eneration TB8 0 in the transmit mode The UARTCONO 2 RB8 is also for settings of the even parity checking RB8 0 or the odd parity checking RB8 1 in the receive mode The parity enable generation checking functions are not available in UART mode 0 and 1 If you don t want to use a parity mode UARTCONO 2 RB8 and UARTCONO 3 TB8 are a normal control bit as the 9 data bit in this case PENO UARTO and PEN1 UART1 must be disable 0 in mode 2 and 3 Also it is needed to select the 9th data bit to be transmitted by writing TB8 to 0 or 1 The receive parity error flag RPEO RPE1 will be set to 0 or 1 depending on parity error whenever the 8 data bit of the receive data has been shifted UART DATA REGISTER UDATAO UDATA1 UART Data Register UDATAO E2H Set 1 Bank 1 R W UDATA1 FAH Set 1 Bank 1 R W Transmit or receive data Figure 14 3 UART Data Register UDATAO UDATA1 ELECTRONICS 14 5 UART O 1 S3F84NB_UM_REV1 00 UART BAUD RATE DATA REGISTER BRDATAHO BRDATALO BRDATAH1 BRDATAL1 The value stored in the UARTO baud rate register BRDATAHO BRDATALO lets you determine the UARTO clock rate baud rate The value stored in the UART1 baud rate register BRDATAH1 BRDATAL1 lets you determine the UART1 clock rate baud rate UART Baud Rate Data Register BRDATAHO E4H Set 1 Bank 1 R W BRDATALO E5H Set 1 Bank 1 R W BRDATAH1 00H Page8 R W BRDATAL1 01H Page8 R
181. er 14 4 14 3 UART Data Register UDATAO 1 14 5 14 4 UART Baud Rate Data Register BRDATAHO BRDATALO BRDATAH1 BRDATAL1 14 6 14 5 UART Functional Block Diagram u 14 8 14 6 Timing Diagram for UART Mode 0 14 9 14 7 Timing Diagram for UART Mode 1 Operration 14 10 14 8 Timing Diagram for UART Mode 2 Operration seen 14 12 14 9 Connection Example for Mutiprocessor Serial Data Communications 14 14 53 84 UM REV1 00 MICROCONTROLLER xiii List of Figures Concluded Figure Title Page Number Number 15 1 A D Converter Control Register ADCONJ a 15 2 15 2 A D Converter Data Register ADDATAH ADDATAL 15 3 15 3 A D Converter Circuit Diagram eene nennen nennen 15 3 15 4 A D Converter Timing Diagram ennemis 15 4 15 5 Recommended A D Converter Circuit for Highest Absolute Accuracy 15 5 16 1 Watch Timer Circuit Diagram eee nennen nnne nenas 16 3 17 1 Pattern Generation Flow enne neret nennen nennen 17 1 17 2 PG Control Register PGCONJ
182. er 02H 17H and C 0 RRC 00H gt Register OOH 2AH C 1 RRC 01H gt Register 01H 02H register 02H OBH C 1 In the first example if general register OOH contains the value 55H 01010101B the statement RRC OOH rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010B in destination register 00H The sign flag and overflow flag are both cleared to 0 ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET SBO Select Bank 0 SB0 Operation BANK lt 0 The SBO instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SB0 clears FLAGS 0 to 0 selecting bank 0 register addressing ELECTRONICS 6 75 INSTRUCTION SET S3F84NB_UM_REV1 00 SB1 Select Bank 1 SB1 Operation BANK lt 1 The SB1 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some KS88 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting
183. er stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONICS 6 67 INSTRUCTION SET S3F84NB_UM_REV1 00 PUSHUI Push User Stack Incrementing PUSHUI Operation Flags Format Example dst src IR IR 1 dst lt src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst src 3 8 83 IR R Given Register 00 03 register 01H 05H and register 04H 2 PUSHUI 00H 01H Register 00H 04H register 01H 05H register 04H 05H If the user stack pointer register OOH for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET RCF Reset Carry Flag RCF Operation Flags Format Example 0 The carry flag is cleared to logic zero regardless of its previous value C Cleared to 0 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 CF Given C 1 or 0
184. errupt Enable interrupt P6 4 External Interrupt INT10 Enable Bit Disable interrupt Enable interrupt P6 3 External Interrupt INT9 Enable Bit Disable interrupt Enable interrupt P6 2 External Interrupt INT8 Enable Bit Disable interrupt Enable interrupt Not used for the S3F84NB must keep always 0 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER P6INTPND Port 6 Interrupt Pending Register EEH Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W _ _ Addressing Mode Register addressing mode only 7 P6 7 PND13 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 6 P6 6 PND12 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 5 P6 5 PND11 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 4 P6 4 PND10 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 3 P6 3 PND9 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 2 P6 2 PND8 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 1 0 Not used for the S3F84NB
185. ess D3H and is read write addressable using register addressing mode A reset clears BTCON to 00 This enables the watchdog function and selects a basic timer clock frequency of 15 4096 To disable the watchdog function write the signature code 1010B to the basic timer register control bits BTCON 7 BTCON A The 8 bit basic timer counter BTCNT set 1 bank 0 FDH can be cleared at any time during normal operation by writing a 1 to BTCON 1 To clear the frequency dividers write a 1 to BTCON O ELECTRONICS 10 1 BASIC TIMER S3F84NB_UM_REV1 00 Basic Tlmer Control Register BTCON D3H Set 1 R W Watchdog timer enable bits Divider clear bit for all timers 1010B Disable watchdog function 0 No effect Other value Enable watchdog function 1 Clear divider Basic timer counter clear bit 0 No effect 1 Clear BTCNT Basic timer input clock selection bits 00 fxx 4096 01 fxx 1024 10 fxx 128 11 16 Figure 10 1 Basic Timer Control Register BTCON 10 2 ELECTRONICS S3F84NB_UM_REV1 00 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by setting BTCON 7 BTCON 4 to any value other than 1010B The 1010B value disables the watchdog function A reset clears BTCON to automatically enabling the watchdog timer function A reset also selects the CPU clock as determined by the current CLKCO
186. essable using Register addressing mode A reset clears TACON to This sets timer A to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer A interrupts You can clear the timer A counter at any time during normal operation by writing a 1 to TACON 3 The timer A overflow interrupt TAOVF is interrupt level IRQ1 and has the vector address C2H When a timer A overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware To enable the timer A match capture interrupt IRQ1 vector COH you must write TACON 1 to 1 To generate the exact time interval you should write TACON 3 and 0 to 1 which cleared counter and interrupt pending bit When interrupt service routine is served the pending condition must be cleared by software by writing a 0 to the interrupt pending bit TINTPND O or TINTPND 1 Timer A Control Register TACON EAH Set 1 Bank 0 R W Reset 00H ve e Timer A input clock selection bit Timer A start stop bit 00 fxx 1024 0 Stop timer A 01 fxx 256 1 Start timer A 10 fxx 64 11 External clock TACK Timer A match capture interrupt Timer A operating mode selection bit enable bit 00 Interval mode TAOUT mode 0 Disable interrupt 01 Capture mode capture on rising edge 1 Enable interrrupt counter running OVF can occur 10 Capture mode capture on falling edge
187. ext byte has been completely received the first data byte will be lost Overrun error In all operating modes transmission is started when any instruction usually a write operation uses the UDATAO UDATA 1 register as its destination address In mode 0 serial data reception starts when the receive interrupt pending bit UARTPND 1 UARTPND 3 is 0 and the receive enable bit UARTCONO 4 UARTCON1 4 is 1 In mode 1 2 and 3 reception starts whenever an incoming start bit 0 is received and the receive enable bit UARTCONO 4 UARTCON1 4 is set to 1 PROGRAMMING PROCEDURE To program the UARTO modules follow these basic steps 1 Configure P5 3 and P5 2 to alternative function RxDO P5 3 TxDO P5 2 for UARTO module by setting the P5CONL register to appropriatly value Load an 8 bit value to the UARTCONO control register to properly configure the UARTO I O module For parity generation and check in UARTO mode 2 or 3 set parity enable bit UARTPND 5 to 1 For interrupt generation set the UARTO interrupt enable bit UARTCONO 1 UARTCONO 0 to 1 When you transmit data to the UARTO buffer write transmit data to UDATAO the shift operation starts When the shift operation transmit receive is completed UARTO pending bit UARTPND 1 or UARTPND 0O is set to 1 and an UARTO interrupt request is generated oo Rom ELECTRONICS 14 1 UART O 1 S3F84NB UM REV1 00 UART CONTROL REGISTER UARTCONO UARTCON1 The
188. f these 2 150 registers 16 bytes are for CPU and system control registers 64 bytes are for peripheral control and data registers 16 bytes are used as shared working registers and 2 048 registers are for general purpose use You can always address set 1 register location regardless of which of the 8 register pages is currently selected The set 1 locations however can only be addressed using direct addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the bank selection instructions SBO and SB1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3F84NB Register Type Summary Register Type Number of Bytes General purpose registers including 16 byte common 2 064 working register area the 192 byte prime register area and the 64 byte set 2 area CPU and system control registers 16 Mapped clock peripheral I O control and data registers 64 Mapped peripheral registers page 8 6 Total Addressable Bytes 2 150 ELECTRONICS 2 5 ADDRESS SPACES S3F84NB_UM_REV1 00 Bank 0 System and Peripheral Control Registers Register Addressing Mode Page 0 System and Set 2 Peripheral Control Registers Register Addressing Mode General Purpose Data Registers General Purpose Register Indirect Register Inde
189. fected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 10 R 4 11 IR Given Register OAAH register 01H 02H and register 02H 17H C 0 RLC 00H gt Register 54H C 1 RLC 01 Register 01H 02H register 02H 2EH C 0 In the first example if general register has the value 10101010B the statement RLC 00H rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H leaving the value 55H 01010101B The MSB of register 00H resets the carry flag to 1 and sets the overflow flag ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET RR Rotate Right RR Operation Flags Format Examples dst C dst 0 dst 7 dst 0 dst n lt dst n 1 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 EO
190. fferent applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics objectives Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24653 Al
191. for shift operation Clear 3 bit counter and start shift operation Shift operation transmit enable Mode selection transmit receive or receive only Data direction selection MSB first or LSB first A reset clears the SIOCON value to 00H This configures the corresponding module with an internal clock source P S clock at the SCK selects receive only operating mode the data shift operation and the interrupt are disabled and the data direction is selected to MSB first So if you want to use SIO module you must write appropriate value to SIOCON Serial Module Control Registers SIOCON E1H Set 1 Bank 1 R W SIO Shift clock selection bit 0 Internal clock P S clock 1 External Clock SCK Data direction control bit 0 MSB first mode 1 LSB first mode SIO mode selection bit 0 Receive only mode 1 Transmit receive mode Shift clock edge selection bit 0 Tx at falling edeges Rx at rising edges 1 Tx at rising edeges Rx at falling edges SIO interrupt pending bit 0 No interrupt pending 0 Clear pending condition when write 1 Interrupt is pending SIO interrupt enable bit 0 Disable SIO interrupt 1 Enable SIO interrupt SIO shift operation enable bit 0 Disable shifter and clock counter 1 Enable shifter and clock counter SIO counter clear and shift start bit 0 No action 1 Clear 3 bit counter and start shifting Figure 13 1 Serial I O Module Control Registers SIOC
192. fxt 32 768Hz pending clear ELECTRONICS S3F84NB_UM_REV1 00 PATTERN GENERATION MODULE PATTERN GENERATION MODULE OVERVIEW PATTERN GNERATION FLOW You can output up to 8 bit through P0 0 P0 7 by tracing the following sequence First of all you have to change the PGDATA into what you want to output And then you have to set the PGCON to enable the pattern generation module and select the triggering signal From now bits of PGDATA are on the P0 0 P0 7 whenever the selected triggering signal occurs Write pattern data to PGDATA Triggering signal selection PGCON 3 0 Triggering signal generation Data output through P0 0 P0 7 Figure 17 1 Pattern Generation Flow ELECTRONICS 17 1 PATTERN GENERATION MODULE S3F84NB_UM_REV1 00 Pattern Generation Module Control Register PGCON FEH Set 1 Bank 1 R W Not used PG operation mode selection bit 00 Timer A match signal triggering Bit3 0 No effect 01 Timer B underflow signal triggering 1 Software trigger start 10 Timer 1 0 match signal triggering auto clear bit 1 Software triggering mode Bit2 0 PG operation disable 1 PG operation enable Figure 17 2 PG Control Register PGCON PGDATA Set 1 Bank 1 FFH PG Buffer po7_ L_JLJ 6 5 P0 4 P0 3 P0 2 P0 1 poo JU TULIT Software PGCON 3 Timer A match signal Timer B underflow signal Timer 1 0 match signal PGCON 2 Figure 17 3 Pattern Generation C
193. g Clear pending condition when write 1 Interrupt is pending ELECTRONICS 4 37 CONTROL REGISTERS S3F84NB_UM_REV1 00 SIOPS slo Prescaler Register F4H Set 1 Bank 1 Bit Identifier 7 6 5 4 33 2 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Baud rate Input clock fxx SIOPS 1 x 4 or SCK input clock SPH stack Pointer High Byte D8H Set 1 RESET Value X x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address SP15 SP8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset SPL stack Pointer Low Byte D9H Set 1 RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The low byte stack pointer value is the lower eight bits of the 16 bit stack pointer address SP7 SP0 The upper byte of the stack pointer value is located in register SPH D8H The SP value is undefined following a reset 4 38 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER STPCON Stop Control Register FDH Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W
194. g stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode dst src opc dst src 2 4 42 r r 43 r Ir src dst 3 6 44 R R 45 R IR dst src 3 6 46 R IM Given RO 15H R1 2AH R2 01H register 00H 08H register 01H 37H and register 08H 8AH OR RO R1 gt RO R1 2AH OR RO R2 gt RO 37H R2 01H register 01H 37H OR 00H 01H gt Register OOH register 01H 37H OR 01H 900H gt Register 00H 08H register 01H OBFH OR 00H 402H gt Register OOH OAH In the first example if working register RO contains the value 15H and register R1 the value 2AH the statement OR RO R1 logical ORs the RO and R1 register contents and stores the result in destination register RO The other examples show the use of the logical OR instruction with the various addressing modes and formats ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET POP Pop From Stack POP Operation Flags Format Examples dst dst lt SP lt SP 1 The contents of the location addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one No flags affected Bytes C
195. gh the TxDO P5 2 pin or received through the RxDO P5 3 pin Each data frame has three components e Start bit 0 e 8 data bits LSB first e Stop bit 1 When receiving the stop bit is written to the RB8 bit in the UARTCONO register The baud rate for mode 1 is variable Mode 1 Transmit Procedure 1 Select the baud rate generated by 16bit BRDATA 2 Select mode 1 8 bit UARTO by setting UARTCONO bits 7 and 6 to 01B 3 Write transmission data to the shift register UDATAO E2H set 1 bank 1 The start and stop bits are generated automatically by hardware Mode 1 Receive Procedure 1 Select the baud rate to be generated by 16bit BRDATA 2 Select mode 1 and set the RE Receive Enable bit in the UARTCONO register to 1 3 The start bit low 0 condition at the RxDO P5 3 pin will cause the UARTO module to start the serial data receive operation Tx Clock Write to Shift Register UDATA Stop Bit o c S fL JL L JL JL H fL TL BtDeeeSameTme TTL 1 O TU ITP _ RIP Figure 14 7 Timing Diagram for UART Mode 1 Operation 14 10 ELECTRONICS S3F84NB_UM_REV1 00 UART O 1 UART MODE 2 FUNCTION DESCRIPTION In mode 2 11 bits are transmitted through the TxDO pin or received through the RxDO pin Each data frame has four components e Start bit 0 e 8 data bits LSB first e Programmable 9th dat
196. gure 3 2 Working Register Addressing 3 2 ELECTRONICS S3F84NB_UM_REV1 00 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations COH FFH in set 1 using the Indirect Register addressing mode Program Memory Register File Sbi Register ENSE ADDRESS OPCODE Point to One Register in Register File Instruction Example Address of Operand used by Instruction Value used in OPERAND Instruction Execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES S3F84NB_UM_REV1 00 INDIRECT REGISTER ADDRESSING MODE Continued Register File Program Memory Example REGISTER Instruction dst e References OPCODE Points to Program Register Pair 16 Bit Memory Address Points to Program Memory Program Memory Sample Instructions Value used
197. h Timer Clock Selection Bit 0 Main system clock divided by 256 fxx 256 Sub system clock fxt 6 Watch Timer Interrupt Enable Bit ES Disable watch timer interrupt Enable watch timer interrupt 5 4 Buzzer Signal Selection Bits EXE 0 5 kHz buzzer BUZ signal output EDES 1 kHz buzzer BUZ signal output Pi fo 2 kHz buzzer BUZ signal output 4 kHz buzzer BUZ signal output 3 2 Watch Timer Speed Selection Bits opi pasma lt o Pi o fossmea ooo 1 Watch Timer Enable Bit o Disable watch timer Clear frequency dividing circuits Enable watch timer 0 Watch Timer Interrupt Pending Bit ES Interrupt is not pending Clear pending bit when write Interrupt is pending 4 54 ELECTRONICS S3F84NB_UM_REV1 00 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 series interrupt structure has three basic components levels vectors and sources The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are eight possible interrupt levels IRQ0 IRQ7 also
198. h capture Timer C 1 match overflow Timer C match capture 0 match overflow D Timer A overflow IRQ1 1 Timer A match capture 0 UARTO receive 4 P4 7 external interrupt IRQ6 7 236 4 6 external interrupt 6 234 P4 5 external interrupt 5 232 E8H P4 4 external interrupt 4 230 E6H P4 3 external interrupt 3 228 E4H P4 2 external interrupt 2 226 2 P4 1 external interrupt 1 224 4 0 external interrupt 0 222 P6 7 external interrupt IRQ5 5 220 DCH P6 6 external interrupt 4 218 DAH P6 5 external interrupt 3 216 D8H P6 4 external interrupt 2 214 D6H P6 3 external interrupt 1 212 D4H P6 2 external interrupt 0 210 D2H Watch timer IRQ4 1 208 SIO receive transmit 0 3 2 1 0 1 0 2 2 Timer B undertow _ 2 If two or more interrupts within the same level contend the interrupt with the lowest vector address usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware ELECTRONICS S3F84NB_UM_REV1 00 INTERRUPT STRUCTURE ENABLE DISABLE INTERRUPT INSTRUCTIONS El DI Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always cont
199. he chosen frequency The RESETB pin must be held to Low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal CPU clock oscillation to stabilize The minimum required oscillation stabilization time for a reset is approximately 6 55 ms 2 fosc fosc 10 MHz When a reset occurs during normal operation with both Vpp and RESETB at High level the signal at the RESETB pin is forced Low and the reset operation starts All system and peripheral control registers are then set to their default hardware reset values see Table 8 1 The MCU provides a watchdog timer function in order to ensure graceful recovery from software malfunction If watchdog timer is not refreshed before an end of counter condition overflow is reached the internal reset will be activated The S3F84NB has a built in low voltage reset circuit that allows detection of power voltage drop of external Vpp input level to prevent a MCU from malfunctioning in an unstable MCU power level This voltage detector works for the reset operation of MCU This Low Voltage reset includes an analog comparator and Vref circuit The value of a detection voltage is set internally by hardware The on chip Low Voltage Reset features static reset when supply voltage is below a reference voltage value Typical 3 0 V Thanks to this feature external reset circuit can be removed while keeping the application safety As long as the supply v
200. ically cleared by hardware when it has been serviced A timer 1 0 match capture interrupt T1INTO pending condition is also cleared by hardware when it has been serviced The timer 1 1 module can generate two interrupts the timer 1 1 overflow interrupt T1OVF1 and the timer 1 1 match capture interrupt T1INT1 T1OVF1 is interrupt level IRQ3 vector CEH T1INT1 also belongs to interrupt level IRQ3 but is assigned the separate vector address CCH A timer 1 1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer 1 1 match capture interrupt T1INT1 pending condition is also cleared by hardware when it has been serviced Interval Mode match The timer 1 0 module can generate an interrupt the timer 1 0 match interrupt T1INTO T1INTO belongs to interrupt level IRQ3 and is assigned the separate vector address C8H In interval timer mode a match signal is generated and T1OUTO is toggled when the counter value is identical to the value written to the Timer 1 reference data registers T1DATAHO and T1DATALO The match signal generates a timer 1 0 match interrupt T11NTO vector C8H and clears the counter value The timer 1 1 module can generate an interrupt the timer 1 1 match interrupt T1INT1 T1INT1 belongs to interrupt level IRQ3 and is assigned the separate vector address CCH In interval timer mode a match signal is generated and T1OUTI1 is toggled when the counter value
201. illator Control Bit Main System Oscillator RUN Main System Oscillator STOP 1 Sub System Oscillator Control Bit Sub system oscillator RUN 1 Sub system oscillator STOP Not used for the S3F84NB System Clock Selection Bit Main oscillator select 1 Subsystem oscillator select ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER POCON Port 0 Control Register EFH Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P0 7 P0 6 P0 5 P0 4 Ears Push pull output Alternative function mode PGOUT lt 7 4 gt 5 4 P0 3 P0 2 fo 0 mpamede Fo r mumuepdw Pi fo Push pullout _ 3 2 P0 1 0 o iromo po o ooo a oferon _ 1 0 P0 0 oofa K EJ Push pull output Alternative function mode PGOUT lt 0 gt ELECTRONICS 4 17 CONTROL REGISTERS S3F84NB_UM_REV1 00 P1CONH Port 1 Control Register High Byte FOH Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 7 ADC7 Configration Bits fo i SSS 5 4 P1 6 ADC6 Configration Bits o o mumum Fo r mummepdu _ _ Push pullout 3 2 P1 5 ADC5 Configrati
202. imer C 1 Control Register F3H Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Timer 1 Start Stop Bit nm Stop Timer C 1 Start Timer C 1 6 4 Timer C 1 3 bits Prescaler Bits Fo r r meya r o o ps afo ps 1 1 0 Divided by 7 3 Ti 3 er C 1 Counter Clear Bit No effect Clear the timer C 1 counter Auto clear bit 1 2 Timer C 1 Mode Selection Bit fxx 1 amp PWM mode fxx 64 amp interval mode 1 1 Timer C 1 Interrupt Enable Bit Disable interrupt Enable interrupt 0 Timer C 1 Pending Bit No interrupt pending EU Clear pending bit when write Interrupt pending 4 46 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER TINTPND Timer A Timer 1 Interrupt Pending Register E7H Set 1 Bank 0 Bit Identifier 7 6 5 A 3 2 0 RESET Value _ _ 0 0 0 0 0 0 Read Write _ _ R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for the S3F84NB 5 Timer 1 1 Overflow Interrupt Pending Bit EN No interrupt pending ES Clear pending bit when write Interrupt pending 4 Timer 1 1 Match Capture Interrupt Pending Bit ES No interrupt pending E Clear pending bit when write Interrupt pending 3 Timer 1 0 Overflow Interrupt Pending Bit ES No interrupt pending Clear pending bit when write
203. in OPERAND CALL RR2 Instruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS S3F84NB_UM_REV1 00 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File MSB Points to RPO or RP1 RPO or RP1 Selected RP points Program Memory to start fo m working register 4 bit block o Register dm Address ORCODE Working Register ADDRESS T Go 22051 Value used in OPERAND ae te We C Sample Instruction Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES S3F84NB_UM_REV1 00 INDIRECT REGISTER ADDRESSING MODE Continued Register File MSB Points to RPO or RP1 RPO or RP1 Selected RP points to start of working register oe ee Program Memory 4 bit Working Register Address 0 Register Next 2 bit Point Pair ko c E References either Register Pair Program Memory or 1 of 4 Data Memory 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data memory Value used in Instruction OPERAND Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS S3F84NB_UM_REV1 00 ADDRESSING MODES INDEXED ADDRESSING MODE X Indexe
204. interrupt service routine has been initiated The application program detects interrupt requests by polling the P6INTPND register at regular intervals When the interrupt enable bit of any port 6 pin is 1 a rising or falling signal edge at that pin will generate an interrupt request The corresponding PeINTPND bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must clear the pending condition by writing a 0 to the corresponding P6INTPND bit Subsystem Oscillator Input XTin Output XTout The reset value of PECONL register is OFH so that P6 0 and P6 1 pins are set to the subsystem oscillation mode after CPU Reset This allows fast oscillation starting If you don t use subsystem oscillation mode in your applications it is recommended to set these pins as Push up output mode for protecting current leakage ELECTRONICS 9 21 PORTS S3F84NB UM REV1 00 Port 6 Control Register High Byte PECONH E8H Set 1 Bank 0 R W 5 5 6 7 6 6 6 5 6 4 INT13 INT12 INT11 INT10 7 6 P6 7 INT13 Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output 5 4 bit P6 6 INT12 00 01 10 11 Input mode falling edge interrupt Input mode risi
205. ion in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address e The high order bit of the 4 bit address selects one of the register pointers 0 selects RPO 1 selects RP1 e The five high order bits in the register pointer select an 8 byte slice of the register space e The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 12 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 13 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC R6 is 0 which selects RPO The five high order bits stored in RPO 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B 2 16 ELECTRONICS S3F84NB_UM_REV1 00 ADDRESS SPACES Selects RPO or RP1 Address OPCODE Kusma 4 bit address Register pointer provides three provides five low order bits high order bits Together they create an 8 bit register address Figure 2 12 4 Bit Working Register
206. ion with various addressing modes and formats ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET MULT Multiply Unsigned MULT dst src Operation dst lt dst src The 8 bit destination operand even register of the register pair is multiplied by the source operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers Flags C Set if result is gt 255 cleared otherwise Z Set if the result is 0 cleared otherwise S Set if MSB of the result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Examples Given Register 00H 20H register 01H 03H register 02H 09H register O3H 06H MULT 00H 02H gt Register 00H 01H register 01H 20H register 02H 09H MULT 00H 01H gt Register OOH OOH register 01H OCOH MULT 00H 30H gt Register OOH 06H register 01H OOH In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register 00H of the register pair 00H 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair 00H 01H ELECTRONICS 6 59 INSTRUCTION SET S3F84NB_UM_REV1 00 NEXT Next NEXT Operation lt IP IP P 2 The NEXT instruction is useful when imp
207. iptions in Part Il If you are not yet familiar with the S3F8 series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6 Later you can reference the information in Part as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the S3F84NB microcontroller Also included in Part Il are electrical mechanical data It has 16 chapters Chapter 7 Clock Circuit Chapter 15 A D Converter Chapter 8 RESET and Power Down Chapter 16 Watch Timer Chapter 9 I O Ports Chapter 17 Pattern Generation Module Chapter 10 Basic Timer Chapter 18 Low Voltage Reset Chapter 11 8 Bit Timer A B C 0 1 Chapter 19 Embedded Flash Memory Interface Chapter 12 16 Bit Timer1 0 1 Chapter 20 Electrical Data Chapter 13 Serial I O Port Chapter 21 Mechanical Data Chapter 14 UART 0 1 Chapter 22 Development Tools S3F84NB_UM_REV1 00 MICROCONTROLLER iii Table of Contents Part Programming Model Chapter 1 Product Overview S3F8 Series Microcontrollers S3F84NB Microcontroller Features Block Diagram Pin Assignment Pin Descriptions Chapter 2 Address Spaces Register Architecture ees i e geste ce e teh Le
208. ircuit Diagram 17 2 ELECTRONICS S3F84NB_UM_REV1 00 PATTERN GENERATION MODULE Programming Tip Using the Pattern Generation ORG 0000h ORG 0100h INITIAL SB0 LD SYM 00h Disable Global Fast interrupt SYM LD IMR 01h Enable IRQO interrupt LD SPH High byte of stack pointer gt SPH LD SPL 0FFh Low byte of stack pointer gt SPL LD BTCON 10100011b Disable Watch dog LD CLKCON 00011000b Non divided fxx LD POCON 11111111b Enable PG output mode El MAIN NOP NOP SB1 LD PGDATA 10101010b PG data setting OR PGCON 000001006 Triggering by Timer A match then pattern data are output SBO NOP NOP JR T MAIN END ELECTRONICS 17 3 S3F84NB_UM_REV1 00 LOW VOLTAGE RESET LOW VOLTAGE RESET OVERVIEW By smart option 3FH 7 in ROM user can select internal RESET LVR or external RESET The S3F84NB can be reset in four ways e external power on reset bythe external reset input pin pulled low e by the digital watchdog timing out e by the Low Voltage reset circuit LVR During an external power on reset the voltage Vpp is High level and the RESETB pin is forced Low level The RESETB signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This brings the S3F84NB into a known operating status To ensure correct start up the user should take that reset signal is not released before the Vpp level is sufficient to allow MCU operation at t
209. is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 73 r Ir src dst 3 6 74 R R 75 R IR opc dst src 3 6 76 R IM Given RO 0C7H R1 02H R2 18H register 2BH register 01H 02H and register 02H 23H TM RO R1 gt RO OC7H R1 02H 2 0 RO R1 gt RO OC7H R1 02H register 02H 23H Z 0 00H 01H gt Register OOH 2BH register 01H 02H Z 0 00H 01H Register 2BH register 01H 02H register 02H 23H Z 0 00H 54H gt Register 00H 2BH Z 1 In the first example if working register R0 contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TM RO R1 tests bit one in the destination register for a 0 value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 85 INSTRUCTION SET S3F84NB_UM_REV1 00 Wait For Interrupt WFI Operation Flags Format Example The CPU is effectively halted until an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including a fast interrupt No flags are affected Bytes Cycles Opcode Hex n 1 2 3
210. is identical to the value written to the Timer 1 reference data register TIDATAH1 and T1DATAL1 The match signal generates a timer 1 1 match interrupt T1INT1 vector CCH and clears the counter value Capture Mode In capture mode for timer 1 0 a signal edge that is detected at the T1CAPO pin opens a gate and loads the current counter value into the timer 1 data registers T1DATAHO T1DATALO for rising edge or falling edge You can select rising or falling edge to trigger this operation The timer 1 0 also gives you capture input source the signal edge at the T1CAPO pin You select the capture input by setting the value of the timer 1 0 capture input selection bit in the port 3 control register low PSCONL set 1 bank 0 F5H Both kinds of timer 1 0 interrupts T1OVFO T1INTO can be used in capture mode the timer 1 0 overflow interrupt is generated whenever a counter overflow occurs the timer 1 0 capture interrupt is generated whenever the counter value is loaded into the timer 1 data register By reading the captured data value in T1I DATAHO T1DATALO and assuming a specific value for the timer 1 0 clock frequency you can calculate the pulse width duration of the signal that is being input at the T1CAPO pin In capture mode for Timer 1 1 a signal edge that is detected at the T1CAP1 pin opens a gate and loads the current counter value into the timer 1 data register T1DATAH1 T1DATAL1 for rising edge or falling edge You can
211. it Complete SET SIOCON 3 Figure 13 5 SIO Timing in Transmit Receive Mode Tx at rising edge SIOCON 4 1 ELECTRONICS 13 5 SERIAL I O PORT S3F84NB_UM_REV1 00 Transmit Complete SET SIOCON 3 Figure 13 6 SIO Timing in Receive Only Mode Rising edge start PROGRAMMING Use Internal Clock to Transfer and Receive Serial Data 1 The method that uses interrupt is used DI LD P2CONL 03H SB1 LD SIODATA TDATA LD SIOPS 90H LD SIOCON 2EH SB0 El SIOINT PUSH RP0 SRP0 RDATA SB1 LD R0 SIODATA OR SIOCON 08H AND SIOCON 11111110b SB0 POP RP0 IRET Disable All interrupts 2 2 2 0 are selected to alternative function for 51 SO SCK respectively Load Tx data to SIO buffer Baud rate input clock fxx 144 1 x 4 Internal clock MSB first transmit receive mode Select falling edges to start shift operation Clear 3 bit counter and start shifting Enable shifter and clock counter Enable SIO interrupt and clear pending Load received data to general register SIO restart Clear interrupt pending bit ELECTRONICS S3F84NB_UM_REV1 00 SERIAL I O PORT X PROGRAMMING Use Internal Clock to Transfer and Receive Serial Data Continued 2 The method that uses software pending check is used DI Disable All interrupts SB1 LD SUSR 4 00H Select SIO interface module LD SIODATA TDATA Load Tx data to SIO buffer LD SIOPS 90 Baud rate input clock fxx 144
212. k you can flexibly define the working register area to support program requirements PROGRAMMING TIP Setting the Register Pointers SRP 70H RPO 70H RP1 lt 78H SRP1 48H RPO lt nochange RP1 lt 48H SRPO 0A0H RPO OAOH RP1 lt nochange CLR RPO RPO lt OOH RP1 lt nochange LD RP1 0F8H RPO lt nochange RP1 OF8H Register File Contains 32 8 Byte Slices 00001X XxX La 8 Byte Slice 16 Byte Contiguous Working 00000XXX 8 Byte Slice Register block Figure 2 7 Contiguous 16 Byte Working Register Block ELECTRONICS 2 11 ADDRESS SPACES S3F84NB_UM_REV1 00 8 Byte Slice Register File Contains 32 8 Byte Slices 16 byte Non contiguous working register block 11110XXX RPO 00000XXX Figure 2 8 Non Contiguous 16 Byte Working Register Block PROGRAMMING TIP Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses from 80H through 85H contain the values 10H 11H 12H 13H 14H and 15 H respectively SRPO 80H RPO lt 80H ADD RO R1 RO lt RO R1 ADC RO R2 RO lt RO R2 C ADC RO R3 RO lt RO R3 C ADC RO R4 RO lt RO R4 C ADC RO R5 RO lt RO R5 C The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the registe
213. l semiconductor products are designed and manufactured in accordance with the highest quality standards and Samsung Electronics Co Ltd San 24 Nongseo Dong Giheung Gu Yongin City Gyeonggi Do Korea C P O Box 37 Suwon 446 711 TEL 82 31 209 5238 FAX 82 31 209 6494 Home Page URL Http Wwww samsungsemi com Printed in the Republic of Korea NOTIFICATION OF REVISIONS ORIGINATOR Samsung Electronics LSI Development Group Gi Heung South Korea PRODUCT NAME S3F84NB 8 bit CMOS Microcontroller DOCUMENT NAME S3F84NB User s Manual Revision 1 00 DOCUMENT NUMBER 21 S3 F84NB 122007 EFFECTIVE DATE December 2007 DIRECTIONS Revision 1 00 REVISION HISTORY Preliminary Spec for internal release only Lo Ebo 1 Aug 2006 REVISION DESCRIPTIONS FOR REVISION 1 00 Subjects Major changes comparing with last version Chapter Name m 01 Product Overview Operating Voltage Range is changed form 2 0 V to 5 5 V at 10MHz 1 fosc LVR disabled to 2 0 V to 5 5 V 9 1 4MHz LVR disabled and 3 0 to 5 5 V 1 10MHz Figure 2 2 Smart Option LVR level is changed from 3 9V to 4 0V when LVR Level Selection Bits is set to 01 Modified default LVR state from enable to disable 02 Address Space E 2 Added sentence However if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register du
214. lementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex ope 1 10 OF Example The following diagram shows one example of how to use the NEXT instruction Before After Address Data Address Data PC 0120 43 Address 0130 44 Address L Address Data 43 Address H 44 Address L 45 Address Address Data 45 Address H 130 Routine 120 Memory Memory ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET NOP No Operation NOP Operation Flags Format Example No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration No flags are affected Bytes Cycles Opcode Hex ope 1 4 FF When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ELECTRONICS 6 61 INSTRUCTION SET S3F84NB_UM_REV1 00 OR Logical OR OR Operation Flags Format Examples dst src dst lt dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 bein
215. ll peripherals timers remain active Port pins retain the mode input or output they had at the time idle mode was entered There are two ways to release idle mode 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to 00B If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the CLKCON 4 and CLKCON 3 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt IRET occurs the instruction immediately following the one that initiated idle mode is executed ELECTRONICS 8 7 S3F84NB_UM_REV1 00 PORTS I O PORTS OVERVIEW The S3F84NB microcontroller has seven bit programmable I O ports PO P6 This gives a total of 56 I O pins Each port can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special I O instructions are required Table 9 1 gives you a general overview of the S3F84NB I O port functions Table 9 1 S3F84NB Port Configuration Overview Configuration Options Bit programmable port input or output mode selected by software in
216. lower four bits and upper four bits of the destination operand are swapped C Undefined Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 FO R 1 IR Given Register register 02H and register OA4H SWAP 00H gt Register OOH OE3H SWAP 02H gt Register 02H register 4AH In the first example if general register contains the value 00111110B the statement SWAP 00H swaps the lower and upper four bits nibbles in the OOH register leaving the value OE3H 11100011B ELECTRONICS 6 83 INSTRUCTION SET S3F84NB_UM_REV1 00 TCM Test Complement Under Mask TCM Operation Flags Format Examples 6 84 dst src NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected
217. lue 05H which is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates C 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in working register R3 6 30 ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET CPIJE Compare Increment and Jump on Equal CPIJE Operation Flags Format Example dst src RA If dst src 0 lt PC RA Ir lt Ir 1 The source operand is compared to subtracted from the destination operand If the result is O the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 3 12 C2 ro dr NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 and register 03H 02H CPIJE R1 R2 SKIP gt R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 0000001 0B to 02H 00000010B Because the result of the comparison is equ
218. med by Serial OTP MTP Tools SPW2 plus single programmer or GW PRO2 gang programmer and so on The other modules except flash memory module are at a reset state This mode doesn t support the sector erase but chip erase all flash memory erased at a time and two protection modes Hard lock protection Read protection The read protection mode is available only in tool program mode So in order to make a chip into read protection you need to select a read protection option when you write a program code to a chip in tool program mode by using a programming tool After read protect all data of flash memory read 00 This protection is released by chip erase execution in the tool program mode Table 19 1 Descriptions of Pins Used to Read Write the Flash in Tool Program Mode Normal Chip During Programming PinName PinName Pinno vo Function P5 6 SDAT 14 7 Serial data pin Output port when reading input port when writing SDAT P5 6 can be assigned as an input or push pull output port SCLK 15 8 Serial clock pin Input only pin TEST TEST 20 13 Tool mode selection when TEST pin sets Logic value 1 If user uses the flash writer tool mode ex spw2 etc user should connect TEST pin to S3F84NB supplies high voltage 12 5V by internal high voltage generation circuit nRESET nRESET 23 16 Chip Initialization Vpp Vss Vpp Vss 16 9 17 10 Power supply pin for logic circuit Vpp
219. must keep always 0 ELECTRONICS 4 3 CONTROL REGISTERS S3F84NB_UM_REV1 00 PGCON Pattern Generation Control Register FEH Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value _ _ _ _ 0 0 0 0 Read Write _ _ _ _ R W R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for the S3F84NB 3 Software Trigger Start Bit EN No effect Software trigger start will be automatically clear 2 PG Operation Disable Enable Selection Bit PG operation disable 1 PG operation enable 1 0 PG Operation Trigger Mode Selection Bits Timer A match siganal triggering EJES Timer B underflow siganal triggering KEE Timer 1 0 match siganal triggering Software triggering mode 4 34 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER PP Register Page Pointer DFH Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Destination Register Page Selection Bits o 0 0 bestnaion pageo o ofo 1 0 bestnaion page2 of o 1 Fo o o o o o bestnaion Dee Other values Don t care 3 0 Source Register Page Selection Bits roo 0
220. n LD RO BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES S3F84NB_UM_REV1 00 INDEXED ADDRESSING MODE Continued 3 8 Register File MSB Points to RPO or RP1 gt RPO or 1 Selected RP points to start of ki Program Memory Pace OFFSET i NEXT 2 Bits 4 bit Working dst src Register Register Address OPCODE Point to Working Pair block p nM 16 Bit address added to p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in 16 Bits Instruction LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed Sample Instructions Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset ELECTRONICS S3F84NB_UM_REV1 00 INDEXED ADDRESSING MODE Continued Register File RPO or RP1 MSB Points to RPO or RP1 Program Memory 4 bit Working NEXT 2 Bits Register Address Register Pair o aa el P Register Point to Working Pair p Program Memory LSB Selects or Data Memory 16 Bits 16 Bits OPERAND 16 Bits Sample Instructions LDC R4 1000H RR2 are loaded into register R4 LDE R4 1000H RR2 ADDRESSING MODES Selected RP points to start of working register block 16 Bit
221. n 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as one that consists of 32 8 byte register groups or slices Each slice comprises of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any one time to form a 16 byte working register block Using the register pointers you can move this 16 byte register block anywhere in the addressable register file except for the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces e working register slice is 8 bytes eight 8 bit working registers RO R7 R8 R15 e One working register block is 16 bytes sixteen 8 bit working registers RO R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file other than set 2 The base addresses for the two selected 8 byte register slices are contained in register pointers RPO and RP1 After a reset RPO and RP1 always point to the 16 byte common area in set 1 COH CFH Slice 32 11111XXX Slice 31 RP1 Registers R8 R15 Each register pointer points to one 8 byte slice of the register I space selecting a total 16 byte working register block 00000XXX RPO R
222. n Bits Lo e Elapsed time for low data value fo 1 Elapsed time for high data value Elapsed time for low and high data values Not Used Timer B Interrupt Enable Bit K Disable Interrupt 1 Enable Interrupt Timer B Start Stop Bit K Stop timer B Start timer B Timer B Mode Selection Bit EN One shot mode Repeating mode Timer B Output flip flop Control Bit T FF is low T FF is high 1 fxx is selected clock for system ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER TCCONO Timer C 0 Control Register F2H Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Timer 0 Start Stop nm Stop Timer C 0 Start Timer C 0 6 4 Timer C 0 3 bits Prescaler Bits roo 0 Nondeveed ofo omes Fo r r peya 1 1 0 1 Divided by6 F 1 O Divided by 7 1 Divided by 8 3 Ti 3 er C 0 Counter Clear Bit No effect 1 Clear the timer C 0 counter Auto clear bit 2 Timer C 0 Mode Selection Bit 0 fxx 1 amp PWM mode fxx 64 amp interval mode 1 Timer C 0 Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer 0 Pending Bit No interrupt pending ES Clear pending bit when write Interrupt pending ELECTRONICS 4 45 CONTROL REGISTERS S3F84NB_UM_REV1 00 TCCON T
223. n chip main oscillator stops and the supply current is reduced to less than 3 except for the current consumption of LVR Low voltage Reset circuit All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset or by interrupts NOTE Do not use stop mode if you are using an external clock source because Xy input must be restricted internally to to reduce current leakage Using RESET to Release Stop Mode Stop mode is released when the RESET signal is released and returns to high level all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained A reset operation automatically selects a slow clock 1 16 because CLKCON 3 and CLKCON 4 are cleared to 00B After the programmed oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H and 0101H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the S3F84NB interrupt structure that can be used to release Stop mode are e External interrupts P4 0 P4 7 I
224. n write any value in the not used addresses 003CH and 003DH The default value of smart option bits in program memory is OFFH LVR disable Normal reset vector address 100H ISP protection disable Before execution the program memory code user can set the smart option bits according to the hardware option for user to want to select ROM Address 003CH MSB LSB Not used ROM Address 003DH Not used ROM Address 003EH LSB ISP Reset Vector Change Selection Bit 9 Not used ISP Protection Size Selection Bits 0 OBP Reset vector address 00 256 bytes 01 512 byt 1 Normal vector address 100H 10 1024 11 2048 bytes ISP Reset Vector Address Selection Bits 00 200H ISP Area size 256 bytes 01 300H ISP Area size 512 bytes 10 500H ISP Area size 1024 bytes 11 900H ISP Area size 2048 bytes ISP Protection Enable Disable Bit 9 0 Enable Not erasable 1 Disable Erasable ROM Address 003FH MSB LSB Not used LVR Level Selection Bits 01 4 0V 10 2 2V 11 3 0V LVR Control Bit 1 LVR disable 0 LVR enable Figure 2 2 Smart Option ELECTRONICS 2 3 2 4 ADDRESS SPACES S3F84NB_UM_REV1 00 NOTES By setting ISP Reset Vector Change Selection Bit 7 to 0 user can have the available ISP area If ISP Reset Vector Change Selection Bit 3EH 7 is 1 3EH 6 and 3EH 5 are meaningless If ISP Reset Vector Change Selection
225. nal is generated and TAOUT is toggled when the counter value is identical to the value written to the timer A reference data register TADATA The match signal generates a timer A match interrupt TAINT vector COH and clears the counter If for example you write the value 10H to TADATA and to TACON the counter will increment until it reaches 10H At this point the Timer A interrupt request is generated the counter value is reset and counting resumes Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TAOUT pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the Timer A data register TADATA In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at and then continues incrementing from OOH Although you can use the match signal to generate a timer A overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TAOUT pin is held to Low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to tc 256 Capture Mode In capture mode a signal edge that is detected at the TACAP pin opens a gate and loads the
226. nctional components e Clock frequency divider fxx divided by 1024 256 or 64 with multiplexer e External clock input pin TACK e 8 bit counter TACNT 8 bit comparator and 8 bit reference data register e pins for capture input TACAP PWM or match output TAOUT e Timer A overflow interrupt IRQ1 vector C2H and match capture interrupt IRQ1 vector COH generation e Timer A control register TACON set 1 bank0 EAH read write ELECTRONICS 11 1 8 BIT TIMER A B C 0 1 S3F84NB_UM_REV1 00 FUNCTION DESCRIPTION Timer A Interrupts IRQ1 Vectors COH and C2H The timer A module can generate two interrupts the timer A overflow interrupt TAOVF and the timer A match capture interrupt TAINT TAOVF is interrupt level IRQ1 vector C2H TAINT also belongs to interrupt level IRQ1 but is assigned the separate vector address COH A timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer A match capture interrupt TAINT pending condition is also cleared by hardware when it has been serviced Interval Timer Function The timer A module can generate an interrupt the timer A match interrupt TAINT TAINT belongs to interrupt level IRQ1 and is assigned the separate vector address COH When the timer A match interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware In interval timer mode a match sig
227. nder are incorrect Both operands are treated as unsigned integers Flags C Setifthe V flag is set and quotient is between 28 and 29 1 cleared otherwise Z Set if divisor or quotient 0 cleared otherwise S Setif MSB of quotient 1 cleared otherwise V Set if quotient is gt 28 or if divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given RO 10H R1 O3H R2 40H register 40H 80H DIV RRO R2 gt RO R1 40H DIV RRO R2 gt RO R1 20H DIV RRO 20H gt RO 03H R1 80H In the first example destination working register pair RRO contains the values 10H RO and 03H R1 and register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 6 38 ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET DJNZ Decrement and Jump if Non Zero DJNZ Operation Flags Format Example r dst r r 1 If r z 0 PC dst The working register being used as a counter
228. neeseaeeesaeeeeaeeeenees 11 6 Timer B Pluse Width Calculation U U 11 7 8 bit Timer 0 1 ia ta i a uh eed a 11 11 I II HET EE 11 11 Timer C 0 1 Control Register TCCON0 TCCON1 L L 11 12 Block Magra rS 11 13 Chapter 12 16 Bit Timer 1 0 1 OVSIVIOW ite erae pa it RU enu fot i dede s fed uide eroe UU ee fed feu uten 12 1 Function Description C 12 2 Timer 1 0 1 Control Register T1CON0 T1CON101 a 12 3 Block Diagrami avandia ay Ane canine ail Av eg Gil ane Ay a ee aed 12 6 Chapter 13 Serial I O Port hu EET el ae 13 1 Programming Procedure a iva e eod tee n ee Ee ER I HO 13 1 SIO Control Register SIOGQON eoi tiat E REEL EDRRULU HERR EDRRRRMLU TIERE 13 2 SIO Pre Scaler Register SIOPS ssssssssssssssssssseseee nennen tnn niter ennt entren 13 3 Block Diagram ida tat a end Tre e dp eee dtd 13 4 Serial Timing Diagra risi un u y s a S nmmn a entes etna ss nns siste nent 13 5 viii S3F84NB UM REV1 00 MICROCONTROLLER Table of Contents Concluded Chapter 14 UART 0 1 i i D 14 1 Programming PIOCGGUre L ut eerta beth ae wa Da M ec Sa says La ene 14 1 UART Control Registers UARTCON0 UARTCON11 n S S 14 2 UART Interrupt Pending Register UARTPEND U u 14 4 UART Data R gister
229. ng edge interrupt Input mode pull up falling edge interrupt Push pull output 3 2 bit P6 5 INT11 00 01 10 11 Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output 1 0 bit P6 4 INT10 00 01 10 11 Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output Figure 9 14 Port 6 High Byte Control Register PECONH ELECTRONICS S3F84NB_UM_REV1 00 PORTS Port 6 Control Register Low Byte E9H Set1 Bank 0 R W sO T2 e P6 3 P6 2 P6 1 P6 0 INT9 INT8 XTout XTin 7 6 bit P6 3 INT9 Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output 5 4 bit P6 2 INT8 Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output 2 bit P6 1 XTout Input mode Input mode pull up Push pull output Alternative function Sub Clock Oscillator Output XTout 0 bit P6 0 XTin Input mode Input mode pull up Push pull output Alternative function Sub Clock Oscillator Input XTin Figure 9 15 Port 6 Low Byte Control Register P6CONL ELECTRONICS 9 23 PORTS S3F84NB UM REV1 00 Port 6 Interrupt Control Register P6INT EDH Set 1 Bank 0 R W
230. ng modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are e Register R e Indirect Register IR e Indexed X e Direct Address DA e Indirect Address 1 e Relative Address RA e Immediate IM ELECTRONICS 3 1 ADDRESSING MODES S3F84NB_UM_REV1 00 REGISTER ADDRESSING MODE R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 Program Memory Register File g bit Register J o ae OPERAND S CODE Register in Register One Operand File Instruction Example Value used in Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Point to RPO ot RP1 RPOorRP1 Selected RP points to start of working register Program Memory 4 bit Point to the OPCODE Working Register Two Operand Instruction Example Working Register dst block OPERAND Sample Instruction ADD R1 R2 Where R1 and R2 are registers in the currently selected working register area Fi
231. nterrupts are triggered by a rising or falling edge depending on the corresponding control register setting Figure 5 2 S3F84NB Interrupt Structure 5 4 ELECTRONICS S3F84NB_UM_REV1 00 INTERRUPT STRUCTURE INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3F84NB interrupt structure are stored in the vector address area of the internal 64 Kbyte flash memory OH FFFFH see Figure 5 3 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the flash memory is 0100H Decimal 65 535 64 Kbyte Memory Area 0100H RESET Address FFH Interrupt Vector Area Figure 5 3 ROM Vector Address Area ELECTRONICS 5 5 INTERRUPT STRUCTURE Vector Address Decimal Hex Value Value 100H Basic timer WDT overflow 246 244 242 240 238 Table 5 1 Interrupt Vectors Interrupt Priority in HW s w Level Level Dee T3 Interrupt Source UART1 transmit UART1 receive UARTO transmit S3F84NB UM REV1 00 206 204 202 200 198 194 NOTES 1 Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so on CEH CCH CAH C8H C6H C4H C2H COH BEH Timer 1 1 overflow Timer 1 1 1 Timer 1 0 overflow 0 Timer 1 0 matc
232. nversion is completed ADCON 3 the end of conversion EOC bit is automatically set to 1 and the result is dumped into the ADDATAH ADDATAL registers where it can be read The ADC module enters an idle state Remember to read the contents of ADDATAH and ADDATAL before another conversion starts Otherwise the previous result will be overwritten by the next conversion result NOTE Because the ADC does not use sample and hold circuitry it is important that any fluctuations in the analog level at the ADCO ADCT7 input pins during a conversion procedure be kept to an absolute minimum Any change in the input level perhaps due to circuit noise will invalidate the result ELECTRONICS 15 1 A D CONVERTER S3F84NB_UM_REV1 00 A D CONVERTER CONTROL REGISTER ADCON The A D converter control register ADCON is located in set1 bank 1 at address F7H ADCON is read write addressable using 8 bit instructions only But the EOC bit ADCON 3 is read only ADCON has four functions e Bits 6 4 select an analog input pin ADCO ADC7 e Bit 3 indicates the end of conversion status of the A D conversion e Bits 2 1 select a conversion speed e BitO starts the A D conversion Only one analog input channel can be selected at a time You can dynamically select any one of the eight analog input pins ADCO ADC7 by manipulating the 3 bit value for ADCON 6 ADCON 4 A D Converter Control Register ADCON F7H Set 1 Bank 1 R W ADCON 3 bit is read only Keep
233. o the manual of serial program writer tool provided by the manufacturer The program procedure in user program mode 1 Set Flash Memory User Programming Enable Register FMUSR 10100101B 2 Set Flash Memory Control Register FMCON 01 100001 3 Set Flash Memory User Programming Enable Register FMUSR to 00000000B PROGRAMMING Hard Lock Protection LD 88 LD FMUSR 0A5H User program mode enable LD FMCON 01100001B Select Hard Lock Mode and Start protection LD FMUSR 00H User program mode disable LD PP 00H 19 18 ELECTRONICS S3F84NB_UM_REV1 00 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter SSF84NB electrical characteristics are presented in tables and graphs The information is arranged in the following order e Absolute maximum ratings e Input output capacitance e D C electrical characteristics e A C electrical characteristics e Oscillation characteristics e Oscillation stabilization time e Data retention supply voltage in stop mode e Serial l O timing characteristics e UART timing characteristics in mode 0 e A D converter electrical characteristics e LVR Circuit Characteristics e Electrical Characteristics for Internal Flash ROM ELECTRONICS 20 1 ELECTRICAL DATA S3F84NB_UM_REV1 00 Table 20 1 Absolute Maximum Ratings TA 25 Parameter Symbot Conditions Uni e nes Durs Vo
234. og Timer Function Disable Code for System Reset Disable watchdog timer function Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Bits fxx 4096 9 fxx 1024 fxx 128 Basic Timer Counter Clear Bit 1 No effect Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer 2 EN No effect Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following the write operation the BTCON 1 value is automatically cleared to 0 2 When you write a 1 to BTCON O the corresponding frequency divider is cleared to OOH Immediately following the write operation the BTCON 0 value is automatically cleared to 0 3 The fxx is selected clock for system main OSC or sub OSC ELECTRONICS 4 CONTROL REGISTERS S3F84NB_UM_REV1 00 CLKCON System Clock Control Register D4H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write _ _ _ R W R W _ _ _ Addressing Mode Register addressing mode only 7 5 Not used for the S3F84NB must keep always 0 4 3 CPU Clock System Clock Selection Bits note SSCS 2 0 Not used for the S3F84NB must keep always 0 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate value
235. oltage is below the reference value there is an internal and static RESET The MCU can start only when the supply voltage rises over the reference voltage When you calculate power consumption please remember that a static current of LVR circuit should be added a CPU operating current in any operating modes such as Stop Idle and normal RUN mode ELECTRONICS 18 1 LOW VOLTAGE RESET S3F84NB_UM_REV1 00 Watchdog nRESET nRESET Internal System nRESET When the Vpb level is lower than Vivr NOTES BGR is Band Gap voltage Reference Figure 18 1 Low Voltage Reset Circuit NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON 18 2 ELECTRONICS S3F84NB_UM_REV1 00 EMBEDDED FLASH MEMORY INTERFACE EMBEDDED FLASH MEMROY INTERFACE OVERVIEW The S3F84NB has an on chip flash memory internally instead of masked ROM The flash memory is accessed by instruction LDC This is a sector erasable and a byte programmable flash User can program the data in a flash memory area any time you want The S3F84NB s embedded 64K byte memory has two operating features as below e User Program Mode e Tool Program Mode
236. omatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE S3F84NB_UM_REV1 00 INTERRUPT TYPES The three components of the S3C8 interrupt structure described before levels vectors and sources are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source 54 Type 2 One level IRQn one vector V4 multiple sources S S Type 3 One level IRQn multiple vectors V V multiple sources S4 95 S4 4 Spam In the SSF84NB microcontroller two interrupt types are implemented Levels Vectors Sources 1 IRQn V1 Si 51 Type 2 IRQn gt 2 53 Sn 51 3 IRQn T 82 53 Sn NOTES 1 The number of Sn and Vn value is expandable 2 In the SSF84NB implementation interrupt types 1 and are used Figure 5 1 S3C8 Series Interrupt Types 5 2 ELECTRONICS S3F84NB_UM_REV1 00 INTERRUPT STRUCTURE S3F84NB INTERRUPT S
237. on Bits ooo _ Pio Push pullout _ 1 0 P1 4 ADC4 Configration Bits O 0 Inputmode ooo 0 1 mpumodepulup _ Pupo _ 4 18 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER P1CONL Port 1 Control Register Low Byte F1H Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 3 ADC3 Configration Bits Lo o mumd Co i input mode pup a o SSS 5 4 P1 2 ADC2 Configration Bits o o i momoe pmo 3 2 P1 1 ADC1 Configration Bits 9 0 o Pio Push pullout _ 1 0 P1 0 ADCO Configration Bits Fo o mumd Fo i mume a fo Puspo _ ELECTRONICS 4 19 CONTROL REGISTERS S3F84NB_UM_REV1 00 P2CONH Port 2 Control Register High Byte F2H Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 7 TAOUT ofo mame Co i K EJ Push pull output Alternative output mode TAOUT 5 4 2 6 _ Fo t pupa 3 2 2 5 oo o 1
238. op mode is released 1 During stop mode a power on reset or an interrupt occurs to trigger the Stop mode release and oscillation starts 2 If a power on reset occurred the basic timer counter will increase at the rate of fxx 4096 If an external interrupt is used to release stop mode the BTCNT value increases at the rate of the preset clock source 3 Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows When a BTONT 4 overflow occurs normal CPU operation resumes ELECTRONICS 10 3 BASIC TIMER S3F84NB_UM_REV1 00 RESETor STOP Basic Timer Control Register y Write 1010xxxxB to Disable Data Bus fxx 4096 fxx 1024 8 Bit Up Counter MUX BTCNT Read Only RESET ph 128 Start the CPU NOTE During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows Figure 10 2 Basic Timer Block Diagram 10 4 ELECTRONICS S3F84NB_UM_REV1 00 8 BIT TIMER A B C 0 1 8 BIT TIMER A B C 0 1 8 BIT TIMER A OVERVIEW The 8 bit timer A is an 8 bit general purpose timer counter Timer A has three operating modes you can select one of them using the appropriate TACON setting e Interval timer mode Toggle output at TAOUT pin e Capture input mode with a rising or falling edge trigger at the TACAP pin e PWM mode TAPWM Timer A has the following fu
239. output 3 2 bit P4 5 INT5 Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output 1 0 bit P4 4 INT4 Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output Figure 9 8 Port 4 High Byte Control Register ELECTRONICS 9 15 PORTS S3F84NB UM REV1 00 Port 4 Control Register Low Byte P4CONL F7H Set 1 Bank 0 R W 5 5 4 3 2 4 BEEN P4 3 P4 2 P4 1 INT3 INT2 INT1 7 6 bit P4 3 INT3 00 Input mode falling edge interrupt 01 Input mode rising edge interrupt 10 Input mode pull up falling edge interrupt 11 Push pull output 5 4 bit P4 2 INT2 00 Input mode falling edge interrupt 01 Input mode rising edge interrupt 10 Input mode pull up falling edge interrupt 11 Push pull output 3 2 bit P4 1 INT1 oo Input mode falling edge interrupt 01 Input mode rising edge interrupt 10 Input mode pull up falling edge interrupt 11 Push pull output 1 0 bit P4 0 INTO 00 Input mode falling edge interrupt 01 Input mode rising edge interrupt 10 Input mode pull up falling edge interrupt 11 Push pull output Figure 9 9 Port 4 Low Byte Control Register PACONL 9 16 ELECTRONICS S3F84NB_UM_REV1 00 PORTS Port 4 In
240. ow interrupts in the PWM mode these interrupts are not typically used in PWM type applications Instead the pulse at the T1TOUTO T1OUT1 pin is held to low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to high level for as long as the data value is greater than gt the counter value One pulse width is equal to tc TIMER 1 0 1 CONTROL REGISTER T1CONO T1CON1 You use the timer 1 0 1 control register T1CON1 to e Select the timer 1 0 1 operating mode Interval timer Capture mode PWM mode e Select the timer 1 0 1 input clock frequency e Clear the timer 1 0 1 counter TTCNTHO LO T1CNTH1 L1 e Enable the timer 1 0 1 overflow interrupt e Enable the timer 1 0 1 match capture interrupt T1CONO is located in set 1 and Bank 1 at address EAH and is read write addressable using Register addressing mode T1CON1 is located in set 1 and Bank 1 at address EBH and is read write addressable using Register addressing mode A reset clears T1 CONO T1CON1 to OOH This sets timer 1 0 1 to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer 1 0 1 interrupts To disable the counter operation please set T1CON 0 1 7 5 to 111B You can clear the timer 1 0 1 counter at any time during normal operation by writing a 1 to T1 CON 0 1 3 The timer 1 0 overflow interrupt T1OVFO is interrupt level IRQ3 and
241. owohegser WTOON 2s o o o o Oscilatorconvoleaister osccon se ADD converter conolregster Fm o o o o 9 AD converter data egiterigh byte ADDATAH 248 o o 0 AD converter data regsterlow byte ADDATAL 240 Fon o o o DARTI dataregister 25 EA 1 1 1 1 7 DARTI conmweregser Fea o o o o UART pending register 229 o o 0 o STOP conoi register STPCON 25 o o E o Patern generation contol regsier Pecon 24 Palem generation data regter PGDATA 255 o 6 8 4 ELECTRONICS S3F84NB_UM_REV1 00 RESET and POWER DOWN Table 8 4 SSF84NB Pages Register Values After RESET woe afte ete oe wx a a 2 9 VARTI baud rate data register BRDATAHI o oo t 1 1 1 1 1 1j AL Flash memory sector address register FMSECH 02H High byte Flash memory sector address register FMSECL 3 03H Low byte Flash memory user programming FMUSR 04H enable register Ee G e m ELECTRONICS 8 5 RESET POWER DOWN S3F84NB_UM_REV1 00 POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the o
242. per Address Byte Lower Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS 3 11 ADDRESSING MODES S3F84NB_UM_REV1 00 INDIRECT ADDRESS MODE IA In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory Next Instruction LSB Must be Zero urren Instruction P OPCODE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS S3F84NB_UM_REV1 00 ADDRESSING MODES RELATIVE ADDRESS MODE RA In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current
243. perating system As it produces the re locatable object codes only the user should link object files Object files can be linked with other object files and loaded into memory SASM requires a source file and an auxiliary register file device_name reg with device specific information SAMA ASSEMBLER The Samsung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generating an object code in the standard hexadecimal format Assembled program codes include the object code used for ROM data and required In circuit emulators program control data To assemble programs SAMA requires a source file and an auxiliary definition device name def file with device specific information HEX2ROM HEX2ROM file generates a ROM code from a HEX file which is produced by the assembler A ROM code is needed to fabricate a microcontroller which has a mask ROM When generating a ROM code file by HEX2ROM the value FF is automatically filled into the unused ROM area up to the maximum ROM size of the target device ELECTRONICS 22 1 DEVELOPMENT TOOLS S3F84NB_UM_REV1 00 TARGET BOARDS Target boards are available for all the S3C8 series microcontrollers All the required target system cables and adapters are included on the device specific target board TB84NB is a specific target board for the SSF84NB development IBM PC AT or Compatible RS 232C Emulator SMDS2 or SK 1000 Target gt RAM Break Display Unit
244. pt oooO i Input mode rising edge interrupt 1 0 input mode pul up faling edge interupt 1 0 P4 4 INT4 Fo Input mode falling edge interrupt oja Input mode rising edge interrupt K EJ Input mode pull up falling edge interrupt Push pull output 4 24 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER PACONL Port 4 Control Register Low Byte F7H Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P4 3 INT3 Fo Input mode falling edge interrupt ESEE Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output 5 4 P4 2 INT2 Lo Fo Input mode sing i 0 pulp tating edge SSCS 3 2 P4 1 INT1 o o edge interupt i oja Input mode rising edge interrupt 1 0 input mode pul up faling edge interupt 1 0 P4 0 INTO EE Input mode falling edge interrupt oja Input mode rising edge interrupt KE EJ Input mode pull up falling edge interrupt Push pull output ELECTRONICS 4 25 CONTROL REGISTERS S3F84NB_UM_REV1 00 P4INT Port 4 Interrupt Control Register FAH Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addre
245. puro 1 0 P2 4 TBPWM ofo mam _ Co i K EJ Push pull output Alternative output mode TBPWM 4 20 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER P2CONL Port 2 Control Register Low Byte F3H Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 3 BUZOUT ofo mame Co i input mode pup SSS Ears Push pull output Alternative output mode BUZOUT 5 4 P2 2 SCK Skimpy Fo putus _ 3 2 P2 1 SI o o mumu Fo r mumwepuw Pio Push pullout _ 1 0 P2 0 SO of ofm o fi iremos po o KE fo Push pull output Alternative output mode SO ELECTRONICS 4 21 CONTROL REGISTERS S3F84NB_UM_REV1 00 P3CONH Port 3 Control Register High Byte F4H Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 7 TCOUT1 ofo mame Push pull output Alternative output mode TCOUT1 5 4 P3 6 TCOUTO o o mumm Fo r mummepdw Pio Push pullout _ 3 2 P3 5 T10UT1 Pos iromo rio Push pullout _ 1 0 P3 4
246. put or push pull output Software assignable pull up Alternately P0 0 P0 7 can be used as the PG output port PGO PG7 Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternatively used as analog input pins for A D converter modules Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately 2 0 2 7 can be used as I O for TIMERA TIMERB BZOUT SIO Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately P3 0 P3 7 can be used as I O for TIMER C 0 TIMER C 1 TIMER 1 0 TIMER 1 1 Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up 4 0 4 7 can alternately be used as inputs for external interrupts INTO INT7 respectively with noise filters and interrupt controller Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately P5 0 P5 3 can be used as I O for serial port UARTO UART1 respectively Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up P6 0 P6 1 can alternately be used as Subsystem oscillator XTn XTour pins and P6 2 P6 7 can alternately be used as inputs for external interrup
247. r Circuit Crystal or Ceramic Oscillator Crystal Oscillator ELECTRONICS 7 1 CLOCK CIRCUIT S3F84NB_UM_REV1 00 CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and Idle mode affect the system clock as follows e n Stop mode the main oscillator is halted Stop mode is released and the oscillator is started by a reset operation or an external interrupt with RC delay noise filter and can be released by internal interrupt too when the sub system oscillator is running and watch timer is operating with sub system clock e In Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or by an external or internal interrupt Stop Release Main System Sub system Oscillator Oscillator Circuit Circuit Watch Timer LCD Controller Selector 1 OSCCON 3 OSCCON 0 STOP OSC 1 8 1 4096 Basic Timer inst Timer Counters gt Watch Timer Frequency Dividing Circuit STPCON 12 1 8 1 16 i System Clock Selector 2 CPU Clock _ IDLE Instruction Figure 7 3 System Clock Circuit Diagram 7 2 ELECTRONICS S3F84NB_UM_REV1 00 CLOCK CIRCUIT SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON is located in the bank 0 of set 1 address D4H It is read write addressable and has the following functions e Oscillator frequency divide
248. r IM r8 r R r OtoF 4 D7 Ir r src dst 3 6 E4 R R 6 E5 R IR opc dst src 3 6 E6 R IM 6 D6 IR IM opc src dst 3 6 F5 IR R 5 5 xt 5 5 Y ELECTRONICS 6 49 INSTRUCTION SET LD Load LD Continued S3F84NB_UM_REV1 00 Examples Given RO 01H R1 OAH register OOH 01H register 01H 20H register 02H 02H LOOP and register OFFH LD LD LD LD LD LD LD LD LD LD LD LD RO 10H R0 01H 01H RO R1 RO RO R1 00H 01H 02H 00H 00H 0AH 00H 10H 00H 02H RO LOOP R1 LOOP RO R1 E ES E E ES e A RO 10H RO 20H register 01H 20H Register 01H 01H RO 01H R1 20H RO 01H RO 01H R1 OAH register 01H OAH Register 00H 20H register 01H 20H Register 02H 20H register OOH 01H Register 00H 0AH Register OOH 01H register 01H 10H Register OOH 01H register 01H 02 register 02H 02H RO OFFH R1 0AH Register 31H OAH RO 01H R1 OAH ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET LDB Load Bit LDB LDB Operation Flags Format Examples dst src b dst b src dst 0 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected No flags are affected Bytes Cycles Opcode Addr
249. r Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode INSTRUCTION SET S3F84NB_UM_REV1 00 FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits that describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 can be tested and used with conditional jump instructions two others FLAGS 3 FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously two write will occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H R W Bank address Carry flag C status flag BA Fast interrupt Zero flag Z status flag FIS Sign flag S Half carry flag H Overflow flag V Decimal adjust flag D Figure 6 1 System Flags
250. r address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET Table 6 4 Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6 6 r Working register only Rn n 0 15 rb Bit b of working register Rn b n 0 15 b 0 7 ro Bit 0 LSB of working register Rn n 2 0 15 rr Working register pair RRp 0 2 4 14 R Register or working register reg or Rn reg 0 255 n 0 15 Rb Bit b of register or working register reg b reg 0 255 b 0 7 RR Register pair or working register pair reg or RRp reg 0 254 even number only where p 0 2 14 IA Indirect addressing mode addr addr 0 254 even number only Ir Indirect working register only Rn 0 15 IR Indirect register or indirect working register Rn or reg reg 0 255 n 0 15 Irr Indirect working register pair only RRp p 0 2 14 IRR Indirect register pair or indirect working RRp or reg reg 0 254 even only where register pair p 0 2 14 X Indexed addressing mode reg Rn reg 0 255 0 15 XS Indexed short offset addressing mode addr RRp addr range 128 to 127 where p 0 2 14 XL Indexed long offset addressing mode addr RRp addr range 0 65535 where p 0 2 14 DA Direct addressing mode addr addr range 0 65535 RA Relative a
251. r counter with selectable operating modes e Two asynchronous UART e One synchronous SIO e One Watch timer for real time clock e One Pattern generation Module e 10 bit 8 channel A D converter The SSF84NB is versatile microcontroller for home appliances and ADC applications etc They are currently available in 64 pin QFP and 64 pin SDIP package ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU e SAM8RC CPU core Memory e Program memory 64 Kbyte Internal Flash Memory Sector size 128Bytes 10years data retention Fast Programming Time Sector Erase 10ms Byte Program 32us Byte Programmable User programmable by LDC instruction Sector 128 bytes Erase available External serial programming support Endurance 10 000 Erase Program cycles Expandable OBPTM On Board Program e Data memory 2064 byte general purpose RAM Oscillation Sources Crystal or ceramic for main clock Crystal for sub clock 32 768 kHz Instruction Set e 78 instructions e IDLE and STOP instructions added for power down modes Instruction Execution Time e 400 ns at 10 MHz fosc minimum Interrupts e 29 interrupt sources with 29 vectors 8 levels Fast interrupt processing feature Ports e Total 56 bit programmable pins 8 Bit Basic Timer e One programmable 8 bit basic timer for oscillation stabilization control e Watchdog timer function Timers e 8 bit timer counter Timer A with three
252. r pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H 80H lt 80H 81H ADC 80H 82H 80H lt 80H 82H C ADC 80H 83H 80H lt 80H 83H C ADC 80H 84H 80H lt 80H 84H C ADC 80H 85H 80H lt 85H C Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rather than 36 cycles 2 12 ELECTRONICS S3F84NB_UM_REV1 00 ADDRESS SPACES REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you access any location in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored
253. ransmit interrupt pending bit UARTPND 0 and the receive interrupt pending bit UARTPND 1 the UART1 data transmit interrupt pending bit UARTPND 2 and the receive interrupt pending bit UARTPND 3 In mode 0 of the UART module the receive interrupt pending flag UARTPND 1 UARTPND 3 is set to 1 when the 8th receive data bit has been shifted In mode 1 2 and 3 the UARTPND 1 UARTPND 3 bit is set to 1 at the halfway point of the stop bit s shift time When the CPU has acknowledged the receive interrupt pending condition the UARTPND 1 UARTPND 3 flag must then be cleared by software in the interrupt service routine In mode 0 of the UART module the transmit interrupt pending flag UARTPND 0 UARTPND 2 is set to 1 when the 8th transmit data bit has been shifted In mode 1 2 or 3 the UARTPND 0 UARTPND 2 bit is set at the start of the stop bit When the CPU has acknowledged the transmit interrupt pending condition the VARTPND 0O UARTPND 2 flag must then be cleared by software in the interrupt service routine UART Pending Register UARTPND FCH Set 1 Bank 1 R W MSB PEN1 RPE1 PENO RPE0 TIP1 TIPO LSB UART1 parity enable disable UARTO transmit interrupt pending flag 0 Disable 0 Not pending 1 Enable 0 Clear pending bit when write 1 Interrupt pending UART1 receive parity error 0 No error UARTO receive interrupt pending flag 1 Parity error 0 Not pending 0 Clear pending bit when write
254. ration and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 16 High Address Top of stack Stack contents Stack contents after a call after an instruction interrupt Low Address Figure 2 16 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least significant byte SP7 SPO is stored in the SPL register D9H After a reset the SP value is undetermined Because only internal memory space is implemented in the S3F84NB the SPL must be initialized to an 8 bit value in the range The SPH register is not needed and can be used as a general purpose register if necessary When the SPL register contains the only stack pointer value that is when it points to a system stack in the register file you can use the SPH register as a general purpose data register However if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations the
255. rce register with the bit O value of register R1 destination leaving the value 06H 00000110B in register R1 ELECTRONICS 6 17 INSTRUCTION SET S3F84NB_UM_REV1 00 BCP Bit Compare BCP Operation Flags Format Example dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison Unaffected Set if the two bits are the same cleared otherwise Cleared to O Undefined Unaffected Unaffected TOSONO Bytes Cycles Opcode Addr Mode Hex dst src NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H register 01H 01H BCP R1 01H 1 gt R1 07H register 01H 01H If destination working register R1 contains the value 07H 000001 11B and the source register 01H contains the value 01H 00000001B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag Z is cleared in the FLAGS register OD5H ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET BITC Bit Complement BITC Operation Flags Format Example dst b
256. re 2 1 The first 256 bytes of the program memory are reserved for interrupt vector addresses Unused locations 0000H OOFFH except 03CH 03DH and in this address range can be used as normal program memory The location 03CH is used as smart option ROM cell If you use the vector address area to store program code be careful to avoid overwriting vector addresses stored in these locations The program memory address at which program execution starts after reset is 0100H default If you use ISPTM sectors as the ISPTM software storage the reset vector address can be changed by setting the Smart Option Refer to Figure 2 2 Decimal 65 536 Internal Program Memory Flash S3F84NB 64Kbyte Figure 2 1 Program Memory Address Space NOTES 1 The size of ISP sector can be varied by Smart Option Refer to Figure 2 2 According to the smart option setting related to the ISP ISP reset vector address can be changed one of addresses to be select 200H 300H 500H or 900H 2 ISPTM sector can store On Board Program Software Refer to chapter 15 Embedded Flash Memory Interface 2 2 ELECTRONICS S3F84NB_UM_REV1 00 ADDRESS SPACES SMART OPTION Smart option is the program memory option for starting condition of the chip The program memory addresses used by smart option are from 003CH to The SSF84NB only use 003EH and 003FH User ca
257. re 9 13 Port 5 Low Byte Control Register P5CONL 9 20 ELECTRONICS S3F84NB_UM_REV1 00 PORTS PORT 6 Port 6 is an 8 bit digital I O port that you can use three ways e General purpose digital I O e External interrupt inputs for INT8 INT13 e Subsystem oscillator input XT iN output XT oy pins Port 6 is accessed directly by writing or reading the port 6 data register P6 at location E6H in set 1 bank 0 Port 6 Control Register P6CONL Port 6 pins are configured individually by bit pair settings in two control registers located in set 1 bank 0 P6CONL low byte 9 and PeCONH high byte E8H When you select output mode a push pull circuit is configured In input mode three different selections are available for 6 2 6 7 e Schmitt trigger input and interrupt generation on falling signal edges e Schmitt trigger input and interrupt generation on rising signal edges e Schmitt trigger input with pull up resister and interrupt generation on falling signal edges Port 6 Interrupt Enable and Pending Registers P6INT PeINTPND To process external interrupts at the port 6 pins two additional control registers are provided the port 6 interrupt enable register 6 EDH set 1 bank 0 and the port 6 interrupt pending register 6 set 1 bank 0 The port 6 interrupt pending register P6INTPND lets you check for interrupt pending conditions and clear the pending condition when the
258. re set to XTin and XTout respectively e Peripheral control and data registers are disabled and reset to their default hardware values e The program counter PC is loaded with the program reset address in the ROM 0100H e When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed NORMAL MODE RESET OPERATION In normal masked ROM mode the TEST pin is tied to Vss A reset enables access to the 48 Kbyte on chip ROM NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON ELECTRONICS 8 1 RESET POWER DOWN S3F84NB_UM_REV1 00 HARDWARE RESET VALUES Table 8 1 8 2 and 8 3 list the reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values e 1 0 shows the reset bit value as logic one or logic zero respectively e An x means that the bit value is undefined after a reset e Adash means that the bit is either not used or not mapped but read 0 is the bit value Table
259. received ELECTRONICS 14 13 UART O 1 S3F84NB_UM_REV1 00 Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications Set all S8F84NB devices masters and slaves to UART mode 2 or 3 with parity disable 2 Write the MCE bit of all the slave devices to 1 The master device s transmission protocol is e First byte the address identifying the target slave device 9th bit 1 e Next bytes data 9th bit 0 4 When the target slave receives the first byte all of the slaves are interrupted because the 9th data bit is 1 The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive incoming data The other slaves continue operating normally Full Duplex Multi S3F84NB Interconnect TxD RxD TxD Master Slave 1 S3F84NB S3F84NB S3F84NB S3F84NB Figure 14 9 Connection Example for Multiprocessor Serial Data Communications 14 14 ELECTRONICS S3F84NB_UM_REV1 00 A D CONVERTER A D CONVERTER OVERVIEW The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10 bit digital values The analog input level must lie between the and AVss values The A D converter has the following components e Analog comparator with successive approximation logic e D A converter logic resistor string type e control
260. register FMCON 0 is a bit for the operation start of Erase and Hard Lock Protection Therefore operation of Erase and Hard Lock Protection is activated when you set FMCON O to 1 If you write to 1 for erasing CPU is stopped automatically for erasing time min 10ms After erasing time CPU is restarted automatically When you read or program a byte data from or into flash memory this bit is not needed to manipulate FLASH MEMORY USER PROGRAMMING ENABLE REGISTER FMUSR The FMUSR register is used for a safe operation of the flash memory This register will protect undesired erase or program operation from malfunctioning of CPU caused by an electrical noise After reset the user programming mode is disabled because the value of FMUSR is 00000000P by reset operation If necessary to operate the flash memory you can use the user programming mode by setting the value of FMUSR to 10100101B The other value of 10100101B user program mode is disabled Flash Memory User Programming Enable Register FMUSR EEH Page 8 R W Flash Memory User Programming Enable Bits 10100101 Enable user programming mode Other values Disable user programming mode Figure 19 4 Flash Memory User Programming Enable Register FMUSR 19 6 ELECTRONICS S3F84NB_UM_REV1 00 EMBEDDED FLASH MEMORY INTERFACE FLASH MEMORY SECTOR ADDRESS REGISTERS There are two sector address registers for the erase or programming flash memory The FMSE
261. relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET DA Decimal Adjust DA Operation Instruction ADD ADC SUB SBC Flags Format dst dst lt DA dst The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits Carry Bits 4 7 H Flag Bits 0 3 Number Added Carry Before DA Value Hex Before DA Value Hex to Byte After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 0 A F 0 0 9 60 1 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 0 0 8 1 6 F FA 06 0 1 7 F 0 0 9 60 1 1 6 F 1 6 F 9A 66 1 C Set if there was a carry from the most significant bit cleared otherwise see table Z Set if result is 0 cleared otherwise S Set if result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 40 R 4 41 I
262. rence voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first bit conversion is always 1 2 AVper CONVERSION TIMING The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to step up A D conversion Therefore total of 50 clocks is required to complete a 10 bit conversion With a 10 MHz CPU clock frequency one clock cycle is 400 ns 4 fxx If each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bits step up time 10 clock 50 clocks 50 clock x 400 ns 20 us at 10 MHz 1 clock time 4 fxx ADCON 0 C 1 50 ADC Clock Conversion Start I I I I EOC moons I I I Valid Data Previous ADDATAH 8 Bit ADDATAL 2 Bit Value 40 Clock 10 clock Figure 15 4 A D Converter Timing Diagram 15 4 ELECTRONICS S3F84NB_UM_REV1 00 A D CONVERTER INTERNAL A D CONVERSION PROCEDURE 1 Analog input must remain between the voltage range of AVss and 2 Configure 1 0 1 7 for analog input before A D conversions To do this you load the appropriate value to the P1CONH and P1CONL for ADCO ADCT7 registers 3 Before the conversion operation starts you must first select one of the eight input pins ADCO ADC7 by writing the appropriate value to the ADCON register 4 When
263. rful data manipulation capabilities and features of the instruction set include e A full complement of 8 bit arithmetic and logic operations including multiply and divide e special instructions I O control data registers are mapped directly into the register file e Decimal adjustment included in binary coded decimal BCD operations e 16 bit word data can be incremented and decremented e Flexible instructions for bit addressing rotate and shift operations Data Types The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit Register Addressing To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data or 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Section 2 Address Spaces Addressing Modes There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Section 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET Mnemonic Load Instructions CLR LD LDB LDE LDC
264. ring normal stack operations the value in the 2 2 SPL register will overflow or underflow to the SPH register overwriting any other data that is currently stored there To avoid overwriting data in the SPH register you can initialize the SPL value to instead of OOH 05 Interrupt Structure Added a note in Figure 5 6 15 A D Converter Modified ADCON 7 to be Keep Always Logic 0 3 0 6 19 Embedded Flash Figure 19 2 Smart Option LVR level is changed from 3 9V to 4 0V Memory Interface when LVR Level Selection Bits is set to 01 20 Electrical Data Changed the pull up resistor value to 50kQ in Table 20 3 Deleted the strong mode in Table 20 8 3 Preface The S3F84NB Microcontroller User s Manual is designed for application designers and programmers who are using the S3F84NB microcontroller for application development It is organized in two main parts Part Programming Model Part Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to SSF84NB with general product descriptions as well as detailed information
265. rking register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in register R1 6 16 ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET BAND Bit AND BAND BAND Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 AND src b or dst b lt dst b AND src 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected ITO lt ONO Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 67 Rb ro NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 05H BAND R1 01H 1 gt R1 06H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example source register 01H contains the value 05H 00000101B and destination working register R1 contains 07H 00000111B The statement BAND R1 01H 1 ANDs the bit 1 value of the sou
266. roup C is IRQ5 IRQ6 and IRQ7 Interrupt request register This register contains a request pending bit for each interrupt level System mode register SYM R W _ This register enables disables fast interrupt processing dynamic global interrupt processing NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended ELECTRONICS 5 7 INTERRUPT STRUCTURE S3F84NB_UM_REV1 00 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system level control points in the interrupt structure are e Global interrupt enable and disable by El and DI instructions or by direct manipulation of SYM 0 e Interrupt level enable disable settings IMR register e Interrupt level priority settings IPR register e Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register pointer information Interrupt Request Register RESET Read only IRQO IRQ7 Interrupts Interrupt Priority Vector Register Interrupt Cycle Interrupt Mask Register Global Interrupt Control El DI or SYM O manipulation Figure 5 4 Interrupt Function Diagram PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there i
267. rrupt Subgroup B Priority Control Bit gt IRQ4 IRQ4 gt IRQ3 2 Interrupt Group Priority Control IRQ2 gt IRQ3 IRQ4 1 IRQ3 IRQ4 gt IRQ2 0 Interrupt Group A Priority Control Bit IRQO gt IRQ1 IRQ1 gt IRQO 4 14 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER IRQ Interrupt Request Register DCH Set 1 Bit Identifier 7 6 5 4 3 2 RESET Value 0 0 0 0 0 0 0 0 Read Write R R R R R R R R Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Request Pending Bit 0 Not pending 1 Pending 6 Interrupt Level 6 IRQ6 Request Pending Bit Not pending Pending 5 Interrupt Level 5 IRQ5 Request Pending Bit Not pending 1 Pending 4 Interrupt Level 4 IRQ4 Request Pending Bit Not pending Pending 3 Interrupt Level 3 IRQ3 Request Pending Bit Not pending Pending 2 Interrupt Level 2 IRQ2 Request Pending Not pending Pending 1 Interrupt Level 1 IRQ1 Request Pending Bit Not pending Pending 0 Interrupt Level 0 IRQ0 Request Pending Bit Not pending Pending ELECTRONICS 4 1 CONTROL REGISTERS S3F84NB_UM_REV1 00 OSCCON Oscillator Control Register F6H Set 1 Bank 1 Bit Identifier 7 6 5 A 3 2 1 0 RESET Value 0 0 0 Read Write _ _ _ _ R W R W _ R W Addressing Mode 7 4 Register addressing mode only Not used for the S3F84NB Main System Osc
268. rviced the following conditions must be met Interrupt processing must be globally enabled El SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The PON CPU then initiates an interrupt machine cycle that completes the following processing sequence Reset clear to 0 the interrupt enable bit in the SYM register SYM 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags setting SYM O to 1 It allows the CPU to process the next interrupt request ELECTRONICS S3F84NB_UM_REV1 00 INTERRUPT STRUCTURE GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM 00H FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence oo rf oN gt Push the program counter s low byte value to
269. s Figure 14 5 UART Functional Block Diagram 14 8 ELECTRONICS S3F84NB_UM_REV1 00 UART O 1 UART MODE 0 FUNCTION DESCRIPTION In mode 0 UARTO is input and output through the RxDO P5 3 pin and TxDO P5 2 pin outputs the shift clock Data is transmitted or received in 8 bit units only The LSB of the 8 bit value is transmitted or received first Mode 0 Transmit Procedure 1 Select mode 0 by setting UARTCONO 6 and 7 to 2 Write transmission data to the shift register UDATAO E2H set 1 bank 1 to start the transmission operation Mode 0 Receive Procedure 1 Select mode 0 by setting UATCONO 6 and 7 to 2 Clear the receive interrupt pending bit UARTPND 1 by writing a 0 to UARTPND 1 3 Setthe UARTO receive enable bit UARTCONO 4 to 1 4 The shift clock will now be output to the TxDO P5 2 pin and will read the data at the RxDO P5 3 pin A UARTO receive interrupt IRQ7 vector FOH occurs when UARTCONO 1 is set to 1 Write to Shift Register UDATA IL JL JE JL IL JL dL d RxD Data Out DO D1 D2 D3 D4 D5 D6 D7 Transmit TxD Shift Clock Write to UARTPND Clear RIP and set RE RE Shift RxD Data In DO D1 D2 D3 D4 D5 D6 D7 TxD Shift Clock _ _ _ Figure 14 6 Timing Diagram for UART Mode 0 Operation ELECTRONICS 14 9 UART O 1 S3F84NB UM REV1 00 UART MODE 1 FUNCTION DESCRIPTION In mode 1 10 bits are transmitted throu
270. s one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral see Table 5 3 5 8 ELECTRONICS S3F84NB_UM_REV1 00 INTERRUPT STRUCTURE Table 5 3 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s in Set 1 Timer B underflow TBCON DOH bank 0 TBDATAH TBDATAL D1H D2H bank 0 Timer A overflow Timer A match capture Timer C 0 match overflow Timer C 1 match overflow Timer 1 0 match capture Timer 1 0 overflow Timer 1 1 match capture 1 Timer 1 1 overflow TINTPND TACON TADATA TACNT TCCONO TCCON1 TCDATAO TCDATA1 T1DATAHO T1DATALO T1DATAH1 T1DATAL1 T1CONO T1CON1 T1CNTHO T1CNTLO T1CNTH1 T1OCNTL1 E7H bank 0 EAH bank 0 EBH bank 0 ECH bank 0 F2H bank 1 F3H bank 1 FOH bank 1 F1H bank 1 E6H E7H bank 1 E8H E9H bank 1 EAH EBH bank1 ECH EDH bank1 EEH EFH bank1 SIO receive transmit Watch timer P6 7 external interrupt P6 6 external interrupt P6 5 external interrupt P6 4 external interrupt P6 3 external interrupt P6 2 external interrupt P4 7 external interrupt P4 6 external interrupt P4 5 external interrupt P4 4 external interrupt P4 3 external interrupt P4 2 external interrupt P4 1 external interrupt P4 0 external interrupt UARTO receive transmit UART1 receive transmit ELECTRONICS SIOCON SIODATA WTCON P6CONH P6CONL P6INT P6INTPND P4CONH P4CONL P4IN
271. s to CLKCON 3 and CLKCON 4 4 8 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER FLAGS System Flags Register D5H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value x x x x x x 0 0 Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only 7 Carry Flag C Operation does not generate a carry or underflow condition Operation generates a carry out or underflow into high order bit 7 6 Zero Flag 2 Operation result is a non zero value 1 Operation result is zero 5 Sign Flag S Operation generates a positive number MSB 0 1 Operation generates a negative number MSB 1 A Overflow Flag V Operation result is lt 127 or gt 128 1 Operation result is gt 127 or lt 128 3 Decimal Adjust Flag D Add operation completed 1 Subtraction operation completed 2 Half Carry Flag H No carry out of bit 3 or no underflow into bit 3 by addition or subtraction 1 Addition generated carry out of bit or subtraction generated underflow into bit jeo carryout or BES or noun ro By aon reason a pesce E 1 Fast Interrupt Status Flag FIS Interrupt return IRET in progress when read Fast interrupt service routine in progress when read 0 Bank Address Selection Flag Bank 0 is selected 1 Bank 1 is selected ELECTRONICS 4 CONTROL REGISTERS S3F84NB_UM_REV1 00 FMCON Flash Memory Control Register 05H Page
272. s used for set 1 locations COH FFH is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 For the S8F84NB the set 2 address range COH FFH is accessible on pages 0 8 The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 location In order to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode The set 2 register area is commonly used for stack operations 2 8 ELECTRONICS S3F84NB_UM_REV1 00 ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes but page8 is 6byte of the S3F84NB s eight 256 byte register pages is called prime register area Prime registers can be accessed using any of the seven addressing modes see Chapter 3 Addressing Modes The prime register area on page 0 is immediately addressable following a reset In order to address prime registers on pages 0 or 1 you must set the register page pointer PP to the appropriate source and destination values 1 Bank 1 Page 8 CPU and system control Bg General purpose Peripheral and I O Figure 2 5 Set 1 Set 2 Prime Area Register ELECTRONICS 2 9 ADDRESS SPACES S3F84NB_UM_REV1 00 WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields Whe
273. should be tied to 3 3 V during programming NOTE means 64QFP package 19 2 ELECTRONICS S3F84NB_UM_REV1 00 EMBEDDED FLASH MEMORY INTERFACE ISP ON BOARD PROGRAMMING SECTOR ISP sectors located in program memory area can store On Board Program Software Boot program code for upgrading application code by interfacing with I O port pin The ISPTM sectors can t be erased or programmed by LDC instruction for the safety of On Board Program Software The ISP sectors are available only when the ISP enable disable bit is set 0 that is enable ISP at the Smart Option If you don t like to use ISP sector this area can be used as a normal program memory can be erased or programmed by LDC instruction by setting ISP disable bit 1 at the Smart Option Even if ISP sector is selected ISP sector can be erased or programmed in the tool program mode by serial programming tools The size of ISP sector can be varied by settings of smart option Refer to Figure 2 2 and Table 19 2 You can choose appropriate ISP sector size according to the size of On Board Program Software Decimal 65 536 Internal Program Memory Flash O1FFH O2FFH O4FFH or O8FFH OFFH 03FH 03CH 00H Figure 19 1 Program Memory Address Space ELECTRONICS 19 3 EMBEDDED FLASH MEMORY INTERFACE S3F84NB_UM_REV1 00 SMART OPTION Smart option is the program memory option for starting condition of the chip The program memory addre
274. sses used by smart option are from 003CH to The SSF84NB only use 003EH and 003FH User can write any value in the not used addresses 003CH and 003DH The default value of smart option bits in program memory is OFFH IPOR disable LVD enable in the stop mode Normal reset vector address 100H ISP protection disable Before execution the program memory code user can set the smart option bits according to the hardware option for user to want to select ROM Address 003CH Not used ROM Address 003DH Not used ROM Address 003EH ISP Reset Vector Change Selection Bit ISP Protection Size Selection Bits 0 OBP Reset vector address 00 256 bytes 1 Normal vector address 100H 01 512 bytes 10 1024 bytes 11 2048 bytes ISP Reset Vector Address Selection Bits 2 00 200H ISP Area size 256 bytes 01 300H ISP Area size 512 bytes ISP Protection Enable Disable Bit 9 10 500H ISP Area size 1024 bytes 0 Enable Not erasble 11 900H ISP Area size 2048 bytes 1 Disable Erasable ROM Address 003FH LVR Level Selection Bits 01 4 0V 10 2 2V 11 3 0V LVR Control Bit 1 LVR disable 0 LVR enable Figure 19 2 Smart Option 19 4 ELECTRONICS S3F84NB_UM_REV1 00 EMBEDDED FLASH MEMORY INTERFACE NOTES 1 setting ISP Reset Vector Change Selection Bit 3EH 7 to 0 user can have the available ISP area If ISP Reset Vector Change Selection Bit 3E
275. ssing mode only T P4 7 External Interrupt INT7 Enable Bit 0 Disable interrupt 1 Enable interrupt 6 P4 6 External Interrupt INT6 Enable Bit Disable interrupt EB Enable interrupt 5 P4 5 External Interrupt INT5 Enable Disable interrupt Enable interrupt 4 P4 4 External Interrupt INT4 Enable Bit Disable interrupt Enable interrupt 3 P4 3 External Interrupt INT3 Enable Bit Disable interrupt Enable interrupt 2 P4 2 External Interrupt INT2 Enable Disable interrupt Enable interrupt 1 P4 External Interrupt INT1 Enable Bit Disable interrupt Enable interrupt 0 4 0 External Interrupt INTO Enable Bit Disable interrupt Enable interrupt 4 26 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER P4INTPND Port 4 Interrupt Pending Register FBH Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P4 7 PND7 Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 6 P4 6 PND6 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 5 P4 5 PND5 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 4 P4 4 PND4 Interr
276. ster 4 6 BTCON Basic Timer Control Register na a 4 7 CLKCON System Clock Control Register nnne 4 8 FLAGS System Flags Register l sau 4 9 FMCON Flash Memory Control Register enne 4 10 FMSECH Flash Memory Sector Address Register High Byte 4 10 FMSECL Flash Memory Sector Address Register Low Byte 4 11 FMUSR Flash Memory User Programming Enable 4 11 IMR Interrupt Mask Register u n ua n 4 12 IPH Instruction Pointer High Byte u u ener enne 4 13 IPL Instruction Pointer Low Byte 4 13 IPR Interrupt Priority masa a tiana E ea 4 14 IRQ Interrupt Request Register 4 15 OSCCON Oscillator Control Register I 4 16 Port 0 Control 1 5 a 4 17 1 Port 1 Control Register High Byte 4 18 P1CONL Porti Control Register High Byte a 4 19 P2CONH Port 2 Control Register High Byte 4 20 P2CONL Port 2 Control Register Low Byte
277. ster Values after 8 5 SSF84NB Port Configuration Overview sse 9 1 Port Data Register Summary U U 9 2 Commonly Used Baud Rates Generated by BRDATAO 14 7 Watch Timer Control Register WTCON Set1 Bank1 F5H RW 16 2 Descriptions of Pins Used to Read Write the Flash in Tool Program Mode 19 2 ISP Sector eter eade da Feci Rep edu 19 5 Reset Vector Addres Sasina a enne 19 5 XV S3F84NB_UM_REV1 00 MICROCONTROLLER xvi List of Tables Title Page Number Absolute Maximum RatingsS U 20 2 Input Output Capacitance a a nnns 20 2 D C Electrical Characteristics 20 3 A C Electrical Characteristics edes ea dea nee rna 20 5 Main Oscillator Frequency 20 6 Main Oscillator Clock Stabilization Time te4 sees 20 6 Sub Oscillator Frequency t e env 20 8 Subsystem Oscillator crystal Stabilization Time 20 8 Data Retention Supply Voltage in Stop Mode 20 9 Serial I O Timing Characteristics
278. t Figure 20 1 Input Timing for External Interrupts Ports 4 and 6 nRESET Figure 20 2 Input Timing for nRESET ELECTRONICS 20 5 ELECTRICAL DATA S3F84NB_UM_REV1 00 Table 20 5 Main Oscillator Frequency fosc Ta 40 C 85 C Oscillator Clock Grout TeatCondition min Typ Max Unit _ 10 MHz Main crystal or 1 XIN Vpp 2 0 to 5 5 V 1 ceramic External clock Main System Table 20 6 Main Oscillator Clock Stabilization Time ts TA 40 85 Vpp 2 0 V to 5 5 V Oscillator Test Condition Min Typ Max Unit Main Crystal fosc gt 1 0 MHz Main Ceramic Oscillation stabilization occurs when Vpp is equal to the minimum oscillator voltage range Oscillator twarr When released by a reset 1 Stabilization Wait Time twarr when released by an interrupt 2 NOTES 1 fosc is the oscillator frequency 2 The duration of the oscillator stabilization wait time tyay 7 when it is released by an interrupt is determined by the settings in the basic timer control register BTCON 20 6 ELECTRONICS S3F84NB_UM_REV1 00 ELECTRICAL DATA CPU Clock 10 MHz 8 MHz Supply Voltage V Figure 20 3 Operating Voltage Range 0 3 0 7 VDD Figure 20 4 Schmitt Trigger Input Characteristics Diagram ELECTRONICS 20 7 ELECTRICAL DATA S3F84NB_UM_REV1 00 Table 20 7 Sub Oscillator Frequency
279. t Register 01H 24H register 02H ADD 01H 02H Register 01H 2BH register 02H 03H ADD 01H 425H gt Register 01H 46H In the first example destination working register R1 contains 12H and the source working register R2 contains 03H The statement ADD R1 R2 adds 03H to 12H leaving the value 15H in register R1 ELECTRONICS 6 15 INSTRUCTION SET S3F84NB_UM_REV1 00 AND Logical AND AND dst src Operation dst dst AND src The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation results in a 1 bit being stored whenever the corresponding bits in the two operands are both logic ones otherwise a bit value is stored The contents of the source are unaffected Flags C Unaffected Z Setif the result is cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to O D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src opc dst src 2 4 52 r r 53 r Ir opc src dst 3 6 54 R R 6 55 R IR opc dst src 3 6 56 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register O3H OAH AND R1 R2 AND R1 R2 AND 01H 02H AND 01H 02H AND 01H 25H gt Register 01H R1 02H R2 03H R1 02H R2 03H Register 01H 01H register 02H 03H Register 01H 00H register 02H 03H 21H E In the first example destination wo
280. t operation Mode 2 amp 3 Receive Procedure 1 Select the baud rate to be generated by 16bit BRDATA 2 Select mode 2 amp 3 and set the receive enable bit RE in the UARTCONO register to 1 3 If you don t use a parity mode set PENO PEN1 bit of UARTPND register to 0 to disable parity mode If you want to use the parity enable mode select the parity type to be check by writing TB8 to 0 or 1 and set PENO PEN1 bit of UARTPND register to 1 Only 8 bits BitO to Bit7 of received data are available for data value 4 The receive operation starts when the signal at the RxD pin goes to low level ELECTRONICS 14 11 UART O 1 S3F84NB UM REV1 00 Write to Shift Register UDATA Transmit Start Bit DO D1 D7 Stop Bit TB8 or Parity bit RB8 or Parity bit RxD Start Bit DO D1 D2 D3 D4 D5 D6 D7 Stop Bit TTL TITEL TITEL Shift l RIP m Figure 14 8 Timing Diagram for UART Mode 2 amp 3 Operation 14 12 ELECTRONICS S3F84NB_UM_REV1 00 1 SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3C8 series multiprocessor communication features let a master SSF84NB send a multiple frame serial message to a slave device in a multi SSF84NB configuration It does this without interrupting other slave devices that may be on the same serial line This feature can be used only in UART modes 2 or 3 with the parity disable mod
281. te DAH Set 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address IP 15 IP8 The lower byte of the IP address is located the IPL register DBH IPL instruction Pointer Low Byte DBH Set 1 RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located in the IPH register DAH ELECTRONICS 4 13 CONTROL REGISTERS S3F84NB_UM_REV1 00 IPR Interrupt Priority Register FFH Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 0 RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 and 1 Priority Control Bits for Interrupt Groups A B and C fo Groupprintyundeined SS 1 Group priority undefined 6 Interrupt Subgroup C Priority Control Bit IRQ6 gt IRQ7 IRQ7 gt IRQ6 5 Interrupt Group Priority Control IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 3 Inte
282. tents of RO is loaded into program memory location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH LDEPI RR6 RO RR6 RR6 1 contents of is loaded into external data memory location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH ELECTRONICS 6 57 INSTRUCTION SET S3F84NB_UM_REV1 00 LDW Load Word LDW Operation Flags Format Examples dst src dst lt src The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 C4 RR RR C5 RR IR dst src 4 8 C6 RR IML Given R4 06H R5 1CH R6 05H R7 02H register 1AH register 01H 02H register 02H and register OFH LDW RR6 RR4 gt R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H gt Register 03H register 01H OFH register 02H 03H register 03H LDW RR2 R7 R2 03H R3 OFH LDW 04H 01H gt Register 04H 03H register 05H OFH LDW RR6 1234H gt R6 12H R7 34H OEDH LDW 02H 0FEDH gt Register 02H OFH register 03H In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H 03H into the destination word 00H 01H This leaves the value 03H in general register 00H and the value OFH in register 01H The other examples show how to use the LDW instruct
283. terrupt Control Register P4INT FAH Set 1 Bank 0 R W TTTTTTIT INT7 INT6 INT5 INT4 INTS INT2 INT1 INTO PAINT Bit Configuration Settings 0 Interrupt disable 1 Interrupt enable Figure 9 10 Port 4 Interrupt Control Register PAINT Port 4 Interrupt Pending Register PAINTPND FBH Set 1 Bank 0 R W TITTTTTT PND7 PND6 PND5 PND4 PND3 PND2 PND1 PNDO P4INTPND Bit Configuration Settings 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending Figure 9 11 Port 4 Interrupt Pending Register PAINTPND ELECTRONICS 9 17 PORTS S3F84NB_UM_REV1 00 PORT 5 Port 5 is an 8 bit digital I O port with individually configurable pins Port 5 pins are accessed directly by writing or reading the port 5 data register P5 at location E5H in set 1 bank 0 5 7 5 4 can serve as inputs outputs push pull open drain 5 3 5 0 can serve as inputs outputs push pull or you can configure the following alternative functions e Low byte pins P5 3 P5 0 RxDO RxD1 TxD1 Port 5 Control Register 5 P5CONL Port 5 has two 8 bit control registers PSCONH for P5 4 P5 7 and PSCONL for 5 0 5 3 A reset clears the P5CONH and P5CONL registers to OOH configuring all pins to input mode You use control registers settings to select input or output mode push pull open drain and enable the alternative functions When programming the port please rem
284. the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location Branch to the service routine specified by the concatenated 16 bit vector address NOTE A 16 bit vector address always begins at an even numbered ROM address within the range of NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR Execute an IRET Depending on the application you may be able to simplify the procedure above to some extent ELECTRONICS 5 17 S3F84NB_UM_REV1 00 INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers There are 78 instructions The powe
285. tialization routine When more than one interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 GroupA _IRQO IRQ1 GroupB IRQ2 IRQ3 IRQ4 GroupC IRQ5 IRQ6 IRQ7 B21 B22 C21 IRQO IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B C A The setting 101B would select the relationship C gt B gt A The functions of the other IPR bit settings are as follows e PR 5controls the relative priorities of group C interrupts e Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C e PR 0O controls the relative priority setting of IRQO and IRQ1 interrupts 5 12 ELECTRONICS S3F84NB_UM_REV1 00 IN
286. ting EMBEDDED FLASH MEMORY INTERFACE Select Page 8 Set Secotr Base Address Set Address and Data User Program Mode Enable Mode Select Write data at flash User Program Mode Disable Select Page 0 Figure 19 9 Byte Program Flowchart in a User Program Mode ELECTRONICS 19 13 EMBEDDED FLASH MEMORY INTERFACE S3F84NB_UM_REV1 00 PP lt 88H Select Page 8 FMSECH lt High Address of Sector Set Secotr Base Address FMSECL lt Low Address of Sector R n High Address to Write Set Address and Data R n 1 Low Address to Write R data 8 bit Data FMUSR lt 0A5H User Program Mode Enable FMCON lt 301010000B Mode Select Write data atflash LDC lt JQRR n R data User Program Mode Disable Write again NO FMUSR lt 00 User Program Mode Disable Check Sector YES CLR PP Select Page0 ontinuous address 5 Check Address Finish Writing YES INC 1 5 Increse Address s YES Different Data R data lt New 8 bit Data Update Data to Write Figure 19 10 Program Flowchart in a User Program Mode 19 14 ELECTRONICS S3F84NB_UM_REV1 00 EMBEDDED FLASH MEMORY INTERFACE PROGRAMMING TIP Programming 1 1 Byte Programming WR_BYTE LD LDC LD Write data AAH to destination address 4010H PP 88H FMUSR 0A5H User program mode enable FMCON 01010000B _ Selection programming mode FMSECH 40H Set the base address of se
287. trol Register PBCONH sse 9 12 9 7 Port Low Byte Control Register PSCONL sse 9 13 9 8 Port 4 High Byte Control Register PACONH sse 9 15 9 9 Port 4 Low Byte Control Register PACONL 9 16 9 10 Port 4 Interrupt Control Register PAINT 9 17 9 11 Port 4 Interrupt Pending Register 9 17 9 12 Port 5 High Byte Control Register PBCONH sse 9 19 9 13 Port 5 Low Byte Control Register PSCONL seen 9 20 9 14 Port 6 High Byte Control Register 6 9 22 9 15 Port 6 Low Byte Control Register 6 9 23 9 16 Port 6 Interrupt Control Register 9 24 9 17 Port 6 Interrupt Pending Register 6 9 24 xii S3F84NB UM REV1 00 MICROCONTROLLER List of Figures Concluded Figure Title Page Number Number 10 1 Basic Timer Control Register BTCONJ a 10 2 10 2 Basic Timer Block Diagram a su 10 4 11 1 Timer A Control Register 11 3 11 2 Timer A Functional Block Diagram aa 11 4 11 3 Timer B Functional Block Diagram
288. ts INT8 INT13 respectively with noise filters and interrupt controller ELECTRONICS 9 1 PORTS S3F84NB UM REV1 00 PORT DATA REGISTERS Table 9 2 gives you an overview of the register locations of all seven S3F84NB I O port data registers Data registers for ports 0 1 2 3 4 5 and 6 have the general format shown in Table 9 2 Table 9 2 Port Data Register Summary Register Name Decimar Hex Location Ww Pono data register Po 24 EH set RW Pontsdataregister Pe sett Bao RW 9 2 ELECTRONICS S3F84NB_UM_REV1 00 PORTS PORT 0 Port 0 is an 8 bit I O port that you can use two ways e General purpose digital I O e Alternative function PGOUT7 PGOUTO Port 0 is accessed directly by writing or reading the port 0 data register PO at location E0H in set 1 bank 0 Port 0 Control Register POCON Port 0 pins are configured individually by bit pair settings in the control register located in set 1 bank 0 POCON A reset clears the POCON registers to OOH configuring all pins to input modes When programming the port please remember that any alternative peripheral I O function you configure using the port 0 control registers must also be enabled in the associated peripheral module ELECTRONICS 9 3 PORTS S3F84NB UM REV1 00 Port 0 Control Register POCON EFH Set 1 Bank 0 R W IEAEREJEJEREJEREJES P0 7 P0 4 P0 3 P0
289. ull up Alternatively used as analog input pins for A D converter modules P2 0 P2 7 I O Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately P2 0 P2 7 can be used as I O for TIMER A TIMER B SIO and Buzzer output P3 0 P3 7 I O Bit programmable port input or output mode T1CKO selected by software input or push pull output T1CK1 Software assignable pull up T1CAPO Alternately P3 0 P3 7 can be used as I O for T1CAP1 TIMER C 0 1 TIMER 1 0 1 T1OUTO T1OUT1 TCOUTO TCOUT1 NOTE Pin numbers shown in parentheses are for the 64 pin QFP package 1 6 ELECTRONICS S3F84NB_UM_REV1 00 PRODUCT OVERVIEW Table 1 1 S3F84NB Pin Descriptions 64 SDIP Continued Pin Pin Pin Circuit Pin Share Name Type Description Type Number Pins 4 0 4 7 1 Bit programmable port input or output mode 42 35 INTO INT7 selected by software input or push pull output 35 28 Software assignable pull up 4 0 4 7 can alternately be used as inputs for external interrupts INTO INT7 respectively with noise filters and interrupt controller P5 0 P5 7 I O Bit programmable port input or output mode 26 24 selected by software input or push pull output 22 21 Software assignable pull up 15 13 Alternately 5 0 5 3 can be used as for 19 17 serial port UARTO UART1 respectively 15 14 8 6 P6 0 P6 7 P6 0 P6 1 are bit progr
290. upt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 3 P4 3 PND3 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 2 P4 2 PND2 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 1 P4 1 PND1 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 0 P4 0 PNDO Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending ELECTRONICS 4 2 J CONTROL REGISTERS S3F84NB_UM_REV1 00 P5CONH Port 5 Control Register High Byte F8H Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P5 7 oofa Fo t mumdepiip 1 O Push pulloutput 5 4 P5 6 o o mumm Fo r mummepdw Pio Push pullout 3 2 P5 5 0 o iromo o ooo rio Push pullout 1 0 P5 4 0 0 Inputmode j 0 1 Inputmode putue _ 3 O Pushpul ouput O 4 28 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER P5CONL Port 5 Control Register Low Byte F9H Set
291. ut flip flop T FF high LD P2CONH 03H Set P2 4 to TBPWM mode This command generates 38 kHz 1 3 duty pulse signal through P2 4 ELECTRONICS 11 9 8 BIT TIMER A B C 0 1 S3F84NB_UM_REV1 00 8 PROGRAMMING TIP generate one pulse signal through 2 4 This example sets Timer B to the one shot mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 40us width pulse The program parameters are CO c0 ot e Timer B is used in one shot mode e Oscillation frequency is 4 MHz fx 1 4 clock 1 us e TBDATAH 40 us 1 us 40 TBDATAL 1 e Set P2 4 to TBPWM mode ORG 0100H START DI LD TBDATAH 40 1 LD TBDATAL 1 LD TBCON 00010001B LD 2 03H PULSE_OUT LD TBCON 00000101B 11 10 Reset address Set 40 us Set any value except 00H Clock Source lt fxx 4 Disable Timer B interrupt Select one shot mode for Timer B Stop Timer B operation Set Timer B output flip flop T FF high Set P2 4 to TBPWM mode Start Timer B operation to make the pulse at this point After the instruction is executed 0 75 us is required before the falling edge of the pulse starts ELECTRONICS S3F84NB_UM_REV1 00 8 BIT TIMER A B C 0 1 8 BIT TIMER C 0 1 OVERVIEW The 8 bit timer C 0 1 is an 8 bit general purpose timer counter Timer C 0 1 has two operating modes you can select one of them using the appropriate TC
292. utput at TTOUTO T1OUT 1 pin e Capture input mode with a rising or falling edge trigger at the T1CAPO T1CAP1 pin e PWM mode T1PWMO T1PWM1 PWM output shares their output port with T1OUTO T1OUT 1 pin Timer 1 0 1 has the following functional components e Clock frequency divider fxx divided by 1024 256 64 8 1 with multiplexer e External clock input pin T1CKO T1CK1 e A 16 bit counter T1CNTHO LO T1CNTH1 L1 a 16 bit comparator and two 16 bit reference data register T1 DATAHO LO T1DATAH1 L1 e O pins for capture input T1TCAPO T1CAP1 or match output T1OUTO T1OUT1 e Timer 1 0 overflow interrupt IRQ3 vector and match capture interrupt IRQ3 vector C8H generation e Timer 1 1 overflow interrupt IRQ3 vector CEH and match capture interrupt IRQ3 vector CCH generation 0 control register T1T CONO set 1 EAH Bank 1 read write e Timer 1 1 control register TI CON1 set 1 Bank 1 read write e Timer 1 ELECTRONICS 12 1 16 BIT TIMER 1 0 1 S3F84NB_UM_REV1 00 FUNCTION DESCRIPTION Timer 1 0 1 Interrupts IRQ3 Vectors CEH CCH CAH and C8H The timer 1 0 module can generate two interrupts the timer 1 0 overflow interrupt T1OVFO and the timer 1 0 match capture interrupt T1INTO T1OVFO is interrupt level IRQ3 vector CAH T1INTO also belongs to interrupt level IRQ3 but is assigned the separate vector address C8H A timer 1 0 overflow interrupt pending condition is automat
293. val mode Timer 1 counter clear bit 1 Clear counter Auto clear bit 01 Capture mode capture on rising edge OVF can occur 10 Capture mode capture on falling edge OVF can occur 11 mode NOTE Interrupt pending bits are located TINTPND register Figure 12 1 Timer 1 0 1 Control Register TI CONO T1CON1 ELECTRONICS S3F84NB_UM_REV1 00 16 BIT TIMER 1 0 1 Timer A Timer 1 Pending Register TINTPND E7H Set 1 Bank 0 R W Not used Timer 1 1 overflow interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Timer 1 1 match capture interrupt pending bit 0 No interrupt pending 1 Interrrupt pending match capture pending bit interrupt 0 No interrupt pending 1 Interrrupt pending Timer A overflow pending int ferrupt 0 No interrupt pending 1 Interrrupt pending Timer 1 0 match capture interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Timer 1 0 overflow interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Figure 12 2 Timer A Timer 1 0 1 Pending Register TINTPND ELECTRONICS 16 BIT TIMER 1 0 1 BLOCK DIAGRAM T1CON 7 5 M U X 16 bit Comparator f xx 1024 gt f xx 256 gt fxx 64 8 gt 1 gt Data Bus 16 bit Up Counter TCK Read Only Vss gt v M TICAP U i T1CON 4 3 16 bit Timer Data Register T1DATAH L
294. x dst src opc dst 3 6 07 Rb ro NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Given R1 07H and register 01H 03H BOR R1 01H 1 gt R1 07H register 01H 03H BOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example destination working register R1 contains the value 07H 00000111B and source register 01H the value 03H 00000011B The statement BOR R1 01H 1 logically ORs bit one of register 01H source with bit zero of R1 destination This leaves the same value 07H in working register R1 In the second example destination register 01H contains the value 03H 0000001 1B and the source working register R1 the value 07H 00000111B The statement BOR 01H 2 R1 logically ORs bit two of register 01H destination with bit zero of R1 source This leaves the value 07H in register 01H ELECTRONICS S3F84NB_UM_REV1 00 INSTRUCTION SET BTJRF Bit Test Jump Relative on False BTJRF Operation Flags Format Example dst src b If src b is a 0 then PC PC dst The specified bit within the source operand is tested If it is a the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRF instruction is executed No flags are affected Bytes Cy
295. xed Register Addressing Mode Mode and Stack Operations Page 8 s Prime 05H 6 Bytes Peripheral Reigster ata Registers L_ OOH All Addressing Modes Figure 2 3 Internal Register File Organization 2 6 ELECTRONICS S3F84NB_UM_REV1 00 ADDRESS SPACES REGISTER PAGE POINTER PP The S3C8 series architecture supports the logical expansion of the physical 2 064 byte internal register file using an 8 bit data bus into as many as 16 separately addressable register pages Page addressing is controlled by the register page pointer PP DFH In the S3F84NB microcontroller a paged register file expansion is implemented for data registers and the register page pointer must be changed to address other pages After a reset the page pointer s source value lower nibble and the destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing Register Page Pointer PP DFH Set 1 R W e 7 s e us Destination register page selection bits Source register page selection bits Destination Page 0 0000 Source Page 0 Destination Page 8 1000 Source Page 8 NOTE A hardware reset operation writes the 4 bit destination and source values shown above to the register page pointer These values should be modified to address other pages Figure 2 4 Register Page Pointer PP PROGRAMMING TIP Using the Page Pointer for
296. y User Programming Enable Bits Pt Toft Enable userprogramming meds NOTES 1 To enable flash memory user programming write 10100101b to FMUSR 2 To disable flash memory operation write other value except 10100101b into FMUSR ELECTRONICS 4 1 _ CONTROL REGISTERS S3F84NB_UM_REV1 00 IMR Interrupt Mask Register DDH Set 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Enable Bit Disable mask Enable un mask EB 6 Inte rupt Level 6 IRQ6 Enable Bit Disable mask Enable un mask 5 Inte rupt Level 5 IRQ5 Enable Bit Disable mask e Enable un mask 4 Inte rupt Level 4 IRQ4 Enable Bit Disable mask Enable un mask Inte rupt Level 3 Enable Bit Disable mask fel Enable un mask 2 Inte rupt Level 2 IRQ2 Enable Bit Disable mask 1 Enable un mask 1 Inte rupt Level 1 IRQ1 Enable Bit Disable mask Enable un mask 0 Inte rupt Level 0 IRQO Enable Bit Disable mask e Enable un mask NOTE When an interrupt level is masked any interrupt requests that may be issued are not recognized by the CPU 4 12 ELECTRONICS S3F84NB_UM_REV1 00 CONTROL REGISTER IPH instruction Pointer High By
297. ycles Opcode Addr Mode Hex dst dst 2 8 50 R 51 IR Given Register 00H 01H register 01H 1BH SPH OD8H 00H SPL OD9H OFBH and stack register OFBH 55H POP 00H gt Register 55H SP 00FCH POP 00H gt Register 01H register 01H 55H SP 00FCH In the first example general register OOH contains the value 01H The statement POP OOH loads the contents of location OOFBH 55H into destination register OOH and then increments the stack pointer by one Register 00H then contains the value 55H and the SP points to location OOFCH ELECTRONICS 6 63 INSTRUCTION SET S3F84NB_UM_REV1 00 POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example dst src dst lt src IR IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 92 R IR Given Register 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H gt Register OOH 41H register 02H 6FH register 42H 6FH If general register OOH contains the value 42H and register 42H the value 6FH the statement POPUD 02H 00H loads the contents of register 42H into the destination register 0

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