Peripheral Driver Generator V.1.02 User`s Manual
Contents
1. Timer tune 5 pp I I I Boolean OpenSerialDriver async LUO p1 void Boolean CloseSerialDriver async LO pi void Boolean ConfigSerialDriverNotify async UO Boolean SetSerialFormat asvnc UO pl void Boolean SetSeriallnterrupt async UO pi void Boolean StartSerialReceiving async LIO pl Boolean StartSerialSending async LO pl u Boolean StopSerialReceiving async UO pl Boolean StopSerialSending async UO pi void Boolean PollingSerialReceiving asvnc UO pl OpentInitialize the appointed serial Close the appointed serial I F Register the appointed type of notif Change serial setting Set up serial interrupt Start receiving Start transmitting Stop receiving Stop transmitting Polling reception Related item Notification function name Bit number Clock selection Transmit interrupt Transmit lt Rnnlean PnllinnSeriallSendinm asvne IIN nif Pollinn transmission r trenesasIPDG nroiidefaulll Serial PollinnSeri Clock asynchronous SIO mode caf Ready Figure 1 5 Generated File Information Window 2 Changing Character Size 1 Right click on the generated file information window or select Display gt Character size of the generated file information window 2 Select a size from Large Medium and Small 3 The character size will be changed 1n the list REJ10J1769 0100 Rev 1 00 Nov 28 20072. su mammaa ux EESSuuuuusssssas se ZE 5 cru Hesar Ec yu Divide ratio of on chip oscillator QR Selection of on chip oscillator frequency ees CPU main clock divider selection Divided by 1 pito poz QM Selection of PLL multiplier 4 4 j 8E Periodic value 1 6 6 6 4 4644 Used Sub clock dividing ratio Divided by 2 Input frequency to sub clock oscillation circuit 0 032768 Main clock Used Input frequency to main clock oscillation circuit 20 000000 On chip oscillater clock Oo Penh PLL clock o 641 6g IR Input frequency to PLL circuit OO PE Onchip oscilator frequency 8E PLL frequency eo 6 6444 E CPU Serial Relatert Figure 4 5 Example of Displaying Project after Conversion REJ10J1769 0100 Rev 1 00 Nov 28 2007 LENESAS 4 4 Peripheral Driver Generator V 1 02 User s Manual Publication Date Nov 28 2007 Rev 1 00 Sales Strategic Planning Div Published by Renesas Technology Corp Microcomputer Tool Development Department Edited by Renesas Solutions Corp 2007 Renesas Technology Corp and Renesas Solutions Corp All rights reserved Printed in Japan Peripheral Driver Generator V 1 02 User s Manual LENESAS Renesas Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan REJ10J1769 0100
3. C C compiler package V 6 01 Release 01 for H8SX H8S H8 family 1 6 API Libraries The API libraries packaged in the PDG are listed below Table 1 4 List of API Libraries Library file name H8 Tiny lib h8_tiny rapi he 3687 lib rapi_h8_36049 lib rapi h8 36077 lib rapi he 36109 lib R8C Tiny lib r8c_tiny rapi rec 13 lib rapi rec 22 23 hib rapi rec 24 25 lib rapi rec 26 27 hib rapi rec 28 29 lib rapi rec 2A 2B lib rapi rec 2C 2D lib MI6C Tiny lib m16c_tiny rapi_m16c_28 lib rapi_m16c_29 lib M16C 60 lib m16c rapi_m16c_62p lib For reference the source files of the API libraries are stored in the source directory REJ10J1769 0100 Rev 1 00 Nov 28 2007 sZENESAS 1 3 Peripheral Driver Generator 1 7 Main Window 1 7 1 Setting Details Display Window This window displays the setting details of the currently opened project file Section 1 Overview The tabs at the bottom the trees in the left and the list in the right show functions created setup pattern and the details of the currently selected setting in the trees respectively Double clicking on Setting in the trees or any one of the setting items in the list shows a dialog box for specifying the corresponding setting 0 Peripheral Driver Generator default a File F Function U Displav v Tool T Win d ow iy Be Timer M16C 28 a Timer mode D GE a Help H Timer mode Event counter
4. Delete resource from the pop up menu 2 The selected resource is deleted REJ10J1769 0100 Rev 1 00 Nov 28 2007 LENESAS 3 11 Peripheral Driver Generator Section 3 How to Operate the PDG 3 6 Generating Sources Collectively You can generate source codes according to the function settings of the currently opened project Source codes can be generated when a resource 1s allocated to at least one of the created setup patterns 1 Select File Generate Sources Collectively from the menu 2 Source files are generated and stored in the same directory as the currently opened project At the same time information on those files is shown in the Generated File Information window 1 you create a setup pattern and check the Generate batch source check box in the peripheral I O function setting dialog box source files are generated automatically after the dialog box is closed To delete generated source files collectively select File gt Delete Sources Collectively from the menu 3 7 Viewing Generated Function Information in CSV Format Function information generated collectively by the PDG can be listed in CSV file format after source files are generated collectively 1 Select Tool gt Display output function list from the menu 2 A generated function list is displayed by the program associated with the csv file 3 8 Updating a Generated Function Information You can update function information
5. LEN ESAS Peripheral Driver Generator 1 8 The menu items are listed in table 1 5 Menu Section 1 Overview Table 1 5 Menu List Main menu Sub menu File F Open Project O Save Project S Save Project As A Convert Project C Generate Sources Collectively S Delete Sources Collectively D Exit X Function CPU C Modify setting M U Serial Newly Synchronous S S create setting N Asynchronous A Duplicate setting C Delete setting D Modify setting M Set UART number S Delete UART number L Newly Single shot Mode S REJ10J1769 0100 Rev 1 00 Nov 28 2007 create LENESAS Description Create New Project N Creates a new project Always available Opens an existing project Always available Saves the currently opened project Always available Saves the currently opened project under a new name Always available Converts an existing project into a new project with a different CPU Always available Generates source files Available when peripheral I O settings are completed Deletes all the generated files Available after source generation is performed Lists projects that were opened Always available Exits the PDG Always available Modifies settings for a CPU Only available when a project 1s opened Creates a new setup pattern of serial synchronous 5 Only available when a project is opened Creates a new setup pat
6. New Setup Pattern of Peripheral I O Modules 0 0 0 ccccccccsssssssssseeeeeceeeeeeeeeeeaaaeaescseseeeeeeeeees 3 8 3 4 2 Modifying a Setup Pattern of Peripheral I O Modules cccccssssssesseseeeceeeeeceeeeeeaaaaeeseseeseeeeeeeeeess 3 10 3 4 3 Duplicating a Setup Pattern of Peripheral I O Modules cc ccccssssssssseseeceeceeeeeceeeeeaeaeesseeeeeeeeeeeeeeees 3 10 3 4 4 Deleting a Setup Pattern of Peripheral I O Modules ccccccccssssssssssseeeececceceeeeeeeaaaeesenseseeeeeeeseeeees 3 11 3 5 Allocating and Deleting a RESOUICE versace cisndaresasantsnraretssnmunatiatastasehsiatWanntdatdenhedentinhedtanisiebWannkaeksloebstindsnsacadieebsiadwass 3 11 3 5 1 Allocating a RESOUTCE AAA nasser anoeie oaan aan EREE a EEr En Ees Eain EEEren ianed 3 11 3 3 2 D en AR oe a EE E eseede ean 3 11 3 6 Generating Sources Collectively sssrinin anke uesto ka dive aa a aa Riia 3 12 3 7 Viewing Generated Function Information in CSV Format cccccccccssssssssssssseseeeeceeeeeeeeeeaeaaeeeesseseeeeeeeeeeeeees 3 12 3 8 Updating a Generated Function Information sss cade So cop A sabe E LEO OS kak 3 12 REJ10J1769 0100 Rev 1 00 Nov 28 2007 stENESAS i Peripheral Driver Generator 3 9 Registering Generated Files in a HEW Project ssssssssssssssssssssseeeenenknnnkknnnnnnnnneeeeeenIIIntIIIKkktees 3 12 3 9 1 Registranon PIC ON TTT oatiede AA a ta sagaaschnsen a aoeuneonatacdl aa aeaiiai 3 12 3892 How to Asse rod Soile ISU TET TT
7. UNREGISTE unregtools wc6 re200l dill Figure 2 12 Example of the Directory where the HEW is Installed REJ10J1769 0100 Rev 1 00 Nov 28 2007 z ZENESAS 2 6 Peripheral Driver Generator Section 3 How to Operate the PDG oF How to Operate the PDG 3 1 Developing an Application with the PDG The PDG generates C source files that contain functions reflecting settings for peripheral I O modules An application that operates peripheral I O modules can be developed by calling functions generated by the PDG The following gives an overview of the application development with the PDG 1 Creating a workspace for the application development in the HEW You will create a workspace for the application to be developed by selecting a menu item such as Create a new project workspace in the HEW 2 Creating a PDG project for driver development You will select a microcomputer and create a project in the PDG 3 Setting peripheral I O modules You will set peripheral I O modules in the created project in the PDG beginning with CPU settings 4 Generating and registering sources in the workspace After setting the peripheral I O modules you will generate source files collectively in the PDG and then register them in the created HEW workspace from the PDG 5 Creating the application You will call the functions which are written in the source files generated by the PDG and which operate the peripheral I O modules in the right pl
8. V I Tooth indos HelpiH a ss Ia e 1 uxEBESBEZEZEOAU ssusssas se cru nursso CET Nu i Divide ratio of on chip oscillator Qi Selection of on chip oscillator frequency a CPU main clack divider selection Divided by 1 Pin Sale QE Selection of PLL multiplier 6446 4 QM Periodic value 4071 6 4g4g06 6 44 PGP Subclock SSCs Sub clock dividing ratio livid by 2 SP Input frequency to sub clock oscillation circuit 0 032768 Used Input frequency to main clock oscillation circuit 20 000000 B On chip oscillater clock o I PLL clock 4 4 1 1 14 J Input frequency to PLL circuit 4 iS iS iS iS Tiner PoE PLL frequency OO O E P Sub clock frequency COB On chip oscillator frequency ae E P CPU Interrupt Relater No source is generated yet The generated sour 1 Setting lt Timer mode Ready CAP 2 Figure 4 4 Example of Displaying Project after Conversion 7 indicates that the corresponding item requires to be modified or checked because of the difference of the CPU specification or other reasons Modify the setup pattern if necessary REJ10J1769 0100 Rev 1 00 Nov 28 2007 sZENESAS 4 3 Peripheral Driver Generator Section 4 Converting a Project 8 After necessary modification is made P becomes J E T AQ Peripheral Driver Generator H83687 Sel a File F Function Displayiv Tool T vindowoj HelptH _ o x
9. document or Renesas products 7 With the exception of products specified by Renesas as suitable for automobile applications Renesas products are not designed manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth above 8 Notwithstanding the preceding paragraph you should not use Renesas products for the purposes listed below 1 artificial life support devices or systems 2 surgical implantations 3 healthcare intervention e g excision administration of medication etc 4 any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp its affiliated companies and their officers directors and employees against any and all damages arising out of such applica
10. frequency to main cloc 20 000000 jaj On chip oscillater clock PS oaaae ce Input frequency to PLL circuit 2G On chip oscillator frequency i x PLL frequency Sub clock frequency 0 016384 A D CPU Serial Timer Interrupt Related item c lrenesas PDG_projidefault Serial _ OpenSeri Boolean OpenSerialDriver async UO pi void Open Initialize the appointed serial cilrenesas PDG_projidefault Serial _ CloseSeri Boolean CloseSerialDriver async UO pi void Close the appointed serial I F c lrenesas PDG_projidefault Serial _ ConfigSer Boolean ConfigSerialDriverNotify async UO Register the appointed type of notif Notification function name c renesas PDG_proj default Serial _ SetSerialF Boolean SetSerialFormat async UO pi void Change serial setting Bit number Clock selection Sto cikrenesas PDG projtdefaultiSeriali SetSeriall Boolean SetSeriallnterrupt asvnc UO pilfvoid Set up serial interrupt Transmit interrupt Transmit inte c lrenesas PDG_projidefault Serial _ StartSeria Boolean StartSerialReceiving async UO pi Start receiving Mi Iii Clock asynchronous SIO mode Ready Timer LO AD Others Serial Figure 3 4 Existing Project REJ10J1769 0100 Rev 1 00 Nov 28 2007 z ZENESAS 3 6 Peripheral Driver Generator Section 3 How to Operate the PDG 3 3 3 Setting CPU Clocks After a new project 1s created the CPU clock setting dialog box opens automatical
11. generated collectively by the PDG after source files are generated collectively 1 Select Tool gt Place output function list in the latest status 2 The CSV file of the generated function list is updated The CSV file is updated when sources are generated collectively Note that when sources are generated while the CSV file is opened it may not be updated In this case close the CSV file and follow the steps above 3 9 Registering Generated Files 1n a HEW Project 3 9 1 Registration Function You can register all source files generated by the PDG collectively in an existing HEW project automatically At the same time API libraries used in the source files are registered in library options and the intprg c file is excluded from the build target when it is already registered in the HEW project so that no collision between interrupt functions occurs When the already registered intprg c file contained user codes it is required that the user codes be manually copied into the newly registered intprg c REJ10J1769 0100 Rev 1 00 Nov 28 2007 s2ENGSAS 3 12 Peripheral Driver Generator Section 3 How to Operate the PDG 5 9 2 How to Register Generated Files Generated files can be registered by the steps below when the sources has already been generated 1 Select Tool gt Register file in HEW project from the menu 2 When the HEW is not launched the message dialog box appears asking whether to launch it or not
12. mode Only available when a project is opened Creates a new setup pattern of event counter mode Only available when a project is opened REJ10J1769 0100 Rev 1 00 Nov 28 2007 sZENESAS 1 8 Peripheral Driver Generator Section 1 Overview Main menu Sub menu Description Pulse Width Creates a new setup pattern of pulse width modulation mode Modulation Mode M Only available when a project is opened Pulse Period Creates a new setup pattern of pulse period measurement mode Measurement Mode P Pulse Width Creates a new setup pattern of pulse width measurement mode Only available when a project is opened Measurement Mode Only available when a project is opened W Input Capture Mode Creates a new setup pattern of input capture mode 1 Only available when a project is opened Output Compare Creates a new setup pattern of output compare mode Mode O Only available when a project is opened Duplicate setting C Duplicates a setup pattern of a timer Only available when timer setting is selected Delete setting D Deletes a setup pattern of a timer Only available when timer setting is selected Modify setting M Modifies timer settings Only available when timer setting is selected Set timer T Sets a timer type for a setup pattern of a timer Only available when timer setting is selected Delete timer L Deletes a timer type from a setup pattern of a timer Only av
13. mode Pulse width modulation mode Pulse period measurement mode B I 0 Interrupt A D ti Setting 2 Timer type Al prej Timer setting value 393 keo Event counter mode Ta Setting E qe Timer type A R Timer setting value 12 D Pulse width modulation mode tu Setting 2 Timer type Al Timer setting value high order bit Timer setting value low order bit Pulse period measurement mode Setting 2 Timer type BO Pulse width measurement mode Settinal 2 Timer type BO H Input capture mode E Ta Setting Be Timer tune S sas ET E Ko CPU Serial Timer Period C fl 20 000000 Operation During initialization Operation start Underflow interruption Underflow interruption disa Underflow interruption function name Underflow interruption priority level 0 Overflow interruption Overflow interruption function name SS Overflow interruption priority level Timer output Pulse is output Clock output function Auto reload function Control to write to timer e 2 Gate function Count Source Frequency Do not use gate function 20 000000 e c renesas PDG_projidefault Serial _ OpenSeri Boolean OpensSerialDriver async UO pi void OpentInitialize the appointed serial c renesas PDG_proj default Seriall__CloseSeri Boolean CloseSerialDriver_async_UO_pi voi
14. schematically shows the relationship between the PDG and the API libraries and applications User system Project T ENG Code generator Call library gt Call library API API libraries libraries Generates functions DLLs for each microcomputer Compile Link Figure 1 2 Roles of the PDG 1 4 Operating Environment The PDG has been confirmed to be capable of operating properly on the host machines under the OS versions listed below Table 1 1 Host Machine Host machine OS version IBM PC AT and its Microsoft Windows 2000 compatibles Microsoft Windows XP If the PDG is to be run on any other host machine or under other OS that you are using please consult the manufacturer of your host machine or OS to confirm whether the PDG will operate properly on it REJ10J1769 0100 Rev 1 00 Nov 28 2007 sZENESAS Peripheral Driver Generator Section 1 Overview The recommended hardware specifications are listed below Table 1 2 Recommended Hardware Specifications Main memory Sufficient memory capacity for the OS to operate normally is recommended 256 Mbytes or more Free disk space 70 Mbytes or more Resolution of display 1024 x 768 or greater is recommended 1 5 Compiler Combinations The PDG operates normally in combination with the compilers listed below Table 1 3 Compiler Package PDG Compiler products V1 02 C compiler package M3T NC30WA V 5 40 Release 00 for M16C series
15. the converted project they are modified according to the CPU model of the converted project For information on the modification of the settings refer to the next section Common I F Tiny API Serial driver B Serial driver C Created by PDG Figure 4 1 Project Conversion Overview 4 2 Modifying and Displaying the Settings through Project Conversion 1 Settings are modified in the following two methods 1 Setting values are modified or new setting values are set e When the original setting values cannot be used 1n the converted project e When items are invalid in the original while new setting values are required in the converted project ui Setting items themselves are disabled e When the converted project CPU model does not support the setting items 2 Resource settings All resource settings are deleted 3 Displaying Project Conversion Results Conversion results are displayed using the icons listed in table 4 1 Table 4 1 Displaying Conversion Results The original setting values are used The program modified the setting values 1 for 1 The item itself was disabled through the conversion ii for 1 The original setting values are used The item itself is invalid both in the original and converted project REJ10J1769 0100 Rev 1 00 Nov 28 2007 stENESAS 4 1 Peripheral Driver Generator Section 4 Converting a Project 4 3 How to Convert a Project 1 Select File gt Project Convert fro
16. 2007 sZENESAS 1 12 Peripheral Driver Generator Section 2 Preparation for Using the PDG 2 Preparation for Using the PDG You will install the PDG and specify an editor to be used via the PDG and other settings necessary for the PDG to collaborate with the HEW Note that screen Images of the HEW may differ depending on the version you are using 2 1 Installing the PDG After the installer launches follow the instructions to install the PDG with administrator right Peripheral Driver Generator InstallShield Wizard Welcome to the InstallShield Wizard for Penpheral Driver Generator The InstallShield Wizard will install Peripheral Driver Generator on your computer To continue click Next Cancel Figure 2 1 Installer after Launched 22 Setting an Editor Any editor can be used to open generated source files in a project on the generated file information window 1 Select Tool gt Setting from the menu to open the Setting dialog box 2 Specify the name of the editor program that you wish to use when opening source files 3 Specify the parameters of the program according to its specifications Replace file names and line numbers in the parameters with F and L respectively 1f necessary Click OK to close the dialog box and complete the settings Setting Joko When the parameter is lt file name gt Editor CAProgram Files MIAMI EXE Ref line number enter F L i AA
17. 3UO Sta 6 2 0 C Program Files Renesas Hew s T ool H Series Libraria C Program Files Aenesas Hew s Tool H Series Libraria C Program Fless enesasvH z odl sa jiii Search statue 5 files found Figure 2 11 Search Disk for Components Dialog Box 6 Click on the close button to close the Search Disk for Components dialog box 7 Click OK to close the Tools Administration dialog box 8 Execute REGISTERSERVER bat in the directory where the HEW is installed By default the directory is as follows c Program Files Renesas Hew REGISTERSERVER bat File Edit view Favorites Tools Help C Program Files Renesas Hew SEE Luj Q Back Dd wi p Search Key Folders ii s O C Program Files Renesas Hew v Go AppExtRes dll AUM bugtrack hdb BugTracker dl C source CC head Conspawn A File and Folder Tasks Other Places 2 2 Context Csh dll Csourcefile shl Default shl DefaultSynt DefaultWin editordefaul Details REGISTERSERYER 2 O kJ E MS DOS Batch File GenericSeri Hew2 HEW2 hewdbvi dl HewTarget hewtools Adb HimToHew Date Modified Thursday October 24 2002 1 27 PM saree z a a a a hmake InstalCustG OEG1as dl OE611las dl OEZDiasdl OTZilas dl OTPZias dll OTP8O01as dil PDREGISTE PdTargets PDUNREGIS pretools hdb ReadMe README E jJ a 4 4 1 3 a objs hdb ResPg dl RWUXThem sflil4as dll sfli1as dll sfl201as dll a as TEMPLATE toolsdb hdb
18. CTS ATS func LSB first MSB first selection LSB first Parity bit Parity disable o Stop bit One stop bit Internal clock 8 BRG count source A e Notification function name Transmit interrupt Transmit interrput inhibit LE Transmit interrupt level Timer type IEN Operation during initialization Operation start Frequency of count source 20 000000 MHz Interruption Enable Underflow interruption cilrenesasiPDG pl Count source in 7 tern pi Clock asynchronous Period 0 000000 micro sec Interuntion function name Result of calculation Timer output The values in this frame are set Period 0 000000 micro sec Error 0 000000 sy lu Gate function Do not use gate function start AJ Peripheral Driver Gen Figure 1 1 Example of PDG Display 4 Supports conversion of the contents set by GUI for diverted use between microcomputers 1 2 PDG Project The PDG manages the generated software based on the concept of project Following are managed as project 1 Setup information on each peripheral IO 2 Function management information on set content REJ10J1769 0100 Rev 1 00 Nov 28 2007 LEN ESAS 1 1 Peripheral Driver Generator Section 1 Overview 1 3 Roles of the PDG The user incorporates functions for calling API libraries which are generated by the PDG into a user program to create an application The following
19. Click Yes Figure 3 10 Message Asking whether to Launch the HEW PDG 3 The message dialog box appears asking whether to register the files or not When the work space is being opened with HEW the source file thus generated le registered in the active project When rio work space is opened with HEV the generated source file ts registered in the active project after the work space was selected When several work spaces are being opened note that a file ig registered in all work spaces Do you really want to start source file registration Tes r Figure 3 11 Message Asking whether to Register the Files PDG e When a HEW workspace in which the files are to be registered has already been opened 4 Click Yes e When a HEW workspace in which the files are to be registered is an existing workspace 4 Click Yes to open the Open File dialog box Specify a HEW workspace in which the files are to be registered Click Open to open the workspace e When a HEW workspace in which the files are to be registered is not created 4 Do not close the dialog box In the HEW create a new HEW workspace and leave the workspace open In the message dialog box of the PDG click Yes REJ10J1769 0100 Rev 1 00 Nov 28 2007 RENESAS 3 13 Peripheral Driver Generator Section 3 How to Operate the PDG 5 The Library link priority setup dialog box appears Move the libraries up and down according to their pri
20. F21256 R5F21257 R5F21258 R5F21262 R5F21264 R5F21265 R5F21266 R5F21272 R5F21274 R5F21275 R5F21276 R8C 28 R5F21282 R5F21284 R8C 29 R5F21292 R5F21294 R8C 2A R5F212A7 R5F212A8 RSF212AA R5F212AC R5F212B7 R5F212B8 RSF212BA R5F212BC R5F212C7 R5F212C8 RS5F212CA R5F212CC R5F212D7 R5F212D8 R5F212DA R5F212DC M16C 60 M16C 62P M30622F8PFP M30622F8PGP M30623F8PGP M30620FCPFP M30620FCPGP M30621FCPGP M3062LFGPFP M3062LFGPGP M30625FGPGP M30626FHPFP M30626FHPGP M30627FHPGP M30626FJPFP M30626FHPGP M30627FJPGP 4 Click OK to create a new project REJ10J1769 0100 Rev 1 00 Nov 28 2007 s2ENGSAS 3 4 Peripheral Driver Generator Section 3 How to Operate the PDG 5 Immediately after the creation of a new project the CPU clock setting dialog box opens automatically Proceed to setting CPU clocks a Peripheral Driver Generator default EJ File F Function U Display Tool T Window W li Il q CPU clock setting psu memm System clock selection System clock frequency Main clock IV Use as peripheral function clock source Input frequency to main clock circuit 20 000000 MHz On chip oscillator clock s 2x Be88e88 4 lxi CPU M16728 CPU setting T Use as peripheral function clock source Frequency selection Periodic value Divider selection On chip oscillator frequency 0 000000 MHz Pll clack Use as peripheral function clock source Input freq
21. Function Displayviv ToolfT o vi osuEmBo Clock synchronous SIO mode Clock asynchronous SIO mode TO Tan E Santer md Figure 3 6 New Setup Pattern Creation Window 2 After setting functions of each peripheral I O modules see figure 3 7 clicking on the Setting button lists the setting details setup pattern in the right of the main window see figure 3 8 REJ10J1769 0100 Rev 1 00 Nov 28 2007 LENESAS 3 8 Peripheral Driver Generator Section 3 How to Operate the PDG Clock asynchronous 5IO mode setting Serial port Yo settir BAG register BAG register setting value Bit number BAG count source i Stop bit One stop bit Baud rate J600 pps Set details Parity bit Party disable a Clock selector intemal clock Interrupt enable Permit transmit interruption Clock polarity selection E E saloj Transit interruption level LSE first ET MSE first selection L Permit receive interruption Reverse data logic Do Hot reverze Receive mteruption level CTS ATS function Do not use CTS ATS function Permit 51 0 interruption Noise canceller NE s1 d interruption level Notification function name Tranemit Aeceiwe pins select p Clock pin select E Generate batch source M Seting Cancel Figure 3 7 Clock asynchronous SIO mode setting Dialog Box AC Peripheral Driver Generator default a File F Function U Display T
22. Peripheral I O Modules Modify an existing setup pattern through the following steps 1 Double click on Setting on the trees in the left of the main window or double click on the name of the setting item on the list in the right Or select Function gt CPU Serial A D I O Timer or INT gt Modify setting 2 The dialog box corresponding to the selected peripheral I O module opens Modify the settings 3 Click on the Setting button to close the dialog box The list in the right of the main window reflects the modification to the settings Clock asynchronous SIO mode setting Serial port BRAG register BAG register setting value 129 Bit number a bit l BAG count source l Stop bit One stop bit a Baud rate J600 bos Set details Parity bit Parity disable xe Clack selection Internal clock Interrupt enable Permit transmit interruption LSB first l ET MSB first selection re Permit receive interruption Reverse data logic Do nol reverse CTS ATS function Da not use CTS ATS function Zi Notification function name Clock pin select Setting Cancel Figure 3 9 Clock asynchronous SIO mode setting Dialog Box 3 4 3 Duplicating a Setup Pattern of Peripheral I O Modules You can duplicate an existing setup pattern When a resource is allocated to a setting to be duplicated the resource setting is also duplicated A setup pattern can be duplicated only w
23. Setting is selected on the trees in the left of the main window 1 Select Setting except for CPU clock on the trees in the left of the main window and then select Function gt Serial A D I O Timer or INT gt UART number setting Input group pin setting Port setting Timer setting or Interrupt setting from the menu or right click on Setting on the trees in the left of the main window and then select Resource setting from the pop up menu 2 Select a resource that you wish to allocate to the selected setup pattern in the Resource setting dialog box 3 After clicking on OK closes the dialog box the resource is allocated to the selected setup pattern At the same time a message appears if allocating the resource disables some items Also note that after the resource is allocated settings that require to be modified are marked with icons in the setting list J92 Deleting a Resource You can delete a resource allocated in Resource setting An allocated resource can be deleted only when it is selected on the trees in the left of the main window 1 Select lt resource name gt on the trees in the left of the main window and then select Function gt Serial A D T O Timer or INT gt Delete UART number Delete input group input pin Delete port Delete timer or Delete interrupt from the menu or right click on lt resource name gt on the trees in the left of the main window and then select
24. T TTT TTTTTTETTTTTTTI 3 13 3 9 3 Canceling Registration of Piles sao LE ED A 3 14 Be A onyono EO UP TTE 4 1 4 1 Project Conversion I UNUO asia on dego ncanacsveaiteaaneasiaignnenbsetantanaasmvast ennea SNEEN EA EEEREN EN EAEE ENEE ESENES EN aE 4 1 4 2 Modifying and Displaying the Settings through Project ConverslOn ssssssssssssssssss sseseeeennnnnnnnsss 4 1 4 3 Hor oC Con a a ikoj SO eee E E E E TE E ene TE 4 2 REJ10J1769 0100 Rev 1 00 Nov 28 2007 stENESAS iv Peripheral Driver Generator Section 1 Overview l Overview 1 1 PDG Features The PDG allows users to specify settings of microcomputer peripheral I O modules such as serial timer and IO via its GUI and to generate functions which reflect the settings for calling API libraries for those modules 1 Assists in setting up each peripheral IO via GUI 2 Outputs the set contents as functions 3 Registers automatically generated sources collectively into a project of the High performance Embedded Workshop hereafter referred to as HEW Peripheral Driver Generator default E i etF Functlon L Display V Tool T j EEA IE Serial M16C 28 Clock synchronous SIO m Bit number a bit Clock asynchronous SID i o BRG register setting value E 129 Ek onal Clock polarity selection hs UARTO i Reverse data logic EA NINN 8 CTS ATS function Do not use
25. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website hitp www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to hitp www renesas com inquiry LENESAS 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted
26. When the parameter is line lt line number gt lt file name gt enter Figure 2 2 Setting Dialog Box REJ10J1769 0100 Rev 1 00 Nov 28 2007 stENGSAS 2 1 Peripheral Driver Generator Section 2 Preparation for Using the PDG 2 3 Registering the PDG in the HEW You will register the PDG in the HEW menu so that the PDG can launch from it 1 Launch the HEW If it has already launched close all the workspaces 2 Click Administration in the Welcome dialog box Welcome a Ed Options Create a new project workspace ance C Administration gt Figure 2 3 Welcome Dialog Box in the HEW 3 If the HEW has already launched select Administration from the tool menu 53 High performance Embedded Workshop BEAR Fie Edit View Project Build Debug Setup Tools indow Test ufindow Help psuo a TO Sesa aae Change Toolchain Version version Control ar Launch External Debugger i i Launch Slave HEW Macros Record Macro D Play Macro D Stop Macro Hitachi Call Walker Renesas H Series Librarian Interface Renesas Call Walker Renesas Mapview zoron as at i ar o Bm E EENS EA EECI Figure 2 4 HEW Tool Menu REJ10J1769 0100 Rev 1 00 Nov 28 2007 2ENESAS po Peripheral Driver Generator Section 2 Preparation for Using the PDG 4 Click on the Register button Tools Administration Registered compo
27. aces of the application Note that when the operation functions are called the header files generated by the PDG must be included in advance 6 Build You will build the application in the HEW Note that before performing a build the following settings are required and that the HEW V 4 02 or later automatically specifies library files e Specifying the directory path to the header files generated by the PDG I option e Specifying library files to link API libraries L option If build errors occur in the operation functions generated by the PDG make sure that the functions are called 7 Debug You will debug the application built with the HEW 8 Evaluation You will evaluate the application to make sure that it functions as expected REJ10J1769 0100 Rev 1 00 Nov 28 2007 s2ENGSAS 3 1 Peripheral Driver Generator Section 3 How to Operate the PDG a2 PDG Operation Flow This section explains how to operate the PDG You will begin with settings for determining how to use peripheral I O module functions and then generate and use source files to develop drivers as follows Creating opening a project Setting CPU clocks Selecting peripheral I O modules functions Setting the selected peripheral I O modules functions Generating source files collectively Outputting source files according to the peripheral I O modules functions Registering the generated source files in the HEW project Figure 3 1 PDG Op
28. ailable when a timer is selected INT N Newly create setting N Creates a new setup pattern of external interrupt Only available when a project is opened Duplicate setting C Duplicates a setup pattern of external interrupt Only available when external interrupt setting is selected Delete setting D Deletes a setup pattern of external interrupt Only available when external interrupt setting is selected Modify setting M Modifies settings for external interrupt setting Only available when external interrupt setting is selected Set interrupt I Sets an interrupt type for a setup pattern of external interrupt Only available when external interrupt setting is selected Delete interrupt L Deletes an interrupt type from a setup pattern of external interrupt Only available when external interrupt type is selected Display CV Character size of the generated file information Changes the character size of the generated file information window window C Selectable from large medium or small REJ10J1769 0100 Rev 1 00 Nov 28 2007 sZENESAS 1 9 Peripheral Driver Generator Section 1 Overview Tool T Display output function list D Lists output functions in CSV file format Place output function in the latest status P Updates the output function list Window Unsupported in version 1 02 W Help H About Peripheral Driver Generator A Shows the version information of the PDG Setup pat
29. ain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronic
30. at sweep mode 0 Only available when a project is opened Creates a new setup pattern of A D repeat sweep mode 1 Only available when a project is opened Creates a new setup pattern of A D simultaneous sampling sweep mode x Only available when a project is opened Creates a new setup pattern of A D delay trigger mode 0 Only available when a project is opened Creates a new setup pattern of A D delay trigger mode 1 Only available when a project is opened Duplicates a setup pattern of A D Only available when A D setting is selected Deletes a setup pattern of A D Only available when A D setting is selected Modifies A D settings Only available when A D setting is selected Sets an input group and pin for a setup pattern of A D Only available when A D setting is selected Deletes an input group and pin from a setup pattern of A D Only available when an input group and pin are selected Creates a new setup pattern of I O Only available when a project is opened Duplicates a setup pattern of I O Only available when I O setting is selected Deletes a setup pattern of I O Only available when I O setting is selected Modifies I O settings Only available when I O setting is selected Sets a port for a setup pattern of I O Only available when I O setting is selected Deletes a port from a setup pattern of I O Only available when a port is selected Creates a new setup pattern of timer
31. ation Dialog Box 7 Click OK to close the Tools Administration dialog box 2 4 Setting HewTargetServer In order to register sources generated by the PDG in the HEW HewTargetServer in the HEW requires to be set properly Set HewTargetServer as follows 1 Select Administration from the tool menu 2 Make sure that the HewTargetServer version is 1 05 00 in Extension Components When earlier version than 1 05 00 is shown select HewTargetServer and click Unregister to unregister it Tools Administration Registered components Toolchains System Tools l Utility Phases Register Debugger Components 4 Extension Components Z 7A Cancel v ace ECs Properties E 1 04 00 omna Eri EEHS Search disk Help System Tools Tool information 4 Uninstaller Show all components Current HE tools database location C Program Filess enezassHew PNE KUJ e Figure 2 8 Tools Administration Dialog Box REJ10J1769 0100 Rev 1 00 Nov 28 2007 2ENESAS 2 4 Peripheral Driver Generator Section 2 Preparation for Using the PDG 3 Click on the Search disk button in the Tools Administration dialog box Tools Administration Registered components o 3 LIE Component Version Cancel Toolchains System Tools Utility Phases Register Debugger Components Extension Components Unregister Communication Tools p an Help System Tools LIGREIMES E
32. cccccccccccceessssesseeeeeceeeeeeeeeeeaaaaessseeeeeeeeeeeeeeeeesaaaaaasssseeseseeeeess 1 5 1 8 DM essay tg cscs es eta op aces A N ee se ee eae A ine E E O T A eae tree A E l 7 1 9 TOOD e EE E E E A E A A A E O 1 10 1 10 Support Range of Peripheral I O Module FUunctions cccccccccccccccccecceessssssseseeececeeeeeeeeeeeeeeaasaassssseeseeeeeess l 12 IN LOA T E E R l 12 1102 A D CONVESSO sesoses AE EER EENE E EEEIEE ENEE ERRERA 1 12 Preparation for Usine the PDG srania ENE 2 1 2i MS et Tis GIS a a E E E E AE E E E T E E A T A A E EET 2 1 22 PO GUM Ze E O a R E E E R E E E E E ET 2 1 Zo Resisteriri the PDG in the HEW seso E SEE KV Va KS KPE da VK rr 22 2 4 Be Fl MyM A801 T E A E T E E E TTT A 2 4 How to Operate he PDU siirinsesi AAEE osa kiea cebreevata 3 1 3 1 Developing an Application with the PDG sssssensssssssoeeeeeeessssssssssssssesteeressssssssssssssrereresererssssssssssssseresssssssssseses 3 1 o 2 TOGOPO O a E E EEE E KA e E a 3 2 3 3 Creating Opening a gre so TTTTTTTTTTTTTTETTTTTTTTETTTTTTREETTTTTTTTETTTT TTT 3 3 3 3 1 Creating a New ui KO TTTTTTTTTTTTTTTTTTTTTTTTTTTTT TRETT TETTETTTTTTTTET 3 3 2 KJPENMINO UTE KISTO RO cc Ene nen oE OO E o E E TI A EN ere 3 6 3 3 3 Si mio CTO CRS RTTTTTTTTTTTTTTTTTTTT7TFFFTFT F P FTT1TT TUTP TErTFTTETFTP T7TTTI7TEr 3 7 3 4 Selecting Setting Peripheral I O Modulles ccccccccccccccsnssssssssssseeececeeeeeeeeeeaaeessseeeeeeeceeeseseeeseaeasasuseseeeeeeeees 3 8 3 4 1 Creating a
33. cts may not be easily detached from your products Renesas shall have no liability for damages arising out of such detachment 12 This document may not be reproduced or duplicated in any form in whole or in part without prior written approval from Renesas 13 Please contact a Renesas sales office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries For inquiries about the contents of this document or product fill in the text file the installer generates in the following directory and email to your local distributor SUPPORT Product name SUPPORT TXT Renesas Tools Homepage http www renesas com en tools Peripheral Driver Generator Preface The Peripheral Driver Generator hereafter referred to as PDG is a tool that supports the development of a driver for a peripheral I O module in a microcomputer The PDG which contains peripheral I O module API libraries allows users to design and automatically generate functions for calling the libraries via its user interface It runs on a Microsoft Windows operating system with an IBM PC compatible machine The supported microcomputers are the H8 Tiny R8C Tiny and M16C Tiny series and main groups of the M16C 60 series For details refer to Overview in this manual Usage Precautions Even though we carefully evaluate the API libraries and functions generated by the PDG fully exami
34. d Close the appointed serial I F c Wrenesas1PDG projtdefaultiSeriali ConfigSer Boolean ConfigSerialDriverNotify async UO Register the appointed type of notif c trenesas1PDG projtdefaultiSeriali SetSerialF Boolean SetSerialFormat async UO plf void Change serial setting c renesas PDG_projidefault Serial _ SetSeriall Boolean SetSerialinterrupt async LUO pifvoid Set up serial interrupt cilrenesas PDG_projidefault Serial _ StartSeria Boolean StartSerialReceiving async LO pl Start receiving a ci renesas PDG_proj default Serial _ StartSeria Boolean _ StartSerialSending_async_UO_pifu Start transmitting cilrenesas PDG_proj default Serial _ StopSerial cilrenesas PDG_proj default Serial _ StopSerial ci renesas PDG_proj default Serial __PollingSeri PallinnSeri r trenesasIPDG nrniidefanlhi Seriali Boolean StopSerialReceiving async LO pl Boolean StopSerialSending async UO pi void Boolean PollingSerialReceiving async UO pl PallinnSerialSendinn asvne IIO nif Rinnleari Stop receiving Stop transmitting Polling reception Polling transmissinn Related item Notification Function name Bit number Clock selection Transmit interrupt Transmit lt lt I Clock asynchronous SIO mode Ready kapl Figure 1 3 Setting Details Display Window REJ10J1769 0100 Rev 1 00 Nov 28 2007 2E NESAS 1 4 Peripheral Driver Generator Section 1 Overview 1 7 2 New Setup Pattern C
35. default Serial _ PollingSeri Boolean PollingSerialReceiving async LUO pl Polling reception ritrenesasIPDG noroiidefalt Serial PollingSeri Ranlean PollinnSerialSending asvne IIO nif Pollinn transmission m gt Clock asynchronous SIO mode Ready CAP Figure 1 4 New Setup Pattern Creation Window 1 7 3 Generated Hile Information Window 1 Displayed contents The generated file information on each function and each mode in the currently opened project file 1s displayed The following are listed as the generated source information Generated file name Generated function name Functional description of function Related item name Double clicking on a generated file name opens the corresponding file by using a specified editor REJ10J1769 0100 Rev 1 00 Nov 28 2007 2ENESAS 1 5 Peripheral Driver Generator Section 1 Overview 0 Peripheral Driver Generator default a Fie F Function U Displav v Tool T rdo Help H oF X BiEs Nee TroNK JN ie E Ta Setting Timer output Pulse is output Event counter mode 8 Timer type A1 af Clock output function Timer setting value high order bit Auto reload function Timer setting value low order bit Control to write to timer Pul iod measurement mode i Egga Pulse perio Gate function Do not use gate function paso ea ca My Setting Count Source Frequency 20 000000 2 Timer type BO EI Pulse width measurement m
36. eat sweep When a project is opened setup creation New A D repeat sweep mode REJ10J1769 0100 Rev 1 00 Nov 28 2007 LENESAS 1 10 Section 1 Overview Peripheral Driver Generator O setup creation mode o d New A D repeat sweep mode Creates a new setup pattern of A D repeat sweep When a project is opened uu 1 setup creation lll mode 1 New A D simultaneous Creates a new setup pattern of A D simultaneous When a project is opened sampling sweep mode setup sampling sweep mode creation New A D delay trigger mode Creates a new setup pattern of A D delay trigger When a project is opened O setup creation New A D delay trigger mode Creates a new setup pattern of A D delay trigger When a project 1s opened 1 setup creation New I O setup creation New timer mode setup When a project is opened creation New timer event count mode When a project is opened setup creation New timer pulse width modulation mode setup creation New timer pulse period measurement mode setup creation New timer pulse width Creates a new setup pattern of timer pulse width modulation mode Creates a new setup pattern of timer pulse period measurement mode Creates a new setup pattern of timer pulse width When a project is opened When a project is opened When a project is opened measurement mode setup measurement mode creation New timer input capture When a project is opened mode setup creation New timer outpu
37. eration Flow REJ10J1769 0100 Rev 1 00 Nov 28 2007 s2ENGSAS 3 2 Peripheral Driver Generator Section 3 How to Operate the PDG 3 3 Creating Opening a Project 3 3 1 Creating a New Project Create a new project through the following steps 1 Select File Create New Project to open the Create New dialog box see figure 3 2 Project new Project name default Director e enesasPD l prop default Ref Type of CPU Series MIEC Tiy Group MIECB Type Ho MaDBOPE ROM capacity 48K aK bites RAM capacity po ak bute Cancel Figure 3 2 Project new Dialog Box 2 Enter the name of the project to be created and specify the directory where the project is stored 3 Select the CPU series group and type No see table 3 1 Table 3 1 List of Supported Microcomputers M16C Tiny M16C 28 M30280F6 M30280F8 M30280FA M30280FC M30281F6 M30281F8 M3028 1FA M3028 1FC M16C 29 M30290FA M30290FC M30291FA M3029 1FC H8 300H Tiny H8 3687 HD64F3687 HD64F3684 H8 36077 HD64F36077 HD64F36074 H8 36049 HD64F36049 H8 36 ae II eem HD64F36109 R8C Tiny PRs R5F21132 R5F21133 R5F21134 R8C 22 R5F21226 R5F21227 R5F21228 R5F2122A R5F2122C REJ10J1769 0100 Rev 1 00 Nov 28 2007 LENESAS 3 3 Peripheral Driver Generator Section 3 How to Operate the PDG R8C 23 R5F21236 R5F21237 R5F21238 R5F2123A R5F2123C RSE21244 RSF21245 RSF21246 R5F21247 R5F21248 RSE21254 RSF21255 RS
38. esas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equ
39. hen Setting is selected on the trees in the left of the main window 1 Select Setting on the trees in the left of the main window and then select Function gt Serial A D I O Timer or INT gt Duplicate setting from the menu or right click on Setting and then select Duplicate setting from the pop up menu 2 A duplicated setup pattern is shown at the bottom of the mode that the original setup pattern belongs to REJ10J1769 0100 Rev 1 00 Nov 28 2007 s2ENGSAS 3 10 Peripheral Driver Generator Section 3 How to Operate the PDG 3 4 4 Deleting a Setup Pattern of Peripheral I O Modules You can delete an existing setup pattern When a resource is allocated to a setting to be deleted the resource setting is also deleted A setup pattern can be deleted only when Setting is selected on the trees in the left of the main window 1 Select Setting on the trees in the left of the main window and then select Function gt Serial A D I O Timer or INT gt Delete setting from the menu or right click on Setting and then select Delete setting from the pop up menu 2 The selected setup pattern is deleted 3 5 Allocating and Deleting a Resource od Allocating a Resource You can allocate a resource peripheral I O module to a setup pattern to which no resource is allocated according to each peripheral function Only one resource can be allocated to each setup pattern A resource can be allocated only when
40. hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Ren
41. ipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under cert
42. ly Perform setting for CPU clocks CPU clock setting System clock selection System clock frequency 20 000000 jay Man clock W Use as peripheral function clock source Input frequency to main clock circuit 20 000000 pay On chip oscillator clock Use as peripheral function clock source Frequency selectors Penodic yalue Divider selection On chip oscillator frequency 0 000000 pays Fil clock Use as peripheral function clock source Input frequency to PLL circuit 10 000000 jay Selection of multiplicatiom E PLL frequency 0 000000 pays Sub clock Use as peripheral function clock source Input frequency to sub clock Circuit 1 0327566 pay Sub clack divider E Sub clock 0 000000 WH CPU main clock divider Divided by 1 Interrial period 50 000000 pg cancel Figure 3 5 CPU clock setting Dialog Box REJ10J1769 0100 Rev 1 00 Nov 28 2007 RENESAS 3 7 Peripheral Driver Generator Section 3 How to Operate the PDG 3 4 Selecting Setting Peripheral I O Modules 3 4 1 Creating a New Setup Pattern of Peripheral I O Modules Create a new setup pattern of peripheral I O modules through the following steps 1 Click on the button see figure 3 6 corresponding to the peripheral I O module to be controlled or select Function gt Serial A D I O Timer or INT gt Create New Setting to select a mode A Peripheral Driver Generator default Ma FilefF
43. m the menu to open the Convert dialog box 2 Enter the names of the projects to be converted and newly created and also enter the directory in which the new project 1s to be stored 3 Select a series group and type No of the CPU into which the original is to be converted from the pull down menu Then click OK Convert Convert source project name CXxrenezassPDG projvdefaulidefault pd Ref Convert destination project name project Directory E renesas POG_propsproject2 Ref Type of convert destination CPU SEMEF MIGC Tiy l Group M16728 Type No M30280F5 RUM capacity ABKrAK bite AM capacity AK biel Cancel Figure 4 2 Convert Dialog Box 4 A new project file is created in the specified directory A message dialog box appears telling you that the conversion of the project is completed Converting completed Open NEW project Figure 4 3 Message Telling Completion of Project Conversion PDG REJ10J1769 0100 Rev 1 00 Nov 28 2007 stENGSAS 4 2 Peripheral Driver Generator Section 4 Converting a Project 5 Chcking on Yes opens the created project file 6 Some of the settings may be disabled or may require to be modified depending on the CPU and other settings for the original project Open setup pattern display window of each peripheral I O module to check the setting details A Peripheral Driver Generator H83687 FilefF Function U Displav
44. ne your application on your own responsibility when using this software to develop your application IBM is a registered trademark of International Business Machines Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation in the United States and other countries All brand or product names used in this manual are trademarks or registered trademarks of their respective companies or organizations REJ10J1769 0100 Rev 1 00 Nov 28 2007 stENESAS i Peripheral Driver Generator REJ10J1769 0100 Rev 1 00 Nov 28 2007 LENESAS Peripheral Driver Generator 1 Contents 179 ny 2 EEE A TTTTTETETTTTTTTTTTTTTTETTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTE TERTTET 1 1 1 1 FOGE O eoi E l 1 1 2 POC PR O E E E E E E E 1 1 1 3 Roks orhe PII oeseri eene se naaantenents oon seamuarancusereaandanee EEE IEEE SEI REEE ESAS 1 2 1 4 Operating Environment essari EEE EEE EN EEE ER 1 2 1 5 SOMPUOI OMDINA IONO peen tne te tenn Tan A o a kako an ok Sa a E ENNEA va 1 3 Mo JEK loj kio LTTITTTTTTTTTTTTTTTTTTTTTTTETTTTTTTITTTTTTTTTTTTTTTT TTT 1 3 17 DY VGH WN TAG ON ATT TTTTTTTrTRTRTT MMm TTTTRERTRTT rTT T ES 1 4 1 7 1 SENO TD CaaS AEG lic A TIN spreken a e akeo bed a lev koia Sa bo kamo 1 4 1 7 2 New Setup Pattern Creation Window cccccccccccccsssssssssssssseseeccccccceeceesaaaeesssssseeeeeecececeeeeeeeessssauaaaasseseseeess 1 5 1 7 3 Generated File Information Window cccccc
45. nents Version Toolchains System Tools l Utility Phases A ao Debugger Components Extension Components Unregister Communication Tools z Help System Tools Properties Export Search disk Tool information al Uninstaller T Show all components Current HEW tools database location CAProgram Filess ernesas Hewi Modify Figure 2 5 Tools Administration Dialog Box 5 Select the PDG hrf file in the directory where the PDG is installed By default the directory is C Renesas PDG Select HEW Registration File File name FDG hi Files of type HEW Registration Files hrf Cancel Figure 2 6 Select HEW Registration File Dialog Box REJ10J1769 0100 Rev 1 00 Nov 28 2007 2ENESAS 2 3 Peripheral Driver Generator Section 2 Preparation for Using the PDG 6 Make sure that the PDG is registered in System Tools in the Tools Administration dialog box Tools Administration Registered components th Toolchains System Tools ig Call Walker fe H Series Librarian Interface Cancel Mapviea ape Perpheral Driver Generator 1 02 000 tnt Phare Debugger Components Extension Components Communication Tools Search disk Help System Tools Tool information 4 Llninistaller Y r HHEH Show all components Current HEW tools database location E Program Filess enesas Hew Figure 2 7 Tools Administr
46. ode Setting Timer type BO Pulse period measurement IN 88 ve Input capture mode mode v B Ta Setting ALS Timer mode 1 Setting dx TEA Timer MIGC 29 Timer mode ti Setting Ta Setting I 0 CPU Serial Timer Generated function name Functional explanetion of Functions c renesas PDG_proj default Serial __OpensSeri c lrenesas PDG_projidefault Serial__CloseSeri E 22 Timer type A1 praj Timer setting value 399 fax Event counter mode E 2 Timer type A 48 Timer setting value 12 E ia Pulse width modulation mode ci renesas PDG_projidefaulti Serial _ConfigSer ci renesas PDG_proj defaulti Serial __SetSerialF ci renesas PDG_proj defaulti Serial __SetSeriall ci renesas PDG_proj defaulti Serial _StartSeria ci renesas PDG_proj defaulti Serial StartSeria ci renesas PDG_proj defaulti Serial _StopSerial ci renesas PDG_proj defaulti Serial _StopSerial ci renesas PDG_proj defaulti Serial PollingSeri Atem Setting vale f Period 20 000000 Operation During initialization Operation start Underflow interruption disa Underflow interruption function name e e Underflow interruption e Underflow interruption priority level Overflow interruption o A 2 a Overflow interruption function name Overflow interruption priority level
47. oolfT window Help H 3 ax DO sa Ex OG RX BESEEGEEBE 9 XESSSERS SE Big Seiat MIGL ZO en Sng vee Clock synchronous SIO mode Clock asynchronous SIO mode CPU D E A to i BRG register setting value 129 ta e Clock polarity selection E J i amp Reverse data logic Do not reverse CTS ATS function Do not use CTS RTS function Clock synchronous SIO mode Q LSE first MSB first selection LSB first i e Parity bit Parity disable Stop bit One stop bit QC Clock selection Internal clock Clock asynchronous SIO mode e ane pout i i Notification function name o Transmit interrupt Transmit interrput inhibit l amp Transmit interrupt level 0 i 6 Receive interrupt Receive interrupt inhibit Receive interrupt level 0 5120 interrupt 51 0 interrupt level la Baud rate Noise canceller i Transmit eceive pins select Clock pin select CPU Serial Timer VO Interrupt AD af Generated Function name Functional explanetion of Functions Related item i m No source is qenerated yet The generated sour n a i Clock synchronous SIO mode Clock asynchronous SIO mode asynchronous SIO mode Ready Figure 3 8 Setup Pattern Display Window REJ10J1769 0100 Rev 1 00 Nov 28 2007 RENESAS 3 9 Peripheral Driver Generator Section 3 How to Operate the PDG AZ Modifying a Setup Pattern of
48. orities When OK is clicked the files begin to be registered in the HEW project Library link priority setup Set the priority in which order libraries are linked Priority nic 3DliE lib high C Renesas POGSIbSM16C_Tingsrap mlbce 28 lib Friority low Figure 3 12 Library link priority setup Dialog Box When several HEW workspaces are opened files are registered in all active projects as stated in the dialog box that asks whether to register the files Close workspaces in which you do not register the files before performing registration 6 The message dialog box appears telling you that the registration is completed A The source file has completely been registered Figure 3 13 Message Telling Completion of the Registration PDG 3 9 3 Canceling Registration of Files Once source files are registered in the HEW you cannot cancel their registration via the PDG When you cancel them 1n the project tab of the HEW workspace window select a source file that you wish to cancel and right click on the file to open a pop up menu Then select Remove File or Exclude Build REJ10J1769 0100 Rev 1 00 Nov 28 2007 z ZENESAS 3 14 Peripheral Driver Generator Section 4 Converting a Project 4 Converting a Project 4 1 Project Conversion Function You can convert a project setting with a certain CPU model in order to use the project with another CPU model When settings in the original are not appropriate in
49. reation Window When a project file is opened buttons in this window are enabled Selecting a function and then clicking on a mode button opens a function setup dialog box that enables user to create a new setup pattern AC Peripheral Driver Generator default AGI ia File F Function U Displav v Tool T wincow i HelpfH x Dsu Se eee Taner METO pime impe fl Gh Timer mode Timer count source iy Setting Q Period 20 000000 El e Timer type Al Operation During initialization Operation start ee Timer setting value 333 i Underflow interruption Underflow interruption disa F Event counter mode Underflow interruption function name E Ta setting Underflow interruption priority level 0 Timer mode Timer type A Overflow interruption o Timer setting value 12 Overflow interruption function name E amp Pulse width modulation mode Overflow interruption priority level E T Setting Timer output Pulse is output Event counter mode 22 Timer type A1 B Clock output function Timer setting value high order bit Auto reload function Timer setting value low order bit m Control to write to timer Pul iod measurement mode EJ a o Pulse perio Gate function Do not use gate function Pulse width modulation mode E T Setting Count Source Frequency 20 000000 22 Timer type BO S Pulse width meas
50. s products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics C D lt Q Q Peripheral Driver Generator V 1 02 User s Manual Renesas Electronics Rev 1 00 2007 11 www renesas comM Notes regarding these materials 1 This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas producis for their use Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document 2 Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document including but not limited to product data diagrams charts programs algorithms and application circuit examples 3 You should not use the producis or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use When e
51. t compare Creates a new setup pattern of timer output When a project is opened mode setup creation compare mode New external interrupt setup Creates a new setup pattern of external interrupt When a project is opened creation REJ10J1769 0100 Rev 1 00 Nov 28 2007 stENESAS 1 11 Peripheral Driver Generator Section 1 Overview 1 10 Support Range of Peripheral I O Module Functions 1 10 1 Timer Table 1 7 lists the operating modes supported by the timer Table 1 7 Operating Mode Supported by Timer MI6C Tiny R8C Tiny H8 300H Tiny M16C 60 Pulse width modulation Pulse width modulation Pulse width modulation Pulse width modulation mode mode mode mode Pulse period Pulse period measurement Pulse period measurement Pulse period measurement measurement mode mode mode mode Pulse width measurement Pulse width measurement Pulse width measurement Pulse width measurement mode mode mode mode Input capture mode Input capture mode Input capture mode Po Output compare mode Output compare mode Output compare mode NN 1 10 2 A D Conversion Table 1 8 lists the operating modes supported by the A D conversion Table 1 8 Operating Mode Supported by A D Conversion Singlesweepmode Single sweepmode Single sweep mode ETER Repeat sweep mode 1 ART MA ETT sweep mode l Simultaneous sampling sweep mode Operating Detay wager mode fF mode nepre REJ10J1769 0100 Rev 1 00 Nov 28
52. tern refers to the details of peripheral I O settings 1 9 Toolbar The toolbar icons are listed in table 1 6 Table 1 6 List of Toolbar Icons Newproiet createsanew project Ae 0 0 0 0 a ses Moo Saves the open project When a project is opened Project Convert Erio Converts the open project for use in other Always microcomputers Batch source generate E Generates the sources for each setup completed When peripheral I O settings are peripheral IO collectively completed Output function list display E Displays output function list After batch source generation is performed Output function list update Updates output function list After batch source generation is performed Fa Shows the version of the PDG CPU setting Modifies settings for a CPU When a project is opened New serial synchronous Creates a new setup pattern of serial synchronous When a project is opened mode setup creation mode New serial asynchronous Creates a new setup pattern of serial asynchronous When a project is opened mode setup creation mode New A D single shot mode Creates a new setup pattern of A D single shot When a project is opened setup creation mode New A D repeat mode setup Creates a new setup pattern of A D repeat mode When a project is opened creation New A D single sweep mode Creates a new setup pattern of A D single sweep When a project is opened mode Creates a new setup pattern of A D rep
53. tern of serial asynchronous Only available when a project is opened Duplicates a setup pattern of serial Only available when serial setting is selected Deletes a setup pattern of serial Only available when serial setting is selected Modifies serial settings Only available when serial setting is selected Sets a UART for a setup pattern of serial Only available when serial setting is selected Deletes a UART from a setup pattern of serial Only available when UART is selected Creates a new setup pattern of A D single mode Only available when a project is opened 1 7 Peripheral Driver Generator Section 1 Overview Main menu Sub menu Description Creates a new setup pattern of A D repeat mode 5 setting N Repeat Mode R Single Sweep Mode G Repeat Sweep Mode 0 W Repeat Sweep Mode 1 E Simultaneous Sampling Sweep Mode P Delay Trigger Mode 0 D Delay Trigger Mode 1 L Duplicate setting C Delete setting D Modify setting M Set input group and pin I Delete input group and pin L I O D Newly create setting N Duplicate setting C Delete setting D Modify setting M Set port P Delete port L Timer Newly Timer Mode T T create setting N Event Counter Mode E Only available when a project is opened Creates a new setup pattern of A D single sweep mode Only available when a project is opened Creates a new setup pattern of A D repe
54. tions 9 You should use the products described herein within the range specified by Renesas especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges 10 Although Renesas endeavors to improve the quality and reliability of its products IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Please be sure to implement safety measures to guard against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other applicable measures Among others since the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you 11 In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed the risk of accident such as swallowing by infants and small children is very high You should implement safety measures so that Renesas produ
55. uency to PLL circuit 10 000000 1442 Selection of multiplication B v PLL frequency 0 000000 MHz la CPU Serial Time Sub dloekidividej YJ Sub clock I Use as peripheral function clock source Input frequency to sub clock circuit 0 032768 44 Sub clock 0 000000 MHz CPU main clock divider Divided by 1 Internal period 50 000000 ng Cancel Ready E el Tm Figure 3 3 CPU clock setting Dialog Box REJ10J1769 0100 Rev 1 00 Nov 28 2007 z ZENESAS 3 5 Peripheral Driver Generator Section 3 How to Operate the PDG 2 Opening an Existing Project Open an existing project through the following steps 1 Select File gt Open from the menu to open the Open File dialog box 2 Select a project that you wish to open and click on the Open button or double click on the file name 3 The selected project opens A Peripheral Driver Generator default a File E Function U Display Toot window Help H JX Dru BESS I 2X BOSBSBEEuu Ad 4SBSSRS SE CPU H8387 lm G w 7 ia Setting SE Divide ratio of on chip oscila B Selection of on chip oscillato Divided by 1 i Selection of PLL multiplier Periodic value Sub clock Used i Sub clock dividing ratio Divided by 2 Input frequency to sub clock 0 032768 System clock selection Main clock CPU setting Main clock Used Input
56. urement mode Setting Timer type BO Pulse period measurement IN 88 Input capture mode mode I Ta Setting 1 0 Be Timer tune 5 ba I I Interrupt A D CPU Serial Timer Interrupt Generated function name Functional explanetion of Functions Related item e c lrenesas PDG_projidefault Seriall_ OpenSeri Boolean OpenSerialDriver async UO pl void Open Initialize the appointed serial c lrenesas PDG_projidefault Serial __CloseSeri Boolean CloseSerialDriver async LO pif void Close the appointed serial I F pi c lrenesas PDG_projidefault Serial _ ConfigSer Boolean ConfigSerialDriverNotify async LUO Register the appointed type of notif Notification function name c trenesas PDG projidefaultiSeriali SetSerialF Boolean SetSerialFormat async UO pifvoid Change serial setting Bit number Clock selection c renesas PDG_projidefault Serial _ SetSeriall Boolean SetSerialinterrupt async LO pl void Set up serial interrupt Transmit interrupt Transmit x c renesas PDG_projidefault Serial _ StartSeria Boolean StartSerialReceiving async UO plf Start receiving 3 c lrenesas PDG_projidefault Serial _ StartSeria Boolean StartSerialSending async UO pi u Start transmitting c renesas PDG_projidefault Serial _ StopSerial Boolean StopSerialReceiving async UO pl Stop receiving c renesas PDG_projidefault Serial _ StopSerial Boolean StopSerialSending async UO pl void Stop transmitting c renesas PDG_proji
57. xport Search disk p Tool information E E l Uninstaller T Show all components Current HE tools database location CAProgram Files AenesassHew Modify Figure 2 9 Tools Administration Dialog Box 4 Enter the directory where the HEW is installed in the Search Disk for Components dialog box and click on the Start button to search for HewTargetServer Search Disk for Components acted Ti CAProgram Files Henesas Hew i Include subfo Located components Version HAF Location Register All Search status Idle Figure 2 10 Search Disk for Components Dialog Box REJ10J1769 0100 Rev 1 00 Nov 28 2007 stENGSAS 2 5 Peripheral Driver Generator Section 2 Preparation for Using the PDG 5 From Located components select HewTargetServer 1 05 00 and click on the Register button Search Disk for Components Select the directory in which to begin the search CAProgram Files ernezaswHew Browse Close i Include subfolders Located components Q C Program Files PERME ew Syst DI E agram Files Bane vako Register All C Program Files A enesas Hew Sut Call Walker C Program Files Renesas Hew s T ool Call Walker C Program Files Renesas Hew T ool Hes HO 3UO Sta 6 0 0 C Program Files Aenesas Hew sT ool HES H8B 3UO Sta 6 1 1 C Program Files Renesas Hew T ool HES H8
58. xporting the products or technology described herein you should follow the applicable export control laws and regulations and procedures required by such laws and regulations 4 All information included in this document such as product data diagrams charts programs algorithms and application circuit examples is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas producis listed in this document please confirm the latest product information with a Renesas sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website http www renesas com 5 Renesas has used reasonable care in compiling the information included in this document but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document 6 When using or otherwise relying on the information in this document you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application Renesas makes no representations warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this
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