Home

TPS-1 User`s Manual - Renesas Electronics

1. OSC_CLK ES 25 MHz YY bii wo H lt lt lt v gee RESETN 555 z o0 external lt lt lt gt nnn oO SS 2 Sua TT POR_OUT E internal na s x y 10 us 30us 50Qus Figure 10 1 Reset behavior The start up time of the oscillator depends on the external components quartz RLC As a general rule of thumb it is roughly in the range of ms R19UH0081ED0104 Rev 1 04 RENESAS page 54 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 11 Boundary Scan Interface JTAG 11 Boundary Scan Interface JTAG The JTAG interface is used for the Boundary Scan test Table 11 1 JTAG interface pin definition Pin Designation Type Description Remark K5 TASTN Test Reset JTAG Reset Input Reset signal of the target port External pull down 4K7 Q to GND L6 TMS Test Mode Select JTAG interface is activated from the debug unit pull up 4K7 Q to Vpp L7 TDO O Test Data Output J5 TCK l Test Clock JTAG clock signal to the TPS 1 It is recommended that this pin be set to a defined state on the target board External pull up 4K7 Q to Vpp L5 TDI I Test Data Input External pull up 4K7 Q to Vpp Table 11 2 JTAG interface pin definition Pin TMO Pin TM1 Function 0 normal operation mode 1 Boundary scan mode see BSDL file R19UH0081ED0104 Rev 1 04 Jul 13 2015 tENESAS page 55 of 80 TPS
2. Name Host_IRQ_low Address 0x0008 Access r Bits Type of Event Description Init 31 00 IRQ Bits 0 PN Event low 0 or Host IRQMask low 1 0X00000000 1 PN_Event_low 1 and Host_IRQMask_low 0 Table 4 11 Register Host IRQ high Name Host IRQ high Address 0x000C Access r Bits Type of Event Description Init 31 00 IRQ Bits 0 PN Event low 0 or Host IRQMask low 1 0X00000000 17 PN Event low 1 and Host_IRQMask_low 0 The deactivation of the interrupt pin INT OUT is processed by writing into the register Host FOI 0x0028 A new activation of the interrupt pin depends on the written value bits 17 00 Wait Time The activated events can be identified by reading the register Host IRQ low and Host IRQ high Table 4 12 Register Host EOI Name Host EOl Address 0x0028 Access r w Bits Type of Event Description Init 17 00 Wait_Time Period of deactivating of the interrupt pin INT_OUT 0X00000 Number of entities 10ns max value 2 6 ms 31 18 reserved R19UH0081EDO104 Rev 1 04 RENESAS page 39 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 4 Shared memory structure 4 5 Status LEDs of theTPS 1 The TPS 1 uses 4 GPIOs to indicate the device status These GPIOs can be connected directly to LEDs to display the status Table 4 13 Stat
3. PROFINET CPU Core Internal RAM Boot ROM During the manufacturing process the following data have to be written to the boot Flash UART Interface Boot Flash SPI Slave SPI Master Interface Ethernet Interface LAN Interface Figure 5 1 TPS 1 structure for the boot process e manufacturer information e device data device configuration e I amp M information e operating mode of the TPS 1 e MAC addresses e PROFINET CPU firmware Target Host Image The necessary data for the boot Flash is assembled by the configuration tool TPS Configurator R19UH0081EDO104 Rev 1 04 RENESAS page 41 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 5 TPS 1 boot subsystem 5 2 Loading and update of the firmware during the manufacturing process The serial boot Flash can be written in several ways e before mounting with a programmer e via JTAG interface e via serial interface UART N e via ETHERNET interface BOOTP TFTP Note 1 Basically we recommend to use serial interface UART during the development phase to fill an empty Flash 2 via ETHERNET is for firmware update only If you have TPS 1 toolkit v1 1 0 2 or later Please pre program empty Flash with default image in the toolkit before the Flash is soldered It allows to do all required setting via ETHERNET 5 2 1 UART interface UART boot The UART interface is used for basic communication with the TPS 1 The
4. R19UH0081EDO104 Rev 1 04 RENESAS page 28 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 3 Host Interface 33222 SPI Slave Interface Handshake Wait Mode When using the Handshake Wait Mode the SPI master deactivates the data transfer after the header has been transmitted and starts a wait time During this time the SPI Slave can provide the requested data POST PEEN EEFE EFI ULILILILILI LI LILILI LT ror sano fe SAI ee TTT SPI Status gt Motorola SPI SPI RD Datm format SPO 0 SPH 0 Figure 3 13 SPI Read Timing Wait Mode The following equation describes the Wait Time after the command bytes before starting the payload data Twait 32 fiys fspr 10 Tar L fsys Wait Time The time between two complete data transfers is calculated with the following equation L 4 Twait 10 8 f fspr L La break between two cycles The following table shows a rough estimation for two frequencies Table 3 9 SPI Wait Time SPI Clock MHz Wait Time us 12 5 2 46 2 5 25 118 12 R19UH0081EDO104 Rev 1 04 RENESAS page 29 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 3 Host Interface 3 3 3 SPI Slave Interface Reset Timing Figure 3 14 describes the behavior when a reset for the SPI Slave interface occurs The communication process is interrupted and after a wait time of4 system clocks 40 ns for the TPS 1 the next transfer can
5. D0 ADi gt ADO AD15 LBU READY OUT EA N WAITN LBU_READ_EN_IN RDN RDN LBU_BE_1_IN rer LBU BE 2 IN WRIN LBU WR EN IN Figure 3 7 Connection of a V850 CPU with a 16 bit data bus R19UH0081ED0104 Rev 1 04 RENESAS page 22 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 3 Host Interface 3 3 SPI Slave Interface Another way to connect a host CPU is the SPI interface The maximum speed for serial access to the shared memory is 25 MHz The transmission clock frequency should range between 1 MHz and 25 MHz A control unit for processing the SPI Master commands is implemented into the TPS 1 The SPI Master commands are described in this chapter Table 3 6 SPI host interface signals Pin GPIO Pin Signal designation Function Remarks P3 GPIO 38 HOST RESET IN Serial Reset The SPI Slave interface can be reset by using this signal signal is active high N3 GPIO 39 HOST SFRN IN Serial Frame The start of a new SPI transfer is signalized N2 GPIO 40 HOST SRXD IN Serial Data Input MOSI Master out Slave in N4 GPIO 41 HOST SCLK IN Serial Clock Input Serial Clock driven by the SPI Master M4 GPIO 42 HOST STXD OUT Serial Data Output MISO Master in Slave out P4 GPIO_43 HOST_SHDR_OUT Serial Header Information header information available An unknown or wrong SPI access causes an Error IRQ that is reported to the host CPU by the event unit
6. Write MEM R19UH0081ED0104 Rev 1 04 Jul 13 2015 Writes to the transferred address The length is coded in the length byte 0b0100_0000 0x40 ENESAS 1 32K 64K page 26 of 80 TPS 1 User s Manual Hardware 3 Host Interface 3 3 2 SPI Slave Interface Timing The SPI transfer is controlled by the signal HOST_SFRN_IN A chip select signal is not used 3 3 2 1 SPI Slave Interface Typical Timing The following figure shows a typical SPI Slave Timing Motorola Mode Each transfer a transmission of 8 bit starts with a falling edge of the HOST_SFRN_IN signal The transmission is controlled by the clock signal All receive and transmit data is processed in the Little Endian format by the serial host interface When connecting a Big Endian Host System the format has to be changed into the correct order There is a maximum clock frequency of 25 MHz possible using this interface HOST_SCLK_IN PLL LLL PLL LLL TIUU HOST SFRN IN DO Jeo SPI Header lt SPI Data o0008005 80880080 8686 MSBit LSBit MSBit LSBit HOST SHDR OUT Figure 3 10 SPI Slave Timing The signal HOST SHDR OUT is used to inform the SPI master that header information has been received HOST SHDR OUT 0 When the signal goes to high level HOST SHDR OUT 1 payload data is expected R19UH0081ED0104 Rev 1 04 RENESAS page 27 of 80 Jul 13 2015 TPS 1 User s Manual Hardware
7. 3 2 1 Operating modes of the parallel interface The parallel interface can be used with an 8 bit or 16 bit data bus Table 3 1 Operating Modes of the parallel interface Setting Description Operating mode Separate Read Write signal Intel Mode Read Write Control Motorola Mode Polarity of ready signal Ready Signal active low Ready Signal active high Data bus width 8 bit 16 bit The configuration of the parallel interface is also done with TPS Configurator R19UH0081EDO104 Rev 1 04 RENESAS page 16 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 3 Host Interface 3 2 2 Signal description of the parallel interface The shared memory has an address space of 64 Kbyte refer to chapter Shared memory structure The typical page size is 16 KByte For a correct alignment you have to connect the highest address bits to the signals LBU SEGO IN and LBU SEGI IN see Table 3 2 Figure 3 1 and Figure 3 2 TPS 1 Host Interface LBU Ax IN 13 0 A 130 Ext Host CPU A 15 0 LBU SEG 1 0 IN A 15 14 Figure 3 2 TPS 1 with address page 16 Kbyte You can also choose a page size of 4 Kbyte When you choose 4 Kbyte pages you have less space inside the NRT area for configuration slots and subslots TPS 1 Host Interface LBU Ax IN 13 12 LBU Ax IN 11 0 A 11 0 Ext Host CPU A 13 0 LBU SEG 1 0 IN A 13 12 Figure 3 3
8. The clock phase and the CPOL clock polarity is adjustable active low active high The following figure shows the connection of a host CPU V850ES JG2 to the SPI Slave interface of the TPS 1 The chip select line is not connected The data transfer is controlled by the status of the clock line CSI Master The pins HOST RESET IN HOST SFRN IN and HOST_SHDR_OUT are not supported directly by the HOST CPU They have to be simulated by the pins P02 P03 and P04 HOST CPU V850ES JG2 CSIBx Master HOST_SRXD_IN MOSI SOBx HOST_STXD_OUT MISO SIBx HOST_SCLK_IN SCLK SCKBx SPI SLAVE HOST RESET IN SPI Reset P03 Output HOST_SFRN_IN SFRM_I P02 Output HOST_SHDR_OUT SHDR OUT P04 Input Figure 3 8 Connection of a V850 CPU to the SPI interface R19UH0081EDO104 Rev 1 04 RENESAS page 23 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 3 Host Interface 3 3 1 Serial access to the shared memory The access to the shared memory is processed with command bytes that are part of the SPI Header The command structure depends on the device Generally an SPI interface works like a shift register The clock is driven by the SPI master After processing the SPI command the SPI slave sends the requested data to the host CPU or data is only sent to the SPI slave As long as the chip select signal is active data are exchanged between the devices master slave 3 3 1 1 Header structure The content and
9. 1 0V VDD ov T 4 Trampup_3 3V Trampup_1 DV 100ms 100ms Figure 8 3 TPS 1 Power up sequence R19UH0081EDO104 Rev 1 04 RENESAS page 52 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 9 Clock circuit 9 Clock circuit The clock distribution of the TPS 1 requires an oscillator with 25 MHz XCLKI XCLK2 All necessary internal clock signals are derived from this external clock internal clock unit APPL REFCLK 25 MHz REFCLK 16 25 MH 15pF 50V SE 15pF 50V MOOVMIO MOOT Td ZHI 001 Wu 1719 Figure 9 1 Wiring of the TPS 1 clock The circuitry example Figure 9 1 is based on the Epson Toyocom FA 238 Crystal Unit The crystal tolerance must not be more than 50 ppm at 25 MHz The duty cycle has to be 50 10 This tolerance must be preserved for the entire life span R19UH0081EDO104 Rev 1 04 RENESAS page 53 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 10 Reset of the TPS 1 10 Reset of the TPS 1 An external reset is caused by a low level at the signal pin RESETN This condition is held until the low level changes to a high level During startup of the power supply the 3 3 V voltage is controlled by the TPS 1 internal The 1 5 V voltage if fed from external and the 1 0 V voltage must be controlled by an external circuitry
10. Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2015 Renesas Electronics Corporation All rights reserved Colophon 4 0 TPS 1 LENESAS Renesas Electronics Corporation R19UH0081ED0104
11. LENESAS E d D T d D I TPS 1 User s Manual Hardware RENESAS ASSP Ethernet Controller for PROFINET IO Devices All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http www renesas com Renesas Electronics WwWW renesas com Rev 1 04 Jul 2015 10 11 12 Notice Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics does n
12. TPS 1 with address page 4 Kbyte R19UH0081ED0104 Rev 1 04 RENESAS page 17 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Table 3 2 describes all signals of the parallel Host interface Table 3 2 Parallel Host Interface Layout 3 Host Interface Signal designation Function Remarks LBU WR EN IN Write Control active low Intel mode 0 write 1 read Motorola mode LBU READ EN IN Read Control active low Intel mode no function Motorola Mode LBU CS IN Chip Select LBU BE 1 IN Byte Selection 1 LBU BE 2 IN Byte Selection 2 LBU READY OUT Ready Signal polarity changeable LBU DATAO LBU DATA15 data line 0 15 LBU AO IN LBU A13 IN Address lines 0 13 LBU SEGO IN Low Bit of the segment page selection LBU SEG1 IN High Bit of the segment page selection During a memory access the TPS 1 behaves like a 16 bit Little Endian device with an 8 bit or 16 bit memory The possible access types are listed in Table 3 3 Table 3 3 16 Bit external Host Databus LBU BE 2 IN LBU BE 1 IN Access type 1 0 8 Bit LOW 0 1 8 Bit HIGH 0 0 16 Bit Other combinations Not allowed Table 3 4 8 Bit external Host Databus LBU A 1 0 LBU BE 2 IN LBU BE 1 IN Access type 00 1 0 8 Bit access 01 1 0 8 Bit access 10 1 0 8 Bit access ti 1 0 8 Bit access Other combinatio
13. The serial Flash must have a minimum size of 1 MByte and must support the Motorola SPI compatible interface The serial flash must be able to write sectors with a size of 4 kByte The used SPI protocol configuration is as follows e Motorola SPI frame format e 8 bit data words e SPI clock out pin has a steady state high value when data is not being transferred e Data is captured on the rising edges and propagated on the falling edges of the SPI clock signal You should avoid a device with write protection particularly with a default setting after power up The Flash ROM must support the SPI Commands listed in Table 5 3 SPI Boot Loader Driver Commands The following flash devices are recommended e M25PX32 V MW 3 4M x 8 Numoyx Micron e M25PX64 8M x 8 Numoyx Micron e M25PX80 1M x 8 Numoyx Micron e MX25L6406E 64M x 8 Macronix e MX25L3206E 32M x 8 Macronix e MX25L8006E 8M x 8 Macronix Table 5 2 Boot Flash SPI Master Interface Pin Signal name Typ Function M12 CS_FLASH_OUT O SPI Master Interface Firmware Flash Chip Select TPS 1 active low N13 SPI3 SCLK OUT O SPI Master Interface Firmware Flash CLOCK TPS 1 M13 SPI3_SRXD_IN SPI Master Interface Firmware Flash Receive Data TPS 1 MISO M14 SPI3_STXD_OUT O SPI Master Interface Firmware Flash Send Data TPS 1 MOSI R19UH0081EDO104 Rev 1 04 RENESAS page 43 of 80 Jul 13 2015 TPS 1 User s Manual Har
14. U K Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 6503 0 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd Room 1709 Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100191 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 301 Tower A Central Towers 555 Langao Road Putuo District Shanghai P R China 200333 Tel 86 21 2226 0888 Fax 86 21 2226 0999 Renesas Electronics Hong Kong Limited Unit 1601 1611 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2886 9022 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei 10543 Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 80 Bendemeer Road Unit 406 02 Hyflux Innovation Centre Singapore 339949 Tel 65 6213 0200 Fax 65 6213 0300 Renesas Electronics Malaysia Sdn Bhd Unit 1207 Block B Menara Amcorp Amcorp Trade Centre No 18 Jin Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics India Pvt Ltd No 777C 100 Feet Road HALII Stage Indiranagar Bangalore India Tel 91 80 67208700 Fax 91 80 67208777 Renesas Electronics Korea Co Ltd 12F 234 Teheran ro Gangnam Gu Seoul 135 080
15. siu see sd 5 2 1 VARTinterface VAR ME 5 2 2 SPI masterinterfa e Boob Flash su A A A EE deeso IA INIA NASA A 45 6 1 GPIO DIGITALINPUTAND OUTPUT idol 45 TPS EWATCHDOG E See dE Eed 46 7 1 SIGNALWD OUTPIN B19 ss subsia a kea dla kaksa lla la kiak dalla la diala kakto la 46 moj SIGNAL WD IN PIN A11 PROFA TO SV OH jeer repo e ono rebo cabs nko os 48 8 1 10OBASE EX INTERFACE sss skunnstunkistas ona ana skala boa tia 8 1 1 100Base TX interface Port 1 8 1 2 100Base TX interface Port 2 8 2 100BASE FX INTERFACE FIBER OPTIC 8 2 1 IQOBase EXinterface Port l sus ks kasus lk ask ok 8 2 2 TIOOBase EXdnterface Port ai tai oran i keco iai 8 3 I2C BUS LWC DIAGNOSTIC i 8 4 ADDITIONAL TPSA EE 8 5 INTEGRATED VOLTAGE REGULATOR GD Vuk kanon ni dd page 6 of 80 9 SCEOCK CIRCULE eet eege o o epeo po eano p sr oo den 53 10 RESET OF THE TPS iii sa enas i e ne esee 54 11 BOUNDARY SCAN INTERFACE STAG ei eege ee 55 Lani Circuit recommendation of the JTAG Interface 56 APPENDIX A SETTING OF OPERATING MODES eee seen iau dsd NEEN dao P Ina i a EE 57 Al HOSTIN TERA EE ALVA Parallel Interact E E ide AZ Serial interlace 112 te wk acts tele dd id tdt tii it btt E A 2 THO CONFIGURATION eege E A A A te AZ Le Parallel EE A 2 2 IO Local Interface A 2 3 I amp MO Configuration I MO data A3 ETHERNET INTERFACE CONFIGURATION esesesesereretrtecrerertttttttttttttttttt
16. 1 User s Manual Hardware 11 Boundary Scan Interface JTAG 11 1 1 Circuit recommendation of the JTAG Interface If the JTAG interface is unused in the customer application the TRSTN input of the TPS 1 should be connected to digital GND via a 4 7kQ resistor The circuit recommendation for the interface looks as follows open All resistors 4 7kQ Figure 11 1 Unused JTAG Interface If the customer wants to use the JTAG interface for boundary scan test the customer has to check whether the boundary scan tool that he intends to use has specific requirements with respect to the TRSTN circuit in the target system If the boundary scan tool has specific requirements the circuit in the target system must be made configurable The subsequent figure shows the situation that the boundary scan tool requires a pull up at the TRSTN input of TPS 1 For using the JTAG interface with a boundary scan tool you should implement the following All resistors 4 7kQ 1 2 Connect 1 2 for boundary scan 3 Connect 2 3 for normal operation Figure 11 2 JTAG useable for boundary scan R19UH0081EDO104 Rev 1 04 RENESAS page 56 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Appendix A Setting of operating modes Appendix A Setting of operating modes The basic configuration of the TPS 1 is managed with the TPS Configurator software You can set the configuration of the host interface serial parallel or the configuration of the Loc
17. 3 Host Interface 3 3 2 2 SPI Slave Interface Handshake Mode If the header contains a read or exchange command it is necessary to wait for a short time after transferring the header in order to enable the slave interface to collect the data before transferring There are two methods to do this You can enable the busy mode polarity high or low or use the wait mode 3 3 2 2 1 SPI Slave Interface Handshake Busy Mode The handshake mode and the polarity can be configured with the TPS Configurator After transmitting the header information the Busy Enable signal is set no clock and HOST SRXD IN in high or low depends on the Busy POL When the SPI slave interface can transmit the requested data the HOST STRX OUT signal is set to its active level This indicates to the SPI master that it can start the next cycle and the master release the Busy Enable signal This forces the SPI slave to release the Busy level and the master starts the next clock cycle A lO PULL LILI LILILILTI HOST SFRN KEE MM y emo ohe ee DIAAN e SPI Status Ji li SPI e ormat SPO 0 SPH 0 SR SR SR E Figure 3 11 SPI Read Timing Busy_POL 0 HosT_sCLK_IN PULL LIL LULL HosTsFANIN TT i DECH Ir HOST SRXD IN d o 6 2 2 6 2 Busy Enable 2028 MOLINO 00006 DT SPI Status p gt Motorola SPI SPI RD Data format SPO 0 SPH 0 komenee Figure 3 12 SPI Read Timing Busy POL 1
18. 7 Ethernet Interface Configuration as well in order to support port based communication services for e g LLDP The serial number of the device is edited in S N The IP addresses Destination IP and Source IP are needed for the transmission of configuration data via the Ethernet interface of the TPS 1 MAC address The PC on which this tool is running represents the Source IP address The Destination IP represents the PROFINET Device to configure The configuration of the device is carried out in a subnet to which only the Source PC and the PROFINET Device belong factory configuration The device at first accepts any frame that contains the necessary MAC addresses It is possible to program the MAC addresses one time it is not allowed to change this initial configuration later R19UH0081ED0104 Rev 1 04 Jul 13 2015 TENESAS page 64 of 80 TPS 1 User s Manual Hardware Appendix A Setting of operating modes AA Copying the configuration data into the Boot Flash After the configuration data is complete it has to be transferred to the PROFINET device During the manufacturing process the data can be copied into the Flash device with a special program FS Prog exe The TPS Configurator can generate a command with all the parameters see Generate Command File Settings Help General Settings Ident Settings IO General Settings IO Parallel Settings Diag Channel Destination IP Source
19. EOl register to reset the interrupt pin INT OUT It is only necessary to set the mask register during the start sequence of your device once Each occurring event has to acknowledge by writing the Host IRQack low and Host IRQack high register After writing an acknowledge register the Host EOI register must be written The value written into this register disables the interrupt pin for the given period period count 10ns Wait Time The interrupt signal is active low Note You must write the register Host EOl during the initialization program start to set the signal line to its passive state low level The register PN Event low and PN Event high is used to inform the external host about events An ISR can check the event by reading these registers Table 4 4 Register PN Event low Name PN Event low Address 0x003C Access r w Bits Type of Event Description Init 31 00 Event Bit high active events 0X00000000 HW Evenis Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Receive Output Data AR1 Bit 8 Receive Output Data ARO Bit 9 15 reserved Bit 16 31 further use R19UH0081EDO104 Rev 1 04 RENESAS page 36 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Table 4 5 Register PN Event high 4 Shared memory structure Name PN Event high Address 0x0040 Access r w Bits Type of Event Description Init 31 00 Ev
20. GND Figure B 6 100BASE TX Interface circuit Example R19UH0081ED0104 Rev 1 04 RENESAS page 72 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Appendix B Board Design Information B 3 3 Unused 100Base TX Interface In applications that do not use the 100BASE TX mode but only the 100BASE FX mode the analog I Os should be left open Only EXTRES must still be connected with the 12 4 kQ resistor to analog GND open open open open open 12 4 KO 1 AGND Figure B 7 Unused 100BASE TX Interface R19UH0081ED0104 Rev 1 04 RENESAS page 73 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Appendix B Board Design Information B 3 4 100BASE FX Mode Circuitry In case of 100BASE FX operation a PN IO compliant optical transceiver module like Avago AFBR 5978Z or QFBR 5978Z is connected to the FX interface The signals between the PHY and the transceiver module are 100 Q differential respectively 50 Q single ended signals PxTD_OUT_P PxTD_OUT_N Vcc 3 3V IC2 x D INOUT SCLK x INOUT Figure B 8 100BASE FX Interface Example Note All resistors in this example should have a tolerance of 1 R19UH0081EDO104 Rev 1 04 RENESAS page 74 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Appendix B Board Design Information The circuitry for the connection of the SD Pin of the transceiver to the SD P SD N Pin of the TPS 1 is shown in Figure B 9 The active circuitry is necessary because the QFBR AF
21. INOUT O Fiber Optic Port 2 C Bus Clock e g SC RJ C11 LINK PHY2 O LINK indication ETHERNET Port 2 up or down active high A10 ACT PHY2 O Activity ETHERNET Port 2 active high J13 P2 TX P O ETHERNET Port 2 Transmit Data positive e g RJ45 J14 P2 TX N O ETHERNET Port 2 Transmit Data negative e g RJ45 K13 P2 RX P ETHERNET Port 2 Receive Data positive e g RJ45 K14 P2 RXN ETHERNET Port 2 Receive Data negative e g RJ45 N8 P2 SDP Fiber Optic Port 2 Signal Detect positive e g SC RJ P8 P2 SD N Fiber Optic Port 2 Signal Detect negative e g SC RJ N9 P2 RD P Fiber Optic Port 2 Receive Data positive e g SC RJ P9 P2 RDN l Fiber Optic Port 2 Receive Data negative e g SC RJ N6 P2 TD OUT P O Fiber Optic Port 2 Transmit Data negative e g SC RJ P6 P2 TD OUT N O Fiber Optic Port 2 Transmit Data positive e g SC RJ R19UH0081ED0104 Rev 1 04 RENESAS page 11 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 2 Pin function P5 P2 FX EN OUT O Fiber Optic Port 2 Transmitter enable active high e g SC RJ Oscillator N11 XCLK1 l Connection external oscillator 1 25 MHZ P11 XCLK2 O Connection external oscillator 2 25 MHz JTAG Interface L4 TMO l Test Input 0 Chip Test 10k to GND pull down J10 TMi l Test Input 1 Chip Test 10k to GND pull down K5 TRSTN
22. e Host Serial A host CPU is connected via the SPI slave interface e Host Parallel A host CPU is connected via the parallel interface e 10 Serial An IO device is connected via a simple SPI master interface e JO Parallel The GPIO pins are used in a user specific order By choosing a special operation mode the corresponding configuration tabs are activated label active Only these tabs can be edited all others are locked R19UH0081EDO104 Rev 1 04 RENESAS page 57 of 80 Jul 13 2015 TPS 1 User s Manual Hardware A1 Host Interface The host interface realizes the connection of external host CPUs Data exchange is carried out via an internal Shared Memory area Depending on the type of external host CPU you can choose a serial SPI slave or a parallel interface A 1 1 Parallel Interface The parallel host interface can be configured to work at 8 bit or 16 bit data width and in Motorola or Intel operating mode Thus the interface facilitates the connection of different processor types You find the respective parameters on the window tab Host Parallel Settings a TPS Configurator File Settings Help General Settings Ident Settings Host Parallel Settings Ethernet Settings Appendix A Setting of operating modes 30 01 2014 10 54 53 Parameter changed sucessful WatchdogTime gt 100 RENESAS Figure A 2 Parallel host interface configuration R
23. for IOSAR is disconnected TPS_EVENT_ONREADRECORD Set when a Record Read Request is available in a Record Mailbox TPS_EVENT_ONWRITERECORD Set when a Record Write Request is available in a Record Mailbox TPS EVENT ONALARM ACK 0 Set when an alarm low priority is acknowledged from the controller TPS EVENT ONDIAG ACK Set if a diagnostic alarm is acknowledged TPS EVENT ONCONNECT REQ REC 0 Set if a Connect Req for the first AR ARO is received TPS EVENT ONCONNECT REQ REC 1 Set if a Connect Req for the first AR AR1 is received TPS EVENT ONCONNECT REQ REC 2 Set if a Connect Req for the third AR AR2 is received TPS EVENT ON SET DEVNAME Device name is send to the host application TPS EVENT ON SET IP PERM IP address should be set permanent TPS EVENT ON SET IP TEMP IP address should only be set temporary TPS EVENT ONDCP BLINK START Action LED flashing is should start TPS EVENT ONDCP FACTORY RESET All settings are set to the factory settings TPS EVENT ONALARM ACK 1 Set when an alarm high priority is acknowledged from the controller TPS EVENT RESET A RESET of the Host CPU is forced TPS EVENT ETH FRAME REC A TCP IP Ethernet Frame is received R19UH0081ED0104 Rev 1 04 Jul 13 2015 tENESAS page 34 of 80 TPS 1 User s Manual Hardware 4 Shared memory structure 4 3 Events from the host
24. start nost ser in LE LILI LE LUULI PLL LILI LIAL HOST_SFRN_IN RII KRKI E HOST SHDR OUT 4 x SysCLK HOST_RESET_IN Figure 3 14 SPI Slave Reset Timing The signal HOST_RESET_IN is the only way to set the slave interface to a defined status The signal is active high During the normal operation the signal is set to low level R19UH0081ED0104 Rev 1 04 RENESAS page 30 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 4 Shared memory structure 4 Shared memory structure Figure 4 1 describes the structure of the shared memory The serial and parallel interfaces see the same memory image 64 Kbyte If you use 4 kByte memory pages then you can only use the NRT Area up to Ox9FFF o es reserved Event and lO area 32k Byte Ge Output Area Input Area MC Provider IO RAM Area 2k Byte 0x2800 reserved Device Vendor Information ARO RecordMailbox ARO AlarmMailbox high ARO AlarmMailbox low RecordMailbox NRT AlarmMailbox high Area 32k Byte AlarmMailbox low RecordMailbox Supervisor AR RecordMailBox Implicit AR TCP IP Mailbox Slot Subslot configuration OxFFFF Figure 4 1 TPS 1 Shared Memory Structure Dual Ported RAM R19UH0081ED0104 Rev 1 04 RENESAS page 31 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 4 Shared memory structure The structure of the configuration written into the NRT area is checked by the TPS 1 firmware If ther
25. to GND This external resistor should be placed as close as possible to the chip It must be terminated to analog GND 8 5 Integrated voltage regulator 1 5 V The integrated PHY components require a supply voltage of 3 3 V and 1 5 V The supply voltage 1 5 V is supported by an internal voltage regulator For a correct operation some additional electronic components are necessary Figure 8 2 Internal voltage regulator shows the design of the switching regulator During normal operation Switching Regulator is running and POR is active the pins TEST1 TEST2 and TEST3 are connected to GND via a pull down resistor It is also possible to feed the TPS 1 with an external voltage of 1 5 V Then you have to switch off the regulator Pin TESTI set to 1 with a pull up The regulator output Pin LX changes to HiZ status The POR function must be in operation because this signal is used in combination with the external signal RESETN to enable the TPS 1 dies Caution The 3 3 V supply voltage has to be connected to BVDD pin J1 and AVDD_REG pin F2 AVDD_REG is used to generate the internal POR signal of the TPS 1 If you are not using the internal regulator the pin AVDD_REG has also be connect to 3 3 V to prevent reset blocking The other combinations of the signals TEST1 TEST2 and TEST3 are used for the chip test at the factory process The switching regulator is designed to supply the PHY components It is not allowed to connect addit
26. 1 User s Manual Hardware Appendix B Board Design Information B 3 Board Design Recommendations for Ethernet PHY B 3 1 Supply Voltage Circuitry The on chip PHYs of the TPS 1 require additional filtered operating voltages as shown in the table below Table B 2 Supply Voltages Circuitry for Ethernet PHY Pin Pin Name Function Supply Voltage Generation D14 P1VDDARXTX Analog port RX TX power supply 1 5 V PHY port 1 Must be generated from VDD15 L14 P2VDDARXTX Analog port RX TX power supply 1 5 V PHY port2 15 V via a filter G14 VDDAPLL Analog central power supply 1 5 V H14 VDDACB Analog central power supply 3 3 V Must be generated from VDD33 E12 VDD33ESD Analog test power supply 3 3 V 3 3 V via a filter G13 VSSAPLLCB Analog central GND Must be derived from GND Core lO via a filter or connected to GND Core lO at the far end from TPS 1 D12 AGND Analog GND for PHYs Must be generated from digital D13 GND by filter L12 L13 Besides filtering the PHY specific supply voltages should be equipped with pairs of decoupling capacitors 10 nF and 22 nF capacitors should be used for VDD33ESD VDDAPLL VDDACB and P 2 1 VDDARXTX They should be placed as close as possible to the chip Decoupling with 0 1 uF and 22 uF Power Filters GND VDD15 VDD33 Decoupling with 10 nF and 22 nF as close to the pins as possible Figure B 4 Decoupling capacitors for s
27. 19UH0081ED0104 Rev 1 04 Jul 13 2015 RENESAS page 58 of 80 TPS 1 User s Manual Hardware A 1 2 Serial Interface The serial host interface is an SPI Slave interface The necessary hardware settings are available on tab Host Serial Settings Appendix A Setting of operating modes The watchdog function for the host CPU is configured below the headline General Settings You can choose watchdog time and activity level File Settings Help Gel neral Settings Ident Settings Host Serial Settings Frame Format Ethernet Settings SPICLKPolarity SPICLKPhaseShift SPIHandshakeMode BusyPolarity Motorola SPI y ActiveLow FallingEdge v wait y AciveLow O DADatenablage TPS Development Toolkit P 1 1 3 4 TPS Configurator Example Configuration host_interface_parallel xml Below the headline Host Serial Settings you find the settings for the SPI interface MotorolaSPI Microwire etc gs y Figure A 3 Serial host interface configuration R19UH0081ED0104 Rev 1 04 Jul 13 2015 TENESAS page 59 of 80 TPS 1 User s Manual Hardware Appendix A Setting of operating modes A 2 I O Configuration These settings control the 48 GPIOs and the SPI master interface GPIOs can be set individually or in groups Single or groups of GPIOs can be configured to work as inputs or outputs On the tab Channel you can configure
28. 3 741 824 Data Type Word 32 bits Halfword 16 bits Byte 8 bits Driver Interface TPS 1 Note 3 Listof Abbreviations and Acronyms CSI Clocked Serial Interface FO Fiber Optic FPBGA Fine Pitch Ball Grid Array GND Ground Potential GPIO General Purpose Input Output Input VO or IlO Input Output MISO Master in Slave out SPI signal MOSI Master out Slave in SPI signal MRP Media Redundancy Protocol IEC 61158 O Output PCB Printed Circuit Board PCF Photonic Crystal Fiber PECL Positive Emitter Coupled Logic PLL Phase Locked Loop POF Plastic Optical Fiber POR Power On Reset RJ 45 Ethernet connection copper wire SC RJ Ethernet connection fiber optic SPI Serial Peripheral Interface UART Universal Asynchronous Receiver Transmitter n c Not connected ppm Parts per Million Abbreviation Full Form Application Relation PROFINET terms Communication Relation PROFINET terms Identification amp Maintenance Isochronous Real Time PROFINET operating mode Non Real Time PRFINET terms PROFINET lO Real Time All trademarks and registered trademarks are the property of their respective owners 1 Table of Contents OVERVIEW ss ero ANSA RRA rk ida RAS 8 1 1 FEATURES EEE EE AT AES ASA A O ATTE T A OTE T O ETE 8 LS NC EE 9 1 3 BLOCK DIAGRAM 10 JEN GOJON LOJN Le EE 11 24 SIGNAL OVERVIEW AND DESCRIPTI
29. 4 of 80 TPS 1 User s Manual Hardware 2 Pin function 2 3 Supply Voltage Circuitry The TPS 1 works with three operating voltages VDD15 1 5 V VDD33 3 3 V IO and VDD10 1 0 V core Additionally the on chip PLL for the device clock generation requires a supply called PLL AVDD 1 0 V which is typically a filtered version of VDD10 The integrated PHYs of the TPS 1 require additional filtered operating voltages Table 2 3 Supply Voltage Circuitry Pin Pin Name Function Supply Voltage Generation D14 P1VDDARXTX Analog port RX TX Must be generated from VDD15 L14 P2VDDARXTX power supply 1 5 V via a filter PHY port 1 and port 2 G14 VDDAPLL Analog central power supply 1 5 V PHY H14 VDDACB Analog central power Must be generated from VDD33 supply 3 3 V PHY via a filter E12 VDD33ESD Analog test power supply 3 3 V PHY G13 VSSAPLLCB Analog central GND Must be generated from GND PHY Core lO via a filter or connected to GND Core lO at the far end from TPS 1 C8 VDDQ PECL Bi PECL buffer power M8 VDDQ PECL B2 supply 3 3 V port 1 and port 2 L9 PLL AGND Analog Ground for the internal CPU clock generation L10 PLL_AVDD Power supply for the internal CPU clock generation 1 0V A1 A14 B7 F7 F8 F9 G6 G7 GND Digital GND G8 G9 G10 G12 H6 H7 H8 H9 H10 J2 J6 J7 J8 J9 J12 M10 N7 N10 P1 P14 D12 D13 L12 L13 AGND Analog Ground for PHYs B1
30. After receiving this event it is necessary to check each mail box In the header of the respective mail box the READ FLAG is set The following tables describe the structure of the event register for each direction For each possible event bit in the event register a special callback function is implemented For example the event EVENT ONCONNECT REQ REC 0 bit 13 indicates a Connect Req for the first AR ARO In this case the check function will call in the function OnConnect and process the event R19UH0081ED0104 Rev 1 04 RENESAS page 33 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 4 Shared memory structure 4 2 Events from the TPS 1 firmware to the host Table 4 1 TPS 1 Firmware Events Name Description TPS Event Bits Firmware Stack Host TPS EVENT ONCONNECTDONE ARO Set when a connection for IOARO is established TPS EVENT ONCONNECTDONE AR1 Set when a connection for IOAR1 is established TPS EVENT ONCONNECTDONE AR2 Set when a connection for IOSAR is established TPS EVENT ON PRM END DONE IOARO All parameter available for IOARO TPS EVENT ON PRM END DONE IlOAR1 All parameter available for IOAR1 TPS EVENT ON PRM END DONE IOSAR All parameter available for IOSAR TPS EVENT ONABORT IOARO Connection for IOARO is disconnected TPS_EVENT_ONABORT_IOAR1 Connection for IOAR1 is disconnected TPS_EVENT_ONABORT_IOSAR Connection
31. B14 C7 F6 F10 H2 VDD33 Voltage Supply 3 3 V External N1 N14 P7 P10 A2 A7 A13 F12 K1 K12 M9 VDD15 Voltage Supply 1 5 V form Switching Regulator or P2 P13 external E6 E7 E8 E9 K6 K7 K8 K9 VDD10 Voltage Supply 1 0 V External R19UH0081ED0104 Rev 1 04 RENESAS page 15 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 3 Host Interface 3 Host Interface The host interface is designed to connect external microprocessors These processors access the internal shared memory of the TPS 1 in order to exchange cyclic or acyclic data with the PROFINET IO interface The shared memory has an address space of 64 Kbyte The data exchange is processed with the help of an Event Unit Another way to inform the external host CPU about a new PROFINET status is the integrated interrupt system The parallel interface can be switched to Motorola or Intel mode It is only possible to use the Host parallel interface or the Host serial interface It is not possible to use both at the same time 3 1 Testing DPRAM Interface For testing the DPRAM Interface it is useful to have addresses with defined values After start of the TPS 1 firmware the TPS 1 writes the magic number and the NRT Area Size into the addresses 0x8000 and 0x8004 ARM CPU The application CPU read LOS Bees Number the Magic Number to NRT Area Size recognize the start up of the TPS 1 Figure 3 1 TPS 1 with address page 16 Kbyte 3 2 Parallel Interface
32. BR transceiver provides no differential signal SD active circuitry Vcc 3 3V tolerance 5 SN65LVELT22 TI Figure B 9 Circuitry for the SD Signal Table B 3 SD Signal for Transceiver SD Output COMP OUT SD N SD P No Link 0 0 1 0 Link 1 1 0 1 Using the AVAGO QFBR 5978Z or AFBR 5978Z Transceiver you must ensure the tolerance of the Supply Voltage 3 3V between 5 Note All resistors in this example should have a tolerance of 5 see the exceptions If you want to use the FO diagnostic features you can implement the AVAGO QFBR 5978AZ transceiver For using the special features of this transceiver you must connect the TPS 1 to the transceiver by an I2C bus Receive and transmit lines are compliant to the LVPECL technology These lines must be routed carefully to avoid influence from e g the FC buses The power supply for the AVAGO transceiver is divided into the transmitter and receiver part You need additional electronic components to reduce noise It is important to take care in the layout of the device board to achieve optimum performance from the transceiver It is recommended to add a filter to the power supply for the transmitter and receiver part R19UH0081EDO104 Rev 1 04 RENESAS page 75 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Appendix B Board Design Information VDD33 tolerance 5 10 uF 0 1 uF I Figure B 10 Power Supply for AVAGO Transceiv
33. IP Serialnumber MAC Ethernert MAC Port1 MAC Port2 192 168 16 227 192 168 16 201 0000001234567890 00 A0 45 4C 7E 3A 00 A0 45 4C 7E 39 00 A0 45 4C 7E 38 Send configuration Ethernet Settings Add to clipboard CAProgram Files x86 KW Software TPS Configurator FS_PROG FS_PROG exe D Datenablage TPS Development Toolkit P 1 1 3 ATPS Configurator Example Configurationihost_interface_parallel xml 192 168 16 227 192 168 16 201 00A0454C7E39 00A0454C7E38 00A0454C7E3A 0000001234567890 O DADatenablage TPS Development Toolkit P 1 1 3 4 TPS Configurator Example Configuration host_interface_parallel xml Figure A 8 Writing the TPS 1 configuration By clicking Send Configuration the transfer of the configuration data to the PROPINET IO device is started R19UH0081ED0104 Rev 1 04 Jul 13 2015 TENESAS page 65 of 80 TPS 1 User s Manual Hardware Appendix A Setting of operating modes Ab Generating a complete serial boot Flash Image Vendor Device ID Device Date 18M Information Operating Mode TPS 1 Slot Subslot Configuration etc Compilation Config Block Firmware Block Flash Image FS_prog exe write Factory Settings Firmware Image UART TFTP BOOTP Figure A 9 Generating a Boot Flash Image The generated XML file is compiled and assembled to a Configuration Block the TPS Configurator build the Co
34. JTAG Interface Test Reset pull down L6 TMS JTAG Interface Test Mode Select pull up L7 TDO O JTAG Interface Test Data Output J5 TCK JTAG Interface Test Clock pull up L5 TDI JTAG Interface Test Data Input pull up Reset Test A12 RESETN TPS 1 Reset Global Reset active low H12 ATP Test pin for production test n c H13 EXTRES O External reference resistor 12 4 kQ 1 99 connect to analog GND E10 TMC1 Test Mode Control 1 production test pull down K10 TMC2 Test Mode Control 2 production test pull down D6 TEST 1 IN l Test Pin 1 for hardware test of the TPS 1 pull down D7 TEST 2 IN Test Pin 2 for hardware test of the TPS 1 pull down D8 TESTDOUT5 O Test Data Output 5 High Speed Signals for PHY D9 TESTDOUT6 O Test Data Output 6 High Speed Signals for PHY L8 TESTDOUT7 O Test Data Output 7 High Speed Signals for PHY Host interface Ati WD IN Watchdog input from the Host the rising edge resets the active high watchdog counter of the TPS 1 B12 WD OUT O Watchdog output to the Host active low K11 INT_OUT O Interrupt output to the Host active low Boot interface serial C14 UARTE TX O Boot UART Transmit Data C13 UART6 RX Boot UART Receive Data P12 BOOT 1 l Forced Boot Test signals for switching regulator H3 TESTI Test Pin switching regulator in combination with Test2 3 G3 TEST2 Test Pin switching regulator in combination with Testi 3 E1 TEST3 Test Pin switching reg
35. ON 11 2 2 GPIO MULTIPLEXING 0 a A A E BS e 14 2 3 SUPPELY VOETAGE CIRCUIT RV ii oda dia 15 HOST INTERFACE iii EES degen 16 3 1 TESTING DP RAMINTERRACE SA SAA A NE 16 3 2 PARALLEL INTERFACE 16 3 2 1 Operating modes of the parallel interface 16 3 2 2 Signal description of the parallel interface oooooocccinococonononcnononcnnonnnnnnnnononnnononnon nn nono nn nn nono nn nono nn nono nn nono nn nnnnnnnnnnnnnnnnnnns 1 3 2 3 Memory Segmentation at 4 kByte and 16 kByte page size 3 2 4 Connection example for a 8bit data bus 3 2 5 Connection example fora 16 bit data b scalo akaparo iaj 3 3 SPI SLAVE INTERFACE 3 3 1 Serial access to the shared memory 3 3 2 SPI Slave Interface AA lanoo TEEN Ka aea kadr SSE Kokava dada a ela oa ITa NAA 3 3 3 SPI Slave Interface Reset Timing SHARED MEMORY STRUCTURE ciao iii Eri E A a AA tdt 31 4 1 EVENT COMMUNICATION WITH THE TPS 1 FIRMWARE 4 2 EVENTS FROM THE TPS 1 FIRMWARE TO THE HO 4 3 EVENTS FROM THE HOST TO THE TPS 1 FIRMWARE nena nene nn nene r r e nene nene e r nenenenenenenenenenenenennnes 4 4 INTERRUPT COMMUNICATION WITH THE TPS 1 4 4 1 How to generate an interrupt by an event 4 5 STATUS LEDS OF THEE PS Bit da A a A da data cd TPS BOOT SUBSYSTEM za sati a e e ee 41 al HARDWARE STRUCTURE FOR THE BOOT OPERATION eretet eretet etere E EEE PEPEEEEEEEPEEE PEPEPEPE EErEE EEEren ereraa eneee 5 2 LOADING AND UPDATE OF THE FIRMWARE DURING THE MANUFACTURING PROCESS
36. a GRM32ER71A226KE20L Ria Resistor 100 MO 1 Evaluated with MCR18EZHFLR100 ROHM To avoid the recommended tantalum capacitor it is possible to compose the needed characteristics with a series connection of a resistor and a ceramic capacitor If you use ceramic capacitors only C1 has to be replaced by a ceramic capacitor in connection with a series resistor C2 did not need a series resistor R19UH0081EDO104 Rev 1 04 RENESAS page 68 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Appendix B Board Design Information Ria e L D gt T Cla Figure B 2 Change Tantalum to Ceramic Capacitor B 2 2 Layout Example for Switching Regulator This chapter shows an example for the connection between the external output and regulator The real design of the layout must be done on the PCB board TPS 1 AVDD BVDD Nu 7 Pattern Switching Regulator Input Pin J1 3 3V BVDD M LX Pattern VOUT Pattern Regulator Ouput 1 5V LX Connection to VDD15 Pin H1 Powerplane GND for Switching BGND G1 Regulator AGND_REG G2 DEE e 22 uF Tantal GND Pattern mg E 22 uF Tantal D1 AVDD_REG F2 Feedback Regulator FB Pin F1 Figure B 3 Switching Regulator layout example Instead of the tantalum capacitors you can also use ceramic capacitors Please refer to chapter B2 1 R19UH0081ED0104 Rev 1 04 RENESAS page 69 of 80 Jul 13 2015 TPS
37. aces with software tool configuration data are stored in a boot Flash R19UH0081ED0104 Rev 1 04 RENESAS page 8 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 1 Overview 1 2 Abstract The PROFINET Device Chip TPS 1 is designed for easy and cost efficient implementation of PROFINET interfaces for automation devices It is a highly integrated single chip solution that meets all requirements of the PROFINET protocols The configurable host interfaces facilitate the flexible realization of different use cases like direct connection of an external host CPU or digital I Os without additional circuitry The TPS 1 complies with PROFINET Conformance Class C The integrated components realize the complete interface functionality The internal structure is designed to fulfill the requirements of the IRT protocol Special synchronous signals are available to realize all synchronization tasks To support line topologies in PROFINET networks the TPS 1 is equipped with two integrated PHYs and an integrated IRT switch Time critical PROFINET protocols are supported by hardware For the complete implementation of a PROFINET device interface only the TPS 1 a serial Flash device an oscillator and the physical adaptations for the Ethernet interface transformers and connectors are needed The serial Flash component contains the individual chip configuration and firmware for the PROFINET CPU Due to the low space requirement and low power dissipation of th
38. al 5 isochronous mode IRT D11 T6 O Clock signal 6 isochronous mode IRT LED signals device status PROFINET B13 LED BF_OUT O Control LED Bus Failure active low B11 LED SF OUT O Control LED System Fail active low C10 LED READY OUT O Control LED Device Ready active low B10 LED MT OUT O Control LED Maintenance active low PHY Port 1 C9 126 1 D INOUT 1 0 Fiber Optic Port 1 I C Bus Data e g SC RJ C6 SCLK 1 INOUT O Fiber Optic Port 1 I C Bus Clock e g SC RJ C12 LINK PHY1 O LINK indication ETHERNET Port 1 up or down active high D10 ACT PHY1 O Activity ETHERNET Port 1 active high F13 Pi TX P O ETHERNET Port 1 transmit data positive e g RJ45 F14 P1 TX N O ETHERNET Port 1 transmit data negative e g RJ45 E13 Pi RX P ETHERNET Port 1 Receive Data positive e g RJ45 E14 Pi RXN l ETHERNET Port 1 Receive Data negative e g RJ45 B8 Pi SDP Fiber Optic Port 1 Signal Detect positive e g SC RJ A8 Pl SDN Fiber Optic Port 1 Signal Detect negative e g SC RJ B9 Pi RD P Fiber Optic Port 1 Receive Data positive e g SC RJ AQ Pi RDN Fiber Optic Port 1 Receive Data negative e g SC RJ B6 Pi TD OUT P O Fiber Optic Port 1 Transmit Data negative e g SC RJ A6 Pi TD OUT N O Fiber Optic Port 1 Transmit Data positive e g SC RJ A5 Pi FX EN OUT O Fiber Optic Port 1 Transmitter enable active high e g SC RJ PHY Port 2 M11 l2C 2 D INOUT I O Fiber Optic Port 2 12C Bus Data e g SC RJ L11 SCLK 2
39. al IO Interface There you can choose the IO interface serial or parallel digital outputs When you choose one of the four operation modes from the General Settings only that operation mode will be activated and the values can be modified Other operation modes will be deactivated and their values can be viewed but not modified The configuration data and the firmware are stored into the serial boot Flash device During each start up the configuration is used to initialize the TPS 1 The necessary MAC Addresses are permanently stored on the Flash Device They cannot be changed after the initial setting see Ethernet Settings tab al TPS Configurator File Settings Help General Settings Ident Settings I HostParallel Settings Ethernet Settings Operation Mode Port1 Port2 9 Host Interface parallel 9 Interface RJ45 9 Interface RJ45 Watchdog Time ms 100 Host Interface serial Interface SC RJ Interface SC RJ Watchdog Polarity AciveLow v 3 IO Serial FO Diagnosis FO Diagnosis 10 Parallel Interface Off Interface Off IM_Para_1 VendorID DevicelD OrderD 0x 174 ox 1234 1234567 RENESAS O DADatenablage TPS Development Toolkit P 1 1 3 4 TPS Configurator Example Configuration host_interface_parallel xml Figure A 1 First tab of the TPS Configurator The configuration items on tab General Settings set the basic operation modes
40. al application profile this parameter contain information about the usage of its channels and or sub devices IM VERSION This parameter indicates the implemented version of the 18M functions IM SUPORTED This parameter indicates the availability of ISM records All parameters must be edited separately or can be copied as default values from the firmware If you need more information regarding I MO parameters please refer to the PROFINET specification R19UH0081ED0104 Rev 1 04 Jul 13 2015 RENESAS page 63 of 80 TPS 1 User s Manual Hardware A 3 Ethernet Interface Configuration Appendix A Setting of operating modes The Ethernet configuration is edited on tab Ethernet Settings This is also the window for configuring the factory settings e g MAC addresses File Settings Help Destination IP Source IP Serialnumber MAC Ethernert MAC Port 1 MAC Port2 Generate command 192 168 16 227 192 168 16 201 0000001234567890 00 A0 45 4C 7E 3A 00 A0 45 4C 7E 39 00 A0 45 4C 7E 38 Send configuration Add to clipboard RENESAS PER O DADatenablage TPS Development Toolkit P 1 1 3 4 TPS Configurator Example Configurationihost_interface_parallel xml The TPS 1 needs three MAC addresses to operate One is used for the TPS 1 itself additionally each of the two ports has an individual Figure A
41. al detect Difference P9 P2 RDN Receive signal Difference N9 P2 RD P Receive signal Difference P5 P2 FX EN OUT Transmitter enable transceiver output N6 P2 TD OUT P Transmit signal Difference P6 P2_TD_OUT_N Transmit signal Difference 8 3 I2C Bus LWC Diagnostic The TPS 1 provides two EC Interface Lines for fiber optics diagnostic purposes The recommended AVAGO transceiver AFBR 5978Z features 8 PROFINET IO switch internal registers that can be read by the FC interface The transceiver can deliver diagnostic information via the PC interface If signal quality is dropping an alarm indication can be sent to the controller Table 8 6 PC interface lines Pin Signal TPS 1 Description CO I2C 1 D INOUT Fiber Optic Porti FC Bus Data C6 SCLK 1 INOUT Fiber Optic Port1 1 C Bus Clock M11 I2C 2 D INOUT Fiber Optic Port2 1 C Bus Data 111 SCLK 2 INOUT Fiber Optic Port2 C Bus Clock R19UH0081ED0104 Rev 1 04 Jul 13 2015 tENESAS page 50 of 80 TPS 1 User s Manual Hardware 8 PROFINET IO switch 8 4 Additional TPS 1 pins The pins ATP and EXTRES are used for PHY1 and PHY2 Table 8 7 Additional TPS 1 pins Pin Designation UO Description H12 ATP Al O analog I O Analog Test This signal is used for the manufacturing process Pin is left open H13 EXTRES AI O analog I O Reference resistor Connect via a resistor 12 4KQ 1
42. but not limited to the development of weapons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations It is the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 2012 4 Instructions for the use of product In this section the precautions are described for over whole of CMOS device Please ref
43. data J14 P2_TX_N Transmit data K13 P2 RX P Receive data K14 P2 RXN Receive data 8 2 100Base FX interface Fiber Optic The physical transmission complies with the standard e IEEE 802 3 Clause 26 100 Mbit s Ethernet for multimode fiber optic The connection of fiber optic wiring POF und PCF should be done with Fiber Optic Diagnostic Transceivers Avago Technologies QFBR 5978AZ this transceiver fulfilled the requirements for the automation industry These devices provide the medium conversion and line diagnostics R19UH0081EDO104 Rev 1 04 RENESAS page 49 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 8 2 1 100Base FX interface Port 1 Table 8 4 Signal lines 100Base FX interface Port 1 Pin Designation Description c9 12C_1_D_INOUT DC data line C6 SCLK 1 INOUT FC clock line B8 Pil SDP Signal detect Difference A8 Pl SDN Signal detect Difference A9 Pi RDN Receive signal Difference B9 P1 RD P Receive signal Difference A5 P1 FX EN OUT Transmitter enable transceiver output B6 P1 TD OUT P Transmit signal Difference A6 P1_TD_OUT_N Transmit signal Difference 8 2 2 100Base FX interface Port 2 Table 8 5 Signal lines 100Base FX interface Port 2 Pin Designation Description M11 12C_2 D_INOUT DC data line L11 SCLK 2 INOUT C clock line N8 P2 SD P Signal detect Difference P8 P2 SDN Sign
44. dentifier API e It is only one module slot possible e It is only one submodule subslot possible e The input output and diagnostic bits must be in a connected order e You must always choose groups in byte range 8 16 24 32 etc The TPS Configurator supports the configuration of the IO Local Parallel Interface Refer Appendix A Configuration of the IO Local Parallel Interface 6 1 GPIO digital input and output The I O interface supports 48 GPIOs General Purpose Inputs Outputs The GPIOs can be used for digital IOs Each pin can be used individually or in combination with other pins Parallel use of the GPIOs and the host interface is not possible Unused GPIO pins should be pulled up 10 k to VCC33 Refer chapter2 note 2 to this R19UH0081ED0104 Rev 1 04 RENESAS page 45 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 7 TPS 1 Watchdog 7 TPS 1 Watchdog The TPS 1 contains two watchdog controllers One is used to control the PROFINET CPU The other shall be used to control the connected Host CPU The signals WD IN and WD OUT are used by the host CPU and the TPS 1 for mutual supervision and to force a restart if necessary Table 7 1 Watchdog signals Pin Signal TPS 1 Description Remark A11 WD IN Watchdog Input This signal triggers the TPS 1 watchdog that monitors the Host from the Host CPU A rising edge of this signal restarts the watchdog counter B12 WD_OUT Watchdog Output This
45. direct connection of SPI Slaves to exchange process data e 48 GPIO for direct connection of digital peripheral signals digital I Os e Serial Flash interface e Support of PROFINET IO communication channels NRT RT and IRT e Watchdog support for connected host CPUs e Compliance with PROFINET Conformance Class C e Hardware support for time critical PROFINET protocols including PTCP with LLDP e Firmware download during the manufacturing process via JTAG Boundary Scan interface Ethernet or UART interface e Firmware update via Ethernet interface with BOOTP TFTP e Easy configuration of host interfaces and GPIOs e 2 Fast Ethernet Ports with integrated PHYs 100 Mbit full duplex data transmission IRT Bridge Delay lt 3 usec Auto Negotiation Auto Cross Over Auto Polarity Support for 100Base TX and 100Base FX ports Monitoring of fiber optic transmission links with integrated 1 C interfaces e Power dissipation around lt 1 W Host Interface e Serial SPI up to 25 MHz and parallel 8 or 16 bit interface for use with an external host CPU e Data exchange cyclic and acyclic with external host via integrated Shared Memory Area event and interrupt controlled e 340 Byte maximum data for cyclic exchange inclusive IOxS e One application relation available firmware version 1 1 e The TPS 1 firmware allows a up to 64 Slot Subslots e g 1 Slot with up to 64 Subslots e Configuration of all host interf
46. dware 5 TPS 1 boot subsystem 5 2 2 1 SPI Command Set A SPI memory device must support the following commands Writing to the flash requires the command Sector Erase SE It must be possible to write sectors with a size of 4 Kbyte Table 5 3 SPI Boot Loader Driver Commands Instruction Code Address bytes Dummy bytes Data bytes Write enable 0x06 0 0 0 Write disable 0x04 0 0 0 Read status register 0x05 0 0 1 Read Data 0x03 3 0 1 0 Page Program 0x02 3 0 1 to 256 Sector Erase 4KB 0x20 3 0 0 Chip Bulk erase OxC7 0 0 0 Read Identification Ox9F 0 0 3 This command requires a sector size of 4 Kbyte 5 2 2 2 SPI Flash Timing Requirements eff JIVE PP ae a Figure 5 2 Serial Flash output timing requirement CLK CS Chip select input of serial Flash device CLK Clock input of serial Flash device DO Data output of serial Flash device DI Data input of serial Flash device tCLQV Clock low to output valid time max 8 ns R19UH0081ED0104 Rev 1 04 RENESAS page 44 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 6 IO Local GPIO Interface 6 IO Local GPIO Interface For the development of small IO Devices the TPS 1 offers the IO Parallel Interface with a maximum of 48 IO lines These lines could be used for input output and diagnostic purposes There are some restrictions when using the IO Local Parallel interface e You can have only one Application I
47. e ARO is reported APP EVENT ALARM SEND REQ AR1 Set when an alarm for the ARI is reported APP EVENT ALARM SEND REQ AR2 Set when an alarm for the AR2 is reported APP EVENT RESET STACK CONFIG APP EVENT ETH FRAME SEND A TCP IP Ethernet frame MAC should be send from the mailbox APP EVENT WRITE INPUT DATA Process data written APP EVENT READ OUTPUT DATA Process data read APP EVENT RESET PN STACK Host CPU forces a software reset of the TPS 1 R19UH0081ED0104 Rev 1 04 Jul 13 2015 tENESAS page 35 of 80 TPS 1 User s Manual Hardware 4 Shared memory structure 4 4 Interrupt Communication with the TPS 1 The communication between the TPS 1 and the Host CPU is processed by the Event Unit If you want to use the interrupt control you need the registers shown in Table 4 3 Table 4 3 Event Register List Register Name Read Write Offset Address Host IRQ low R 0x0008 Host_IRQ_high R 0x000C Host IRQmask low RW 0x0010 Host_IRQmask_high RW 0x0014 Host_IRQack_low W 0x0020 Host_IRQack_high AN 0x0024 Host EOl R W 0x0028 PN Event low RAW 0x003C PN_Event_high R W 0x0040 4 4 1 How to generate an interrupt by an event The following steps are necessary for generating an interrupt from an occurring event 1 Set the mask register low or high 2 Acknowledge an Interrupt by deleting the event bits 3 Write the Host
48. e TPS 1 a PROFINET interface can also be integrated into automation devices with special requirements regarding housing size and protection classes Conductor routing between the balls is still possible in order to keep down PCB cost Flash SP I Slave TPS 1 Application PROFINET CPU Device Chip Media Dependent Interface Media Dependent l Interface Port 1 Port 2 l l BIE EI Figure 1 1 TPS 1 Overview R19UH0081EDO104 Rev 1 04 RENESAS page 9 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 1 Overview 1 3 Block Diagram The block diagram shows the internal structure and main components of the TPS 1 The additional serial boot Flash component the oscillator and the physical adaptation for the Ethernet interfaces are not listed Serial Flash SPI Slave JTAG Debug PROFINET CPU Host Interface Parallel Serial ARM Core 48 GPIO Status Info LEDs Control Signals Clock Signals T1 to T6 Power Supply Switching Regulator MDI Link1 Act1 Link2 Act2 MDI l Test Sync 25 MHz 3 3 V Figure 1 2 TPS 1 Block Diagram The TPS 1 contains the PROFINET CPU the PROFINET core the I O interface and the Host Interface for connecting a host CPU The PROFINET core processes the PROFINET communication All time critical services are implemented in hardware to realize high performance The communication between an external hos
49. e are structure errors the TPS 1 firmware does not start The host interface and the NRT area are accessible in a continuous address space NRT Area Access Library PROFINET agron or serial STACK Input Output Area SWITCH Figure 4 2 General overview host interface Access to the NRT area and Input Output area is processed with the support of a software library The memory area shared memory is used for the access to acyclic and cyclic data The size depends on the device Exchange of the cyclic data is managed in the peripheral interface input output area The structure of this area is fixed It is possible to manage one AR Application Relations in the first release e one l Data CR e one O Data CR The IO data has a maximum size of 340 Byte cyclic data R19UH0081ED0104 Rev 1 04 RENESAS page 32 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 4 Shared memory structure 4 1 Event communication with the TPS 1 Firmware After system start up the communication between the TPS 1 and the host CPU is processed by the event register one register for each direction Each bit of the event register causes a special action Figure 4 3 TPS 1 Event Communication For process changes of the event register the TPS 1 and the host CPU has to poll these registers You can also use an interrupt control mode if the host CPU supports this The event bits corresponding to the mail box access are not ambiguous
50. en into the Boot Flash and is active after the next restart The watchdog interval can be chosen between 1 ms and 512 ms During the development you can disable the Host CPU watchdog by setting the interval value to 0 TPS Configurator Be aware that the watchdog must be activated to avoid unsecure operations of the device ES a HostWatchdogTime Figure 7 2 Watchdog Characteristics R19UH0081EDO104 Rev 1 04 RENESAS page 47 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 8 PROFINET IO switch 8 PROFINET IO switch The TPS 1 contains a PROFINET switch with 2 external ports Thus PNIO devices can be connected directly to each other without the need for external switching devices line topology Figure 8 1 Network topologies with the TPS 1 All necessary PROFINET protocols are implemented LLDP PTCP MRP etc Additionally the TPS 1 features 2 integrated PHY devices IEEE 802 3 IEEE802 3u ANSI X3 263 1995 and ISO IEC93 14 Each port of the integrated PROFINET switch has its own MAC address The MAC addresses are provided by the device manufacturer and stored in the Boot Flash of the TPS 1 The implemented hardware processes support all PROFINET communication channels NRT RT and IRT The Ethernet standards 100B ASE TX and 100BASE FX are supported Additionally the PHYs support the following features e Auto Negotiation e Auto Crossing e Auto Polarity In order to indicate network statu
51. ent Bit Stack Events high active events Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 TPS_EVENT_ONCONNECTDONE_IOARO TPS_EVENT_ONCONNECTDONE_IOAR1 TPS_EVENT_ONCONNECTDONE_IOSAR TPS_EVENT_ON_PRM_END_DONE_IOARO TPS_EVENT_ON_PRM_END_DONE_IOAR1 TPS_EVENT_ON_PRM_END_DONE_IOSAR TPS_EVENT_ONABORT_IOARO TPS_EVENT_ONABORT_IOAR1 TPS_EVENT_ONABORT_IOSAR TPS_EVENT_ONREADRECORD Bit 10 TPS EVENT ONWRITERECORD Bit 11 TPS EVENT ONALARM ACK 0 Bit 12 TPS EVENT ONDIAG ACK Bit 13 TPS EVENT ONCONNECT REQ REC 0 Bit 14 TPS EVENT ONCONNECT REQ REC 1 Bit 15 TPS EVENT ONCONNECT REQ REC 2 Bit 16 TPS EVENT ON SET DEVNAME Bit 17 TPS EVENT ON SET IP PERM Bit 18 TPS EVENT ON SET IP TEMP Bit 19 TPS EVENT ONDCP BLINK START Bit 20 TPS EVENT ONDCP FACTORY RESET Bit 21 TPS EVENT ONALARM ACK 1 Bit 22 TPS EVENT RESET Bit 23 TPS EVENT ETH FRAME REC Bit 24 31 reserved for further use 0X00000000 R19UH0081ED0104 Rev 1 04 Jul 13 2015 RENESAS page 37 of 80 TPS 1 User s Manual Hardware 4 Shared memory structure One or more bits written in to these registers low and high process an external interrupt event INT OUT A new one will influence no bits set before Table 4 6 Register Host IRQmask low Name Host IRQmask low Address 0x0010 Access r w Bits Type of Event Description Init 31 00 IRQ Bits 0 the Ev
52. ent is registered in PN Event low OxFFFFFFFF 1 the Event is not registered in PN_Event_low Table 4 7 Register Host IRQmask high Name Host IRQmask high Address 0x0014 Access r w Bits Type of Event Description Init 31 00 IRQ Bits 0 the Event is registered in PN Event high OxFFFFFFFF 1 the Event is not registered in PN_Event_high After processing an event the corresponding bit must be acknowledged by writing of acknowledgment register Host_IRQack_low and Host IRQack high Table 4 8 Register Host IRQack low Name Host IRQack low Address 0x0020 Access w Bits Type of Event Description Init 31 00 Ack Bits 0 the Event Bit is not deleted in PN_Event_low 1 the Event Bit is deleted in PN_Event_low Table 4 9 Register Host_IRQack_high Name Host_IRQack_high Address 0x0024 Access w Bits Type of Event Description Init 31 00 Ack Bits 0 the Event Bit is not deleted in PN_Event_high 1 the Event Bit is deleted in PN Event high R19UH0081EDO104 Rev 1 04 RENESAS page 38 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 4 Shared memory structure You can verify the interrupt event sources by reading the Host IRQ low and Host IRQ high register Each bit corresponds with a masked event A bit set to 1 shows a masked bit Table 4 10 Register Host_IRQ_low
53. er It is further recommended that a contiguous ground plane is provided in the device board directly under the transceiver to provide a low inductance ground for signal return current The ground plane for the receiver and transmitter should also be divided and connected with a filter During the operation of the transceiver peaks on the supply voltage can occur so it is useful to add additional capacitors see also the data sheet of the transceiver R19UH0081ED0104 Rev 1 04 RENESAS page 76 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Appendix B Board Design Information B 3 5 Unused 100Base FX interface Figure B 11 shows the wiring of an unused Fiber Optic Transceiver The interface uses PECL lines Ifa 100Base FX interface is not used the pins Pr TD OUT P and Px TD OUT Ncan remain open no Pull Up or Pull Down resistor necessary All other signals should be connected to GND level Px TD OUT P open Px TD OUT Figure B 11 Unused pins at 100Base FX interface R19UH0081ED0104 Rev 1 04 RENESAS page 77 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Appendix C Fast Start Up Requirements Appendix C Fast Start Up Requirements Prioritized startup refers to the PROFINET function for accelerating the startup of IO devices in a PROFINET IO system with RT and IRT communication It shortens the time that the respective configured IO device requires in order to reach the cyclic user data exchange The p
54. er to this manual about individual precaution When there is a mention unlike the text of this manual a mention of the text takes first priority 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to rese
55. esign Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including
56. for the Switching Regulator The following figure gives the recommendation of the wiring The switching regulator output LX delivers the 1 5 V voltage that is smoothed with the external devices This voltage is connected to pin Vpp 5v The following external devices are necessary for the switching regulator Figure B 1 shows the wiring for the external regulator circuit if the regulator is used to generate the 1 5 V for the PHYs Notes All components should be placed as close as possible to the TPS 1 Important The characteristic of C1 is mandatory A lower ESR will cause problems with the regulator oscillation TPS 1 Switching Regulator Input VDD 3 3V Pin J1 3 3V BVDD C2 22 uF Ceramic or Regulator Ouput 1 5V LX Tantalum Pin H1 Ci 22 uF GND for Switching BGND G1 Tantal Regulator AGND REG G2 T digital GND Feedback Regulator FB Pin F1 Supply 1 5V Input Pin K1 VDD15 Figure B 1 Wiring of the switching regulator Table B 1 Part Table for the Switching Regulator Part Type Characteristics Recommended components C1 Tantalum Capacitor 22 uF 20 PSLB21A226M NEC TOKIN ESR 150 350 mQ TCJB226M010R0300 AVX T494C226K016AT KEMET C2 Capacitor 22uF 20 Ceramic or Tantalum D1 Schottky Rectifier 30V 1A SBS005 Sanyo Diode STPS1L30UPBF ST L1 Inductor 10 uH VLCF5028T TDK Cla Ceramic Capacitor 22 uF 10 Evaluated with Murat
57. interface is reduced to a minimum and has no modem lines Table 5 1 Boot UART lines Pin Signal TPS 1 Description C14 UART6_TX Boot UART Transmit data C13 UART6_RX Boot UART Receive data P12 BOOT_1 Forced Boot Value Function 0x0 BROM Boot from Boot Flash is enabled normal operating mode 0x1 UART Boot via UART is enabled The signal line BOOT_1 Forced Boot forces a firmware update For this update the UART interface is used In this case also a corrupt version can be updated The following parameters are set fix for the Interface e Baudrate 115200 baud e 8 bit data length e I stop bit e no parity check e no hardware flow control R19UH0081EDO104 Rev 1 04 RENESAS page 42 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 5 TPS 1 boot subsystem 5 2 2 SPI master interface Boot Flash The TPS 1 has one SPI master interface for connecting a serial Flash device The Flash contains the TPS 1 firmware as well as the device configuration and the three required MAC addresses The operation of this interface is managed by the boot loader The interface operates at a maximum speed of 25 MHz This speed is necessary to realize the device fast startup function with the TPS 1 It is necessary to have a delay time clock low to data valid not greater than 8 ns The Flash contains the TPS 1 firmware as well as the device configuration and the three required MAC addresses
58. ional components You will find a recommendation for the circuitry of the switching regulator in the Chapter Board Design Information Switching Regulator Table 8 8 Switching regulator operating modes describes the different modes of the switching regulator Table 8 8 Switching regulator operating modes TESTS Pin E1 TEST2 Pin G3 TEST1 Pin H3 Function 0 Normal mode Regulator and POR on Only POR mode Regulator off POR on 1 0 Regulator and POR circuitry switched off Note Other options reserved for test Note This combination should be avoided because you set the TPS 1 permanently into the reset state R19UH0081ED0104 Rev 1 04 RENESAS page 51 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 8 PROFINET IO switch It is important that the input FB is connected to a smoothed 1 5 V voltage The regulator adjusts the output voltage with negative feedback using this pin BVDD 3 3 V Chip Supply Pin J1 LX 1 5 V Output Triangle Wave Pin H1 Generator AGND BGND Pin G1 FB Feedback Pin F1 Band Gap Reference Circuit AVDD REG 3 3 V Chip Supply Pin F2 i E chip internal use interna Figure 8 2 Internal voltage regulator The time of power supply rise to the point where all power supplies are stabilized must be reached within 100 ms The typical behavior of the power supplies is shown in Figure 8 3 V VDD3 3v 3 0V 2 0V VDD1 5v
59. l xml Figure A 6 IO Local Parallel Interface Mask R19UH0081EDO104 Rev 1 04 RENESAS page 62 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Appendix A Setting of operating modes A 2 3 I MO Configuration l MO data The provision of these parameter values is mandatory for every PROFINET device I amp M0 profile Table A 1 I M0 Parameter Parameter Description VENDOR ID The parameter VENDOR ID carries the ID of the respective device manufacturer It is assigned by PI ORDER ID This parameter contains the complete order number or at least a relevant part that allows unambiguous identification of the device module within the manufacturer s web site SERIAL NUMBER A serial number is a unique production number of the device manufacturer even for devices with the same hardware software or firmware edition Hardware Revision The content of this parameter characterizes the edition of the hardware only Software Revision The content of this parameter characterizes the edition of the software or firmware of a device or module REVISION COUNTER A changed value of the REVISION COUNTER parameter of a given module marks a change of hardware or of its parameters PROFILE ID A module providing a special application profile may contain extended information PROFILE SPECIFIC TYPE about its function and or sub devices e g HART PROFILE SPECIFIC TYPE In case a module provides a speci
60. meaning of SPI data is defined by the implementation of the SPI slave The following chapter describes the structure of the SPI slave commands Table 3 7 SPI header structure Header Data Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 max Command Address Address Length Length 1 Byte 1 Byte 1 Byte 1 Byte 1 Byte 1 Byte max length Shared Memory An indirect command contains the length information in byte 3 and 4 A direct command contains the length information in the bits 0 to 3 of the command byte The maximum address access is limited to 15 byte R19UH0081ED0104 Rev 1 04 RENESAS page 24 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 3 Host Interface 3 3 1 2 Structure of a command byte Figure 3 8 shows the format ofa command byte A command byte can be followed by an address area length area and data ECCEECCEED E Direct IO Length s E EE q EEE OO a b6 1 write i b7 1 read Figure 3 9 Command byte for SPI slaves host interface The bits of the command byte have the following meaning D b7 indicates a read command D b6 indicates a write command b5 and b4 describe the addressing range 00 MEM access to the complete shared memory 64 Kbyte O1 IO access to the input output area 10 access to a multicast provider CR only write 11 fractional access to an I CR b6 1 or MC CR b6 0 b3 bO contain the length for an
61. nfiguration Block that is transferred The configuration data is then copied to the TPS 1 and stored into the serial boot Flash device Factory Settings Block On the TPS 1 special software is running that enables you to copy a firmware image into the serial boot Flash device The firmware block can be copied from every directory on your PC R19UH0081ED0104 Rev 1 04 RENESAS page 66 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Appendix B Board Design Information Appendix B Board Design Information This chapter provides useful information related to PCB design B 1 Voltage supply The TPS 1 requires 3 supply voltages The necessary supply voltages can be delivered directly from the power supply unit In this case the switching regulator is not needed refer Chapter8 5 You can also use the integrated voltage regulator that is fed with 3 3 V The recommended circuitry described in AppendixB 2 Necessary supply voltages of the TPS 1 e 3 3 V nominal between 3 0 V and 3 6 V e 1 5 V nominal between 1 35 V and 1 65 V e 1 0 V nominal between 0 9 V and 1 1 V core voltage B 2 Switching Regulator Switching regulator features e Output voltage 1 1 5V 5 e Output current 250 mA max DC e Power supply voltage 3 3V 0 3V e Switching frequency 1 MHz typ R19UH0081ED0104 Rev 1 04 RENESAS page 67 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Appendix B Board Design Information B 2 1 Wiring
62. ng the manual These notes occur within the body of the text at the end of each section and in the Usage Notes section The revision history summarizes the locations of revisions and additions It does not list all revisions Refer to the text of the manual for details The following documents apply to the TPS 1 Make sure to refer to the latest versions of these documents The newest versions of the documents listed may be obtained from the Renesas Electronics Web site Document Type Data Sheet Description Hardware overview and electrical characteristics Document Title TPS 1 Datasheet Document No R19DS0069EJ User s manual for Hardware User s manual Hardware specifications pin assignments memory maps peripheral function specifications electrical characteristics timing charts and operation descriptiont TPS 1 User s Manual Hardware This User s manual User Manual TPS 1 Note Driver Manual TPS 1 API functions Note These documents are available from Phoenix Contact Software 2 Notation of Numbers and Symbols Note Explanation of Note in the text Caution Item deserving extra attention Remark Supplementary explanation to the text Numeric notation Binary XXXb Decimal XXXX Hexadecimal XXXXH or 0x XXXX Prefixes representing powers of 2 address space memory capacity k kilo 210 1024 M mega 220 10242 1 048 576 G giga 230 10243 1 07
63. ns Not allowed An illegal access results in an Error IRQ from the event unit R19UH0081EDO104 Rev 1 04 RENESAS page 18 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 3 Host Interface 3 2 3 Memory Segmentation at 4 kByte and 16 kByte page size You decide the page size with the TPS Configurator A connected Host CPU selected the pages with the LBU SEGx IN signals Table 3 5 shows the page decoding Table 3 5 Page selection with LBU SEGx IN signals LBU_SEG 1 0 Selected Page 00 Page 00 01 Page 01 10 Page 02 11 Page 03 The segmentation with 16 Kbyte pages is shown in Figure 3 3 With 16 address lines you can reach the whole 64 kByte address space 16 K Page Size 0x0000 Page 00 0x2000 0x4000 Page 01 NRT Area 0x8000 Page 02 0xC000 Page 03 OxFFFF Figure 3 4 16 kByte page size R19UH0081ED0104 Rev 1 04 RENESAS page 19 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 3 Host Interface Using the 4 kByte address pages limits the available address space of the NRT area Figure 3 4 shows the pages You can reach the complete Event Unit and the complete IO RAM Out of the NRT area you can only use the address space between 0x8000 and Ox9FFF 4 K Page Size 0x0000 0x1000 Page 00 0x2000 Page 01 0x3000 NRT Area 0x8000 Page 02 0x9000 Page 03 Ox9FFF OxFFFF Figure 3 5 4 kByte page size Because of the page size it is not possible to use the ma
64. optimized direct data access 0000 no direct access 0000 direct access length information maximum of 15 byte R19UH0081ED0104 Rev 1 04 RENESAS page 25 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 3 Host Interface 3 3 1 3 Command overview The SPI commands are optimized for the use with PROFINET The following table describes the implemented commands Table 3 8 Implemented SPI commands DirectMEM Access This gives the external host CPU access to the complete address space of 64 Kbyte Each access transfers not more than 15 byte The length is coded in the command byte Command Description Command code Number of address bytes Number of length bytes Number of data bytes Read MEM Direct Reads from the transferred address The length is coded in the command byte 0b1000_nnnn Ox8n 1 15 Write MEM Direct MEM Access Writes to the transferred address The length is coded in the command byte 0b0100_nnnn Ox4n With this command the external host CPU can read from and write to the complete 64 Kbyte address space with a maximum data length of 64 Kbyte access to cyclic and acyclic data Command Description Command code Number of address bytes Number of length bytes Number of data bytes Read MEM Reads from the transferred address The length is coded in the length byte Ob1000 0000 0x80 1 32K 64K
65. or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for Which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance d
66. ost interface at the same time Alternate Use Description Write Enable Read Enable Chip Select Byte Selection low Byte Selection high Ready Signal TPS 1 Note 1 Note 2 Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Address Bit Address Bit Address Bit Address Bit Address Bit Address Bit Address Bit Address Bit Address Bit Address Bit Address Bit Address Bit Address Bit Address Bit Segment choice 1 Segment choice 2 Reset Host SPI Interface Start new SPI Transfer SPI receive data SPI Clock SPI transmit data Header recognized SPI Clock SPI master lO interface SPI Chip Select SPI master IO interface SPI receive date SPI master lO interface SPI transmit data SPI master lO interface Note 1 The LBU READY OUT is designed to connect only to one microcontroller If you want to connect additional devices you must add circuitry to realize the high impedance state Note 2 If your processor does not have a READY Input you can choose a wait time of 80 ns 8 CPU cycle during each transfer cycle R19UH0081ED0104 Rev 1 04 Jul 13 2015 tENESAS page 1
67. ot assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products
68. rface parallel xxml Figure A 5 Parallel Interface configuration part 2 R19UH0081ED0104 Rev 1 04 RENESAS page 61 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Appendix A Setting of operating modes A 2 2 IO Local Interface For the development of small IO Devices the TPS 1 offers the IO Parallel Interface with a maximum of 48 IO lines These lines could be used for input output and diagnostic purposes There are some restrictions when using the IO Local Parallel interface e You can have only one Application Identifier API e Iltis only one module slot possible e Itis only one submodule subslot possible e The input output and diagnostic bits must be in a connected order e You must always choose groups in byte range 8 16 24 32 etc The TPS Configurator supports the configuration of the IO Local Parallel Interface You can set all necessary parameters for the IO Local Parallel Interface e g API SlotNumber ModuleldentNumber etc On the next program tap you can configure the diagnostic channels File Settings Help General Settings Ident Settings 10 General Settings lO Parallel Settings Diag Channel l Ethernet Settings ModuleldentNumber SubslotNo SubModuleldentNumber x 1 Ox 20 StartGPIOPinForDiagChannel RENESAS asd O D Datenablage TPS Development Toolkit P 1 1 3 4 TPS Configurator Example Configurationihost_interface_paralle
69. roperty prioritized startup demanded a startup time less than 500 ms If you want to realize this feature be aware that the complete device TPS 1 and you own Application must come up to this time requirement The function Autonegotiation is disabled and the system operates with a fixed transmission rate To avoid the usage of crossover cables the Port 2 must get a crossover of the TX and RX lines PROFINET lO PROFINET IO Device Device Cross Over Straight Cross Over Straight Patch cable EE Patch cable Figure C 1 Line Structure with crossover on board The reset time ofa device is very important for calculating the Start Up time It is necessary to keep the reset time short R19UH0081ED0104 Rev 1 04 RENESAS page 78 of 80 Jul 13 2015 REVISION HISTORY TPS 1 User s Manual Hardware Description Summary Sep 20 2012 First Edition issued Dec 12 2012 1 1 Features added regarding TPS 1 Stack version 1 1 3 1 3 Connection example for a 8bit data bus added 3 1 4 Connection example for a 16bit data bus Figure 3 4 changed 4 4 Interrupt Communication with the TPS 1 added 5 2 add note 1 and 2 loading firmware to an empty Flash recommendation B 3 4 100BASE FX Mode Circuitry changed C Fast Start Up Requirements added Jan 25 2013 3 1 2 Signal description of the parallel interface corrected Figure 3 1 Figure 3 2 corrected 5 2 Note1 changed C Figure C 1 correct spelling errors J
70. rved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 1 How to Use This Manual Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU It is intended for users designing application systems incorporating the MCU A basic knowledge of electric circuits logical circuits and MCUs is necessary in order to use this manual The manual comprises an overview of the product descriptions of the CPU system control functions peripheral functions and electrical characteristics and usage notes Particular attention should be paid to the precautionary notes when usi
71. s and traffic the TPS 1 provides respective signaling outputs Table 8 1 Status signals of the ETHERNET interface Pin Signal Name Meaning Ci2 Link PHY1 LINK ETHERNET Port 1 D10 ACT PHY1 Activity ETHERNET Port 1 C11 Link PHY2 LINK ETHERNET Port 2 A10 ACT PHY2 Activity ETHERNET Port 2 R19UH0081EDO104 Rev 1 04 RENESAS page 48 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 8 PROFINET IO switch 8 1 100Base TX interface Physical transmission complies with the standard e 100Base TX IEEE 802 3 Clause 25 CAT 5 For this interfaces typically RJ45 plugs are used However it is recommended to use special connectors here that are suitable for industrial requirements The interface hardware of the TPS 1 can be connected directly to the Ethernet transformer The standard 100Base TX requires CATS cables Interface activity is indicated by the signals LED LINK PHYI 2 and LED ACTIVITY PHYI 2 The signal LED LINK PHY1 2 is also used to indicate the function Search Device Flashing 8 1 1 100Base TX interface Port 1 Table 8 2 Signal lines 100Base TX interface Port 1 Pin Designation Description F13 Pl TX P Transmit data F14 Pl TXN Transmit data E13 Pi RXP Receive data E14 Pi RXN Receive data 8 1 2 100Base TX interface Port 2 Table 8 3 Signal lines 100Base TX interface Port 2 Pin Designation Description J13 P2 TX P Transmit
72. see table Alternate use of the GPIO Note 2 GPIO_47 After reset the GPIO pin are configured as Inputs no pull up or down Notes 1 Pin F2 must be always connected to VDD33 refer Figure 8 2 Internal voltage regulator 2 Unused GPIO pins should be connect with a pull up 10 KQ to VCC33 This resistor should not be greater than 10 kO 3 The signal TEST SYNC must be available for certification test an accessible pad is sufficient R19UH0081ED0104 Rev 1 04 RENESAS page 13 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 2 2 GPIO multiplexing Table 2 2 Alternate use of the GPIOs 2 Pin function Pin Designation D5 GPIO 0 B5 GPIO 1 C5 GPIO 2 C4 GPIO 3 A4 GPIO 4 B4 GPIO 5 C3 GPIO 6 A3 GPIO 7 B3 GPIO 8 B2 GPIO 9 D3 GPIO 10 D4 GPIO 11 C1 GPIO 12 C2 GPIO 13 D2 GPIO 14 D1 GPIO 15 E2 GPIO 16 E3 GPIO 17 E4 GPIO 18 E5 GPIO 19 FS GPIO 20 F4 GPIO 21 F3 GPIO 22 G5 GPIO 23 G4 GPIO 24 H5 GPIO 25 H4 GPIO 26 J4 GPIO 27 J3 GPIO 28 K3 GPIO 29 K4 GPIO 30 K2 GPIO 31 L2 GPIO 32 L3 GPIO 33 L1 GPIO 34 M2 GPIO 35 M1 GPIO 36 M3 GPIO 37 P3 GPIO 38 N3 GPIO 39 N2 GPIO 40 N4 GPIO 41 M4 GPIO 42 P4 GPIO 43 N5 GPIO 44 M5 GPIO 45 M6 GPIO 46 M7 GPIO 47 Note You can only use one interface exclusively It is not allowed to use e g the parallel and serial h
73. signal is set when a watchdog trigger of the TPS 1 occurs to the Host active low WD_IN Figure 7 1 TPS 1 Watchdog Lines 7 1 Signal WD_OUT pin B12 The WD_OUT signal is processed by the TPS 1 The TPS 1 starts its watchdog during start up the signal is set to high level during power up This is done by the TPS 1 firmware The signal WD_OUT indicates that a watchdog error occurs inside the TPS 1 A watchdog error forces the TPS 1 to a reset All communication connections to a controller are dropped down After a restart of the TPS 1 the host must configure the TPS 1 again If you are using the HOST Interface the external CPU must guarantee a secure behavior of the process output signals in case of a TPS 1 Watchdog In case of using the local lO interface additional circuitry must avoid insecure signals for process outputs R19UH0081EDO104 Rev 1 04 RENESAS page 46 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 7 TPS 1 Watchdog 7 2 Signal WD IN pin A11 The signal WD IN is implemented as a watchdog trigger When recognizing the host watchdog event the TPS 1 generates a diagnostic alarm and sets the IOPS of the input data to the BAD state The watchdog start of the host CPU depends on the individual host The TPS 1 starts checking the host watchdog when receiving the event APP_EVENT_CONFIG_FINISHED The Watchdog Interval can be configured with the TPS Configurator This information is writt
74. some GPIOs for diagnostic functions PROFINET ChannelDiagList A 2 1 IO Parallel At first you have to configure the basic addressing e g API SlotNo et cetera a TPS Config ato Kach x File Settings Help General Settings Ident Settings lO General Settings IO Parallel Settings Diag Channel Ethernet Settings API SlotNo ModuleldentNumber SubslotNo SubModuleldentNumber 0 1 ox i 1 Ox 20 NumberOfDiagChannels StartGPIOPinForDiagChannel O DADatenablage TPS Development Toolkit P 1 1 3 4 TPS Configurator Example Configuration host_interface_parallel xml Figure A 4 Parallel Interface configuration part 1 After that you configure the diagnosis channels DiagChannels R19UH0081ED0104 Rev 1 04 RENESAS page 60 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Appendix A Setting of operating modes To configure the GPIO s you must refer to the part IO Parallel Settings ki a TPS Configurato Sox File Settings Help General Settings Ident Settings 10 General Settings O Parallel Settings Diag Channel Ethernet Settings ParallelNumberOfOutputs StartGPIOPinForOutput ParallelNumberOfinputs StartGPIOPinForinputs RENESAS O DADatenablage TPS Development Toolkit P 1 1 3 4 TPS Configurator Example Configurationhhost inte
75. t CPU and other PROFINET components is processed by the PROFINET CPU connection establishment administration and management of Application Relations controlling of Ethernet connections setup and monitoring of RT and IRT channels etc Simple IO interfaces can be realized with the I O interface only e g digital I Os R19UH0081EDO104 Rev 1 04 RENESAS page 10 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 2 Pin function 2 1 Signal overview and description Table 1 contains an overview about all signals of the TPS 1 Table 2 1 TPS 1 signal overview and description 2 Pin function Pin Designation Type Function Remark SPI Master for Boot Flash ROM M12 CS FLASH OUT O SPI Master Interface Firmware Flash Chip Select TPS 1 active low N13 SPI3_SCLK OUT O SPI Master Interface Firmware Flash CLOCK TPS 1 M13 SPI3_SRXD_IN SPI Master Interface Firmware Flash Receive Data TPS 1 MISO M14 SPI3_STXD_OUT O SPI Master Interface Firmware Flash Send Data TPS 1 MOSI Synchronization signals Ni2 TEST SYNC O Clock signal for certification Note 3 Jti Ti O Clock signal 1 isochronous mode IRT H11 T2 O Clock signal 2 isochronous mode IRT G11 T3 O Clock signal 3 isochronous mode IRT F11 T4 O Clock signal 4 isochronous mode IRT E11 T5 O Clock sign
76. to the TPS 1 firmware Table 4 2 Host Events Name Description Host Event Bits Host Firmware Stack APP EVENT CONFIG FINISHED Set by TPS StartDevice Configuration is valid APP EVENT APP RDYO Set when the device is complete parameterized for ARO APP EVENT APP RDY 1 Set when the device is complete parameterized for AR1 APP EVENT APP RDY 2 Set when the device is complete parameterized for AR2 Supervisor AR APP EVENT RECORD DONE Set after processing a request of the Record Mailbox APP EVENT DIAG CHANGED Set when the status of the diagnostic mailbox changed APP EVENT ONCONNECT OK 0 Connect ARO ok Is set after the host processes the Framelayout Parameter out of a Connect Request of the ARO APP EVENT ONCONNECT OK 1 Connect AR1 ok Is set after the host processes the Framelayout Parameter out of a Connect Request of the AR1 APP EVENT ONCONNECT OK 2 Connect AR2 ok Is set after the host processes the Framelayout Parameter out of a Connect Request of the AR2 APP EVENT ABORT AR 0 ARO is disconnected by the host APP EVENT ABORT AR 1 AR1 is disconnected by the host APP EVENT ABORT AR 2 AR2 is disconnected by the host APP EVENT PULL SUBMODULE A submodule is pulled out of the device APP EVENT RETURN SUBMODULE A submodule returns in to the device APP EVENT ALARM SEND REQ ARO Set when an alarm for th
77. ttt ttt ttt ttt ttt ttt ttt ttt ttt t t ett e ett t e e E E E e e reee reee ee reee 64 A 4 COPYING THE CONFIGURATION DATA INTO THE BOOT tan 65 A 5 GENERATING A COMPLETE SERIAL BOOT FLASH IMAOk ttt trett ttt ttt e etete e r rtr r r errer errr rrrrrrreree 66 APPENDIX B BOARD DESIGN INFORMATION tniii sd on eE AT AEAEE TAEA casa sea AEEA EAA eA Eaa o Ee iaa 67 B 1 VOLTAGE DOE EEN 67 B 2 SWITCHING Ae TLU KON EE 67 B 2 1 Wiring for the Switching Hegulator nono n recon nr nn neon neon RR Rnn RR nn neon ne E SEEA SEESE nc none cnnnnrnnncnnnennnns 68 B 2 2 Layout Example for Switching Regulator 2 0 cceceecsessceesseceseceeeeesseecsecesceesneecasecuecseeeesaeecsaecseeseneecaaecaecseeeeeneesaeeeeenees 69 B 3 BOARD DESIGN RECOMMENDATIONS FOR ETHERNET PAY cooococcnnnnnonnnicoccnononnnncoccnnnonnnnroconnnnnnononconononnnncocrnnnonnnncnronnnnnannniiinns 70 B 3 l Supply Voltage EE B 3 22 100BASE TX Mode Circuitry B 3 3 Unused 100Base TX Interface B34 IQOBASE EX Mode Cir culty sse o na o Uo o a rmo ae ea DT ONE B 3 5 Unused 100Base FX interface APPENDIX C FAST START UP REQUIREMENTO essseeseseesanonnnnkin nnkina neka n Ika nKi E II K II PIKI LIKI LIIIN conca IKI deaa annaa 78 page 7 of80 LENESAS R19UH0081ED0104 Rev 1 04 TPS 1 Jul 13 2015 1 Overview 1 1 Features PROFINET Device Chip e Integrated PROFINET CPU e Host CPU interface SPI Slave or 8 16 bit parallel e SPI Master Interface for
78. ul 17 2014 Changed new printouts of the TPS Configurator Changed Name PROFINET IO changed to PROFINET Chapter 2 Table 2 1 changed Chapter 2 Table 2 2 changed Chapter 3 3 Table 3 3 changed LBU BE x IN in Chapter 3 2 2 1 figure 3 9 changed HOST SCLK IN Chapter 3 2 2 2 2 added the equitation for calculating the wait and latency time for the TPS 1 SPI Wait Mode Chapter 4 Figure 4 1 changed Chapter 5 2 2 added Flash types Chapter 11 changed Appendix B 2 1 and B 2 2 added alternative description to avoid a tantalum capacitor Jul 13 2015 Added chapter 3 1 Testing DPRAM Interface additional information for testing the memory interface Table B 3 added FX interface C 1 page 79 of 80 TPS 1 User s Manual Hardware Publication Date Rev 1 00 Sep 20 2012 Rev 1 04 Jul 13 2015 Published by Renesas Electronics Corporation page 80 of 80 LENESAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2801 Scott Boulevard Santa Clara CA 95050 2549 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 9251 Yonge Street Suite 8309 Richmond Hill Ontario Canada L4C 9T3 Tel 1 905 237 2004 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH
79. ulator in combination with Testi 2 PHY supply voltages E12 VDD33ESD Analog test supply 3 3 V C8 VDDQ PECL B1 PECL buffer power supply 3 3 V Port 1 M8 VDDQ PECL B2 PECL buffer power supply 3 3 V Port 2 D14 P1VDDARXTX Analog Rx Tx port power supply Analog 1 5 V Vpp must be generated via a filter from digital 1 5 V power supply Port 1 L14 P2VDDARXTX Analog Rx Tx port power supply Analog 1 5 V Vpp must be generated via a filter from digital 1 5 V power supply Port 2 H14 VDDACB Analog 3 3 V Vpp must be generated via a filter from digital 3 3 V power supply G13 VSSAPLLCB Analog central GND G14 VDDAPLL Analog central power supply for PHYs 1 5 V Pins for core PLL power supply L9 PLL AGND PLL analog GND core PLL L10 PLL AVDD PLL analog 1 0 V core PLL Pins for switching regulator J1 BVDD Supply voltage for the switching regulator 3 3 V supply for the switching transistor R19UH0081ED0104 Rev 1 04 Jul 13 2015 TENESAS page 12 of 80 TPS 1 User s Manual Hardware 2 Pin function G1 BGND GND for switching regulator please place bypass capacitor between analog power supply and GND F2 AVDD_REG Analog VDD for regulator 3 3 V supply Note 1 smoothed voltage to feed the internal POR G2 AGND REG Analog GND switching regulator H1 LX O 1 5 V output of the internal switching regulator F1 FB Feedback regulator Configurable GPIOs GPIO_00 1 0
80. upply voltage Additional pairs of 0 1 uF and 22 uF capacitors should be applied to VDD33ESD and P 2 1 VDDARXTX R19UH0081EDO104 Rev 1 04 RENESAS page 70 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Appendix B Board Design Information Figure B 5 illustrates the power supply pins and their recommended connection Digital supply and digital ground is not shown PHY Supply Voltages 3 3V VDD33ESD E12 VDDACB H14 VDDQ PECL B1 C8 VDDQ_PECL_B2 M8 1 5V VDDAPLL G14 P1VDDARXTX D14 P2VDDARXTX L14 AGND D12 AGND D13 AGND L12 AGND L12 VSSAPLLCB G13 1 0V Figure B 5 Voltage Supply Concept R19UH0081ED0104 Rev 1 04 RENESAS page 71 of 80 Jul 13 2015 TPS 1 User s Manual Hardware Appendix B Board Design Information B 3 2 100BASE TX Mode Circuitry The analog input and output signals are very noise sensitive and the PCB layout of these signals should be done very carefully Transmit and receive lines must be routed with differential 100 Q impedance and the trace length must be kept as short as possible The EXTRES input must be connected to analog GND with a 12 4 kQ resistor 1 tolerance See Additional TPS 1 Pins The figure below shows a typical circuit example for a IOOBASE TX operation mode Analog 3 3 V PHY Unmarked resitors 1 16 W and 1 tolerance Resitors marked with 1 8 W and 1 tolerance 10nF 2kV AGND PHY Case GND or digital
81. us LEDs PROFINET LED Color Pin State Description LED BF OUT red B13 Bus Communication ON No link status available Flashing Link status ok no communication link to a PROFINET Controller OFF The PROFINET Controller has an active communication link to this PROFINET Device LED SF OUT red B11 System Fall ON PROFINET diagnostic exists OFF No PROFINET diagnostic LED MT OUT yellow B10 Maintenance Required Manufacturer specific depends on the ability of the device LED READY OUT green C10 Device Ready OFF TPS 1 has not started correctly Flashing TPS 1 is waiting for the synchronization of the Host CPU firmware start is complete ON TPS 1 has started correctly The status signals LED BE OUT LED SF OUT LED READY OUT and LED MT OUT are driven active low R19UH0081ED0104 Rev 1 04 RENESAS page 40 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 5 TPS 1 boot subsystem 5 TPS 1 boot subsystem During each startup of the TPS 1 the firmware and the configuration are read from the boot Flash The configuration contains also the MAC addresses for the network ports which connect the device to other PROFINET IO devices 5 1 Hardware Structure for the Boot Operation The TPS 1 uses a boot loader which reads all necessary data from the boot Flash and carries out the necessary settings The boot loader is integrated into the ASIC and cannot be changed JTAG Connector
82. x possible number of slots and subslots Other page sizes than 16 kByte and 4 kByte are not possible R19UH0081EDO104 Rev 1 04 RENESAS page 20 of 80 Jul 13 2015 TPS 1 User s Manual Hardware 3 Host Interface 3 2 4 Connection example for a 8bit data bus Figure 3 5 shows a connection example of an 8 bit data bus to the TPS 1 TPS 1 LBU_CS_IN INT_OUT LBU_AO_IN LBU_A13_IN LBU_SEGO_IN LBU_SEG1_IN LBU DATAO LBU DATA7 LBU READY OUT LBU READ EN IN LBU BE 1 IN LBU BE 2 IN LBU WR EN IN CSN INTN A14 1 CSN INT Port A a An A15 A15 LA DO ADT ADO AD7 READYN jp WAITN DD RDN WRON byte HOST CPU R19UH0081ED0104 Rev 1 04 Jul 13 2015 Figure 3 6 Connection example for an 8 bit data bus RENESAS page 21 of 80 TPS 1 User s Manual Hardware 3 Host Interface 3 2 5 Connection example for a 16 bit data bus Figure 3 3 6 shows the connection ofa 16 bit CPU to the TPS 1 The connection uses a 16 bit data bus and an address bus of 16 bit Thus it is possible to access the entire address space of 64 KByte Address line AO should not be connected using the 16 bit data bus The Address line LBU A0 IN should be connected to a pull down TPS 1 HOST CPU LBU CS IN ke CSN INT OUT NN INT Port LBU Ai IN LBU A13 IN M E A15 LBU SEGO IN An LBU SEG1 IN LBU AO IN LBU DATAO LBU DATA15

TPS-1 User`s Manual - Renesas Electronics

Contents

Download Pdf Manuals

Related Search

Related Contents