PALCE16V8H-15/25 Just Like a GAL ® Device
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1. 2 20 28 About this Tutorial About this Tutorial This tutorial is a step by step procedure on using PALASM software to design a decoder for the PALCE16V8 It describes only those features of PALASM software that are required for the decoder design Therefore it works merely as an introduction to PALASM software The full featured version of the software provides you with additional design capability for advanced applications Contact your local Advanced Micro Devices sales office for a full featured version of PALASM software The software package includes a comprehensive user manual Prerequisites You need IBM PC XT AT or compatible with a hard disk You need the two software disks labelled PALCEI6V8 Evaluation Kit e To program the PALCE16V8 sample a programmer must be linked up to your computer e Tocommunicate with the programmer programmer communications program of your choice must be installed on your computer How to Use this Tutorial This tutorial is designed to be read sequentially from beginning to end First you install the software then create a Boolean equation design compile the design simulate the design and finally view the output files The process takes approximately one hour 2 Design a Decoder for the PALCE16V8 March 1989 Install the Software Install the Software The software on the two floppy disks labelled 16 8 Evaluation Kit has b2. 0711 62 33 77 PAX 0711 625187 TUX cp 721882 HONG KONG 852 5 8654525 FAX MD E 852 5 8654335 67955AMDAPHX ITALY Milan TEL 02 3390541 p RENE 02 3533241 02 3498000 qe ME 315286 JAPAN Kanagawa ij 462 47 2911 462 47 1729 Tokyo 0 03 345 8241 03 342 5196 J24064AMDTKOJ 06 243 3250 06 243 3253 KOREA Seoul TEL 822 784 0030 822 784 8014 LATIN AMERICA Ft Lauderdale TEL sioe 305 484 8600 FAX 305 485 9736 5109554261 AMDFTL NORWAY Hovik TEL 02 537810 02 591959 SINGAPORE 65 3481188 65 3480161 55650 AMDMMI SWEDEN Stockholm 08 733 03 50 FAX 08 886 2 7213393 5 886 2 7122066 886 2 7723422 UNITED KINGDOM Manchester 0925 828008 0925 827693 jb cT 628524 London area 0483 740440 FAX 0483 756196
3. DC Input Voltage 0 5 to Vee tionality of the device is guarantee 0 5V Static Discharge Voltage gt 2001V Latchup Current TA 0 C to 75 C gt 100 Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure Functionality at or above these limits is not implied Exposure to absolute maximum ratings for extended periods may affect device reliability DC CHARACTERISTICS over operating range unless otherwise specified Parameter Parameter Symbol Descriptions Test Conditions Output HIGH Voltage Vec MIN lon 3 2 mA 2 4 V Vin Vin OF Vic Vo Output LOW Voltage MIN lo 24mA 0 5 V Vin Vin OF Vic Input HIGH Voltage Guaranteed Input Logical HIGH 2 0 Voltage for all Inputs Note 1 Vi Input LOW Voltage Guaranteed Input Logical LOW V Voltage for all Inputs Note 1 Input Leakage Current GND lt lt Voc Max Note 2 7107 ha Off State Output Current GND gt Max Note 2 pA Output Short Circuit Current OV Note 2 Rd Supply Current Outputs Open lo 0A mA Veo Max 15MHz 1 These are absolute values with respect to device ground and all overshoots due to system or tester noise are included 2 VO pin leakage is the worst case of I and loz or and 3 No more than one output should be shorted at a time and duration of t
4. CLOCKF CLOCK CHECK A B C D E F G H SETF X Y CLOCKF CLOCK CHECK B G X CLOCK CHECK B C D G H SETF X Y 277 CLOCKF CLOCK CHECK A B C D E F G H SETF X 2 CLOCK CHECK D E G H SETF 7 CLOCKF CLOCK CHECK D E H SETF X CLOCKF CLOCK CHECK C D E F 1989 Design Decoder for the PALCE16V8 21 Create the Decoder Design Process the Design File Before you begin processing the decoder design created in the previous sections take a look at the software processing sequence The processing sequence consists of two simple steps 1 Compile the design and generate JEDEC output 2 Simulate the design The main purpose of using PALASM is to translate your input design into programmer readable JEDEC output However through simulation PALASM allows you to test your design without actually programming a device Figure 8 illustrates the software processing sequence Notice that both the compile and Simulation processes generate output files Figure 9 PALASM Software Processing Sequence Compile Simulate the Design the Design Fuse Map Simulation History JEDEC Fuse Data Simulation Trace JEDEC Test Data 22 Design a Decoder for the PALCE16V8 March 1989 Create the Decoder Design Now that you have an overview of the procedure you
5. e Simulation History Decoder HST Simulation Trace Decoder TRF Test Data Decoder JDC The decoder design does not use the TRACE command Therefore the trace file is not generated and is not discussed in this tutorial 28 Design a Decoder for the PALCE16V8 March 1989 The Simulation History Create the Decoder Design The simulation history shows the status of all the signals defined in the pin list It uses symbols to represent the different states H High L Low X Undefined Z Output disabled Figure 12 shows a sample history file Figure 12 Sample Simulation History File March 1989 CLOCK ER GA g represents represents SETF CLOCKF cg LHLLHLLHLLHLLHLLHLLHLLHL LLLLLLLLLLLLLHHHHHHHHHHH LLLLLLHHHHHHLLLLLLHHHHHH LLLHHHLLLHHHLLLHHHLLLHHH LLLLLLLLLLLLLLLLLLLLLLLL HHHLLLLLLLLLLLLLLLLLLLLL LLLHHHLLLLLLLLLLLLLLLLLL LLLLLLHHHLLLLLLLLLLLLLLL LLLLLLLLLHHHLLLLLLLLLLLL LLLLLLLLLLLLHHHLLLLLLLLL LLLLLLLLLLLLLLLHHHLLLLLL LLLLLLLLLLLLLLLLLLHHHLLL LLLLLLLLLLLLLLLLLLLLLHHH Design a Decoder for the PALCE16V8 29 Create the Decoder Design The JEDEC Test Data The simulation process generates test vectors that are added to the JEDEC file discussed in The JEDEC File above The test vectors can be used to test and verify the design on the device programmer This completes the PALASM design and simulation process The next step is to download y
6. PALASM uses simple commands to define the simulation instructions Figure 7 shows the completed simulation segment for the decoder design in PALASM syntax 16 Design a Decoder for the PALCE16V8 March 1989 Create the Decoder Design Figure 7 Simulation Segment for the Decoder Design SIMULATION SETF OE CLOCK Z CLOCKF CLOCK CHECK A B C D E F G H SETF ALS CLOCK CHECK D E G H SETF X X 7 7 CLOCKF CLOCK CHECK C D F G H SETF 7 CLOCK CHECK C D E F G H SETF X Y CLOCKF CLOCK CHECK B C D E F G H SETF X 2 CLOCK CHECK B D E G H SETF x Y 2 CLOCKF CLOCK CHECK A B C D E F G H SETF CLOCK CHECK D The procedure to enter the Simulation commands the DECODER PDS file follows March 1989 Design a Decoder for the PALCE16V8 17 Create the Decoder Design Step 1 In the editor DECODER PDS use the arrow key to move the cursor just under the keyword SIMULATION Step 2 Enter the Simulation segment shown Figure 7 At the end of each line press lt return gt to go to the next line Step 3 When you have entered all the equations press lt escape gt to display the menu bar Step 4 Go to the File menu and select Save Step 5 Figure 8 shows you the complete decoder design file Check your ed
7. PALCE16V8H 15 25 Just Like GAL Device Advanced Micro Only Better Devices Advanced Micro Devices is proud to introduce the PALCE16V8 EECMOS PAL device that is pin function and fuse map compatible with all 20 pin GAL devices This kit is provided to introduce you to the many benefits of using electrically erasable universal architecture PAL devices Please use the enclosed business reply card to request additional and more detailed information Why do we think you will want to use the PALCE16V8 Because it replaces up to 16 standard PAL devices it consumes only half the power of those same devices it is reprogrammable within seconds and most importantly itis produced by AMD the world s leading supplier of programmable logic devices Give our new PALCE16V8 a try Take a look at our data sheet and compare the critical set up and clock to output specifications to other suppliers GAL devices Once you do you will agree that the PALCE16V8 is just like a GAL device only better A Andy Robin Director of Marketing Programmable Logic 5 15 8 Data PALASM 2 Software Support for the PALCE16V8 1 Design a Decoder for the 16 8 44 1 Abo tthis Tutorial
8. d Operating Conditions PAL CE 16 V8H 15P C d OPERATING CONDITIONS Commercial 0 C to 75 C c PACKAGE TYPE P Plastic DIP PD 020 J Plastic Leaded Chip Carrier PL 020 Valid Combinations The valid Combinations table lists configurations planned to be supported in volume for this device Con sult the local AMD sales office to confirm availability of specific valid combinations to check on newly released combinations and to obtain additional data on AMD s standard military grade products PALCE16V8H 15 25 DESCRIPTION Symbol Type GND CLK I TTL input TTL Input ls la TTL inputs TTLI O Function Five Volt Power Input Ground Clock If the CLK function is not used it can used as a TTL input signal Output Enable If the OE function is not used it can be used as a TTL input signal Input 1 through Input 8 I O through PALCE16V8H 15 25 FUNCTIONAL DESCRIPTION The PALCE16V8 is a universal PAL device It has eight independently configurable macrocells MC The macrocells can be configured as registered output combinatorial output combinatorial I O or dedicated in put The programming matrix implements a program mable AND logic array which drives a fixed OR logic ar ray Buffers for device inputs have complementary out puts to provide user programmable input signal polarity Pins 1 and 11 serve either as array input
9. 2 Install th SoftWare 255403 Y d Fe Capi PL X a nerd des 3 M RUM EL E E 4 Create the Decoder orant ep peste ade 5 Learn the Structure of the PALASM Design File 6 Build the Declaration Segment essen 8 Build the Simulation exon dE nox onera 15 Process the Design Elle 22 Autorun Compile and 23 View debet e dedil dv tanga toc cas n Eee eges 26 View the Compile Output 27 View the Simulation Output Files eene 28 x PALCE16V8H 15 25 EE CMOS Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS W Pin function and fuse map compatible with all 20 pin GAL devices E Electrically erasable CMOS technology provides reconfigurable logic and full testability High speed CMOS technology 15 05 propagation delay for 15 version 25 ns propagation delay for 25 version Direct plug in replacement for the PAL16R8 series and most of the PAL10H8 series Outputs programmable as registered or combinatorial in any combination GENERAL DESCRIPTION The PALCE16V8 is an advanced PAL device built with low power high speed electrically erasable CMOS technology It is functionally compatible with all 20 pin GAL devices The m
10. ANY CHANGE STATE PERMITTED UNKNOWN 12015A 018A PALCE16V8H 15 25 XV gt Apply the desired value to all registered out put pins Leave combinatorial output pins floating Output Register Preload The PRELOAD function allows the registers to be loaded from the output pins This feature aids functional gt RUE pel p Ve testing of sequential designs by allowingdirectsettingot Remove Vi Vw from registered outputs output states The procedure is as follows 7 Lower 8 to Vi Vin 8 Enable the output registers by lowering 1 Raise Vcc to 5 0 V 0 5 V 9 Verify for at all registered output pins Note 2 Setpin8 to 10 0 V 0 5 V that the output pin signal will be the inverse of the 3 Set OE HIGH preload input Parameter Symbol Parameter Description e Tine tom Prees pn ee SE us te SetupTimefromOEtoData 1 1 le a a a tes HeldTimetromClockto Data mu cl mas dwdt VeoFalinpSlewRate pn8 2 12015 015A Preload Waveforms xvi PALCE16V8H 15 25 Power Up Reset Due to the synchronous operation of the power up reset and the wide range of ways Vcc can rise to its stead The PALCE16V8 has been designed with the capability state two Eee ide to insure a to reset during system power up F
11. TEX UE 59103 North American Representatives Burnaby DAVETEK MARKETING 604 430 3680 Alberta AVETEK MARKETING 403 291 4984 Kanata Ontario VITEL ELECTRONICS 613 592 0060 Mississauga Ontario ee PE ONES 416 676 9720 Lachine pA TEL TECTRONICS 514 636 5951 i ANLEBMOUN LAUS TECH MKTG 208 888 6071 INDIRNA TECHNICAL MARKETING 312 577 9222 ELECTRONIC MARKETING CERE SUAM SS ING iate 317 921 3452 LORENZ SALES 319 377 4666 KANSAS Merriam LORENZ SALES 813 384 6556 Wichita LORENZ SALES 316 721 0500 KENTUCKY ELECTRONIC MARKETING CONSULTANTS INC 317 921 3452 MICHIGAN Holland COM TEK SALES INC 616 399 7273 Novi COM TEK SALES INC 313 344 1409 MISSOURI LORENZ SALES 814 997 4558 NEBRASKA LORENZ SALES 402 475 4660 NEW MEXICO ORRON DESERT STATES 505 293 8555 East Syracuse diy 315 437 8343 Woodbury COMPO NENT SNO ET ANTS INC 516 364 8020 Centerville DOLFUSS ROOT 8 CO 513 433 6776 Columbus DOL
12. fixed OR array allows upto eight data product terms per output for logic functions The sum of these products feeds the output macrocell Each macrocell can be pro grammed as registered or combinatorial with an active HIGH or active LOW output The output configuration is determined two global bits and one local bit control ling four multiplexers in each macrocell PALCE16V8 32 X 64 Programmabie AND 12015 0014 PALCE16V8 Block Diagram Publication 4 12015 Rev A Amendment Issue Date April 1989 CONNECTION DIAGRAMS 119 DIP ORDERING INFORMATION Standard Products AMD MMI standard products are available in several packages The order number Valid Combination is formed by a combination of a PROGRAMMABLE ARRAY LOGIC CMOS ELECTRICALLY ERASABLE NUMBER OF ARRAY INPUTS OUTPUT TYPE V Versatile NUMBER OF FLIP FLOPS b POWER H Half Power PERFORMANCE 15 15 ns tpp 25 25 ns tpp Valid Combinations PALCE16V8H 15 PC JC PALCE16V8H 25 PLCC 2 19 110 2 1CLK g 13 181 13114 17 110 1 16 110 51 16 15 110 15117 13 Jo 12 vo GND GND l Og VO 12015 002A 12015 003 Pin Designations Input Note Pin 1 is marked for orientation VO InputOutput OE Output Enable CLK Clock Supply Voltage GND Ground Device Number b Speed Power Option c Package Type
13. information for the decoder design Figure 4 shows the completed file header 10 Design a Decoder for the PALCE16V8 March 1989 Create the Decoder Design Figure 4 File Header for the Decoder Design TITLE DECODER PATTERN A REVISION 1 0 AUTHOR J ENGINEER COMPANY ADVANCED MICRO DEVICES DATE 3 20 89 Enter the CHIP Statement The chip name and the device name are required fields You can enter descriptive chip name of your choice The software selects the device name PALCE16V8 for you CHIP ChipName PAL_AMD Device PALCE16V8 Enter the Pin List Each on the PALCE16V8 that you use in your design requires a pin statement The pin statement consists of the following fields e Pin e Pin number Input output or I O Specify one of the above Input or Output type Specify whether the input or output is combinatorial or registered March 1989 Design a Decoder for the PALCE16V8 11 Create the Decoder Design e Polarity type Specify whether the output 15 active low or active high In Create the Decoder Design notice that the decoder design consists of three inputs and eight outputs In addition you must define pin 1 as the clock pin and pin 11 as the output enable pin The procedure to enter the pin list follows Step 1 Enter the pin statements using the arrow keys or the tab key to move from field to field Notice that the template allows you to save time by giving you choic
14. inputs X Y and Z Figure 6 shows the complete equations segment for the decoder design file Figure 6 Equations Segment for the Decoder Design EQUATIONS A X X Z B X Y 7 C Y Z Y 7 E Z 7 G Z 7 After exiting the PDS Declaration Segment template the software displays the file DECODER PDS on your screen You are now in the editor Until you quit the editor and return to PALASM use the editor commands The procedure to enter the Boolean equations in the Equations segment of the DECODER PDS file follows Step 1 Use the arrow key to move the cursor to the line just under the keyword EQUATIONS 14 Design a Decoder for the PALCE16V8 March 1989 Create the Decoder Design Step 2 Enter the Boolean equations as shown in Figure 6 At the end of each line press lt return gt to go to the next line Step 3 When you have entered all the equations press escape to display the menu bar Step 4 Go to the File menu and select Save Proceed to Build the Simulation Segment to complete the decoder design file Build the Simulation Segment This segment of the design file is optional Including the simulation segment in the design file makes simulation of the design possible Simulation allows you to predict the behavior of your design in software The PALASM simulator allows you to monitor the status of inputs and outputs to control the in
15. is automatically performed by the programming hardware No special erase operation is required Security Bit A security bit is provided on the PALCE16V8 as deter rent to unauthorized copying of the array configuration patterns Once programmed this bit defeats readback of the programmed pattern by device programmer se curing proprietary designs from competitors However programming and verification are also defeated by the security bit The bit can only be erased in conjunction with the array during a bulk erase cycle Basic PAL Device Notation The multi input gates inthe PAL device s programmable AND gate array are simplified in the logic diagrams The PAL device notation for an AND gate called a product term in a PAL device is shown below 12015 006A Figure 3 PAL Device AND Gate This is equivalent to the standard logic notation below A Figure 4 Standard AND Gate 12015 007A Each vertical line in the PAL device is a potential input to the AND gate At each crosspoint is a programmable bit which provides a potential connection in the pro grammed state The Xs in the diagram indicate a con nection at the crosspoint In electrically erasable devices the crosspoints are origi nally disconnected They are either connected or left open during device programming Multiplexers in the PAL device logic diagrams use a sim ple notation for maximum clarity A 2 1 multiplexer that selec
16. 004 PALCE16V8 Macrocell vi PALCE16V8H 15 25 Configuration Options Each macrocell can be configured as one of the follow ing registered output combinatorial output or dedicated input In the registered output configuration the output bufferis enabled by the OE pin In the combinatorial con figuration the buffer is either controlled by a product term or always enabled the dedicated input configu ration it is always disabled With the exception of MC and macrocell configured as a dedicated input derives the input signal from an adjacent derives its input from pin 11 OE and from pin 1 CLK The macrocell configurations are controlled by bits stored in the configuration control word It contains 2 global bits 560 and 581 and 16 local bits SLOo through 5107 and SL10 through 51 17 SGO determines whether registers will be allowed SG1 determines whetherthe PALCE16V8 will emulate a 16R8 family or a PAL10H8 family device SLOx in conjunction with SG1 selects the configuration of the macrocell and SL1x sets the output as either active LOW or active HIGH for the individual macrocell The configuration bits work by acting as control inputs forthe multiplexers in the macrocell There are four mul tiplexers a product term input an enable select an out put select and a feedback select multiplexer SG1 and SLOx are the control signals for all four multiplexers In addition SLO for the adja
17. 22 9323 408 749 5703 12176A Printed in USA
18. D command replaces the old PRLDF command described in Chapter 4 of the PAL Data Bock Include the PRELOAD command in the simulation segment of your PDS design file The syntax for the PRELOAD command follows Advanced Micro Devices a 3 PALASM 2 Software Support for the PALCE16V8 Syntax PRELOAD list of register identifiers Example PRELOAD 01 02 03 The example above shows the PRELOAD command setting the register values to 101 high low high The PRELOAD command is similar to the old PRLDF command It forces a register into a known state either 1 or 0 The PRELOAD statement allows you to initialize registers Figure 1 illustrates a PALCE16V8 output register Notice the register is identified by the output node name A Figure 1 Output Register To set the A register value to 1 the PRELOAD statement is written as shown in the example below Example PRELOAD A In the example above the PRELOAD command sets the register to a value of 1 The inverter causes the output value to change to 0 Thus the PRELOAD command determines the value of the register alone The output value is determined by the device architecture Advanced Micro Devices PALASM 2 Software Support for the PALCE16V8 Note Unlike the PRELOAD command the old PRLDF command determined the value of outputs not registers The example below shows a partial simulation segment for a PALCE16V8 Example CHECK 014 015 016 017 SETF OE PRE
19. FUSS ROOT 8 614 885 4844 Strongsville DOLFUSS ROOT 8 216 238 0300 PENNSYLVANIA DOLFUSS 8 412 221 4420 PUERTO RICO REP ASSOCIATES 809 746 6550 801 595 0631 WASHINGTO TECHNICAL SALES eene 206 455 3600 HEARTLAND TECHNICAL MARKETING 414 796 1128 Advanced Micro Devices reserves the right to make changes in its product without notice in order to improve design or performance characteristics The performance characteristics listed in this document are guaranteed by specific tests guard banding design and other practices common to the industry For specific testing details contact your local AMD sales representative The company assumes no responsibility for the use of any circuits described herein Advanced Micro Devices Inc 901 Thompson Place P O Box 3453 Sunnyvale 94088 USA Tel 408 732 2400 TWX 910 339 9280 TELEX 34 6306 TOLL FREE 800 538 8450 4 APPLICATIONS HOTLINE FREE 800 222 9323 408 749 5703 1989 Advanced Micro Devices Inc 12176A 2 16 89 AW SVP 25 2M 3 89 Printed in USA ADVANCED MICROU DEVICES INC 901 Thompson Place P O Box 3453 Sunnyvale California 94088 3453 408 732 2400 TWX 910 339 9280 TELEX 34 6306 TOLL FREE 800 538 8450 APPLICATIONS HOTLINE 800 2
20. KINNYDIP are registered trademarks of Advanced Micro Devices LogicPak and UniSite are trademarks of Data Corporation GAL is a registered trademark of Lattice Semiconductor Corp This part is covered by various U S and foreign patents owned by Advanced Micro Devices XX PALCE16V8H 15 25 PALASM 2 SOFTWARE SUPPORT FOR THE PALCE16V8 About this Section This section describes PALASM 2 software special considerations for the PALCE16V8 It is intended as a supplement to the PALASM 2 software user documentation in part 4 of the 1988 PAL Device Data Book If you do not already have the Data Book contact your local AMD sales office for Boolean Equation Design Entry 1 Thepin list for the PALCE16V8 follows 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 GND 711 12 13 14 15 16 17 18 19 20 OE 01 02 03 04 05 06 07 08 Note lines beginning with semicolon are comments and ignored by the software 2 You use the SIGNATURE command to program the signature fuse The command must be used in the Declaration segment of your design file It must follow the CHIP statement If you enter it in the Equations segment the software displays an error message The signature command syntax follows Advanced Micro Devices a 1 2 PALASM 2 Software Support for the 16 8 Syntax SIGNATURE number or string Each of the syntax options is defined below Syntax optio
21. LOAD 014 015 016 017 Preload registers 0010 SETF Check output CHECK 014 015 016 017 CLOCK CLK Next state CHECK 014 015 016 017 Note The above example assumes the list shown earlier in this document Keep the following special considerations in mind when using the PRELOAD command on the PALCE16V8 register is forced to a known state and the output is calculated from the register After the register is clocked the value that represents the next state appears at the output An error is generated if the output is not disabled before preload PRELOAD statement works on the register the CHECK statement validates the output Advanced Micro Devices a 5 DESIGN DECODER FOR THE PALCE16V8 About this Tutorial Install the Software po 3 Learn th ioc 4 Create the Decoder isi esa Learn the Structure of the PALASM Design File 8 Build the Declaration 8 Build the Simulation 5 15 Process the Design File 2 ON xn ERA 22 Autorun Compile Simulate 23 View the Output Files cokes 26 View the Compile Output 27 View the Simulation Output
22. NSAS iie acciri vetito 913 451 3115 MARYLAND 301 796 9310 617 273 3970 MINNESOTA 612 938 0001 MISSOURI RP 913 451 3115 NEW JERSEY Cherry 609 662 2900 amp 201 299 0002 NEW YORK Liverpool 315 457 5400 Poughkeepsie 914 471 8180 919 878 8111 Columbus 614 891 6455 DEGERE 513 439 0470 OREGON 503 245 0080 PENNSYLVANIA SOUTH CAROLINA 215 398 8006 803 772 6760 TEXAS AUSM ii 512 346 7830 934 9099 Hm 713 785 9001 International BELGIUM Bruxelles 771 91 42 FAX 762 CREER FRANCE Paris TEL 49 75 10 49 75 10 13 eit 263282 WEST GERMANY Hannover area TEL 0511 736085 FAX 0511 721254 922850 M nchen TEL 089 4114 0 089 406490 523883 Stuttgart
23. acrocells provide a universal device architecture The PALCE16V8 will directly replace the PAL16R8 and 10 series devices with the excep tion of the PAL16C1 Device logicis automatically configured according to the user s design specification Design is simplified by PALASM design software allowing automatic creation of a programming file based on Boolean or state equa tions PALASM software also verifies the design and can provide test vectors for the finished device Pro gramming can be accomplished on standard PAL device programmers BLOCK DIAGRAM 1 Advanced Micro Devices Programmable output polarity Programmable enable disable control E Preloadable output registers for testability Automatic register reset on power up Cost effective 20 plastic DIP and PLCC packages B Programmable on standard device programmers Supported by PALASM software Fully tested for high programming and functional yields and high reliability The PALCE16V8 utilizes the familiar sum of products AND OR architecture that allows users to implement complex logic functions easily and efficiently Multiple levels of combinatorial logic can always be reduced to sum of products form taking advantage of the very wide input gates available in PAL devices The equa tions are programmed into the device through floating gate cells inthe AND logic array that can be erased elec trically The
24. binations of inputs Table 1 Truth Table for Decoder Inputs Outputs Generated 1 Q X YZ ABCDE Or 6 Design a Decoder for the PALCE16V8 March 1989 Create the Decoder Design Notice that each of the output pins is high or has a value of 1 in response to a unique combination of the three input pins Output pin A for example is high only if the three input pins are low The Boolean expression that corresponds to this condition is IX Y Z Note is used for AND is used for NOT You can create a Boolean equation that defines all the conditions under which output pin is high Az X Y Z Similarly you can create all of the Boolean equations required to completely define the decoder functions A K Y Z B X Y Z Z 7 E X Y Z F X Y Z G X Y Z H X Y Z Now that you have Boolean equations to describe the decoder functions it is time to create a complete PALASM design file for the decoder March 1989 Design a Decoder for the PALCE16V8 7 Create the Decoder Design Learn the Structure of the PALASM Design File PALASM software requires a specific design file layout Figure 2 illustrates the layout The equations defined above go into the Equations se
25. bject to change MANUFACTURER PROGRAMMER CONFIGURATION Adams MacDonald Contact Manufacturer 2999 Monterey Salinas Hwy Monterey CA 93940 408 373 3607 Data I O Corporation System 29B UniSite Willow Road NE LogicPak 4 Rev 2 5 PO Box 97046 Adapter 303A 011A Rev V10 Family Pinout Code Redmond WA 98073 9746 80 55 800 247 5700 Digelec Inc Contact Manufacturer 1602 Lawrence Avenue Suite 113 Ocean NJ 07712 201 493 2420 Kontron Electronics Inc Contact Manufacturer Contact Manufacturer 1230 Charleston Road Mountain View CA 94039 7230 415 965 7020 Logical Devices Contact Manufacturer 1201 E Northwest 65th Place Fort Lauderdale FL 33309 Micropross Contact Manufacturer Parc d Activite des Pres 5 rue Denis Papin 59650 Villeneuve d Ascq 20 47 90 40 Stag Microsystems Inc Contact Manufacturer 1600 Wyatt Drive Suite 3 Santa Clara CA 95054 408 988 1118 Varix Corporation Contact Manufacturer 1210 E Campbell Road Suite 100 Richardson TX 75081 214 437 0777 MANUFACTURER SOFTWARE DEVELOPMENT SYSTEM Advanced Micro Devices PALASM 2 23D 901 Thompson Place Sunnyvale CA 94088 3453 800 222 9323 Data Corporation Contact Manufacturer 10525 Willow Road NE PO Box 97046 Redmond WA 98073 9746 800 247 5700 Personal CAD Systems Contact Manufacturer Assisted Technology Division 1290 Parkmoor Avenue San Jose CA 95126 408 971 1300 PAL PALASM and S
26. can begin processing the decoder design Proceed to Autorun Compile and Simulate Autorun Compile and Simulate Use the arrow keys to go to the Run menu in PALASM Notice that the Run menu offers you three choices Figure 9 illustrates the Run menu Figure 10 Run Menu Simulate Autorun PALASM software offers you a time saving autorun feature that combines the compile and Simulation processes into one keystroke The autorun procedure follows Step 1 Select Autorun in the Run menu A window opens at the bottom of your screen March 1989 Design a Decoder for the PALCE16V8 23 Create the Decoder Design Step 2 Watch the status line as PALASM software completes the following operations Parse Minimize Assemble Simulate Step 3 When you see the message PLDSIM Program Successful Press esc If the process was successful you can skip steps 4 11 If the process was unsuccessful and produces errors proceed to step 4 Step 4 Select Edit in the PALASM menu bar The Edit menu appears on your screen Step 5 Select Design File in the Edit menu The design file DECODER PDS appears 24 Design a Decoder for the PALCE16V8 March 1989 Step 6 Step 7 Step 8 Step 9 Step 10 Step 11 Step 12 Note Create the Decoder Design Carefully compare the file on your screen with the printed file in Figure 8 Complete Decoder Design File If your have typos in your screen file make the necessary chan
27. cent I O is a control input to the feedback multiplexer In MC 500 replaces SG1 on the feedback multiplexer This accommodates CLK being the adjacent pin for and OE for Registered Output Configuration The control bit settings 500 0 SG1 1 and 51 0 0 There is only one registered configuration All eight product terms are available as inputs to the OR gate Data polarity is determined by 511 The flip flop is loadedonthe LOW to HIGH transition of CLK The feed back path is on the register The output buffer is enabled by OE Combinatorial Configurations The PALCE16V8 has three combinatorial output con figurations dedicated output in a non registered device 1 in a non registered device and I O in a registered de vice Dedicated Output In a Non Registered Device The control bit settings are SGO 1 561 O and SLO 0 All eight product terms are available to the OR gate Because the macrocell is a dedicated output the feed back is not used Because CLK andOE are not used in a non registered device pins 1 and 11 are available as in put signals Pin 1 will use the feedback path of MC and pin 11 will use the feedback path of MCo Combinatorial I O In a Non Registered Device The control settings 560 1 561 1 and SLO 1 Only seven product terms are available to the OR gate The eighth product term is used to enable the output buffer The signal at the
28. een compressed into archive format The installation procedure dearchives the software programs before installing them on your hard disk This procedure takes approximately seven minutes Step 1 Step 2 Step 3 Step 4 Step 5 Note Place disk 1 in drive A Enter A INSTALL lt return gt At the prompt specify the drive on which you want the software installed At the prompt if necessary allow the software to make changes to the system files AUTOEXEC BAT and CONFIG SYS When the message window at the bottom of your screen prompts you place disk 2 in drive A When the installation procedure is complete the following message appears on your screen Re boot and enter C PALC16V8 Follow the instructions to start up the program The command to call up the software is PALC16V8 and not PALCEI6V8 March 1989 Design a Decoder for the PALCE16V8 3 Learn the Menu Learn the Menu The PALCE16V8 Evaluation Kit banner is the first screen that appears when you call up the software When you press any key the menu appears on your screen Figure 1 shows the four part software menu These four parts File Edit View and Run are arranged at the top of the screen in a menu bar Figure 1 PALASM Menu Screen Menu bar Status line File menu PAL Setup PAL Setup Current Directory C PALC16V8 Design File DECODER 4 Design Decoder for the PALCE16V8 March 1989 Learn the Menu Each of
29. es for several of the fields Figure 5 shows the completed pin list Step 2 Press 10 not return to save your pin list and exit the template 12 Design a Decoder for the PALCE16V8 March 1989 Create the Decoder Design Figure 5 Pin List for the Decoder Design Pin Number Name I O Type Polarity Pin 1 CLOCK Input Comb Active high Pin 2 X Input Comb Active high Pin 3 Y Input Comb Active high Pin 4 2 Input Comb Active high Pin 11 Input Comb Active high Pin 12 A Output Reg Active high Pin 13 Output Reg Active high Pin 14 C Output Reg Active high Pin 15 Output Reg Active high Pin 16 E Output Reg Active high Pin 17 Output Reg Active high Pin 18 G Output Reg Active high Pin 19 H Output Reg Active high PALASM software transfers you to the editor and displays the file DECODER PDS Notice that the entire Declaration segment that you created in the template has been copied into the file Also notice that headings of the remaining segments of the file have been entered to prompt you to complete the design file The Equations Segment The Simulation Segment Proceed to Build the Equations Segment to complete the next part of the decoder design file March 1989 Design a Decoder for the PALCE16V8 13 Create the Decoder Design Build the Equations Segment The Equations segment contains the Boolean equations that specify the decoder design In Table 1 the truth table defines the desired outputs A H as a function of the
30. ges Press lt esc gt to display the editor menu bar Select File in the menu bar The File menu appears Select Save in the File menu To quit the editor select Quit in the menu bar The Quit menu appears Select Quit All Files The software returns you to the PALASM menu Now repeat steps 1 3 to recompile and simulate your design file The decoder design has been tested and found error free If your compile and simulation processes produce errors you probably have typos in your file Now that the design file has been successfully processed you can look at the output files that the compile and simulation processes Proceed to View the Output Files March 1989 Design a Decoder for the PALCE16V8 25 Create the Decoder Design View the Output Files In the last section you used autorun to run the compile and Simulation processes with one keystroke PALASM however generates a set of output files after each process Proceed to view each set of output files The procedure to view any of the output files follows Step 1 Use the arrow keys to select the View menu Figure 11 shows the View menu as it appears on your screen Step 2 Notice that the list contains input output and intermediate files To view a file select the item and press lt return gt Step 3 file is now displayed on your screen Notice you can scroll up and down using the arrow keys Step 4 Press lt esc gt to exit the fi
31. gment of the file Figure 2 PALASM Design File Layout DECLARATION SEGMENT EQUATIONS SEGMENT SIMULATION SEGMENT The PALASM design file is also known as the PDS PAL device Design Specification file Proceed to Build the Declaration Segment to begin creating the decoder design file using PALASM software Build the Declaration Segment The PALASM software menu provides a template for building the Declaration segment of your design file The procedure to use the template follows Step 1 Use your arrow keys to move to the File menu 8 Design a Decoder for the PALCE16V8 March 1989 Create the Decoder Design Step 2 Select New Design File in the File menu and press return Step 3 A window appears Enter a file name of your choice This tutorial uses the file name shown below Enter DECODER PDS return The PDS Declaration Segment template appears on your screen Figure 3 shows the template as it appears on your screen Notice you can use return to move from field to field However some fields require you to enter information before you can move on Also use F10 and not return to save the segment March 1989 Design a Decoder for the PALCE16V8 9 Create the Decoder Design Figure 3 Screen Template of PDS Declaration Segment Enter the File Header Information The first part of the Declaration segment consists of descriptive information about your file You can enter the following or similar
32. he short circuit should not exceed one second Notes Capacitance Note 1 5 0V 25 C Output Capacitance 2 0V at f 1MHz Note 1 These parameters are not 100 tested but are evaluated at initial characterization and at any time the design is modi fied where capacitance may be affected xii PALCE16V8H 15 25 SWITCHING CHARACTERISTICS over Commercial operating range Note 1 Symbol Description Input or Feedback to Combinatorial Output Note 2 Setup Time from Input or Feedback to 12 e 15 10 _ Width of Clock HM HIGH Maximum External Feedback 1 ts tco 4 MHz Frequency 50 ts Input to Output Enable Notes 4andS tn Input to Output Disable Notes 4and5 Notes 15 15 15 o Ala 1 Commercial Test Conditions 2000 3900 see switching test circuit 2 trois tested with S closed and C 50pF including jig capacitance OV Vor 1 5V 3 These parameters are not 100 tested but are calculated at initial characterization and at any time the design is modified where frequency may be affected 4 For three state outputs enable times are tested with 50pF to the 1 5V level S is open for high impedance to HIGH tests and closed for high impedance 10 LOW tests Ou
33. itor file to see if there are any typos Your file will not process correctly if there are syntax errors Correct your errors and save the file again Step Press esc to call up the editor menu bar Step 6 Select Quit Files in the Quit menu to return to PALASM The decoder design file is now complete and ready for PALASM to process Proceed to Process the Design File 18 Design a Decoder for the PALCE16V8 March 1989 Create the Decoder Design Figure 8 Complete Decoder Design File PALASM Design Description Dre Declaration Segment TITLE DECODER PDS PATTERN A REVISION 1 0 AUTHOR J ENGINEER COMPANY ADVANCED MICRO DEVICES INC DATE 3 20 89 CHIP PAL AMD PALCE16V8 PP E Pin Declarations PIN 1 CLK PIN 2 X PIN 4 PIN 11 12 13 PIN 14 HIGH REG PIN 15 D HIGH REG PIN 16 E HIGH REG PIN 17 F HIGH REG PIN 18 G HIGH REG PIN 19 H HIGH REG March 1989 Design a Decoder for the PALCE16V8 19 Create the Decoder Design EGRE rt ha OSS ee Boolean Equations Segment EQUATIONS A X X Z B X Y 7 C Y Z 7 E Z F X 7 G Z 20 Design a Decoder for the PALCE16V8 March 1989 Create the Decoder Design SIMULATION SETF OE CLOCK Y Z CLOCKF CLOCK CHECK A B C D E F G H SETF X
34. le 26 Design a Decoder for the PALCE16V8 March 1989 Create the Decoder Design Figure 11 View Menu R Input data Fuse map JEDEC fuse data JEDEC test data Simulation history Simulation trace Other file enter select an option home top of line 4 move cursor esc exit View the Compile Output Files The compile process generates the following output files The Fuse Decoder XPT The JEDEC Fuse Data Decoder JED Notice the file names shown above in italic that PALASM assigns the output files The first part of the name is user defined The second part is the extension that the software assigns March 1989 Design a Decoder for the PALCE16V8 27 Create the Decoder Design The Fuse Map The fuse map is a detailed map of the connections that are programmed along each product term on the device The following symbols illustrate which connections are programmed and unprogrammed X Unprogrammed connection Programmed connection The JEDEC Fuse Data This file is the programmer readable translation of the input design file It be downloaded to the programmer to program the PALCE16V8 JEDEC stands for Joint Electronic Device Engineering Council the organization that creates the standards for this file View the Simulation Output Files The Simulation output files show you whether your design produces the desired outputs The Simulation process produces the following output files
35. n 1 SIGNATURE number The number you use can be e binary B or b octal 0 or 0 decimal or d hexadecimal or sth Notice that each number base is specified by an upper case or lower case designator The examples below illustrate different ways to specily the signature as a number Examples SIGNATURE 123456 SIGNATURE 40845 SIGNATURE 1976 5 Note the following space in the last example is allowed but is deleted the software Number designators are optional If you do not use a number designator the software assumes a decimal number Advanced Micro Devices PALASM 2 Software Support for the PALCE16V8 Simulation 64 least significant bits are programmed The remaining most significant bits on the left are truncated e software does not program decimal numbers greater than 15 digits Syntax option 2 SIGNATURE string Examples SIGNATURE abcdefgh SIGNATURE ABC_123 Note the following Astring must begin with an alpha character Alphanumeric characters and underscores are allowed software converts alpha characters to the corresponding ASCII code e Spaces are allowed in strings The software converts all lower case characters that you enter into upper case characters e left most 8 characters are programmed with the corresponding ASCII code The remaining characters on the right are truncated The PRELOA
36. ollowin wer up all flip flops willbe resetto LOW The Guth stato willbe These HIGH independent of the logic polarity This feature pro 1 The Vcc rise must be monotonic vides extra flexibility to the designer and is especially 2 Following reset the clock input must not be driven valuable in simplifying state machine initialization A from LOW to HIGH until all applicable input and feed timing diagram and parameter table are shown below back setup times are met Parameter Parameter Symbol Descriptions its Input or Feedback Setup Time 12 See Switching Characteristics Clock width Power 4 PR Registered Active LOW Output ts gt tw 12015 017A PALCE16V8H 15 25 xvii fuax Parameters The parameter fmax is the maximum clock rate at which the device is guaranteed to operate Because flexibility inherent in programmable logic devices offers a choice of clocked flip flop designs is specified for three types of synchronous designs The first type of design is a state machine with feedback signals sent off chip This external feedback could go back to the device inputs or to a second device in a multi chip state machine The slowest path defining the period is the sum of the clock to output time and the input setup time for the external signals ts tco The reciprocal is the maximum freq
37. our JEDEC file to a device programmer Consult the Programmers Development Systems Table in this data sheet part of this document for information on programmers Also refer to your programmer manual for instructions on setup and use Where to Go from Here This tutorial did not explore all the capabilities of PALASM software or the PALCE16V8 To order the full featured version of PALASM software contact your local AMD sales office today 30 Design a Decoder for the PALCE16V8 March 1989 Sales Offices International Continued North American ALABAMA nS 205 882 9122 ARIZONA et 602 242 4400 FORNIA Culver City UENIT 213 645 1524 Newport Beach 714 752 6262 Roseville 916 786 6700 San Diego 619 560 7030 San Jose 408 452 0500 Woodland Hills 818 992 4155 CANADA Ontario 613 592 0060 416 224 5193 COLORADO 50050 ero sta 303 741 2900 CONNECTICUT 203 264 7800 FLORIDA ClearWater 813 530 9971 Ft Lauderdale 305 776 2001 le Gn 407 830 8100 22520000 enden 404 449 7920 ILLINOIS uere oer erre tito eorr 312 773 4422 Napervilla eret trece 312 505 9517 KA
38. pin is fed back to the AND array via the feedback multiplexer This allows the pin to be used as an input Because CLK and OE are not used a non registered device pins 1 and 11 are available as inputs Pin 1 will use the feedback path of MC and pin 11 will use the feedback path of MC Combinatorial I O Registered Device The control bit settings SGO 0 SG1 1 and 510 1 Only seven product terms are available to the OR gate The eighth product term is used as the output enable The feedback signal is the corresponding 1 signal Dedicated Input Configuration The control bit settings 500 1 SG1 0 and SLOx 1 The output buffer is disabled Except for and the feedback signal is an adjacent I O For MC and MC the feedback signals are pins 1 and 11 These configu rations are summarized in Table 1 and illustrated in Fig ure 2 Configuration 500 SG1 SLox Cell Configuration Devices Emulated Device Uses Registers PAL 16R8 16R6 16R4 1 0 Registered Output PAL10H8 12H6 14H4 16 2 1018 1216 1414 1612 PAL12H6 14H4 16 2 1216 1414 1612 Programmable Output Polarity The polarity of each macrocell can be active HIGH or active LOW either to match output signal needs or to reduce product terms Programmable polarity allows Boolean expressions to be written in their most compact form true or inverted and the outp
39. put signals and to check the outputs against your predicted outputs To simulate this design thoroughly you must e Set the inputs in every possible combination Check if each combination of inputs produces the desired outputs Supply a clock pulse to effect the change in outputs March 1989 Design a Decoder for the PALCE16V8 15 Create the Decoder Design Enable the outputs by setting the output enable OE pin low The simulation for the decoder design may be described in natural language as follows Set the output enable clock and input levels to OE CLOCK X Y Z Supply a clock pulse Check that the output levels A B C D E F G H Set the input levels to X Y Z Supply a clock pulse Check that the output levels are A B C D E F G H Set the input levels to X Y Z Supply a clock pulse Check if the output levels are A B C D E F G H Set the input levels to X Y Z Supply a clock pulse Check if the output levels are A B C D E F G H Set the input levels to X Y Z Supply a clock pulse Check if the output levels are A B C D E F G H Set the input levels to X Y Z Supply a clock pulse Check if the output levels are A B C D E F G H Set the input levels to X Y Z Supply a clock pulse Check if the output levels are A B C D F Set the input levels to X Y Z Supply a clock pulse Check if the output levels are A B C D E F G H
40. s or as clock CLK and output enable OE for all flip flops Unused input pins should be tied directly to VCC or GND Product terms with all bits unprogrammed dis connected assume the logical HIGH state and product terms with both true and complement of any input signal connected assume a logical LOW state The programmable functions on the PALCE16V8 are automatically configured from the user s design specifi cation which can be in a number of formats The design specification is processed by development software to verify the design and create a programming file This file once downloaded to a programmer configures the device according to the user s desired function The user is given two design options with the PALCE16V8 First it canbe programmed as a standard PAL device from the PAL16R8 and PAL10H8 series The PAL programmer manufacturer will supply device codes for the standard PAL device architectures to be used with the PALCE16V8 The programmer will pro gram the PALCE16V8 in the corresponding architec ture This allows the user to use existing standard PAL device files without making any changes to them This includes JEDEC files Alternatively the device can be programmed as PALCE16V8 Here the user must use the PALCE16V8 device code This option allows full utilization of the macrocell SLOx From Adjacent Macrocell macrocells MC and MC SG1 is replaced by SGO on the feedback multiplexer 12015
41. the menu bar items contains a different set of program options related to that menu function For example the options for finding a file or a directory are located in the File menu When you highlight one menu bar item its menu appears Notice that you can move laterally across the screen using the cursor movement arrows The status line at the bottom of the screen gives information about how to control the screen Check this information frequently because the information changes as you perform different tasks Use the arrow keys to move the cursor to the operation you wish to perform Get familiar with the menu by exploring the various options When you are ready to begin using the software functions proceed to Create the Decoder Design March 1989 Design a Decoder for the PALCE16V8 5 Create the Decoder Design Create the Decoder Design The simple decoder design is created in Boolean equations and implemented in a PALCE16V8 device Your first task in creating the design is to understand the function of the decoder and interpret the function in Boolean equations Note Although decoders are usually combinatorial for the purpose of this exercise assume a registered decoder design The Function of the Decoder Table 1 shows a truth table for the decoder The decoder has three input pins X Y and Z The function of the decoder is to monitor the three input pins and assert one of eight output lines A H for each of the eight com
42. tput disable times are tested with 5pF HIGH to high impedance tests are made to an output voltage of 0 5 with S open LOW to high impedance tests are made to an output voltage of Vo to 0 5V with S closed 5 Equivalent function to tezx texz but using product term control PALCE16V8H 15 25 xiii SWITCHING WAVEFORMS Input or tpp Register Combinatorial V Output T 12015 010 Combinatorial Output 12015 020A Clock Input Combinatorial ter tea Output Output 057 9 12019 0194 12015 013A Clock to Feedback to Combinatorial Output Input to Output Disable Enable See Path at Right Output 12015 014A 12015 011A Clock Width OE to Output Disable Enable Input or Feedback tor ty Clock to Registered Vy Output 12015 012 Registered Output Notes 1 1 5V 2 Input pulse amplitude 0 to 3 0 Input rise and fall times 2 5 ns typical xiv PALCE16V8H 15 25 SWITCHING TEST CIRCUIT Voc 07 Output Switching Test Circuit 12015 019 Notes on Testing Information Z gt H Open ter gt 2 Open 2 0 5V ee i zi6bsed 99PF 89944 79900 1 gt 2 Vo 40 5V Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS MUST BE WILL BE STEADY STEADY MAY CHANGE WILL CHANGING ees FROM H TOL MAY CHANGE WILL BE FROM L CHANGING DON T CARE CHANGING
43. ts X when the control is LOW and Y when the control is HIGH is shown below 12015 008A Figure 5 PAL Device Multiplexer Notice that the control is operated by a programmable cell that is initially disconnected from GND floating to Vcc selecting the 1 path through the multiplexer When the cell is programmed it is connected to GND selecting the 0 path through the multiplexer PALCE16V8H 15 25 ix cu gt aL gt LEE EES SB 3 4 4 9 7 0 MENT 4 4 44 4 4 4 4 41 1 41 122221111 gt i HEH ii Bt ET tut 12015 009A PALCE16V8H 15 25 e TITIO 1203 14 98 18173016 pnns nnen ax of mal VO 11 11 021 1141 111 1111 21 121 1224 2 1 94 Pett tt ttt Ht PT iy Figure 6 PALCE16V8 Logic Diagram PALCE16V8H 15 25 xi ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature 65 C to 150 C Commercial C Devices Ambient Temperature under bias 55 1 125 C Temperature T Operating Supply Voltage with Respect Free Air 0 C to 75 C to Ground 0 5V to 7 0V Supply Voltage Vec 4 75V to 5 25V DC Output Voltage pi 10 Vee Operating ranges define those limits between which the func 5
44. uency with external feedback or in conjunction with an equivalent speed device This fmax is designated external The second type of design is a single chip state ma chine with internal feedback only In this case flip flop outputs are defined by the device inputs and flip flop outputs Under these conditions the period is limited by the internal delay from the flip flop outputs through the internal feedback and logic to the flip flop inputs ts This is designated fmax internal The third type of design is a simple data path applica tion In this case input data is presented to the flip flop and clocked through no feedback is employed Under these conditions the period is limited by the sum of the data setup time and the data hold time ts t However as lower limit for the period of each fmax type is the mini mum clock period tw Usually this minimum clock period designates the period forthe third fvax des ignated fmax no feedback CLK SECOND CHIP ts 9 1 8 fmax External Feedback 1 ts tco CLK fma Internal Feedback 1 ts tcr CLK fmax No Feedback 1 ts ty or 1 tw 12015 020A xviii PALCE16V8H 15 25 PHYSICAL DIMENSIONS PD 020 140 200 125 160 014 023 12015 021 020 009 015 069700 PALCE16V8H 15 25 xix Programmers Development Systems su
45. ut can still be of the desired polarity It can also save DeMorganizing efforts Selection is through a programmable bit SL1 which controls an exclusive OR Gate at the output of the AND OR logic The output is active HIGH if SL1x is 1 and active LOW if SL1x is O PALCE16V8H 15 25 vii Registered Active LOW Registered Active HIGH Combinatorial Active LOW Combinatorial I O Active HIGH Combinatorial Output Active LOW Combinatorial Output Active HIGH gj Adjacent I O Dedicated Input 12015 005 Figure 2 Macrocell Configurations viii PALCE16V8H 15 25 Power Up Reset Allflip flops power up to a logic LOW for predictable sys tem initialization Outputs of the PALCE16V8 will de pend onwhether they are selected as registered or com binatorial If registered is selected the output will be LOW if combinatorial is selected the output is a func tion of the logic Electronic Signature Word An electronic signature word is provided in the PALCE16V8 device It consists of 64 bits of programm able memory that can contain user defined data The signature data is always available to the user independ ent of the security bit Programming and Erasing The PALCE16V8 can be programmed on standard logic programmers Approved programmers are listed in this data sheet The PALCE16V8 may be erased to reset a previously configured device back to its virgin state Bulk erase
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