FM489 User Manual
Contents
1. Le ma ma ats mea o ron s2 am mu 100 101 maa Fo 120 mam 102 10 na cra e7 leen 104 I 105 rensa cis ete Fena 106 17 exa tor k FPxs 108 100 pa mz ma lw mn it Laassunal at m 13 rexe ce vee rexsr ma 115 asvesviev ow m nz saveswrev asvesunev 118 119 FP_X38 K22 G23 FP_X39 120 Table 7 Front Panel IO daughter card pin assignment Bank B Connected to a global clock pin on the FPGA LVDS output not supported 9 Connected to a regional clock pin on the FPGA LVDS output not supported 2 Ybatt is connected to both Virtex 5 devices Vbatt pin FM489 User manual September 2009 www 4dsp com 16 FM489 user manual ur SE connector Signal Signal connector pin Name FPGApin FPGA pin name pin 291 repaz pie B z reps 122 128 renaz os ate FPN 12 4 125 rexo Hs k3 Lal e 127 repso c7 pe Fpp 123 129 Fenag pz ps Femo 130 91 rex e ez rexs 132 133 Fear pa E21 Fe pae 134 135 eena me p Fema 13 137 rex a pe Lei 1383 29 eppas ra een Fpp wun 10 eem oe B rena 12 1 rexe e ra Lal wu 145 Ieper mo Ba Fep 146 107 Fpnas Ho an Fens 148 10 px ae2. This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system FM489 User manual September 2009 www 4dsp com 93 FM489 user manual ur OS gt V2 2 8 Technical support Technical support for all 4DSP Product hardware software and firmware is available under 4DSP Terms and Conditions of Sales ONLY in its original condition AS SHIPPED unless agreed to by 4DSP and documented in writing prior to any modifications Terms and Conditions are available from htip Awww 4dsp com T Cs txt Technical support requests should be sent to support 4dsp com Any electrical connections made to the board or other components shall be made only with approved connectors as specifically identified in the products official documentation Any modification to hardware including but not limited to removing of components soldering or other material changes to in part or in whole to the PCM and or its components will immediately invalidate and make void any warranty or extended support if any Further and changes or modifications to software and or firmware supplied with the Product unless provided for in the Products official documentation shall im
3. B Lal wen a51 eppaz cae az FPPpas 152 153 renaz B22 ax Fem 154 155 FPpxso cas cs exs 156 157 epp e cz FPpso we i59 pma e p FPNSO 160 161 Fpxse peo aso rexa e 163 epps vee Ber FPps2 we 165 eens e a FPns we 167 Fpxs4 Bso cso Fexss 168 169 Ire B czs Fe ps4 170 mu epnss awe Der Fpensa 172 173 exse pa as rex 7 4 175 rpe pss yoo an Fe pss 17 a77 Fess sa aen rense 178 179 FPx58 B pst FPx59 mm Table 8 Front Panel IO daughter card pin assignment Bank C FM489 User manual September 2009 www 4dsp com V2 2 17 FM489 user manual ur OS gt V2 2 3 5 2 Power connection to the front panel I O daughter card The Front Panel I O daughter card on side 1 of the PCB is powered via a 7 pin connector of type BKS Samtec Each pin can carry up to 1 5A The power connector s pin assignment is as follows 41 43gv 330 2 3 45v GND 4 5 12v GND 6 7 ax Table 9 Daughter card power connector pin assignment on PMC side 1 On side 2 of the PCB the daughter card is powered via a 33 pin connector of type BKS Samtec Each pin can carry up to 1 5A The power connector s pin assignment is as follows 4 van GND 2 3 am GND 4
4. ke u5 rex a rem s e rem 3 ss ren re ev rm a o ex o ka rxs 4 as epep wg mo reps a a rpnia w o FPnis 4 47 exa Ks k2 rxs se 49 ep pue K8 J14 FP p17 50 FM489 User manual September 2009 www 4dsp com 15 FM489 user manual ur EB LT V2 2 o Luew m3 Lucie e exe ap s2 Lui s se rp pia ma ku repro e 5 rpnie ms sm re nig s 59 FP_X18 H12 F14 FP X19 60 Table 6 Front Panel IO daughter card pin assignment Bank A Connected to a global clock pin on the FPGA LVDS output not supported 9 Connected to a regional clock pin on the FPGA LVDS output not supported Connector FPGA FPGA Connector e rero an mo mr 62 es reno cr Ho mena 64 ee exo ets em mxi e er repo cs m lee oa ee renee we ais pw 70 nm mx ou rie rxs z 7a pipes no mo repos 7 75 eena vo cto rens m 77 maa Lo we mae z 79 repo ro E12 reez so ei renee re ers renz ss exs us cro ewe 4 se ma em e9 mr s er reng en cs Fon 0 exs Fre m ewe oo 9 reps s3 m2 reps 2 rens cis cre Fena o 95 exo er Gao rex
5. 0 Flashing FPGA A or B bitstream or user _ ROM _register is currently being written to the flash ON FPGA A not configured OFF FPGA A configured LED 1 Flashing FPGA A or B bitstream or user_ROM_register is currently being written to the flash ON FPGA B not configured OFF FPGA B configured LED 2 Flashing The Virtex 4 device has been configured with the safety configuration bitstream programmed in the flash at factory Please write a valid Virtex 4 device bitstream to the flash FM489 User manual September 2009 www 4dsp com 11 FM489 user manual ur OS gt V2 2 ON Flash is busy writing or erasing OFF Flash device is not busy LED 3 ON CRC error Presumably a wrong or corrupted FPGA bitstream has been written to the flash Once on this LED remains on CPLD LED3 3 CPLD LED2 Si Bla CPLD LED ek 12 mm CPLD LEDO 18 Ra IEN Figure 5 CPLD LED locations 3 2 3 JTAG A JTAG connector is available on the FM489 for configuration purposes The JTAG can also be used to debug the FPGA design with the Xilinx Chipscope A press fit connector is delivered that can be plugged into the connector holes The JTAG connector is located on side 1 of the PCB see Figure 6 Figure 6 JTAG connector J6 location FM489 User manual September 2009 www 4dsp com 12 FM489 user manual ur OS gt V2 2 The JTAG connector pinout is as follows Table 5 JTAG pin
6. UC 12V daughter card Low noise 2 5V regulator Switching 1 8V regulator Switching 1 2V regulator Switching 1 0V regulator Switching 0 9V regulator 12V 5V 3 3V 12V External Power connector Figure 9 Power supply An ADT7411 device is used to monitor the power on the different voltage rails as well as the temperature The ADT7411 data are constantly passed to the Virtex 4 device Measurements can be accessed from the host computer via the PCI bus A software utility delivered with the board allows the monitoring of the voltage on the 2 5V 1 8V 1 2V 1 0V and 0 9V rails It also displays both FPGAs junction temperature 4 1 External power connector for stand alone mode An external power connector J2 is available on side 2 of the PMC next to the PMC connectors It is used to power the board when it is in stand alone mode This is a right angled connector and it will be mounted on board only if the card is ordered as a stand alone version FM489 SA The height and placement of this connector on the PCB breaches the PMC specifications and the module should not be used in an enclosed chassis compliant to PMC specifications if the external power connector is present on board Do not connect an external power source to J2 if the board is powered via the PMC connectors Doing so will result in damaging the board The external power connector is of type Molex 43045 1021 Each circuit can carry a maximum current of 5A The
7. connector pin assignment is as follows Pin Signal Signal Pin 1 33av 33V 2 3 v 5 4 5 GND GND 6 7 GND GND 8 oa lax 12V 10 Table 13 External power connector pin assignment FM489 User manual September 2009 www 4dsp com 21 FM489 user manual ur r V2 2 WARNING UNREGULATED UNPROTECTED EXTERNAL POWER SUPPLY CONNECTION This board is designed with an UNSUPPORTED feature for an external power connector labeled as J2 Mounting a connector on the PCB breaches the PMC electrical and mechanical specifications of the PMC standard This is a FACTORY ONLY feature that is used in the manufacturing process when powering the board is required in an UN MOUNTED PCI bus mode thus in stand alone mode DO NOT connect an external power source to J2 doing so may result in damaging the board and will automatically VOID WARRANTY Consult factory for further information FM489 User manual September 2009 www 4dsp com 22 FM489 user manual ur SE 5 Environment 5 1 Temperature Operating temperature e OC to 60 C Commercial e 40 C to 85 C Industrial Storage temperature e 40C to 120C 5 2 Convection cooling 600LFM minimum 5 3 Conduction cooling V2 2 The FM489 can optionally be delivered as conduction cooled PMC The FM489 is compliant to ANSI VITA 20 2001 standard for conduction cooled PMC 6 Safety This module presents no hazard to the user 7 EMC
8. ee 6 3 1 2 ler ee 9 3 2 FPGA devices Configuraton nenne nnnnn nenn nenne nenne nnnnn nenne nenne nnnnnenn 10 3 2 1 PASIAN SO e GR 10 3 2 2 CREDIT ee eu 10 3 2 3 JPA E 12 3 3 BOCK een 13 3 4 Memory ele 14 3 4 1 BEASTODR2ZSBPAN ea ee 14 3 4 2 BLAST DDR2 SDRAM een 14 3 4 3 BLAST DDRS SDRAM Zee re ee nee 14 3 4 4 DORZ SDRAM ee een ea ne en ee eek 14 3 5 Front Panel 1O fe toile EE 15 3 5 1 Virtex 5 device to I O front Panel daughter Card 15 3 5 2 Power connection to the front panel I O daughter Card 18 3 6 Font Panel OCI CT nee ee ee 19 4 Powerregu iemeniS SORBBENERERDENSINNNE REED EEE ERSENENERESBEEREE DE AERENFEEESEEREREFERENNEBEE SEBEEEEEEPEBNNEREESSER 20 4 1 External power connector for Stand alone mode onen nennen nennen 21 5 ENVIRONMENT ses Essen nen na scien EE Ewa ernennen ernennen een nn Een 23 5 1 Thee 23 5 2 CONVECTION COO ne ME 23 5 3 COICO COON EE 23 O E 23 T EMO SPESEN E RE BE EN ESEA 23 Se Ve 11 aller 1 Be 18 61 0101 essin a EE Ee AEREE EEEN ENS 24 PPB 0 11 1 1 Ur E 24 10 UE UNG E 25 FM489 User manual September 2009 www 4dsp com 3 FM489 user manual ur OS gt V2 2 1 Acronyms and related documents 1 1 Acronyms PCI Peripheral Component Interconnect PCI e PCI Express oo PLL Phase Locked Loop SDRAM Synchronous Dynamic Random Access memory SRAM Synchronous Random Access memory Table 1 Glossary 1 2 Related Documents e IEEE Std 1386 1 2001 IEEE Standard Phy
9. single ended l or 32 LVDS pairs WE ED ED nd Ena User VO PCI Express XMC PCI X PCI 66 33MHz 64 32 bit Figure 1 FM489 block diagram FM489 User manual September 2009 www 4dsp com 5 FM489 user manual ur OS gt V2 2 2 Installation 2 1 Requirements and handling instructions e The FM489 must be installed on a motherboard compliant to the IEEE Std 1386 2001 standard for 3 3V PMC e Do not flex the board e Observe SSD precautions when handling the board to prevent electrostatic discharges e Do not install the FM489 while the motherboard is powered up 2 2 Firmware and software Drivers API libraries and a program example working in combination with a pre programmed firmware for both FPGAs are provided The FM489 is delivered with an interface to the Xilinx PCI core in the Virtex 4 device as well as an example VHDL design in the Virtex 5 device so users can start performing high bandwidth data transfers over the PCI bus right out of the box For more information about software installation and FPGA firmware please refer the FM489 Get Started Guide 3 Design 3 1 FPGA devices The Virtex 4 and Virtex 5 FPGA devices interface to the various resources on the FM489 as it is shown on Figure 1 They also interconnect to each other via 68 general purpose pins and 4 clock pins 2 pairs one in each direction 100Q terminated 3 1 1 Virtex 4 device 3 1 1 1 Virtex 4 device family and package The Virtex 4 device is
10. 5 aav GND 6 7 as GND 8 9 v GND 10 on 5v GND 12 13 5v GND 14 15 45V GND 16 17 nx GND 18 ig nz GND 20 21 ax GND 22 23 12V GND 24 25 GND reserved 26 27 Reserved reserved 28 29 Reserved reserved 30 31 Reserved reserved 32 33 GND Table 10 Daughter card power connector pin assignment on PMC side 2 FM489 User manual September 2009 www 4dsp com 18 FM489 user manual ur OS gt V2 2 3 6 Front Panel Rocket lO Eight Rx Tx Multi Gigabit Transceivers connected to FPGA B are available in the front panel area on two connectors of type QTE These connectors provide a base for a daughter card dedicated to high bandwidth communication via optical transceivers or copper please refer to the FM489 web page for more details about available daughter cards Infiniband protocols as well as Gigabit Ethernet OC48 and Fibre channel SFPDP can be implemented over the transceivers Eight LVTTL signals four per connector are also available for daughter card control Two low jitter clocks 106 25MHz or 125MHz are directly connected to the MGT clock inputs so multi rate applications can be implemented on the FM489 The MGT banks have power supplies independent from the digital supply provided to the FPGAs in order to insure low noise and data integrity LDO regulators are used to generate the 1V 1 2V and 2 5V necessar
11. FM489 user manual ur OS gt V2 2 FM489 User Manual 4DSP Inc 955 S Virginia Street Suite 214 Reno NV 89502 USA 4DSP bv Crown Business Centre Leidse Schouw 2 2408 AE Alphen a d Rijn Netherlands Email support 4dsp com This document is the property of 4DSP Inc and may not be copied nor communicated to a third party without the written permission of 4DSP Inc 4DSP 2008 FM489 user manual ur OS gt V2 2 Revision History Date Revision Version March 5 2008 First release ao April 10 2008 Major updates 1 1 February 18 2009 Updated the DDR2 sdram size to be maximum 1 2 256MB Updated the JTAG pin locations Updated the DIP switch March 3 2009 Updated the Pn4 table 2 0 Apr 29 2009 Added the technical support chapter and the 2 1 external power warning Sept 8 2009 Modified QTE connector pinout table 2 2 FM489 User manual September 2009 www 4dsp com FM489 user manual ur OS gt V2 2 Table of Contents 1 Acronyms and related documents uussuuuuunnanunnnnnnnnnnunnanunnnnnnnnnnnnnanunnnnnnnnnnennanen 4 1 1 PAG el EEN 4 1 2 Pre ete DOG UN NS nenn ee ee 4 1 3 General COSC HID MON Eee ee een 5 2 ANSIAllaHlon scissa cennssticeedewetansannsosnsceeeneiscanwacseessaeoneetteeceeesennees 6 2 1 Requirements and handling instructions nenne nenn nenne nenn nnne nennen 6 2 2 Firmware and SCH WAS ee nee ser 6 3 ES E 6 3 1 FP CCS ea ee ee ee 6 3 1 1 VIe CC ee ee en
12. assignment 3 3 Clock tree The FM489 clock architecture offers an efficient distribution of low jitter clocks Both FPGA devices receive a low jitter 125MHz clock A low jitter programmable clock able to generate frequencies from 62 5MHz to 255 5MHz in steps of 0 5MHz is also available This clock management approach ensures maximum flexibility to efficiently implement multi clock domains algorithms and use the memory devices at different frequencies Both clock buffer devices CDM1804 and the frequency synthesizer ICS8430 61 are controlled by the Virtex 4 device Two MGT reference clocks of 106 25MHz or 125MHz Epson EG2121CA are connected to the Virtex 5 device and make it possible to implement several standards over the MGT I Os connected to the optical transceivers 16MHz Low jitter DDR QDR A Frequency DDR i d T synthesizer PCUPCI X Aa ae 33 66 1 33MHz i ho 2 Daughter Virtex 5 Intex nd T Et KH Clock buffer LVPECL Ks Low jitter LYCMOS m 31 25MHz MGT clock Low jitter eco MGT clocks zor 125MHz or 106 25MHz Clock synthesizer Figure 7 Clock tree FM489 User manual September 2009 www 4dsp com 13 FM489 user manual ur OS gt V2 2 3 4 Memory resources 3 4 1 BLAST QDR2 SRAM A maximum of 3 QDR2 SRAM devices can be connected to the virtex 5 device This requires every BLAST site to be populated with a QDRII SRAM The QDR2 SRAM device available on the FM489 is 2M words deep 9Mbyt
13. ce In the default FPGA firmware the LEDs are driven by the Virtex 5 device via the inter FPGA interface The LEDs are located on side 2 of the PCB in the front panel area 2 TP Geste FPGA LED3 e jie JEE nm FPGA LED2 P del d ag IE a E FPGA LED1 FEN See FPGA LEDO Figure 2 FPGA LED locations FM489 User manual September 2009 www 4dsp com 7 FM489 user manual ur OS gt V2 2 3 1 1 6 Pn4 user I O connector The Pn4 connector is connected to the Virtex 4 device The 32 lower bits are available only if an XC4VFX60 device is mounted on board All signals are single ended 3 3V 2 5V or 1 8V signalling can be chosen for Pn4 Signal FPGA oe Signal a 1 Pna oo Log m4 Pic 2 3 Loes ou pol 4 5 Paio H13 Hu Piss 6 7 Pna o6 H12 u Png tov 8 9 Pna os vie A Pmt tog 10 1 Pn4toto Hie g4 Png tort 12 13 P 012 K13 K Png tors 14 15 Pnatoi4 yis Ki Pm1015 16 17 LPmg og mo Pna 1017 18 19 Lpnoglun m9 pol 20 21 Pn4 020 Nn8 Pe Png 1021 22 23 Pn41022 Nn7_ ne Pn 023 24 25 Pn4 1024 P11 N9 Pm 1035 26 27 Lpnooeleg P9 Pn 0277 28 29 Pn4 1028 P8 R7 Pm 1029 30 31 Loupe Re Ip 32 33 Pn4 1032 N21 m20 Pna os 34 35 Pn41034 m21 m9 Pn 035 36 37 Pn41036 N18 P Pn4 1037 38 29 Pna ioss n 7 M Pns 1039 40 41 P
14. e at the time of order Using the Xilinx DCI termination options to match the signals impedance allows many electrical standards to be supported by this interface All signals are routed as 1000 LVDS pairs and optionally 1000 terminations can be fitted on the card The VRP and VRN pins on the I O banks connected to the daughter card connector are respectively pulled up and pulled down with 500 resistors in order to ensure optimal performances when using the Xilinx DCI options The VREF pins are connected to 0 9V for DDR2 DCI terminations Please contact 4DSP Inc for more information about the daughter card types available The 180 pin Samtec connector pin assignment is as follows All signals are shown as LVDS pairs in the table but they can be used for any standard that does not breach the electrical rules of the Xilinx I O pad Connector Signal Signal Connector 1 rppo ne 7 Lenz 3 epno me pe rm 4 5 exo wo m x 6 7 pp re ns reps 8 rm u s eens 10 1m ex to rp PX 12 13 re n m Pa 14 as em nv mw FPN5 416 1 ex pm pm r s 1 pppoe m gz rer 20 a rnu is k ren 2 L 2 exs r u rx a 2 ere Hr ce pro 2 en y a epno 2 ex pm use Px 30 L a ppp s Hs rep 32 oa Lui 5 o renn a e rPxo
15. es 2Mx36 3 4 2 BLAST DDR2 SDRAM One 32Mx32 bit DDR2 SDRAM device up to 128Mbytes per BLAST site is possible This will give the Virtex 5 device a maximum of 3 DDR2 banks with a total memory size of 756 MB 3 4 3 BLAST DDR3 SDRAM With the DDR3 SDRAM BLAST it is possible to have 6 ddr3 memory banks of 256 Mbytes that connect to the Virtex5 device Each BLAST has two independent ddr3 memory banks 3 4 4 DDR2 SDRAM One 64Mx32 bit DDR2 SDRAM device up to 256Mbytes is connected to the Virtex 4 FPGA device This memory resource can be accessed by the PowerPC processor in the Virtex 4 device or can be used as a data buffer for custom user logic Note 256Mbytes of DDR2 SDRAM is available for the Virtex 4 FX60 only FM489 User manual September 2009 www 4dsp com 14 FM489 user manual ur OS gt V2 2 3 5 Front Panel IO daughter card 3 5 1 Virtex 5 device to I O front Panel daughter card Only available with daughter card purchase The Virtex 5 device interfaces to a 180 pin connector placed in the Front panel I O area on both side 1 and side 2 of the PCB It serves as a base for a daughter card and offers I O diversity to the FM489 PMC On side 2 of the PCB the connectors and mounting holes placement complies with the SLB standard except for the 1 5V mounting hole that is not present on this module The FPGA I O banks are powered either by 1 8V 2 5V or 3 3V via a large 0 ohms resistor 3 3V is the default if not specified otherwis
16. from the Virtex 4 FX family It can be either an XC4VFX20 or XC4VFX6O0 in a Fineline Ball Grid array with 672 balls FF672 3 1 1 2 Power PC embedded processor Up to two IBM PowerPC RISC processor cores are available in the Virtex 4 device This core can be used to execute C based algorithms and control the logic resources implemented in the FPGA 3 1 1 3 Virtex 4 device external memory interfaces The Virtex 4 device is connected to a SDRAM bank with a 32 bit data bus width The total SDRAM memory size can be up to 256MB This memory resource can be used by the PowerPC core or can serve as data buffer FM489 User manual September 2009 www 4dsp com 6 FM489 user manual ur OS gt V2 2 3 1 1 4 PClinterface The Virtex 4 device interfaces directly to the PCI bus via the PMC Pn1 Pn2 and Pn3 connectors An embedded PCI core from Xilinx is used to communicate over the PCI bus with the host system on the motherboard PCI X 64 bit 66MHz 133MHz PCI 64 bit 66MHz and PCI 32 bit 33MHz are supported on the FM489 The bus type must be communicated at the time of the order so the right Virtex 4 device firmware can be loaded into the flash prior to delivery The following performances have been recorded with the FM489 transferring data on the bus gt PCI X 64 bit 133MHz 750Mbytes s sustained gt PCI X 64 bit 66MHz 450Mbytes s sustained gt PCI 32 bit 33MHz 120Mbytes s sustained 3 1 1 5 LED Four LEDs are connected to the Virtex 4 devi
17. mediately invalidate and make void any warranty or extended support if any 9 PCB revisions Below a summary of the main differences between the PCB revisions V2 MGT reference clocks are AC coupled The XMC reference clock has moved to balls AF3 and AF4 Added protection circuitry to prevent damage in 12V XMC main boards V3 Modified the frontpanel IO area to support 4 optical transceivers To do this the MGT connectors have been removed and the card is not compatible anymore to the conduction cooling specification The BLAST site 0 and 1 have been remapped to be able to have the ddr3 signals compatible with the Xilinx MIG design The XMC reference clock has been moved to balls Y3 and Y4 The MGT reference clock for the Optical tranceivers is mapped to balls D8 and C8 The XMC nMRSTI control signal has been connected to ball B18 The rest of the XMC control signals are disconnected Modified the VPOWER protection circuitry FM489 User manual September 2009 www 4dsp com 24 FM489 user manual u EB LIT V2 2 10 Warranty FM489 User manual September 2009 www 4dsp com 25
18. na 1040 Pp21 P Pna oa 42 43 Pn4 1042 p20 N19 Pn4 043 44 45 Pn41044 R8 PB Pna 1045 46 47 Lpnoagleg R6 Pn4 1047 48 49 Pn4 1048 aaia AB12 Pn4 1049 op 51 Pn4 1050 AA13 AAt2 Pn4 051 SS 53 Pn4 1052 aB14 Ac s Pn4 1053 54 SS Pn4 1054 ac14 ac12 Pn4 1055 56 Si Pn4 1056 aD15 AE13 Pn4 1057 58 59 Pn4 1058 AD14 AD13 Pn4 059 6o 61 Pn4 1060 aE15 AF14 Pn4 1061 62 I 63 Pn4_1062 AF15 AF13 Pna 1068 64 Table 2 Pn4 pin assignment FM489 User manual September 2009 www 4dsp com 8 FM489 user manual ur OS gt V2 2 3 1 2 Virtex 5 device 3 1 2 1 Virtex 5 device family and package The Virtex 5 device is dedicated to Digital Signal Processing applications and can be chosen from the SXT or LXT family devices Its package is based on Fineline Ball Grid array with 1136 balls In terms of logic and dedicated DSP resources the FPGA B can be chosen from the following types LT110T and SX95T 3 1 2 2 Virtex 5 device BLAST interfaces BLAST Board Level Advanced Scalable Technology is a small PCB module that allows customization of the FM489 in memory extensions processing units and communication interfaces Each FM489 can be populated by up to 3 BLAST modules BLAST modules available e QDRII SRAM memory device 1 x 2M x 32 bit MBytes e DDR2 SDRAM memory device 1 x 32M x 32 bit 128MBytes e DDR3 SDRAM memo
19. ry device 2 x 64M x 16 bit 256MBytes e ADV212 JPEG2000 compression devices 2 CODECs e 8GB NAND Flash Solid State Drive 3 1 2 3 Virtex 5 device interface to Front Panel daughter card The Virtex 5 device interfaces to the front panel daughter card on the FM489 via a high speed connector 174 I Os are available from the FPGA to from the daughter card Refer to the Front Panel I O section of this document for more details about the daughter card connector electrical characteristics FM489 User manual September 2009 www 4dsp com 9 FM489 user manual ur OS gt V2 2 3 2 FPGA devices configuration 3 2 1 Flash storage The FPGA firmware is stored on board in a flash device The 512Mbit device is partly used to store the configuration for both FPGAs In the default CPLD firmware configuration the Virtex 4 device A and the Virtex 5 device B are directly configured from flash if a valid bitstream is stored in the flash for each FPGA The flash is pre programmed in factory with the default firmware example for both FPGAs l S29GL512M 512Mbit Flash amp bit parallel configuration CoolRunner Il CPLD Virtex 4 XC2C256 VO100 DIP switch Figure 3 Configuration circuit 3 2 2 CPLD device As shown on Figure 2 a Cool Runner Il CPLD is present on board to interface between the flash device and the FPGA devices The CPLD is used to program and read the flash The data stored in the flash is transferred from the host mo
20. sical and Environmental Layers for PCI Mezzanine Cards PMC e ANSI VITA 39 2003 PCI X for PMC and Processor PMC e ANSI VITA 20 2001 Conduction Cooled PMC e ANSI VITA 42 0 2005 XMC Switched Mezzanine Card Auxiliary Standard e IEEE Std 1386 2001 IEEE Standard for a Common Mezzanine Card CMC Family e Xilinx Virtex 4 user guides e Xilinx Virtex 5 user guides e Xilinx PCI X core datasheet FM489 User manual September 2009 www 4dsp com 4 FM489 user manual ur OS gt V2 2 1 3 General description The FM489 is a high performance PMC X or XMC module dedicated to data acquisition processing and communication applications with complex requirements Built on the success of the FM48x series the FM489 offers two FPGAs the Virtex 4 and the Virtex 5 The latter has direct links to the BLAST sites BLAST is an innovative and modular technology for the newer high performance FM489 PMC X and XMC modules BLAST Board Level Advanced Scalable Technology is a small PCB module that allows customization of the FM489 in memory extensions processing units and communication interfaces Each FM489 can be populated by up to 3 BLAST modules Optional Front Panel IO 4x 2 5Gb s optical daughter card transceivers UCR er Rocket I0 FPGAB XCSVLX110T XCSVSX95T Configuration circuit Tac POI express TED ma xd Flash 512 Wem em d FPGA A Mbit ACAVFX20 60 SDRAM LED xd 64
21. therboard via the PCI bus to the Virtex 4 device and then to the CPLD that writes the required bit stream to the storage device A 31 25 MHz clock connects to the CPLD and is used to generate the configuration clock sent to the FPGA devices At power up if the CPLD detects that an FPGA configuration bitstream is stored in the flash for both FPGA devices it will start programming the devices in SelecMap mode Do NOT reprogram the CPLD without 4DSP s approval The CPLD configuration is achieved by loading with a Xilinx download cable a bitstream from a host computer via the JTAG connector The FPGA devices configuration can also be performed using the JTAG FM489 User manual September 2009 www 4dsp com 10 FM489 user manual ur OS gt V2 2 3 2 2 1 DIP Switch A switch J1 is located next to the JTAG programming connector J6 see Figure 4 The switch positions are defined as follows 1 Sw1 OFF Default setting The Virtex 4 device configuration is loaded from the flash at power up ON Virtex 4 device safety configuration loaded from the flash at power up To be used only if the Virtex 4 device cannot be configured or does not perform properly with the switch in the OFF position Sw2 Reserved Sw3 Reserved Sw4 Reserved Table 3 Switch description 3 2 2 2 LED and board status Four LEDs connect to the CPLD and give information about the board status LED
22. work load By using high efficiency power converters all care has been taken to ensure that power consumption will remain as low as possible for any given algorithm After power up the FM489 typically consumes 2 Watts of power For precise power measurements it is recommended to use the Xilinx power estimation tools for both the Virtex 4 and Virtex 5 FPGA devices The maximum current rating given in the table below is the maximum current that can be drawn from each voltage rail in the case resources are used to their maximum level Device Interface Voltage Maximum current rating DCI and memory reference 0 9V 5A voltage Virtex 5 device core 1 0V 12A Virtex 4 device core 1 2V 12A QDR2 DDR2 SDRAM core and 1 8V 10A UO banks Virtex 4 devices IC banks connected to the front panel daughter card Virtex 4 device O bank 3 3V 2A connected to the PCI bus Flash CPLD front Panel I O daughter card Front Panel IO daughter card 5V 1A Front Panel IO daughter card 12V 0 5A Front Panel IO daughter card 12V 0 5A MGT power supply 1 2V 1 5V 2 5V 1 7A 0 5A 0 01A Virtex 5 device WO bank 1 8V 2 5 3 3V 1 5A respectively Table 12 Power supply Optionally the FM489 can be used as a stand alone module and is powered via the external power connector FM489 User manual September 2009 www 4dsp com 20 FM489 user manual ur OS gt V2 2 PMC XMC connectors 12V re Front Panel
23. y for the MGT to operate The power filtering network includes a 220nF decoupling capacitor and ferrite bead MP21608S221A per power pin The signal differential pairs are routed on a specific inner layer with one reference GND plane on each side of the layer stack up Low jitter MGT clocks Standard PMC edge 125MHz or Front Panel 106 25MHz Front Panel Panel MGT VO ee Daughter Daughter Virtex 4 Virtex 5 card Power supply for MGT 1 0V 1 2V and 2 5V Figure 8 Multi Gigabit signals The table below provides the pinout for the two independent QTE connectors Pin Signal Signal Pin Pin Signal Signal Pin 41 Rxp37 3 3V 2 15 Txn2 6 CTRL9 7 16 3 runs 3 3V 4 17 RxpiS GND 18 5 Txp37 3 3v 6 19 Rxnt GND 20 7 Txng7 3 3vV 8 21 Txp15 GND 22 9 Rxp2 6 CTRLO4 10 23 Txnt GND 24 141 Rxn2 6 CTRL1 5 12 25 Rxn0 4 Txn0 4 26 13 Txp2 6 CTRL2 6 14 27 Rxpo4 Txpo4 28 Table 11 QTE connector pinout FM489 User manual September 2009 www 4dsp com 19 FM489 user manual ur OS gt V2 2 4 Power requirements The Power is supplied to the FM489 via the PMC or XMC Several DC DC converters generate the appropriate voltage rails for the different devices and interfaces present on board The FM489 power consumption depends mainly on the FPGA devices
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