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dio24 manual - RTD Embedded Technologies, Inc.

1. CMOS buffer 12 mA max TTL buffer 16 mA max Low level output current Isink CMOS buffer 24 mA max TTL buffer 64 mA max INPUEIOAO RE 10 HA ect nan Ra u qu GS 10 pF Input capacitance prot A A 10 pF Output capacitance ee tipo e MA Z u u NAB 20 pF Timer Counters ien EN CMOS 82054 Three 16 bit down counters 6 programmable operating modes Counter input source External clock 8 MHz max or on board 8 MHz clock Counter outputs Available externally used as PC interrupts Counter gate source External gate or always enabled Current Requirements 194 mA 5 volts Connectors P2 50 pin right angle shrouded box header P6 20 pin box header Size Short slot 3 875 H x 5 25 W 99mm x 134mm A 4 APPENDIX B VO CONNECTOR PIN ASSIGNMENTS B 1 B 2 I O Connector P2 PCO PC1 PC2 PC3 PC4 PC5 PC6 PC7 PBO O e e Y U v uU ki PA7 5 VOLTS 9 e 9 O E e On board Connector P6 PC0 PC2 PC4 Pce DIGITAL GND EXT GATE 0 EXT CLK 1 T C OUT 1 EXT GATE 2 DIGITAL GND B 3 EXTINT D
2. 4 5 BA 5 Interrupt Status Clear Read Write 4 5 LE EE 4 6 BA 7 u uapa santai u waq S ansa NGA Qa a na hn 4 6 BA 8 8254 Timer Counter 0 Read Write 4 6 BA 9 8254 Timer Counter 1 Read Write 4 6 BA 10 8254 Timer Counter 2 Read Write 4 6 BA 11 8254 Control Word Write Only P 4 6 Programming the DON qutm eek een einen 4 7 Clearing and Setting Bits ih 3 Poll nn een 4 8 Initializing the KN 4 9 Digital O Operations un nr anaiai aeaio anaiai 4 9 a EE 4 9 OT 4 11 What Is an AA AA 4 11 Interrupt Request Lines u A u de eo u W s sa am NI 4 11 8259 Programmable Interrupt Controller 4 11 Interrupt Mask Register IMR aanne a 4 11 End of Interrupt EOI Command 4 11 What Exactly Happens When an Interrupt Occurs 4 11 Using Interrupts in Your Programs 4 12 Writing an Interrupt Service Routine ISR J e a 4 12 Saving the Startup Interrupt Mask Regi
3. DIO24 User s Manual UO Real Time Devices Inc Accessing the Analog World DIO24 Seeme User s Manual Un REAL TIME DEVICES INC Post Office Box 906 State College Pennsylvania 16804 Phone 814 234 8087 FAX 814 234 5218 Published by Real Time Devices Inc P O Box 906 State College PA 16804 Copyright 1992 by Real Time Devices Inc All rights reserved Printed in U S A Rev B 9352 Table of Contents INTRODUCTION zusenden i 1 Digital MO EE i 3 What Comes With Your Board Qu a a Naam iN o i 3 Board EE i 3 Using This Manual a usu orte an deet EENEG i 4 When You Need Help a BAGA Hie a u a q Do ERAN NG Edi i 4 CHAPTER 1 BOARD SETTINGS 1 1 Factory Configured S witch and Jumper Settings 1 3 P3 Interrupt and Interrupt Channels Factory Setting GND Connected Interrupt Channels Disabled 1 4 P4 Interrupt Source Select Factory Setting EXT 1 4 P5 8254 Timer Counter Clock Sources Factory Settings CLKO XTAL CLK1 OUTO CLK2 OUT1 1 5 S1 Base Address Factory Setting 300 hex 768 decimal 1 6 S2 Buffer Bypass Switch Factory Setting OPEN Not Bypassed 1 7 Fl External 5 volt EE 1 7 Pull up Pull down
4. 4 4 When bit 7 of this word is set to 0 a write can be used to individually program the Port C lines Set Reset Bit Set Reset x Function Bit Bit Select 0 set bit to 0 0 active 000 PC0 set bit to 1 001 PC1 010 PC2 011 PC3 100 PC4 101 PC5 110 PC6 111 PC7 For example if you want to set Port C bit 0 to 1 you would set up the control word so that bit 7 is 0 bits 1 2 and 3 are 0 this selects PCO and bit 0 is 1 this sets PCO to 1 The control word is set up like this 0 x x X 0 0 0 1 Sets PCO to 1 written to BA 3 X don t care Set Reset Function Bit Bit Select 000 PCO BA 4 IRQ Enable Write Only Enables and disables interrupt generation Writing a 1 enables interrupt generation writing a 0 disables interrupt generation Interrupt Enable Disable 0 interrupt disabled 1 interrupt enabled BA 5 Interrupt Status Clear Read Write A read shows the status of the interrupt bit 0 only as defined below A write clears the interrupt data written is irrelevant Each time the interrupt status bit goes high a write should follow to clear the bit Interrupt Status 0 no interrupt 1 interrupt has occurred BA 6 Reserved BA 7 Reserved BA 8 8254 Timer Counter 0 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded BA 9
5. EXTENDED TEMPERATURE Ta 40 C to 85 C for Extended Temperature Symbol Parme ecm Ca we e es wo ram 25 25 sl e m ws Gate Delay orSamping 25 25 ls intel 82C54 WAVEFORMS WRITE DATA 8US 231244 14 DATA BUS m u m 231244 15 RECOVERY 231244 16 3 98 82054 CLOCK AND GATE 231244 17 Last byte of count being written A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT INPUT OUTPUT ee 231244 18 A C Testing inputs are driven at 2 4V for a logic 1 and 0 45V 231244 19 for a logic 0 Timing measurements are made at 2 0V for a logic C rol P 1 and 0 8V for a logic 0 L includes Jig capacitance 3 99 WB APPENDIX D WARRANTY LIMITED WARRANTY Real Time Devices Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from REAL TIME DE VICES This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period REAL TIME DEVICES will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to REAL TIME DEVICES All replaced parts and products become the property of REAL TIME DEVICES Before returning
6. 82C55A 82C55A FUNCTIONAL DESCRIPTION General The 82C55A is a programmable peripheral interface device designed for use in intel microcomputer sys tems Its function is that of a general purpose O component to interface peripheral equipment to the microcomputer system bus The functional configu ration of the 82C55A is programmed by the system software so that normally no external logic is neces sary to interface peripheral devices or structures Data Bus Buffer This 3 state bidirectional 8 bit buffer is used to inter face the 82C55A to the system data bus Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU Control words and status information are also transferred through the data bus buffer Read Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words It accepts inputs from the CPU Address and Control busses and in turn issues commands to both of the Control Groups Group A and Group B Controls The functional configuration of each port is pro grammed by the systems software In essence the CPU outputs a control word to the 82C55A The control word contains information such as mode bit set bit reset etc that initializes the func tional configuration of the 82C55A SE nn mr un Each of the Control blocks Group A and Group B accepts
7. 1 5 8254 Timer Counter Circuit Block Diagram u 1 6 Base Address Switeh oia 1 6 Port Buffer CHEN us iSe 1 8 Port A Pull up Pull down Resistor Circuitry 1 9 Adding Pull ups and Pull downs to Some Digital I O Lines 1 9 P2 and P6 I O Connector Pin Assignments 2 4 DIO24 Block Diagram RD 3 3 8254 Timer Counter Circuit Block Diagram sen vecenre 4 10 ili INTRODUCTION The DIO24 series boards are general purpose digital I O board for use in the IBM PC XT AT or compatible computer The DIO24 series has two models the DIO24 1 and the DIO24 2 with timer counters Installed within a single short or full size expansion slot in the computer the DIO24 features 24 TTL CMOS 8255 based programmable digital I O lines Direct connection to opto 22 I O system modules Buffered outputs for high driving capability Three 16 bit timer counters DIO24 2 model only e Optional pull up pull down resistors Simple I O or strobed I O operation Software enabled interrupts IRQ2 IRQ7 Assembly BASIC Turbo Pascal and Turbo C source code diagnostics program The following paragraphs briefly describe the major function
8. Customer Service Department at 814 234 8087 If you require service outside the U S contact your local distributor Board Accessories In addition to the items included in your DIO24 package Real Time Devices offers a full line of accessories Call your local distributor or our main office for more information about these accessories and for help in choosing the best items to support your board s application Accessories for the DIO24 include the TB50 terminal board and XB50 prototype terminal board for prototype development and easy signal access the XO50 cable assembly for direct connection to opto 22 systems and the TW50 twisted pair wire flat ribbon cable assembly for external interfacing Using This Manual This manual is intended to help you install your new board and get it running quickly while also providing enough detail about the board and its functions so that you can enjoy maximum use of its features even in the most complex applications We assume that you already have an understanding of data acquisition principles and that you can customize the example software or write your own applications programs When You Need Help This manual and the example programs in the software package included with your board provide enough information to properly use all of the board s features If you have any problems installing or using this board contact our Technical Support Department 814 234 8087 during regular busin
9. O PotB DatBus _t fo ol 1 o Portc Datagus ENCA Control Word Data Bus Output Operation Write Lolo ilo o oaamus Pora of a o o DataBus Pons o o DataBus Ponc pt ts To o DataBus Conte Disable Function EX x x x dataBus 3 state EX x i 1 o Ges e 3 Se PORT C PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B j O PORT C PINS 0 3 Lower nibble of Port C I O PORT B PINS 0 7 An 8 bit data output latch buffer and an 8 bit data input buffer SYSTEM POWER 5V Power Supply 1 O DATA BUS Bi directional tri state data bus lines connected to system data bus RESET A high on this input clears the control register and all Ports are set to the input mode WRITE CONTROL This input is low during CPU write Operations O PORT A PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input latch 3 125 m 11 13 15 1 0 UU O N 1 gt O O e ar _ N 8 Ka 8 ES N er i N BN m D u 37 40 O gt T A 1 12 23 34 z k intel
10. PERIPHERAL BUS 231256 20 Figure 15 MODE 2 Bidirectional NOTE Any sequence where WR occurs before ACK and STB occurs before RD is permissible INTR IBF lt MASK e STB RD OBF e MASK e ACK e WR Bag Mna nn s e 3 137 Mode Definition Summary Special Mode Combination Considerations There are several combinations of modes possible For any combination some or all of the Port C lines are used for control or status The remaining bits are either inputs or outputs as defined by a Set Mode command During a read of Port C the state of all the Port C lines except the ACK and STB lines will be piaced on the data bus In place of the ACK and STB line States flag status will appear on the data bus in the PC2 PC4 and PC6 bit positions as illustrated by Figure 18 Through a Write Port C command only the Port C pins programmed as outputs in a Mode O group can be written No other pins can be affected by a Write Port C command nor can the interrupt enable flags be accessed To write to any Port C output pro grammed as an output in a Mode 1 group or to 82C55A GROUP A ONLY mnb MODE 0 OR MODE 1 ONLY change an interrupt enable flag the Set Reset Port C Bit command must be used With a Set Reset Port C Bit command any Port C line pogammed as an output including INTR IBF and OBF can be written or an interrupt enable fiag can be either set or
11. commands from the Read Write Control Logic receives control words from the internal data bus and issues the proper commands to its as sociated ports Control Group A Port A and Port C upper C7 C4 Control Group B Port B and Port C lower C3 CO The control word register can be both written and read as shown in the address decode table in the pin descriptions Figure 6 shows the control word format for both Read and Write operations When the contro word is read bit D7 will always be a logic 4 as this implies control word mode information Ports A B and C The 82C55A contains three 8 bit ports A B and C All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 82C55A Port A One 8 bit data output latch buffer and one 8 bit input latch buffer Both pull up and pull down bus hold devices are present on Port A Port B One 8 bit data input output latch buffer Only pull up bus hold devices are present on Port B Port C One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B Only pull up
12. Control Word is written to a Counter all Control Logic is immediately reset and OUT goes to a known initial state no CLK pulses are required for this GATE The GATE input is always sampled on the rising edge of CLK In Modes 0 2 3 and 4 the GATE input is level sensitive and the logic level is sampled on the rising edge of CLK in Modes 1 2 3 and 5 the GATE input is rising edge sensitive In these Modes a rising edge of GATE trigger sets an edge sensi tive flip flop in the Counter This flip flop is then sam pled on the next rising edge of CLK the flip flop is reset immediately after it is sampled In this way a trigger will be detected no matter when it occurs a high logic level does not have to be maintained until the next rising edge of CLK Note that in Modes 2 and 3 the GATE input is both edge and level sensi tive In Modes 2 and 3 if a CLK source other than the system clock is used GATE should be pulsed immediately following WR of a new count value COUNTER New counts are loaded and Counters are decre mented on the falling edge of CLK The largest possible initial count is 0 this is equiva lent to 216 for binary counting and 104 for BCD counting The Counter does not stop when it reaches zero In Modes 0 1 4 and 5 the Counter wraps around to the highest count either FFFF hex for binary count ing or 9999 for BCD counting and continues count ing Modes 2 and 3 are periodic the Counter relo
13. Count flag of the selected coun ter s The command is written into the Control Word Reg ister and has the format shown in Figure 10 The command applies to the counters selected by set ting their corresponding bits D3 D2 D1 1 D De Ds D4 Ds D2 D Do COUNT STATUS cT 2 cr oer o o Ds 0 Latch count of selected counter s Da 0 Latch status of selected counter s Da 1 Select counter 2 Do 1 Select counter 1 D4 1 Select counter 0 Do Reserved for future expansion must be 0 Figure 10 Read Back Command Format The read back command may be used to latch multi ple counter output latches OL by setting the COUNT bit D5 0 and selecting the desired coun ter s This single command is functionally equiva lent to several counter latch commands one for each counter latched Each counter s latched count is held until it is read or the counter is repro grammed That counter is automatically unlatched when read but other counters remain latched until they are read If multiple count read back commands are issued to the same counter without reading the 82054 count all but the first are ignored i e the count which will be read is the count at the time the first read back command was issued The read back command may also be used to latch status information of selected counter s by setting STATUS bit D4 0 Status must be latched to be read status of a counter is accessed by a
14. Resistors on Digital YO Lines 1 8 CHAPTER 2 BOARD INSTALLATION 2 1 Board MASA u ne au Sa s Qa 2 3 External T O Connections m SS 2 4 Connecting the Digital MO eee e enses a aan 24 Connecting the Timer Counter I O annen annenenenvenenensensnsenenenserenasnsnensnenvesnensnunversonsnvevevevonn vaissen 24 Connecting the External A ii 2 4 Running the 24DIAG Diagnostics Program nn l u 2 4 CHAPTER 3 HARDWARE DESCRIPTION t Siga 3 1 Digital I O 8255 Programmable Peripheral Interface 3 3 Te EE 3 4 UO TN 3 4 CHAPTER 4 BOARD OPERATION AND PROGRAMMING 4 1 Defining the 1 O E 4 3 BA 0 PPI Port A Digital I O Read Write Y 4 3 BA 1 PPI Port B Digital YO Read Write E 4 3 BA 2 PPI Port C Digital YO Read Write non 4 3 BA 3 8254 PPI Control Word Write Only P 4 4 BA 4 IRQ Enable Write Only
15. goes here Do not use any DOS functions outportb BaseAddress 5 0 Clear DIO24 interrupt outportb 0x20 0x20 Send EOI command to 8259 In Pascal Procedure ISR Interrupt begin Your code goes here Do not use any DOS functions Port BaseAddress 5 0 Clear DIO24 interrupt Port 20 20 Send EOI command to 8259 end Saving the Startup Interrupt Mask Register IMR and Interrupt Vector The next step after writing the ISR is to save the startup state of the interrupt mask register and the interrupt vector that you will be using The IMR is located at I O port 21H The interrupt vector you will be using is located in the interrupt vector table which is simply an array of 256 bit 4 byte pointers and is located in the first 1024 bytes of memory Segment 0 Offset 0 You can read this value directly but it is a better practice to use DOS function 35H get interrupt vector Most C and Pascal compilers provide a library routine for reading the value of a vector The vectors for the hardware interrupts are vectors 8 through 15 where IRQO uses vector 8 IRQ1 uses vector 9 and so on Thus if the DIO24 will be using IRQ3 you should save the value of interrupt vector 11 Before you install your ISR temporarily mask out the IRQ you will be using This prevents the IRQ from requesting an interrupt while you are installing and initializing your ISR To mask the IRQ read in the current IMR at I O
16. of the board A more detailed discussion of board functions is included in Chapter 3 Hardware Operation and Chapter 4 Board Operation and Programming The board setup is described in Chapter 1 Board Settings Digital UO The DIO24 has 24 TTL CMOS compatible digital I O lines which can be directly interfaced with external devices or signals to sense switch closures trigger digital events or activate solid state relays These lines are provided by the on board 8255 programmable peripheral interface chip The 8255 can be operated in one of two modes Mode 0 or Mode 1 To ensure high driving capacity CMOS buffers are installed TTL buffers are available on request Pads for installing and activating pull up or pull down resistors are included on the board Installation proce dures are given at the end of Chapter 1 Board Settings 8254 Timer Counter DIO24 2 An 8254 programmable interval timer contains three 16 bit 8 MHz timer counters to support a wide range of timing and counting functions The clock gate and output pins for each of the timer counters are available at P6 a 20 pin on board box header connector What Comes With Your Board You receive the following items in your DIO24 package DIO24 1 or DIO24 2 with timer counters interface board Software and diagnostics diskette with Assembly BASIC Turbo Pascal and Turbo C source code e User s manual If any item is missing or damaged please call Real Time Devices
17. other bits You can preserve the status of all bits you do not wish to change by proper use of the AND and OR binary operators Using AND and OR single or multiple bits can be easily cleared in one operation To clear a single bit in a port AND the current value of the port with the value b where b 255 2 Clear bit 5 in a port Read in the current value of the port AND it with 223 223 255 2 and then write the resulting value to the port In BASIC this is programmed as V INP PortAddress V V AND 223 OUT PortAddress V To set a single bit in a port OR the current value of the port with the value b where b 2 Example Set bit 3 in a port Read in the current value of the port OR it with 8 8 23 and then write the resulting value to the port In Pascal this is programmed as V Port PortAddress V V OR 8 Port PortAddress V Setting or clearing more than one bit at a time is accomplished just as easily To clear multiple bits in a port AND the current value of the port with the value b where b 255 the sum of the values of the bits to be cleared Note that the bits do not have to be consecutive Example Clear bits 2 4 and 6 in a port Read in the current value of the port AND it with 171 171 255 2 2 2 and then write the resulting value to the port In C this is programmed as v inportb port_address v v 171 outportb port address v To set mu
18. the initial count and the process is repeated This sequence continues indefinitely Mode 3 Square Wave Mode Similar to Mode 2 except for the duty cycle output this mode is typically used for baud rate generation The output is initially high and when the count decrements to one half its initial count the output goes low for the remainder of the count The timer counter reloads and the output goes high again This process repeats indefinitely Mode 4 Software Triggered Strobe The output is initially high When the initial count expires the output goes low for one clock pulse and then goes high again Counting is triggered by writing the initial count Mode 5 Hardware Triggered Strobe Retriggerable The output is initially high Counting is triggered by the rising edge of the gate input When the initial count has expired the output goes low for one clock pulse and then goes high again 4 10 Interrupts What Is an Interrupt An interrupt is an event that causes the processor in your computer to temporarily halt its current process and execute another routine Upon completion of the new routine control is returned to the original routine at the point where its execution was interrupted Interrupts are very handy for dealing with asynchronous events events that occur at less than regular intervals Keyboard activity is a good example your computer cannot predict when you might press a key and it would be a wast
19. 00 5 Fig 1 1 Board Layout Showing Factory Configured Settings 1 3 P3 Interrupt and Interrupt Channels Factory Setting GND Connected Interrupt Channels Disabled This header connector shown in Figure 1 2 lets you connect an interrupt source selected on P4 to an interrupt channel IRQ2 through IRQ7 To connect the interrupt source to an interrupt channel you must install a jumper across the desired IRQ channel e e sg o on o x P3 Fig 1 2 Interrupt and Interrupt Channel Jumper P3 The rightmost pair of pins on P3 labeled G are provided so that you can install a jumper which connects a 1 kilohm pull down resistor to the output of a high impedance tri state driver which carries the interrupt request signal This pull down resistor drives the interrupt request line low whenever interrupts are not active So whenever an interrupt request is made the tri state buffer is enabled forcing the output high and causing an interrupt You can monitor the interrupt status through bit 0 in the status word I O address location BA 5 After the interrupt has been serviced the clear command returns the IRQ line low disabling the tri state buffers and pulling the output low again Figure 1 3 shows this circuit Because the interrupt request line is driven low only by the pull down resistor you can have two or more boards which share the same IRQ channel You can tell which board issued the interrupt reque
20. 000600 o lojo lo lo o RS vr Pe ka o o lol o o lol beus AN7 ol SIS gt H E o lojo lo lo EXTCLKt O B o of o o oo o o o9 o o lolo o o 00000000 o GOL Joo amea SS be Bana 0000000000 G o o o lo 3 lo lo felel lol 5060600000 9 ai 8 lo lololx o jo ore SI B klei lo le 74LS244 D PAL ao eer O e E el Jo lol o 9 000000000 0000000000 0600000000 3 0550055555 Made n UGA cu SE Copyright C 1993 Real Time Devices Inc State Coliege PA 16804 USA gen I mad PORT A PAO 7 Fig 1 10 Adding Pull ups and Pull downs to Some Digital I O Lines 1 9 1 10 CHAPTER 2 BOARD INSTALLATION The DIO24 is easy to install in your IBM PC XT AT It can be placed in any slot short or full size This chapter tells you step by step how to install and connect the board After you have installed the board and made all of your con nections you can turn your system on and run the 24DIAG board diagnostics program included on your example software disk to verify that your board is working Board Installation Keep the board in its antistatic bag until you are ready to install it in your computer When removing it from the bag hold the board at the edges and do not touch the components or connectors Before installing the board in your computer check the jumper settings Chapte
21. 141 82C55A CAPACITANCE Ta 25 C Voc GND ON nen fc 1 MHz NOTE 5 Sampled not 100 tested A C CHARACTERISTICS Ta 0 to 70 C Voc 5V 21096 GND OV Ta 40 C to 85 C for Extended Temperature BUS PARAMETERS READ CYCLE fort e L E ws EEL o w taa Maares Hold Time anerRDT o v m Bn ml vw 1 eo DwaDywemRD ml v we RD Daran ol m m my Recovery Time between DAR mo m trv omeen ww Gets RR TH o lad Address Hold Time After WR T 1 20 ms PotsA amp B 20 n Porc ww WRPusewan 100 m Hoo tow Data soup we e E E so ns Ponc WRITE CYCLE 3 142 intel 82C55A OTHER TIMINGS ms T Conditions Test Parameter WR 1 to Output Peripheral Data Before R D al pi Peripheral Data After ACK Pulse Width STB Pulse Width Per Data Before STB High Per Data After STBHigh AD ACK 0 to Output AK T a o o ed _ N m sto AGK 1 to Output Float 250 wo WH 1to0BF 0 150 RCM ACK 0 to OBF 1 E d o s o te STB oto BF 1 5 s te AD 1 to BF 0 o so n RD 0to INTR 0 Eo ao _ SIR lt en m nm o ACK 1toInTR 1 s m WR Oto INTR 0 20 n seenote1 tres ResetPusewan so ns sente
22. 8254 Timer Counter 1 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded BA 10 8254 Timer Counter 2 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded BA 11 8254 Control Word Write Only Accesses the 8254 control register to directly control the three timer counters BCD Binary O binary 1 BCD Counter Select 00 Counter 0 Counter Mode Select 01 Counter 1 000 Mode 0 event count 10 Counter 2 Read Load 001 Mode 1 programmable 1 shot 11 read back setting 00 latching operation x10 Mode 2 rate generator 01 read load LSB only x11 Mode 3 square wave rate generator 10 read load MSB only 100 Mode 4 software triggered strobe 11 read load LSB then MSB 101 Mode 5 hardware triggered strobe Programming the DIO24 This section gives you some general information about programming and the DIO24 board and then walks you through the major DIO24 programming functions These descriptions will help you as you use the example pro grams included with the board All of the program descriptions in this section use decimal values unless otherwise specified The DIO24 is programmed by writing to and reading from the correct I O port locations on the board These I O ports were defined in the previous sec
23. C54 Counters are programmed by writing a Control Word and then an initial count The control word format is shown in Figure 7 All Control Words are written into the Control Word Register which is selected when Ay Ag 11 The Control Word itself specifies which Counter is being programmed By contrast initial counts are written into the Coun ters not the Control Word Register The Ay Ao in puts are used to select the Counter to be written into The format of the initial count is determined by the Control Word used D3 D2 Dj ser oo ewe awo we wt ve seo SC Select Counter SCH SCO o o SelectCountero o 1 SelectCounter 1 O SelectCounter2 1 Read Back Command I See Read Operations RW Read Write RW1 RWO Counter Latch Command see Read Operations KIP o area en Read Write least significant byte only 0 Read Write most Read Write most significant byte only byte only Read Write least significant byte first then most significant byte NOTE Don t care bits X should be 0 to insure compatibility with future Intel products Binary Counter 16 bits 1 Binary Coded Decimal BCD Counter 4 Decades Figure 7 Control Word Format 3 87 intel 82054 Write Operations The programming procedure for the 82C54 is very flexible Only two conventions need to be remem bered 1 For each Counter the Control Word must be written before the initial count
24. D D D De CONTROL WORD 5 D D D D Dj D D CONTROL WORD 6 D D Ds D D O D D CONTROL WORD 7 D D D D D De D D 3 132 CONTROL WORD 8 De D D 0 D De CONTROL WORD 9 D De D De D D 0 Do CONTROL WORD 10 D O D D 0 D D Do CONTROL WORD 11 O Ds Ds D D D D Do PCy PC PCy PCy rae 231256 11 intel 82C55A MODE 0 Configurations Continued CONTROL WORD 12 CONTROL WORD 14 D D O amp D D D Do D De Dy O D D O D CONTROL WORD 913 CONTROL WORD 15 D Os Ds D D D D D D De Ds D 0 D D D 231256 12 M ional initions Operating Modes ode 1 Basic functional Definitions e Two Groups Group A and Group B MODE 1 Strobed Input Output This functional e Each group contains one 8 bit data port and one configuration provides a means for transferring LO 4 bit control data port data to or from a specified port in conjunction with The 8 bit data be either i strobes or handshaking signals In mode 1 Port A bit data port can be either input or output and Port B use the lines on Port C to generate or Both inputs and outputs are latched accept these handshaking signals e The 4 bit port is used for control and status of the 8 bit data port otra T eism pe R ann eae 3 133 intel 82C55A Input Control Signal Definition iios REN STB Strobe Input A low on this input loads data into the input latch C
25. DE 0 each group of 12 i O pins may be programmed in sets of 4 and 8 to be inputs or outputs In MODE 1 each group may be programmed to have 8 lines of input or output 3 of the remaining 4 pins are used for handshaking and interrupt control signals MODE 2 is a strobed bi directional bus configuration The 82C55A is fabricated on Intel s advanced CHMOS Ill technology which provides low power consumption with performance equal to or greater than the equivalent NMOS product The 82C55A is available in 40 pin DIP and 44 pin plastic leaded chip carrier PLCC packages BDE C TIONAL DATA BUS 231256 1 Figure 1 82C55A Block Diagram 231256 2 Figure 2 82C55A Pinout Diagrams are for pin reference only Package sizes are not to scale September 1987 3 124 Order Number 231256 004 intel 82C55A Table 1 Pin Description Pin Number Symbol Dip pLcc Type Name and Function O PORT A PINS 0 3 Lower nibble of an 8 bit data output latch buffer and an 8 bit data input latch READ CONTROL This input is low during CPU read operations CHIP SELECT A low on this input enables the 82C55A to respond to RD and WR signals RD and WR are ignored otherwise I ADDRESS These input signals in conjunction RD and WR control the selection of one of the three ports or the control word registers Ay Ao RD WR CS input Operation Read O0 PortA DataBus _1
26. FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITA TIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EXCLU SIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE DIO24 Board User Selected Settings Base UO Address
27. IGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND DIGITAL GND PC1 PC3 Pcs PC7 EXT CLK 0 T C OUT 0 EXT GATE 1 EXT CLK 2 T C OUT 2 DIGITAL GND B 4 APPENDIX C COMPONENT DATA SHEETS C 1 Intel 82C55A Programmable Peripheral Interface Data Sheet Reprint intel 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE m Compatible with all Intel and Most a Control Word Read Back Capability Other Microprocessors m Direct Bit Set Reset Capability m High Speed Zero Wait State Operation with 8 MHz 8086 88 and m 2 5 mA DC Drive Capability on all 1 0 80186 188 Port Outputs m 24 Programmable 1 0 Pins m Available in 40 Pin DIP and 44 Pin PLCC B Available in EXPRESS m Low Power CHMOS Standard Temperature Range m Completely TTL Compatible Extended Temperature Range The Intel 82C55A is a high performance CHMOS version of the industry standard 8255A general purpose programmable I O device which is designed for use with all Intel and most other microprocessors It provides 24 O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation The 82C55A is pin compatible with the NMOS 8255A and 8255A 5 In MO
28. IO24 board attempts to use I O address locations already used by another device contention results and the board does not work To avoid this problem the DIO24 has an easily accessible DIP switch S1 which lets you select any one of 32 starting addresses in the computer s I O Should the factory setting of 300 hex 768 decimal be unsuitable for your system you can select a different base address simply by setting the switches to any value shown in Table 1 2 The table shows the switch settings and their corresponding decimal and hexadecimal in parentheses values Make sure that you verify the order of the switch numbers on the switch 1 through 5 before setting them When the switches are pulled forward they are OPEN or set to logic 1 as labeled on the DIP switch package When you set the base address for your board record the value in the table inside the back cover Figure 1 7 shows the DIP switch set for a base address of 300 hex 768 decimal Fig 1 7 Base Address Switch S1 Base Address Switch Setting Decimal Hex 4321 Decimal Hex 4321 512 200 10000 528 210 10001 54 02 10010 560 230 10011 SE 10100 592 250 10101 624 270 9133 SE 11000 656 290 11001 11011 11100 DE TETE 736 2E0 11110 752 F0 TENE 0 closed 1 open S2 Buffer Bypass Switch Factory Setting OPEN Not Bypassed When operating the 8255 in Mode 1 the lines of Port C functi
29. ONTROL WORD D D D O D 0 D De EDUC Par 1 INPUT IBF Input Buffer Full F F A high on this output indicates that the data has been loaded into the input latch in essence an ac knowledgement IBF is set by STB input being low and is reset by the rising edge of the RD input INTR Interrupt Request MODE 1 PORT 8 A high on this output can be used to interrupt the EES CPU when an input device is requesting service INTR is set by the STB is a one IBF is a one and INTE is a one It is reset by the falling edge of PS a RD This procedure allows an input device to re quest service from the CPU by simply strobing its data into the port INTE A Controlled by bit set reset of PC4 INTE B 231256 13 Controlled by bit set reset of PC Figure 8 MODE 1 Input 231256 14 Figure 9 MODE 1 Strobed input 3 134 intel 82C55A Output Control Signal Definition OBF Output Buffer Full F F The OBF output will go low to indicate that the CPU has written data out to the specified port The OBF F F will be set b the rising edge of the WR input and reset by ACE Input being low ACK Acknowledge Input A low on this input informs the 82C55A that the data from Port A or Port B has been accepted In essence a response from the peripheral device indicating that it has received the data output by the CPU INTR interrupt Request A high on this o
30. above DON T Addition and subtraction may seem logical but they will not work if you try to clear a bit that is already clear or set a bit that is already set For example you might think that to set bit 5 of a port you simply need to read in the port add 32 2 to that value and then write the resulting value back to the port This works fine if bit 5 is not already set But what happens when bit 5 is already set Bits 0 to 4 will be unaffected and we can t say for sure what happens to bits 6 and 7 but we can say for sure that bit 5 ends up cleared instead of being set A similar problem happens when you use subtraction to clear a bit in place of the method shown above Now that you know how to clear and set bits we are ready to look at the programming steps for the DIO24 board functions Initializing the 8255 PPI Before you can operate the DIO24 the 8255 must be initialized This step must be executed every time you start up reset or reboot your computer The 8255 is initialized by writing the appropriate control word to I O port BA 3 The contents of your control word will vary depending on how you want to configure your I O lines Use the control word description in the previous I O map section to help you program the right value Remember that the DIO24 cannot use Mode 2 In the example below a decimal value of 128 sets up the 8255 so that all I O lines are Mode 0 outputs 1 0 0 0 0 0 0 0 7 os os pa os o2 pt n
31. ads itself with the initial count and continues counting from there intel 82054 ABSOLUTE MAXIMUM RATINGS Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam Ambient Temperature Under Bias 0 C to 70 C age to the device This is a stress rating only and Storage Temperature 65 to 150 C functional operation of the device at these or any Supply Voltage 0 5to 8 0V other conditions above those indicated in the opera Operating Voltage 4Vto 7V tional sections of this specification is not implied Ex Voltage on any Input GND 2Vto 6 5V posure to absolute maximum rating conditions for Voltage on any Output GND 0 5V to Voc 0 5V extended periods may affect device reliability Power Dissipation 1 Watt D C CHARACTERISTICS TA 0 C to 70 C Vec 5V 10 GND 0V TA 40 C to 85 C for Extended Temperature Symbo Parameter Mn Max Units TestConditions Vi mputtowvoltage 05 os Pv Dou input HighVottage 20 vecros V 3 vor Outputtowvotage 04 V jig 725m Vu Vin VoL V VoH Output High Voltage 3 0 V loH 25mA Voc 0 4 V lon 100 H Input Load Current BEER Output Float Leakage Current 10 pA Vour Vocto0 0V Voc Supply Current mA E 8MHz 82054 IccsB Voc Supply Curre
32. aning you may have to avoid floating point real math in your ISR Note that the problem of reentrancy exists no matter what programming language you are using Even if you are writing your ISR in assembly language DOS and many floating point emulators are not reentrant Of course there are ways around this problem such as those which involve checking to see if any DOS functions are currently active when your ISR is called but such solutions are well beyond the scope of this discussion The second major concern when writing your ISR is to make it as short as possible in terms of execution time Spending long periods of time in your ISR may mean that other important interrupts are being ignored Also if you 4 12 spend t00 long in your ISR it may be called again before you have completed handling the first run This often leads to a hang that requires a reboot Your ISR should have this structure Push any processor registers used in your ISR Most C and Pascal interrupt routines automatically do this for you Put the body of your routine here Clear the interrupt bit on the DIO24 by writing any value to BA 5 Issue the EOI command to the 8259 interrupt controller by writing 20H to port 20H Pop all registers pushed on entrance Most C and Pascal interrupt routines automatically do this for you The following C and Pascal examples show what the shell of your ISR should be like In C void interrupt ISR void Your code
33. any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAM AGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by REAL TIME DEVICES acts of God or other contingencies beyond the control of REAL TIME DEVICES OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN REAL TIME DEVICES EXCEPT AS EX PRESSLY SET FORTH ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND REAL TIME DEVICES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL REAL TIME DEVICES BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAM AGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSE QUENTIAL DAMAGES
34. are used by the standard system resources IRQO is used by the system timer IRQ is used by the key board IRQ3 by COM2 IRQ4 by COMI and IRQ6 by the disk drives Therefore it is important for you to know which IRQ lines are available in your system for use by the DIO24 board 8259 Programmable Interrupt Controller The chip responsible for handling interrupt requests in the PC is the 8259 Programmable Interrupt Controller To use interrupts you will need to know how to read and set the 8259 s interrupt mask register MR and how to send the end of interrupt EOI command to the 8259 Interrupt Mask Register IMR Each bit in the interrupt mask register IMR contains the mask status of an IRQ line bit 0 is for IRQO bit 1 is for IRQ1 and so on If a bit is set equal to 1 then the corresponding IRQ is masked and it will not generate an interrupt If a bit is clear equal to 0 then the corresponding IRQ is unmasked and can generate interrupts The IMR is programmed through port 21H per mos ios mas nas ma mor mao voorz For all bits 0 IRQ unmasked enabled 1 IRQ masked disabled End of Interrupt EOI Command After an interrupt service routine is complete the 8259 interrupt controller must be notified This is done by writing the value 20H to I O port 20H What Exactly Happens When an Interrupt Occurs Understanding the sequence of events when an interrupt is triggered is necessary to properly w
35. bus hold devices are present on Port C See Figure 4 for the bus hold circuit configuration for Port A B and C 3 126 intel 82C55A BIDIRECTIONAL DATA BUS INTERNAL DATA NOTE 231256 4 Port pins loaded with more than 20 pF capacitance may not have their logic level guaranteed following a hardware reset Figure 4 Port A B C Bus hoid Configuration 3 127 intel 82C55A 82C55A OPERATIONAL DESCRIPTION CONTROL WORD Mode Selection BEBBEBSBE There are three basic modes of operation that can be selected by the system software Mode 0 Basic input output Mode 1 Strobed Input output GROUP 8 Mode 2 Bi directional Bus PORT C LOWER 1 INPUT When the reset input goes high all ports will be set to the input mode with all 24 port lines held at a logic one level by the internal bus hold devices see Figure 4 Note After the reset is removed the f 82C55A can remain in the input mode with no addi MODE SELECTION tional initialization required This eliminates the need ee for pullup or pulldown devices in all CMOS de signs During the execution of the system program any of the other modes may be selected by using a single output instruction This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine 1 1 0 OUTPUT The modes for Port A and Port B can be separately defined while Port C is d
36. d most m Three independent 16 bit counters other microprocessors m Low Power CHMOS m High Speed Zero Wait State cc 10 mA 8 MHz Count Operation with 8 MHz 8086 88 and frequency 80186 188 m Completely TTL Compatible m Handles Inputs from DC to 8 MHz 10 MHz for 82C54 2 E ks pg Modes m Available in EXPRESS REC Standard Temperature Range m Status Read Back Command Extended Temperature Range m Available in 24 Pin DIP and 28 Pin PLCC The Intel 82054 is a high performance CHMOS version of the industry standard 8254 counter timer which is designed to solve the timing control problems common in microcomputer system design It provides three independent 16 bit counters each capable of handling clock inputs up to 10 MHz All modes are software programmable The 82C54 is pin compatible with the HMOS 8254 and is a superset of the 8253 Six programmable timer modes allow the 82C54 to be used as an event counter elapsed time indicator programmable one shot and in many other applications The 82C54 is fabricated on Intel s advanced CHMOS III technology which provides low power consumption with performance equal to or greater than the equivalent HMOS product The 82C54 is available in 24 pin DIP and 28 pin plastic leaded chip carrier PLCC packages DATA SUFFER 231244 3 CLK 2 CONTROL WORD GATE 2 REGISTER DUT 2 231244 1 Figure 1 82C54 Block Diagram 231244 2 Diagrams are
37. dress contention when you first use your board in your system Table 1 1 Factory Settings Switch Jumper Function Controlled Connects 1 of 6 interrupt sources to an interrupt GND ground for buffer channel pulls tri state buffer to ground GND for connected interrupt channels P3 Factory Settings Jumpers Installed multiple interrupt applications disabled Selects the interrupt source EXT external interrupt Sets the clock sources for the three 8254 CLKO XTAL CLK1 OUTO CLK2 OUT1 all three P5 timer counters TCO TC2 timer counters are cascaded Sets the base address 300 hex 768 decimal Bypasses Port C buffers for Mode 1 operation Open buffers not bypassed 90000 7 000059 op 0000000 00000000 ADDRESS 00000 an OOOO 0000000 x 00000000 0000000 O24 assss G55559 1024 s 90009090000 009099 RN11 FO 3000000000000 A me eel 000000000000 Uto UO 22 2 s OGGG0G00m 95928 C DN 000000000000 og 000000000000 00000000008 SPELIHYL 0000000000 2 0000000000 7415244 0000000000 ug ce 0000000000 000000000000 00000000000 n0o00000 0000000000 00999909990 000000000 Made in USA C15 Copyright C93 Real Time Devices Inc State College PA 16804 Long Aa A 00000000 o n oD B Z lt e 00000000000000000000 GOO00000000000000000 E 0000000000 0000000000 8 St LOUP C13 uwa 900000000D 00000000
38. e 0 Basic input output Lets you use simple input and output operation for a port Data is written to or read from the specified port Mode 1 Strobed input output Lets you transfer I O data from Port A or Port B in conjunction with strobes or handshaking signals These modes are detailed in the 8255 Data Sheet reprinted from Intel in Appendix C The bidirectional buffers on the 8255 s I O lines monitor the 8255 control word to automatically set their direction Hardware changes to the buffer circuitry is required only when using Mode 1 where the Port C buffers must be removed as described in Chapter 1 3 3 Timer Counters An 8254 programmable interval timer provides three 16 bit 8 MHz timer counters to support a wide range of timing and counting functions These timer counters can be cascaded or used individually for many applications Each timer counter has two inputs CLK in and GATE in and one output timer counter OUT The clock sources for the timer counters can be selected using jumpers on header connector P5 see Chapter 1 The timer counters can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in Chapter 4 The command word also lets you set up the mode of operation The six programmable modes are Mode 0 Event Counter Interrupt on Terminal Count Mode 1 Hardware Retriggerable One Shot Mode 2 Rate Generator Mode 3 Square Wave Mode Mode 4 Softwar
39. e Triggered Strobe Mode 5 Hardware Triggered Strobe Retriggerable These modes are detailed in the 8254 Data Sheet reprinted from Intel in Appendix C Interrupts The DIO24 can use any one of six signal sources to generate interrupts These sources are OTO OT1 and OT2 which are the three 8254 timer counter outputs available on the DIO24 2 model PC3 which is the INTRA signal from the 8255 PPI PCO which is the INTRB signal from the 8255 PPI and EXT an external interrupt you can route onto the board through the P2 I O connector Chapter 1 tells you how to set the jumpers on interrupt header connectors P3 and P4 and Chapter 4 provides some programming information 3 4 CHAPTER 4 BOARD OPERATION AND PROGRAMMING This chapter shows you how to program and use your DIO24 board It provides a complete description of the I O map and a detailed description of programming operations to aid you in programming The example programs included on the disk in your board package are listed at the end of this chapter These programs written in Turbo C Turbo Pascal Assembly and BASIC include source code to simplify your applications programming 4 1 Defining the UO Map The UO map for the DIO24 is shown in Table 4 1 below As shown the board occupies 12 consecutive I O port locations The base address designated as BA can be selected using DIP switch S1 as described in Chapter 1 Board Settings This switch can be acce
40. e of processor time for it to do nothing while waiting for a keystroke to occur Thus the interrupt scheme is used and the processor proceeds with other tasks Then when a keystroke does occur the keyboard interrupts the processor and the processor gets the keyboard data places it in memory and then returns to what it was doing before it was interrupted Other common devices that use interrupts are modems disk drives and mice Your DIO24 board can interrupt the processor when one of the six interrupt sources is enabled By using these interrupts you can write software that effectively deals with real world events Interrupt Request Lines To allow different peripheral devices to generate interrupts on the same computer the PC bus has eight different interrupt request IRQ lines A transition from low to high on one of these lines generates an interrupt request which is handled by the PC s interrupt controller The interrupt controller checks to see if interrupts are to be acknowledged from that IRQ and if another interrupt is already in progress it decides if the new request should supersede the one in progress or if it has to wait until the one in progress is done This prioritizing allows an interrupt to be interrupted if the second request has a higher priority The priority level is based on the number of the IRQ IRQO has the highest priority IRQ1 is second highest and so on through IRQ7 which has the lowest Many of the IRQs
41. ed General Some of the other counter timer functions common The 82C54 is a programmable interval timer counter to microcomputers which can be implemented with designed for use with Intel microcomputer systems the 82054 are It is a general purpose multi timing element that can be treated as an array of I O ports in the system software Real time clock Even counter Digital one shot Programmable rate generator Square wave generator Binary rate multiplier Complex waveform generator Complex motor controller The 82C54 solves one of the most common prob lems in any microcomputer system the generation of accurate time delays under software control In stead of setting up timing loops in software the pro grammer configures the 82054 to match his require ments and programs one of the counters for the de 3 84 82C54 Block Diagram DATA BUS BUFFER This 3 state bi directional 8 bit buffer is used to in terface the 82C54 to the system bus see Figure 3 COUNTER 0 E e gt s e lt z x z 231244 4 Figure 3 Block Diagram Showing Data Bus Buffer and Read Write Logic Functions READ WRITE LOGIC The Read Write Logic accepts inputs from the sys tem bus and generates control signals for the other functional blocks of the 82C54 A4 and Ao select one of the three counters or the Control Word Regis ter to be read from written into A low on the R input tells the 82C54 that
42. ess hours eastern standard time or eastern daylight time or send a FAX requesting assistance to 814 234 5218 When sending a FAX request please include your company s name and address your name your telephone number and a brief description of the problem CHAPTER 1 BOARD SETTINGS The DIO24 board has jumper and switch settings you can change if necessary for your application The board is factory configured with the most often used settings The factory settings are listed and shown on a diagram in the beginning of this chapter Should you need to change these settings use these easy to follow instructions before you install the board in your computer Note that DIP switch S2 has been provided to bypass the Port C buffers and allow Mode 1 operation of the 8255 Also note that by installing resistor packs at three locations around the 8255 PPI and soldering jumpers in the desired locations in the associated pads you can configure your digital I O lines to be pulled up or pulled down This procedure is explained at the end of this chapter Factory Configured Switch and Jumper Settings Table 1 1 lists the factory settings of the user configurable jumper and switches on the DIO24 board Figure 1 1 shows the board layout and the locations of the factory set jumpers The following paragraphs explain how to change the factory settings Pay special attention to the setting of S1 the base address switch to avoid ad
43. f six modes depending on your application The following paragraphs briefly describe each mode 4 9 ON BOARD r au pm me pe e ma VO CONNECTOR P6 TIMER pi COUNTER 21 0 I I XTAL 8 MHz A EXT CLK 0 5v 29 PIN 11 EXT GATE 0 PIN 121 T C OUT O TIMER COUNTER 1 PIN 13 i I l l EXT CLK 1 PIN 144 EXT GATE 1 PIN 154 T C OUT 1 CLK2 O Q TIMER 1 COUNTER CLK O O s EXT CLK 2 2 LI TK 5 V GATE PIN 17 gt EXT GATE 2 OUT PIN 184 T C OUT 2 r 7 Fig 4 1 8254 Timer Counter Circuit Block Diagram Mode 0 Event Counter Interrupt on Terminal Count This mode is typically used for event counting While the timer counter counts down the output is low and when the count is complete it goes high The output stays high until a new Mode 0 control word is written to the timer counter Mode 1 Hardware Retriggerable One Shot The output is initially high and goes low on the clock pulse following a trigger to begin the one shot pulse The output remains low until the count reaches 0 and then goes high and remains high until the clock pulse after the next trigger Mode 2 Rate Generator This mode functions like a divide by N counter and is typically used to generate a real time clock interrupt The output is initially high and when the count decrements to 1 the output goes low for one clock pulse The output then goes high again the timer counter reloads
44. for pin reference only Package sizes are not to scale Figure 2 82C54 Pinout A AA September 1989 3 83 Order Number 231244 005 intel 82054 Table 1 Pin Description 1 0 Data Bidirectional tri state data bus lines connected to system data bus Ciock 0 Clock input of Counter 0 I Output 0 Output of Counter 0 BEE LO 1 Gate 0 Gate input of Counter __ Ground Power supply connection O Outt OutputofCountert SN NEUE Gate 1 Gate input of Counter 1 Clock 1 Clock input of Counter 1 Gate 2 Gate input of Counter 2 Out 2 Output of Counter 2 Clock 2 Clock input of Counter 2 Address Used to select one of the three Counters or the Control Word Register for read or write operations Normally connected to the system address bus Counter 0 Counter 1 Counter 2 Control Word Register cs 21 24 Chip Select A low on this input enables the 82054 to respond to RD and WR signals RD and WR are I ignored otherwise LEON Read Control This input is low during CPU read operations 27 Write Control This input is low during CPU write operations Veo 2 28 Power 5V power supply connection LN 1 151525 NoComeet No Connect sired delay After the desired delay the 82C54 will FUNCTIONAL DESCRIPTION interrupt the CPU Software overhead is minimal and variable length delays can easily be accommodat
45. g too much pressure can result in damage to the board or to the computer After the board is installed secure the slot bracket back into place and put the cover back on your computer The board is now ready to be connected via the external I O connector at the rear panel of your computer External I O Connections Figure 2 1 shows the DIO24 s P2 I O connector pinout and P6 on board I O connector pinout Refer to these diagrams as you make your I O connections DIGITAL GNO P2 DIGITAL GNO Poo QO ETINT eco OO Pc PC1 DIGITAL GND PC2 PC3 PC2 DIGITAL GND REN BO Pes PG DO DIGITAL GND Gee ex PCA 9609 DIGITAL GND pcs 5 5 DIGITAL ono DIGITAL GND S 9 EXT CLK o pcs G2G2 DIGITAL GND EXT GATE 0 Q Tc our o Pc 9 9 DIGITAL og EXT CLK 1 OA EXT GATE 1 Pao 05051 DIGITAL GND Tre OUT 1 O Ext c K 2 Par 109201 DIGITAL GND EXT GATE 2 2689 T c ouT2 og Ss hen DIGITAL GND 369 DIGITAL GND PBA amp amp DIGITAL GND pas G5 G8 DIGITAL oND f P6 pas 3 69 DIGITAL ano 20 pin on board I O connector PB7 DE DIGITAL GNO PAO BG DIGITAL GND PAI HE DIGITAL GND PA 83 DIGITAL GND PA3 BHB DIGITAL GND PAS 9 42 DIGITAL GND PAS EIG DIGITAL GND PAG Bf DIGITAL GNO e O 5 VOLTS 50 pin VO connector Fig 2 1 P2 and P6 I O Connector Pin Assignments Connecting the Digital UO The DIO24 is designed for direct connection to industry standard opto 22 isolated I O rack
46. he Counter is programmed In this way if the Counter has been programmed for one byte counts either most significant byte only or least significant byte only the other byte will be zero Note that the CE cannot be written into whenever a count is written it is written into the CR I The Control Logic is also shown in the diagram CLK n GATE n and OUT n are all connected to the out side world through the Control Logic 82C54 SYSTEM INTERFACE The 82C54 is treated by the systems software as an array of peripheral I O ports three are counters and the fourth is a control register for MODE program ming Basically the select inputs Ag A4 connect to the Ag Au address bus signals of the CPU The CS can be derived directly from the address bus using a linear select method Or it can be connected to the output of a decoder such as an Intel 8205 for larger sys tems A Ae TE De Dr KO WR g COUNTER COUNTER 1 gt see OUT GATE CLK OUT GATE CLK OUT GATE CLK COUNTER 2 231244 7 Figure 6 82C54 System Interface intel 82C54 OPERATIONAL DESCRIPTION General After power up the state of the 82C54 is undefined The Mode count value and output of all Counters are undefined How each Counter operates is determined when it is programmed Each Counter must be programmed before it can be used Unused counters need not be programmed Control Word Format A Ao 11 CS 0 PD R 0 D4 Programming the 82
47. hich was latched first The next one or two reads depending on whether the counter is programmed for one or two type counts return latched count Subsequent reads return un latched count Results Figure 13 Read Back Command Example 82C54 os Rb wn a a o ofofo writeintoCountero o o oo 4 wrteimocounter Lo o f1 0 write into Counter ofna 1 wete contri word Lolo Tele Read trom Counter o_ ol of 1 o read trom counter 1 o o 1 1 o Read trom Counter 2 Lo o 4 1 NoOperation 3 Stato Lo 1 1 x x no Operation 3 State Figure 14 Read Write Operations Summary Mode Definitions The following are defined for use in describing the operation of the 82054 CLK PULSE a rising edge then a falling edge in that order of a Counter s CLK input TRIGGER a rising edge of a Counter s GATE in put COUNTER LOADING the transfer of a count from the CR to the CE refer to the Functional Descrip tion MODE 0 INTERRUPT ON TERMINAL COUNT Mode 0 is typically used for event counting After the Control Word is written OUT is initially low and will remain low until the Counter reaches zero OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Coun ter GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After the Control Word and
48. ied port P i e 16 different Input Output configurations are pos sible in this Mode MODE 0 BASIC INPUT menen HN tao ee 231256 8 MODE 0 BASIC OUTPUT 231256 9 3 130 intel 82C55A MODE 0 Port Definition SEN GROUP B PORTC PORTC UPPER PORT B LOWER o D Q v gt D B Lo o o o oureut ourur o ourpur lo o o ourur output po o 1 o ourur OUTPUT 2 input ouor o o 1 1 ourur ourur s meur INPUT Lo o o ourur wur 4 output outor Lo 1 o oureur wur 5 ourur PUT 7 Lo 1 1 o ourur wur e input OUTPUT o 1 1 1 ourur wur 7 meur eur 1 o o o meur ouru 8 ourur outeur i o o wer ouru e ourvur L1 o 1 o pu ourur 1 input output pt o 1 1 meur ourur 11 INPUT weu pt o o weur meu 12 output OUTPUT i o 1 INPUT meur 13 output INPUT 1 c 1 o wer meur 14 input OUTPUT t 1 1 weu wer 45 INPUT INPUT MODE 0 Configurations CONTROL WORD 0 CONTROL WORD 42 D D Ds O O O D D D D Ds D D D D 0 CONTROL WORD 1 CONTROL WORD 3 D De D D D b D D D D D D 0 D D D pare 231256 10 3 131 82C55A MODE 0 Configurations Continued CONTROL WORD 4 D De D D
49. in the Figure when latched contains the current contents of the Control Word Register and status of the output and null count flag See detailed explanation of the Read Back command The actual counter is labelled CE for Counting Ele ment It is a 16 bit presettable synchronous down counter Olm and OL are two 8 bit latches OL stands for Output Latch the subscripts M and L stand for Most significant byte and Least significant byte respectively Both are normally referred to as one unit and called just OL These latches normally fol low the CE but if a suitable Counter Latch Com mand is sent to the 82C54 the latches latch the present count until read by the CPU and then return to following the CE One latch at a time is enabled by the counter s Control Logic to drive the internal bus This is how the 16 bit Counter communicates over the 8 bit internal bus Note that the CE itself cannot be read whenever you read the count it is the OL that is being read Similarly there are two 8 bit registers called CRm and CRI for Count Register Both are normally referred to as one unit and called just CR When a new count is written to the Counter the count is stored in the CR and later transferred to the CE The Control Logic allows one register at a time to be loaded from the internal bus Both bytes are trans ferred to the CE simultaneously CRy and CR are cleared when t
50. ing the on board 8 MHz oscillator the output of TCO providing the clock for TC1 and the output of TC1 providing the clock for TC2 You can connect any or all of the sources to an external clock input through the P6 on board I O connector or you can set TC1 and TC2 to be clocked by the 8 MHz oscillator Figure 1 6 shows a block diagram of the timer counter circuitry to help you with these connections NOTE When installing jumpers on this header make sure that only one jumper is installed in each group of two or three CLK pins P5 XTAL EXTCLKO OUTO XTAL EXTCLK1 OUT1 XTAL EXTCLK2 MID 031 Used with DIO24 2 model only r N Fig 1 5 8254 Timer Counter Clock Source Jumpers P5 ON BOARD v D VO CONNECTOR I P6 l XTAL 8 MHz I PIN 100 EXT CLK O v SY PIN 11 EXT GATE 0 TIMER COUNTER 0 PIN 12 L T C OUT O TIMER COUNTER 1 PIN 13 i I I I EXT CLK 1 PIN 14 EXT GATE 1 PIN 154 T C OUT 1 TIMER I COUNTER O Op ry s EXT CLK 2 2 emm 5 V PIN 17 L EXT GATE 2 PIN 18 L T C OUT 2 Fig 1 6 8254 Timer Counter Circuit Block Diagram S1 Base Address Factory Setting 300 hex 768 decimal One of the most common causes of failure when you are first trying your board is address contention Some of your computer s I O space is already occupied by internal I O and other peripherals When the D
51. initial count are written to a Counter the initial count will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not go high until N 1 CLK pulses after the initial count is written If a new count is written to the Counter it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens 1 Writing the first byte disables counting OUT is set low immediately no clock pulse required 2 Writing the second byte allows the new count to be loaded on the next CLK pulse 3 91 This allows the counting sequence to be synchroniz ed by software Again OUT does not go high until N 1 CLK pulses after the new count of N is written If an initial count is written while GATE 0 it will still be loaded on the next CLK pulse When GATE goes high OUT will go high N CLK pulses later no CLK pulse is needed to load the Counter as this has already been done CW 10 15804 LR Sns es ee E CWa10 L 825 lee SU GATE ee gle sim 231244 8 NOTE The Following Conventions Apply To All Mode Timing Diagrams 1 Counters are programmed for binary not BCD counting and for Reading Writing least significant byte LSB only 2 The counter is always selected CS always low 3 CW stands for Control Word CW 10 means a control word of 10 he
52. is written 2 The initial count must follow the count format specified in the Control Word least significant byte only most significant byte only or least sig nificant byte and then most significant byte Since the Control Word Register and the three Counters have separate addresses selected by the Au Ag inputs and each Control Word specifies the Counter it applies to SCO SC1 bits no special in _ Counter 0 Counter 0 Counter 0 Counter 1 Counter 1 Counter 1 Counter 2 Counter 2 Counter 2 Control Word LSB of count MSB of count Control Word LSB of count MSB of count Control Word LSB of count MSB of count 44200 A E OH D oo 2009 Control Word Counter Word Control Word LSB of count LSB of count LSB of count MSB of count MSB of count MSB of count Counter 0 Counter 1 Counter 2 Counter 2 Counter 1 Counter 0 Counter 0 Counter 1 Counter 2 0000 a A ua P o 00 0 P NOTE struction sequence is required Any programming sequence that follows the conventions above is ac ceptable i A new initia count may be written to a Counter at any time without affecting the Counters pro grammed Mode in any way Counting will be affected as described in the Mode definitions The new count must follow the programmed count format If a Counter is programmed to read write two byte counts the following precaution applies A prog
53. its count until it is read Counter Latch Commands do not affect the programmed Mode of the Counter in any way If a Counter is latched and then some time later latched again before the count is read the second Counter Latch Command is ignored The count read will be the count at the time the first Counter Latch Command was issued With either method the count must be read accord ing to the programmed format specifically if the Counter is programmed for two byte counts two bytes must be read The two bytes do not have to be read one right after the other read or write or pro 3 89 gramming operations of other Counters may be in serted between them Another feature of the 82C54 is that reads and writes of the same Counter may be interleaved for example if the Counter is programmed for two byte counts the following sequence is valid 1 Read least significant byte 2 Write new least significant byte 3 Read most significant byte 4 Write new most significant byte If a Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between reading the first and second byte to another routine which also reads from that same Counter Otherwise an incorrect count will be read READ BACK COMMAND The third method uses the Read Back command This command allows the user to check the count value programmed Mode and current state of the OUT pin and Null
54. ivided into two portions as required by the Port A and Port B definitions All of the output registers including the status flip flops oe will be reset whenever the mode is changed Modes MIA E may be combined so that their functional definition can be tailored to almost any I O structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display computa tional results Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an 231256 6 interrupt driven basis Figure 6 Mode Definition Format The mode definitions and possible mode combina tions may seem confusing at first but after a cursory review of the complete device operation a simple logical I O approach will surface The design of the 82C55A has taken into account things such as effi cient PC board layout control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic jolie jede jede jede Such design represents the maximum use of the vet PP POPC PAPA available pins B A o o Single Bit Set Reset Feature Mo ST Quo reine Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction This feature re gt duces software requirements in Control based appli vo BI DIRECTIONAL cations hh o tag Te 231256 5 When Port C is being used as status control for Port A or B these bits can be set or reset by usi
55. le functions are also available MODE 2 Basic Functional Definitions e Used in Group A only e One 8 bit bi directional bus port Port A and a 5 bit contro port Port C e Both inputs and outputs are latched The 5 bit control port Port C is used for control and status for the 8 bit bi directional bus port Port A Bidirectional Bus LO Control Signal Definition INTR interrupt Request A high on this output can be used to interrupt the CPU for input or output oper ations Output Operations OBF Output Buffer Full The OBF output will go low to indicate that the CPU has written data out to port A ACK Acknowledge A low on this input enables the tri state output buffer of Port A to send out the data Otherwise the output buffer will be in the high impedance state INTE 1 The INTE Flip Flop Associated with OBP Controlled by bit set reset of PC6 Input Operations STB Strobe Input A low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output indicates that data has been loaded into the input latch INTE 2 The INTE Flip Flop Associated with IBF Controlled by bit set reset of PCA 3 136 intel 82C55A CONTROL WORD D D D D D D D Dy DINA 1 INPUT De OUTPUT PORTB 1 INPUT 0 OUTPUT GROUP B MODE 0 MODE 0 1 MODE 1 231256 18 Figure 13 MODE Control Word 231256 19 Figure 14 MODE 2
56. ltiple bits in a port OR the current value of the port with the value b where b the sum of the individual bits to be set Note that the bits to be set do not have to be consecutive Example Set bits 3 5 and 7 in a port Read in the current value of the port OR it with 168 168 2 25 27 and then write the resulting value back to the port In assembly language this is programmed as mov dx PortAddress in al dx or al 168 out dx al Often assigning a range of bits is a mixture of setting and clearing operations You can set or clear each bit individually or use a faster method of first clearing all the bits in the range then setting only those bits that must be x set using the method shown above for setting multiple bits in a port The following example shows how this two Step operation is done Example Assign bits 3 4 and 5 in a port to 101 bits 3 and 5 set bit 4 cleared First read in the port and clear bits 3 4 and 5 by ANDing them with 199 Then set bits 3 and 5 by ORing them with 40 and finally write the resulting value back to the port In C this is programmed as 4 8 v inportb port_address v v amp 199 v v 40 outportb port_address v A final note Don t be intimidated by the binary operators AND and OR and try to use operators for which you have a better intuition For instance if you are tempted to use addition and subtraction to set and clear bits in place of the methods shown
57. ng does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current period the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current counting cycie In mode 2 a COUNT of 1 is illegal MODE 3 SQUARE WAVE MODE Mode 3 is typically used for Baud rate generation Mode 3 is similar to Mode 2 except for the duty cycle of OUT OUT will initialiy be high When half the ini tial count has expired OUT goes low for the remain der of the count Mode 3 is periodic the sequence above is repeated indefinitely An initial count of N results in a square wave with a period of N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes tow while OUT is low OUT is set high immediately no CLK pulse is required A trigger reloads the Counter with the initial count on the next CLK pulse Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This allows the Counter to be synchronized by software also Writing a new count while counting does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current half cycle of the square wave the Counter will be loaded with the new co
58. ng the Bit Figure 5 Basic Mode Definitions and Bus Set Reset operation just as if they were data output rn Interface ports 3 128 intel 82C55A Interrupt Control Functions When the 82C55A is programmed to operate in mode 1 or mode 2 control signals are provided that can be used as interrupt request inputs to the CPU The interrupt request signals generated from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset BIT SELECT function of port C 011 2 374 5 6 7 This function allows the Programmer to disallow or allow a specific I O device to interrupt the CPU with out affecting any other device in the interrupt struc ture BIT SET RESET FLAG 0 ACTIVE INTE flip flop definition 231286 7 BIT SET INTE is SET Interrupt enable INTE i di Figure 7 Bit Set Reset Format BIT RESET INTE is RESET Interrupt disable Note All Mask flip flops are automatically reset during mode selection and device Reset 3 129 intel 82C55A Operating Modes Mode 0 Basic Functional Definitions e lt Mode 0 Basic Input Output This functional con pate DO NE a E PONE figuration provides simple input and output opera e Any port can be input or output tions for each of the three ports No handshaking e Outputs are latched is required data is simply written to or read from a e Inputs are not latched specif
59. nt Standby pA CLK Freq DC CS Voc All Inputs Data Bus Vcc All Outputs Floating IccsB1 Voc Supply Current Standby pA CLK Freq DC CS Voc All Other inputs 1 O Pins Van Outputs Open Ow Input Capacitance 10 fe 1MHz 1 O Capacitance 20 PF Unmeasured pins Output Capacitance DE pr SED A C CHARACTERISTICS TA 0 C to 70 C Voc 5V 10 GND 0V Ta 40 C to 85 C for Extended Temperature BUS PARAMETERS Note 1 READ CYCLE ELCHE EN Min tam Address Stable Betore RD 45 tsa CSStbleBetoneRD o ima AddresHoldTimeAfterRDT 0 ns t RDPusewdn 150 n tao DeaaDeayromRD 30 85 n tap DataDelayfromAddress 220 185 ms pr L ADf toDataFloatng 5 9 5 65 ms my Command Recovery Time 20 as nm NOTE 1 AC timings measured at Voy 2 0V Vo 0 8V a c ftm ea 3 96 intel 82054 A C CHARACTERISTICS Continued WRITE CYCLE Parameter w ae meo Min Max Min Max taw Address Stable BeforeWA o o RV tw G5 stable Betre WR 0 twa Address Hold Time After o L 9 ns ww W PuseWdn lolog tow Data Setup Time Berre WAT 120 es n two Data Hola Time After WAY lol 9 T tay Command Recovery Time 200 165 CLOCK AND GATE Parameter Mn Max Min Ma
60. o Digital I O Operations Once the 8255 is initialized you can use the digital I O lines to control or monitor external devices Timer Counters An 8254 programmable interval timer provides three 16 bit 8 MHz timer counters for timing and counting functions such as frequency measurement event counting and interrupts All three timer counters are cascaded at the factory Figure 4 1 shows the timer counter circuitry Each timer counter has two inputs CLK in and GATE in and one output timer counter OUT They can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in the I O map section at the beginning of this chapter One of two clock sources the on board 8 MHz crystal or an external clock routed through on board I O connector P6 can be selected as the clock input to each timer counter In addition the timer counters can be cas caded by connecting TCO s output to TC1 s clock input and TC1 s output to TC2 s clock input The diagram shows how these clock sources are connected to the timer counters An external gate source can be connected to each timer counter through P6 When a gate is disconnected an on board pull up resistor automatically pulls the gate high enabling the timer counter The output from each timer counter is available at P6 where it can be used for interrupt generation or for counting functions The timer counters can be programmed to operate in one o
61. of the selected Counter must be inhibited by using either the GATE input or external logic Other wise the count may be in the process of changing when it is read giving an undefined result 82C54 COUNTER LATCH COMMAND The second method uses the Counter Latch Com mand Like a Control Word this command is written to the Controi Word Register which is selected when Ay Ag 11 Also like a Control Word the SCO SC1 bits select one of the three Counters but two other bits D5 and D4 distinguish this command from a Contro Word A1 Ao 11 CS 0 RD 1 WR 0 D7 De Ds D4 D3 Da Du Do Leo sco o o x x x x SC1 SCO specify counter to be latched SCH SCH Counter Read Back Command D5 D4 00 designates Counter Latch Command X don t care NOTE Don t care bits X should be O to insure compatibility with future Intel products Figure 9 Counter Latching Command Format The selected Counter s output latch OL latches the count at the time the Counter Latch Command is received This count is held in the latch until it is read by the CPU or until the Counter is reprogrammed The count is then unlatched automatically and the OL returns to following the counting element CE This allows reading the contents of the Counters on the fly without affecting counting in progress Multiple Counter Latch Commands may be used to latch more than one Counter Each latched Coun ter s OL holds
62. ol turning motors on and off These motors turn on when the digital lines controlling them are high To use the pull up pull down feature you must first install 10 kilohm resistor packs in any or all of the four locations around the 8255 labeled PA PB PCL and PCH PA and PB take a 10 pin pack and CL and CH take 6 pin packs Figure 1 9 shows these locations After the resistor packs are installed you must connect them into the circuit as pull ups or pull downs Locate the three hole pads on the board near the resistor packs They are labeled G for ground on one end and V for Vcc on the other end The middle hole is common PA is for Port A PB for Port B CL is for Port C Lower and CH is for Port C Upper Figure 1 9 shows a blowup of the pads for Port A To operate as pull ups solder a jumper wire between the common pin middle pin of the three and the V pin For pull downs solder a jumper wire between the common pin middle pin and the G pin For example Figure 1 10 shows Port A lines with pull ups Port C Lower with pull downs and Port C Upper with no resistors 1 8 v 6 v 6 PCL 90000 080050 Eed dsd GHOST SWITCH cs a 0000000 00000000 m 0000000 90000 SWITCH D 74HCT243 100000 gt 0600000 e 10000000 00000600 amp 9 DIO24 009097 o D 777770 999999090000 9 8 9 7 e 82 ER D PAL o gu o p Accensing the Analog World o loloj 3 o ol 060000
63. on as control lines some as outputs and some as inputs When using Mode 1 the Port C buffers must be removed and bypassed to allow the Port C lines to be individually set as inputs or outputs Figure 1 8 shows the Port C buffers and the following steps tell you how to configure the board for Mode 1 operation To remove buffering from Port C 1 Close DIP switches 1 through 8 on S2 2 Remove U3 from the board 3 Remove U4 from the board CAUTION Remember whenever you close the switches be sure to remove the buffers U3 and U4 from the board Failure to do so may damage the board F1 External 5 volt Fuse This 1 ampere fuse protects the 5 volt line available at I O connector P2 pin 49 from drawing too much current and damaging system equipment DIO24 LO CONNECTOR P2 Fig 1 8 Port C Buffer Circuitry Pull up Pull down Resistors on Digital UO Lines The 8255 programmable peripheral interface provides 24 parallel TTL CMOS compatible digital I O lines which can be interfaced with external devices The lines are divided into four groups eight Port A lines four Port C Lower lines eight Port B lines and four Port C Upper lines You can install and connect pull up or pull down resistors for any or all of these four groups of lines You may want to pull lines up for connection to switches This will pull the line high when the switch is disconnected Or you may want to pull down lines connected to relays which contr
64. ontinues until the new count expires CWs12 LSB 3 3333151212 CW 12 LSB 3 HAHA CW 12 LSB 2 o FFI FF Oo 0 Oj FF FE 4 3 231244 9 Figure 16 Mode 1 MODE 2 RATE GENERATOR This Mode functions like a divide by N counter It is typicially used to generate a Real Time Clock inter rupt OUT will initially be high When the initial count has decremented to 1 OUT goes low for one CLK pulse OUT then goes high again the Counter re loads the initial count and the process is repeated Mode 2 is periodic the same sequence is repeated indefinitely For an initial count of N the sequence repeats every N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low during an output pulse OUT is set high immediately A trigger reloads the Counter with the initial count on the next CLK pulse OUT goes low N CLK pulses after the trigger Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse OUT goes low N CLK Pulses after the initial count is writ ten This allows the Counter to be synchronized by software also CW 14 LSB 3 KALAKAKABABAK lated sts CW 14 LSBe3 CWs 4 LSB 4 Ininindniiisieltislilsi 231244 10 NOTE A GATE transition should not occur one clock prior to terminal count Figure 17 Mode 2 3 92 Se 82C54 Writing a new count while counti
65. output data groups Port C Upper and Port C Lower between the board and an external device A read transfers data from the external device through P2 and into PPI Port C a write transfers the written data from Port C through P2 to an external device 4 3 BA 3 8255 PPI Control Word Write Only When bit 7 of this word is set to 1 a write programs the PPI configuration Bit 6 must always be set to 0 Mode 2 operation is not supported by the DIO24 The table below shows the control words for the 16 possible Mode 0 Port I O combinations Set Flag Port C Lower active 0 output II an Mode Select 1 input 00 mode 0 01 mode 1 l Port B 1x mode 2 output input Port A 0 output Mode Select 1 input 0 mode 0 1 mode 1 ort C Upper Ll___________ P L Group B a 0 output Group A 1 input U EN ze 8255 Port UO Flow Direction and Control Words Mode 0 ona Ge roro L I aay Less me Upper Port B Lower Binary Decimal opa ou oupa oupa 10000000 12 Output ouput oe input 10000001 12o o Output Output hou Oups 10000010 tso s Output Output input input 1000001 tes es tooroooo a 10010010 10010011 10011000 10011001 6 7 2 co N 4 1 gt lt a LA o gt 10011010 154 155 m 10011011
66. port 21H and set the bit that corresponds to your IRQ remember setting a bit disables interrupts on that IRQ while clearing a bit enables them The IMR is arranged so that bit O is for IRQO bit 1 is for IRQ1 and so on See the paragraph entitled Interrupt Mask Register IMR earlier in this chapter for help in determining your IRQ s bit After setting the bit write the new value to I O port 21H With the startup IMR saved and the interrupts on your IRQ temporarily disabled you can assign the interrupt vector to point to your ISR Again you can overwrite the appropriate entry in the vector table with a direct memory write but this is a bad practice Instead use either DOS function 25H set interrupt vector or if your compiler provides it the library routine for setting an interrupt vector Remember that vector 8 is for IRQO vector 9 is for IRQ1 and so on If you need to program the source of your interrupts do that next For example if you are using the program mable interval timer to generate interrupts you must program it to run in the proper mode and at the proper rate Finally clear the bit in the IMR for the IRQ you are using This enables interrupts on the IRQ 4 13 Restoring the Startup IMR and Interrupt Vector Before exiting your program you must restore the interrupt mask register and interrupt vectors to the state they were in when your program started To restore the IMR write the value that was saved when you
67. r 1 reviews the factory settings and how to change them If you need to change any settings refer to the appropriate instructions in Chapter 1 Note that incompatible jumper settings can result in unpredictable board operation and erratic response Also note that the P2 I O connector mounting bracket has an oversized cutout to allow space for running the cable to 20 pin on board connector P6 through the same I O slot If you want to run both cables through the same slot you must make these connections before installing the board To install the board 1 2 Turn OFF the power to your computer Remove the top cover of the computer housing refer to your owner s manual if you do not already know how to do this Select any unused short or full size expansion slot and remove the slot bracket Touch the metal housing of the computer to discharge any static buildup and then remove the board from its antistatic bag Holding the board by its edges orient it so that its card edge bus connector lines up with the expansion slot connector in the bottom of the selected expansion slot After carefully positioning the board in the expansion slot so that the card edge connector is resting on the computer s bus connector gently and evenly press down on the board until it is secured in the slot NOTE Do not force the board into the slot If the board does not slide into place remove it and try again Wiggling the board or exertin
68. r program started to I O port 21H Restore the interrupt vector that was saved at startup with either DOS function 35H get interrupt vector or use the library routine supplied with your compiler Performing these two steps will guarantee that the interrupt status of your computer is the same after running your program as it was before your program started running Common Interrupt Mistakes Remember that hardware interrupts are numbered 8 through 15 even though the corresponding IRQs are numbered 0 through 7 Two of the most common mistakes when writing an ISR are forgetting to clear the interrupt status of the DIO24 and forgetting to issue the EOI command to the 8259 interrupt controller before exiting the ISR Example Programs Included with the DIO24 is a set of example programs that demonstrate the use of many of the board s features These examples are in written in C Pascal Assembly and BASIC Also included is an easy to use menu driven diagnostics program 24DIAG which is especially helpful when you are first checking out your board after installa tion Before using the software included with your board make a backup copy of the disk You may make as many backups as you need C and Pascal Programs These programs are source code files so that you can easily develop your own custom software for your DIO24 board Digital VO DIGITAL Simple program the shows how to read and write the digital I O lines Timer Counter
69. ram must not transfer control between writing the first and second byte to another routine which also writes into that same Counter Otherwise the Counter will be loaded with an incorrect count d Counter 2 Counter 1 Counter 0 Counter 2 Counter 2 Counter 1 Counter 1 Counter 0 Counter 0 Control Word Control Word Control Word LSB of count MSB of count LSB of count MSB of count LSB of count MSB of count OO OO Oh gt hb k gt oo ooa DP mb Counter 1 Counter 0 Counter 1 Counter 2 Counter 0 Counter 1 Counter 2 Counter 0 Counter 2 Control Word Control Word LSB of count Control Word LSB of count MSB of count LSB of count MSB of count MSB of count OH A CO A E A A P gt 0o00 0 gt In all four examples all counters are programmed to read write two byte counts These are only four of many possible programming sequences Figure 8 A Few Possible Programming Sequences Read Operations lt is often desirable to read the value of a Counter without disturbing the count in progress This is easi ly done in the 82054 There are three possible methods for reading the counters a simple read operation the Counter 3 88 Latch Command and the Read Back Command Each is explained below The first method is to per form a simple read operation To read the Counter which is selected with the A1 AO inputs the CLK input
70. read from that counter The counter status format is shown in Figure 11 Bits D5 through DO contain the counter s programmed Mode exactly as written in the last Mode Control Word OUTPUT bit D7 contains the current state of the OUT pin This allows the user to monitor the counter s output via software possibly eliminating some hardware from a system Da D3 Da D D De Ds Do NULL sr se een Dy 1 Out Pin is 1 0 Out Pin is 0 Dg 1 Null count 0 Count available for reading D5 Do Counter Programmed Mode See Figure 7 Figure 11 Status Byte NULL COUNT bit D6 indicates when the last count written to the counter register CR has been loaded into the counting element CE The exact time this happens depends on the Mode of the counter and is described in the Mode Definitions but until the count is loaded into the counting element CE it can t be read from the counter If the count is latched or read before this time the count value will not reflect the new count just written The operation of Null Count is shown in Figure 12 Command P De 0g Da Sa Pg Bs Po Description Read back count and status of Count and status latched Counter 0 for Counter 0 1 BEEN Lolo Read back status of Counter 1 Status latched for Counter 1 Read back status of Counters 2 1 Status latched for Counter 2 but not Counter 1 KI Read back count and status of Count latched for Counter 1 Counter 1 but not stat
71. reset Port C lines programmed as inputs including ACK and STB lines associated with Port C are not affected by a Set Reset Port C Bit command Writing to the corresponding Port C bit positions of the ACK and STB lines with the Set Reset Port C Bit command will affect the Group A and Group B interrupt enable flags as illus trated in Figure 18 Current Drive Capability Any output on Port A B or C can sink or source 2 5 mA This feature allows the 82C55A to directly drive Darlington type drivers and high voltage displays that require such sink or source current 3 139 82C55A MODE 2 AND MODE 0 OUTPUT MODE 2 AND MODE O INPUT CONTROL WORD D D Ds D D D D Do DL RA lie fo CONTROL WORD D Ds D D D Oz D De DDD hal PC 20 1 INPUT 0 OUTPUT MODE 2 AND MODE 1 OUTPUT MDDE 2 AND MODE 1 INPUT CONTROL WORD Dy De Ds Da D D D Dp DI Pd DI CONTROL wORO D De Ds D Da D D Do PI PP Lo PQ 231256 21 Figure 16 MODE 1 Combinations 3 138 intel 82C55A Reading Port C Status In Mode 0 Port C transfers data to or from the pe ripheral device When the 82C55A is programmed to function in Modes 1 or 2 Port C generates or ac cepts hand shaking signals with the peripheral de vice Reading the contents of Port C allows the pro grammer to test or verify the status of each pe
72. rigger This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after a trigger A trigger results in the Counter being loaded with the initial count on the next CLK pulse The counting sequence is retriggerable OUT will not strobe low for N 1 CLK pulses after any trigger GATE has no effect on OUT If a new count is written during counting the current counting sequence will not be affected If a trigger occurs after the new count is written but before the current count expires the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there CW 1A 1 823 Isle jujun eales CWelA LSB 3 Vala felafelalstelstelse lk CW tA LSB 3 158 5 AGA KAKA KARA Tope HA 231244 13 Figure 20 Mode 5 3 94 82C54 Signal Low Status Or Going Modes Low Disables Enables counting counting 1 initiates counting 2 Resets output after next clock 1 Disables counting Initiates Enables 2 Sets output counting counting immediately 1 Disables counting initiates Enables 2 Sets output counting counting immediately high Enables counting Initiates counting NOTE 0 is equivalent to 216 for binary counting and 104 for BCD counting Figure 22 Minimum and Maximum initial Counts 3 95 Operation Common to All Modes Programming When a
73. ripheral device and change the program flow ac cordingly There is no special instruction to read the status in formation from Port C A normal read operation of Port C is executed to perform this function PC2 PC4 PC6 Interrupt Enable Flag Position Alternate Port C Pin Signal Mode ACKg Output Mode 1 or STBg Input Mode 1 STBA Input Mode 1 or Mode 2 ACKA Output Mode 1 or Mode 2 INPUT CONFIGURATION D De Ds Da Ds Dz D Do GROUP B OUTPUT CONFIGURATIONS 6 Ds D4 Da D Dj D D7 D 2 0 Ba An GROUP A GROUP B Figure 17a MODE 1 Status Word Format GROUP A D Dg D D D DO D D GROUP B GROUP A Defined By Mode 0 or Mode 1 Selection Figure 17b MODE 2 Status Word Format Figure 18 Interrupt Enable Flags in Modes 1 and 2 3 140 intel 82C55A ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias 0 C to 70 C Storage Temperature 65 C to 150 C Supply Voltage 0 5 to 8 0V Operating Voltage 4Vto 7V Voltage on any Input GND 2V to 6 5V Voltage on any Output GND 0 5V to Voc 0 5V Power Dissipation 1 Watt D C CHARACTERISTICS Ta 0 C to 70 C Voo 5V 10 GND OV Ta 40 C to 85 C for Extended Temperture Symbol Parameter Output High Voltage Output Float Leakage Current Darlington Drive Current IPHLO Port Hold Lo
74. rite software interrupt handlers When an interrupt request line is driven high by a peripheral device such as the DIO24 the 4 11 interrupt controller checks to see if interrupts are enabled for that IRQ and then checks to see if other interrupts are active or requested and determines which interrupt has priority The interrupt controller then interrupts the proces sor The current code segment CS instruction pointer IP and flags are pushed on the stack for storage and a new CS and IP are loaded from a table that exists in the lowest 1024 bytes of memory This table is referred to as the interrupt vector table and each entry is called an interrupt vector Once the new CS and IP are loaded from the interrupt vector table the processor begins executing the code located at CS IP When the interrupt routine is completed the CS IP and flags that were pushed on the stack when the interrupt occurred are now popped from the stack and execution resumes from the point where it was interrupted Using Interrupts in Your Programs Adding interrupts to your software is not as difficult as it may seem and what they add in terms of performance is often worth the effort Note however that although it is not that hard to use interrupts the smallest mistake will often lead to a system hang that requires a reboot This can be both frustrating and time consuming But after a few tries you ll get the bugs worked out and enjoy the benefits of properl
75. s TIMER A short program demonstrating how to program the 8254 for use as a timer BASIC Programs These programs include both source code files and executable files so that you can run them on your DIO24 All of the executable programs are set up to look for the board at a base address BA of 300 hex 768 decimal If you change the base address of the board you must also change the BA in your programs Digital VO DIGITAL Simple program the shows how to read and write the digital I O lines Timer Counters TIMER A short program demonstrating how to program the 8254 for use as a timer 4 14 A 1 APPENDIX A DIO24 SPECIFICATIONS A 2 DIO24 Characteristics Typical 25 C Interface Switch selectable base address I O mapped Jumper selectable interrupts Digital VO SE CMOS 82C55 Opto 22 compatible Number of lines x u 24 Logic compatibility ano nnne TTL CMOS Configurable with optional I O pull up pull down resistors High level output voltage 4 2V min Low level output voltage T 0 45V max High level input voltage 2 2V min 5 5V max Low level input voltage 0 3V min 0 8V max High level output current Isource
76. s and system modules Each digital I O line on P2 has a digital ground as shown in Figure 2 1 For all digital I O connections the high side of an external signal source or destination device is connected to the appropriate signal pin on the I O connector and the low side is connected to the DIGITAL GND A cable to provide direct connection to opto 22 systems is available as an accessory from RTD Connecting the Timer Counter UO External connections to the timer counters on the DIO24 2 model can be made by connecting the high side of the external device to the appropriate signal pin on on board connector P6 and the low side to a P6 DIGITAL GND Connecting the External Interrupt The DIO24 can receive an externally generated interrupt signal EXTINT through I O connector P2 pin 2 and route it to an IRQ channel through on board header connectors P3 and P4 Interrupt generation is enabled through software When interrupts are enabled a rising edge on the EXTINT line will cause the selected IRQ line to go high and the IRQ status bit will change from 0 to 1 The pulse applied to the EXTINT pin should have a duration of at least 100 nanoseconds Running the 24DIAG Diagnostics Program Now that your board is ready to use you will want to try it out An easy to use menu driven diagnostics program 24DIAG is included with your example software to help you verify your board s operation You can also use this program to make sure that your current ba
77. se address setting does not contend with another device 2 4 CHAPTER3 HARDWARE DESCRIPTION This chapter describes the major features of the DIO24 s 8255 based digital I O and 8254 timer counters This chapter also de scribes the hardware selectable interrupts 3 1 The DIO24 provides buffered digital 1 O lines as shown Figure 3 1 In addition the DIO24 2 model providesthree 16 bit timer counters This chapter describes the hardware which makes up the digital UO circuitry timer counters and hardware selectable interrupts ON BOARD CONNECTOR o w o o 9 BUFFERS AN D PULL UP DOWN RESISTORS CONTROL Fig 3 1 DIO24 Block Diagram Digital VO 8255 Programmable Peripheral Interface The 8255 programmable peripheral interface PPI can be easily configured to solve a wide range of digital real world problems This high performance TTL CMOS compatible chip has 24 parallel programmable digital UO lines divided into two groups of 12 lines each Group A Port A 8 lines and Port C Upper 4 lines Group B Port B 8 lines and Port C Lower 4 lines Each group can be programmed for Mode 0 or Mode 1 operation Do not try to use Mode 2 operation The DIO24 does not support Mode 2 When operating in Mode 1 the on board buffers must be removed from the Port C lines This procedure is described in Chapter 1 in the S2 DIP switch discussion The DIO24 operating modes are Mod
78. ssed without removing the board from the computer The following sections describe the register contents of each address used in the I O map Table 4 1 DIO24 I O Map Register Description Read Function Write Function Decimal 8255 PPI Port A BA 0 8255 PPI Port B BA 1 8255 PPI Port C BA 2 8255 PPI Control Word BA 3 Enable and disable interrupt IRQ Enable Not used generation BA 4 o NIN PI ala o Io SIS o lo 9 3 5 13 ala jo 1D SIS e la elo o N Interrupt Status Clear Read status of interrupt Clear interrupt BA 5 SZ ae nn 777 8254 Timer Counter 0 Sep 8254 Timer Counter 1 BA 9 BA 10 BA 11 D gt D D Zo o gt a a 2 bi o BA 0 PPI Port A Digital I O Read Write Transfers the 8 bit Port A digital input and digital output data between the board and an extemal device A read transfers data from the external device through P2 and into PPI Port A a write transfers the written data from Port A through P2 to an external device BA 1 PPI Port B Digital I O Read Write Transfers the 8 bit Port B digital input and digital output data between the board and an external device A read transfers data from the external device through P2 and into PPI Port B a write transfers the written data from Port B through P2 to an external device BA 2 PPI Port C Digital I O Read Write Transfers the two 4 bit Port C digital input and digital
79. st by monitoring each board s IRQ status bit NOTE When you use multiple boards that share the same interrupt only one board should have the G ground jumper installed The rest should be disconnected Whenever you operate a single board the G jumper should be installed INT SOURCE IRQ STATUS INTERRUPT REGISTER INTERRUPT CLR Fig 1 3 Pulling Down the Interrupt Request Line P4 Interrupt Source Select Factory Setting EXT This header connector shown in Figure 1 4 lets you connect one of six interrupt sources for interrupt genera tion These sources are OTO OT1 and OT2 which are the three 8254 timer counter outputs available on the DIO24 2 model PC3 which is the INTRA signal from the 8255 PPI PCO which is the INTRB signal from the 8255 PPI and EXT an extemal interrupt you can route onto the board through the P2 1 O connector To connect an interrupt source place the jumper across the desired set of pins Note that only ONE interrupt source can be acti vated at a time 1 4 EXT PC3 PCO OTO OT OT2 P4 Fig 1 4 Interrupt Source Select Jumper P4 P5 8254 Timer Counter Clock Sources Factory Settings CLK0 XTAL CLK1 OUTO0 CLK2 OUT1 This header connector shown in Figure 1 5 lets you select the clock sources for the 8254 timer counters TCO TC1 and TC2 which are on the DIO24 2 model The factory setting cascades all three timer counters with the clock source for TCO be
80. ster IMR and Interrupt Vector 4 13 Restoring the Startup IMR and Interrupt Vector 4 14 Common Interrupt Mistaffffeeeee 4 14 Example Programs E 4 14 C and Pascal Programs u u Eege ERE ei ER E N Ei r ii 4 14 BASIC Programs y ere Ee Ee 4 14 APPENDIX A DIO24 SPECIFICATIONS A 1 APPENDIX B UO CONNECTOR PIN ASSIGNMENT S B 1 APPENDIX C COMPONENT DATA SHEETS C 1 APPENDIX D WARRANTY iy ANA isst D 1 1 1 1 2 1 3 14 1 5 1 6 1 7 1 8 1 9 1 10 2 1 3 1 4 1 LIST OF ILLUSTRATIONS Board Layout Showing Factory Configured Settings 1 3 Interrupt and Interrupt Channel Jumper P3 1 4 Pulling Down the Interrupt Request Line 1 4 Interrupt Source Select Jumper P4 1 5 8254 Timer Counter Clock Source Jumpers P5
81. the CPU is reading one of the counters A low on the WR input tells the 82054 that the CPU is writing either a Control Word or an initial count Both RD and WR are qualified by CS RD and WR are ignored unless the 82C54 has been selected by holding CS low 3 85 CONTROL WORD REGISTER The Control Word Register se Figure 4 is selected by the Read Write Logic when Ay Ag 11 If the CPU then does a write operation to the 82C54 the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters The Control Word Register can only be written to status information is available with the Read Back Command DATA Bus BUFFER o 5 2 x z Iw E z 231244 5 Figure 4 Block Diagram Showing Control Word Register and Counter Functions COUNTER 0 COUNTER 1 COUNTER 2 These three functional blocks are identical in opera tion so only a single Counter will be described The internal block diagram of a single counter is shown in Figure 5 The Counters are fully independent Each Counter may operate in a different Mode The Control Word Register is shown in the figure it is not part of the Counter itself but its contents de termine how the Counter operates 82C54 CONTROL WORD REGISTER es STAT REGISTER L LL control L LI 231244 6 Figure 5 Internal Block Diagram of a Counter The status register shown
82. the basics just something that will convince you that it works such as incrementing a global variable NOTE If you are writing an ISR using assembly language you are responsible for pushing and popping registers and using IRET instead of RET There are a few cautions you must consider when writing your ISR The most important is do not use any DOS functions or routines that call DOS functions from within an ISR DOS is not reentrant that is a DOS function cannot call itself In typical programming this will not happen because of the way DOS is written But what about when using interrupts Then you could have a situation such as this in your program If DOS function X is being executed when an interrupt occurs and the interrupt routine makes a call to DOS function X then function X is essentially being called while it is already active Such a reentrancy attempt spells disaster because DOS functions are not written to support it This is a complex concept and you do not need to understand it Just make sure that you do not call any DOS functions from within your ISR The one wrinkle is that unfortunately it is not obvious which library routines included with your compiler use DOS functions A rule of thumb is that routines which write to the screen or check the status of or read the keyboard and any disk I O routines use DOS and should be avoided in your ISR The same problem of reentrancy exists for many floating point emulators as well me
83. tion Most high level languages such as BASIC Pascal C and C and of course assembly language make it very easy to read write these ports The table below shows you how to read from and write to I O ports using some popular programming languages Tora m E Assembly mov dx Address mov dx Address in al dx mov al Data out dx al In addition to being able to read write the I O ports on the DIO24 you must be able to perform a variety of operations that you might not normally use in your programming The table below shows you some of the operators discussed in this section with an example of how each is used with Pascal C and BASIC Note that the modulus operator is used to retrieve the least significant byte LSB of a two byte word and the integer division operator is used to retrieve the most significant byte MSB C amp a b c a b c a b amp c Pascal MOD DIV AND OR a bMODc a bDIVc a bANDc a bORc BASIC MOD backslash AND OR a bMODc a b c a bANDc a bORc Many compilers have functions that can read write either 8 or 16 bits from to an I O port For example Turbo Pascal uses Port for 8 bit port operations and PortW for 16 bits Turbo C uses inportb for an 8 bit read of a port and inport for a 16 bit read Be sure to use only 8 bit operations with the DIO24 Clearing and Setting Bits in a Port When you clear or set one or more bits in a port you must be careful that you do not change the status of the
84. uence is triggered by writing the initial count GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after the initial count is written If a new count is written during counting it will be loaded on the next CLK pulse and Counting will con tinue from the new count Ha two byte count is writ ten the following happens 3 93 intel 82C54 1 Writing the first byte has no effect on counting 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the sequence to be retriggered by software OUT strobes low N 1 CLK pulses after the new count of N is written CW 18 LSB lt 3 o FF FF FF pm fo 53131 le lee lee rol CWa16 18823 ojo cs SE ao 313123 2 110 lee CW W LS8 3 LSB 2 ojojojo jojo Fr In nininisil tili e 231244 12 Figure 19 Mode 4 MODE 5 HARDWARE TRIGGERED STROBE RETRIGGERABLE OUT will initially be high Counting is triggered by a rising edge of GATE When the initial count has ex pired OUT will go low for one CLK pulse and then go high again After writing the Control Word and initial count the counter will not be loaded until the CLK pulse after a t
85. unt on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current half cycie Mode 3 is implemented as follows Even counts OUT is initially high The initial count is loaded on one CLK puise and then is decremented by two on succeeding CLK pulses When the count expires OUT changes value and the Counter is re loaded with the initial count The above process is repeated indefinitely Odd counts OUT is initially high The initial count minus one an even number is loaded on one CLK pulse and then is decremented by two on succeed ing CLK pulses One CLK pulse after the count ex pires OUT goes low and the Counter is reloaded with the initial count minus one Succeeding CLK pulses decrement the count by two When the count expires OUT goes high again and the Counter is reloaded with the initial count minus one The above process is repeated indefinitely So for odd counts OUT will be high for N 1 2 counts and low for N 1 2 counts CW W LS8 4 K a aS PRL lA Se Cw w 18Bas JUVUUVUVUUVUUUIL Lelsleltelziztztzlziztziziztz Cw W 8806 HOOQGHHHHHHHEHEH 231244 11 NOTE A GATE transition should not occur one clock prior to terminal count Figure 18 Mode 3 MODE 4 SOFTWARE TRIGGERED STROBE OUT will be initially high When the initial count ex Pires OUT will go low for one CLK pulse and then go high again The counting seq
86. us Read back status of Counter 1 Command ignored status already latched for Counter 1 CAUSES Nuli count 1 THIS ACTION A Write to the control word register D B Write to the count register CR 2 C New count is loaded into CE CR CE Null count 1 Null count 0 1 Only the counter specified by the control word will have its null count set to 1 Null count bits of other counters are unaffected I2 Jf the counter is programmed for two byte counts least significant byte then most significant byte null count goes to 1 when the second byte is written Figure 12 Null Count Operation If multiple status latch operations of the counter s are performed without reading the status all but the first are ignored i e the status that will be read is the status of the counter at the time the first status read back command was issued Both count and status of the selected counter s may be latched simultaneously by setting both COUNT and STATUS bits D5 D4 0 This is func tionally the same as issuing two separate read back commands at once and the above discussions ap ply here also Specifically if multiple count and or status read back commands are issued to the same counter s without any intervening reads all but the first are ignored This is illustrated in Figure 13 If both count and status of a counter are latched the first read operation of that counter will return latched status regardless of w
87. utput can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU INTR is set when ACK is a one OBF is a one and INTE is a one It is reset by the falling edge of WR INTE A Controlled by bit set reset of PCg INTE B Controlled by bit set reset of PCo MODE 1 PORT A CONTROL WORD D De Dy D Dy D D Dy BORO 00x Ban 1e INPUT 0 OUTPUT MODE 1 PORT 8 CONTROL WORD D Oz Os D D D D Da L PEDI 1e DS Figure 11 MODE 1 Strobed Output 23125616 82C55A Combinations of MODE 1 Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed 1 O applications CONTROL WORD Dy Ds Dy D D D D D oel hali X o 3 INPUT 0 OUTPUT PORT A STROBED INPUT PORT B STROBED OUTPUT CONTROL WORD D D Ds D D D D Do Jo fs bel PQ PC s 1 S INPUT RD PORT A STROBED OUTPUT PORT B STROBED INPUT 231256 17 Figure 12 Combinations of MODE 1 Operating Modes MODE 2 Strobed Bidirectional Bus 1 0 This functional configuration provides a means for com municating with a peripheral device or structure on a single 8 bit bus for both transmitting and receiving data bidirectional bus 1 0 Handshaking signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1 interrupt generation and enable disab
88. w Overdrive Current loc Vcc Supply Current Vcc Supply Current Standby NOTES 1 Pins Ay Ag CS WA RD Reset Ge 2 Data Bus Ports B CG 3 Outputs open i 4 Limit output current to 4 0 mA Min Vu inputtowvorage os os v Vin Input High votage 20 ve v Output Low Voltage o4 V l 25ma 3 0 Input Leakage Current E 125 Note 4 mA Ports A B C Rext 5000 Vet 17V IPHL Port Hold Low Leakage Current 50 300 pA VouT 1 0V m Port A only Port Hold High Leakage Current J Port Hold High Overdrive Current Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam age to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera tional sections of this specification is not implied Ex posure to absolute maximum rating conditions for extended periods may affect device reliability Max Units Test Conditions V lou 25 mA V lou 100 pA 1 pA Vin Voc to OV Note 1 10 pA Vin Voc to OV Note 2 Vout 3 0V Ports A B C PIE pA Vour 08V BA 10 ma Vout 3 0V Note 3 Voc 5 5V Vin Voc or GND Port Conditions If 1 P Open High O P Open Only With Data Bus High Low CS High Reset Low Pure Inputs Low High pA 3
89. x Clock Period 125 pc twa HighPusewidn 609 sx m tem LowPuseWitn 609 LI um a L3 m t GockfalTme 25 J 25 ms tew GateWidthHgh 50 to GatewidthLow 5o tes GateSetupTimetoCLkf 50 Too T ouput Delay tom cu y Te Dina Oe Gate E BE EE ng Geta Sangin 07 two T OUT Delay from Mode Write 1 te CLK SetUptorGountLatch 40 NOTES 2 In Modes 1 and 5 triggers are sampled on each rising clock edge A second trigger within 120 ns 70 ns for the 82C54 2 of the rising clock edge may not be detected 3 Low going glitches that violate tpwu ipw may cause errors requiring counter reprogramming 4 Except tor Extended Temp See Extended Temp A C Characteristics beiow 5 Sampled not 100 tested Ta 25 C 6 If CLK present at Twc min then Count equals N 2 CLK pulses Two max equals Count N 1 CLK pulse Twc min to Twc max count will be either N 1 or N 2 CLK pulses 7 In Modes 1 and 5 if GATE is present when writing a new Count value at Twa min Counter will not be triggered at TwG max Counter will be triggered 8 If CLK present when writing a Counter Latch or ReadBack Command at Ter min CLK will be reflected in count value latched at Tc max CLK will not be reflected in the count value latched Writing a Counter Latch or ReadBack Command between Tc min and Tw max will result in a latched count vallue which is one least significant bit
90. x is written to the counter 4 LSB stands for Least Significant Byte of count 5 Numbers below diagrams are count values The lower number is the least significant byte The upper number is the most significant byte Since the counter is programmed to Read Write LSB only the most significant byte cannot be read N stands for an undefined count Vertical lines show transitions between count values Figure 15 Mode 0 intel 82054 MODE 1 HARDWARE RETRIGGERABLE ONE SHOT i OUT will be initially high OUT will go low on the CLK pulse following a trigger to begin the one shot pulse and will remain low until the Counter reaches zero OUT will then go high and remain high until the CLK puise after the next trigger After writing the Control Word and initial count the Counter is armed A trigger results in loading the Counter and setting OUT low on the next CLK pulse thus starting the one shot pulse An initial count of N will result in a one shot pulse N CLK cycles in dura tion The one shot is retriggerable hence OUT will remain low for N CLK pulses after any trigger The one shot pulse can be repeated without rewriting the same count into the counter GATE has no effect on OUT If a new count is written to the Counter during a one shot pulse the current one shot is not affected un less the Counter is retriggered In that case the Counter is loaded with the new count and the one shot pulse c
91. y executed interrupts Writing an Interrupt Service Routine ISR The first step in adding interrupts to your software is to write the interrupt service routine ISR This is the routine that will automatically be executed each time an interrupt request occurs on the specified IRQ An ISR is different than standard routines that you write First on entrance the processor registers should be pushed onto the stack BEFORE you do anything else Second just before exiting your ISR you must clear the interrupt status of the DIO24 and write an end of interrupt command to the 8259 controller Finally when exiting the ISR in addition to popping all the registers you pushed on entrance you must use the IRET instruction and not a plain RET The IRET automatically pops the flags CS and IP that were pushed when the interrupt was called If you find yourself intimidated by interrupt programming take heart Most Pascal and C compilers allow you to identify a procedure function as an interrupt type and will automatically add these instructions to your ISR with one important exception most compilers do not automatically add the end of interrupt command to the procedure you must do this yourself Other than this and the few exceptions discussed below you can write your ISR just like any other routine It can call other functions and procedures in your program and it can access global data If you are writing your first ISR we recommend that you stick to
92. z NOTE 1 INTR T may occur as early as WR J 2 Pulse width of initial Reset pulse after power on must be at least 50 Sec Subsequent Reset pulses may be 500 ns minimum 3 143 intel 82C55A WAVEFORMS MODE 0 BASIC INPUT 231256 22 MODE 0 BASIC OUTPUT 231256 23 3 144 intel 82C55A WAVEFORMS Continued MODE 1 STROBED INPUT INPUT FROM PERIPHERAL 231256 24 231256 25 3 145 intel f 82C55A WAVEFORMS Continued MODE 2 BIDIRECTIONAL DATA FROM 8080 TO 8256 PERIPHERAL Bus DATA FROM DATA FROM PERIPHERAL TO 8255 8265 TO PERIPHERAL DATA FROM 8266 TO 8060 231256 26 Note Any sequence where WR rn before ACK AND STB occurs before RD is permissible INTR IBF e MASK e e RD OBF e MASK e ACK e WR WRITE TIMING I READ TIMING DATA BUE Z MIGM IMPEDANCE Z 231256 27 A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT 20 TEST 08 oe 045 231256 29 A C Testing In Are Driven At 2 4V For A Logic 1 And 0 45V pos Log Vexr Is Set At Various Voltages During Testing To Guarantee The Specification CL Includes Jig Capacitance ATAR 231256 30 For A Logic 0 Timing Measurements Are Made At 2 0V For A Logic 1 And 0 8 For A Logic 0 3 146 Intel 82054 Programmable Interval Timer Data Sheet Reprint intel 82C54 CHMOS PROGRAMMABLE INTERVAL TIMER m Compatible with all Intel an

dio24 manual - RTD Embedded Technologies, Inc.

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