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Infineon C868 User`s Manual

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1. T12DTCH Timer T12 Dead Time Control Register High Byte Reset value 00 1 7 6 5 4 3 2 1 0 DTR DTE r rh r rw Field Bits Typ Description DTE 2 0 rw Dead Time Enable Bits Bits DTEO DTE2 enable and disable the dead time generation for each compare channel 0 1 2 of timer T12 ODead time generation is disabled The corresponding outputs switch from the passive state to the active state according to the actual compare status without any delay 1Dead time generation is enabled The corresponding outputs switch from the passive state to the active state according to the compare status with the delay programmed in bitfield DTM DTR 6 4 rh Dead Time Run Indication Bits Bits DTRO DTR2 indicate the status of the dead time generation for each compare channel 0 1 2 of timer T12 OThe value of the corresponding dead time counter channel is 0 1The value of the corresponding dead time counter channel is not O 7 3 r reserved returns 0 if read should be written with 0 Note The dead time counters are clocked with the same frequency as T12 This structure allows symmetrical dead time generation in center aligned and in edge aligned PWM mode A duty cycle of 50 leads to CC6x COUT6x switched on for 0 5 period dead time Note The dead time counters are not reset by bit T12RES but by bit DTRES User s Manual 4 65 V 0 4 2002 01 _ Infineon C868 t
2. 4 103 4 9 1 1 Baud Rate in Mode 2 4 104 4 9 1 2 Baud Rate Mode 1 4 104 4 9 2 Details about Mode 4 106 4 9 3 Details about 2 4 110 4 10 A D Converter 4 114 4 10 1 Register Definition of the ADC 4 115 User s Manual 2 V 0 4 2002 01 _ Infineon C868 technologies d HUE Rd 4 117 4 10 3 Operation of the ADC 4 118 4 10 4 Module Powerdown 4 118 4 11 Conversion and Sample Time 4 119 4 11 1 A D Converter Calibration 4 121 5 Reset and System Clock 5 1 5 1 Hardware Reset Operation 5 1 5 2 Internal Reset after Power On 5 2 5 3 BIOWMOUL PPP 5 4 5 4 Clock Generation 5 5 5 5 PLL Operation m 5 5 5 5 1 VCO Frequency Ranges 5 6 5 5 2 K Divider MMC P 5 6 5 5 3 Determining the PLL Clock Frequency 5 6 5 6 Slow Down Operation 5 8 5 6 1 Switching Between PLL
3. User s Manual 8 3 V 0 4 2002 01 _ Infineon C868 technologies Power Saving Modes 8 3 Idle Mode In the idle mode the oscillator of the C868 continues to run but the CPU is gated off from the clock signal However the interrupt system the serial port the A D converter the capture compare unit and all timers with the exception of the watchdog timer are further provided with the clock The CPU status is preserved in its entirety the stack pointer program counter program status word accumulator and all other registers maintain their data during idle mode The reduction of power consumption which can be achieved by this feature depends on the number of peripherals running If all timers are stopped and the A D converter and the serial interfaces are not running the maximum power reduction can be achieved This state is also the test condition for the idle mode ppc Thus the user has to take care which peripheral should continue to run and which has to be stopped during idle mode Also the state of all port pins either the pins controlled by their latches or controlled by their secondary functions depends on the status of the controller when entering idle mode Normally the port pins hold the logical state they had at the time when the idle mode was activated If some pins are programmed to serve as alternate functions they still continue to output during idle mode if the assigned function is on
4. Field Bits Typ Description IDLE 0 rw ldle mode enable bit When set starting of the idle mode is enabled PDE 1 rw Power down enable bit When set starting of the power down is enabled GFO 2 rw General purpose flag GF1 3 rw General purpose flag SD 4 rw Slow down mode bit When set the slow down mode is enabled 6 5 reserved returns 0 if read should be written with 0 User s Manual 8 2 V 0 4 2002 01 mn Infineon C668 technologies Power Saving Modes PMCONO Wake up Control Register Reset value XXX000000g 7 6 5 4 3 2 1 0 EBO BO SDSTAT WS EWPD r r r rw rw rh rw rw The functions of the shaded bits are not described here Field Bits Typ Description EWPD 0 rw Enable Wake Up from Power Down Mode When this bit is set power down mode can be terminated either by an external active INTO signal or by an external signal from a second source RXD WS 1 rw Wake Up Source Select This is applicable only if EWPD is set 0 INTO will terminate power down mode default 1 RXD will terminate power down mode SDSTAT 2 rh Slow Down Status Bit 0 Slow Down Mode is not active ie system clock is not slow down clock 1 Slow Down Mode is active ie system clock is the slow down clock This bit is set or cleared by hardware only 7 5 r reserved returns 0 if read should be written with 0
5. 3 2 3 2 1 General Purpose Registers 3 2 3 3 Program and Data Memory Organisation 3 3 3 3 1 Special function register SYSCON1 3 3 3 3 2 Chip Mod s 3 5 3 3 2 1 Normal Mode 3 6 3 3 2 2 Bootstrap Mode 3 6 3 9 2 3 Pineda cp TL 3 6 3 3 2 4 Software Unlock Sequence 3 8 3 4 Special Function Registers 3 9 4 On Chip Peripheral Components 4 1 4 1 PTT 4 1 4 2 a EPI 4 1 4 2 1 Register Overview 4 2 4 3 Dedicated PONS saca kaau i ie A 4 6 4 4 Port T Port 3 Circuitry reri tarani 4 7 4 4 1 Read Modify Write Feature of Ports 4 8 45 Timers Counters PL LT 4 9 4 5 1 Timer 0and1 4 9 4 5 1 1 Timer 0 and 1 Registers 4 10 4 5 1 2 ps2 4 15 4 5 1 3 Mode 1 4 16 4 5 1 4 4 17 4 5 1 5 paf Em 4 18 4 6 Functional Description of 2 4 19 4 6 1 Feat
6. Infineon C868 technologies On Chip Peripheral Components 4 On Chip Peripheral Components This chapter gives detailed information about all on chip peripherals of the C868 except for the integrated interrupt controller which is described separately in chapter 7 4 1 Ports The C868 has two kinds of ports The first kind is push pull ports instead of the traditional quasi bidirectional ports The ports belonging to this kind is port 1 which is a 5 bit I O port and port which is an eight bit I O port When configured as inputs these ports will be high impedance with Schmitt trigger feature Port 3 is alternate for capture compare functions whereas port 1 has alternate functions for some of the pins The second kind is dedicated ports which are shared by the interrupts timer 2 inputs capture compare hall inputs and analog inputs 4 2 1 0 Ports Port 1 and 3 are push pull ports Port 1 and port can function as normal I O ports which have associated SFRs at address 90 and BO respectively These ports also have alternate functions as listed in Table 4 2 There are three SFRs dedicated for each of these ports The first one is the port latch P1 P3 and second one is direction control register P1DIR P3DIR which is used to set the direction for each pin In P1DIR PSDIR if the bit is set to 0 the respective port pin is an output and 1 means an input After reset by default all the Port 1 and 3 pins are input The thir
7. Vppc ALE BSL LE 1 Vssc P3 6 COUT60 Q C P3 3 C C62 P3 7 CC60 P3 2 COUT62 RESET P3 5 CC61 P1 4 RxD LJ C AN4 P1 3 INT3 Q AN3 P1 1 EXF2 _ VAGND P1 0 TxD C J CCPOS2 INT2 AN2 CCPOS1 T2EX INT1 AN1 GCPOSO T2 INTO ANO Figure 1 4 C88 Pin Configuration P DSO 28 Package top view User s Manual 1 4 V 0 4 2002 01 _ Infineon technologies C868 Introduction 1 3 Pin Definitions and Functions This section describes all external signals of the C868 with its function Table 1 1 Pin Definitions and Functions Symbol Pin Numbers l O Function P P DSO TSSOP 28 38 1 0 12 8 6 4 1 Port 1 P1 4 12 6 11 4 10 3 9 2 8 1 is a 5 bit push pull bidirectional I O port As alternate digital functions port 1 contains the interrupt 3 timer 2 overflow flag receive data input and transmit data output of serial interface The alternate functions are assigned to the pins of port 1 as follows P1 0 TxD Transmit data of serial interface P1 1 EXF2 Timer 2 overflow flag P1 2 P1 3 INT3 Interrupt 3 P1 4 RxD Receive data of serial interface P3 0 2 3 23 32 33 25 P3 7 24 1 26 31 24 22 5 6 36 37 2 32 3 33 23 25 24 26 1 31 22 24 5 36 6 37 I O Port 3 is an 8 bit push pull bidirectional I O port This port also serves as alternate functions for the CCU6 functions The functions are assigned to the pins of
8. Infineon C868 technologies Memory Organization Table 3 7 Contents of the SFRs SFRs in numeric order of their addresses Addr Reg Content Bit7 Bit5 Bit4 Bit2 Bit1 BitO after ister Reset 984 ISCON 00 SMO ISM1 5 2 IREN TB8 RB8 RI 994 SBUF 00 7 6 5 A 3 2 4 0 25 WDTC XXXX WDT ON XX00p RIN A34 IWDTR 00 7 6 5 4 3 2 4 0 EL A64 PSLRL O0Oy PSL63 PSL5 PSL4 PSL3 PSL2 PSL1 PSLO A84 IENO 0 00 2 5 ET1 EX1 ETO EXO 0000p A94 EN1 EX3 EX2 EADC X000p AAW 2 00 EINP3 EINP2 EINP1 EINPO 00XXp XX00 5 4 3 2 1 0 0000p AD SYSC 10 EALE ONO XXX1ip 0 AF 5 5 00 ESWC SWC 2 _ BSLE SWAP ON1 XO0X0p N BO FFy T 6 5 A 3 2 2 0 BO PSDIR FFy 7 6 5 A 3 2 4 0 1 P3ALT 00H CC60 COUT CC61 CC62 COUT CTRA COUT 60 61 62 P 63 B24 WDTL 00H 7 6 5 4 3 2 4 0 B34 WDTH 00 7 6 5 4 3 2 4 0 B44 PM1ALT XXXO E n RxD INT3 EXF2 TxD 0X00p B6 CC63 00 7 6 5 4 3 2 1 0 SRL 1 X means that the value is undefined and the location is reserved 2 This register is mapped with RMAP SYSCONO 4 0 3 This register is mapped with RMAP SYSCONO 4 1 Shaded registers are bit addressable special function registers User s Manual 3 15 V 0 4
9. C868 Interrupt System IENH Capture Compare Interrupt Enable Register High Byte Reset value 00 1 7 6 5 4 3 2 1 0 ENIDLE ENWHE ENCHE ENTRPF ENT13PM ENT13CM r rw rw rw r rw rw rw Field Bits Description ENT13CM 0 rw Enable Interrupt for T13 Compare Match 0 No interrupt will be generated if the set condition for bit T13CM in register IS occurs 1 An interrupt will be generated if the set condition for bit T13CM in register IS occurs The interrupt line which will be activated is selected by bitfield INPT13 ENT13PM 1 rw Enable Interrupt for T13 Period Match 0 No interrupt will be generated if the set condition for bit T13PM in register IS occurs 1 An interrupt will be generated if the set condition for bit T13PM in register IS occurs The interrupt line which will be activated is selected by bitfield INPT13 ENTRPF 2 rw Enable Interrupt for Trap Flag 0 No interrupt will be generated if the set condition for bit TRPF in register IS occurs 1 An interrupt will be generated if the set condition for bit TRPF in register IS occurs The interrupt line which will be activated is selected by bitfield INPERR ENCHE 4 rw Enable Interrupt for Correct Hall Event 0 No interrupt will be generated if the set condition for bit CHE in register IS occurs 1 An interrupt will be generated if the set condition for bit CHE in register IS occurs The interrupt line which
10. Pi Analog Watchdog Timer 8 Bit ADC q Digital Input Figure 1 1 C868 Functional Units User s Manual 1 1 V 0 4 2002 01 _ Infineon C868 technologies Introduction 1 1 Summary of Basic Features Listed below is a summary of the main features of the C868 C800 core Fully compatible to standard 8051 microcontroller Superset of the 8051 architecture with 8 datapointers 6 25 40 MHz internal system clock built in PLL with software configurable divider external clock of 6 67 10 67 MHz 300ns instruction cycle time 40 MHz system clock 8 Kbyte on chip Program ROM for C868 1R and 8 KByte on chip Program RAM for 868 15 In system programming support for programming the XRAM C868 1R XRAM Program RAM C868 1S This feature is realized through 4KB Boot ROM 256 byte on chip RAM 256 byte on chip XRAM One 8 bit and one 5 bits general purpose push pull I O ports Enhanced sink current of 10 mA on Port 1 3 total sink current of 46 mA 9 100 C Three 16 bit timers counters Timer 0 1 Timer counter 2 up down counter feature Timer 1 or 2 can be used for serial baudrate generator Capture compare unit CCU6 for PWM signal generation 3 channel 16 bit capture compare unit 1 channel 16 bit compare unit Full duplex serial interface UART 5 channel 8 bit A D Converter 13 interrupt vectors with 2 priority levels Programmable 16 bit Watchdog Timer
11. RXD Serial Port Interrupt Read SBUF Shit pag TX Control RX Control Input Shift Register q Send RI Load SBUF Shift 9Bits Internal Bus MCS02103 Figure 4 37 Serial Interface Mode 1 Functional Diagram User s Manual 4 108 V 0 4 2002 01 601 jenuew sasn 10 2002 41 epojy eoejieiu V S 86 TX Clock Write to SBUF Data S1P1 TI 16 Reset RX Clock Bit Detector Sample Times RI MCT02104 2 s u uodwo 2 seiBoJouuoe 8989 _ Infineon C868 technologies On Chip Peripheral Components 4 9 3 Details about Modes 2 and 3 Eleven bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On transmission the 9th data bit TB8 can be assigned the value of 0 or 1 On reception the 9th data bit goes into RB8 in SCON The baud rate is programmable to either 1 32 or 1 64 the system frequency in mode 2 When bit SMOD in SFR PCON 7 is set the baud rate is fsvs 32 In mode the baud rate clock is generated by timer 1 which is incremented by a rate of fs 4 12 or by the internal baud rate generator Figure 4 39 shows a functional diagram of the serial port in modes 2 and 3 The receive portion is exactl
12. TRPS T13PM T13C M 1 X means that the value is undefined and the location is reserved 2 This register is mapped with RMAP SYSCONO 4 0 3 This register is mapped with RMAP SYSCONO 4 1 Shaded registers are bit addressable special function registers User s Manual 3 18 V 0 4 2002 01 _ Infineon C868 technologies Memory Organization Table 3 7 Contents of the SFRs SFRs in numeric order of their addresses Addr Reg Content Bit7 Bit5 Bit4 Bit2 Bit1 BitO after ister Reset E64 2 00 DTM5 DTM4 DTM3 DTM2 DTM1 DTMO CL E74 T12DT 00y DTR2 DTR1 DTRO DTE2 DTE1 DTEO CH E84 CCUDI T2DIS ADCDI N1 X000p S S EA CMPM 004 MCC6 MCC6 MCC6 MCC6 ODIFL 3S 2S 1S 0S EB CMPM 004 MCC6 MCC6 MCC6 MCC6 ODIFH 3R 2R 1R OR ECy 121 00 7 6 5 4 3 2 4 0 EDu T12H 00 7 6 5 A 3 2 4 0 EE T13L 00 7 6 5 4 3 2 4 0 EFy T13H 00 7 6 5 4 3 2 4 0 FO B T 6 JS 4 3 2 4 0 F242 TCTR 00 T12ST T12ST DTRE T12RE T12RS T12RR 4L D R S S F24 TCTR 00 T13TE T13TE T13TE 1 T13TE T13SS T12SS 2L D1 DO C2 C1 CO C C F34 TCTR 00 T13ST T13ST T13RE T13RS T13RR 4H D R S F44 5 00 635 625 615 605 TATL T T T T F54 5 00 T13IM COUT COUT CC62P COUT CC61P COUT C
13. U Up Down Count Disabled 4 25 4 26 V VERO 3 20 VER1 3 20 VER2 3 20 VERS 3 20 VER4 3 20 User s Manual 11 V 0 4 2002 01 mn Infineon technologies C868 VER5 3 20 VER6 3 20 VERSI 3 20 VERSION 3 10 W Watchdog timer 6 1 Block diagram 6 1 Input clock selection 6 6 Refreshing of the WDT 6 5 WDT 3 15 WDTC 3 15 WDTCON 3 11 WDTD 3 16 WDTE 3 16 WDTH 3 11 3 15 WDTL 3 11 3 15 WDTR 3 15 3 16 WDTREL 3 11 WHE 3 18 WS 3 14 X XMAP 3 15 User s Manual V 0 4 2002 01 Infineon goes for Business Excellence Business excellence means intelligent approaches and clearly defined processes which are both constantly under review and ultimately lead to good operating results Better operating results and business excellence mean less idleness and wastefulness for all of us more professional Success more accurate information a better overview and thereby less frustration and more satisfaction Dr Ulrich Schumacher http www infineon com Published by Infineon Technologies AG
14. 004 core B B Register 00j DPH Data Pointer High Byte 834 004 DPL Data Pointer Low Byte 824 004 DPSEL Data Pointer Select Register 844 004 PSW Program Status Word Register 00 SP Stack Pointer 814 074 SCON Serial Channel Control Register 98 004 SBUF Serial Data Buffer 994 004 IENO Interrupt Enable Register 0 8 0X000000 IEN1 Interrupt Enable Register 1 A94 XXXXX000g IEN2 Interrupt Enable Register 2 AAH XX0000XXp IPO Interrupt Priority Register 0 B8p XX000000g IP1 interrupt Priority Register 1 ACy 000000 2 Timer 0 1 Control Register 88 004 TMOD Timer Mode Register 894 004 TLO Timer 0 Low Byte 00H TL1 Timer 1 Low Byte 8By 00y THO Timer 0 High Byte 8Cy TH1 Timer 1 High Byte 8Dy 00 PCON Power Control Register 874 0XXX0000p Sys Wake up Control Register XXX00000pg tem CMCON Clock Control Register 9Fy 10011111 EXICON External Interrupt Control Register 914 XXXXXX00p IRCONO External Interrupt Request Register 924 XXXXXX00p IRCON1 Peripheral Interrupt Request Register 934 XXXXXXXO0p PMCON 1 Peripheral Management Ctrl Register E81 XXXXX000p PMCON2 Peripheral Management Status Register F84 000 2 SCUWDT SCU Watchdog Control Register X0X00000g VERSION ROM Version Register F94 00j SYSCONO System Control Register 0 ADy XX10XXX1g SYSCON1 System Control Register 1 AFy
15. 1 0 returns O if read should be written with 0 User s Manual 7 10 V 0 4 2002 01 _ Infineon C868 technologies Interrupt System 7 2 2 Interrupt Request Flags The request flags for the different interrupt sources are located in several special function registers This section describes the locations and meanings of these interrupt request flags in detail TCON Timer 0 1 Control Register Reset value 004 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TFO TRO IE1 IT1 IEO ITO rwh rw rwh rw rwh rw rwh rw The functions of the shaded bits are not described here Field Bits Typ Description ITO 0 rw External interrupt 0 level edge trigger control flag If ITO 0 low level triggered external interrupt 0 is selected If ITO 1 falling edge triggered external interrupt 0 is selected IEO 1 rwh External interrupt 0 request flag Set by hardware when external interrupt O edge is detected Cleared by hardware when processor vectors to interrupt routine IT1 2 rw External interrupt 1 level edge trigger control flag If IT1 0 low level triggered external interrupt 1 is selected If IT1 2 1 falling edge triggered external interrupt 1 is selected IE1 3 rwh External interrupt 1 request flag Set by hardware when external interrupt 1 edge is detected Cleared by hardware when processor vectors to interrupt routine User s Manual 7 11 V 0
16. Brown out detection Power Saving Modes Slow down mode Idle mode be combined with slow down mode Power down mode with wake up capability through INTO or RxD pins Individual power down control for timer counter 2 capture compare unit and A D converter P DSO 28 1 P TSSOP 38 1 packages Temperature ranges SAB C868 1RR SAB C868 1SR SAB C868 1RG SAB C868 1SG T4 0to709 C SAF C868 1RR SAF C868 1SR SAF C868 1RG SAF C868 1SG 40 85 C User s Manual 1 2 V 0 4 2002 01 _ Infineon C868 technologies Introduction Vssp Port 1 5 bit Digital Port 3 8 bit Digital RESET ALE BSL ane ma 5 ADC channels TxD 4 RxD gt 4 External Interrupts Figure 1 2 Logic Symbol User s Manual 1 3 V 0 4 2002 01 _ Infineon technologies C868 Introduction 1 2 Pin Configuration P1 4 RxD Q1 O RESET P1 3 INT3 7 2 1 P3 7 CC60 P1 2 13 P3 6 COUT60 P1 1 EXF2 C 4 G NC NCO 5 1 ALE BSL P1 0 TxD Ld 6 P3 1 CTRAP 7 P3 0 COUT63 NCC 8 1 P3 4 COUT61 Vppp 9 XTAL2 10 1 XTAL1 CCPOSO T2 INTO ANO 1 CCPOS1 T2EX INT1 AN1 C O CCPOS2 INT2 AN2 P3 3 CC62 VAGND P3 2 COUT62 Varer P3 5 CC61 AN3 C NC AN4 C NC NC C NC Figure 1 3 C868 Pin Configuration P TSSOP 38 Package top view P3 4 COUT61 C XTAL2 P3 0 COUT63L IXTAL1 P3 1 CTRAP
17. Register ISR contains the individual interrupt request reset the corresponding flags by software ISRL Capture Compare Interrupt Status Reset Register Low Byte Reset value 004 7 6 5 4 3 2 1 0 RT12PM RT120M RCC62F RCC62R RCC61F RCC61R RCC60F RCC60R Field Bits Description RCC60R 0 w Reset Capture Compare Match Rising Edge Flag 0 No action 1 Bit CC60R in register IS will be reset RCC60F 1 Ww Reset Capture Compare Match Falling Edge Flag 0 No action 1 Bit CC60F in register IS will be reset RCC61R 2 Ww Reset Capture Compare Match Rising Edge Flag 0 No action 1 Bit CC61R in register IS will be reset RCC61F 3 Ww Reset Capture Compare Match Falling Edge Flag 0 No action 1 Bit CC61F in register IS will be reset RCC62R 4 w Reset Capture Compare Match Rising Edge Flag 0 No action 1 Bit CC62R in register IS will be reset RCC62F 5 w Reset Capture Compare Match Falling Edge Flag 0 No action 1 Bit CC62F in register IS will be reset RT120M 6 Ww Reset Timer T12 One Match Flag 0 No action 1 Bit T12OM in register IS will be reset RT12PM 7 Ww Reset Timer T12 Period Match Flag 0 No action 1 Bit T12PM in register IS will be reset User s Manual 7 23 V 0 4 2002 01 mn Infineon C668 technologies Interrupt System Inte
18. Thus the bit times are synchronized to the divide by 16 counter not to the Write to SBUF signal The transmission begins with activation of SEND which puts the start bit at TxD One bit time later DATA is activated which enables the output bit of the transmit shift register to TxD The first shift pulse occurs one bit time after that As data bits shift out to the right zeroes are clocked in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeroes This condition flags the TX control unit to do one last shift and then deactivate SEND and set This occurs at the 10th divide by 16 rollover after Write to SBUF Reception is initiated by a detected 1 to 0 transition at RxD For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1FFy is written into the input shift register and reception of the rest of the frame will proceed The 16 states of the counter divide each bit time into 16ths At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for the noise rejection If the value accepted during the first
19. User s Manual 7 29 V 0 4 2002 01 mn Infineon C668 technologies Interrupt System C code Interrupt Node Pointer Register High Byte Reset value 39 1 7 6 5 4 3 2 1 0 INPT13 INPT12 INPERR r r rw rw rw Field Bits Type Description INPERR 1 0 rw Interrupt Node Pointer for Error Interrupts This bitfield defines the interrupt node which is activated due to a set condition for bit TRPF if enabled by bit ENTRPF or for bit WHE if enabled by bit ENWHE 00 Interrupt node 10 is selected 01 Interrupt node l1 is selected 10 Interrupt node 12 is selected 11 Interrupt node is selected INPT12 3 2 rw Interrupt Node Pointer for Timer12 Interrupts This bitfield defines the interrupt node which is activated due to a set condition for bit T12OM if enabled by bit ENT12OM or for bit T12PM if enabled by bit ENT12PM 00 Interrupt node 10 is selected 01 Interrupt node l1 is selected 10 Interrupt node 12 is selected 11 Interrupt node is selected INPT13 5 4 rw Interrupt Node Pointer for Timer13 Interrupt This bitfield defines the interrupt node which is activated due to a set condition for bit T13CM if enabled by bit ENT13CM or for bit T13PM if enabled by bit ENT13PM 00 Interrupt node 10 is selected 01 Interrupt node l1 is selected 10 Interrupt node 12 is selected 11 Interrupt node is selected 7 6 r reserved returns 0 if
20. 91 90 P1DIR 4 0 r r r rw Field Bits Typ Description P1DIR 4 0 4 0 rw Port 1 Direction Register This SFR appears at address 90 only if bit SYSCONO 4 is 1 0 The associated pin is an output 1 The associated pin is an input default 7 5 r reserved returns 0 if read should be written with 0 User s Manual 4 3 V 0 4 2002 01 mn Infineon technologies C868 P3 Port 3 Register On Chip Peripheral Components Reset value FF B7 B6 B5 B3 B2 1 1 AW 1 Field Bits Typ Description P3 7 0 rw Port 3 Latch This SFR appears at address BO only if bit RMAP SYSCONO 4 is 0 P3DIR Port 3 Direction Register Reset value B7 B6 B5 B3 B2 P3DIR rw Field Bits Typ Description P3DIR 7 0 rw Port 3 Direction Register This SFR appears at address BO only if bit RMAP SYSCONO 4 is 1 0 The associated pin is an output 1 The associated pin is an input default User s Manual 4 4 V 0 4 2002 01 am Infineon C868 technologies On Chip Peripheral Components P1ALT Port 1 Alternate Function Register Reset value XXX00X00g 7 6 5 4 3 2 1 0 P1ALT 4 3 P1ALT 1 0 r r r rw r rw Field Bits Typ Description P1ALT 1 0 1 0 rw Po
21. A D Converter IRCON O EN1 0 verflow TCON 5 IENO 1 CCPOS2 INT2 EX2 PA AN2 EX2 IRCONO 0 IEN1 1 0 IENO 7 Y Bit addressable 4 Request flag is cleared by hardware Highest Priority Level Lowest Priority Level P i n g S e q u e n C Figure 7 2 Interrupt Structure Overview Part 1 User s Manual V 0 4 2002 01 technologies C868 Interrupt System P1 3 INT3 Capture compare interrupt node 0 EXICON 1 YN Bit addressable 4 Request flag is cleared by hardware Highest Priority Level Priority Level O3530coo o05 0o Figure 7 3 User s Manual Interrupt Structure Overview Part 2 V 0 4 2002 01 technologies C868 Interrupt System Timer 1 Overflow Capture compare interrupt node 1 DN Bit addressable d Request flag is cleared by hardware Highest Priority Level Lowest Priority Level gt gt Figure 7 4 Interrupt Structure Overview Part 3 User s Manual V 0 4 2002 01 technologies C868 Interrupt System wm m E SCON O 7 IENO 4 SCON 1 Capture compare interrupt node 2 P EINP2 DN Bit addressable d Request flag is cleared by hardware Highest Priority Level Lowest Priority Level P 0 i n g S e q u e n C IENO 7 Figure 7
22. Active high Set by software and cleared by general reset WDTEOI 3 rw WDT End of Initialization Active high Set by software and cleared by general reset WDTR 4 rwh WDT Reset Indication Bit Active high Set by hardware when a watchdog timer reset occurs Cleared by reset or WDT RFSH or software PLLR 6 rwh PLL Reset Indication Bit Active high Set by hardware when PLL reset occurs Cleared by reset or software 7 5 r reserved returns 0 if read should be written with 0 User s Manual 6 4 V 0 4 2002 01 Infineon C868 technologies Fail Save Mechanism 6 1 2 Starting the Watchdog Timer When the reset input to the Watchdog Timer the Watchdog Timer is enabled Once disabled it cannot be stopped during active mode of the device If the software fails to clear the watchdog timer an internal reset will be initiated The reset cause external reset or reset caused by the watchdog can be examined by software status flag WDTR in SCUWDT is set A refresh of the watchdog timer is done by setting bits WDTRE and WDTRS in SFR SCUWDT consecutively This double instruction sequence has been implemented to increase system security It must be noted however that the watchdog timer is halted during the idle mode and power down mode of the processor see section Power Saving Modes It is not possible to use the idle mode in combination with the watchdog timer function Ther
23. C868 On Chip Peripheral Components Field Bits Type Description STE12 rh Timer T12 Shadow Transfer Enable Bit STE12 enables or disables the shadow transfer of the T12 period value the compare values and passive state select bits and levels from their shadow registers to the actual registers if a T12 shadow transfer event is detected Bit STE12 is cleared by hardware after the shadow transfer A T12 shadow transfer event is a period match while counting up or a one match while counting down 0 The shadow register transfer is disabled 1 The shadow register transfer is enabled CDIR rh Count Direction of Timer T12 This bit is set reset according to the counting rules of T12 0 T12 counts up 1 T12 counts down CTM T12 Operating Mode 0 Edge aligned Mode T12 always counts up and continues counting from zero after reaching the period value 1 Center aligned Mode T12 counts down after detecting a period match and counts up after detecting a one match 1 A concurrent set reset action on T12R from T12SSC T12RR or T12RS will have no effect The bit T12R will remain unchanged Note A write action to the bit fields T12CLK or T12PRE is only taken into account while the timer T12 is not running T12R 0 User s Manual 4 75 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components TCTROH Timer Control Register 0
24. CC6x T12 xST so M120 Cap_xST_so COUT6x T12 xST ro LI DTCx_o dead time generation Figure 4 17 112 Logic for CC6xST Control The events triggering the set and reset action of the CC6xST bits have to be combined see Figure 4 17 The occurrence of the selected capture event signal Cap_xST_so or the setting of CC6xS in register CMPMODIF also leads to a set action of bit CC6xST whereas the negative edge at pin CCPOSx in hysteresis like mode signal hyst_x_ev or the setting of bit CC6xR leads to reset action The set signal is only generated while bit CC6xST is reset a reset can only take place while the bit is set This permits the OR combination of the resulting set and reset signals to one common signal DTOx rl triggering the reload of the dead time counter It is only triggered if bit CC6xST is changed permitting a correct PWM generation with dead time and the complete duty cycle range of 096 to 10096 in edge aligned and in center aligned mode In the case that the dead time generation is enabled the change of bit CC6xST triggers the dead time unit and a signal DTCx_o is generated The length of the 0 level of this signal corresponds to the desired dead time which is used to delay the rising edge passive to active edge of the output signal In order to generate independent PWM patterns for the highside and the lowside switches of the power inverter the interval when a PWM signal should be active can be selected by
25. Fail Save Mechanism Input Clock Selection The period Pyypr between servicing the Watchdog Timer and the next overflow can therefore be determined by the following formula 6 1 WDTIN 6 216 WDTREL 28 sys Pwpr Table 6 1 lists the possible ranges for the watchdog time which can be achieved using a certain module clock Some numbers are rounded to 3 significant digits Table 6 1 Watchdog Time Ranges Reload value Prescaler for fsy in WOTREL 2 WDTIN 0 128 WDTIN 1 40 MHz 20 2 16MHz 40 2 20MHz 16 MHz FF 12 8 us 25 6 us 32 0 us 819 2 us 1 64 ms 2 05 ms 7Fy 1 65 ms 3 8 ms 4 13ms 105 7 ms 211 3 ms 264 ms 004 3 28 ms 6 55 ms 8 19 ms 209 7 ms 419 4 ms 524 ms Note For safety reasons the user is advised to rewrite WDTCON each time before the Watchdog Timer is serviced User s Manual 6 6 V 0 4 2002 01 Infineon C868 technologies Interrupt System 7 Interrupt System The C868 provides 13 interrupt vectors with two priority levels Nine interrupt requests are generated by the on chip peripherals timer 0 timer 1 timer 2 serial channel A D converter and the capture compare unit with 4 interrupts and four interrupts may be triggered externally The wake up from power down mode interrupt has a special functionality which allows the software power down mode to be terminated by a short negative pulse at pins CCPOSO T2
26. Hall pattern d reset T12 Figure 4 34 Hall Logic User s Manual 4 56 V 0 4 2002 01 Infineon C868 technologies On Chip Peripheral Components For Brushless DC motors there is a special mode MSEL6x 710000 which is triggered by a change of the Hall inputs CCPOSx This mode shows the capabilities of the CCU6 see also figures Multi channel Selection and Synchronization Hall Event Actions Modulation Selection and Alternate Output Enable of T12 and Timer T12 Brushless DC Mode Here T12 s channel 0 acts in capture function channel 1 and 2 in compare function without output modulation and the multi channel block is used to trigger the output switching together with a possible modulation of T13 After the detection of a valid Hall edge the T12 count value is captured to channel 0 representing the actual motor speed and resets the T12 When the timer reaches the compare value in channel 1 the next multi channel state is switched by triggering the shadow transfer of bit field MCMP if enabled in bit field SWEN This trigger event can be combined with several conditions which are necessary to implement a noise filtering correct Hall event and to synchronize the next multi channel state to the modulation sources avoiding spikes on the output lines This compare function of channel 1 can be used as a phase delay for the position input to the output switching which is necessary if a sensorless back EMF technique is used i
27. High Byte Reset value 004 7 6 5 4 3 2 1 0 STE13 T13R T13PRE T13CLK r r rh rh rw rw Field Bits Type Description T13CLK 2 0 rw Timer T13 Input Clock Select Selects the input clock for timer T13 which is derived from the peripheral clock according to the equation o T13CLK 000 foer 001 foer 2 010 1143 foer 4 011 ft13 foer 8 100 r43 fpe 16 101 fr135 fer 32 110 fper 64 111 fr15 fper 128 T13PRE 3 rw Timer T13 Prescaler Bit In order to support higher clock frequencies an additional prescaler factor of 1 256 can be enabled for the prescaler for T13 0 The additional prescaler for T13 is disabled 1 The additional prescaler for T13 is enabled T13R 4 rh T13 Run Bit T13R starts and stops timer T13 It is set reset by SW by setting bits T13RR orT13RS or it is set reset by HW according to the function defined by bitfields T13SSC 1 and T13TED 0 Timer T13 is stopped 1 Timer T13 is running User s Manual 4 76 V 0 4 2002 01 _ Infineon technologies C868 On Chip Peripheral Components Field Bits Type Description STE13 rh Timer T13 Shadow Transfer Enable Bit STE13 enables or disables the shadow transfer of the T13 period value the compare value and passive state select bit and level from their shadow registers to the actual registers if a T13 shadow transfer
28. IRCON1 External Interrupt Request Register 1 Reset value XXXXXXX0g 7 6 5 4 3 2 1 0 J IADC r r r r r r r rwh Field Bits Typ Description IADC 0 rwh Interrupt Request Flag for ADC 0 Interrupt request is not active cleared by software default 1 Interrupt request is active set by hardware 7 1 A reserved returns 0 if read should be written with 0 The A D converter interrupt is generated by IADC bit in register IRCON1 If an interrupt is generated in any case the converted result in ADDATH is valid on the first instruction of the interrupt service routine If continuous conversion is established IADC is set once during each conversion If an A D converter interrupt is generated flag IADC will have to be cleared by software User s Manual 7 15 V 0 4 2002 01 _ Infineon C868 technologies Interrupt System SCON Serial Channel Control Register Reset value 00 1 OF 9E 9D 9C 9B 9A 99 98 SMO SM1 SM2 REN TB8 RB8 TI RI rwh rwh rw rw rw rw rwh rwh The functions of the shaded bits are not described here Field Bits Typ Description RI 0 rwh Serial interface receiver interrupt flag Set by hardware if a serial data byte has been received Must be cleared by software Tl 1 rwh Serial interface transmitter interrupt flag Set by hardware at the end of a serial data transmission Must be cleared by software The serial in
29. The functions of the shaded bits are not described here Field Bits Typ Description RMAP 4 rw Special Function Register Map Control RMAP 0 The access to the non mapped standard special function register area is enabled RMAP 1 The access to the mapped special function register area is enabled 7 2 TUR reserved returns 0 if read should be written with 0 As long as bit RMAP is set the mapped special function register area can be accessed This bit is not cleared automatically by hardware Thus when non mapped mapped registers are to be accessed the bit RMAP must be cleared set respectively by software The 109 special function registers SFR include pointers and registers that provide an interface between the CPU and the other on chip peripherals All available SFRs whose address bits 0 2 are 0 e g 804 884 90 F84 are bit addressable Totally there are 128 directly addressable bits within the SFR area All SFRs are listed in Table 3 6 and Table 3 7 In Table 3 6 they are organized in groups which refer to the functional blocks of the C868 1R C868 1S Table 3 7 illustrates the contents bits of the SFRs User s Manual 3 9 V 0 4 2002 01 _ Infineon technologies C868 Memory Organization Table 3 6 Special Function Registers Functional Blocks Block Symbol Name Add Contents ress after Reset C800 ACC Accumulator 0
30. The time required for a reset operation must be at least tbd tbd usec The same considerations apply if the reset signal is generated externally Figure 5 1 b In each case it must be assured that the logics at ALE BSL TXD and other testmode related pins are latched properly b C868 g RESET Figure 5 1 Reset Circuitries A correct reset leaves the processor in a defined state The program execution starts at location 00004 After reset is internally accomplished the port latches of ports 1 defaulted to and they are set to input The contents of the internal RAM and XRAM of the C868 are not affected by a reset After power up the contents are undefined while it remains unchanged during a reset if the power supply is not turned off 5 2 Internal Reset after Power On Figure 5 2 shows the power on sequence For the C868 the device enter into default reset state once RESET has gone low with all I O ports set to input or high impedance The internal reset is released only after the PLL has locked In Figure 5 2 1 the internal reset remains active even after the RESET pin had gone high the I O ports 1 and remain as input In Figure 5 2 1 detection for continuous PLL lock is done before internal reset is released The 4096 cycles of continuous lock detection ensures that a reset due to PLL unlock will not happen during the transient period after the PLL started functioning After continuous PLL loc
31. This especially applies to the serial interface in case it cannot finish reception or transmission during normal operation As in normal operation mode the ports can be used as inputs during idle mode Thus a capture or reload operation can be triggered the timers can be used to count external events and external interrupts will be detected The idle mode is a useful feature which makes it possible to freeze the processor s status either for a predefined time or until an external event reverts the controller to normal operation as discussed below The watchdog timer is the only peripheral which is automatically stopped during idle mode The idle mode is entered by setting the flag bit IDLE 0 There are two ways to terminate the idle mode The idle mode can be terminated by activating any enabled interrupt The CPU operation is resumed the interrupt will be serviced and the next instruction to be executed after the RETI instruction will be the one following the instruction that had set the bit IDLE The other way to terminate the idle mode is a hardware reset User s Manual 8 4 V 0 4 2002 01 _ Infineon C868 technologies Power Saving Modes 8 4 Slow Down Mode Operation In some applications where power consumption and dissipation are critical the controller might run for a certain time at reduced speed e g if the controller is waiting for an input signal Since in CMOS devices there is an almost linear
32. because the selected synchronization condition has not yet occurred reserved returns 0 if read should be written with 0 1 While IDLE 1 bit field MCMP is cleared User s Manual 4 91 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components MCMOUTH Multi Channel Mode Output Register High Byte Reset value 00 1 7 6 5 4 3 2 1 0 CURH EXPH r r rw rw Field Bits Type Description EXPH 2 0 rh Expected Hall Pattern Bitfield EXPH is written by a shadow transfer from bitfield EXPHS The contents is compared after every detected edge at the hall input pins with the pattern at the hall input pins in order to detect the occurrence of the next desired expected hall pattern or a wrong pattern If the current hall pattern at the hall input pins is equal to the bitfield EXPH bit CHE correct hall event is set and an interrupt request is generated if enabled by bit ENCHE If the current hall pattern at the hall input pins is not equal to the bitfields CURH or EXPH bit WHE wrong hall event is set and an interrupt request is generated if enabled by bit ENWHE CURH 5 3 rh Current Hall Pattern Bitfield CURH is written by a shadow transfer from bitfield CURHS The contents is compared after every detected edge at the hall input pins with the pattern at the hall input pins in order to detect the occurrence of the next desired
33. c5 Spa sharpen i Interrupts Long call to Interrupt Interrupt A E are polled Vector Address Routine Figure 7 7 Interrupt Response Timing Diagram User s Manual 7 34 V 0 4 2002 01 Infineon C868 technologies Interrupt System Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in Figure 7 7 then in accordance with the above rules it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine In some cases it also clears the flag that generated the interrupt while in other cases it does not then this has to be done by the user s software The hardware clears the external interrupt flags IEO and IE1 only if they were transition activated The hardware generated LCALL pushes the contents of the program counter onto the stack but it does not save the PSW and reloads the program counter with an address that depends on the source of the interrupt being vectored to as shown in the following Table 7 3 Table 7 3 Interrupt Source and Vectors Interrupt Source Interrupt Vector Interrupt Request Flags Address core connections External Interrupt O 00034 EXO0 IEO Timer 0 Overflow 000
34. expected hall pattern or a wrong pattern If the current hall input pattern is equal to bitfield CURH the detected edge at the hall input pins has been an invalid transition e g a spike 7 6 r reserved returns 0 if read should be written with 0 1 The bits in the bit fields EXPH and CURH correspond to the hall patterns at the input pins CCPOSx x 0 1 2 in the order EXPH 2 EXPH 1 EXPH 0 CURH 2 CURH 1 CURH 0 CCPOS2 CCPOS 1 50 User s Manual 4 92 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components Register MCMCTR contains control bits for the multi channel functionality MCMCTRLL Multi Channel Mode Control Register Reset value 00 1 7 6 5 4 3 2 1 0 SWSYN SWSEL r r rw r rw Field Bits Description SWSEL 2 0 rw Switching Selection Bitfield SWSEL selects one of the following trigger request sources next multi channel event for the shadow transfer from MCMPS to MCMP The trigger request is stored in the reminder flag R until the shadow transfer is done and flag R is cleared automatically with the shadow transfer The shadow transfer takes place synchronously with an event selected in bitfield SWSYN 000 no trigger request will be generated 001 correct hall pattern CCPOSx detected 010 113 period match detected while counting up 011 T12 one match while counting do
35. periods tsync ts tco and twr TApcc is computed with the following formula tapcc Alfsys ts 8 5 adc_clk The sample time ts is configured in periods of the selected internal ADC clock The table below lists the possible combinations DCTC Clock ADC Basic Clock ADSTC Sample Time ts Divider Periods of TVC adc clk STC 0 default 32 32 00 default 2 1 20 20 01 4 10 16 fsys 16 10 8 11 12 12 11 16 User s Manual 4 119 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components Sample Time ts During this time the internal capacitor array is connected to the selected analog input channel and is loaded with the analog voltage to be converted The analog voltage is internally fed to a voltage comparator With beginning of the sample phase the BSY bit in SFR ADCONO is set Conversion Time tco During the conversion time the analog voltage is converted into a 8 bit digital value using the successive approximation technique with a binary weighted capacitor network During an A D conversion also a calibration takes place During this calibration alternating offset and linearity calibration cycles are executed At the end of the calibration time the ADBSY bit is reset and the IADC bit in SFR IRCON1 is set indicating an A D converter interrupt condition Write Result Time twp At the result phase the conversion result is writt
36. technologies C868 On Chip Peripheral Components Field Bits Typ Description THx 7 0 x 0 1 7 0 rwh Timer 0 1 high register Operating Description Mode 0 THx holds the 8 bit timer value 1 THx holds the higher 8 bit part of the 16 bit timer value 2 THx holds the 8 bit reload value 3 THO holds the 8 bit timer value TH1 is not used User s Manual 4 11 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components TCON Power Control Register Reset value 00 1 8Fy 8DH 8CH 8BH 8AH 89H 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO rwh rw rwh rw rwh rw rwh rw The functions of the shaded bits are not described here Field Bits Typ Description TRO 4 rw Timer 0 run control bit Set cleared by software to turn timer 0 ON OFF TFO 5 rwh Timer 0 overflow flag Set by hardware on timer overflow Cleared by hardware when processor vectors to interrupt routine TR1 6 rw Timer 1 run control bit Set cleared by software to turn timer 1 ON OFF TF1 7 rwh Timer 1 overflow flag Set by hardware on timer overflow Cleared by hardware when processor vectors to interrupt routine User s Manual 4 12 V 0 4 2002 01 _ Infineon technologies C868 On Chip Peripheral Components TMOD Timer Regis
37. technologies On Chip Peripheral Components A T12 xST so e homm DI T12 xST se D T12 xST re T12 xST ro JL T12 prescaler fper MSEL6x end OE 0001 or 0010 or 0011 Single Shat made or 1000 ch 1 2 only 5 1 MSEL6x 1001 Figure 4 16 T12 Compare Logic The T12 compare output lines T12 xST so to set bit CC6xST and T12 xST ro to reset bit CC6xST are also used to trigger the corresponding interrupt flags and to generate interrupts The signal T12 5 so indicates the interrupt event for the rising edge ICC6xR whereas the signal T12 xST ro indicates the falling edge event ICC6xF in compare mode The compare state bits indicate the occurrence of a capture or compare event of the corresponding channel It can be set if it is 07 by the following events upon a software set CC6xS upon a compare set event see switching rules if the T12 runs and if the T12 set event is enabled upon a capture set event The bit CC6xST can be reset if it is 1 by the following events upon a software reset CC6xR upon a compare reset event see switching rules if the T12 runs and if the T12 reset event is enabled including in single shot mode the end of the T12 period e upon a reset event in the hysteresis like control mode User s Manual 4 38 V 0 4 2002 01 Infineon technologies C868 On Chip Peripheral Components hyst x state CC6xPS
38. 0 Interrupts This bitfield defines the interrupt node which is activated due to a set condition for bit CC6OR if enabled by bit ENCC60R or for bit CC6OF if enabled by bit ENCC60F 00 Interrupt node 10 is selected 01 Interrupt node 11 is selected 10 Interrupt node 12 is selected 11 Interrupt node is selected INPCC61 3 2 rw Interrupt Node Pointer for Channel 1 Interrupts This bitfield defines the interrupt node which is activated due to a set condition for bit CC61R if enabled by bit ENCC61R or for bit CC61F if enabled by bit ENCC61F 00 Interrupt node 10 is selected 01 Interrupt node l1 is selected 10 Interrupt node 12 is selected 11 Interrupt node is selected INPCC62 5 4 rw Interrupt Node Pointer for Channel 2 Interrupts This bitfield defines the interrupt node which is activated due to a set condition for bit CC62R if enabled by bit ENCC62R or for bit CC62F if enabled by bit ENCC62F 00 Interrupt node 10 is selected 01 Interrupt node l1 is selected 10 Interrupt node 12 is selected 11 Interrupt node is selected INPCHE 7 6 rw Interrupt Node Pointer for the CHE Interrupt This bitfield defines the interrupt node which is activated due to a set condition for bit CHE if enabled by bit ENCHE 00 Interrupt node 10 is selected 01 Interrupt node l1 is selected 10 Interrupt node 12 is selected 11 Interrupt node is selected
39. 11 bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first a programmable 9th bit and a stop bit 1 On transmit the 9th data bit TB8 in SCON can be assigned to the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 On receive the 9th data bit goes into RB8 in special function register SCON while the stop bit is ignored The baud rate is programmable to either 1 32 or 1 64 of the oscillator frequency See section 4 9 3 for more detailed information Mode 3 9 Bit UART Variable Baud Rate 11 bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 In fact mode 3 is the same as mode 2 in all respects except the baud rate The baud rate in mode 3 is variable See section 4 9 3 for more detailed information In all modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in the modes by the incomming start bit if REN 1 The serial interface also provides interrupt requests when transmission or reception of a frames have been completed The corresponding interrupt request flags are or RI resp See chapter 7 of this user manual for more details about the interrupt structure The interrupt request flags Tl and RI can also be used for polling the serial interface if the serial interrupt is not to be
40. 2 1 0 CC6xS15 8 X 0 1 2 rwh Field Bits Typ Description CC6xS x20 1 2 7 0 of rwh Shadow Register for Channel x Capture CC6x Compare Value SL In compare mode the bitfields contents of CC6xS 7 0 of are transferred to the bitfields CC6xV during a CC6x shadow transfer In capture mode the captured SH value of T12 can be read from these registers User s Manual 4 63 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components Register T12DTC controls the dead time generation for the timer T12 compare channels Each channel can be independently enabled disabled for dead time generation If enabled the transition from passive state to active state is delayed by the value defined by bit field DTM The dead time counter can only be reloaded while it is zero T12DTCL Timer T12 Dead Time Control Register Low Byte Reset value 00 1 7 6 5 4 3 2 1 0 DTM r r rw Field Bits Typ Description DTM 5 0 rw Dead Time Bit field DTM determines the programmable delay between switching from the passive state to the active state of the selected outputs The switching from the active state to the passive state is not delayed reserved returns 0 if read should be written with 0 7 6 User s Manual 4 64 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components
41. 2002 01 _ Infineon technologies C868 Memory Organization Table 3 7 Contents of the SFRs SFRs in numeric order of their addresses Addr Reg wis Bit5 Bit4 Bit2 Bit1 BitO after ister Reset B74 CC63 00 7 6 5 4 3 2 ji 0 SRH B84 IPO XX00 5 4 3 2 41 0 0000p BCH 1551 00 ST12P ST120 SCC62 SCC62 SCC62 SCC62 SCC62 SCC62 M M F R F R F R BCH SRL 00 RT12P IRT120 RCCe6e RCC6 RCC6 RCC6 RCC6 RCC6 M M 2F 2R 2F 2R 2F 2R BD ISSH 00 SIDLE SWHE 5 ST13P ST13C F M M BDH ISRH 00 RIDLE RWHE RCHE RT13P RT13C F M M BE IENL 00 ENT12 ENT12 ENCC ENCC PM OM 62F 62R 61F 61R 60F 60R BEY INPL 00 INPCH INPCH INPCC INPCC INPCC INPCC INPCC E 1 E 0 62 1 62 0 61 1 61 0 60 1 60 0 BF 00 ENIDL ENWH ENTR ENT13 ENT13 E E CHE PF PM CM BFH INPH 00 INPT1 INPT1 INPT1 INPT1 INPER INPER 3 1 3 0 2 1 2 0 R 1 R O SCUW 00 l PLLR WDTR WDTE WDTD WDTR WDTR DT Ol IS S E C24 CC60 00 7 6 5 4 3 2 4 0 RL C34 CC60 00 7 6 5 4 3 2 4 0 RH C44 CC61 00 7 6 5 4 3 2 4 0 RL C54 CC61 00 27 6 5 4 3 2 j 0 RH 1 X means that the value is undefined and the location is reserved 2 This register is mapped with RMAP SYSCONO 4 0 3 This register is mapped with RMAP SYSCONO
42. 5 Interrupt Structure Overview Part 4 User s Manual 7 6 V 0 4 2002 01 technologies C868 Interrupt System Timer 2 Overflow CCPOS 1 T2EX lo ot ExF2 INTI AN1 T2CON 6 T2CON 3 Capture compare interrupt node 3 Bit addressable 4 Request flag is cleared by hardware Highest Priority Level Lowest Priority Level gt IENO 7 Figure 7 6 User s Manual Interrupt Structure Overview Part 5 7 7 V 0 4 2002 01 mn Infineon C668 technologies Interrupt System 7 2 Interrupt Registers 7 2 1 Interrupt Enable Registers Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IENO IEN1 IEN2 Register IENO also contains the global disable bit EA which can be cleared to disable all interrupts at once Generally after reset all interrupt enable bits are set to 0 That means that the corresponding interrupts are disabled The SFR IENO contains the enable bits for the external interrupts 0 and 1 the timer interrupts and the UART interrupt IENO Interrupt Enable Register 0 Reset value 0X000000g AF AE ADy ACh ABy A9 A8 EA ET2 ES ET1 EX1 ETO EX0 rw r rw rw rw rw rw rw Field Bits Typ Description EA 0 rw Enable disable all interrupts If EA 0 no interrupt will be acknowledged If E
43. Clock SDD Clock 5 8 5 7 Oscillator and Clock Circuit 5 10 6 Fail Save 6 1 6 1 Programmable Watchdog Timer 6 1 6 1 1 Register Definition of the Watchdog Timer 6 1 6 1 2 Starting the Watchdog 6 5 6 1 3 Refreshing the Watchdog Timer 6 5 6 1 4 Input Clock Selection 6 6 7 Interrupt System 7 1 7 1 Structure of the Interrupt System 7 1 7 2 Interrupt Registers 7 8 7 2 1 Interrupt Enable Registers 7 8 7 2 2 Interrupt Request 0 7 11 7 2 3 Interrupt Control Registers for 7 17 7 2 4 Interrupt Priority Registers 7 31 7 3 Interrupt Priority Level Structure 7 32 7 4 How Interrupts are Handled 7 34 7 5 Interrupt Response 7 37 8 Power Saving Modes 8 1 8 1 Power Saving Mode Control Registers 8 1 8 2 Register Description ___ 8 2 8 3
44. Components Register T12PR contains the period value for timer T12 The period value is compared to the actual counter value of T12 and the resulting counter actions depend on the defined counting rules This register has a shadow register and the shadow transfer is controlled by bit STE12 A read action by SW delivers the value which is currently used for the compare action whereas the write action targets a shadow register The shadow register structure allows a concurrent update of all T12 related values T12PRL Timer T12 Period Register Low Byte Reset value 004 7 6 5 4 3 2 1 0 T12PV7 0 rwh T12PRH Timer T12 Period Register High Byte Reset value 004 7 6 5 4 3 2 1 0 T12PV15 8 rwh Field Bits Typ Description T12PV 7 0 of rwh T12 Period Value T12 The value T12PV defines the counter value for T12 PRL which leads to a period match When reaching this 7 0 of value the timerT12 is set to zero edge aligned T12 mode or changes its count direction to down PRH counting center aligned mode User s Manual 4 61 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components In compare mode the registers CC6xR x 0 1 2 are the actual compare registers for T12 The values stored in CC6xR are compared all three channels in parallel to the counter value of T12 In capture mode the current value of the T12 counter register is captured by reg
45. DC characteristics Nevertheless during the reset calibration phase single or continuous A D can be executed In this case it must be regarded that the reset calibration is interrupted and continued after the end of the A D conversion Therefore interrupting the reset calibration phase by A D conversions extends the total reset calibration time If the specified total unadjusted error TUE has to be valid for an A D conversion it is recommended to start the first A D conversions after reset when the reset calibration phase is finished Depending on the system frequency selected the reset calibration phase can be possibly shortened by setting ADCTC1 and ADCTCO prescaler value to its final value immediately after reset After the reset calibration a second calibration mechanism is initiated This calibration is coupled to each A D conversion With this second calibration mechanism alternatively offset and linearity calibration values stored in the calibration RAM are always checked when an A D conversion is executed and corrected if required User s Manual 4 121 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components User s Manual 4 122 V 0 4 2002 01 _ Infineon C868 technologies Reset and System Clock Operation 5 Reset and System Clock Operation 5 1 Hardware Reset Operation The hardware reset function incorporated in the C868 allows for an easy automatic start up at a minimum of additio
46. INTO ANO or P1 4 RxD The 13 interrupt sources are divided into six groups Each group can be programmed to one of the two interrupt priority levels Additionally 4 of these interrupt sources are channeled from 7 Capture Compare CCU6 interrupt sources 7 1 Structure of the Interrupt System Figure 7 1 to Figure 7 6 give a general overview of the interrupt sources and illustrate the request and control flags which are described in the next sections User s Manual 7 1 V 0 4 2002 01 C868 technologies Interrupt System P3 7 CCO L4 eoe H i E Bl ISL 1 IENL 1 INPL 1 INPL O zl ze P2 5 IS 2 EE T ISL 3 IENL 3 INPL 3 INPL 2 E E 514 TENLA4 Ei ISL 5 IENL 5 INPL 5 INPL 4 T12 T120M One Match lg mum Er ISL 6 T12 T12PM E ni Period Match 507 IENL 7 INPL1 INPL O T13 T13CM 1 Compare HEC 67 Match ISHO TENHO e Period Match TiSPM BN ISH 1 IENH 1 5 INPH 4 TRPF B Le Maite c ISH 2 Wong EE A ISH 5 IENH 5 INPH 1 INPH O ai M ES Hall Even ae ISH4 INPL 7 INPL 6 CCU6 Interrupt node 0 CCU6 Interrupt node 1 CCU6 Interrupt node 2 CCU6 Interrupt node Figure 7 1 Capture Compare module interrupt structure User s Manual 7 2 V 0 4 2002 01 technologies C868 Interrupt System E Z cone fam CCPOS TCON 1 INTO IENO 0 ANO 0
47. Memory Organization Table 3 7 Contents of the SFRs SFRs in numeric order of their addresses Addr Reg Content Bit 7 Bit6 Bit5 Bit4 Bit2 Bit1 Bit O ister after Reset 81 SP 07 7 6 5 4 3 1 0 82 DPL loop 7 6 5 4 3 4 0 DPH jo 7 le 5 4 4 844 DPSE 00 l D2 D1 DO L 874 0 0 SMOD SD GF1 GFO 884 TCON 006 TF1 TRI TRO IE1 IT1 IEO ITO 89 TMOD 004 C NT1 1 1 MO 1 GATE C NTO M1 0 MO 0 0 00H 7 6 5 4 33 2 1 0 8By TL1 7 6 5 4 3 2 4 0 8C ITHO 00 7 6 25 4 3 2 1 0 8Dy TH1 7 6 5 4 3 2 1 0 8E PMCO XXXO EBO SDST WS EPWD NO 0000 1001 2 KDIV1 KDIVO REL4 REL3 REL2 REL1 RELO N 1111p 901 XXX1 4 3 2 1 0 1111p 9049 P1DIR XXX1 4 19 2 1 0 1111 914 ESEL3 ESEL2 N XX00p 924 IRCO XXXX EXINT EXINT NO XX00p 3 2 934 IRCO XXXX IADC N1 XXX0p 1 X means that the value is undefined and the location is reserved 2 This register is mapped with RMAP SYSCONO 4 0 3 This register is mapped with RMAP SYSCONO 4 1 Shaded registers are bit addressable special function registers User s Manual 3 14 V 0 4 2002 01 _
48. OOXXX0X0p 1 Bit addressable special function registers 2 X means that the value is undefined and the location is reserved 3 Register is mapped by bit RMAP in SYSCONO 4 1 4 Register is mapped by bit RMAP in SYSCONO 4 0 User s Manual 3 10 V 0 4 2002 01 _ Infineon technologies C868 Memory Organization Table 3 6 Special Function Registers Functional Blocks cont d Block Symbol Name Add Contents ress after Reset A D ADCONO A D Converter Control Register 0 0000 000 2 Con ADCON1 A D Converter Control Register 1 D94 XXXX0000p verter ADDATH A D Converter Data Register DBy 00y Ports P1 2 Port 1 Register 904 11111 P1DIR Port 1 Direction Register 904 11111 2 Port 3 Register FFy P3DIR gt Port 3 Direction Register FFH P3ALT Port 3 Alternate Function Register 1 00y P1ALT Port 1 Alternate Function Register B44 XXX00X00p Watch WDTCON Watchdog Timer Control Register A2y XXXXXX00p dog WDTREL Watchdog Timer Reload Register A34 00 WDTL Watchdog Timer Low Byte B24 00 WDTH Watchdog Timer High Byte B34 00 Timer T2CON Timer 2 Control Register 00H 2 T2MOD Timer 2 Mode Register C94 XXXXXXX0p RC2H Timer 2 Reload Capture High Byte CBy 00 4 RC2L Timer 2 Reload Capture Low Byte CAy 00 4 T2H Timer 2 High Byte 00 4 T2L Timer 2 Low Byte CCy 00y 1 Bit addressable s
49. RxD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1FFy is written to the input shift register At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 to 0 transition If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bit come from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in modes 2 and 3 is a 9 bit register it flags the RX control block to do one last shift load SBUF and RB8 and to set RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated User s Manual 4 110 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components 1 RI 0 and 2 Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bit goe
50. T13 Trigger Event Direction Bitfield T13TED delivers additional information to control the automatic set of bit T13R in the case that the trigger action defined by T13TEC is detected O0 reserved no action 01 while T12 is counting up 10 while T12 is counting down 11 independent on the count direction of T12 reserved returns 0 if read should be written with 0 1 If the timer T13 is intended to start at any compare event T12 T13TEC 100 the trigger event direction can be programmed to counting up a T12 channel 0 1 2 compare match triggers T13R only while T12 is counting up counting down gt gt a T12 channel 0 1 2 compare match triggers T13R only while T12 is counting down independent from bit CDIR gt gt each T12 channel 0 1 2 compare match triggers T13R The timer count direction is taken from the value of bit CDIR As a result if T12 is running in edge aligned mode counting up only T13 can only be started automatically if bitfield 01 or 7117 User s Manual 4 79 V 0 4 2002 01 Infineon technologies Register TCTR4 allows the SW control of the run bits T12R and T13R by independent set and reset conditions Furthermore the timers can be reset while running and the bits STE12 and STE13 can be controlled by SW C868 On Chip Peripheral Components TCTR4L Timer Control Regist
51. The C868 includes a high performance high speed 8 bit A D Converter ADC with 5 analog input channels It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors The A D converter provides the following features 5 multiplexed input channels which can also be used as digital inputs 8 bit resolution with TUE of 2 LSB8 Single or continuous conversion mode Interrupt request generation after each conversion Using successive approximation conversion technique via a capacitor array Built in calibration of offset and linearity errors Powerdown in normal idle and slow down modes User s Manual 4 114 V 0 4 2002 01 mn Infineon C868 technologies On Chip Peripheral Components 4 10 1 Register Definition of the ADC The ADCONO and ADCON registers are used to configure and control the ADC It also indicates the status of the ADC functions flags ADCONO A D Converter Control Register 0 Reset value 0000X000g 7 6 5 4 3 2 1 0 ADST ADBSY ADM ADCH rw rh rw r rw Field Bits Typ Description ADCH 2 0 rw Analog Input Selection The number of bits implemented depends on the actual number of channels required for the product Bit O of the register shall be the least significant bit ADM 5 4 rw ADC Mode Selection 00 Single Conversion on Fixed Channel default 01 Continuous Conversio
52. additional modulation source for the output signals MODCTRL Modulation Control Register Low Byte Reset value 00 1 7 6 5 4 3 2 1 0 T12MODEN rw r rw Field Bits Type Description T12MODEN 5 0 rw T12 Modulation Enable Setting these bits enables the modulation of the corresponding compare channel by a PWM pattern generated by timer T12 The bit positions are corresponding to the following output signals bit 0 modulation of CC60 bit 1 modulation of COUT60 bit 2 modulation of CC61 bit 3 modulation of COUT61 bit 4 modulation of CC62 bit5 modulation of COUT62 The enable feature of the modulation is defined as follows 0 The modulation of the corresponding output signal by a T12 PWM pattern is disabled 1 The modulation of the corresponding output signal by a T12 PWM pattern is enabled MCMEN 7 rw Multi Channel Mode Enable 0 The modulation of the corresponding output signal by a multi channel pattern according to bitfield MCMOUT is disabled 1 The modulation of the corresponding output signal by a multi channel pattern according to bitfield MCMOUT is enabled User s Manual 4 82 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components Field Bits Type Description 6 r reserved returns 0 if read should be written with 0 MODCTRH Modulation Control Register High
53. base voltage of the transitor approx 0 7 V i e a logic low level and interpret it as 0 For example when modifying a port bit by SETB or CLR instruction another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to th latch However reading the latch rater than the pin will return the correct value of 1 User s Manual 4 8 V 0 4 2002 01 Infineon C868 technologies On Chip Peripheral Components 4 5 Timers Counters The C868 contains three 16 bit timers counters timer 0 timer 1 and timer counter 2 which are useful in many applications for timing and counting The timer register is incremented every machine cycle Thus one can think of it as counting machine cycles Since a machine cycle consists of 12 periods the counter rate is 1 12 of the system frequency 4 5 1 Timer 0 and 1 Timer 0 and 1 of the C868 are fully compatible with timer 0 and 1 can be used in the same four operating modes Mode 0 8 bit timer with a divide by 32 prescaler Mode 1 16 bit timer Mode 2 8 bit timer with 8 bit auto reload Mode 3 Timer 0 is configured as two 8 bit timers Timer 1 in this mode holds its count The effect is the same as setting TR1 0 External inputs INTO and INT1 can be programmed to function as a gate for timer 0 and 1 to facilitate pulse width measurements Each timer consists of two 8 bit registers THO and TLO for timer 0 TH1 and TL1 f
54. be implemented to suppress spikes on the Hall inputs due to high di dt in rugged inverter environment In case of a Hall event the DTCO is reloaded and starts counting When the counter value of one is reached the CCPOSx inputs are sampled without noise and spikes and are compared to the current Hall pattern CURH and to the expected Hall pattern EXPH If the sampled pattern equals to the current pattern the edge on CCPOSx was due to a noise spike and no action will be triggered implicit noise filter If User s Manual 4 55 V 0 4 2002 01 mn Infineon C868 technologies On Chip Peripheral Components the sampled pattern equals to the next expected pattern the edge on CCPOSx was a correct Hall event the bit CHE is set which causes an interrupt and the resets T12 for speed measurement see description mode 1000 below This correct Hall event can be used as a transfer request event for register MCMOUTS The transfer from MCMOUTS to MCMOUT transfers the new CURH pattern as well as the next EXPH pattern In case of the sampled Hall inputs were neither the current nor the expected Hall pattern the bit WHE wrong Hall event is set which also can cause an interrupt and sets the IDLE mode clearing MCMP modulation outputs are inactive To restart from IDLE the transfer request of MCMOUTS have to be initiated by software bit STRHP and bitfields SWSEL SWSYN write by software 6 V DTCO 1o N _1 R int_event
55. blocked by any of the following conditions An interrupt of equal or higher priority is already in progress The current polling cycle is not in the final cycle of the instruction in progress The instruction in progress is RETI or any write access to registers IENO IEN1 or IPO Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IENO IEN1 or IPO then at least one more instruction will be executed before any interrupt is vectored to this delay guarantees that changes of the interrupt status can be observed by the CPU The polling cycle is repeated with each machine cycle and the values polled are the values that were present at S5P2 of the previous machine cycle Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned or if the flag is no longer active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle interrogates only the pending interrupt requests The polling cycle LCALL sequence is illustrated in Table 7 7 c1 gt 2 c3 P
56. branch logic enables internal and external events to the processor to cause a change in the program execution sequence Additionally to the CPU functionality of the 8051 standard microcontroller the C868 contains 8 datapointers For complex applications with peripherals located in the external data memory space or extended data storage capacity this turned out to be a bottle neck for the 8051 s communication to the external world Especially programming in high level languages PLM51 C51 PASCAL51 requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages Accumulator ACC is the symbol for the accumulator register The mnemonics for accumulator specific instructions however refer to the accumulator simply as A Program Status Word The Program Status Word PSW contains several status bits that reflect the current state of the CPU User s Manual 2 3 V 0 4 2002 01 _ Infineon technologies C868 Fundamental Structure PSW Program Status Word Register Reset value 00 1 D7y D6j D5y D4y D3y D24 Diy DOH CY AC FO RS1 RSO OV F1 P rwh rwh rw rw rw rwh rw rwh Field Bits Typ Description P 0 rwh Parity Flag Set cleared by hardware after each instruction to indicate an odd even number of one bits in the accumulator i e even parity F1 1 rw General Purpose F
57. conversions is not affected by its operation Further the user program has no control over the calibration mechanism The calibration itself executes two basic functions Offset calibration correction of offset errors of comparator and the capacitor network Linearity calibration correction of the binary weighted capacitor network The A D converter calibration operates in two phases First phase is the calibration after a reset operation and the second is the calibration at each A D conversion The calibration phases are controlled by a state machine in the A D converter This state machine executes the calibration phases and stores the calibration results dynamically in a small calibration RAM After a reset operation the A D calibration is automatically started This reset calibration phase alternating offset and linearity calibration is executed For achieving a proper reset calibration the fapc prescaler value must satisfy the condition fapc max 2 MHz If this condition is not met at a specific system frequency with the default prescaler value after reset the fApc prescaler must be adjusted immediately after reset by setting bits ADCTC1 and ADCTCO in SFR ADCON1 to a suitable value It is also recommended to have the proper voltages as specified in the DC specifications applied at the and Pins before the reset calibration has started After the reset calibration phase the A D converter is calibrated according to its
58. group of interrupt sources can be programmed individually to one of two priority levels by setting or clearing one bit in the special function register IPO A low priority interrupt can be interrupted by a high priority interrupt but not by another interrupt of the same or a lower priority An interrupt of the highest priority level cannot be interrupted by another interrupt source If two or more requests of different priority levels are received simultaneously the request of the highest priority is serviced first If requests of the same priority level are received simultaneously an internal polling sequence determines which request is to be serviced first Thus within each priority level there is a second priority structure determined by the polling sequence This is illustrated in Table 7 2 User s Manual 7 32 V 0 4 2002 01 _ Infineon C868 technologies Interrupt System Table 7 2 Interrupt Source Structure Interrupt Priority Bits Interrupt Source Priority Priority Group of Interrupt Group High Priority Low Priority 0 0 0 IADC High 1 IPO 1 TFO EXINT2 2 IPO 2 EXINT1 EXINT3 INPO 3 0 3 TF1 INP1 4 0 4 RI TI INP2 Low 5 5 TF2 INP3 1 Capture compare has 10 interrupt sources channeled to the 4 interrupt nodes INPO 3 The 3 capture compare ports has pairs of interrupt request flags ICC60R ICC60F ICC61R ICC61F ICC62R ICC62F The
59. input channel 0 to the ADC unit RESET 7 38 RESET A low level on this pin for two machine cycle while the oscillator is running resets the device ALE BSL 4 34 lO Address Latch Enable Bootstrap Mode A high level on this pin during reset allows the device to go into the bootstrap mode After reset this pin will output the address latch enable signal The ALE can be disabled by bit EALE in SFR SYSCONO Vssp 14 10 IO Ground 0V Vppp 13 9 IO Power Supply 3 3 Vssc 25 27 Core Ground 0V Vppc 26 28 Core Power Supply 2 5 l Input O Output User s Manual V 0 4 2002 01 _ Infineon technologies C868 Introduction Table 1 1 Pin Definitions and Functions Symbol Pin Numbers l O Function P P DSO TSSOP 28 38 NC 5 7 8 18 Not connected 1920 21 22 23 35 XTAL1 27 29 XTAL1 Output of the inverting oscillator amplifier XTAL2 28 30 O XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generation circuits To drive the device from an external clock source XTAL2 should be driven while XTAL1 is left unconnected l Input O Output User s Manual V 0 4 2002 01 Infineon C868 technologies Introduction User s Manual 1 8 V 0 4 2002 01 _ Infineon C868 technologies Fundamental Structure 2 Fundamental Structure The C868 is fully compatible to the architecture of the standard 8051 microcontrol
60. is completed the interrupt request is asserted and the 8 bit result is transferred to the result register ADDATH In continuous conversion mode bit field ADM is set to 1 In this mode the ADC repeatedly converts the channel specified by ADCH Bit ADST is cleared at the beginning of the first conversion The busy flag ADBSY is asserted until the last conversion is completed At the end of each conversion the interrupt request will be asserted To stop conversion ADM has to be reset by software If the channel number ADCH is changed while continuous conversion is in progress the new channel specified will be sampled in the conversions that follow A new request to start conversion will be allowed only after the completion of any conversion that is in progress 4 10 4 Module Powerdown The ADC is disabled when the chip goes into the powerdown mode as describe in Or it can be individually disabled by setting ADCDIS in register PMCON1 This helps to reduce current consumption in the normal slow down and idle modes of operation if the ADC is not utilized Bit ADCST in register PMCON2 reflects the powerdown status of ADC f the ADC is disabled during an A D conversion ADC will be disabled ADCST 1 only after the conversion is completed Note Generally before entering the power down mode an A D conversion in progress must be stopped If a single A D conversion is running it must be terminated by polling the ADBSY bit or waiting fo
61. of a typical bit latch and I O buffer which is the core of the l O ports The bit latch one bit in the port s SFR is represented as a type D flip flop which will clock in a value from the internal bus in response to a write to latch signal from the CPU The Q output of the flip flop is placed on the internal bus in response to a read latch signal from the CPU The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU Some instructions that read from a port i e from the corresponding port SFR P1 and P3 activate the read latch signal while others activate the read pin signal Figure 4 1 shows a functional diagram of a port latch with alternate function Alternate Read Output Function Latch Int Bus Port Driver Write Circuit to Latch Read Alternate Pin Input Function Figure 4 1 Ports 1 and 3 User s Manual 4 7 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components 4 4 1 Read Modify Write Feature of Ports Some port reading instructions read the latch and others read the pin The instructions reading the latch rather than the pin read a value possibly change it and then rewrite it to the latch These are called read modify write instructions which are listed in 4 3 If the destination is a port or a port pin these instructions read the latch rather than the pin Note that all other instructions which can be use
62. setting of bit CC6xST is only possible while CCPOSx 1 hyst x state CCPOSx in i edge detection F MSEL6x 1001 Figure 4 25 Hysteresis Like Control Mode Logic User s Manual 4 46 V 0 4 2002 01 Infineon C868 technologies On Chip Peripheral Components 4 7 2 Timer T13 4 7 2 1 Overview The timer T13 is built similar to T12 but only with one channel in compare mode The counter can only count up similar to the edge aligned mode of T12 The T13 shadow transfer in case of a period match is enabled by bit STE13 in register TCTRO During the T13 shadow transfer the contents of register CC63SR is transferred to register CC63R Both registers can be read by SW whereas only the shadow register can be written by SW The bits CC63PS T13IM and PSL63 have shadow bits The contents of the shadow bits is transferred to the actually used bits during the T13 shadow transfer Write actions target the shadow bits read actions deliver the value of the actually used bit zero match period match counter register T13 Figure 4 26 T13 Overview Timer T13 counts according to the same counting and switching rules as timer T12 in edge aligned mode User s Manual 4 47 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components 4 7 2 0 Compare Mode The compare structure of T13 is based on the compare signals T13 ST se compare match detected and T13 ST re zero match detecte
63. switching of the clock is performed without spurious or shortened clock pulses when software changes the divider factor KDIV However special attention has to be paid concerning the effect of such a clock change to the various modules in the system 5 5 3 Determining the PLL Clock Frequency This section gives the formulas for the determination of the PLL clock frequency In PLL operation the PLL clock is derived from the VCO frequency fyco divided by the K factor fyco is generated from the external clock multiplied by 15 The PLL clock frequency fp be made proportional to the ratio 15 where bit field CMCON KDIV determines the clock scale factor K The VCO output frequency is determined by 15 Ofosc 5 2 and the resulting PLL clock is determined by 15 fet p 2 0 5 3 Since stable operation of the VCO is only guaranteed if remains inside of the defined frequency range for the VCO see Equation 5 1 the external frequency fosc is also confined to certain ranges Table 5 1 list the range User s Manual 5 6 V 0 4 2002 01 _ Infineon technologies C868 Reset and System Clock Operation Table 5 1 Input Frequencies and N Factorz15 for fyco Nco 100 MHz 160 MHz 6 67 10 67 Table 5 2 Output Frequencies fp Derived from Various Output Factors K Factor fPLL Duty Jitter Selected KDIV fvco fvco Cy
64. the bits CC6xPS They select if the PWM signal is active while the compare state bit is 0 T12 counter value below the compare value or while it is 1 T12 counter value above the compare value User s Manual 4 39 V 0 4 2002 01 mn Infineon C868 technologies On Chip Peripheral Components In Figure 4 17 the signals CC6x_T12_0 and COUT6x_T12_0 are inputs to the modulation control block where they can be combined with other PWM signals 4 7 1 6 Switching Examples in edge aligned Mode The following figure shows two switching examples in edge aligned mode with duty cycles near to 0 and near to 100 The compare period or zero matches lead to modifications of the compare state and the shadow transfer if requested by STE12 1 in the next clock cycle 12 12 2 compare match period match zero match period match zero match CDIR 1 0 1 0 STE12 lt T12P 3 0 T12P T12P CC6x ooo compare active passive active state T12 shadow transfer lt T12 shadow transfer Figure 4 18 Switching Examples in edge aligned Mode 4 7 1 7 Switching Examples in center aligned Mode The following figures show examples of the switching of the compare state and the T12 shadow transfer according to the programmed compare values User s Manual 4 40 V 0 4 2002 01 Infineon technologies C868 On Chip Per
65. used i e serial interrupt not enabled User s Manual 4 100 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components Multiprocessor Communication Modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received The 9th one goes into RB8 Then comes a stop bit The port can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON A way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming The slaves that weren t being addressed leave their SM2s set and go on about their business ignoring the incoming data bytes SM2 can be used in mode 1 to check the validity of the stop bit In a mode 1 reception if SM2 1 the receive interrupt will not be activated unless a valid stop bit is received Serial Po
66. value of T13 and the resulting counter actions depend on the defined counting rules This register has a shadow register and the shadow transfer is controlled by bit STE13 A read action by SW delivers the value which is currently used for the compare action whereas the write action targets a shadow register The shadow register structure allows a concurrent update of all T13 related values T13PRL Timer T13 Period Register Low Byte Reset value 004 7 6 5 4 3 2 1 0 T13PV7 0 rwh T13PRH Timer T13 Period Register High Byte Reset value 004 7 6 5 4 3 2 1 0 T13PV15 8 rwh Field Bits Typ Description T13PV 7 0 of rwh T13 Period Value T13L The value T13PV defines the counter value for T13 7 0 of which leads to a period match When reaching this T13H value the timer T13 is set to zero User s Manual 4 67 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components Registers CC63R is the actual compare register for T13 The values stored in CC63R is compared to the counter value of T13 The register CC63R can only be read by SW the modification of the value is done by a shadow register transfer from register CC63SR The corresponding shadow register CC63SR can be read and written by SW CC63RL Compare Register for Channel CC63 Low Byte Reset value 004 7 6 5 4 3 2 1 0 CC63V7 0 rh CC63RH Compare Registe
67. will be activated is selected by bitfield INPCHE User s Manual 7 27 V 0 4 2002 01 _ Infineon technologies C868 Interrupt System Field Bits Description ENWHE 5 rw Enable Interrupt for Wrong Hall Event 0 No interrupt will be generated if the set condition for bit WHE in register IS occurs 1 An interrupt will be generated if the set condition for bit WHE in register IS occurs The interrupt line which will be activated is selected by bitfield INPERR ENIDLE 6 rw Enable Idle This bit enables the automatic entering of the idle state bit IDLE will be set after a wrong hall event has been detected bit WHE is set During the idle state the bitfield MCMP is automatically cleared 0 The bit IDLE is not automatically set when a wrong hall event is detected 1 The bit IDLE is automatically set when a wrong hall event is detected 3 7 r reserved returns O if read should be written with 0 Registers INPL and INPH contains the interrupt node pointer bits allowing for flexible interrupt handling INPL Capture Compare Interrupt Node Pointer Register Low Byte Reset value 404 7 6 5 4 3 2 1 0 INPCHE INPCC62 INPCC61 INPCC60 rw rw rw rw User s Manual 7 28 V 0 4 2002 01 mn Infineon technologies C868 Interrupt System Field Bits Type Description INPCC60 1 0 rw Interrupt Node Pointer for Channel
68. 00 CMPSTATH Timer Status High Byte F54 00 CMPMODIFL Compare Timer Modification Low Byte 00 CMPMODIFH Compare Timer Modification High Byte 00 4 TCTROL Timer Control Register 0 Low Byte E24 00 TCTROH Timer Control Register 0 High Byte E34 00 TCTR2L Timer Control Register 2 Low Byte F24 00 TCTR4L Timer Control Register 4 Low Byte F24 0y TCTR4H Timer Control Register 4 High Byte F34 00 ISL Cap Com Interrupt Register Low Byte 4 00 ISH Cap Com Interrupt Register High Byte E5 00 ISSL Cap Com Int Status Set Reg Low Byte BCy 00 ISSH Cap Com Int Status Set Reg High Byte 00 ISRL Cap Com Int Status Reset Reg Low Byte BCy 00 ISRH Cap Com Int Status Reset Reg High Byte BD 00 1 Bit addressable special function registers 2 X means that the value is undefined and the location is reserved 3 Register is mapped by bit RMAP in SYSCONO 4 1 4 Register is mapped by bit RMAP in SYSCONO 4 0 User s Manual 3 12 V 0 4 2002 01 _ Infineon technologies C868 Memory Organization Table 3 6 Special Function Registers Functional Blocks cont d Block Symbol Name Add Contents ress after Reset Cap INPL Cap Com Int Node Ptr Reg Low Byte BEy 40 ture INPH Cap Com Int Node Ptr Reg High Byte BFy 39 Com IENL Cap Com Interrupt Register Low Byte BE 00 pare IENH Cap Com Interrupt Re
69. 00p A dedicated 4 Kbyte boot ROM is implemented to support this function The actual code inside the boot ROM could be made up of various components such as programming code for RAM module download code initialization routines or diagnostic software The bootstrap mode can be entered via one of the possible ways hardware start up sequence or software entry using special unlock sequence The exit from the bootstrap mode is possible via one of the possible ways hardware reset or software using special unlock sequence The memory mapping for this mode is shown in the Table 3 3 Table 3 3 Bootstrap Memory Configuration for C868 1R Memory Space Memory Boundary Code Space Boot ROM 0000 to OFFFy Internal Data Space XRAM FF00 to FFFFy ROM RAM 00004 to 1FFFy Once in the bootstrap mode the on chip XRAM is always enabled irrespective of the XMAPO bit in SFR SYSCONO Exiting the bootstrap mode via software the on chip XRAM access returns to the state prior to entering this mode depending on XMAPO 3 3 2 3 Modes In the XRAM modes code and data memory are swapped and in this case the code can be fetched from the data space This is useful for running diagnostic software The entry and exit into this mode is always through the special software unlock sequence The XRAM mode could be entered from either the normal mode or the User s Manual 3 6 V 0 4 2002 01 _ Infineon C868 technologie
70. 1 9 Capture 4 43 4 7 1 10 Single Shot Mode 4 44 4 7 1 11 Hysteresis Like Control Mode 4 46 4 7 2 Mu Spo 4 47 4 7 2 1 Ro a A 4 47 4 7 2 2 Compare 4 48 4 7 2 3 Single Shot Mode 4 49 4 7 2 4 Synchronization 1 12 4 49 4 7 3 Multi channel Mode 4 50 4 7 4 Trap Handling NOTTE 4 52 4 7 5 Modulation 4 53 4 7 6 Hall Sensor Mode 4 55 4 7 7 Interrupt Generation 4 58 4 7 8 Module Powerdown 4 58 4 8 Kernel Description 4 59 4 8 1 Register Overview 4 59 4 8 2 Timer12 Related Registers 4 59 4 8 3 Timer13 Related Registers 4 66 4 8 4 Modulation Control Registers 4 82 4 8 4 1 Global Module 4 82 4 8 4 2 Multi Channel Control 4 88 4 9 Serial Interface 4 100 4 9 1 Baud Rate Generation
71. 16 SWSE 3 17 SWSY 3 17 SYSC 3 15 SYSCONO 3 10 SYSCON1 3 10 T T12CL 3 18 T12DT 3 19 T12DTCH 3 12 T12DTCL 3 12 T12H 3 12 3 19 T12L 3 12 3 19 T12M 3 17 3 19 T12MSELH 3 13 T12MSELL 3 13 User s Manual V 0 4 2002 01 mn Infineon technologies C868 120 3 18 T12PM 3 18 T12PR 3 18 T12PRH 3 12 T12PRL 3 12 T12R 3 18 T12RE 3 19 T12RR 3 19 T12RS 3 19 T12SS 3 19 T12ST 3 19 T13C 3 18 T13CL 3 18 T13H 3 12 3 19 1 3 19 T13L 3 12 3 19 T13M 3 18 T13PM 3 18 T13PR 3 17 T13PRH 3 12 T13PRL 3 12 T13R 3 18 T13RE 3 19 T13RR 3 19 T13RS 3 19 T13SS 3 19 T13ST 3 19 T13TE 3 19 T2CO 3 17 T2CON 3 11 T2DIS 3 19 T2H 3 11 T2L 3 11 T2MO 3 17 T2MOD 3 11 T2ST 3 20 TB8 3 15 4 101 TCLK 3 17 TCON 3 10 3 14 TCTR 3 18 3 19 TCTROH 3 12 TCTROL 3 12 TCTR2L3 3 12 User s Manual 10 V 0 4 2002 01 _ Infineon technologies C868 TCTR4H4 3 12 TCTR4L4 3 12 TFO 3 14 7 12 TF1 3 14 7 12 TF2 3 17 THO 3 10 3 14 TH1 3 10 3 14 TH2 3 17 TI 3 15 4 101 Timer counter 4 9 Timer counter 0 and 1 4 9 Mode 0 13 bit timer counter 4 15 Mode 1 16 bit timer counter 4 16 Mode 2 8 bit rel timer counter 4 17 Mode 3 two 8 bit timer counter 4 18 Registers 4 10 4 15 TLO 3 10 3 14 TL1 3 10 3 14 TL2 3 17 TMOD 3 10 3 14 TRO 3 14 TR1 3 14 TR2 3 17 TRPO 3 17 TRP1 3 17 TRP2 3 17 TRPC 3 17 TRPCTRH 3 13 TRPCTRL 3 13 TRPE 3 17 TRPF 3 18 TRPS 3 18 TxD 3 15
72. 2 1 0 T13STD T13STR T13RES T13RS T13RR r r r Field Bits Type Description T13RR 0 w Timer T13 Run Reset Setting this bit resets the T13R bit 0 T13R is not influenced 1 T13R is cleared T13 stops counting T13RS 1 13 Setting this bit sets the T13R bit 0 T13R is not influenced 1 T13R is set T13 starts counting T13RES 2 w Timer T13 Reset 0 No effect on T13 1 The T13 counter register is reset to zero The switching of the output signals is according to the switching rules Setting of TT 3RES has no impact on bit T13R T13STR 6 Ww Timer T13 Shadow Transfer Request 0 No action 1 STE13 is set enabling the shadow transfer T13STD 7 w Timer T13 Shadow Transfer Disable 0 No action 1 STE13 is reset without triggering the shadow transfer 5 3 r reserved returns 0 if read should be written with 0 Note A simultaneous write of a 1 to bits which set and reset the same bit will trigger no action The corresponding bit will remain unchanged User s Manual 4 81 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components 4 8 4 Modulation Control Registers 4 8 4 4 Global Module Control Register MODCTR contains control bits enabling the modulation of the corresponding output signal by PWM pattern generated by the timers T12 and T13 Furthermore the multi channel mode can be enabled as
73. 4 1 Shaded registers are bit addressable special function registers User s Manual 3 16 V 0 4 2002 01 _ Infineon C868 technologies Memory Organization Table 3 7 Contents of the SFRs SFRs in numeric order of their addresses Addr Reg ele Bit6 Bit5 Bit4 Bit2 Bit1 BitO after ister Reset C64 62 004 7 6 5 4 3 2 4 0 RL C74 CC 62 004 7 6 5 4 3 2 4 0 RH C84 T2CO 00 TF2 EXF2 RCLK TCLK EXEN TR2 C T2 CP N 2 RL2 C94 T2MO XXXX DCEN D XXX0p CA RC2L lon 7 6 5 2 1 fo CBy RC2H 00 7 6 19 4 E 2 0 TL2 lo 7 6 5 4 3 2 0 CDy TH2 00 7 6 5 4 3 2 4 0 TRPC 004 l TRP2 TRP1 TRPO TRL CFy TRPC 00 TRPE TRPE TRH N N13 5 N4 N3 N2 N1 No DO PSW 004 AC FO RS1 RSO F1 P Da T1i3PRioo 7 6 5 4 3 gt 1 L H3PRlO 7 6 5 4 3 2 1 fo H cce3 lo 7 6 5 B3 2 1 fo RL D54 CC63 00 17 6 5 4 E 2 4 0 RH D62 MCMC O0 l SWSY SWSY SWSE SWSE SWSE TRLL N1 NO L2 L1 LO D6 IMODC 00 MCME T12M 12 12 T12M 12 T12M TRL N ODEN ODEN ODEN ODEN ODEN 5 4 3 2 1 0 1 X means that the value is undefined and the location is reserved 2 This register is mapped with RMAP SYSCONO 4 0 3 This register is mapped with RMA
74. 4 2002 01 _ Infineon C868 technologies Interrupt System Field Bits Typ Description TFO 5 rwh Timer 0 overflow flag Set by hardware on timer counter 0 overflow Cleared by hardware when processor vectors to interrupt routine TF1 7 rwh Timer 1 overflow flag Set by hardware on timer counter 1 overflow Cleared by hardware when processor vectors to interrupt routine The timer 0 and timer 1 interrupts are generated by TFO and TF1 in register TCON which are set by a rollover in their respective timer counter registers When a timer interrupt is generated the flag that generated it is cleared by the on chip hardware when the service routine is vectored to The external interrupts 0 and 1 CCPOSO T2 INTO ANO CCPOS1 T2EX INT1 AN1 can each be either level activated or negative transition activated depending on bits ITO and IT1 in register TCON The flags that actually generate these interrupts are bits IEO and IE1 in TCON When an external interrupt is generated the flag that generated this interrupt is cleared by the hardware when the service routine is vectored to but only if the interrupt was transition activated If the interrupt was level activated then the requesting external source directly controls the request flag rather than the on chip hardware IRCONO External Interrupt Control Register 0 Reset value XXXXXX00g 7 6 5 4 3 2 1 0 EXINT3 EXINT2 r r r
75. 68 On Chip Peripheral Components 4 10 2 PMCON1 Peripheral Management Control Register Reset value XXXXX000g 7 6 5 4 2 1 0 CCUDIS T2DIS ADCDIS r r r r rw rw rw The functions of the shaded bits are not described here Field Bits Typ Description ADCDIS 0 rw ADC Disable Request 0 ADC will continue normal operation default 1 Request to disable the ADC is active PMCON2 Peripheral Management Status Register Reset value XXXXX000g 7 6 5 4 2 1 0 CCUST T2ST ADCST r r r r r rh rh rh The functions of the shaded bits are not described here Field Bits Typ Description ADCST 0 rh ADC Disable Status 0 ADC is not disabled default 1 ADC is disabled clock is gated off User s Manual 4 117 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components 4 10 3 Operation of the ADC The ADC supports two conversion modes single and continuous conversions For each mode there are two ways in which conversion can be started by software Writing a 1 to bit field ADST starts conversion on the channel that is specified by ADCH In single conversion mode bit field ADM is cleared to 0 This is the default mode selected after hardware reset When a conversion is started the channel specified is sampled The busy flag ADBSY is set and ADST is cleared When the conversion
76. 68 technologies On Chip Peripheral Components C T2 0 6 C T2 1 9 T2 Overflow Timer 2 Interrupt T2bEX Figure 4 6 Auto Reload Mode 0 4 6 5 2 Up Down Count Enabled If DCEN 1 the up down count selection is enabled The direction of count is determined by the level at input pin T2EX The operational block diagram is shown in Figure 4 7 A logic 1 at pin T2EX sets the timer counter 2 to up counting mode The timer counter therefore counts up to a maximum of FFFFy Upon overflow bit TF2 is set and the timer counter registers are reloaded with a 16 bit reload of the RC2L H registers A fresh count sequence is started and the timer counts up from this reload value as in the previous count sequence This reload value is chosen by software prior to the occurrence of an overflow condition A logic 0 at pin T2EX sets the timer counter 2 to down counting mode The timer counter counts down and underflows when the T2L H value reaches the value stored at registers User s Manual 4 26 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components RC2L H The underflow condition sets the TF2 flag and causes FFFFy to be reloaded into the T2L H registers A fresh down counting sequence is started and the timer counter counts down as in the previous counting sequence In this mode bit EXF2 toggles whenever an overflow or an underflow condition is detected This flag h
77. 868 technologies Power Saving Modes 8 5 Software Power Down Mode In the software power down mode the on chip oscillator which operates with the XTAL pins and the PLL are all stopped Therefore all functions of the microcontroller are stopped and only the contents of the on chip RAM XRAM and the SFR s are maintained The port pins which are controlled by their port latches output the values that are held by their SFR s The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power down mode ALE is held at logic level high unless it is disabled In the power down mode of operation and Vppp can be reduced to minimize power consumption It must be ensured however that and is not reduced before the power down mode is invoked and that and is restored to its normal operating level before the power down mode is terminated However Vpoc cannot be lower than Voor by more than 1 tbd volt The software power down mode can be left either by an active reset signal or by a low signal at one of the wake up source pins Using reset to leave power down mode puts the microcontroller with its SFRs into the reset state Using either the INTO pin or the RXD pin for power down mode exit starts the on chip oscillator and the PLL and maintains the state of the SFRs which have been frozen when power down mode is entered Leaving power dow
78. A 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit ET2 1 rw Timer 2 overflow external reload interrupt enable If ET2 0 the timer 2 interrupt is disabled If ET2 1 the timer 2 interrupt is enabled ES 2 rw Serial channel UART interrupt enable If ES 0 the serial channel interrupt 0 is disabled If ES 1 the serial channel interrupt O is enabled ET1 3 rw Timer 1 overflow interrupt enable If ET1 0 the timer 1 interrupt is disabled If ET1 2 1 the timer 1 interrupt is enabled EX1 4 rw External interrupt 1 enable If EX1 0 the external interrupt 1 is disabled If EX1 1 the external interrupt 1 is enabled ETO 5 rw Timer 0 overflow interrupt enable If ETO 0 the timer O interrupt is disabled If ETO 1 the timer O interrupt is enabled User s Manual 7 8 V 0 4 2002 01 mn Infineon C668 technologies Interrupt System Field Bits Typ Description EXO 7 rw External interrupt 0 enable If EXO 0 the external interrupt 0 is disabled If EXO 1 the external interrupt O is enabled 6 r reserved returns 0 if read should be written with 0 The SFR IEN1 contains the enable bits for the external interrupts 2 to 3 and the A D converter interrupt ae Enable Register 1 Reset value XXXXX000g 7 6 5 4 3 2 1 0 EX3 EX2 EADC r r r r r rw rw rw Field Bits Typ De
79. B4 ETO TFO External Interrupt 1 00134 EX1 IE1 Timer 1 Overflow 001By ET1 TF1 Serial Channel 00234 ES RI TI Timer 2 Overflow 002By4 EX5 TF2 A D Converter 003314 EX6 IADC External Interrupt 2 003By4 EX7 IEX2 External Interrupt 3 004314 EX8 IEX3 004By EX9 0053 EX10 005By EX1 1 0063 EX12 006BH EX13 CCU6 interrupt node 0 0083 4 EX14 INPO CCU6 interrupt node 1 008 15 INP1 CCU6 interrupt node 2 009314 EX16 2 CCU6 interrupt node3 009BL EX17 INP3 18 User s Manual 7 35 V 0 4 2002 01 _ Infineon C868 technologies Interrupt System Table 7 3 Interrupt Source and Vectors 19 00D34 EX20 OODBY EX21 00E34 EX22 Wake up from power down 007By mode 1 Capture compare has 10 interrupt sources channeled to the 4 interrupt nodes INPO 3 The 3 capture compare ports has pairs of interrupt request flags ICC60R ICC60F ICC61R ICC61F ICC62R ICC62F The other flags are T120M T12PM T13CM T13PM TRPF WHE CHE Execution proceeds from that location until the RETI instruction is encountered The RETI instruction informs the processor that the interrupt routine is no longer in progress then pops the two top bytes from the stack and reloads the program counter Execution of the interrupted program continues from the point where it was stopped Note that the RETI instruction is very important because it informs the proce
80. Byte Reset value 00 1 7 6 5 4 3 2 1 0 ECT130 T13MODEN rw r rw Field Bits Type Description T13MODEN 5 0 rw T13 Modulation Enable Setting these bits enables the modulation of the corresponding compare channel by a PWM pattern generated by timer T13 The bit positions are corresponding to the following output signals bit 0 modulation of CC60 bit 1 modulation of COUT60 bit 2 modulation of CC61 bit 3 modulation of COUT61 bit 4 modulation of CC62 bit 5 modulation of COUT62 The enable feature of the modulation is defined as follows 0 The modulation of the corresponding output signal by a T13 PWM pattern is disabled 1 The modulation of the corresponding output signal by a T13 PWM pattern is enabled ECT130 7 rw Enable Compare Timer T13 Output 0 The alternate output function COUT63 is disabled 1 The alternate output function COUT63 is enabled for the PWM signal generated by T13 14 r reserved returns 0 if read should be written with 0 User s Manual 4 83 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components The register TRPCTR controls the trap functionality It contains independent enable bits for each output signal and control bits to select the behavior in case of a trap condition The trap condition is a low level on the CTRAP input pin which is monitored inverted level by bit in register IS While TRPF 1 trap input active t
81. C60P TATH eaPS 62PS S 61PS S 60PS S F6y T12M 00 MSEL MSEL MSEL MSEL MSEL MSEL MSEL SELL 613 612 611 610 603 602 601 600 F74 12 00 MSEL MSEL MSEL MSEL SELH 623 622 621 620 1 X means that the value is undefined and the location is reserved 2 This register is mapped with RMAP SYSCONO 4 0 3 This register is mapped with RMAP SYSCONO 4 1 Shaded registers are bit addressable special function registers User s Manual 3 19 V 0 4 2002 01 _ Infineon technologies C868 Memory Organization Table 3 7 Contents of the SFRs SFRs in numeric order of their addresses Addr Reg Bit6 Bits Bit4 2 Bit1 BitO atter ister Reset F8 PMCO CCUS T2ST ADCS N2 X000p F94 VERSI PROT VER6 VER5 VER4 VER3 VER2 VER1 VERO ON FAQ CC60 004 7 6 5 4 3 2 4 0 RL FB CC60 004 7 6 5 4 3 2 4 0 RH FC 61 00 a 6 5 4 13 2 4 0 RL FD 61 00 7 6 5 4 13 2 41 0 RH FE CC62 004 7 6 5 4 3 2 4 0 RL FFy CC62 00 7 6 5 4 13 2 4 0 RH 1 X means that the value is undefined and the location is reserved 2 This register is mapped with RMAP SYSCONO 4 0 3 This register is mapped with RMAP SYSCONO 4 1 Shaded registers are bit addressable special function registers User s Manual 3 20 V 0 4 2002 01
82. C868 technologies On Chip Peripheral Components be selected as capture event that is used to transfer the contents of timer T12 to the CC6xR and CC6xSR registers In order to work in capture mode the capture pins have to be configured as inputs edge function detection select F MSEL6x Figure 4 23 Capture Logic The block diagram of the capture logic for one channel is shown in Figure 4 23 This logic is identical for all three independent channels of timer T12 The input signal CC6x in from the input pin CC6x is connected to an edge detection logic delivering two output signals one for the rising edge Capt re and one for the falling edge Capt fe These signals are also used as trigger sources for the channel interrupts if capture mode is selected There are several possibilities to store the captured values in the registers In double register capture mode the timer value is stored in the channel shadow register CC6xSR The value formerly stored in this register is simultaneously copied to the channel register CC6xR This mode can be used if two capture events occur with very few time between them The SW can then check the new captured value and has still the possibility to read the value captured before The selection of the capture mode is done by bitfield MSEL6x According to the selected mode and the detected capture event the signals tr T R transfer T12 contents to register CC6xR tr T SR transfer T12 contents to
83. CEN 3 17 DPH 3 10 3 14 DPL 3 10 3 14 DPSE 3 14 DPSEL 3 10 DTEO 3 19 DTE1 3 19 DTE2 3 19 DTMO 3 19 DTM1 3 19 DTM2 3 19 DTMS 3 19 DTMA 3 19 DTM5 3 19 DTRO 3 19 DTR1 3 19 DTR2 3 19 DTRE 3 19 E EA 3 15 EADC 3 15 EALE 3 15 EBO 3 14 EINPO 3 15 EINP1 3 15 EINP2 3 15 EINP3 3 15 EN 3 16 ENCC 3 16 User s Manual 3 V 0 4 2002 01 _ Infineon technologies C868 ENIDL 3 16 ENT12 3 16 ENT13 3 16 ENTR 3 16 ENWH 3 16 EPWD 3 14 ES 3 15 ESEL2 3 14 ESEL3 3 14 ESWC 3 15 ETO 3 15 4 14 ET1 3 15 4 14 ET2 3 15 7 8 3 15 EX1 3 15 EX2 3 15 EX3 3 15 7 9 Execution of instructions 2 7 EXEN 3 17 EXF2 3 15 3 17 EXICO 3 14 EXICON 3 10 EXINT 3 14 EXPH 3 18 F FO 3 17 F1 3 17 Fail save mechanisms 6 1 Fast power on reset 5 2 Features 1 2 Fundamental structure 2 1 G GATE 3 14 GFO 3 14 GF1 3 14 H Hardware reset 5 1 I O ports 4 1 User s Manual V 0 4 2002 01 mn Infineon technologies C868 IADC 3 14 ICC60 3 18 ICC61 3 18 ICC62 3 18 IDLE 3 14 3 18 Idle mode 8 4 IEO 3 14 IE1 3 14 IENO 3 10 3 15 IEN1 3 10 3 15 IEN2 3 10 3 15 IENH 3 16 IENH4 3 13 IENL 3 16 IENL4 3 13 INPCC 3 16 INPCH 3 16 INPER 3 16 INPH 3 16 INPH3 3 13 INPL 3 16 3 13 INPT1 3 16 INT3 3 15 Interrupt 7 16 Interrupt system 7 1 Interrupts Block diagram 7 2 7 7 Enable registers 7 8 External interrupts 7 35 Handling procedur
84. Compare Mode Select Register High Byte Reset value 00 4 7 6 5 4 3 2 1 0 MSEL62 r r r r rw Field Bits Type Description MSEL62 3 0 rw Capture Compare Mode Selection These bitfields select the operating mode of the three timer T12 capture compare channels Each channel n 0 1 2 can be programmed individually either for compare or capture operation according to 0000 Compare outputs disabled pins CC6n and COUTE6n can be used for IO No capture action 0001 Compare output on pin CC6n pin COUT6n can be used for IO No capture action 0010 Compare output on pin COUT6n pin CC6n can be used for IO No capture action 0011 Compare output on pins COUT6n and 01XX Double Register Capture modes see Table 4 4 1000 Hall Sensor mode see Table 4 5 In order to enable the hall edge detection all three MSEL6x have to be programmed to Hall Sensor mode 1001 Hysteresis like mode see Table 4 5 101X Multi Input Capture modes see Table 4 6 11XX Multi Input Capture modes see Table 4 6 7 4 r reserved returns 0 if read should be written with 0 Note In the capture modes all edges at the CC6x inputs are leading to the setting of the corresponding interrupt status flags in register IS In order to monitor the selected capture events at the CCPOSx inputs in the multi input capture modes the CC6xST bits of the corresponding channel are set when detecting the selected event The interrupt statu
85. DTREL rw Field Bits Typ Description WDTREL 7 0 rw Watchdog Timer Reload Value for the high byte of WDT WDTCON Watchdog Timer Register Reset value XXXXXX00g 7 6 5 4 3 2 1 0 WDTIN r r r r r r r rw Field Bits Typ Description WDTIN 0 rw Watchdog Timer Input Frequency Selection 0 Input frequency is feys 2 1 Input frequency is fey 128 7 2 r reserved returns 0 if read should be written with 0 User s Manual 6 2 V 0 4 2002 01 _ Infineon technologies C868 Fail Save Mechanism WDTL Watchdog Timer Low Byte Reset value 004 7 5 4 3 2 1 0 WDT7 0 r WDTH Watchdog Timer High Byte Reset value 00 1 7 5 4 3 2 1 0 WDT15 8 rh Field Bits Typ Description WDT 7 0 of rh Watchdog Timer Current Value WDTL 7 0 of WDTH User s Manual 6 3 V 0 4 2002 01 _ Infineon C868 technologies Fail Save Mechanism SCUWDT SCU Watchdog Control Register Reset value 00 1 7 6 5 4 3 2 1 0 PLLR WDTR WDTEOI WDTDIS WDTRS WDTRE r rwh r rwh rw rw rw rw Field Bits Typ Description WDTRE 0 rw WDT Refresh Enable Active high Set to enable a refresh of the watchdog timer Must be set before WDTRS WDTRS 1 rw WDT Refresh Start Active high Set to start refresh operation on the watchdog timer Must be set after WDTRE WDTDIS 2 rw Disable
86. Figure 4 29 Synchronization of T13 to T12 This figure shows the synchronization of T13 to a T12 event The selected event in this example is a compare match compare value 2 while counting up The clocks of T12 and T13 can be different other prescaler factor but for reasons of simplicity this example shows the case for T12clk equal to T13clk 4 7 3 Multi channel Mode The multi channel mode offers a possibility to modulate all six T12 related output signals within one instruction The bits in bit field MCMP are used to select the outputs that may become active If the multi channel mode is enabled bit MCMEN 1 only those outputs may become active which have a 1 at the corresponding bit position in bit field MCMP This bit field has its own shadow bit field MCMPS which can be written by SW The transfer of the new value in MCMPS to the bit field MCMP can be triggered by and synchronized to T12 or T13 events This structure permits the SW to write the new value which is then taken into account by the HW at a well defined moment and synchronized to a PWM period This avoids unintended pulses due to unsynchronized modulation sources T12 T13 SW User s Manual 4 50 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components write by software Correct Hall Event T13pm T12pm T120m T12c1cm no action B T12zm to modulation selection JL write to 132 bitfield direct MCMPS with ST
87. Nu PTT 8 4 8 4 Slow Down Mode Operation 8 5 8 5 Software Power Down Mode 8 6 8 5 1 Exit from Software Power Down Mode 8 6 User s Manual 3 V 0 4 2002 01 Infineon C868 technologies User s Manual 4 V 0 4 2002 01 Infineon C868 technologies Introduction 1 Introduction The C868 is a member of the Infineon Technologies C800 family of 8 bit microcontrollers It is fully compatible to the standard 8051 microcontroller Its features include the capture compare unit CCU6 which is useful in motor control applications extended power saving provisions on chip RAM and RFI related improvements The C868 has a maximum CPU clock rate of 40MHz At 40MHz it achieves a 300ns instruction cycle time The C868 basically operates with internal program memory only The C868 1R contains 8 8 on chip ROM of program memory and the C868 1S contains 8 8 of on chip RAM of program memory Different operating modes are provided to allow flexibility in the access of the different types of memory An additional RAM XRAM is provided for the implementation of in system programming Figure 1 1 shows the different functional units of the C868 and Figure 1 2 shows the simplified logic symbol of the C868 2560 8 dm Vo 256 08 i CPU 16 bit Capture 8 datapointers Compare Port 3 eub ROM RAM pu 8 0 8K 08 16 bit Compare Unit Boot ROM
88. P SYSCONO 4 1 Shaded registers are bit addressable special function registers User s Manual 3 17 V 0 4 2002 01 _ Infineon C868 technologies Memory Organization Table 3 7 Contents of the SFRs SFRs in numeric order of their addresses Addr Reg Bit6 Bit5 Bit4 Bit2 Bit1 BitO after ister Reset D749 MODC 004 l T13M 13 T13M T13M T13M T13M 13 TRH ODEN ODEN ODEN ODEN 6 5 4 3 2 1 0 D84 ADCO 0000 ADST ADBS ADM1 ADMO ADCH ADCH ADCH NO X000p Y 2 1 0 D94 X1XX CAL ADST ADST ADCT ADCT N1 0000p C1 CO C1 CO DBy ADDA 00 7 6 5 4 3 2 0 TH DCH MCMO 004 l R MCMP MCMP MCMP MCMP MCMP MCMP UTL 5 4 3 2 1 0 DCH MCMO O0OW STRM MCMP MCMP MCMP MCMP MCMP UTSL CM S5 S4 S3 S2 S1 S0 DD MCMO 004 l CURH CURH CURH EXPH EXPH UTH 2 1 0 2 1 0 DDH MCMO 00 STRH CURH CURH CURH EXPH EXPH UTSH P S2 S1 50 52 S1 S0 DE IT12PR 00 4 7 6 5 4 3 2 4 0 L DF 2 7 6 5 4 3 2 1 0 H EO 00 7 6 5 4 8 2 4 0 E24 TCTR 00 CDIR STE12 2 2 12 1 T12CL T12CL OL E K2 K1 KO E3y TCTR 10 5 13 1 7113 T13CL OH PRE CLK2 KO E44 ISL 00 T12PM T12O 62 62 ICC61 6 60 60 M F R F R F R E54 ISH 00 IDLE WHE
89. RMCM 1 Figure 4 30 Modulation Selection and Synchronization Figure 4 30 shows the modulation selection for the multi channel mode The event that triggers the update of bit field MCMP is chosen by SWSEL If the selected switching event occurs the reminder flag R is set This flag monitors the update request and it is automatically reset when the update takes place In order to synchronize the update of MCMP to a PWM generated by T12 or T13 bit field SWSYN allows the selection of the synchronization event which leads to the transfer from MCMPS to MCMP Due to this structure an update takes place with a new PWM period If it is explicitly desired the update takes place immediately with the setting of flag R when the direct synchronization mode is selected The update can also be requested by SW by writing to bit field MCMPS with the shadow transfer request bit STRMOM set If this bit is set during the write action to the register the flag R is automatically set By using the direct mode and bit STRMCM the update takes place completely under SW control The possible HW request events are e a T12 period match while counting up T12pm e aT12 one match while counting down T120m e a T13 period match T13pm User s Manual 4 51 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components e aT12 compare match of channel 1 T12c1cm acorrect Hall event The possible HW synchronization events are e a
90. Rising Edge Interrupt Enable for Channel 0 0 No interrupt will be generated if the set condition for bit CC60R in register IS occurs 1 An interrupt will be generated if the set condition for bit CC60R in register IS occurs The interrupt line which will be activated is selected by bitfield INPCC60 ENCC60F 1 rw Capture Compare Match Falling Edge Interrupt Enable for Channel 0 0 No interrupt will be generated if the set condition for bit CC60F in register IS occurs 1 An interrupt will be generated if the set condition for bit CC60F in register IS occurs The interrupt line which will be activated is selected by bitfield INPCC60 ENCC61R 2 rw Capture Compare Match Rising Edge Interrupt Enable for Channel 1 0 No interrupt will be generated if the set condition for bit CC61R in register IS occurs 1 An interrupt will be generated if the set condition for bit CC61R in register IS occurs The interrupt line which will be activated is selected by bitfield INPCC61 User s Manual 7 25 V 0 4 2002 01 _ Infineon technologies C868 Interrupt System Field Bits Type Description ENCC61F rw Capture Compare Match Falling Edge Interrupt Enable for Channel 1 0 1 No interrupt will be generated if the set condition for bit CC61F in register IS occurs An interrupt will be generated if the set condition for bit CC61F in register IS occurs The interrupt line which will be activated is select
91. S ADDR DATA d MOVX 1 Byte 2 Cycle Access of External Memory Figure 2 2 Fetch Execute Sequence User s Manual 2 7 V 0 4 2002 01 Infineon C868 technologies Fundamental Structure User s Manual 2 8 V 0 4 2002 01 _ Infineon C868 technologies Memory Organization 3 Memory Organization The C868 CPU manipulates operands in the following five address spaces up to 8 Kbyte of RAM internal program memory 8K ROM for C868 1R 8K RAM for C868 1S 4 Kbyte of internal Self test and Boot ROM 256 bytes of internal data memory 256 bytes of internal XRAM data memory 128 byte special function register area Figure 3 1 illustrates the memory address spaces of the C868 XRAM FF00j 1FFFH indi direct pes addr Internal Internal RAM Internal Self Test and Boot ROM Internal 4 KByte 0000H PAMI Code Space Data Space Internal Data Space Figure 3 1 C868 Memory Map The internal Self Test and Boot ROM overlaps the internal program memory in the address range from 0000 to OFFFy Depending on the selected operating mode chipmode either internal program memory or the internal Self Test and Boot ROM is accessed in this address range User s Manual 3 1 V 0 4 2002 01 _ Infineon C868 technologies Memory Organization 3 1 Program Memory Code Space The C868 1S has 8 Kbytes of random access program memory RAM and 4 Kbytes o
92. SW MCC63S 7 This feature allows the user to individually change the status of the output lines by SW e g when the corresponding compare timer is stopped This allows a bit manipulation of CC6xST bits by a single data write action The following functionality of a write access to bits concerning the same capture compare state bit is provided MCC6xR CMPMODIFH MCC6xS 0 0 Bit CC6xST is not changed 0 1 Bit CC6xST is set 1 0 Bit CC6xST is reset 1 1 reserved toggle 5 3 7 r reserved returns O if read should be written with 0 CMPMODIFH Compare State Modification Register High Byte Reset value 00 1 7 6 5 4 3 2 1 0 MCC63R MCC62R MCC61R MCC60R r Ww r r r Ww Ww Ww User s Manual V 0 4 2002 01 _ Infineon technologies C868 On Chip Peripheral Components Field Bits Typ Description MCC60R MCC61R MCC62R MCC63R ND Capture Compare Status Modification Bits These bits are used to reset MCC6xR the corresponding bits CC6xST by SW This feature allows the user to individually change the status of the output lines by SW e g when the corresponding compare timer is stopped This allows a bit manipulation of CC6xST bits by a single data write action The following functionality of a write access to bits concerning the same capture compare state bit is provided MCC xR MCC6xS CMPMODIFL 0 0 Bit CC6xST is not changed 0 1 Bit CC6xST is set 1 0 Bit CC6xS
93. State Level The bits of this bitfield define the passive level driven by the module outputs during the passive state The bit positions are bitO passive level for output CC60 bit 1 passive level for output COUT60 bit 2 passive level for output CC61 bit 3 passive level for output COUT61 bit 4 passive level for output CC62 bit5 passive level for output COUT62 The value of each bit position is defined as 0 The passive level is 0 1 The passive level is 71 PSL632 7 rwh Passive State Level of Output COUT63 This bitfield defines the passive level of the output pin COUT63 0 The passive level is 0 1 The passive level is 71 6 r reserved returns O if read should be written with 0 1 Bitfield PSL has a shadow registers to allow for updates without undesired pulses on the output lines The bits are updated with the T12 shadow transfer A read action targets the actually used values whereas a write action targets the shadow bits User s Manual 4 87 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components 2 Bit PSL63 has a shadow register to allow for updates without undesired pulses on the output line The bit is updated with the T13 shadow transfer A read action targets the actually used values whereas a write action targets the shadow bits 4 8 4 2 Multi Channel Control Register MCMOUTS contains bits controlling the output states for multi
94. T is reset 1 1 reserved toggle 5 3 7 reserved returns 0 if read should be written with 0 User s Manual 4 73 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components Register TCTRO controls the basic functionality of both timers T12 and T13 TCTROL Timer Control Register 0 Low Byte Reset value 00 1 7 6 5 4 3 2 1 0 CTM CDIR STE12 T12R T12PRE T12CLK rw rh rh rh rw rw Field Bits Type Description T12CLK 2 0 rw Timer T12 Input Clock Select Selects the input clock for timer T12 which is derived from the peripheral clock according to the equation friz o T120LK 000 fri2 foer 001 ft12 foer 2 010 fti2 foer 4 011 ft12 fpe 8 100 ft12 16 101 fer 32 110 fr12 fper 64 111 fr12 fer 128 T12PRE 3 rw Timer T12 Prescaler Bit In order to support higher clock frequencies an additional prescaler factor of 1 256 can be enabled for the prescaler for T12 0 The additional prescaler for T12 is disabled 1 The additional prescaler for T12 is enabled T12R 4 rh T12 Run Bit T12R starts and stops timer T12 It is set reset by SW by setting bits T12RR orT12RS or it is reset by HW according to the function defined by bitfield T12SSC 0 Timer T12 is stopped 1 Timer T12 is running User s Manual 4 74 V 0 4 2002 01 _ Infineon technologies
95. T12 One Match Flag 0 No action 1 Bit T12OM in register IS will be set ST12PM 7 Set Timer T12 Period Match Flag 0 No action 1 Bit T12PM in register IS will be set User s Manual 7 21 V 0 4 2002 01 _ Infineon C868 technologies Interrupt System Interrupt Status Reset Register High Byte Reset value 00 1 7 6 5 4 3 2 1 0 SIDLE SWHE SCHE STRPF ST13PM ST13CM r r Field Bits Description ST13CM 0 Ww Set Timer T13 Compare Match Flag 0 No action 1 Bit T13CM in register IS will be set ST13PM 1 Set Timer T13 Period Match Flag 0 No action 1 Bit T13PM in register IS will be set STRPF 2 Set Trap Flag 0 No action 1 Bit TRPF in register IS will be set not taken into account while input CTRAP 0 and TRPPEN 1 SCHE 3 Ww Set Correct Hall Event Flag 0 No action 1 Bit CHE in register IS will be set SWHE 5 Ww Set Wrong Hall Event Flag 0 No action 1 Bit WHE in register IS will be set SIDLE 6 w Set IDLE Flag 0 No action 1 Bit IDLE in register IS will be set 0 2 7 r reserved returns 0 if read should be written with 0 Note If the setting by HW of the corresponding flags can lead to an interrupt the setting by SW has the same effect User s Manual 7 22 V 0 4 2002 01 mn Infineon C668 technologies Interrupt System
96. T12 zero match while counting up T12zm e T13 zero match T13zm 4 7 4 Trap Handling The trap functionality permits the PWM outputs to react on the state of the input pin CTRAP This functionality can be used to switch off the power devices if the trap input becomes active e g as emergency stop During the trap state the selected outputs are forced to the passive state and no active modulation is possible The trap state is entered immediately by HW if the CTRAP input signal becomes active and the trap function is enabled by bit TRPPEN It can also be entered by SW by setting bit trap input flag leading to TRPS 1 trap state indication flag The trap state can be left when the input is inactive by SW control and synchronized to the following events is automatically reset after CTRAP becomes inactive if TRPM2 0 e has to be reset by SW after CTRAP becomes inactive if TRPM2 1 synchronized to T12 PWM after TRPF is reset T12 period match in edge aligned mode or one match while counting down in center aligned mode synchronized to T13 PWM after TRPF is reset T13 period match no synchronization to T12 or T13 User s Manual 4 52 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components T12 me ep mue TRPF CTRAPactive TRPS sync to T13 TRPS 12 TRPS no sync Figure 4 31 Trap State Synchronization
97. The call itself takes two cycles Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine A longer response time would be obtained if the request was blocked by one of the three previously listed conditions If an interrupt of equal or higer priority is already in progress the additional wait time obviously depends on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instructions MUL and DIV are only 4 cycles long and if the instruction in progress is RETI or a write access to registers IENO IEN1 or IPO the additional wait time cannot be more than 5 cycles a maximum of one more User s Manual 7 37 V 0 4 2002 01 _ Infineon C868 technologies Interrupt System cycle to complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is MUL or DIV Thus a single interrupt system the response time is always more than 3 cycles and less than 9 cycles User s Manual 7 38 V 0 4 2002 01 Infineon C868 technologies Power Saving Modes 8 Power Saving Modes The C868 provides two basic power saving modes the idle mode and the power down mode Additionally a slow down mode is available This power saving mode re
98. User s Manual V 0 4 Jan 2002 C868 8 Bit CMOS Microcontroller Microcontrollers Never stop thinking Edition 2002 01 Published by Infineon Technologies AG St Martin Strasse 53 D 81541 M nchen Germany Infineon Technologies AG 2002 All Rights Reserved Attention please The information herein is given to describe certain components and shall not be considered as warranted characteristics Terms of delivery and rights to technical change reserved We hereby disclaim any and all warranties including but not limited to warranties of non infringement regarding circuits descriptions and charts stated herein Infineon Technologies is an approved CECC manufacturer Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide see address list Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life suppo
99. an be used to generate an interrupt In this case flag EXF2 will be set Note When timer counter 2 is in the baudrate generator mode an increment of the timer register happens for every other fsys Therefore software should not access the T2L H registers Software may however read the RC2L H registers Software write into these registers may coincide with a timer update or reload cycle and should therefore be avoided User s Manual 4 29 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components Overflow T2 RC2L H Timer 2 Pin EXF2 T2EX Interrupt EXEN2 Figure 4 9 Baudrate Generator Mode 4 6 8 Count Clock The count clock for the auto reload mode is chosen by the bit C T2 in register T2CON If C T2 0 a count clock of fgys 12 is used for the count operation If C T2 1 timer 2 behaves as a counter that counts 1 to 0 transitions of input pin T2 The counter samples pin T2 over 2 cycles If a 1 was detected during the first clock and a 0 was detected in the following clock then the counter increments by one Therefore the input levels should be stable for at least 1 clocks 4 6 9 Module Powerdown The timer counter 2 is disabled when the chip goes into the powerdown mode as describe Or it can be individually disabled by setting T2DIS in register PMCON1 This helps to reduce current consumption in the normal slow down and idle modes of operation if the timer co
100. ast time 1 A timer T13 compare match has been detected T13PM rh Timer T13 Period Match Flag 0 A timer T13 period match has not yet been detected since this bit has been reset for the last time 1 A timer T13 period match has been detected TRPF rh Trap Flag The trap flag will be set by HW if TRPPEN 1 0 or by SW If TRPM2 0 bit is reset by HW if the input CTRAP becomes inactive TRPPEN 1 If TRPM2 1 bit has to be reset by SW in order to leave the trap state 0 The trap condition has not been detected 1 The trap condition has been detected input CTRAP has been 0 or by SW TRPS rh Trap State 0 The trap state is not active 1 The trap state is active Bit TRPS is set while bit TRPF 1 It is reset according to the mode selected in register TRPCTR User s Manual 7 19 V 0 4 2002 01 mn Infineon C668 technologies Interrupt System Field Bits Description CHE 4 rh Correct Hall Event 0 A transition to a correct expected hall event has not yet been detected since this bit has been reset for the last time 1 A transition to a correct expected hall event has not yet been detected WHE 5 rh Wrong Hall Event 0 A transition to a wrong hall event not the expected one has not yet been detected since this bit has been reset for the last time 1 A tra
101. at a valid hall event which is a reference to the actual speed CC61 can be used for a phase delay function between hall event and output switching CC62 can act as a time out trigger if the expected hall event comes too late The value 71000 has to be programmed to MSELO MSEL1 and MSEL2 if the hall signals are used In this mode the contents of timer T12 is captured in CC60 and T12 is reset after the detection of a valid hall event In order to avoid noise effects the dead time counter channel 0 is started after an edge has been detected at the hall inputs When reaching the value of 000001 the hall inputs are sampled and the pattern comparison is done 1001Hysteresis like control mode with dead time generation The negative edge of the CCPOSx input signal is used to reset bit CC6nST As a result the output signals can be switched to passive state immediately and switch back to active state with dead time if the CCPOSx is high and the bit CC6nST is set by a compare event User s Manual 4 97 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components Table 4 6 Description of the Multi Input Capture modes Description Multi Input Capture modes 1010The timer value of T12 is stored in CC6nR after a rising edge at the input pin The timer value of T12 is stored in CC6nSR after a falling edge at the input pin CCPOSx 1011The timer value of T12 is stored in CC6nR after a falling edge at t
102. ating For clarification some terms regarding the difference between baud rate clock and baud rate should be mentioned The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization Therefore the baud rate generators have to provide a baud rate clock to the serial interface which there divided by 16 results in the actual baud rate However all formulas given in the following section already include the factor and calculate the final baud rate Further the abrevation feys refers to the system frequency User s Manual 4 103 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components The baud rate of the serial port is controlled by a bit which are located in the special function registers as shown below PCON Power Control Register Reset value 0XXX0000g 7 6 5 4 3 2 1 0 SMOD SD GF1 GFO PDE IDLE rw r r rw rw rw rw rw The functions of the shaded bits are not described here Field Bits Typ Description SMOD 7 rw Double baud rate When set the baud rate of serial interface in modes 1 2 3is doubled After reset this bit is cleared Depending on the programmed operating mode different paths are selected for the baud rate clock generation 4 9 1 4 Baud Rate in Mode 2 The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON If SMOD 0 which is the value after reset the baud rat
103. bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 to 0 transition This is to provide rejection or false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bits come in from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in mode 1 is a 9 bit register it flags the RX control block to do one last shift load SBUF and RB8 and set RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RI 0 2 either SM2 0 or the received stop bit 1 User s Manual 4 106 V 0 4 2002 01 Infineon C868 technologies On Chip Peripheral Components If one of these two condtions is not met the received frame is irretrievably lost If both conditions are met the stop bit goes into RB8 the 8 data bit goes into SBUF and RI is activated At this time whether the above conditions are met or not the unit goes back to looking for a 1 0 transition in RxD User s Manual 4 107 V 0 4 2002 01 Infineon technologies C868 On Chip Peripheral Components Write to e Internal Bus SBUF Baud Rate e Clock 1 to 0 Transition Detector
104. bled User s Manual 4 14 V 0 4 2002 01 Infineon C868 technologies On Chip Peripheral Components 4 5 1 2 Mode 0 Putting either timer 0 1 into mode 0 configures it as an 8 bit timer with a divide by 32 prescaler Figure 4 2 shows the mode 0 operation In this mode the timer register is configured as a 13 bit register As the count rolls over from all 1 s to all O s it sets the timer overflow flag TFO The overflow flag TFO then can be used to request an interrupt The counted input is enabled to the timer when TRO 1 and either Gate 0 or INTO 1 setting Gate 1 allows the timer to be controlled by external input INTO to facilitate pulse width measurements TRO is a control bit in the special function register TCON Gate is in TMOD The 13 bit register consists of all 8 bits of THO and the lower 5 bits of TLO The upper 3 bits of TLO are indeterminate and should be ignored Setting the run flag TRO does not clear the registers Mode 0 operation is the same for timer O as for timer 1 Substitute TRO TFO THO TLO and INTO for the corresponding timer 1 signals in Figure 4 2 There are two different gate bits one for timer 1 TMOD 7 and one for timer 0 TMOD 3 CT 0 TLO THO Interrupt 5 Bits 8 Bits Control Gate Figure 4 2 Timer 0 Mode 0 13 Bit Timer User s Manual 4 15 V 0 4 2002 01 Infineon C868 technologies On Chip Peripheral Component
105. channel mode Furthermore the appropriate signals for the block commutation by Hall sensors can be selected This register is a shadow register that can be written for register MCMOUT which indicates the currently active signals MCMOUTSL Multi Channel Mode Output Shadow Register Low Byte Reset value 00 1 7 6 5 4 3 2 1 0 STRMCM MCMPS Ww r rw Field Bits Type Description MCMPS 5 0 rw Multi Channel PWM Pattern Shadow Bitfield MCMPS is the shadow bitfield for bitfield MCMP The multi channel shadow transfer is triggered according to the transfer conditions defined by register MCMCTR STRMCM 7 Ww Shadow Transfer Request for MCMPS Setting this bits during a write action leads to an immediate update of bitfield MCMP by the value written to bitfield MCMPS This functionality permits an update triggered by SW When read this bit always delivers 0 0 Bitfield MCMP is updated according to the defined HW action The write access to bitfield MCMPS doesn t modify bitfield MCMP 1 Bitfield MCMP is updated by the value written to bitfield MCMPS 6 r reserved returns 0 if read should be written with 0 User s Manual 4 88 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components MCMOUTSH Multi Channel Mode Output Shadow Register High Byte Reset value 00 1 7 6 5 4 3 2 1 0 STRHP CURHS EXPHS Ww r
106. cle Factor 100 MHz 160 MHz 2 000g 50 80 50 linear depending on fyco 4 01 25 40 50 at 100MHz 300ps i at fyco 160MHz 250ps 5 011g 20 32 40 additional jitter for odd Kdiv 6 100g 16 67 26 67 50 factors tbd 8 101g 12 5 20 50 91 110g 11 11 17 78 44 10 111p 10 16 50 16 001g 6 25 10 50 1 These odd factors should not be used not tested because off the unsymmetrical duty cycle 2 Shaded combinations should not be used because they are above the maximum CPU frequency of 40MHz User s Manual 5 7 V 0 4 2002 01 _ Infineon C868 technologies Reset and System Clock Operation 5 6 Slow Down Operation The programmable Slow Down Divider SDD divides the PLL output clock frequency by a factor of 1 32 which is specified via CMCON REL When CMCON REL is written during SDD operation the reload counter will output one more clock pulse with the old frequency in order to synchronize it internally before generating the new frequency o D PLL clk SDD Reload Counter ede dani ime t m s dress ues id PLU eck LIU UU UU UU UU UU UU UU UU ae _clk_rel 4 B B Figure 5 4 Slow Down Divider Operation SDD clk PLL_clk CMCON RELg 1 For a 20 MHz basic clock the on chip logic may be run at a frequency down to 625 KHz without an external hardware change During Slow Down operation t
107. d one is the alternate function register P1ALT PSALT which is used to set the function of each pin When used as alternate function the direction of the pins has to be set accordingly When the bit is set an input any read operation will return the value at the port When the bit is set as an output a read operation will return the latched value if it is part of a read modify write operation otherwise a read operation will return the value at the port Note While in the idle mode or the power down mode the I O ports hold the last values User s Manual 4 1 V 0 4 2002 01 Infineon C868 technologies On Chip Peripheral Components 4 2 1 Register Overview The following table lists the port SFR registers They contain the value in the port latches Table 4 1 Memory Organization Register Overview Register Description Address P1 Port 1 SFR 904 P1DIR Port 1 Direction 90H P3 Port 3 SFR P3DIR Port 3 Direction P3ALT Port 3 Alternate Function P1ALT Port 1 Alternate Function P1 and P1DIR is mapped on the same address and depend on the RMAP SYSCONO 4 bit to select between the two registers By default bit 0 P1 occupies the address If the bit is set to 1 then P1DIR occupy the address P3 and P3DIR is mapped on the same address and depend on the RMAP SYSCONO 4 bit to select between the two registers By default bit 0 P3 occupies the address If the bit is s
108. d to read a port exclusively read the port pin In any case reading from latch or pin resp is performed by reading the SFR P3 for example MOV A reads the value from port pins while ANL 0 reads from the latch modifies the value and writes it back to the latch It is not obvious that the last three instructions in Figure 4 3 are read modify write instructions but they are The reason is that they read the port byte all 8 bits modify the addressed bit then write the complete byte back to the latch Table 4 3 Read Modify Write Instructions Instruction Function ANL Logic AND e g ANL P1 A ORL Logic OR e g ORL P2 A XRL Logic exclusive OR e g XRL P3 A JBC Jump if bit is set and clear bit e g JBC P1 1 LABEL CPL Complement bit e g CPL P3 0 INC Increment byte e g INC P4 DEC Decrement byte e g DEC P5 DJNZ Decrement and jump if not zero e g DJNZ P3 LABEL MOV Px y C Move carry bit to bit y of port x CLR Px y Clear bit y of port x SETB Px y Setbit y of port x The reason why read modify write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin For example a port bit might be used to drive the base of a transistor When a 1 is written to the bit the transistor is turned on If the CPU then reads the same port bit at the pin rather than the latch it will read the
109. d without compare match These compare signals may modify bit CC63ST only while the timer is running T13R 1 A T13 N T1 3 ST so T13 ST se T13 ST re rescaler P end of period in single shot mode Figure 4 27 T13 Compare Logic Similar to T12 bit CC63ST can be modified by SW by bits CC63S and CC63R The output line COUT63 T13 o can generate a T13 PWM at the output pin COUT63 The signal MOD T13 o can be used to modulate the other output signals with a T13 PWM In order to decouple COUT63 from the internal modulation the compare state leading to an active signal can be selected independently by bits T13IM and COUT63PS User s Manual 4 48 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components T13 ST so T13 ST ro COUT63PS Figure 4 28 T13 Logic for CC6xST Control 4 7 2 3 Single Shot Mode The single shot mode of T13 is similar to the single shot mode of T12 in edge aligned mode 4 7 2 4 Synchronization of T13 to T12 The timer T13 can be synchronized on a T12 event The bit fields 1 and T13TED select the event which is used to start timer T13 This event sets bit T13R per HW and T13 starts counting Combined with the single shot mode this feature can be used to generate a programmable delay after a T12 event User s Manual 4 49 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components compare match while counting up Na 3 2r
110. dependence of the operating frequency and the power supply current a reduction of the operating frequency results in reduced power consumption The slow down mode is activated by setting the bit SD in SFR PCON If the slow down mode is enabled the clock signals for the CPU and the peripheral units can be reduced from 1 2 to 1 32 of the nominal system clock rate The clock divider is described in the Reset and System Clock Operation chapter The controller actually enters the slow down mode after a short synchronization period max two machine cycles The slow down mode is terminated by clearing bit SD The slow down mode can be combined with the idle mode by setting the IDLE and SD bits in SFR PCON There are two ways to terminate the combined Idle and Slow Down Mode The idle mode can be terminated by activation of any enabled interrupt The CPU operation is resumed the interrupt will be serviced and the next instruction to be executed after the RETI instruction will be the one following the instruction that had set the bits IDLE and SD Nevertheless the slow down mode keeps enabled and if required has to be terminated by clearing the bit SD in the corresponding interrupt service routine or at any point in the program where the user no longer requires the slow down mode power saving The other possibility of terminating the combined idle and slow down mode is a hardware reset User s Manual 8 5 V 0 4 2002 01 _ Infineon C
111. ding upon the DCEN control bit 4 6 5 1 Up Down Count Disabled If DCEN 0 the up down count selection is disabled The timer counter therefore functions as a pure up timer counter only The operational block diagram is shown in Figure 4 6 In this mode if EXEN2 0 the timer counter starts to count up to a maximum of FFFFy once TR2 is set Upon overflow bit TF2 is set and the timer register is reloaded with a 16 bit reload of the RC2L H registers A fresh count sequence is started and the timer counter counts up from this reload value as in the previous count sequence This reload value is chosen by software prior to the occurrence of an overflow condition If EXEN2 1 the timer counter counts up to a maximum to FFFFy once TR2 is set 16 bit reload of the timer registers from register RC2L H is triggered either by an overflow condition or by a negative edge at input pin T2EX If an overflow caused the reload the overflow flag TF2 is set If a 1 to 0 transition at pin T2EX caused a reload bit EXF2 is set In either case an interrupt is generated to the core and the timer counter proceeds to its next count sequence The EXF2 flag similar to the TF2 must be cleared by software Note In counter mode if the reload via T2EX and the count clock T2 are detected simultaneously the reload takes precedence over the count The counter increments its value with the following T2 count clock User s Manual 4 25 V 0 4 2002 01 Infineon C6
112. duces the internal clock rate in normal operating mode and it can also be used for further power reduction in idle mode Further power saving is possible in the normal idle and slow down modes by disabling unutilized peripherals The peripherals that has the power down capability are the timer counter2 capture compare unit and the A D converter 8 1 Power Saving Mode Control Registers The functions of the power saving modes are controlled by bits which are located in the special function registers PCON and PMCONO The bits PDE and IDLE located in SFR PCON select the power down mode or the idle mode respectively If the power down mode and the idle mode are set at the same time power down mode takes precedence Furthermore register PCON contains two general purpose flags For example the flag bits GFO and GF1 can be used to give an indication if an interrupt occurred during normal operation or during idle mode For this an instruction that activates idle mode can also set one or both flag bits When idle mode is terminated by an interrupt the interrupt service routine can examine the flag bits User s Manual 8 1 V 0 4 2002 01 mn Infineon technologies C868 Power Saving Modes 8 2 Register Description PCON Power Control Register Reset value 0XXX0000g 7 6 5 4 3 2 1 0 SMOD SD GF1 GFO PDE IDLE rw r r rw rw rw rw rw The functions of the shaded bits are not described here
113. e 7 33 Priority registers 7 30 Priority within level structure 7 31 Request flags 7 11 Response time 7 36 Sources and vector addresses 7 34 Introduction 1 1 IPO 3 10 3 16 IP1 3 10 3 15 IRCO 3 14 IRCONO 3 10 IRCON1 3 10 ISH 3 12 3 18 User s Manual V 0 4 2002 01 mn Infineon technologies C868 ISL 3 12 3 18 ISRH 3 16 ISRHS 3 12 ISRL 3 16 ISRL3 3 12 ISSH 3 16 ISSH4 3 12 ISSL 3 16 ISSL4 3 12 ITO 3 14 IT1 3 14 K KDIVO 3 14 KDIV1 3 14 KDIV2 3 14 M MO 3 14 M1 3 14 6 3 19 MCMC 3 17 MCMCTRL4 3 13 MCME 3 17 MCMO 3 18 MCMOUTH4 3 13 MCMOUTL4 3 13 MCMOUTSHS 3 13 MCMOUTSLS 3 13 MCMP 3 18 3 17 3 18 MODCTRHG 3 13 MODCTRLS3 3 13 MSEL 3 19 O Operating Mode Selection 4 25 Oscillator operation 5 5 5 1 1 External clock source 5 11 On chip oscillator circuitry 5 11 Recommended oscillator circuit 5 10 OV 3 17 User s Manual V 0 4 2002 01 _ Infineon technologies C868 P P 3 17 P STOP 1 4 5 P1 3 11 3 14 P1ALT 3 11 3 15 P1DIR 3 11 3 14 P3 3 11 3 15 P3ALT 3 11 3 15 P3DIR 3 11 3 15 Parallel I O 4 1 PCON 3 10 3 14 PDE 3 14 PLLR 3 16 PMCO 3 14 3 19 3 20 PMCONO 3 10 PMCON1 3 10 PMCON 3 10 Ports 4 1 Types and structures Port 1 3 4 circuitry 4 7 Standard I O port circuitry 4 7 Power down mode by software 8 6 8 7 Power saving modes 8 1 8 7 Control registers 8 1 Idle mode 8 4 Slow down mode 8 5 Software power d
114. e is 1 64 of the system frequency If SMOD 1 the baud rate is 1 32 of the system frequency SMOD Mode 2 baud rate X system frequency 4 9 1 2 Baud Rate in Mode 1 and 3 In these modes the baud rate is variable and can be generated alternatively by a baud rate generator or by timer 1 Using the Timer 2 as Baud Rate Generator In modes 1 and 3 the C868 can use timer 2 as the baud rate generator for the serial port To enable the baud generator for transmit bit TCLK bit 4 of special function register User s Manual 4 104 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components T2CON must be set To enable the baud generator for receive bit RCLK bit 5 of special function register T2CON must be set With the timer 2 as clock source for the serial port in mode 1 and 3 the baud rate can be determined as follows 2SMOD Mode 1 3 baud rate 32 x timer 2 overflow rate Timer 2 overflow rate 2 216 RC2 system frequency with RC2 RC2H 7 0 RC2L 7 0 and timer2 count direction is set to up Using Timer 2 to Generate Baud Rates In modes 1 and 3 of the serial interface timer 1 can also be used for generating baud rates Then the baud rate is determined by the timer 1 overflow rate and the value of SMOD as follows 2SMOD Mode 1 3 baud rate x timer 1 overflow rate The timer 1 interrupt is usually disabled in this application Timer 1 itself can be confi
115. eared prior to entering this mode User s Manual 3 7 V 0 4 2002 01 Infineon C868 technologies Memory Organization 3 3 2 4 Software Unlock Sequence A special software unlock sequence is required to enter or exit the various chip modes supported The bits ESWC and SWC in SFR SYSCON are implemented in a way to prevent unintentional changing of the bits SWAP and BSLEN Any change of the bits SWAP or BSLEN not accompanied by the software unlock sequence will have no effect and the above bits will revert back to their previous values two instructions after being changed The following programming steps must be executed at the ESWC SWC unlock sequence i First Instruction This instruction should set the ESWC bit and modify of SWAP and or BSLEN as necessary MOV SYSCON1 10000X0YB X is BSLEN Y is SWAP ii Second Instruction The second instruction must set the SWC bit If this instruction sequence is followed then only the mode change in the previous instructions will come into effect Otherwise the previous mode will be retained and both bits ESWC and SWC are cleared The new chip mode becomes effective after the end of the second instruction after the writing of the bit SWC MOV SYSCON1 11000X0YB X is BSLEN Y is SWAP iii Third Instruction The instruction following this sequence should be used for initialization of the program counter to the 16 bit start address of the new code memory resource e g wit
116. echnologies On Chip Peripheral Components 4 8 3 Timer13 Related Registers The generation of the patterns for a single channel pulse width modulation PWM is based on timer T13 The registers related to timer T13 can be concurrently updated with well defined conditions in order to ensure consistency of the PWM signal T13 can be synchronized to several timer T12 events Timer T13 only supports compare mode on its compare channel CC63 Register T13 represents the counting value of timer T13 It can only be written while the timer T13 is stopped Write actions while T13 is running are not taken into account Register T13 can always be read by SW Timer T13 only supports edge aligned mode counting up T13L Timer T13 Counter Register Low Byte Reset value 004 7 6 5 4 3 2 1 0 T13CV7 0 rwh T13H Timer T13 Counter Register High Byte Reset value 00 1 7 6 5 4 3 2 1 0 T13CV15 8 rwh Field Bits Typ Description T13CV 7 0 of rwh Timer 13 Counter Value T13L This register represents the 16 bit counter value of 7 0 of Timer13 T13H Note While timer T13 is stopped the internal clock divider is reset in order to ensure reproducible timings and delays User s Manual 4 66 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components Register T13PR contains the period value for timer T13 The period value is compared to the actual counter
117. ed by bitfield INPCC61 ENCC62R rw Capture Compare Match Rising Edge Interrupt Enable for Channel 2 0 1 No interrupt will be generated if the set condition for bit CC62R in register IS occurs An interrupt will be generated if the set condition for bit CC62R in register IS occurs The interrupt line which will be activated is selected by bitfield INPCC62 ENCC62F rw Capture Compare Match Falling Edge Interrupt Enable for Channel 2 0 1 No interrupt will be generated if the set condition for bit CC62F in register IS occurs An interrupt will be generated if the set condition for bit CC62F in register IS occurs The interrupt line which will be activated is selected by bitfield INPCC62 ENT120M rw Enable Interrupt for T12 One Match 0 1 No interrupt will be generated if the set condition for bit T12OM in register IS occurs An interrupt will be generated if the set condition for bit T12OM in register IS occurs The interrupt line which will be activated is selected by bitfield INPT12 ENT12PM rw Enable Interrupt for T12 Period Match 0 1 No interrupt will be generated if the set condition for bit T12PM in register IS occurs An interrupt will be generated if the set condition for bit T12PM in register IS occurs The interrupt line which will be activated is selected by bitfield INPT12 User s Manual 7 26 V 0 4 2002 01 _ Infineon technologies
118. ed by software RB8 2 rw Serial port receiver bit 9 In modes 2 and 3 8 is the 9th data bit that was received In mode 1 if SM2 0 RB8 is the stop bit that was received In mode 0 RB8 is not used TB8 3 rw Serial port transmitter bit 9 TB8 is the 9th data bit that will be transmitted in modes 2 and 3 Set or cleared by software as desired REN 4 rw Enable receiver of serial port Enables serial reception Set by software to enable serial reception Cleared by software to disable serial reception SM2 5 rw Enable serial port multiprocessor communication in modes 2 and 3 In mode 2 or 3 if SM2 is set to 1 then RI will not be activated if the received 9th data bit RB8 is 0 In mode 1 if SM2 1 then RI will not be activated if a valid stop bit was not received In mode 0 SM2 should be 0 User s Manual 4 102 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components Field Bits Typ Description SMO 7 6 rw Serial port 0 operating mode selection bits Table 1 SMO 5 1 Selected operating mode 0 0 mode 0 reserved 0 1 mode 1 8 bit UART variable baud rate 1 0 mode 2 9 bit UART fixed baud rate 5 32 or 4 64 1 1 Mode 3 9 bit UART variable baud rate 4 9 1 Baud Rate Generation There are several possibilities to generate the baud rate clock for the serial port depending on the mode in which it is oper
119. efore even the watchdog timer cannot reset the device when one of the power saving modes has been entered accidentally 6 1 3 Refreshing the Watchdog Timer At the same time the watchdog timer is started the 8 bit register WDTH is preset by the contents of WDTREL Once started the watchdog cannot be stopped by software but can only be refreshed to the reload value by first setting bit WDTRE and WDTRS in SFR SCUWDT consecutively Bit WDTR will automatically be cleared during the second machine cycle after having been set For this reason setting WDTRS bit has to be a one cycle instruction e g SETB WDTRS This double instruction refresh of the watchdog timer is implemented to minimize the chance of an unintentional reset of the watchdog The reload register WDTREL can be written to at any time as already mentioned Therefore a periodical refresh of WDTREL can be added to the above mentioned starting procedure of the watchdog timer Thus a wrong reload value caused by a possible distortion during the write operation to the WDTREL can be corrected by software User s Manual 6 5 V 0 4 2002 01 Infineon technologies 6 1 4 The time period for an overflow of the Watchdog Timer is programmable in two ways the input frequency to the Watchdog Timer can be selected via bit WDTIN in register WDTCON to be either fsvs 2 or fs 4 128 the reload value WDTREL for the high byte of WDT can be programmed in register WDTCON C868
120. en into the ADDATH registers A D Conversion Timing in Relation to Processor Cycles Depending on the application typically there are three methods to handle the A D conversion in the C868 Software delay The machine cycles of the A D conversion are counted and the program executes a software delay e g NOPs before reading the A D conversion result in the write result cycle This is the fastest method to get the result of an A D conversion Polling ADBSY bit The ADBSY bit is polled and the program waits until ADBSY 0 Attention a polling JB instruction which is two machine cycles long possibly may not recognize the ADBSY 0 condition during the write result cycle in the continuous conversion mode A D conversion interrupt After the start of an A D conversion the A D converter interrupt is enabled The result of the A D conversion is read in the interrupt service routine If other C868 interrupts are enabled the interrupt latency must be regarded Therefore this software method is the slowest method to get the result of an A D conversion User s Manual 4 120 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components 4 11 1 A D Converter Calibration The C868 A D converter includes hidden internal calibration mechanisms which assure a safe functionality of the A D converter according to the DC characteristics The A D converter calibration is implemented in a way that a user program which executes A D
121. er 4 Low Byte Reset value 00 1 7 6 5 4 3 2 1 0 T12STD T12STR DTRES T12RES T12RS T12RR r r Field Bits Type Description T12RR 0 Timer T12 Run Reset Setting this bit resets the T12R bit 0 T12R is not influenced 1 T12R is cleared T12 stops counting T12RS 1 Timer T12 Run Set Setting this bit sets the T12R bit 0 T12R is not influenced 1 T12R is set T12 starts counting T12RES 2 Ww Timer T12 Reset 0 No effect on T12 1 The T12 counter register is reset to zero The switching of the output signals is according to the switching rules Setting of TT2RES has no impact on bit T12R DTRES 3 Ww Dead Time Counter Reset 0 No effect on the dead time counters 1 The three dead time counter channels are reset to zero T12STR 6 Ww Timer T12 Shadow Transfer Request 0 No action 1 STE12 is set enabling the shadow transfer T12STD 7 Ww Timer T12 Shadow Transfer Disable 0 No action 1 STE12 is reset without triggering the shadow transfer 5 4 r reserved returns 40 if read should be written with 0 User s Manual 4 80 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components Note A simultaneous write of a 1 to bits which set and reset the same bit will trigger no action The corresponding bit will remain unchanged TCTRAH Timer Control Register 4 High Byte Reset value 00 1 7 6 5 4 3
122. eriod register T12PR which is also built with a shadow register The write access from the CPU targets the corresponding shadow registers whereas the read access targets the registers actually used except for the three compare channels where the actual and the shadow registers can be read one match zero match period shadow transfer compare shadow transfer according to capture events bitfield MSEL6x counter register T12 Figure 4 10 112 Overview While timer T12 is running write accesses to register T12 are not taken into account If the timer T12 is stopped and the dead time counters are 0 write actions to register T12 are immediately taken into account User s Manual 4 32 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components 4 7 1 2 Counting Rules Referring to T12 input clock the counting sequence is defined by the following counting rules T12 in edge aligned mode The counter is reset to zero and if desired the T12 shadow transfer takes place if the period match is detected The counting direction is always upwards T12 in center aligned mode e The count direction is set to counting up CDIR 0 if the one match is detected while counting down e The count direction is set to counting down CDIR 1 if the period match is detected while counting up e The counter counts up while CDIR 0 and it counts down while CDIR 1 f enabled the shadow
123. es The various chip modes supported are shown in Figure 3 2 Normal 25 Mode E 4 E a z ru Bootstrap Mode 7 Bootstrap amp XRAM bk Hardware P Software Figure 3 2 Entry and exit of Chip Modes A valid hardware reset would of course override any of the above entry or exit procedures Table 3 1 Hardware and Software Selection of Chipmodes Operating Mode Hardware Selection Software Selection Chipmode Normal Mode ALE BSL pin high ALE BSL don t care RESET rising edge setting bits BSLEN SWAP 0 0 execute unlocking sequence Normal XRAM Mode Not possible setting bits BSLEN SWAP 0 1 execute unlocking sequence Bootstrap XRAM Mode Not possible setting bits BSLEN SWAP 1 1 execute unlocking sequence Bootstrap Mode ALE BSL pin low ALE BSL don t care RESET rising edge setting bits BSLEN SWAP 1 0 execute unlocking sequence User s Manual 3 5 V 0 4 2002 01 Infineon C868 technologies Memory Organization 3 3 2 1 Normal Mode The normal mode is the standard 8051 compatible operating mode of the C800 Table 3 2 Normal Memory Configuration for C868 Memory Space Memory Boundary Code Space RAM ROM 0000 to 1FFFY Internal Data Space XRAM FF00 to FFFFy 3 3 2 2 Bootstrap Mode In the bootstrap mode code is fetched from the boot ROM when PC is less than 10
124. escribed here Field Bits Typ Description BO 3 rw Brownout Status Bit 0 Brownout not detected 1 Brownout detected before the last power on if EBO was set before the occurence of brownout This bit is set by hardware only it is cleared by hardware reset and software EBO 4 rw Enable Brownout detect 0 Brownout module is disabled Occurence of brownout will not cause an internal reset 1 Occurence of brownout will cause an internal reset and BO will be set 7 5 r reserved returns 0 if read should be written with 0 User s Manual 5 4 V 0 4 2002 01 Infineon C868 technologies Reset and System Clock Operation 5 4 Clock Generation The top level view of the system clock generation of the C868 is shown in Figure 5 3 XTAL1 On Chip fos Osc clkin XTAL2 Figure 5 3 Block Diagram of the Clock Generation 5 5 PLL Operation The PLL consists of a voltage controlled oscillator VCO with a feedback path A divider in the feedback path divides the VCO frequency down The resulting frequency is then compared to the externally applied frequency The phase detection logic determines the difference between the two clock signals and accordingly controls the frequency of the VCO During start up the VCO increases its frequency until the divided feedback clock matches the external clock frequency A lock detection logic monitors and signals this condition The phase detec
125. escription T2DIS 1 rw Timer 2 Disable Request 0 Timer 2 will continue normal operation default 1 Request to disable the Timer 2 is active PMCON2 Peripheral Management Status Register Reset value XXXXX000g 7 6 5 4 3 2 1 0 CCUST T2ST ADCST r r r r r rh rh rh The functions of the shaded bits are not described here Field Bits Typ Description T2ST 1 rh Timer 2 Disable Status 0 Timer 2 is not disabled default 1 Timer 2 is disabled clock is gated off User s Manual V 0 4 2002 01 am Infineon C868 technologies On Chip Peripheral Components 4 6 4 Operating Mode Selection The operating mode of timer counter 2 is controlled by register T2CON This register serves two purposes during initialization it provides access to a set of control bits during timer operation it provides access to a set of status flags The different modes of operation are Auto Reload Mode Capture Mode and Baudrate Generator Mode 4 6 5 Auto Reload Mode In the auto reload mode timer counter 2 counts to an overflow value and then reloads its registers contents with a 16 bit value start value for a fresh counting sequence The overflow condition is indicated by setting the bit TF2 in the T2CON register This will then generate an interrupt request to the core by an active high signal The overflow flag TF2 must be cleared by software The auto reload mode is further classified into two categories depen
126. et to 1 then P3DIR occupy the address Ports 1 and 3 also serves alternate functions as listed in the Table 4 2 To select between the alternate function and normal I O registers P1ALT and P3ALT are used Each can be set to 1 for alternate functions or reset to 0 for normal I O Table 4 2 Ports 1 and 3 Alternate Functions Port Pin Alt Function Description 1 P1 0 TxD Transmit data of serial interface 1 P1 1 EXF2 Timer 2 overflow flag 1 P1 3 INT3 Interrupt 3 1 P1 4 RxD Receive data of serial interface 3 P3 0 COUT63 16 bit compare channel output 3 P3 1 CTRAP CCU trap input 3 P3 2 COUT62 Output of CCU6 channel 2 3 P3 3 CC62 Input output of CCU6 channel 2 3 P3 4 COUT61 Output of CCU6 channel 1 3 P3 5 CC61 Input output of CCU6 channel 1 3 6 COUT60 Output of CCU6 channel 0 3 P3 7 CC60 Input output of CCU6 channel 0 User s Manual 4 2 V 0 4 2002 01 _ Infineon technologies C868 P1 Port 1 Register On Chip Peripheral Components Reset value XXX111115 94 93 92 91 90 E P1 4 0 r r r rw Field Bits Typ Description P1 4 0 4 0 rw Port 1 Latch This SFR appears at address 90y only if bit SYSCONO 4 is 0 7 5 r reserved returns 0 if read should be written with 0 P1DIR Port 1 Direction Register Reset value 11111 94 93 92
127. event is detected Bit STE13 is cleared by hardware after the shadow transfer A T13 shadow transfer event is a period match 0 The shadow register transfer is disabled 1 The shadow register transfer is enabled 7 6 reserved returns 0 if read should be written with O 1 A concurrent set reset action on T13R from T13SSC T13TEC T13RR or T13RS will have no effect The bit T12R will remain unchanged Note A write action to the bit fields T13CLK or T13PRE is only taken into account while the timer T13 is not running T13R 0 User s Manual 4 77 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components Register TCTR2 controls the single shot and the synchronization functionality of both timers T12 and T13 Both timers can run in single shot mode In this mode they stop their counting sequence automatically after one counting period with a count value of zero The single shot mode and the synchronization feature of 13 to T12 allows the generation of events with a programmable delay after well defined PWM actions of T12 For example this feature can be used to trigger AD conversions after a specified delay to avoid problems due to switching noise synchronously to a PWM event TCTR2L Timer Control Register 2 Reset value 00 1 7 6 5 4 3 2 1 0 T13TED T13TEC T13SSC T12SSC r rw rw rw rw Field Bits Type Description T12SSC 0 rw Time
128. f Boot and Self Test ROM In the normal mode the C868 1S executes program code out of the internal RAM The Boot ROM includes a bootstrap loader program for the bootstrap loader of the C868 1S The software routines of the bootstrap loader program allow the easy and quick programming or loading of the internal program RAM via the serial interface while the MCU is in circuit The C868 1R has 8Kbytes of ROM and 4 Kbytes of Self Test ROM The Self Test ROM has a self test program for the self test mode of the C868 3 2 Data Memory Data Space The data memory address space consists of an internal and an external XRAM memory space The internal data memory is divided into three physically separate and distinct blocks the lower 128 bytes of RAM the upper 128 bytes of RAM and the 128 byte special function register SFR area While the upper 128 bytes of data memory and the SFR area share the same address locations they are accessed through different addressing modes The lower 128 bytes of data memory can be accessed through direct or register indirect addressing the upper 128 bytes of RAM can be accessed through register indirect addressing only the special function registers are accessible through direct addressing Four 8 register banks each bank consisting of eight 8 bit multi purpose registers occupy locations 00 through 1Fy in the lower RAM area The next 16 bytes locations 204 through 2Fy contain 128 directly addressable bit l
129. for block commutation Integrated error handling Fast emergency stop without CPU load via external signal CTRAP Control modes for multi channel AC drives Output levels can be selected and adapted to the power stage Capture compare unit can be powerdown in normal idle and slow down modes The timer T12 can work in capture and or compare mode for its three channels The modes can also be combined The timer T13 can work in compare mode only The multi channel control unit generates output patterns which can be modulated by T12 and or T13 The modulation sources can be selected and combined refer to figure Modulation Selection Passive Level and Alternate Output Enable of T12 for the signal modulation User s Manual 4 31 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components 4 7 1 Timer T12 4 7 1 1 Overview The timer T12 is used for capture compare purposes with three independent channels The timer T12 is a 16 bit wide counter Three channel registers CC60R CC61R CC62R which are built with shadow registers CC60SR CC61SR CC62SR contain the compare value or the captured timer value In compare mode the software writes to the shadow registers and their contents are transferred simultaneously to the actual compare registers during the T12 shadow transfer In capture mode the captured value of T12 can be read from the channel registers The period of the timer T12 is fixed by the p
130. g A machine cycle of the C868 consists of 6 states 12 system clock periods Each state is divided into a phase 1 half and a phase 2 half Thus a machine cycle consists of 12 internal clock periods numbered S1P1 state 1 phase 1 through S6P2 state 6 phase 2 Each state lasts two internal clock periods Typically arithmetic and logic operations take place during phase 1 and internal register to register transfers take place during phase 2 The diagrams in Figure 2 2 show the fetch execute timing related to the internal states and phases Since these internal clock signals are not user accessible the ALE address latch enable signal are shown for external reference ALE is normally activated twice during each machine cycle once during S1P2 and S2P1 and again during S4P2 and S5P1 Execution of a one cycle instruction begins at S1P2 when the op code is latched into the instruction register If it is a two byte instruction the second reading takes place during S4 of the same machine cycle If it is a one byte instruction there is still a fetch at S4 but the byte read which would be the next op code is ignored discarded fetch and the program counter is not incremented In any case execution is completed at the end of S6P2 Figure 2 2 a and b show the timing of a 1 byte 1 cycle instruction and for a 2 byte 1 cycle instruction Most C868 instructions are executed in one cycle MUL multiply and DIV divide are the only ins
131. gister High Byte BFy 00 Unit CC60SRL Cap Com Channel 0 Shadow Low Byte 00 CC60SRH Cap Com Channel 0 Shadow High Byte FB4 00 4 CC61SRL Cap Com Channel 1 Shadow Low Byte FCy 00 CC61SRH Cap Com Channel 1 Shadow High Byte FD 00 CC62SRL Cap Com Channel 2 Shadow Low Byte FE 00 CC62SRH Cap Com Channel 2 Shadow High Byte 00 CC63SRL T13 Compare Shadow Reg Low Byte B6y 00 CC63SRH T13 Compare Shadow Reg High Byte B7 00 MODCTRL Modulation Control Register Low Byte 00y MODCTRH Modulation Control Register High Byte D74 00 TRPCTRL Trap Control Register Low Byte CEy 00 TRPCTRH Trap Control Register High Byte CF4 00 PSLRL Passive State Level Register Low Byte A64 00 MCMOUTL Output Register Low Byte DCy 00 MCMOUTH Output Register High Byte 00 MCMOUTSL MCM Output Shadow Register Low Byte DCy 00 MCMOUTSH MCM Output Shadow Register High Byte 00 MCMCTRL Control Register Low Byte D6y 00 T12MSELL T12 Cap Com Mode Sel Reg Low Byte 00 T12MSELH T12 Cap Com Mode Sel Reg High Byte F74 00 1 Bit addressable special function registers 2 X means that the value is undefined and the location is reserved 3 Register is mapped by bit RMAP in SYSCONO 4 1 4 Register is mapped by bit RMAP in SYSCONO 4 0 User s Manual 3 13 V 0 4 2002 01 _ Infineon C868 technologies
132. gured for either timer or counter operation and in any of its operating modes In most typical applications it is configured for timer operation in the auto reload mode high nibble of TMOD 0010 In this case the baud rate is given by the formula 25 00 x system frequency Mode 1 3 baud rate 32 x 12 x 256 TH1 Very low baud rates can be achieved with timer 1 if leaving the timer 1 interrupt enabled configuring the timer to run as 16 bit timer high nibble of TMOD 0001p and using the timer 1 interrupt for a 16 bit software reload User s Manual 4 105 V 0 4 2002 01 Infineon C868 technologies On Chip Peripheral Components 4 9 2 Details about Mode 1 Ten bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first and a stop bit 1 On reception the stop bit goes into RB8 in SCON The baud rate is determined either by the timer 1 overflow rate or by the internal baud rate generator Figure 4 37 shows a simplified functional diagram of the serial port in mode 1 The associated timings for transmit receive are illustrated in Figure 4 38 Transmission is initiated by an instruction that uses SBUF as a destination register The Write to SBUF signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested Transmission starts at the next rollover in the divide by 16 counter
133. h LUMP OXXXXH XXXX is the 16 bit hexadecimal address in new code memory If both SWAP and BSLEN bits are set in the first instruction both modes will still be entered It is in any case the responsibility of the user to provide the appropriate relocation address depending on the mode prior to the execution of this sequence The special software unlock instruction sequence cannot be interrupted by an interrupt request Any read or write operation to SFR SYSCON will block the interrupt generation for the first cycle of the directly following instruction Therefore the response time of an interrupt request may be additionally delayed User s Manual 3 8 V 0 4 2002 01 _ Infineon C868 technologies Memory Organization 3 4 Special Function Registers All registers except the program counter and the four general purpose register banks reside in the special function register area The special function register area consists of two portions the standard special function register area and the mapped special function register area For accessing the mapped special function area bit RMAP in special function register SYSCONO must be set All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared 0 SYSCONO System Control Register 0 Reset value XX10XXX1 7 6 5 4 3 2 1 0 EALE RMAP XMAPO r r rw rw r r r rw
134. he input pin The timer value of T12 is stored in CC6nSR after a rising edge at the input pin CCPOSx 1100The timer value of T12 is stored in CC6nR after a rising edge at the input pin The timer value of T12 is stored in CC6nSR after a rising edge at the input pin CCPOSx 1101The timer value of T12 is stored in CC6nR after a falling edge at the input pin The timer value of T12 is stored in CC6nSR after a falling edge at the input pin CCPOSx 1110The timer value of T12 is stored in CC6nR after any edge at the input pin CC6n The timer value of T12 is stored in CC6nSR after any edge at the input pin CCPOSx 1111reserved no capture or compare action User s Manual 4 98 V 0 4 2002 01 mn Infineon technologies C868 On Chip Peripheral Components PMCON1 Peripheral Management Control Register Reset value XXXXX000g 7 6 5 4 2 1 0 CCUDIS T2DIS ADCDIS r r r r rw rw rw The functions of the shaded bits are not described here Field Bits Typ Description CCUDIS 2 rw CCU6 Disable Request 0 CCU6 will continue normal operation default 1 Request to disable the CCU6 is active PMCON2 Peripheral Management Status Register Reset value XXXXX000g 7 6 5 4 2 1 0 5 CCUST T2ST ADCST r r r r r rh rh rh The functions of the shaded bits are not described here Field Bits Typ Descr
135. he state of the capture CC62ST 2 compare channels Bits CC6xST x 0 1 2 are CC63ST 6 related to T12 bit CC63ST is related to T13 0 In compare mode the timer count is less than the compare value In capture mode the selected edge has not yet been detected since the bit has been reset by SW the last time 1 In compare mode the counter value is greater than or equal to the compare value In capture mode the selected edge has been detected 5 3 7 Ir reserved returns 0 if read should be written with 0 1 These bits are set and reset according to the T12 T13 switching rules CMPSTATH Compare State Register High Byte Reset value 00 1 7 6 5 4 3 2 1 0 COUT COUT COUT COUT 625 CC62PS CC6IPS Cops 6 5 rwh rwh rwh rwh rwh rwh rwh rwh User s Manua 4 70 V 0 4 2002 01 _ Infineon technologies C868 On Chip Peripheral Components Field Bits Typ Description CC60PS 0 rwh Passive State Select for Compare Outputs CC61PS 2 Bits CC6xPS COUT6xPS select the state of the CC62PS 4 corresponding compare channel which is COUT60PS 1 considered to be the passive state During the COUT61PS 3 passive state the passive level defined in register COUT62PS 5 PSLR is driven by the output pin Bits CC6xPS COUT63PS 6 COUT6xPS x 0 1 2 are related to T12 bit 1 CC63PS is related to T13 0 The corresponding compare o
136. he trap state bit TRPS in register IS is set to 71 TRPCTRL Trap Control Register Low Byte Reset value 00 1 7 6 5 4 3 2 1 0 TRPM2 TRPM1 TRPMO r r r r r rw rw rw Field Bits Description TRPM1 1 0 rw Trap Mode Control Bits 1 0 TRPMO These two bits define the behavior of the selected outputs when leaving the trap state after the trap condition has become inactive again A synchronization to the timer driving the PWM pattern permits to avoid unintended short pulses when leaving the trap state The combination TRPM1 TRPMO leads to 00 The trap state is left return to normal operation according to TRPM2 when a zero match of T12 while counting up is detected synchronization to T12 01 The trap state is left return to normal operation according to TRPM2 when a zero match of T13 is detected synchronization to T13 10 reserved 11 The trap state is left return to normal operation according to TRPM2 immediately without any synchronization to T12 or T13 User s Manual 4 84 V 0 4 2002 01 _ Infineon technologies C868 On Chip Peripheral Components Field Bits Type Description TRPM2 2 rw Trap Mode Control Bit 2 0 The trap state can be left return to normal operation bit TRPS 0 as soon as the input CTRAP becomes inactive Bit TRPF is automatically cleared by HW if the input pin CTRAP become
137. he whole device including bus interface is clocked with the symmetrical SDD clock see figure above 5 6 1 Switching Between PLL Clock and SDD Clock Switching Control logic controls the switching mechanism itself and ensures a continuous and glitch free clock signal to the on chip logic Note When switch from slow down mode to PLL operation if configured Master clock will be switched to PLL clock only after PLL pll_locked is locked Switching to Slow Down operation affects frequency sensitive peripherals like serial interfaces timers PWM etc If these units are to be operated in Slow Down mode their Prescalers or reload values must be adapted Please note that the reduced CPU frequency decreases e g timer resolution and increases the step width e g for baudrate generation The basic clock frequency in such a case should be chosen to accommodate the required resolutions and or baudrates User s Manual 5 8 V 0 4 2002 01 Infineon C868 technologies Reset and System Clock Operation CMCON Clock Control Register Reset value 9Fj 7 6 5 4 3 2 1 0 KDIV REL rw rw Field Bits Typ Description REL 4 0 rw Slowdown divider REL is used to divide down the system clock during slow down mode KDIV 7 5 rw K divider KDIV selects the PLL division factor according to Table 5 2 User s Manual 5 9 V 0 4 2002 01 _ Infineon C868 technologies Reset and Sys
138. hip 4 120 AC 3 17 ACC 2 3 3 10 3 18 ADBS 3 18 ADCDI 3 19 ADCH 3 18 ADCO 3 18 ADCONO 3 11 ADCON1 3 11 ADCS 3 20 ADCT 3 18 ADDA 3 18 ADDATH 3 11 ADMO 3 18 ADM 1 3 18 ADST 3 18 Auto Reload Mode 4 25 B B 2 5 3 10 3 19 Basic CPU timing 2 6 Baudrate Generator Mode 4 29 Block diagram 2 2 BO 3 14 BSLE 3 15 C C 3 14 3 17 CAL 3 18 Capture Mode 4 28 CC60 3 15 3 16 3 20 CC60P 3 19 CC60RH 3 12 CC60RL 3 12 605 3 19 CC60SRH 3 13 CC60SRL 3 13 CC61 3 15 3 16 3 20 CC61P 3 19 User s Manual V 0 4 2002 01 _ Infineon technologies C868 CC61RH 3 12 CC61RL 3 12 CC61S 3 19 CC61SRH 3 13 CC61SRL 3 13 CC62 3 15 3 17 3 20 CC62P 3 19 CC62RH 3 12 CC62RL 3 12 625 3 19 CC62SRH 3 13 CC62SRL 3 13 CC63 3 15 3 16 3 17 CC63RH 3 12 CC63RL 3 12 CC638 3 19 CC63SRH 3 13 CC63SRL 3 13 CCUDI 3 19 CCUS 3 20 CDIR 3 18 CHE 3 18 Clock generation unit Setup of system clock frequency 5 6 CMCO 3 14 CMCON 3 10 CMPM 3 19 CMPMODIFH 3 12 CMPMODIFL 3 12 CMPS 3 19 CMPSTATH 3 12 CMPSTATL 3 12 COCAH 1 3 18 2 3 18 COCAL1 3 18 Count Clock 4 30 COUT 3 15 3 19 CP 3 17 CPU Accumulator 2 3 B register 2 5 Basic timing 2 6 Fetch execute diagram 2 7 User s Manual V 0 4 2002 01 Infineon C868 technologies Functionality 2 3 Program status word 2 3 Stack pointer 2 5 CPU timing 2 7 CTM 3 18 CTRA 3 15 CURH 3 18 CY 3 17 D DO 3 14 D1 3 14 D2 3 14 D
139. hip oscillator and the PLL are started the state of pin INTO is internally latched and INTO can be set again to high level if required The on chip oscillator takes about typically 10 ms to stabilize 4 The PLL will be locked within 1 ms after the on chip oscillator clock is detected for stable nominal frequency Subsequently the microcontroller starts again with its operation initiating the power down wake up interrupt The interrupt address of the first instruction to be executed after wake up is 007B Instruction fetches during the interrupt call are however discarded After the RETI instruction of the power down wake up interrupt routine has been executed the instruction which follows the initiating power down mode instruction sequence will be executed Co All interrupts of the C868 are disabled from phase 2 until the end of phase 5 Other Interrupts can be first handled after the RETI instruction of the wake up interrupt routine The procedure to exit the software power down mode via the RXD pin is identical to the above procedure except that in this case pin RXD replaces pin INTO and bit WS in SFR PCON1 should be set prior to entering software power down mode User s Manual 8 7 V 0 4 2002 01 Infineon C868 technologies Power Saving Modes User s Manual 8 8 V 0 4 2002 01 _ Infineon technologies C868 A A D converter 4 114 Calibration mechanisms 4 121 System clock relations
140. ibe in Or it can be individually disabled by setting CCUDIS in register PMCON1 This helps to reduce current consumption in the normal slow down and idle modes of operation if the CCU6 is not utilized Bit CCUST in register 2 reflects the powerdown status of CCUS User s Manual 4 58 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components 4 8 Kernel Description 4 8 1 Register Overview 4 8 2 Timer12 Related Registers The generation of the patterns for a 3 channel pulse width modulation PWM is based on timer T12 The registers related to timer T12 can be concurrently updated with well defined conditions in order to ensure consistency of the three PWM channels Timer T12 supports capture and compare modes which can be independently selected for the three channels CC60 CC61 and CC62 Register T12 represents the counting value of timer T12 It can only be written while the timer T12 is stopped Write actions while T12 is running are not taken into account Register T12 can always be read by SW In edge aligned mode T12 only counts up whereas in center aligned mode T12 can count up and down T12L Timer T12 Counter Register Low Byte Reset value 00 1 7 6 5 4 3 2 1 0 T12CV7 0 rwh T12H Timer T12 Counter Register High Byte Reset value 00 1 7 6 5 4 3 2 1 0 T12CV15 8 rwh Field Bits Typ Description T12CV 7 0 of rwh Timer 12 Counter Va
141. imer is running As a result write actions to the timer registers while the timer is stopped do not lead to compare actions 4 7 1 4 Duty Cycle of 0 and 100 These counting and switching rules ensure a PWM functionality in the full range between 0 and 100 duty cycle duty cycle active time total PWM period In order to obtain a duty cycle of 0 compare state never active a compare value of T12P 1 has to be programmed for both compare modes A compare value of 0 will lead to a duty cycle of 100 compare state always active 4 7 1 5 Compare Mode of T12 The following figure shows the setting and resetting of the compare state bit CC6xST In order to simplify the description only one out of the three parallel channels is described The letter x in the simplified bit names and signal names indicates that there are more than one channel The CC6xST bit is the compare state bit in register CMPSTAT the bit CC6xPS represents passive state select bit The timer T12 generates pulses indicating events like compare matches period matches and zero matches which are used to set signal T12_xST_se and to reset signal T12_xST_re the corresponding compare state bit CC6xST according to the counting direction The timer T12 modulation output lines T12xO two for each channel can be selected to be in the active state while the corresponding compare state is 0 with CC6xPS 0 or while the corresponding compare state is 1 wi
142. ions The active state and the passive state which are used to generate the desired PWM as a combination of the states delivered by T13 the trap control unit and the multi channel control unit If the active state is interpreted as a 17 and the passive state as a 0 the state information is combined with a logical AND function active AND active active e active AND passive passive passive AND passive passive The compare states change with the detected compare matches and are indicated by the CC6xST bits The compare states of T12 are defined as follows passive if the counter value is below the compare value active if the counter value is above the compare value This leads to the following switching rules for the compare states Set to the active state when the counter value reaches the compare value while counting up reset to the passive state when the counter value reaches the compare value while counting down reset to the passive state in case of a zero match without compare match while counting up set to the active state in case of a zero match with a parallel compare match while counting up compare match 0 compare active passive state Figure 4 14 Compare States for Compare Value 2 User s Manual 4 35 V 0 4 2002 01 mn Infineon C868 technologies On Chip Peripheral Components The switching rules are only taken into account while the t
143. ions of these capacitors User s Manual 5 10 V 0 4 2002 01 Infineon C868 technologies Reset and System Clock Operation To internal timing circuitry Crystal or ceramic resonator Figure 5 6 On Chip Oscillator Circuitry To drive the C868 with an external clock source the external clock signal has to be applied to XTAL2 as shown in Figure 5 7 XTAL1 has to be left unconnected A pullup resistor is suggested to increase the noise margin but is optional if V5 of the driving gate corresponds to the Vim specification of XTAL2 Voce C868 XTAL1 External Clock XTAL2 Signal Figure 5 7 External Clock Source User s Manual 5 11 V 0 4 2002 01 Infineon C868 technologies Reset and System Clock Operation User s Manual 5 12 V 0 4 2002 01 Infineon C868 technologies Fail Save Mechanism 6 Fail Save Mechanism The C868 offers enhanced fail save mechanisms which allow an automatic recovery from software upset or hardware failure a programmable watchdog timer WDT with variable time out period from 12 8 s to 819 2 S at foys 40 MHz 6 1 Programmable Watchdog Timer To protect the system against software failure the user s program has to clear this watchdog within a previously programmed time period If the software fails to do this periodical refresh of the watchdog timer an internal reset will be initiated The software can be designed s
144. ipheral Components compare match compare match 1 0 CDIR 1 0 12 ___ 0 CC x AE mese 2 E x compare state T12 shadow transfer n 2 shadow transfer Figure 4 19 Switching Example for Duty Cycles near 100 12 1 ety 12 1 2 4 T12P SEA T12P T12P 1 X compare match 0 1 0 l 1 CDIR T12 T12P 1 STE12 T12P Y T12P 1 CC6x passive active passive active state 12 shadow transfer Ti 2 shadow transfer Figure 4 20 Switching Example for Duty Cycles near to 0 4 7 1 8 Dead time Generation The generation of complementary signals for the highside and the lowside switches of one power inverter phase is based on the same compare channel For example if the User s Manual 4 41 V 0 4 2002 01 mn Infineon C868 technologies On Chip Peripheral Components highside switch should be active while the T12 counter value is above the compare value compare state 1 then the lowside switch should be active while the counter value is below compare state 0 The compare state which may lead to an active output respecting other modulation sources and the trap functionality can be selected by the CC6xPS bits CC6xST CC6xST DTCx o L CC6xPS CC6xST AND DTCx o CC6x T12 COUT6xPS COUT6x T12 o CC6xST AND DTCx Figure 4 21 PWM signals with Dead time Generation In most cases the switching beha
145. iption CCUST 2 rh CCU6 Disable Status 0 CCU6 is not disabled default 1 CCU6 is disabled clock is gated off User s Manual 4 99 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components 4 9 Serial Interface The serial port of the C868 is full duplex meaning it can transmit and receive simultaneously It is also receive buffered meaning it can commence reception of a second byte before a previously received byte has been read from the receive register however if the first byte still hasn t been read by the time reception of the second byte is complete one of the bytes will be lost The serial port receive and transmit registers are both accessed at special function register SBUF Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register The serial port can operate in 3 asynchronous modes The baud rate clock for the serial port is derived from the oscillator frequency mode 2 or generated either by timer 1 or by a dedicated baud rate generator mode 1 3 Mode 0 is reserved Mode 1 8 Bit UART Variable Baud Rate In mode 1 ten bits are transmitted through TxD or received through RxD They area start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in special function register SCON The baud rate is variable See section 4 9 2 for more detailed information Mode 2 9 Bit UART Fixed Baud Rate
146. isters CC6xR if the corresponding capture event is detected The registers CC6xR can only be read by SW the modification of the value is done by a shadow register transfer from register CC6xSR The corresponding shadow registers CC6xSR can be read and written by SW In capture mode the value of the T12 counter register can also be captured by registers CC6xSR if the selected capture event is detected depending on the selected mode CC6xRL 0 1 2 Capture Compare Register for Channel CC6x Low Byte Reset value 004 7 6 5 4 3 2 1 0 CC6xV7 0 X 0 1 2 rh CC6xRH X 0 1 2 Capture Compare Register for Channel CC6x High Byte Reset value 00 1 7 6 5 4 3 2 1 0 CC6xV15 8 X 0 1 2 r Field Bits Typ Description CC6xV 0 1 2 7 0 of irh Shadow Register for Channel x Capture CC6x Compare Value RL In compare mode the bitfields contents of CC6xS 7 0 of are transferred to the bitfields CC6xV during a CC6x shadow transfer In capture mode the captured RH value of T12 can be read from these registers User s Manual 4 62 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components CC6xSRL x 0 1 2 Capture Compare Shadow Register for Channel CC6x Low Byte Reset value 004 7 6 5 4 3 2 1 0 6 57 0 0 1 2 rwh CC6xSRH x 0 1 2 Capture Compare Shadow Register for Channel CC6x High Byte Reset value 004 7 6 5 4 3
147. k is detected the C868 starts operation Figure 5 2 V User s Manual 5 2 V 0 4 2002 01 _ 2 56 eunBiJj enuen 51950 seiBoJouuoe PLL lock 8980 94 JO 195 uo 19MOd 6 4 Reset active Reset active PLL lock reset gt ja until PLL lock remain active until Start of PLL lock for 4096 program continous cycles execution uone4edo uiejs S pue 10 2002 0 8989 _ Infineon C868 technologies Reset and System Clock Operation 5 3 Brownout An on chip analog circuit detects brownout if the supply voltage Vppc dips below the threshold voltage momentarily while RESET pin is high If this detection is active for tod usec then the device will reset When supply voltage Vppc recovers by exceeding Vrungsuorp While RESET is high the reset is released once PLL is locked for 4096 clocks Bit BO in the PMCONO register is set when brownout detected if brownout detection was enabled this bit is cleared by hardware reset RESET and software All ports are tristated during brownout The has a nominal value of 1 47V a minimum value of 1 1V and a maximum value of 1 8V PMCONO Wake up Control Register Reset value XXX000000g 7 6 5 4 3 2 1 0 EBO BO SDSTAT WS EWPD r r r rw rw rh rw rw The functions of the shaded bits are not d
148. l 7 17 V 0 4 2002 01 _ Infineon technologies C868 Interrupt System Field Type Description ICC60F ICC61F 62 rh Capture Compare Match Falling Edge Flag In compare mode a compare match has been detected while T12 was counting down In capture mode a falling edge has been detected at the input CC6x x 0 1 2 0 The event has not yet occurred since this bit has been reset for the last time 1 The event described above has been detected T120M rh Timer T12 One Match Flag 0 A timer T12 one match while counting down has not yet been detected since this bit has been reset for the last time 1 A timer T12 one match while counting down has been detected T12PM rh Timer T12 Period Match Flag 0 A timer T12 period match while counting up has not yet been detected since this bit has been reset for the last time 1 A timer T12 period match while counting up has been detected User s Manual 7 18 V 0 4 2002 01 _ Infineon technologies ISH Capture Compare Interrupt Register High Byte 7 868 6 5 Interrupt System Reset value 00 1 4 3 2 1 0 IDLE WHE CHE TRPS TRPF T13PM T13CM rh rh rh rh rh Field Bits Type Description T13CM rh Timer T13 Compare Match Flag 0 A timer T13 compare match has not yet been detected since this bit has been reset for the l
149. lag OV 2 rwh Overflow Flag Used by arithmetic instructions RSO 3 rw Register Bank select control bits RS1 4 These bits are used to select one of the four register banks Table 1 RS1 RSO Function 0 0 Bank 0 selected data address 005 074 0 1 Bank 1 selected data address 08p 0F 1 0 Bank 2 selected data address 10 17 1 1 Bank selected data address 18 1 FO 5 rw General Purpose Flag AC 6 rwh Auxiliary Carry Flag Used by instructions which execute BCD operations CY 7 rwh Carry Flag Used by arithmetic instructions User s Manual 2 4 V 0 4 2002 01 _ Infineon C868 technologies Fundamental Structure B Register The B register is used during multiply and divide and serves as both source and destination For other instructions it can be treated as another scratch pad register Stack Pointer The stack pointer SP register is 8 bits wide It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET RETI execution i e it always points to the last valid stack byte While the stack may reside anywhere in the on chip RAM the stack pointer is initialized to 074 after a reset This causes the stack to begin a location 084 above register bank zero The SP can be read or written under software control User s Manual 2 5 V 0 4 2002 01 Infineon C868 technologies Fundamental Structure 2 2 CPU Timin
150. ler family While maintaining all architectural and operational characteristics of the 8051 the C868 incorporates a CPU with 8 datapointers a 8 bit A D converter a 16 bit capture compare unit a 16 bit timer 2 that can be used as baudrate generator an interrupt structure with 2 priority levels built in PLL with a fixed factor of 15 and a variable divider an XRAM data memory as well as some enhancements in the Fail Save Mechanism Unit Figure 2 1 shows a block diagram of the C868 User s Manual 2 1 V 0 4 2002 01 mn Infineon technologies C868 Fundamental Structure XRAM RAM 256 x8 256x8 RESET Capture Compare Unit 4 external interrupts VAREF A D Converter VAGND 8 Bit 5 Bit Analog In ROM RAM 8kx8 digital Port 3 8 bit digital Figure 2 1 Block Diagram of the C868 User s Manual 2 2 V 0 4 2002 01 _ Infineon C868 technologies Fundamental Structure 2 1 CPU The C868 is efficient both as a controller and as an arithmetic processor It has extensive facilities for binary and BCD arithmetic and excels in its bit handling capabilities Efficient use of program memory results from an instruction set consisting of 4496 one byte 4196 two byte and 15 three byte instructions With a 10 67 MHz external crystal giving a 40MHz CPU clock 58 of the instructions execute in 300 ns The CPU Central Processing Unit of the C868 consists of the instruction dec
151. lue T12 This register represents the 16 bit counter value of CVL Timer12 7 0 of T12 CVH User s Manual 4 59 V 0 4 2002 01 _ Infineon C868 technologies Note Note User s On Chip Peripheral Components While timer T12 is stopped the internal clock divider is reset in order to ensure reproducible timings and delays The timer period compare values passive state selects bits and passive levels bits for both timers are written to shadow registers and not directly to the actual registers Thus the values for a new output signal can be programmed without disturbing the currently generated signal s The transfer from the shadow registers to the actual registers is enabled by setting the respective shadow transfer enable bit STEx If the transfer is enabled the shadow registers are copied to the respective registers as soon as the associated timer reaches the value zero the next time being cleared in edge aligned mode or counting down from 1 in center aligned mode When timer T12 is operating in center aligned mode it will also copy the registers if enabled by STE12 if it reaches the currently programmed period value counting up When a timer is stopped 0 the shadow transfer takes place immediately if the corresponding bit STEx is set After the transfer the respective bit STEx is cleared automatically Manual 4 60 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral
152. n mode should not be done before and is restored to its nominal operating level The software power down mode is entered by setting bit PDE PCON 1 Note Before entering the power down mode an A D conversion in progress must be stopped 8 5 1 Exit from Software Power Down Mode If power down mode is exit via a hardware reset the microcontroller with its SFRs is put into the hardware reset state and the content of RAM and XRAM are not changed The reset signal that terminates the power down mode also restarts the on chip oscillator and the PLL The reset operation should not be activated before and is restored to its normal operating level Figure 8 1 shows the behaviour when power down mode is left via the INTO or the RXD wake up capability User s Manual 8 6 V 0 4 2002 01 _ Infineon C868 technologies Power Saving Modes Execution of PLL interrupt at Power Down On chip Oscillator Locked 007B Mode Start up Phase Phase typ 10 ms RETI Instruction Figure 8 1 Wake up from Power Down Mode Procedure When the power down mode wake up capability has been enabled bit EWPD in SFR PMCONO set prior to entering power down mode and bit WS in SFR PMCONO is cleared the power down mode can be exit via INTO while executing the following procedure 1 In power down mode pin INTO must be held at high level 2 Power down mode is left when INTO goes low latch phase After this delay the on c
153. n on Fixed Channel 10 Reserved 11 Reserved Bit 4 is used for mode selection while bit 5 is reserved ADBSY 6 rh Busy Flag 1 Conversion is in progress ADST 7 rw A D Conversion Start Bit Set by user to begin a conversion Cleared by hardware at the beginning of conversion For continuous conversion this bit is cleared at the beginning of first conversion 3 r reserved returns 0 if read should be written with 0 User s Manual 4 115 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components ADCON1 A D Converter Control Register 1 Reset value X1XX0000g 7 6 5 4 3 2 1 0 CAL ADSTC ADCTC r rh r r rw rw Field Bits Typ Description ADCTC 1 0 rw ADC Conversion Time Control ADSTC 3 2 rw ADC Sample Time Control CAL 6 rh Calibrate Indication This bit will be 1 after power on during the calibration phase before returning to 0 s 7 5 4 reserved returns 0 if read should be written with 0 The ADDATH register stores the result of the conversion together with the channel number ADDATH A D Converter Data Register Reset value 00 1 7 6 5 4 3 2 1 0 ADDATH rwh Field Bits Typ Description ADDATH 7 0 rwh Result of ADC conversion User s Manual 4 116 V 0 4 2002 01 mn Infineon technologies C8
154. nal Enable Control 0 External events are disabled 1 External events Capture Reload enabled TCLK 4 rw Transmit Clock Enable 0 Timer counter 2 overflow is not used for UART transmitter clock 1 Timer counter 2 overflow is used for UART transmitter clock RCLK 5 rw Receiver Clock Enable 0 Timer counter 2 overflow is not used for UART receiver clock 1 Timer counter 2 overflow is used for UART receiver clock User s Manual 4 20 V 0 4 2002 01 mn Infineon technologies C868 On Chip Peripheral Components Field Bits Typ Description EXF2 rwh Timer counter 2 External Flag This bit is set by hardware when a capture reload occurred upon a negative transition at pin T2EX if bit EXEN 1 An interrupt request to the core is generated unless bit DCEN 1 This bit must be cleared by software TF2 Timer counter 2 Overflow Flag Set by a timer counter 2 overflow Must be cleared by software TF2 will not be set when either RCLK 1 or TCLK 1 User s Manual 4 21 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components The RC2L H registers are used for a 16 bit reload of the timer counter count upon overflow or a capture of current timer counter count depending on the mode selected RC2L Timer 2 Reload Capture Register Low Byte Reset value 00 1 7 6 5 4 3 2 1 0 RC2 7 0 rw RC2H Timer 2 Reload Captu
155. nal hardware and forces the controller to a predefined default state The hardware reset function can also be used during normal operation in order to restart the device This is particularly done when the power down mode is to be terminated Additional to the hardware reset which is applied externally to the C868 there are three internal reset sources the watchdog timer the brownout and the PLL This chapter deals only with the external hardware reset and brownout The reset input is an active low input An internal Schmitt trigger is used at the input for noise rejection The RESET pin must be held low for at least tbd usec But the CPU will only exit from reset condition after the PLL lock had been detected During RESET at transition from low to high C868 will go into normal mode if ALE BSL is high and bootstrap loading mode if ALE BSL is low A pullup to Vppp is recommended for pin ALE BSL TXD should have a pullup to and should not be stimulated externally during reset as a logic low at this pin will cause the chip to go into test mode if ALE BSL is low At the RESET pin a pullup resistor is connected to Vppp and a capacitor is connected to ground to allow a power up reset After Vppp has been turned on the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset User s Manual 5 1 V 0 4 2002 01 Infineon C868 technologies Reset and System Clock Operation
156. nsition to a wrong hall event not the expected one has been detected IDLE 6 rh IDLE State This bit is set together with bit WHE wrong hall event and it has to be reset by SW 0 No action 1 Bitfield MCMP is cleared the selected outputs are set to passive state 7 r reserved returns 0 if read should be written with 0 During the trap state the selected outputs are setto the passive state The logic level driven during the passive state is defined by the corresponding bit in register COMCON Bit TRPS 1 and TRPF 0 can occur if the trap condition is no longer active but the selected synchronization has not yet taken place On every valid hall edge the contents of CURH is compared with the pattern on pin CCPOSx and if equal bit CHE is set On every valid hall edge the contents of EXPH is compared with the pattern on pin CCPOSx If both compares CURH and EXPH with CCPOSx are not true bit WHE wrong hall event is set 4 Bit field MCMP is hold to 0 by hardware as long as IDLE 1 2 3 Note Not all bits in register IS can generate an interrupt Other status bits have been added which have a similar structure for their set and reset actions Note The interrupt generation is independent from the value of the bits in register IS e g the interrupt will be generated if enabled even if the corresponding bit is already set The trigger for an interrupt generation is the detection
157. nstead of Hall sensors The compare value in channel 2 can be used as a time out trigger interrupt indicating that the motors destination speed is far below the desired value which can be caused by a abnormal load change In this mode the modulation of T12 has to be disabled T12MODENXx 0 CC60 capture event resets T12 CCPOSO CCPOS1 CCPOS2 CC6x COUTS6y Figure 4 35 Timer T12 Brushless DC Mode MSEL6x 1000 User s Manual 4 57 V 0 4 2002 01 aem Infineon s technologies On Chip Peripheral Components 4 7 7 Interrupt Generation The interrupt structure is shown in Figure 4 36 The interrupt event or the corresponding interrupt set bit in register ISS can trigger the interrupt generation The interrupt pulse is generated independently from the interrupt flag in register IS The interrupt flag can be reset by SW by writing to the corresponding bit in register ISR If enabled by the related interrupt enable bit in register IEN an interrupt pulse can be generated at one of the four interrupt output lines of the module length 2 clock cycles If more than one interrupt source is connected to the same interrupt node pointer in register INP the requests are combined to one common line int reset SW int event int set SW other interrupt sources on the same INP Figure 4 36 Interrupt Generation 4 7 8 Module Powerdown The CCU6 is disabled when the chip goes into the powerdown mode as descr
158. o that the watchdog times out if the program does not work properly It also times out if a software error is based on hardware related problems The watchdog timer in the C868 is a 16 bit timer which is incremented by a count rate Of fsys 2 upto fs 4 128 The machine clock of the C868 is divided by a prescaler a divide by two or a divide by 128 prescaler The upper 8 bits of the Watchdog Timer can be preset to a user programmable value via a watchdog service access in order to vary the watchdog expire time The lower 8 bits are reset on each service access Figure 6 1 shows the block diagram of the watchdog timer unit WDT WDTREL Control Clear WDT Low Byte WDTRST fas WDT High Byte DISWDT WDTIN Figure 6 1 Block Diagram of the Programmable Watchdog Timer 6 1 1 Register Definition of the Watchdog Timer The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT which is a non bitaddressable read only register The operation of the Watchdog Timer is controlled by its bitaddressable Watchdog Timer Control Register User s Manual 6 1 V 0 4 2002 01 _ Infineon C868 technologies Fail Save Mechanism WDTCON This register specifies the reload value for the high byte of the timer and selects the input clock prescaling factor WDTREL Watchdog Timer Reload Register Reset value 00 1 7 6 5 4 3 2 1 0 W
159. ocations The stack can be located anywhere in the internal data memory address space and the stack depth can be expanded up to 256 bytes The internal XRAM is located in the in the external data memory area and must be accessed by external data memory instructions MOV X 3 2 1 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers GPRs each Only one of these banks may be enabled at a time Two bits in the program status word RS0 and RS1 select the active register bank This allows fast context switching which is useful when entering subroutines or interrupt service routines The 8 general purpose registers of the selected register bank may be accessed by register addressing With register addressing the instruction opcode indicates which register is to be used For indirect addressing RO and R1 are used as pointer or index register to address internal or external memory e g MOV 9RO User s Manual 3 2 V 0 4 2002 01 _ Infineon C868 technologies Memory Organization Reset initializes the stack pointer to location 07 and increments it once to start from location 08 which is also the first register RO of register bank 1 Thus if one is going to use more than one register bank the SP should be initialized to a different location of the RAM which is not used for data storage 3 3 Program and Data Memory Organisation The C868 can opera
160. oder the arithmetic section and the program control section Each program instruction is decoded by the instruction decoder This unit generates the internal signals controlling the functions of the individual units within the CPU These internal signals have an effect on the source and destination of data transfers and control the ALU processing The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic logic unit ALU an A register B register and PSW register The ALU accepts 8 bit data words from one or two sources and generates an 8 bit result under the control of the instruction decoder The ALU performs the arithmetic operations add substract multiply divide increment decrement BCD decimal add adjust and compare and the logic operations AND OR Exclusive OR complement and rotate right left or swap nibble left four Also included is a Boolean processor performing the bit operations as set clear complement jump if set jump if not set jump if set and clear and move to from carry Between any addressable bit or its complement and the carry flag the ALU can perform the bit operations of logical AND or logical OR with the result returned to the carry flag The program control section controls the sequence in which the instructions stored in program memory are executed The 16 bit program counter PC holds the address of the next instruction to be executed The conditional
161. of a set condition by HW or SW for the corresponding bit in register IS Note In compare mode and hall mode the timer related interrupts are only generated while the timer is running 1 In capture mode the capture interrupts are also generated while the timer T12 is stopped User s Manual 7 20 V 0 4 2002 01 _ Infineon C868 technologies Interrupt System Register ISS contains the individual interrupt request set bits to generate a CCU6 interrupt request by software ISSL Capture Compare Interrupt Status Reset Register Low Byte Reset value 004 7 6 5 4 3 2 1 0 ST12PM ST120M SCC62F SCC62R SCC61F SCC61R SCC60F SCC60R Field Bits Description SCC60R 0 w Set Capture Compare Match Rising Edge Flag 0 No action 1 Bit CC60R in register IS will be set SCC60F 1 Ww Set Capture Compare Match Falling Edge Flag 0 No action 1 Bit CC60F in register IS will be set SCC61R 2 w Set Capture Compare Match Rising Edge Flag 0 No action 1 Bit CC61R in register IS will be set SCC61F 3 Ww Set Capture Compare Match Falling Edge Flag 0 No action 1 Bit CC61F in register IS will be set SCC62R 4 Ww Set Capture Compare Match Rising Edge Flag 0 No action 1 Bit CC62R in register IS will be set SCC62F 5 Ww Set Capture Compare Match Falling Edge Flag 0 No action 1 Bit CC62F in register IS will be set ST120M 6 Ww Set Timer
162. ogies On Chip Peripheral Components 0 passive state ECT13O 1 active state COUTS63 T13 o to output TRPEN13 pin COUT63 Figure 4 33 Modulation Control of the T13 related Output COUT63 Note In order to avoid spikes on the output lines the seven output signals CC60 COUT60 CC61 COUT61 CC62 COUT62 COUT63 are registered out with the peripheral clock 4 7 6 Hall Sensor Mode In Brushless DC motors the next multi channel state values depend on the pattern of the Hall inputs There is a strong correlation between the Hall pattern CURH and the modulation pattern MCMP Because of different machine types the modulation pattern for driving the motor can be different Therefore it is wishful to have a wide flexibility in defining the correlation between the Hall pattern and the corresponding modulation pattern The CCU6 offers this by having a register which contains the actual Hall pattern CURHS the next expected Hall pattern EXPHS and its output pattern MCMPS At every correct Hall event CHE see figure Hall Event Actions a new Hall pattern with its corresponding output pattern can be loaded from a predefined table by software into the register MCMOUTS Loading this shadow register can also be done by a write action on MCMOUTS with bit STRHP 1 The sampling of the Hall pattern on CCPOSx is done with the T12 clock By using the dead time counter mode MSEL6x 71000 a hardware noise filter can
163. or timer 1 which may be combined to one timer configuration depending on the mode that is established The functions of the timers are controlled by two special function registers TCON and TMOD In the following descriptions the symbols THO and TLO are used to specify the high byte and the low byte of timer 0 TH1 and TL1 for timer 1 respectively The operating modes are described and shown for timer 0 If not explicity noted this applies also to timer 1 User s Manual 4 9 V 0 4 2002 01 Infineon C868 technologies On Chip Peripheral Components 4 5 1 1 Timer 0 and 1 Registers Totally seven special function registers control the timer 0 and 1 operation TLO THO and TL1 TH1 timer registers low and high part TCON and IENO control and interrupt enable TMOD mode select TLx x 0 1 Timer x Low Register Reset value 00 1 7 6 5 4 3 2 1 0 TLx7 0 rwh THx x 0 1 Timer x High Register Reset value 00 1 7 6 5 4 3 2 1 0 THx7 0 rwh Field Bits Typ Description TLx 7 0 x 0 1 7 0 rwh Timer counter 0 1 low register Operating Description Mode 0 TLx holds the 5 bit prescaler value 1 TLx holds the lower 8 bit part of the 16 bit timer counter value 2 TLx holds the 8 bit timer counter value 3 TLO holds the 8 bit timer counter value TL1 is not used User s Manual 4 10 V 0 4 2002 01 _ Infineon
164. other flags are T120M T12PM T13CM T13PM WHE CHE Within a column the topmost interrupt is serviced first then the second and the third when available The interrupt groups are serviced from left to right of the table A low priority interrupt can itself be interrupted by a higher priority interrupt but not by another interrupt of the same or a lower priority An interrupt of the highest priority level cannot be interrupted by another interrupt source If two or more requests of different priority levels are received simultaneously the request of the highest priority is serviced first If requests of the same priority level are received simultaneously an internal polling sequence determines which request is to be serviced first Thus within each priority level there is a second priority structure which is illustrated in table 7 10 The priority within level structure is only used to resolve simultaneous requests of the same priority level User s Manual 7 33 V 0 4 2002 01 Infineon C868 technologies Interrupt System 7 4 How Interrupts are Handled The interrupt flags are sampled at S5P2 in each machine cycle The sampled flags are polled during the following machine cycle If one of the flags was in a set condition at S5P2 of the preceeding cycle the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine provided this hardware generated LCALL is not
165. owever does not generate an interrupt request Note In counter mode if the reload via T2EX and the count clock T2 are detected simultaneously the reload takes precedence over the count The counter increments its value with the following T2 count clock C T2 0 C T2 1 9 in T2 Competitor Overflow RC2L H T2EX Figure 4 7 Auto Reload Mode 1 User s Manual 4 27 V 0 4 2002 01 am Infineon C668 technologies On Chip Peripheral Components 4 6 6 Capture Mode In order to enter the 16 bit capture mode bits CP RL2 and 2 in register T2CON must be set In this mode the down count function must remain disabled The timer counter functions as 16 bit timer or counter and always counts up to and overflows Upon an overflow condition bit TF2 is set and the timer counter reloads its registers with 0000 The setting of TF2 generates an interrupt request to the core Additionally with a falling edge on pin T2EX the contents of the timer counter registers T2L H are captured into the RC2L H registers If the capture signal is detected while the counter is being incremented the counter is first incremented before the capture operation is performed This ensures that the latest value of the timer counter registers are always captured When the capture operation is completed bit EXF2 is set and can be used to generate an interrupt request Figure 4 8 describes the capt
166. own mode 8 6 8 7 Exit wake up procedure 8 6 PROT 3 20 PSLO 3 15 PSL1 3 15 PSL2 3 15 PSL3 3 15 PSL4 3 15 PSL5 3 15 PSL63 3 15 PSLRL 3 13 3 15 PSW 2 3 3 10 3 17 R R 3 18 User s Manual V 0 4 2002 01 _ Infineon technologies C868 RB8 3 15 4 101 RC2H 3 11 3 17 RC2L 3 11 3 17 RCC6 3 16 RCHE 3 16 RCLK 3 17 RELO 3 14 REL1 3 14 REL2 3 14 3 3 14 REL4 3 14 REN 3 15 Reset 5 1 Fast power on reset 5 2 Reset circuitries 5 2 RI 3 15 4 101 RIDLE 3 16 RMAP 3 15 RSO 3 17 RS1 3 17 RT120 3 16 RT12P 3 16 RT13C 3 16 RT13P 3 16 RTRP 3 16 RWHE 3 16 RxD 3 15 S SBUF 3 10 3 15 4 101 SCC62 3 16 SCHE 3 16 SCON 3 10 3 15 4 101 SCUW 3 16 SCUWDT 3 10 SD 3 14 SDST 3 14 Serial interface USART 4 100 4 113 Baudrate generation 4 103 with internal baud rate generator 4 104 with timer 1 4 105 Multiprocessor communication 4 101 Operating mode 1 4 106 4 109 User s Manual 8 V 0 4 2002 01 _ Infineon technologies C868 Operating mode 2 and 3 4 110 4 113 Registers 4 101 SIDLE 3 16 Slow Down Mode 5 8 SMO 3 15 5 1 3 15 SM2 3 15 SMOD 3 14 Software Unlock Sequence 3 8 SP 2 5 3 10 3 14 Special Function Registers Table address ordered 3 14 Table functional order 3 10 SSCCON 4 25 ST120 3 16 ST12P 3 16 ST13C 3 16 ST13P 3 16 STE12 3 18 STRH 3 18 STRM 3 18 STRP 3 16 Summary of Basic Features 1 2 SWAP 3 15 SWAP Mode 3 6 SWC 3 15 SWHE 3
167. pecial function registers 2 X means that the value is undefined and the location is reserved 3 Register is mapped by bit RMAP in SYSCONO 4 1 4 Register is mapped by bit RMAP in SYSCONO 4 0 User s Manual 3 11 V 0 4 2002 01 _ Infineon technologies C868 Memory Organization Table 3 6 Special Function Registers Functional Blocks cont d Block Symbol Name Add Contents ress after Reset Cap T12L Timer T12 Counter Register Low Byte ECy 00 4 ture T12H Timer T12 Counter Register High Byte ED 00 Com T13L Timer T13 Counter Register Low Byte EE 00 pare T13H Timer T13 Counter Register High Byte EF 00 Unit T12PRL Timer T12 Period Register Low Byte DE 00 T12PRH Timer T12 Period Register High Byte DFy 00 T13PRL Timer T13 Period Register Low Byte D24 00 T13PRH Timer T13 Period Register High Byte D34 00 CC60RL Capture Compare Ch 0 Reg Low Byte C2 00 CC60RH Capture Compare Ch 0 Reg High Byte C3 00 CC61RL Capture Compare Ch 1 Reg Low Byte 00 CC61RH Capture Compare Ch 1 Reg High Byte C5 00 CC62RL Capture Compare Ch 2 Reg Low Byte C64 00 CC62RH Capture Compare Ch 2 Reg High Byte C7 00 CC63RL T13 Compare Register Low Byte D44 00 CC63RH T13 Compare Register High Byte D5y 004 T12DTCL Timer T12 Dead Time Ctrl Low Byte E6 00 T12DTCH Timer T12 Dead Time Ctrl High Byte E74 00 CMPSTATL Compare Timer Status Low Byte F44
168. port 3 as follows P3 0 COUT63 16 bit compare channel output P3 1 CTRAP CCU trap input P3 2 COUT62 Output of capture compare ch 2 P3 3 CC62 Input output of capture compare ch 2 P3 4 COUT61 Output of capture compare ch 1 P3 5 CC61 Input output of capture compare ch 1 P3 6 COUT60 Output of capture compare ch 0 P3 7 CC60 Input output of capture compare ch 0 Reference voltage for the A D converter VacNp 18 14 Reference ground for the A D converter l Input O Output User s Manual 1 5 V 0 4 2002 01 mn Infineon technologies C868 Introduction Table 1 1 Pin Definitions and Functions Symbol Pin Numbers Function P P DSO TSSOP 28 38 AN4 21 17 Analog Input Channel 4 is input channel 4 to the ADC unit AN3 20 16 Analog Input Channel 3 is input channel 3 to the ADC unit CCPOSO 17 13 External Interrupt 2 Input INT2 AN2 Analog Input Channel 2 Multiplexed external interrupt input or Hall input signal and input channel 2 to the ADC unit CCPOS1 16 12 Timer 2 Trigger External Interrupt 1 Input T2EX Analog Input Channel 1 INT1 AN1 Multiplexed external interrupt input or Hall input signal input channel 1 to the ADC unit trigger to Timer 2 CCPOS0 15 11 Input to Counter 2 External Interrupt 0 Input T2 INTO Analog Input Channel 0 ANO Multiplexed external interrupt input or Hall input signal counter 2 input or
169. r T12 Single Shot Control This bit controls the single shot mode of T12 0 The single shot mode is disabled no HW action on T12R 1 The single shot mode is enabled the bit T12R is reset by HW if T12 reaches its period value in edge aligned mode T12 reaches the value 1 while down counting in center aligned mode In parallel to the reset action of bit T12R the bits CC6xST x20 1 2 are reset T13SSC 1 rw Timer T13 Single Shot Control This bit controls the single shot mode of T13 0 No HW action on T13R 1 The single shot mode is enabled the bit T13R is reset by HW if T13 reaches its period value In parallel to the reset action of bit T13R the bit CC6SST is reset User s Manual 4 78 V 0 4 2002 01 _ Infineon technologies C868 On Chip Peripheral Components Field Bits Type Description T13TEC 4 2 rw T13 Trigger Event Control Bitfield T13TEC selects the trigger event to start T13 automatic set of T13R for synchronization to T12 compare signals according to following combinations 000 no action 001 set T13R ona T12 compare event on channel 0 010 set T13R ona T12 compare event on channel 1 011 set 1 ona T12 compare event on channel 2 100 set T13R on any T12 compare event ch 0 1 2 101 set T13R upon a period match of T12 110 set T13R upon a zero match of T12 while counting up 111 set T13R on any hall state change T13TED 6 5 Timer
170. r for Channel CC63 High Byte Reset value 004 7 6 5 4 3 2 1 0 CC63V15 8 rh Field Bits Typ Description CC63V 7 0 of irh Channel CC63 Compare Value CC63 The bitfield CC63V contains the value that is RL compared to the T13 counter value 7 0 of CC63 RH User s Manual 4 68 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components CC63SRL Compare Shadow Register for CC63 Low Byte Reset value 004 7 6 5 4 3 2 1 0 CC63S7 0 rw CC63SRH Compare Shadow Register for CC63 High Byte Reset value 00 1 7 6 5 4 3 2 1 0 CC63S15 8 rw Field Bits Typ Description CC63S 7 0 of rw Shadow Register for Channel CC63 Compare CC63 Value SRL The bitfield contents of CC638 is transferred to the 7 0 of bitfield CC63V during a shadow transfer CC63 SRH User s Manual 4 69 V 0 4 2002 01 Infineon technologies Capture Compare Control Registers The Compare State Register CMPSTAT contains status bits monitoring the current capture and compare state and control bits defining the active passive state of the C868 On Chip Peripheral Components compare channels CMPSTATL Compare State Register Low Byte Reset value 00 1 7 6 5 4 3 2 1 0 CC63ST CC62ST CC61ST CC60ST r rh r r r rh rh rh Field Bits Typ Description CC60ST 0 rh Capture Compare State Bits CC61ST 1 Bits CC6xST monitor t
171. r r r rwh rwh Field Bits Typ Description EXINT2 0 rwh Interrupt Request Flag for External Interrupt 2 0 Interrupt request is not active cleared by software default 1 Interrupt request is active set by hardware User s Manual 7 12 V 0 4 2002 01 _ Infineon C868 technologies Interrupt System Field Bits Typ Description EXINT3 1 rwh Interrupt Request Flag for External Interrupt 3 0 Interrupt request is not active cleared by software default 1 Interrupt request is active set by hardware 7 2 reserved returns 0 if read should be written with 0 The external interrupt 2 and 3 CCPOS2 INT2 AN2 P1 3 INT3 can be either positive or negative transition activated depending on the bits register EXICON The flags that actually generates this interrupt are bits EXINT2 and EXINTS in register IRCONO When processing the external interrupts flags must be cleared by software EXICON External Interrupt Control Register Reset value XXXXXX00g 7 6 5 4 3 2 1 0 ESEL3 ESEL2 r r r r r r rw rw Field Bits Typ Description ESEL2 7 0 rw External Interrupt 2 Edge Trigger Select 0 Interrupt on falling edge default 1 Interrupt on rising edge ESEL3 7 0 rw External Interrupt 3 Edge Trigger Select 0 Interrupt on falling edge default 1 Interrupt on rising edge 7 2 r reserved return
172. r rh rh Field Bits Type Description 5 0 rh Multi Channel PWM Pattern Bitfield MCMP is written by a shadow transfer from bitfield MCMPS It contains the output pattern for the multi channel mode If this mode is enabled by bit MCMEN in register MODCTR the output state of the following output signal can be modified bitO multi channel state for output CC60 bit 1 multi channel state for output COUT60 bit 2 multi channel state for output CC61 bit 3 multi channel state for output COUT61 bit 4 multi channel state for output CC62 bit5 multi channel state for output COUT62 The multi channel patterns can set the related output to the passive state 0 The output is set to the passive state The PWM generated by T12 or T13 are not taken into account 1 The output can deliver the PWM generated by T12 or T13 according to register MODCTR User s Manual 4 90 V 0 4 2002 01 _ Infineon technologies C868 On Chip Peripheral Components Field Bits Type Description rh Reminder Flag This reminder flag indicates that the shadow transfer from bitfield MCMPS to MCMP has been requested by the selected trigger source This bit is cleared when the shadow transfer takes place and while MCMEN 0 0 Currently no shadow transfer from MCMPS to MCMP is requested 1 A shadow transfer from MCMPS to MCMP has been requested by the selected trigger source but it has not yet been executed
173. r the A D conversion interrupt In continuous conversion mode ADM must be cleared and the last A D conversion must be terminated before entering the power down mode User s Manual 4 118 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components 4 11 Conversion and Sample Time Control The conversion and sample times are programmed via the bit fields ADCTC and ADSTC respectively of the register ADCON1 Bit field ADCTC conversion time control selects the internal ADC clock adc clk Bit field ADSTC sample time control selects the sample time The data in ADCTC and ADSTC can be modified while a conversion is in progress but will only be evaluated after the current conversion has completed Thus the change will only affect the subsequent conversion The internal ADC clock is derived from the peripheral clock fsys according to adc clk fsys clock divider Please note that the clock divider must be selected such that adc clk does not exceed 2MHz The A D conversion procedure is divided into four parts Synchronizing phase tsync delay before actual conversion commence Sample phase ts used for sampling the analog input voltage Conversion phase tco used for the real A D conversion includes calibration Write result phase twp used for writing the conversion result into the ADDAT registers The total A D conversion time is defined by which is the sum of the four phase
174. re Register High Byte Reset value 00 1 7 6 5 4 3 2 1 0 RC2 15 8 rw Field Bits Typ Description RC2 7 0 of rw Reload Capture Value RC2L These contents are loaded into the timer counter 7 0 of registers upon an overflow condition if CP RL2 0 If RC2H CP RL2 1 this registers are loaded with the current timer count upon a negative transition at pin T2EX when EXEN2 1 User s Manual 4 22 V 0 4 2002 01 mn Infineon C868 technologies On Chip Peripheral Components The T2L H registers holds the current 16 bit value of the Timer 2 count T2L Timer 2 Low Byte Reset value 00 7 6 5 4 3 2 1 0 T2 7 0 r T2H Timer 2 High Byte Reset value 00 1 7 6 5 4 3 2 1 0 T2 15 8 1 1 rh 1 Field Bits Typ Description T2 7 0 of rh Timer 2 Value T2L These bits indicate the current timer value 7 0 of T2H User s Manual 4 23 V 0 4 2002 01 Infineon technologies T2DIS in PMCON register controls the powerdown of timer counter 2 T2ST in 2 shows the power status of timer counter 2 C868 On Chip Peripheral Components 1 Peripheral Management Control Register Reset value XXXXX000g 7 6 5 4 3 2 1 0 CCUDIS T2DIS ADCDIS r r r r r rw rw rw The functions of the shaded bits are not described here Field Bits Typ D
175. read should be written with 0 User s Manual 7 30 V 0 4 2002 01 Infineon C868 technologies Interrupt System 7 2 4 Interrupt Priority Registers The lower six bits of these two registers are used to define the interrupt priority level of the interrupt groups as they are defined in Table 7 2 in the next section IPO Interrupt Priority Register 0 Reset value XX000000g BF BE BD BC BB BA B9 B84 IPO r r rw Field Bits Typ Description IPOx 5 0 rw Interrupt group priority level bits x 0 5 0 Interrupt group x is set to priority level 0 lowest 1 Interrupt group x is set to priority level 1 highest 7 6 reserved returns 0 if read should be written with 0 User s Manual 7 31 V 0 4 2002 01 _ Infineon C868 technologies Interrupt System 7 3 Interrupt Priority Level Structure The 13 interrupt sources of the C868 are grouped according to the listing in Table 7 1 Table 7 1 Interrupt Source Structure Interrupt Associated Interrupts Group 0 External interrupt A D converter 0 interrupt 1 Timer 0 Overflow External interrupt 2 2 External interrupt External interrupt Capture compare 1 3 interrupt node 0 3 Timer 1 overflow Capture compare interrupt node 1 4 Capture compare Serial interrupt interrupt node 2 5 Timer 2 overflow Capture compare interrupt node 3 Each
176. register CC6xSR or tr SR R transfer contents of CC6xSR to register CC6xR are activated Note In capture mode a shadow transfer can be requested according to the shadow transfer rules except for the capture compare registers that are left unchanged 4 7 1 10 Single Shot Mode In single shot mode the timer T12 stops automatically at the end of the its counting period Figure 4 24 shows the functionality at the end of the timer period in edge aligned User s Manual 4 44 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components and in center aligned mode If the end of period event is detected while bit T12SSC is set the bits T12R and all CC6xST bits are reset edge aligned mode center aligned mode period match T12P while counting up one match while if T12SSC 1 counting down T12 1255 1 T12 T12R T12R CC6xST Figure 4 24 End of Single Shot Mode of T12 User s Manual 4 45 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components 4 7 1 11 Hysteresis Like Control Mode The hysteresis like control mode MSEL6x 1001 offers the possibility to switch off the PWM output if the input CCPOSx becomes 0 by resetting bit CC6xST This can be used as a simple motor control feature by using a comparator indicating e g over current While CCPOSx 0 the PWM outputs of the corresponding channel are driving their passive levels The
177. rrupt Status Reset Register High Byte Reset value 00 1 7 6 5 4 3 2 1 0 RIDLE RWHE RCHE RTRPF RT13PM RT13CM r r Field Bits Type Description RT13CM 0 Ww Reset Timer T13 Compare Match Flag 0 No action 1 Bit T13CM in register IS will be reset RT13PM 1 Reset Timer 13 Period Match Flag 0 No action 1 Bit T13PM in register IS will be reset RTRPF 2 Reset Trap Flag 0 No action 1 Bit TRPF in register IS will be reset not taken into account while input CTRAP 0 and TRPPEN 1 RCHE 4 w Reset Correct Hall Event Flag 0 No action 1 Bit CHE in register IS will be reset RWHE 5 Ww Reset Wrong Hall Event Flag 0 No action 1 Bit WHE in register IS will be reset RIDLE 6 Ww Reset IDLE Flag 0 No action 1 Bit IDLE in register IS will be reset 3 7 r reserved returns 0 if read should be written with 0 User s Manual 7 24 V 0 4 2002 01 _ Infineon technologies C868 Interrupt System Register IEN contains the interrupt enable bits and a control bit to enable the automatic idle function in the case of a wrong hall pattern IENL Capture Compare Interrupt Enable Register Low Byte Reset value 00 1 7 6 5 4 3 2 1 0 ENT12PM ENT12OM ENCC62F ENCC62R ENCC61F ENCC61R ENCC60F ENCC60R rw rw rw rw rw rw rw rw Field Bits Description ENCC60R 0 rw Capture Compare Match
178. rt devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered C868 8 Bit CMOS Microcontroller Infineon technologies thinking C868 Revision History 2002 01 V 0 4 Previous Version Page Subjects major changes since last revision Controller Area Network CAN License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com Ea _ Infineon C868 technologies 1 INTOGUCHION xu ens dated SQ S E EE lei ol ce ee eee ee 1 1 1 1 Summary of Basic Features 1 2 1 2 pene MM PEUT 1 4 1 3 Pin Definitions and Functions 1 5 2 Fundamental Structure 2 1 2 1 ri M e P weet haa aed ce a el ies 2 3 2 2 2 6 3 Memory Organization 3 1 3 1 Program Memory Code 3 2 3 2 Data Memory Data Space
179. rt 1 Alternate Function Switch P1ALT 4 3 4 3 0 The associated pin is a normal I O default 1 The associated pin is an alternate function Please see Table 4 2 All the other bits in this register are reserved for the future use 7 5 2 r reserved returns 0 if read should be written with 0 P3ALT Port 3 Alternate Function Register Reset value 00 1 7 6 5 4 3 2 1 0 P3ALT 1 AW Field Bits Typ Description P3ALT 7 0 rw Port 3 Alternate Function Switch 0 The associated pin is a normal I O default 1 The associated pin is an alternate function Please see Table 4 2 User s Manual 4 5 V 0 4 2002 01 mn Infineon C868 technologies On Chip Peripheral Components 4 3 Dedicated Ports Beside I O Port the rest of the ports are dedicated ports These dedicated ports do not require bit latches as it uses the alternate access ANALOG 4 0 These are pure analog inputs to the ADC module The signals from the pin should be rightaway directed to the ADC module These pins are used as digital input for the interrupts hall inputs to the CCU6 module and inputs to the timer 2 module User s Manual 4 6 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components 4 4 Port 1 Port 3 Circuitry The pins of ports 1 and 3 are multifunctional They are port pins and also serve to implement special features as listed in Table 4 2 Figure 4 1 shows a functional diagram
180. rt Registers The serial port control and status register is the special function register SCON This register contains not only the mode selection bits but also the 9th data bit for transmit and receive TB8 and RB8 and the serial port interrupt bits and RI SBUF is the receive and transmit buffer of serial interface Writing to SBUF loads the transmit register and initiates transmission Reading out SBUF accesses a physically separate receive register SBUF Serial Data Buffer Register Reset value 00 1 7 6 5 4 3 2 1 0 SBUF 1 1 AW Field Bits Typ Description SBUF 7 0 rw Serial Interface Buffer Register User s Manual 4 101 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components SCON Serial Channel Control Register Reset value 00 1 OF y 9Ey By 99 98 SMO SM1 SM2 REN TB8 RB8 TI RI rw rw rw rw rw rw rw rw Field Bits Typ Description RI 0 rw Serial port receiver interrupt flag is set by hardware at the end of the 8th bit time in mode 0 or halfway through the stop bit time in the other modes in any serial reception exception see 5 2 RI must be cleared by software Tl 1 rw Serial port transmitter interrupt flag Tl is set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes in any serial transmission must be clear
181. rw rw Field Bits Type Description EXPHS 2 0 rw Expected Hall Pattern Shadow Bitfield EXPHS is the shadow bitfield for bitfield EXPH The bitfield is transferred to bitfield EXPH if an edge on the hall input pins CCPOSx x 0 1 2 is detected CURHS 5 3 rw Current Hall Pattern Shadow Bitfield CURHS is the shadow bitfield for bitfield CURH The bitfield is transferred to bitfield CURH if an edge on the hall input pins CCPOSx x 0 1 2 is detected STRHP 7 Ww Shadow Transfer Request for the Hall Pattern Setting this bits during a write action leads to an immediate update of bitfields CURH and EXPH by the value written to bitfields CURHS and EXPH This functionality permits an update triggered by SW When read this bit always delivers 0 0 The bitfields CURH and EXPH are updated according to the defined HW action The write access to bitfields CURHS and EXPH doesn t modify the bitfields CURH and EXPH 1 The bitfields CURH and EXPH are updated by the value written to the bitfields CURHS and EXPHS 6 r reserved returns 0 if read should be written with 0 User s Manual 4 89 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components Register MCMOUT shows the multi channel control bits that are currently used Register MCMOUT is defined as follows MCMOUTL Multi Channel Mode Output Register Low Byte Reset value 00 1 7 6 5 4 3 2 1 0 R MCMP
182. s 4 5 1 3 Mode 1 Mode 1 is the same as mode 0 except that the timer register is running with all 16 bits Mode 1 is shown in Figure 4 3 12 C T 0 TLO THO Interrupt 8 Bits 8 Bits P Control Gate Figure 4 3 Timer 0 Mode 1 16 Bit Timer Counter User s Manual 4 16 V 0 4 2002 01 aem 7 Infineon C868 technologies On Chip Peripheral Components 4 5 1 4 Mode2 Mode 2 configures the timer register as an 8 bit counter TLO with automatic reload as shown in Figure 4 4 Overflow from TLO not only sets TFO but also reloads TLO with the contents of THO which is preset by software The reload leaves THO unchanged CT sg TFO Interrupt Reload Gate Figure 4 4 Timer 0 1 Mode 2 8 Bit Timer Counter with Auto Reload User s Manual 4 17 V 0 4 2002 01 mtn Infineon C668 technologies On Chip Peripheral Components 4 5 1 5 3 Mode has different effects on timer 0 and timer 1 Timer 1 in mode 3 simply holds its count The effect is the same as setting TR1 0 Timer 0 in mode 3 establishes TLO and THO as two seperate counters The logic for mode 3 on timer 0 is shown in Figure 4 5 TLO uses the timer 0 control bits C T Gate TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from timer 1 Thus THO now controls the timer 1 interrupt Mode 3 is provided for applications req
183. s Memory Organization bootstrap mode Table 3 4 and Table 3 5 show the various memory configurations respectively in an example Table 3 4 Normal XRAM Mode Memory Space Memory Boundary Code Space XRAM FF00 to FFFFy Data Space ROM RAM 0000 to 1FFFj Table 3 5 Bootstrap XRAM Mode Memory Space Memory Boundary Code Space Boot ROM 0000 to OFFF XRAM FF00 to FFFF Data Space RAM ROM 0000 to 1FFFj The on chip XRAM which is in the upper part of the 64 KB data space is always enabled in this mode for code access irrespective of the bit The external data space also becomes code space The actual physical sizes of the various memory types as mentioned above are product specific In the C868 the external accesses are prohibited For code spaces appropriate branch instructions must therefore be inserted The on chip data space is accessible as usual via MOVX instructions The on chip data memory accesses to RAM ROM are restricted by the physical memory available in the respective product For the C868 1R the option to disable the access to the ROM is selectable upon request This option is reflected in SFR Version bit 7 1 for access disabled An exit from the XRAM mode is possible by software only In this mode the on chip XRAM is disabled as data space irrespective of XMAPO bit in SFR SYSCONO It will remain disabled after exit from XRAM mode unless the XMAPO had been cl
184. s 0 if read should be written with 0 All external interrupts CCPOS2 INT2 AN2 P1 3 INT3 can be either positive or negative transition activated depending on the bits register EXICON The flags that actually generates this interrupt are bits EXINT2 and in register IRCONO The flags must be cleared by software User s Manual 7 13 V 0 4 2002 01 mn Infineon technologies C868 Interrupt System T2CON Timer 2 Control Register Reset value 00 1 CE CDy CCy CBy CAy C8 TF2 EXF2 RCLK TCLK 2 TR2 C T2 CP RL2 rwh rwh rw rw rw rw rw rw The functions of the shaded bits are not described here Field Bits Typ Description EXF2 6 rwh Timer counter 2 External Flag This bit is set by hardware when a capture reload occurred upon a negative transition at pin T2EX if bit EXEN2 1 An interrupt request to the core is generated unless bit DCEN 1 This bit must be cleared by software TF2 7 rw Timer 2 Overflow Flag Set by a timer 2 overflow Must be cleared by software TF2 will not be set when either RCLK 1 or TCLK 1 The timer 2 interrupt is generated by bit TF2 or EXF2 in register T2CON This flags are not cleared by hardware when the service routine is vectored to They should be cleared by software User s Manual 7 14 V 0 4 2002 01 mn Infineon technologies C868 Interrupt System
185. s 1 Bit TRPS is automatically cleared by HW if bit is 0 and if the synchronization condition according to TRPMO 1 is detected The trap state can be left return to normal operation bit TRPS 0 as soon as bit is reset by SW after the input CTRAP becomes inactive TRPF is not cleared by HW Bit TRPS is automatically cleared by HW if bit TRPF 0 and if the synchronization condition according to TRPMO 1 is detected 7 3 reserved returns O if read should be written with 0 User s Manual 4 85 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components TRPCTRH Trap Control Register High Byte Reset value 00 1 7 6 5 4 3 2 1 0 TRPPEN TRPEN13 TRPEN rw rw rw Field Bits Description TRPEN 5 0 rw Trap Enable Control Setting these bits enables the trap functionality for the following corresponding output signals bitO trap functionality of CC60 bit 1 trap functionality of COUT60 bit 2 trap functionality of CC61 bit 3 trap functionality of COUT61 bit 4 trap functionality of CC62 bit5 trap functionality of COUT62 The enable feature of the trap functionality is defined as follows 0 The trap functionality of the corresponding output signal is disabled The output state is independent from bit TRPS 1 The trap functionality of the corresponding output signal is enabled The output is
186. s bits and the CC6xST bits have to be reset by SW User s Manual 4 96 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components Table 4 4 Description of the Double Register Capture modes Description Double Register Capture modes 0100The contents of T12 is stored in CC6nR after a rising edge and in CC6nSR after a falling edge on the input pin CC6n 0101The value stored in CC6nSR is copied to CC6nR after a rising edge on the input pin CC6n The actual timer value of T12 is simultaneously stored in the shadow register CC 6nSR This feature is useful for time measurements between consecutive rising edges on pins CC6n COUTEn is IO 0110The value stored in CC6nSR is copied to CC6nR after a falling edge on the input pin CC6n The actual timer value of T12 is simultaneously stored in the shadow register CC 6nSR This feature is useful for time measurements between consecutive falling edges on pins CC6n COUTEn is IO 0111The value stored in CC6nSR is copied to CC6nR after any edge on the input pin The actual timer value of T12 is simultaneously stored in the shadow register CC 6nSR This feature is useful for time measurements between consecutive edges on pins CC6n COUTEn is IO Table 4 5 Description of the Combined T12 modes Description Combined T12 modes 1000Hall Sensor mode Capture mode for channel 0 compare mode for channels 1 and 2 The contents of T12 is captured into CC60
187. s into SBUF One bit time later whether the above conditions were met or not the unit goes back to looking for a 1 to O transition at the RxD input Note that the value of the received stop bit is irrelevant to SBUF RB8 or RI User s Manual 4 111 V 0 4 2002 01 Infineon technologies C868 On Chip Peripheral Components M Internal Bus 2 TB8 Write to e e SBUF Stop Bit Shift E eta Generation Data TX Control 5 16 TX Clock Send Baud Serial Rate e Port Clock Interrupt 1 to 0 RX Clock r Transition Detector RX Control gt Input Shift Register 9Bits RXD Shift Load Shit Read EVO 5 Internal Bus 0 MCS02105 Figure 4 39 Serial Interface Mode 2 and 3 Functional Diagram User s Manual 4 112 V 0 4 2002 01 enuen sasn 10 2002 pue z epojy eoejio1u jenas Op p xa to SBUF E Mode 2 S6P1 Send Mode 3 S1P1 Data o Stop Bit Gen 16 Reset RX Clock RX Start Bit D1 D2 D3 D4 D5 D7 RB8 Stop Bit usuta j E 8 Bit Detector lt R Sample Times RI MCT02587 sjueuoduio jeueudiueg diu uo seiBoJouuoe 8989 mn Infineon C868 technologies On Chip Peripheral Components 4 10 A D Converter
188. scription EADC 0 rw A D converter interrupt enable If EADC 0 the A D converter interrupt is disabled If EADC 1 the A D converter interrupt is enabled EX2 1 rw External interrupt 2 enable If EX2 0 external interrupt 2 is disabled If EX2 1 external interrupt 2 is enabled EX3 2 rw External interrupt Timer 2 capture compare interrupt 0 enable If EX3 0 external interrupt 3 is disabled If EX3 1 external interrupt 3 is enabled 7 3 r reserved returns 0 if read should be written with 0 User s Manual 7 9 V 0 4 2002 01 mn Infineon C668 technologies Interrupt System 00 Enable Register 2 Reset value XX0000XXg 7 6 5 4 3 2 1 0 EINP3 EINP2 EINP1 EINPO r r rw rw rw rw r r Field Bits Typ Description EINPO 2 rw Capture compare interrupt node 0 enable If EINPO 0 the interrupt node 0 is disabled If EINPO 1 the interrupt node 0 is enabled EINP1 3 rw Capture compare interrupt node 1 enable If EINPO 0 the interrupt node 1 is disabled If EINPO 1 the interrupt node 1 is enabled EINP2 4 rw Capture compare interrupt node 2 enable If EINPO 0 the interrupt node 2 is disabled If EINPO 1 the interrupt node 2 is enabled EINP3 5 rw Capture compare interrupt node 3 enable If EINPO 0 the interrupt node is disabled If EINPO 1 the interrupt node 3 is enabled 7 6 r reserved
189. set to the passive state while TRPS 1 TRPEN13 6 rw Trap Enable Control for Timer T13 0 The trap functionality for T13 is disabled Timer T13 if selected and enabled provides PWM functionality even while TRPS 1 1 The trap functionality for T13 is enabled The timer T13 PWM output signal is set to the passive state while TRPS 1 TRPPEN 7 rw Trap Pin Enable 0 The trap functionality based on the input pin CTRAP is disabled A trap can only be generated by SW by setting bit TRPF 1 The trap functionality based on the input pin CTRAP is enabled A trap can be generated by SW by setting bit TRPF or by 0 User s Manual 4 86 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components Register PSLR defines the passive state level driven by the output pins of the module The passive state level is the value that is driven by the port pin during the passive state of the output During the active state the corresponding output pin drives the active state level which is the inverted passive state level The passive state level permits to adapt the driven output levels to the driver polarity inverted not inverted of the connected power stage PSLRL Passive State Level Register High Byte Reset value 00 1 7 6 5 4 3 2 1 0 PSL63 PSL rwh r rwh Field Bits Description PSL 5 0 rwh Compare Outputs Passive
190. signal DTCx o becomes 71 The dead time counter can be reloaded while it is counting DTC2 rl DTC1 rl DTCO rl channel 2 TL channel 1 channel 0 channel 0 only A N D 1 6 bit down counter T12clk b 2i 1 Figure 4 22 Dead time Counter Each of the three channels works independently with its own dead time counter and the trigger and enable signals The value of bit field DTM is valid for all of the three channels In the Hall sensor mode timer T12 is used to measure the rotational speed of the motor channel 0 in capture mode and to control the phase delay before switching to the next state channel 1 in compare mode Furthermore channel 2 can be used to generate a time out signal in compare mode As a result T12 can not be used for modulation and due to the block commutation patterns a dead time generation is not required In order to built an efficient noise filter for the Hall signals channel 0 of the dead time unit is triggered reloaded with each detected edge of the Hall signals see signal Hall edge o in Figure 4 17 For this feature channel 0 also generates a pulse if its counter value is one 4 7 1 9 Capture Mode In capture mode the bits CC6xST indicate the occurrence of the selected capture event according to the bit fields MSEL6x A rising and or a falling edge on the pins CC6x can User s Manual 4 43 V 0 4 2002 01 Infineon
191. ssor that the program left the current interrupt priority level A simple RET instruction would also have returned execution to the interrupted program but it would have left the interrupt control system thinking an interrupt was still in progress In this case no interrupt of the same or lower priority level would be acknowledged External Interrupts The external interrupts 0 and 1 can be programmed to be level activated or negative transition activated by setting or clearing bit ITx x 0 or 1 respectively in register TCON If ITx 0 external interrupt x is triggered by a detected low level at the INTx pin If ITx 2 1 external interrupt x is negative edge triggered In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle interrupt request flag IEx in TCON is set Flag bit IEx 1 then requests the interrupt If the external interrupt O or 1 is level activated the external source has to hold the request active until the requested interrupt is actually generated Then it has to deactivate the request before the interrupt service routine is completed or else another interrupt will be generated The external interrupts 2 and 3 can be programmed to be negative or positive transition activated by setting or clearing bits I2FR or I3FR in register T2CON If IXFR 0 x 2 or 3 then the external interrupt x is negative transition activated If IXFR 1 external interrupt is triggered by a positi
192. te in four different operating modes chipmodes with different program and data memory organisations Normal Mode Normal XRAM Mode Bootstrap Mode Bootstrap XRAM Mode 3 3 1 Special function register SYSCON1 There are four control bits located in SFR SYSCON which control the code and data memory organisation of the C868 Two of these bits BSLEN and SWAP cannot be programmed as normal bits but with a special software unlock sequence The special software unlock sequence was implemented to prevent unintentional changing of these bits and consists of consecutive followed instructions which have to set set two dedicated enable bits SYSCON 1 System Control Register 1 Reset value 00XXX0X0g 7 6 5 4 3 2 1 0 ESWC SWC BSLEN SWAP Ww Ww r r r rw r rw Field Bits Typ Description SWAP 0 rw SWAP Code and Data Memory SWAP 20 Code data memory are in their standard locations default SWAP 21 Code and data memory are swapped The modification of this bit is by software only and must be completed by the special software unlock sequence in order to effect the mode change Otherwise this bit automatically reverts to its previous value with the third EOI end of instruction after this bit is modified This is to prevent any incorrect status read User s Manual 3 3 V 0 4 2002 01 _ Infineon technologies C868 Memory Organization Field Bi
193. tem Clock Operation 5 7 Oscillator and Clock Circuit XTAL2 and XTAL1 are the input and output of a single stage on chip inverter which can be configured with off chip components as a Pierce oscillator The oscillator in any case drives the internal clock generator The clock generator provides the internal clock signals to the chip These signals define the internal phases states and machine cycles Figure 5 5 shows the recommended oscillator circuit Crystal Oscillator Mode Driving from External Source External Oscillator Signal XTAL2 6 67 10 67 MHz XTAL1 C tbd pF pF for crystal operation incl StrayCapacitance Figure 5 5 Recommended Oscillator Circuit In this application the on chip oscillator is used as a crystal controlled positive reactance oscillator a more detailed schematic is given in Figure 5 6 It is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip The crystal specifications and capacitances are non critical In this circuit tod pF can be used as single capacitance at any frequency together with a good quality crystal A ceramic resonator can be used in place of the crystal in cost critical applications If a ceramic resonator is used the two capacitors normally have different values depending on the oscillator frequency We recommend consulting the manufacturer of the ceramic resonator for value specificat
194. ter Reset value 00 1 7 6 5 4 3 2 1 0 GATE1 C NT1 M1 1 MO 1 GATEO C NTO M1 0 MO 0 rw rw rw rw rw rw rw rw Field Bits Typ Description 0 0 0 rw Mode select bits M1 0 1 MO 1 4 M1 x MO x Function M1 1 5 0 0 8 bit timer THx operates as 8 bit timer TLx serves as 5 bit prescaler 0 1 16 bit timer THx and TLx are cascaded there is no prescaler 1 0 8 bit auto reload timer THx holds a value which is to be reloaded into TLx each time it overflows 1 1 Timer 0 TLOis an 8 bit timer controlled by the standard timer 0 control bits THO is an 8 bit timer only controlled by timer 1 control bits Timer 1 Timer counter 1 stops C NTO 2 rw Counter or timer select bit C NT1 6 Cleared for timer operation input from internal system clock GATEO 3 rw Gating control GATE1 7 When set timer x is enabled only while INT x pin is high and TRx control bit is set User s Manual 4 13 V 0 4 2002 01 mn Infineon technologies C868 On Chip Peripheral Components IENO Interrupt Enable Register Reset value 00 1 AFy AEH ADH ACH ABH AAH A9H A8H EA ET2 ES ET1 EX1 ETO EX0 rw r rw rw rw rw rw rw The functions of the shaded bits are not described here Field Bits Typ Description ETO 1 rw Timer 0 overflow interrupt enable If ETO 0 the timer O interrupt is disabled ET1 3 rw Timer 1 overflow interrupt enable If ET1 0 the timer 1 interrupt is disa
195. terface interrupt is generated by a logical OR of flag RI and Tl in SFR SCON Neither of these flags is cleared by hardware when the service routine is vectored to In fact the service routine will normally have to determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the interrupt and the corresonding bit will have to be cleared by software User s Manual 7 16 V 0 4 2002 01 mn Infineon C668 technologies Interrupt System 7 2 3 Interrupt Control Registers for CCUG Register IS contains the individual interrupt request bits This register can only be read write actions have no impact on the contents of this register The SW can set or reset the bits individually by writing to the registers ISS to set the bits or to register ISR to reset the bits ISL Capture Compare Interrupt Register Low Byte Reset value 00 1 7 6 5 4 3 2 1 0 T12PM T120M 62 ICC62R ICCe1F ICC61R 6 ICC60R rh rh rh rh rh rh rh rh Field Bits Description ICC60R 0 rh Capture Compare Match Rising Edge Flag ICC61R 2 In compare mode a compare match has been ICC62R 4 detected while T12 was counting up In capture mode arising edge has been detected at the input CC6x x 0 1 2 0 The event has not yet occurred since this bit has been reset for the last time 1 The event described above has been detected User s Manua
196. th CC6xPS 1 The bit COUT6xPS has the same effect for the second output of the channel The example is shown without dead time User s Manual 4 36 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components period value compare value state 0 T12 xST re T12 xST se CC6xST CC6x T12 xO CC6xPS 0 passive active passive CC6x T12 xO CC6xPS 1 passive active Figure 4 15 Compare States of Timer T12 According to the desired capture compare mode the compare state bits have to be switched Therefore an additional logic see Figure 4 16 selects how and by which event the compare state bits are modified The mode selection by bitfields MSEL6x in register T12MSEL enables the setting and the resetting of the compare state bits due to compare actions of timer T12 The HW modifications of the compare state bits is only possible while the timer T12 is running Therefore the bit T12R is used to enable disable the modification by HW For the hysteresis like compare mode MSEL6x 1001 the setting of the compare state bit is only possible while the corresponding input CCPOSx 1 inactive If the Hall Sensor mode MSEL6x 1000 is selected the compare state bits of the compare channels 1 and 2 are modified by the timer T12 in order to indicate that a programmed time has elapsed User s Manual 4 37 V 0 4 2002 01 _ Infineon C868
197. tion The T2CON register is used for controlling the various modes of timer counter 2 module Additionally this register also indicates the status of the timer counter 2 functions flags T2MOD Timer 2 Mode Register Low Byte Reset value 00 1 7 6 5 4 3 2 1 0 g DCEN r r r r r r r rw Field Bits Typ Description DCEN 0 rw Up Down Counter Enable 0 Up Down Counter function is disabled 1 Up Down Counter function is enabled and controlled by pin T2EX Up 1 Down 0 reserved returns 0 if read should be written with 0 A 7 6 User s Manual 4 19 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components T2CON Timer 2 Control Register Low Byte Reset value 00 1 CFy CEH CDH CCH CBH CAH C9H C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 rwh rwh rw rw rw rw rw rw Field Bits Typ Description CP RL2 0 rw Capture Reload Select 0 Reload upon overflow or upon negative transition at pin T2EX when EXEN2 1 1 Capture timer counter 2 data register contents on negative transition at pin T2EX provided EXEN2 1 If TCLK RCLK 1 this bit is ignored C T2 1 rw Timer or Counter Select 0 Timer function selected 1 Count upon negative edge at pin T2 TR2 2 rw Timer counter 2 Start Stop Control 0 Stop Timer counter 2 1 Start Timer counter 2 EXEN2 3 rw Timer counter 2 Exter
198. tion logic continues to monitor the two clock signals and adjusts the VCO clock if required The PLL provides mechanisms to detect a failure of the external clock and to bring the C868 into a safe state in such a case When the PLL loses the lock to the external clock either due to a break of the crystal or an external line it generate an internal reset The PLLR flag in the SCUWDT register is set this flag can only be reset by a hardware reset or by software Due to this operation the VCO clock of the PLL has a frequency which is a multiple of the externally applied clock The factor for this is controlled through the value applied to the divider in the feedback path That is why this factor is often called a multiplier although it actually controls a divider This parameter called the feedback divider has a fixed value N 15 When software power down mode is entered the PLL is powered down User s Manual 5 5 V 0 4 2002 01 _ Infineon C868 technologies Reset and System Clock Operation 5 5 1 VCO Frequency Ranges The frequency range for fyco is 100 2 fco 160 MHz 5 1 5 5 2 K Divider The K Divider is a software controlled divider The bit field KDIV is provided in register CMCON Software can write to this field in order to change the PLL frequency The default KDIV value is 4 Table 5 2 lists the possible values for KDIV and the resulting division factor The divider is designed such that a synchronous
199. transfer takes place ifthe period match is detected while counting up e if the one match is detected while counting down The timer T12 prescaler is reset while T12 is not running to ensure reproducible timings and delays The counting rules lead to the following sequences 2 1 period match zero match CDIR valuen value n 1 CC6x lt shadow transfer Figure 4 11 112 in edge aligned mode User s Manual 4 33 V 0 4 2002 01 mn Infineon technologies C868 On Chip Peripheral Components In the center aligned mode T12 counts up and down the counting rules lead to the following behavior 2 one match zero match up 0 value n value 1 CC6x lt shadow transfer Figure 4 12 T12 in center aligned mode one match detected 2 T12P 1 T12P period match down 1 value n value n 1 CC6x lt shadow transfer Figure 4 13 T12 in center aligned mode period match detected User s Manual 4 34 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components 4 7 1 3 Switching Rules The compare actions take place in parallel for the three compare channels Depending on the count direction the compare matches have different meanings In order to get the PWM information independent from the output levels two different states have been introduced for the compare act
200. tructions that take more than two cycles to complete they take four cycles Normally two code bytes are fetched from the program memory during every machine cycle The only exception to this is when a MOVX instruction is executed MOVX is a one byte 2 cycle instruction that accesses external data memory During a MOVX the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed Figure 2 2 c and d show the timing for a normal 1 byte 2 cycle instruction and for a MOVX instruction User s Manual 2 6 V 0 4 2002 01 C868 Infineon technologies Fundamental Structure 61 52 53 54 55 56 S1 52 S3 54 55 S6 2 2 2 2 ALE Read Next code Di p iscard Read Bm _ Opcode Again Byte 1 Cycle Instruction e g INC A Read Read an Opcode Byt i Ms Read Next y Opcode Sooo b 2 Byte 1 Cycle Instruction e g ADD A Data Read Read Next Opcode Again Read Next Opcode Discard Opcode 1 2 Instruction e g INC DIST Read Next Opcode Again Read Read Next Opcode Opcode No Fetch No MOVX Discard qi No ALE Fetch VA STSISTSTSTSTSTSTS Te TS I
201. ts Typ Description BSLEN Bootstrap Mode Enable BSLEN 1 Bootstrap mode BSLEN 0 Normal mode default This bit is initialised to the reverse of the value at external pin ALE BSL latched at the rising edge of RESET This bit can be set cleared by software to change between the modes The modification of this bit by sofware must be completed by the special software unlock sequence in order to effect the mode change Otherwise this bit automatically reverts to its previous value with the third EOI end of instruction after this bit is modified This is to prevent any incorrect status read SWC Switch Mode The SWC bit must be set as the second instruction in a special software unlock sequence directly after having set bit ESWC The new chipmode becomes active after the second EOI end of instruction after this event and the SWC bit is also cleared simultaneously SWC is a write only bit Reading SWC returns 0 ESWC Enable Switch Mode The ESWC bit must be set during the first instruction in the special software unlock sequence The bit ESWC will be cleared by hardware with the third EOI end of instruction after this event ESWC is a write only bit Reading ESWC returns a 0 7 2 reserved returns 0 if read should be written with 0 User s Manual 3 4 V 0 4 2002 01 Infineon C868 technologies Memory Organization 3 3 2 Chip Mod
202. ture Compare Mode Selection MSEL61 7 4 These bitfields select the operating mode of the three timer T12 capture compare channels Each channel 0 1 2 be programmed individually either for compare or capture operation according to 0000 Compare outputs disabled pins CC6n and COUTE6n can be used for IO No capture action 0001 Compare output on pin CC6n pin COUT6n can be used for IO No capture action 0010 Compare output on pin COUT6n pin CC6n be used for IO No capture action 0011 Compare output on pins COUT6n and 01XX Double Register Capture modes see Table 4 4 1000 Hall Sensor mode see Table 4 5 In order to enable the hall edge detection all three MSEL6x have to be programmed to Hall Sensor mode 1001 Hysteresis like mode see Table 4 5 101X Multi Input Capture modes see Table 4 6 11XX Multi Input Capture modes see Table 4 6 Note In the capture modes all edges at the CC6x inputs are leading to the setting of the corresponding interrupt status flags in register IS In order to monitor the selected capture events at the CCPOSx inputs in the multi input capture modes the CC6xST bits of the corresponding channel are set when detecting the selected event The interrupt status bits and the CC6xST bits have to be reset by SW User s Manual 4 95 V 0 4 2002 01 Infineon C868 technologies On Chip Peripheral Components T12MSELH T12 Capture
203. uiring an extra 8 bit timer or counter When timer 0 is in mode and when 1 is set timer 1 can be turned on by switching it to any mode other than 3 and off by switching it into its own mode 3 or can still be used by the serial channel as a baud rate generator or in fact in any application not requiring an interrupt from timer 1 itself Timer Clock TFO Interrupt Control Gate TF1 Interrupt TR1 Figure 4 5 Timer 0 Mode 3 Two 8 Bit Timers Counters User s Manual 4 18 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components 4 6 Functional Description of Timer Counter 2 Timer two serves as a 16 bit timer counter for which is also capable of being used as a baudrate generator for the UART module 4 6 1 Features 16 bit auto reload mode selectable up or down counting one channel 16 bit capture mode Baudrate generator for UART Timer counter powerdown in normal idle and slow down modes 4 6 2 Overview Timer 2 is a 16 bit general purpose timer counter which can additionally function as a baudrate generator This module is functionally compatible to the Timer 2 in the C501 product family Timer counter 2 can function as a timer or counter in each of its modes As a timer it counts with an input clock of fsys 12 As a counter it counts 1 to 0 transitions on pin T2 In the counter mode the maximum resolution for the count is 24 4 6 3 Register Descrip
204. unter 2 is not utilized Bit T2ST in register PMCONe reflects the powerdown status of timer counter 2 User s Manual 4 30 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components 4 7 Capture Compare Unit CCU6 The CCU6 provides two independent timers T12 T13 which can be used for PWM generation especially for AC motor control Additionally special control modes for block commutation and multi phase machines are supported Timer 12 Features Three capture compare channels each channel can be used either as capture or as compare channel Generation of a three phase PWM supported six outputs individual signals for highside and lowside switches 16 bit resolution maximum count frequency system clock Dead time control for each channel to avoid short circuits in the power stage Concurrent update of the required T12 13 registers Center aligned and edge aligned PWM can be generated Single shot mode supported Many interrupt request sources Hysteresis like control mode Timer 13 Features One independent compare channel with one output 16 bit resolution maximum count frequency system clock Can be synchronized to T12 Interrupt generation at period match and compare match Single shot mode supported Additional Features Block commutation for Brushless DC drives implemented Position detection via Hall sensor pattern Automatic rotational speed measurement
205. ure function of timer counter 2 2 0 C T2 1 9 Overflow Timer 2 Interrupt T2EX Figure 4 8 Capture Mode User s Manual 4 28 V 0 4 2002 01 mn Infineon C668 technologies On Chip Peripheral Components 4 6 7 Baudrate Generator Mode The baudrate generator mode of timer counter 2 can be selected by setting the bits TCLK and or RCLK in register T2CON So the baudrate for the receive and transmit functions can be individually controlled The timer counter itself functions similar to the auto reload mode with up down counting is disabled The timer counter counts up and overflows but the overflow condition does not set the TF2 flag An interrupt request to the core is not generated Upon an overflow condition the timer counter registers are reloaded with the RC2L H registers content and continues counting as before The overflow signal is provided as an output of the timer counter 2 block This is active for one clock cycle only Additionally the status of the TCLK and RCLK bits are also provided as outputs of the timer 2 block The UART for e g could use these signals to control its baudrates The main difference between the auto reload mode and the baudrate generator mode is that timer 2 as a baudrate generator uses fsys 2 as the count clock In the auto reload mode the timer counter 2 uses fgys 12 as the count clock If EXEN2 1 in the baudrate generator mode a falling edge on pin T2EX c
206. ures PPP TITEL 4 19 4 6 2 Overview 4 19 4 6 3 Register Description 4 19 4 6 4 Operating Mode Selection 4 25 4 6 5 Auto Reload 4 25 4 6 5 1 Up Down Count Disabled 4 25 4 6 5 2 Up Down Count Enabled 4 26 User s Manual 1 V 0 4 2002 01 _ Infineon C868 technologies 4 6 6 Capture Mode 4 28 4 6 7 Baudrate Generator 4 29 4 6 8 qe rtm 4 30 4 6 9 Module Powerdown 4 30 4 7 Capture Compare Unit 6 4 31 4 7 1 Wier TIS ended Cae 4 32 4 7 1 1 eU CR AEE EROS eRe eee eee 4 32 4 7 1 2 Counting Rules 4 33 4 7 1 3 Switching Rules 4 35 4 7 1 4 Duty Cycle of 0 and 100 4 36 4 7 1 5 Compare Mode 12 4 36 4 7 1 6 Switching Examples in edge aligned Mode 4 40 4 7 1 7 Switching Examples in center aligned Mode 4 40 4 7 1 8 Dead time Generation 4 41 4 7
207. utput drives passive level while CC6xST is 0 1 The corresponding compare output drives passive level while CC6xST is 1 In capture mode these bits are not used T13IM 7 rwh T13 Inverted Modulation Bit T13IM inverts the T13 signal for the modulation of the CC6x and COUTE6x x 0 1 2 signals 0 T13 output is not inverted 1 T13 output is inverted for further modulation 1 These bits have shadow bits and are updated in parallel to the capture compare registers of T12 T13 respectively A read action targets the actually used values whereas a write action targets the shadow bits 2 This bit has a shadow bit and is updated in parallel to the compare and period registers of T13 A read action targets the actually used values whereas a write action targets the shadow bit User s Manual 4 71 V 0 4 2002 01 Infineon technologies The Compare Status Modification Register contains control bits allowing for modification by SW of the Capture Compare state bits C868 On Chip Peripheral Components CMPMODIFL Compare State Modification Register Low Byte Reset value 00 1 7 6 5 4 3 2 1 0 MCC63S MCC62S MCC61S MCC60S r Ww r r r Ww Ww Ww Field Bits Typ Description MCC60S 0 w Capture Compare Status Modification Bits MCC61S 1 These bits are used to set MCC6xR the MCC62S 2 corresponding bits CC6xST by
208. ve transition Since the external interrupt pins are sampled once in each machine cycle an input high or low should be held for at least 3 oscillator periods to ensure sampling If the external interrupt is positive negative transition activated the external source has to hold the request pin low high for at least one cycle and then hold it high low for at least one User s Manual 7 36 V 0 4 2002 01 Infineon C868 technologies Interrupt System cycle to ensure that the transition is recognized so that the corresponding interrupt request flag will be set see Figure 7 8 The external interrupt request flags will automatically be cleared by the CPU when the service routine is called a Level Activated Interrupt P3 x INTx Low Level Threshold gt 1 Machine Cycle b Transition Activated Interrupt High Level Threshold e g P3 x INTx Low Level Threshold MCTO1921 lt gt gt 1 Machine Cycle gt 1 Machine Cycle Transition to be detected Figure 7 8 External Interrupt Detection 7 5 Interrupt Response Time If an external interrupt is recognized its corresponding request flag is set at S5P2 in every machine cycle The value is not polled by the circuitry until the next machine cycle If the request is active and conditions are right for it to be acknowledged a hardware subroutine call to the requested service routine will be the next instruction to be executed
209. vior of the connected power switches is not symmetrical concerning the times needed to switch on and to switch off A general problem arises if the time to switch on is smaller than the time to switch off the power device In this case a short circuit in the inverter bridge leg occurs which may damage the complete system In order to solve this problem by HW this capture compare unit contains a programmable dead time counter which delays the passive to active edge of the switching signals the active to passive edge is not delayed see Figure 4 21 The dead time generation logic see Figure 4 22 is built in a similar way for all three channels of T12 Each change of the CC6xST bits triggers the corresponding dead time counter 6 bit down counter clocked with T12clk The trigger pulse DTCx_rl leads to a reload of the dead time counter with the value which has been programmed in bit field User s Manual 4 42 V 0 4 2002 01 Infineon C868 technologies On Chip Peripheral Components DTM This reload can only take place if the dead time feature is enabled by bit DTEx and while the counter is zero While counting down zero is not yet reached the output line DTCx o becomes 0 This output line is combined with the T12 modulation signals leading to a delay of the passive to active edge of the resulting signal which is shown in Figure 4 21 When reaching the counter value zero the dead time counter stops counting and the
210. with TRM2 0 4 7 5 Modulation Control The modulation control part combines the different modulation sources CC6x 12 COUT6x T12 o six T12 related signals from the three compare channels the T13 related signal MOD T13 o and the multi channel modulation signals MCMP bits each modulation source can be individually enabled for each output line Furthermore the trap functionality is taken into account to disable the modulation of the corresponding output line during the trap state if enabled User s Manual 4 53 V 0 4 2002 01 Infineon C668 technologies On Chip Peripheral Components CC6x T12 o COUT6x T12 o 0 passive state 1 active state to output pin CC6x COUT6x Figure 4 32 Modulation Control of T12 related Outputs The logic shown in Figure 4 32 has to be built separately for each of the six T12 related output lines referring to the index x in the figure above The output level that is driven while the output is in the passive state is defined by the corresponding bit in bit field PSL If the resulting modulation signal is active the inverted level of the PLSx bit is driven by the output stage The modulation control part for the T13 related output COUT63 combines the T13 output signal COUT63_T13_0 and the enable bit ECT13O with the trap functionality The output level of the passive state is selected by bit PSL63 User s Manual 4 54 V 0 4 2002 01 Infineon C868 technol
211. wn 100 T12 channel 1 compare match detected phase delay function 101 T12 period match detected while counting up else reserved no trigger request will be generated SWSYN 5 4 rw Switching Synchronization Bitfield SWSYN triggers the shadow transfer between MCMPS and MCMP if it has been requested before flag R set by an event selected by SWSEL This feature permits the synchronization of the outputs to the PWM source that is used for modulation T12 or T13 00 direct the trigger event directly causes the shadow transfer 01 T13 zero match triggers the shadow transfer 10 aT12zero match while counting up triggers the shadow transfer 11 reserved no action User s Manual 4 93 V 0 4 2002 01 mn Infineon technologies C868 On Chip Peripheral Components Field Bits Description 3 r reserved 7 6 returns O if read should be written with 0 Note The generation of the shadow transfer request by HW is only enabled if bit MCMEN 1 User s Manual 4 94 V 0 4 2002 01 _ Infineon C868 technologies On Chip Peripheral Components Register T12MSEL contains control bits to select the capture compare functionality of the three channels of timer T12 T12MSELL T12 Capture Compare Mode Select Register Low Byte Reset value 00 1 7 6 5 4 3 2 1 0 MSEL61 MSEL60 rw rw Field Bits Type Description MSEL60 3 0 Cap
212. y the same as in mode 1 The transmit portion differs from mode 1 only in the 9th bit of the transmit shift register The associated timings for transmit receive are illustrated in Figure 4 40 Transmission is initiated by any instruction that uses SBUF as a destination register The Write to SBUF signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested Transmission starts at the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the Write to SBUF signal The transmission begins with activation of SEND which puts the start bit at TxD One bit time later DATA is activated which enables the output bit of the transmit shift register to TxD The first shift pulse occurs one bit time after that The first shift clocks a 1 the stop bit into the 9th bit position of the shift register Thereafter only zeroes are clocked in Thus as data bits shift out to the right zeroes are clocked in from the left When TB8 is at the output position of the shift register then the stop bit is just to the left of TB8 and all positions to the left of that contain zeroes This condition flags the TX control unit to do one last shift and then deactivate SEND and set TI This occurs at the 11th divide by 16 rollover after Write to SBUF Reception is initiated by a detected 1 to 0 transition at RxD For this purpose

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