User Manual
Contents
1. LAYER am cm ISSUE GND po mH ND cb Y ome Wei 5 NE GND I Ja GND ER lt D5B R148 C76 A141 D6B ENB 048 078 PNG Wes 2 E C ee d E LEM GND 38 oee GNO on lo D5A DBA m E 1P32 D2B ise D4A bes D7A ao D9B TP41 GND D3A R139 O us GND DBA END RE GND R138 a1 a um Teso e COME a m pi D2A D8A TP42 GNO v oan UE E TE E Gd mE m LESER E B amp amp amp cup 8 5 E E amp cup Im ja D88 D1A oooga IL DIBA 0118 C52 C56 c71 TP43 1 cc RIB4 GND 128 reel E real R1 86 ame 142 DBA EV e R95 pog Oo mea O Rin DIIA DVSS cea 89 ce4 meaz C nup IX c68 PL1 VEE u2 ces u2. x s oz 2 zon c TOC roc ES Bod ood o nom mW g zog E 2 E zw 5 un 5 5 n n N S 9 OR OH NNNNA AN ee oe PE tE rc r r zr r k r cee HAR HR RR ry Ala B H A lo 7 OD Kk OH s mn N S m o D D D D D D D o p OR N E E P C D CoC C ce amp ms n m Nm mm m 00 00 D R28 R28 c12 p C28 C34 B 227 s SE re E R4 C26 C7 R47 R48 R3 RS DINO NNNRNRN soooos A AB C78 R142 Lj R1 ca RI 2V P7 PS AVOD O AVSS P11 cuir PB AVSS 1 Su m IN P1 DE PAIN FB P2 P3 FB 1 AVSS P12 PIBAPP VSS 5 2V PB P9 sv MB86881 VERSION 1 2 3 4 5 6 7 8 9 Figure B2 Component Overlay For Layer 4 Solder Side Copyright 1999 Fujitsu Microelectronics Europe GmbH Page 21 of 26 November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 co FUJITSU Appendix C Connector Pin Functions DK86061 3 12 bit 400MSa s DAC Evaluation Board Table C1 Data Connector PL2 Pin Functions Pin Function 1 Data Bit 11 MSB 3 Data Bit 10 Data Bi 1p 5 ata Bit 9 mm 7 Data Bit 8 m 9 Data Bit 7 8 11 Data Bit 6 NH 13 Data Bit 5 NH mm
3. Tess ISSUE GNO JL Bae du mE e A ae n o m di a e ENG Po TH da GND Is a 058 mue cC mu 068 s END d pte o ove GNIS DM lolo dod BE C ede GND pe E eB GND Boc illum e ull m Tes D28 cp x 088 Tent END 03A gg o ue GND DBA END zy 22 _ oa Tess UT 1es7 EJ TOES ar pie O2A OSA 0188 ui GND od od Sot apie E 588 2 227 od sno Fer 33 8522 8 amp amp amp cup 8 5 amp E cup jm a DaB DIA ces Ices Jen D1BA D11B He Ae ma KENN DBA sei o R35 nas Oo mea O mus Ba do DVSS csa AS cee rez Rite E PL1 VEE uz Desa usi Des m C c7 ESI s 1712 TPIS SW1 vee NED a ccs en die Dvss 1 P TERM SRR RSE SSR ERE E TWOC EERE ER EEG EEE SHUF agen os E 1999 SHUF 1 A E FUJITSU MICROELECTRONICS EUROPE TEST ved amp RRERENRRERILE E MBBB881 DAC TEST CARD PL1 irr ink ISSUE 3 n gt MAA 2 9 E SW2 488 PL2 1 T n52 SW3 ES us tee vss vTH reza P52 1 y _ ves 5 l me VOD Tea ma ven van ree O m R43 ED Y ELK 1 has R37 R38 m ok ouT Clock Out m 1 ER o ae has A li Cm o a5 VREF isi A bis
4. O O O O O O O o O O Oo Oo Oo Oo O o O Figure D1 Prototype Area Layout Page 24 of 26 Copyright O 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 co FUJITSU DK86061 3 12 bit 400MSa s DAC Evaluation Board This page left intentionally blank Copyright O 1999 Fujitsu Microelectronics Europe GmbH Page 25 of 26 November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 co FUJITSU DK86061 3 12 bit 400MSa s DAC Evaluation Board Worldwide Headquarters Japan Fujitsu Limited Asia Fujitsu Microelectronics Asia Pte Limited Tel 481447543753 1015 Kamikodanaka 4 1 1 Tel 65 281 0770 151 Lorong Chuan Fax 481447543329 Nakahara ku Fax 465 281 0220 3605 08 New Tech Park Kawasaki shi Singapore 556741 Kanagawa ken 211 88 Japan http www fujitsu co jp http www fmap com sg USA Fujitsu Microelectronics Inc Eu rope Fujitsu Microlectronics Europe GmbH Tel 1 4089229000 3545 North First Street Tel 449 6103 6900 Am Siebenstein 6 10 Fax 414089229179 San Jose CA 95134 1804 Fax 449 6103 690122 D 63303 Dreieich Buchschlag USA Germany Tel 1 800 866 8608 Customer Response Center http www fujitsu fme com Fax 414089229179 Mon Fri 7am 5pm PST http www fujitsumicro com The contents of this document are subject to change without notice Customers are advised to consult with FUJITSU sales representatives before
5. Appendix C Connector Pin Functions Appendix D Prototype Area eeesseeeeeeees Copyright O 1999 Fujitsu Microelectronics Europe GmbH co FUJITSU od ie te sete 9 Page 3 of 26 November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 co FUJITSU DK86061 3 12 bit 400MSa s DAC Evaluation Board This page left intentionally blank Page 4 of 26 Copyright O 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 co FUJITSU DK86061 3 12 bit 400MSa s DAC Evaluation Board 1 Overview The DK86061 3 evaluation board allows users to evaluate and demonstrate the different operational modes of the MB86061 12 bit 400MSa s DAC The evaluation board consists of an MB86061 device with support circuitry for single ended or differential analog output interfaces a clock input interface and a clock output interface This will enable simple connection of measurement equipment For convenience customer evaluation boards have been configured using soldered zero ohm links for transformer coupled differential output only The ECL input data interface has a 40way IDC header with selectable termination to VEE or DVSS Separate SMA SMB connectors for individual data bit connections are also available but not normally fitted with selectable termination to VEE or DVSS Provision is made to multiplex data onto the input data interface from two speed limited but phase adjusta
6. NETWORK HOUSE NORREYS DRIVE MAIDENHEAD BERKSHIRE SL6 4FT Date September 15 1999 Sheet Copyright O 1999 Fujitsu Microelectronics Europe GmbH CET INM LL o To Te Te Te Te Te le Ts le le D gt 2 J S 5 5 8 a 29 la oz s D o D D on co FUJITSU T k C36 noon KPY SS C37 Em KPY SS d c38 TOS KPY SS j c39 TE KPY SS j 100n C41 ron KPY SS J C42 T KPY SS u C43 TOS KPV SS C44 Em KPV SS C45 Em KPY SS d C46 TUR KRYSS j C47 100n VEE DVSS Title z p MB86061 DAC TEST CARD e Sor B CAD DATA C9906 3 1 of 2 Page 15 of 26 co FUJITSU November 1999 Version 3 2 FME MS SFDAC1E UM 1 4133 DK86061 3 12 bit 400MSa s DAC Evaluation Board R90 R91 R92 R93 51R 51R 51R 51R D 0 A mou gt U n Page 16 of 26 VEE WOO dimus R117 51R u2 MC10E158 R94 R95 R96 R97 R98 R99 R100 R101 R102 R103 R104 R105 R106 R107 R108 R109 Ri 51R 51R 51R 51R 51R 51R 51R 51R 51R 51R 51R 51R 51R 51R 51R 51R f D D D D D D D D D D D D D D D D JY 2 2 3 3 4 4 5 5 6 E y B A B A B A B A B A B A B A B A B ooz noz OE R132 R131 R130 OR OR OR U3 MC10E158 C60 C61 Ce2 Ce3 C64 C65 C66 C67 100n 100n 100n 100n 100n 100n 100n 100n o vg r3 o Copyright 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 co FUJITSU DK86061 3 12 bit 400MS
7. 5 Press Reset Press the Reset button to ensure that the device is in the correct operating condition Press Reset every time a configuration change is made Copyright 1999 Fujitsu Microelectronics Europe GmbH Page 11 of 26 November 1999 Version 3 2 FME MS SFDAC1E UM_ 1 4133 co FUJITSU 4 Testing DK86061 3 12 bit 400MSa s DAC Evaluation Board This section provides a brief introduction to testing with the DK86061 3 12 bit 400MSa s DAC Evaluation Board The MB86061 incorporates a 12 bit 400MSa s digital to analog converter designed to give excellent SFDR performance Traditional 12 bit converters have been speed limited in particular when considering CMOS solutions and applications have tended to be limited to around 100MSa s In certain applications it is now possible to consider using the MB86061 with a 400MSa s DAC conversion rate even though the generated signal band may only be for example up to 40MHz or less In theory a 100MSa s converter would be sufficient to reproduce this 40MHz signal band but according to Nyquist the converters performance will tend to be limited due to step size and sinx x roll off as a result of the converters sample amp hold output stage A 400MSa s DAC conversion rate will significantly reduces effects due to both of these Sinx x roll off is reduced from 4dB to 0 22dB and the increased oversampling DAC conversion rate signal rate reduces step sizes to give a direct improvement in spuriou
8. shown in Figure 2 1 Flexible cable of 16 28 AWG 0 5 1 5mm should be used The format of the power connector is common across Fujitsu s DAC Development Kit range Some of the supply pins are connected to test points for convenience if the user requires supplies for the prototype area Standard Requirement MM X Page 6 of 26 PCB mounted power header 5 2V f Data 2V Sense Data 2V Force Data GND Data 3 3V Force Data 3 3V Sense Pin 16 Opt 3 3V Sense t Opt 3 3V Force t 3 3V Sense 3 3V Force GND 2V Force 2V Sense 5V T 12V f Relay t Figure 2 1 Power Connections Copyright O 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 DK86061 3 12 bit 400MSa s DAC Evaluation Board 2 2 Board and Interface Controls co FUJITSU LAYER
9. to select Jumper links LK4 to LK7 inclusive and LK10 should be Not linked and LK8 and LK9 should be set to 2 to 3 linked Switch SW3 should be set to position A Step 2 Connect data input amp analog output connectors to the board The input data should be connected via the 40 way IDC header PL1 or if fitted the SMA SMB connectors J20 to J42 inclusive evens only See Table C1 for the pin description of the IDC header The output is provided as a transformer coupled differential signal via a BNC connector Differential Output signal J7 504 source resistance The DAC is coupled to a single output connector using a transmission line and a 1 1 balun transformer Signal swing is 0 5V with a high impedance load or 0 25V with an external 502 load For sinusoidal signals this corresponds to approximately 2dBm into a 504 external load Step 3 Connect clock The clock input is provided to the device through a transmission line transformer via a BNC connector RF clock J12 509 input impedance The DAC is coupled to a single input connector using a transmission line transformer Sine wave or square wave input signals between 10dBm and 10dBm are acceptable depending on clock frequency and required output jitter phase noise Step 4 Connect power header to power supplies Ensure that the power supplies are connected according to Figure 2 1 Connect the power header to the board and turn power supplies on Step
10. 100nF Decoupling capacitors R1 OR Optional power supply PSRR resistor R7 R12 OR Single ended output relay bypass resistors R9 R13 51R Single ended output termination resistors R16 R132 51R Analog output RC network resistors R17 OR CMRR jumper link bypass resistor R35 51R Reference series resistor R36 1K Reference current limit resistor R90 to R113 51R Input data termination resistors R126 to R137 SR1 to OR Input data multiplexers selection and bypass resistors SR12 R138 to R141 51R XCLK termination resistors U2 U3 U4 MC10E158 Input data multiplexers U5 MC10E107 Input data multiplexer quad XOR T2 Optional analog output circuit transformer Page 18 of 26 Copyright 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 co DK86061 3 12 bit 400MSa s DAC Evaluation Board FUJITSU A 2 Changes to PCB Schematics Table A2 Schematic Changes Reference New Value Description T1 a ADTT1 1 Mini Circuits 1 1 analog output transformer T1 b ADTL1 12 Mini Circuits transmission line transformer 1L LL 6 9 9 To Output To DAC 3 T1b Tla Y 5 Figure A1 Replacement Schematic For T1 Pin Numbers Refer To T1 Copyright O 1999 Fujitsu Microelectronics Europe GmbH Page 19 of 26 co FUJITSU November 1999 Version 3 2 FME MS SFDAC1E UM 1 4133 DK86061 3 12 bit 400MSa s DAC Evaluation Board Appendix B Component Overlays
11. 15 Data Bit 4 E 17 Data Bit 3 mm 19 Data Bit 2 o 21 Data Bit 1 NH v 23 Data Bit 0 LSB gH H 25 Not Used E m 27 Not Used no 29 Not Used E 31 Not Used HN m mg 33 Not Used gH E 35 Not Used 39 E m 37 Not Used 39 Not Used 2 to 40 Even num Data Ground DVSS bers only Page 22 of 26 Copyright O 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 co FUJITSU DK86061 3 12 bit 400MSa s DAC Evaluation Board Table C2 Control Connector PL1 Pin Functions Pin Function 1 to 13 Digital Ground VSS 14 TWOC 15t SOUT O P 16 SHUFO 17 SHUF1 18 TEST 19 RESETB 201 Test point 8 211 Test point 7 221 Test point 6 231 Test point 5 241 Test point 4 251 Test point 3 T These pins are connected to test points so that connections to the prototype area can be made via the control connector t These pins are for factory test purposes only Copyright O 1999 Fujitsu Microelectronics Europe GmbH Page 23 of 26 November 1999 Version 3 2 FME MS SFDAC1E UM_ 1 4133 co FUJITSU Appendix D Prototype Area DK86061 3 12 bit 400MSa s DAC Evaluation Board A prototype area has been introduced into the DK86061 3 development kit PCB This area takes the form of a matrix of pads with plated through holes on a 2 54mm pitch The pads are made square to allow for 0805 format surface mount devices to be fitted between adjacent pads
12. Qo User Manual FUJITSU November 1999 DK86061 3 Version 3 2 12 bit 400MSa s DAC Evaluation Board FME MS SFDAC1E UM 1 4133 Fujitsu s DK86061 3 12 bit 400MSa s DAC Evaluation Board provides a simple and effective means of evaluating the MB86061 12 bit 400MSa s DAC This enables faster device evaluation without incurring the time and cost penalties of in house PCB design and manufacture EVALUATION BOARD The board provides a complete evaluation environment for the DAC device A selectable single ended or transformer coupled differential analog output interface is provided on development environments The clock is sourced from a transformer coupled RF source 12 bit ECL data is input via a 40way IDC header or optional SMA SMB connectors The MB86061 device is a single 12 bit DAC enclosed in a 64 pin QFP package with a 0 65mm pin pitch Features 12 bit ECL data input via a choice of connectors Transformer coupled differential output via BNC Transformer coupled RF clock input via BNC Requires DC power supplies of 3 3V and 2V Copyright O 1999 Fujitsu Microelectronics Europe GmbH Page 1 of 26 co FUJITSU A November 1999 Version 3 2 FME MS SFDAC1E UM_ 1 4133 DK86061 3 12 bit 400MSa s DAC Evaluation Board CAUTION ELECTROSTATIC DISCHARGE SENSITIVE DEVICE High electrostatic charges can accumulate in the human body and discharge without detection Ensure proper ESD procedures are followed when hand
13. The matrix area has four rows individually linked together to act as power rails These rows are arranged as two pairs with connections to the internal planes layers 2 and 3 made to each of the rows The internal plane regions only occupy the prototype area and are not linked to any other area of the PCB The prototype area layout is shown in Figure D1 Layer 2 would typically be used as the ground plane and layer 3 as the power plane with signals routed on layer 1 However the choice in the prototype area is free as the planes are entirely separate to the rest of the PCB O Oo o O Oo O O O O O O 0 o Oo o O o O Oo ojo O Oo o Oo o O O O O O O O o o O o o O Oo o o o Oo Layer NAAA a ayer 3088 E El El El El E Al Al O 0 AAA AAA AA AAA Oo o Oo o O O O O O O O 9 o O o O O O o Oo o Oo o o o Oo Oo O O O O O O Oo o O o Oo o Oo o ojo Oo O o O O O Oo O O O O O Oo O O O O O O o Oj J O O o Oo o O o O O O O O Q O o o O o O o O ojo o Layer 2 M M ll ll ll El E DE DE 0 00000000 a Layer3 ll El El ll El ll E EN 00000 I O O O O O 9 O O O O O O O O O O O O O Oo O O O O O O j O J O O O O O O O
14. a l s ya c70 LK 1 TP12 TP13 VSS VDD CV lee Ge eve an ek Ot DVS 125 TERM Rael PARR AH eRe EA a e TWOC t t r t t C E tee ee C y SHUFB Asi ot 1988 m2 SHUF 1 P SS Sk FUJITSU MICROELECTRONICS EUROPE nas TEST IRENE NERER DS S MB86261 DAC TEST CARD Ras VEE ne ISSUE 3 sw uke oO TPB 1 n ut mus mons D 5 ses PER GC G Po GB Go POR xg d i i PL2 T5 RESET Tsw 1 TP3 A B J18 R52 NA ns xs reza VSS VTH Tp23 R52 ui n T2 VOD Dvss SE TP22 R39 VRI DV J nr uc aet ST sta ES SES ELK rast ha Tre o IOUT 318 1 LK E or ras _ Jas m O ra ts q i m7 war ii VREF Fasl Cia s Ciel p32 A ian Jes p 1 e reis RVDDL hes e hel az 512 317 T5 RYSS E rea T E ce m CLKB RREF A Aton m TP18 312 573 C16 l CVDD CLK ozs 14 CVSS aa IN ST4 ca 1 dat uke p a R28 TPIS eI ise P JE a2 jerkcm x sts e Uus CMRR S tipo D Fe Fe B cvoo H R i pan AVOD AVSS gt STB cs LK2 LK1D AVDD sra Avon Y PSRR sra s IOUTB ME Jes IOUT sa 35 TU 45V ce DIFF LES OUT TP2 412V SEDUT sa 37 js Figure B1 Component Overlay For Layer 1 Component Side Page 20 of 26 Copyright O 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1E UM 1 4133 c2 FUJITSU DK86061 3 12 bit 400MSa s DAC Evaluation Board
15. a s DAC Evaluation Board D10A Dios u3 u4 MC10E158 MC10E158 D D 4 8 A B D11B 26 DAS Dv 72 R138 US 51R 1 MC10E107 alz 1 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 19 103 R104 R105 R106 R107 R108 R109 R110 R111 R112 R113 51R 51R 51R 51R 51R 51R 51R 51R 51R 51R 51R D D D D D D D T y 8 8 9 9 B A B A B A B FUJITSU MICROELECTRONICS EUROPE NETWORK HOUSE NORREYS DRIVE MAIDENHEAD BERKSHIRE SL6 4FT Title MB86061 DAC TEST CARD MULTIPLEXER Size Document Number REV B CAD DATA C9906 3 Date September 15 1999 Sheet 2 of 2 Copyright 1999 Fujitsu Microelectronics Europe GmbH Page 17 of 26 November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 co FUJITSU A 1 DK86061 3 12 bit 400MSa s DAC Evaluation Board Components Not Fitted to the PCB Table A1 Components Not Fitted Reference Value Description LK1a b c d Power supply selection jumper links LK2 PSRR jumper link LK3 Single ended output selection jumper link LK9 Input data termination selection jumper link J2 J4 J6 J8 J10 J11 SMA SMB SMA SMB connectors J13 J14 J16 to J20 to J44 evens J45 J3 J5 BNC BNC connectors D1 TCO4BCZM Reference diode RL1 RF103 12 Output selection relay C4 150uF Optional power supply decoupling capacitor C9 C78 33pF Analog output RC network capacitors C60 to C61 C72 to C77
16. aces covers 2 pages Sheet2 ECL data input multiplexers including SMA SMB input data connectors covers 2 pages Copyright O 1999 Fujitsu Microelectronics Europe GmbH Page 13 of 26 co FUJITSU November 1999 Version 3 2 FME MS SFDAC1E UM 1 4133 DK86061 3 12 bit 400MSa s DAC Evaluation Board 52N D 2VS D 2VF DGND D 3 3VF D 3 3VS OPTS OPTF 3 3VS 43 3VF SGND 2VF 24S 5V 412V RELAY ANALOGU APP GND 1 2 3 4 5 6 7 8 9 RVBRSSADVV RRGVHHSSDS EEASUUUUDS FFPSPPBB domaJ oo0 n cta SS 72 oy 100n VEE VDD R30 R25 R20 VIS o 10K 10K OR R29 J14 R26 75R tt TOK R28 C16 m R19 75R 100n 10K 40K o 2 ss C13 APP GND 100n Dv Dv Dv Dv Page 14 of 26 Copyright O 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 DK86061 3 12 bit 400MSa s DAC Evaluation Board PL1 ololololololololololo oQ 12h 2p pr 2 2 1 1 1 1 1 3 5 f 4 1 3 Jo 2 u o 7 9 8 5 7 4 6 3 5 2 Ez 1 KYSS RVSS TEST MDO R78 MD1 R79 MD2 E MD3 g MD4 S S MD5 g MD6 E E MD7 g MD8 g El E MD9 MD10 R88 MD11 R89 R66 1200 Laa 51R R67 MDI El 2mncro omncro c JAuom4 oo zm E E R72 z amp a m MD8 MD9 do D PAE qa op MD10 100n 100n 100n 100n 100n NDD R30 OR 200R FUJITSU MICROELECTRONICS EUROPE
17. ble data generators For this a second set of SMA SMB connectors again not normally fitted SMA not recommended due to insufficient space to rotate the body are also available The setup of the device is controlled by on board DIP switches but these controls can be accessed and overridden via a male D type connector if remote control is required The evaluation board has been designed to address requirements of both automatic and conventional bench testing Standard evaluation boards feature a simplified build state where certain components and connectors are omitted These omissions are documented in Appendix A with the evaluation board schematics This User Manual is intended to document the DK86061 3 Development Kit PCB titled MB86061 DAC TEST CARD ISSUE 3 only Copyright O 1999 Fujitsu Microelectronics Europe GmbH Page 5 of 26 co FUJITSU November 1999 Version 3 2 FME MS SFDAC1E UM 1 4133 DK86061 3 12 bit 400MSa s DAC Evaluation Board 2 Evaluation Board 2 1 Power Supply The DK86061 3 evaluation board requires two low voltage DC supplies and a number of other low voltage DC supplies depending upon build configuration marked T A cable mounting socket suitable for mating with the PCB mounted power plug is supplied with the development board Additional sockets type Weidm ller BL3 5 16 may be obtained from RS Components http rswww com Stock no 216 2683 The power should be connected to the board via this connector as
18. d RESET mode B Device in normal operating mode A Note SW1 may appear to malfunction if pressure is placed on the slider when in either the left or right position In this case the DAC control pin will be floating Page 8 of 26 Copyright 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 DK86061 3 12 bit 400MSa s DAC Evaluation Board 2 2 2 Jumper Links Table 4 Jumper Links co FUJITSU Link Name Mode Function Setting LK1AT Optional supply used for VDD 1 to 2 linked VDD Common supply used for VDD 2 to 3 linked LK1BT Optional supply used for CVDD 1 to 2 linked CVDD Common supply used for CVDD 2 to 3 linked LK1CT Optional supply used for RVDD 1 to 2 linked RVDD Common supply used for RVDD 2 to 3 linked LK1DT Optional supply used for AVDD 1 to 2 linked AVDD Common supply used for AVDD 2 to 3 linked LK2T Power supply ripple rejection disabled Linked PSRR Power supply ripple rejection enabled Not Linked LK3 Select single ended output Linked SEOUT Select differential output Not linked LK4 Centre tap of T1 linked to AVSS Linked CMRR Centre tap of T1 decoupled to AVSS Not linked LK5 CLK IN Ground linked to CVSS Linked CLK IN Ground floating Not Linked LK6 CLK OUT biasing enabled Linked CLK OUT biasing disabled Not Linked LK7 CLK OUT Ground linked to VSS Linked CLK OUT Ground f
19. itions If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan the prior authorization by Japanese government should be required for export of those products from Japan FME MS SFDAC1E UM_1 4133 3 2 Page 26 of 26 Copyright 1999 Fujitsu Microelectronics Europe GmbH
20. ling this device Copyright 1999 Fujitsu Limited Tokyo Japan Fujitsu Microelectronics Europe GmbH and Fujitsu Microelectronics Inc USA All Rights Reserved The information contained in this document has been carefully checked and is believed to be entirely reliable However Fujitsu and its subsidiaries assume no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Fujitsu Page 2 of 26 Fujitsu Limited and its subsidiaries reserve the right to change products or specifications without notice No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without the prior consent of Fujitsu Copyright 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 DK86061 3 12 bit 400MSa s DAC Evaluation Board 1 OVErVIEW sonar 2 Evaluation Board io a RON 21 Power Supply ss i oett ee LAS 2 2 Board and Interface ControlS 22 1 OWNCNES aia ese ai 2 22 Jumper LinkS oocoocccccocnnno ooo 3 Getting Started noc a nd e caf a 4 Tesi ssssun xuaukteks nazi ek ke rh ae pac a Appendix A Evaluation Board Circuit Diagrams A 1 X Components Not Fitted to the PCB A 2 Changes to PCB Schematics Appendix B Component Overlays
21. loating Not Linked LK8 DAC input terminated toDVSS 1 to 2 Linked DAC input terminated to VEE 2 to 3 Linked LK9 Multiplexer data input terminated to DVSS 1 to 2 Linked Multiplexer data input terminated to VEE 2 to 3 Linked LK10 DIFF OUT Ground linked to AVSS Linked DIFF OUT Ground floating Not Linked Note Bold type indicates default jumper settings T Standard Evaluation Kits are not configured to use the optional power supply LK1 amp LK2 are not used t Standard Evaluation Kits are configured for Differential output LK3 is not used Copyright O 1999 Fujitsu Microelectronics Europe GmbH Page 9 of 26 November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 co FUJITSU DK86061 3 12 bit 400MSa s DAC Evaluation Board This page left intentionally blank Page 10 of 26 Copyright O 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 co FUJITSU DK86061 3 12 bit 400MSa s DAC Evaluation Board 3 Getting Started This Chapter documents the basic steps to powering up and starting to use the DK86061 3 Evaluation Board Component references may be cross referenced with the component overlay in Appendix B Step 1 Configure board for data input format The data input format must be configured to either Offset Binary or 2 s Complement Use configuration switch SW1 1 to select The device control signals should be set to the default conditions shown in Section 2 2 Use configuration switch SW1
22. ordering The information and circuit diagrams in this document presented as examples of semiconductor device applications and are not intended to be incorporated in devices for actual use Also FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams FUJITSU semiconductor devices are intended for use in standard applications computers office automation and other office equipment industrial communications and measurement equipment personal or household devices etc CAUTION Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physica injury or property damage or where extremely high levels of reliability are demanded such as aerospace systems atomic energy controls sea floor repeaters vehicle operating controls medical devices for life support etc are requested to consult with FUJITSU sales representatives before such use The company will not be responsible for damages arising from such use without prior approval Any semiconductor devices have inherently a certain rate of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating cond
23. s performance The limitation of adopting a high DAC conversion rate then becomes data generation These issues should be considered when testing the MB86061 and measurements should be obtained at different conversion rates to establish the most appropriate operating conditions for the target application For convenience the board has been configured using soldered zero ohm links as a transformer coupled differential output To enable single ended outputs changes to the soldered zero ohm links would be required For rise fall time tests the transformer coupled output should not be used since the transformer response will limit the dV dt The DAC current switches are designed to give the best possible differential performance at the expense of some single ended performance so there is a noticeable difference between the two configurations The revised analog output circuit uses an additional transmission line transformer to improve rejection of common mode distortion at the DAC output If a spectrum analyser is used to measure the output spectrum this must have very good noise and distortion for example HP8562E or R amp S FSEA30 In addition the input attenuator setting should be chosen such that input mixer distortion does not limit the measurements e g 30dB RF attenuation This implies that narrow resolution bandwidths and or averaging are required to obtain low enough measurement noise floor Input data can be generated with an Arbitrary Wa
24. us Y sTi C18 Cis 1 4 El TP RVOD 33 5 Ris lazo 22 512 arms RVSS EJ 53 cz i wu e CLKB en AREF e EVE LK ai2 E ue EVES n3 IN 1 34 sra A wa LL nas Tera nb UN UN lt lt E e OF I deenl fing Power be O ame A L CRE Tis AVDD AVSS a Clock In Tee ste cs 1x2 Us AVDD ste AvoD UU PSRR smie PERS IOUTB nts ja IOUT po EJ EN m T 45V DIFF i of be Gut T2 412V Er SEDUT 33 7 ss Differential Out Figure 2 2 Evaluation Board Component Side Layout Copyright 1999 Fujitsu Microelectronics Europe GmbH Page 7 of 26 November 1999 Version 3 2 FME MS SFDAC1E UM_ 1 4133 co FUJITSU 2 2 1 Switches DK86061 3 12 bit 400MSa s DAC Evaluation Board There are several control switches on the evaluation board as shown in Figure 2 2 Switch idents are marked on the board silk screen Table 1 Switch 1 Settings Switch Mode Function Settings SW1 1 Offset binary input data VSS TWOC 2 s Compliment input data VDD SW1 2 3 Segment Shuffling disabled VSS VSS HUFO SHUF1 i Random every 4 cycles VDD VSS Random every 8 cycles VSS VDD Random every 16 cycles VDD VDD SW1 4 Factory Use Only VSS TEST Table 2 Switch 2 Settings Switch Mode Function Setting SW2 Device Reset Push to Reset Table 3 Switch 3 Settings Switch Mode Function Setting SW3 Device in force
25. veform Generator for example a Sony Tektronix AWG520 This can produce 10 bit ECL data set the digital output to 0 2V to 0 8V and a data clock Care should be taken to ensure that the data cables and the clock cable are the same length so as to avoid any shift in the clock to data timing relationship However the phase of the AWGs clock out may be outside the DACs allowable range If so a low noise signal generator such as the Marconi 2042 could be used to provide the clock This has the facility to adjust the phase of the output signal compared with its frequency standard output which is driving the AWGs 10MHz reference input Page 12 of 26 Copyright O 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1E UM_1 4133 co FUJITSU DK86061 3 12 bit 400MSa s DAC Evaluation Board Appendix A Evaluation Board Circuit Diagrams Appendix A shows the circuit diagrams of the DK86061 3 evaluation board Note that these diagrams are for reference only and that some components fitted to the board may be of a different value to the schematics or not fitted at all Fujitsu has undertaken to document these changes where possible The schematic is divided over four pages for clarity Two 12 bit wide data busses are used to minimize diagram complexity and are referred to as the Data bus DOA DOB to D11A D11B and the Multiplexer Data bus MDO to MD1 1 Sheet 1 Main DAC support circuitry including analog output interf
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