Manual - Lumistar
Contents
1. 24 U4400101 Lumistar Inc Page 3 12 07 07 5 044 Quad Bit Synchronizer User s Manual List of Figures Figure 2 1 15 40 Block Component Layout eene nnne nnne nna nnns 6 Figure 2 2 LS 44 Front and Rear Panel 7 Figure S 1 Configuration Shunt BIOCKS oit a 10 Figure 3 2 LS 44 connections to AC power and PC peripherals 11 Figure 3 3 15 44 Primary PCM Processing Engine Interface 12 Figure 3 4 LS 44 Auxiliary PCM Processing Engine Interface Connections 13 Figure 4 1 LS 44 QBS Host Software Status Display 14 Figure 4 2 LS 44 QBS Host Software 4 nnn nnn nnns 15 Figure 4 3 Bit Sync Setup 1 16 Figure 4 4 Bitsync FSP History 9 n nnns nnn nnns 19 Figure 4 5 BERT Pattern 21 Figure 4 6 BEHT Pattermn So rce Intermal E et e ec aa de ota mde 21 Figure 4 7 LS 44 QBS Remote Software Status nnne nnns 22 Figure 4 8 Network Management 23 List of Tables Table 2 1 LS 44 Technical Specifications c cc cseeececececcceseneeeeeeesecceeseeceeescccoesseeeecenssecesssene2. Differential PCM Input Future Growth Differential PCM Input Future Growth Future Growth Future Growth PCM Single Ended Input Select Future Growth Input Future Growth Differential Input Select Future Growth Diff Input 100 Ohm Termination Notes 1 All shunts shown in the default configuration Diff Input 100 Ohm 2 Shunts denoted with an asterisk are user configuration items Termination Figure 3 1 Configuration Shunt Blocks The LS 44 is shipped with the PCM input selection for each channel set to single ended mode To configure a particular PCM processing channel to utilize differential inputs the shunt connecting pins 31 and 34 should be moved to connect pins 34 and 37 The unit is shipped with differential input termination impedances of 100 ohms Removing the shunt between pins 29 and 32 and the shunt between pins 35 and 38 will allow the differential input impedance to be loaded with 7 5K ohms 3 2 Installation The LS 44 assembly is provided with removable mounting flanges In the event that the unit will not be installed in a 19 rack the mounting flanges may be removed by extracting three mounting screws on each flange U4400101 Lumistar Inc Page 10 12 07 07 5 044 Quad Bit Synch
3. 6 DM M DM S M S RNRZ L RNRZ S RNRZ M 22 12 lee Control Status 640 480 Standard PS2 style interfaces Temperature Operational 0 to 70 C Commercial Temperature Storage 20 to 70 C Humidity non condensing 40 0 90 gt 40 C 0 to 75 N Environmental U4400101 Lumistar Inc Page 8 12 07 07 5 044 Quad Bit Synchronizer User s Manual 3 Hardware Configuration Installation 3 1 Hardware Configuration The LS 44 has been shipped with the internal hardware configuration set for the most common operating environments The LS 44 does not require access of any internal configuration settings under normal circumstances However in situations where differential inputs are required for one or more PCM processing channels it is necessary to remove the top cover of the unit and adjust internal configuration jumpers Warning Prior to removing the top cover of the 15 044 turn of the Master power switch and remove the AC power cord from the unit The top cover of the unit is attached with eight 8 4 flathead Philips screws Remove and retain these screws to expose the interior of the unit Once the cover has been removed the interior will appear as shown in Figure 2 1 Viewing the unit from the front panel of the chassis four groups of configuration blocks will appear along the right hand edge of the PCM Processing Engine motherboard assembly Silk screen nomenclatur
4. Seege Reload About Enter Number of bitsynes installed Number of Bitsyncs 2 4 Colors The user also customize the appearance of the displays by selecting the Colors command from the Config menu The color scheme may be configured for the Background the Data text and the Labels Select the item of interest from the colors menu and select the desired color from the resulting dialog box as shown below The use may select a color from a pre defined pallet of colors or define a new custom color 15 44 Host Ver 1 25 mrmnmmr misr mi mE Sg 1 Se eee Number of Biksyncs ET BIS T TERES Data EEEE Jm L h Cantar 1 9062 Reload About Framesync Status SEARCH E SESE Eee U4400101 Lumistar Inc Page 15 12 07 07 5 044 Quad Bit Synchronizer User s Manual After configuring the LS 44 QBS software save the configuration by selecting the File command from the top level menu and then select the Save As command as shown left Enter a file name for the configuration from the resulting file Save dialog box and click the Save button After the configuration UE Bitsyne setup has been saved in this manner it may be recalled and loaded Recall by selecting the Recall command from the menu 8 44 Host Ver 1 25 Config Reload About The LS
5. 15 044 Series Rackmount Multi channel Digital Bit Synchronizer Hardware and Software User s Manual U44000101 Date 6 December 2007 Lumistar Inc 2701 Loker Ave West Suite 230 Carlsbad CA 92010 760 431 2181 www lumi star com This document is the intellectual property of Lumistar Inc The document contains proprietary and confidential information Reproduction disclosure or distribution of this document is prohibited without the explicit written consent of Lumistar Inc This document is provided as is with no warranties of any kind Lumistar Inc disclaims and excludes all other warranties and product liability expressed or implied including but not limited to any implied warranties of merchantability or fitness for a particular purpose or use liability for negligence in manufacture or shipment of product liability for injury to persons or property or for any incidental consequential punitive or exemplary damages In no event will Lumistar Inc be liable for any lost revenue or profits or other indirect incidental and consequential damages even if Lumistar Inc has been advised of such possibilities as a result of this document or the usage of items described within The entire liability of Lumistar Inc shall be limited to the amount paid for this document and its contents RESTRICTED RIGHTS LEGEND Use duplication or disclosure by the Government is subject to restrictions set forth in subparagraph c 1
6. 2 e e 5o Pattern Source Disabled Pattern Source External PAN Pattern 15 Bit Forced Error OFF BT 2211 Communications Communications O Mersinn DW Version 0057 Power e 09939 Power Man oos Error Count Clock Count 499996 Clock Count 4999966 Offset Freg Hz 3 2D ODE 1 Offset Freg Hz 3 4000 1 AGC Threshold M 3B AGC Threshold M 3 5 dE 14 0 dB 14 0 BER 0 0000 0 Figure 4 5 BERT Pattern Disabled Figure 4 6 BERT Pattern Source External The Extended Functions Display The Remote application shown in figure 4 7 below runs on a separate desktop or other Windows PC and provides graphical setup and control for up to four LS 40 bit syncs installed in the remote 5 44 chassis With the slight exception of the Network Info section the displays of the Remote application are identical to those of the Host application described earlier 14400101 Lumistar Inc Page 21 12 07 07 5 044 Quad Bit Synchronizer User s Manual 15 44 Remote Ver 1 21 File Config Reload Select Host About Setup Hetwork Info B S 1 B S 4 Viewing Le 44 Number 1 IP Address 192 169 016 050 Bitsync 1 Lock 1 Bit Rate 5 0 Mbps Bitsync Status Scan Input Code MEL e Loop width 0 1 Fitter Method NOME Output Code BIOL Lock State Quick React OFF BS o 5 o 9 FSP Disabled FS FSP Rate D View History Vi
7. Input CH4 Diff PCM Input CH4 Threshold Output CH3 19 10 1 piccole dede ig Pins 20 through 37 are Ground Figure 3 4 LS 44 Auxiliary PCM Processing Engine Interface Connections U4400101 Lumistar Inc Page 13 12 07 07 5 044 Quad Bit Synchronizer User s Manual 4 Software Application The LS 44 is configured with a Microsoft Windows application for both local and remote IP network control and setup of the bit sync hardware The LS 44 QBS software consists of two executables The Host application shown in figure 4 1 below runs on the LS 44 and provides graphical setup and control for up to four LS 40 bit syncs The Remote application shown in Figure 4 7 on page 22 runs on a separate desktop or other Windows PC and provides graphical setup and control for up to four LS 40 bit syncs installed in the remote LS 44 chassis v 8 44 Host Ver 1 28 Config Reload About Hetwork Info Host GBa4 n007 Sddres 192 168 16 50 Bitsync Setup 851 52 Bis 4 1 LOCK Bit Rate 5 0 Mbps Bitsync Status Scan Input Code MEL 2 Loop Width 0 1 Filter Method Output Code React OFF FSP Mode Disabled FSP Rate 0 Lock State B5 2 9 OGG View Extended Functions Extended Functions 1 Bitswnc 2 Bitswnc 3 Bitzync 4 1 e oe 9 Pattern Source Disabl
8. ii of the rights in Technical Data and Computer Software clause in DFARS 252 227 7013 Lumistar Inc and its logo are trademarks of Lumistar Inc All other brand names and product names contained in this document are trademarks registered trademarks or trade names of their respective holders 2007 Lumistar Inc All rights reserved Lumistar Inc 2 01 Loker Avenue West 230 Carlsbad CA 92010 760 431 2181 760 431 2665 Fax www lumi star com 5 044 Quad Bit Synchronizer User s Manual 1 Hoe 5 1 1 5 RE NIS 5 2 PRODUCT OVERVIEW AND TECHNICAL SPECIFICATIONS 6 2 1 PRODUCT OVER VIEW T 6 22 TECHNICAL SPECIFICA TIONS du 8 3 HARDWARE CONFIGURATION INSTALLATION 9 3 1 FIABDWARECGONPEIGUBATIONG es ed ctun ILLE Ad ace ice e 9 S N TALAT s RR 10 4 SOFTWARE APPLICATION eue ace eue euo Ces eo 14 5 MAINTENANCE EM LU c c ae CORE REE Sar S LM IDE MALIS
9. upgrades the unit also contains a 1 44MB floppy drive which is accessible from the front panel BNC jacks are provided on the rear panel for primary PCM engine interfaces Auxiliary PCM interfaces are provided through two D style 37 pin rear panel connectors Figure 2 1 provides a block component layout diagram of the internal components of the LS 44 system Figure 2 2 shows a front and rear panel view of the LS 44 chassis BIT SYNC 3 BIT SYNC 4 SYNC 1 SYNC 2 Configuration Shunts 4 sets O O O g Og Hg Hg Lumistar PCM Processing Engine Quad Fan Assembly 586 class SBC Figure 2 1 LS 40 Block Component Layout Diagram U4400101 Lumistar Inc Page 6 12 07 07 5 044 Quad Bit Synchronizer User s Manual Front Panel View PCM Processing Engine Status Indicators Cooling Air Inlet Filter STATUS INDICTAORS PLL ENG NK NECI 1 44 Master Power Switch Master Power Indicator Rear Panel View Cooling Air Exhaust Vents AC Power Jack PCM I O Parallel I O Future SBC Status LEDs RS 232 Serial Growth SBC Reset Button Primary PCM I O 4 sets Ethernet Activity LEDs Growth Monitor Connector Ethernet Interface Growth Keyboard Mouse Connector Figure 2 2 LS 44 Front and Rear Panel Views 14400101 Lumistar Inc Page 7 12 07
10. 07 5 044 Quad Bit Synchronizer User s Manual 2 2 Technical Specifications The table below provides technical specifications for the LS 44 system Table 2 1 15 44 Technical Specifications Category Specifications Details Chassis Dimensions 19 W x 21 D x 1 75 H 2 FomFrFado AU Chassis 0722 35lbs 15 9K9 2 i Supply Voltage 7 100 120 200 240 Auto switched AC Supply Frequency 442 Total Power S00W PCM Input Channel Characteristics 1 4 channels Quantity 1 SE Differential Input Jumper Selected Impedance 50 750riKOQ JumperSelectable Rate 50 20Mbps NRZ Codes 50 10Mbps others Polarity Normal or Inverse Software Programmable SignalAmplitude 0 Vtot10Vpp Voltage permissible 25V RMS LBW settings 0 01 to 2 data rate dependent Acquisition Range 4 x LBW Setting Tracking Range 10xLBWSeting Mean Acquisition Time PCM Output Channel Characteristics 1 4 channels 222 NRZLDataOupt TTL TTIL 0 Po 8 Clock Output TTT PPCM Output X s 1Vp pQ509 Programmable Line Codes POM PRN Output future TTL TTL Programmable Line Codes POM PRN Patterns future 2 1 27 1 Programmable PCM Line Codes NRZ L NRZ M NRZ S
11. 44 QBS Host software status display shown in Figure 4 1 on page 14 has six major functional status display areas These include Bitsync Setup Network Info Bitsync Status Scan Lock State Bitsync FSP History and Extended Functions Each will be discussed in the following paragraphs The Bitsync Setup display shown in figure 4 3 below will have from one to four individual tabs corresponding to each LS 40 bit sync installed in the chassis To configure any of the eight 8 setup parameters shown in the display simply place the mouse cursor anywhere within the display Immediately a text box will appear stating Right click to set up the bitsync Bitsync Setup 5 1 2 1 Framesyne Status Bit Rate Input Code Loop width Filter Output Code React FSP Mode FSP Rate LOCK Lock 5 0 Mbps 0 02 MONE Enabled 1221 Figure 4 3 Bit Sync Setup Display Bit Rate The eight bit sync setup functions are shown right They include Bit Hate Input Code Input Code Loop Bandwidth Use Filter Output Code Quick React Mode FSP add Mode and FSP Mode Setup Each setup function will be described in the Output Cade k following paragraphs Quick React Mode FSP Made Input Value between 10 amp 200 00 00000 Rate The LS 40 DB20 Bit Synchronizer 1 can operate over input range of 100 bits per second to 20 Mbps for all NR
12. FSP Lsw Msw The frame synchronization pattern is a unique binary bit pattern used to indicate the beginning of a telemetry minor frame To achieve this a frame synchronizer is employed with a correlator amp state machine circuitry that recognizes unique bit patterns indicating the beginning of minor frame data The frame synchronizer typically searches for patterns checks for the recurrence of the pattern in the same position for several frame periods and then locks on the pattern In this application the frame synchronization pattern entered by the user in two 32 bit words designated as FSP Msw most significant word and FSP Lsw least significant word U4400101 Lumistar Inc Page 18 12 07 07 5 044 Quad Bit Synchronizer User s Manual The Network Info display shown right lists both the host name and its local network IP address This information is Hetwork Info needed for example when the user runs the Remote Host joeblowasdf Application a different Windows machine connected to Address 1921681646 the same local area network as the 15 44 Note the Remote Application has only been tested where the LS 44 and the Remote Windows machine are on the same LAN Remote operation of the LS 44 over a wide area network WAN or the Internet has not been tested REUTERS The Bitsync Status Scan and the Lock State display both shown left present information about the 15 40 bit sync s installed in the chassi
13. Z codes or from 100 bits per second to 10 Mbps for the Bi Phase and Miller codes The LS 40 DB10 is limited to 10 Mbps for NRZ codes and 5 Mbps for the Bi Phase and Miller codes By invoking the Bit Rate command the user may enter the required input data rate in bits per second FSP Mode Setup U4400101 Lumistar Inc Page 16 12 07 07 5 044 Quad Bit Synchronizer User s Manual Input Code The LS 40 Bit Synchronizer supports the PCM input Bit Rate NRZL code types specified in the figure below Both normal and inverted a variants are available To select the appropriate input code invoke Output Code BIOL the Input Code command and select the specific input code from the Quick React Mode 2 drop down list wv FSP Mode DMM PSP Mode Setup Drs Table 4 1 LS 40 Supported PCM Input Codes normal or inverted 2 NRZ codes NRZ L NRZ M NRZ S RZ ide oplit phase codes BiPhase L BiPhase M BiPhase S s Miller codes DM M DM S 2 M S INV MRZM INV_NRZS Randomized codes RNRZ L RNRZ M RNRZ S 1 Randomization 511 4 515 4 517 4 523 4 INY DMM sequence INV RNRZ11 INV 215 INV 21 INV RMRZ23 Bit Rate Loop Bandwidth The Loop Bandwidth of the PLL circuit in the LS 40 may be programmed by the user from 0 01 to 2 depending on the bit rate of the input signal The Acquisition Range 0 04 to 8 depending Output Code 05 on the Loop Bandwidth selected and the Tracki
14. bps to 20Mbps for NRZ PCM codes and 100bps to 10Mbps for all other support PCM codes The LS 44 enclosure is a space saving 1U 19 inch rackmount chassis The unit can be purchased with an optional 1U rackmount monitor keyboard drawer that contains a built in 8 channel keyboard video mouse switch The optional keyboard would allow a single point of control for up to eight separate LS 44 chassis 1 2 Manual Format This manual is separated into the following sections Chapter 1 provides an introduction to this manual Chapter 2 provides a brief product overview and technical specifications Chapter 3 provides hardware configuration and installation instructions Chapter 4 provides software application instructions Chapter 5 provides maintenance instructions U4400101 Lumistar Inc Page 5 12 07 07 LS 044 Quad Bit Synchronizer User s Manual 2 Product Overview and Technical Specifications 2 1 Product Overview The LS 44 is a self contained PCM recovery system The core PCM processing engine contains up to four Lumistar LS 40 Digital Bit Synchronizers Control and status of the PCM processing engine is provided by an internal 586 class Single Board Computer SBC Power is converted and supplied to both the SBC and the PCM processing engine by an ATX style power supply Filtered cooling air is supplied to internal components via four 10 8 CFM fans Evacuation airflow is provided via the sides and the rear of the unit To allow for future
15. dress from the list as shown right To shut down a specific host chassis invoke the Host Shut Down Single command from the Config menu and select the desired IP address from the list as shown lower right To shut down all of the LS 44 chassis defined in the host table shown in figure 4 8 invoke the Host Shut Down All command from the Config menu Network Management Include These Host L5 44 This IP Address 132 158 1 5 This PC Mame joeblowabdt Y ip Cancel Nw Jet Figure 4 8 Network Management Host 16 44 Remote Ver 1 18 File Sei Reload Select Host Hosts Colors Host Shut Down Single 15 44 Remote Ver 1 18 Hast Shut Down All File Config Reload 233 5 About 0 192 168 016 053 16 165 016 049 15 44 Remote Ver 1 18 File eee Reload Select Host About Hosts Colors me I Viewing 3 2 192 168 016 053 1 192 168 016 043 Host Shut Down Single Hast Shuk Down All Note With no input signal applied it is normal operation to see the SIG LED on the front panel and the signal status indication periodically display that a signal is present Note With no input signal applied it is normal operation to see the BIT LED on the front panel blink at a 5 Hz rate This is an indication of PCM AGC processing reset cycles 14400101 Lumistar Inc Page 23 12 07 07 5 044 Quad B
16. e right The user may Pause the display define the Max History Length of the display and Clear History The maximum history length may be set from 1 to 86 400 seconds View History View History wv Bitsync FSP BER History Bitsync FSP BER History B 51 52 B s 4 B 51 gis 2 5 4 Expected FSP Rate 1220 70 Bate State 0400 5 0600 5 5 5 0400 5 0400 5 0400 5 0400 5 0400 5 0400 5 0400 5 5 Figure 4 4 Bit Sync FSP BER History Display 3 3 3 3 3 3 3 3 3 3 3 3 U4400101 Lumistar Inc Page 19 12 07 07 5 044 Quad Bit Synchronizer User s Manual The Extended Functions display shown in figures 4 5 amp 4 5 on page 21 has several modes of appearance depending PRN Pattern External what BERT pattern mode was selected To set the mode 9 Forced Error Disabled place the mouse cursor within the display and right click The resulting menu displayed above right allows the user to select the BERT Pattern Source the PRN Pattern and optionally to Force Error in the pattern When the Pattern Source is Disabled the Extended Functions display will appear as shown in Figure 4 5 on page 21 If the Pattern Source is either nternal or External then the Extended Functions display will appear as shown in Figure 4 6 on page 21 To display the i
17. e will appear along the right hand chassis wall identifying which channel each individual PCM processor is controlling Each PCM processor has a respective configuration header Table 3 1 identifies the configuration jumper headers for each PCM processing channel Table 3 1 PCM Channel Configuration Shunt Block Reference Designators PCM Channel Number Ref Designator JP1 2 JP2 3 JP3 4 A silk screened reference designator will appear next to each PCM processor configuration shunt block indicating the Pin 1 location of each header These headers are used to route various signals to and from the rear panel interface connectors to configure the input source selection and to adjust termination values for the differential input signals Figure 3 1 provides a detailed drawing of the configuration shunt blocks Default jumper configurations are shown The user should not alter the first nine installed shunts Shunts designated with an asterisk in Figure 3 1 are user configuration items U4400101 Lumistar Inc Page 9 12 07 07 5 044 Quad Bit Synchronizer User s Manual Threshold Output Future Growth PLL Lock Output Future Growth Es No Quality Output Future Growth BIT Status Output Future Growth PRN Test Output Future Growth NRZL Output Future Growth CLK Output Future Growth
18. ed Bitsync FSP BER History Bis gis2 Bis 4 0000 0 ek BT e 0000 0 oO oO oO Figure 4 1 15 44 QBS Host Software Status Display U4400101 Oooo Communications Version Power Clock Count 4999972 Offset Freg Hz 2 0 1 AGC Threshold 3 7 Es Mo dB 14 0 Lumistar Inc 5 044 Quad Bit Synchronizer User s Manual Upon power up of the LS 44 chassis the 15 44 QBS Host software application will begin running automatically The Host application will initially be in an un configured state as shown in figure 4 2 below The Host application s top level commands include File Config Reload and About Each will be described in subsequent paragraphs X 15 44 Host Ver 1 75 File Config Reload About Host jasebloaw asdf F Address 192 168 16 46 Figure 4 2 LS 44 QBS Host Software Status Display in Un configured State The first step in configuring the LS 44 is to specify the number of LS 40 bit syncs installed in the chassis From the Config menu select the Number of Bitsync command and then enter the number of bit syncs in the resulting dialog box as shown below Input Value 515 44 Host Ver 1 28
19. ew Extended Functions w Bitsyne FSP BER History Extended Functions pis 2 eis a 884 Lr tune 2 2 nonc d e e 26060 Pattern Source Disabled 0600 5 5 00 5 Communications 0 5 OW Verion 0600E 5 1 B5 0E 5 Power Man 0600E 5 O600E 5 O600E 5 Clock Count 43333 00 5 Offset Freq Hz 3 2000E 1 5 AGC Threshold v 3 6 0 5 dE 14 0 0600 5 DI Wi OF Figure 4 7 15 44 QBS Remote Software Status Display The Network Info display shown in the figure above right lists the host name and its local network IP address of the selected LS 44 chassis Note the Remote Application has only been tested where the LS 44 and the Remote Windows machine are on the same LAN Remote operation of the LS 44 over a wide area network WAN or the Internet has not been tested 14400101 Lumistar Inc Page 22 12 07 07 5 044 Quad Bit Synchronizer User s Manual To configure the Remote Application first invoke the Config command from the top level menu and select the Hosts command as shown upper right The resulting display is shown in figure 4 8 below Enter the IP address of each LS 44 chassis to be controlled remotely and then click the Accept button Next select a specific host LS 44 chassis to control remotely by invoking the Select Host command from the top level menu and select the desired IP ad
20. greatly increases the speed of reacquisition when the incoming signal experience fades dropouts or other interruptions By selecting the Quick Heact Mode command from the menu the control loops that govern signal offset AGC automatic gain control and the Costas Loop are all placed into a quasi freeze state When the input signal interruption ends the LS 40 attempts to reacquire the signal with all of its internal loop states essentially the same as before the interruption The Quick React Mode should not be used when the LS 40 is trying to acquire a signal for the first time For this reason the Quick React Mode is always disabled when the Host application first starts running FSP Mode The LS 40 bit sync has the unique feature of being able to lock onto the frame sync pattern of an incoming signal To achieve this a frame synchronizer is employed with a correlator amp state machine circuitry that recognize the unique bit patterns indicating the beginning of a minor frame of data The frame synchronizer typically searches for patterns checks for the recurrence of the pattern in the same position for several frame periods and then locks on the pattern To enable this feature the user must select the FSP Mode command from the setup menu A check mark next to the command will result indicating the status Also note that when this function is enabled the Framesync Status Lock indicator will also appear in the Bitsync Status display windo
21. it Synchronizer User s Manual 5 Maintenance The LS 44 Rack Mount system requires minimal maintenance The only user maintenance that is required is the periodic cleaning of the air inlet filter and the inspection cleaning of the air exhaust ports Refer to the Figure 2 2 on page 7 To clean the air inlet filter remove the two thumbscrews on the front panel of the LS 44 Remove the filter insert and clean excess dust from the filter with a clean dry pressurized air Reinstall the filter and reattach the filter cover using the thumbscrews Inspection of the airflow exhaust vents can be made from the rear of the LS 44 there is excess of dust build up in the air exhaust ports perform the following steps 1 Remove AC power from the LS 44 2 Remove the unit from its mounting fixture 3 Remove the top cover by removing the eight securing screws 4 Direct a clean dry pressurized air source at the rear panel air exhaust ports from the inside of the unit 5 Direct a clean dry pressurized air source at the side panel air exhaust ports from the inside of the unit 6 Inspect the power supply fan assembly and air inlet ducts for excessive dust if necessary 7 Reinstall the top cover 8 Reinstall in the mounting fixture 9 Reapply AC power to the LS 44 14400101 Lumistar Inc Page 24 12 07 07
22. ndividual meaning of each of the LEDs simply hover the mouse cursor over each LED and an explanation of the LEDs function will appear A summary of the LED functions is shown in Table 4 3 below Paten Saee The user may select either an 11 bit pattern or a 15 pattern as 11 Bit shown right When the BERT pattern is disabled the Extended Functions display will indicate the Pattern Source the BIT status the Communications status the SW Version Power Management status the Clock Count the Offset Frequency Hz the AGC Threshold Voltage and the Es No measured by the bit sync In addition when the BERT pattern is nternal or External the Extended Functions display will also indicate the Pattern selected the Forced Error mode status the Error Count and the BER Bit Error Rate measured by the BERT Table 4 3 Extended Functions LED Meanings Forced Error 15 1 Pattern 1 Bitsync Status 13 Syntax Error 2 Inout Signal Above Threshold 14 Protocol Error PLL Lock 15 3 3 VDC 6 3 4 Input Quality Above Threshold 6 18 42VDC 7 Synchronization Flag 12 VDC 12 Semantic Ero 4 O VCC 5 VDC 8 0 14400101 Lumistar Inc Page 20 12 07 07 5 044 Quad Bit Synchronizer User s Manual View Extended Functions Extended Functions Extended Functions Bitsenc 1 Bitsunc 2 Bitsyne 3 Bitsunc 4 Bitzync 1 Bitzunc 2 Bitsunc 3 Bitsync 4 e
23. ng Range 0 196 to 2096 v QuickReact mode again depending the Loop Bandwidth selected are both heavily vrspmode 0 05 dependent on the loop bandwidth of the PLL To select the appropriate FSP Mode Setup pes loop bandwidth invoke the Loop Bandwidth command and select the specific value from the drop down list Use Filter The user may enable additional data filtering prior to the actual phase lock loop of the bit synchronizer by invoking the Use Filter command The additional filter uses a Raised Root Cosine topology and is used to improve the performance metric of the bit synchronizer Bit Rate Output Code The LS 40 Bit Synchronizer supports the PCM output cader code types specified in the table below Both normal and inverted em variants are available To select the appropriate output code invoke Output Code the Output Code command and select the specific output from the w Quick React Mode drop down list w FSP Table 4 2 LS 40 DB Supported PCM Output Codes NRZ codes NRZ L NRZ M NRZ S INV NRZ L FSP Mode Setup RZ codes RZ INV_RZ Split phase codes BiPhase L BiPhase M BiPhase S INV BIOL Miller codes DM M DM S 2 M S Randomized RNRZ L RNRZ M RNRZ S codes sequence MEMS INV IM BIOL 14400101 Lumistar Inc Page 17 12 07 07 5 044 Quad Bit Synchronizer User s Manual Quick React Mode The LS 40 bit sync design features an enhanced acquisition mode that
24. reeeeesoceseeseeeeeesees 8 Table 3 1 PCM Channel Configuration Shunt Block Reference 9 Table 3 2 LS 44 Auxiliary PCM Processing Engine Signal 12 Table 4 1 LS 40 Supported PCM Input Codes normal or 17 Table 4 4 2 LS 40 DB Supported PCM Output Codes 222220000 1 000110 nennen nennen nennen nnn 17 Table 4 3 Extended Functions LED Meanlhgs ipee tO ere etnia Iu 20 U4400101 Lumistar Inc Page 4 12 07 07 5 044 Quad Bit Synchronizer User s Manual 1 Introduction 1 1 General This document is the Hardware and Software User s Manual for the Lumistar LS 44 Series 1U Rackmount Multi channel Bit Synchronizer chassis The intent of this document is to provide unit specifications operational information and maintenance instructions for the end user The Lumistar LS 44 Multi channel Digital Bit Synchronizer chassis provides a means of obtaining correlated clock and data recovery from up to four independent PCM streams For each PCM input stream the LS 44 provides independently controllable translation of various PCM formats and provides a user programmable PCM output format which may be used for tape storage or as a means of providing PCM format translation Each PCM processing channel may be programmed to receive inputs from 100
25. ronizer User s Manual Warning The LS 044 assembly weighs approximately 35 Ibs 15Kgs weight can not be supported by the front mounting flanges alone Support the unit when mounted in a 19 rack by slides or supports An interface diagram for connecting the LS 44 to AC power keyboard interfaces mouse interfaces and a monitor is shown in Figure 3 2 IEC AC Power Cord Included Pa lt 225 lt 2 gt 2 LZ TSL 25 77 Pay LLLI CLZ Pa Ween 2 Figure 3 2 LS 44 connections to AC power and PC peripherals Interconnection to primary PCM interfaces are made via BNC male cables at the rear panel of the LS 44 Connections to a PCM processing channel are shown in Figure 3 3 Auxiliary PCM interfaces are made via the two DC 37 female connectors Mating connectors for the DC 37 Auxiliary PCM I O connectors and shrouds have been supplied with the shipment of the LS 44 Pins outs and signal names for these connectors are shown in Figure 3 4 Table 3 2 contains auxiliary PCM interface signal descriptions and detailed definitions U4400101 Lumistar Inc Page 11 12 07 07 5 044 Quad Bit Synchronizer User s Manual PCM Input Stream NRZL Data Output Single Ended PCM Output Encoder Tape Output Clock Data Output Figure 3 3 LS 44 Primary PCM Processing Engine Interface Connections Table 3 2 LS 44 Auxiliary PCM Processing Engine Signal Definitions Signal Name Type Outpu
26. s The Bitsync Status Scan shows the operator that the Host application is running and scanning each LS 40 for status The scan display is really Linc a hey I m alive and still running indication for the operator This is helpful for scenarios where none of the other displays are changing and one might question if the application had crashed or was not working The Lock State display shows both the bit sync signal lock and if enabled the frame sync lock states for each LS 40 installed If the FSP Mode is not enabled then the LED indicator next to the F S in the display will disappear The Bitsync FSP BER History display shown in figure 4 4 below will have from one to four individual tabs corresponding to each LS 40 bit Pause sync installed in the chassis To enable this display the user must first Max History Length check the View History box as shown below When the FSP mode is Clear History enable for a bit sync the FSP BER History display shows in a tabular form the time sync state and expected and actual rate of the frame sync pattern defined for the bit sync When the FSP mode for a bit sync is disabled and the BERT mode is turned on from the extended functions display see figure 4 5 and 4 6 on page 21 then the time BER and error count are displayed in a tabular form Placing the mouse cursor above the table and right clicking allows the user to control the tabular display The resulting menu is shown abov
27. t Gnd 5VDC Active low Gnd 5VDC Active low Gnd 5VDC Active low Gnd 5VDC Active low 2Vp p around ground Z 75 ohms TTL Inverted NRZL TTL Inverted CLK Differential PCM RS 422 Levels 100 ohms loaded default Differential PCM RS 422 Levels 100 ohms loaded default U4400101 Lumistar Inc Page 12 12 07 07 5 044 Quad Bit Synchronizer User s Manual Auxiliary I O Connector Threshold Output CH2 Diff PCM Input CH1 No Connection Diff PCM Input CH1 CLK Output CH1 PLL Lock Output CH2 Es No Quality Output CH2 BIT Status Output CH2 PRN Test Output CHZ NRZ L Output CH1 PRN Test Output CH1 NRZ L Output CH2 BIT Status Output CH1 Es No Quality Output CH1 PLL Lock Output CH1 Threshold Output CH1 CLK Output CH2 Diff PCM Input CH2 Diff PCM Input CH2 19 10 1 Pins 20 through 37 are Ground Threshold Output Auxiliary Connector Diff Input PLL Lock Output 4 Diff PCM Input CH3 Es No Quality Output CH4 CLK Output CH3 BIT Status Output CH4 No Connection NRZ L Output CH3 PRN Test Output CH4 PRN Test Output CH3 BIT Status Output CH3 Es No Quality Output CH3 PLL Lock Output CH3 NRZ L Output CLK Output Diff PCM
28. w shown in Figure 4 3 on page 16 FSP Mode Setup There are four paremeters that must be specified for the FSP mode to operate correctly These include the length of the frame Bits Per Frame the length of the pattern FSP Length the FSP correlator tolerance FSP Tolerance and the frame sync pattern value FSP Msw Lsw FSP MODE DATA Bits Per Frame 4096 FSP Length 32 FSP Mew 2 4 Bits Per Frame FSP Lew 000000000 FSP Length FSP Tolerance 1 FSP Tolerance FSP Law Bits Per Frame To define the major frame length in bits the E user must invoke the Bits per Frame command The user must enter a length from 24 to 65 535 bits FSP Length To enter the required frame synchronization pattern the user must first invoke the FSP Length command to specify the bit length of the frame sync pattern The length of the pattern may be up to 64 bits FSP Tolerance The user may specify the number of bits in the acquired sync pattern that may be different from the ideal pattern and still achieve amp maintain synchronization by invoking the FSP Tolerance command The user may specify that the received pattern must contain no bit errors and would thus set the tolerance to Zero 0 In a noisy signal environment such a setting would likely result in the LS 40 NEVER acquiring or maintaining frame synchronization For the noisy real world environment the user may set the bit error tolerance from 1 to 16 bits
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