Investigation of Altera DE2 Development and Education Board
Contents
1. 12 13 14 15 DRAM DRAM_UDQM DRAM_RAS_N DRAM_WE_N FL ADDR O FL ADDR 1 FL ADDR 2 FL ADDR 3 FL ADDR A FL ADDR 5 FL ADDR 6 FL ADDR 7 FL ADDR S FL ADDR 9 FL ADDR 10 FL ADDR 11 FL ADDR 12 FL ADDR 13 FL ADDR 14 FL ADDR 15 FL ADDR 16 FL ADDR 17 PIN AE3 PIN AB3 6 7 PIN_AC3 PIN_V6 PIN_AA2 PIN AA1 PIN Y3 PIN 4 PIN R8 PIN T8 PIN V7 PIN W6 PIN AB2 PIN AB1 PIN 4 PIN AA3 PIN AC2 PIN PIN AA5 PIN AD2 PIN Y5 PIN ABA PIN AD3 PIN AC18 AB18 AE19 AF19 PIN AE18 PIN AF18 PIN Y16 PIN AA16 PIN AD17 PIN AC17 PIN AE17 PIN AF17 PIN W16 PIN W15 PIN AC16 PIN AD16 PIN AE16 PIN AC15 43 FL ADDR 18 FL ADDR 19 FL ADDR 20 FL ADDR 21 FL CE N FL OE N FL DO O FL 1 FL 2 FL 3 FL DO 4 FL DO 5 FL DO 6 FL DO 7 FL RST N FL WE N HEXO 1 HEXO 2 HEXO 3 HEXO 4 HEXO 5 HEXO 6 HEX1 0 HEX1 1 HEX1 2 HEX1 3 HEX1 4 HEX1 5 HEX1 6 HEX2 0 HEX2 1 HEX2 2 HEX2 3 HEX2 4 HEX2 5 HEX2 6 HEX3 0 HEX3 1 HEX3 2 HEX3 3 HEX3 4 HEX3 5 PIN AB15 PIN AA15 PIN Y15 PIN Y14 PIN V17 PIN W17 PIN AD19 PIN AC19 PIN AF20 PIN AE20 PIN AB20 PIN AC20 AF21 PIN AE21 PIN AA18 PIN AA17 PIN AF10 PIN AB12 PIN AC12 PIN AD11 PIN AE11 PIN V14 PIN V13 PIN V20 PIN V21 PIN W21 PIN Y22 P2. declare signals count and cnt which are used in the program Signals are similar to variables but have a delay during assignments whereas variable assignments are instantaneous The lines begin and end architecture counter_behavior delimit the block of code that describes the behavior of the counter The next line process clk asynch clr sensitivity list is the process statement A process statement is the main construct in behavioral modeling that allows the use of sequential statements to describe the behavior of a system over time The inputs clk and asynch clr within the left and right parenthesis are called the sensitivity list The sensitivity list is the set of signals to which the process is sensitive Any change in the value of the signals in the sensitivity list in this case clk and asynch clr will cause immediate execution of the process 32 The next lines begin if asynch_clr 0 then asynch clr is Pushbutton 0 count 00000000 elsif rising edge clk then after so many clocks increment decrement count if cnt CNT MAX then cnt lt others gt 0 up down is Toggle Switch 0 up position count up down count down if up down 2 1 then count lt count 00000001 else count lt count 00000001 end if else cnt lt cnt 1 end if end if end process Q lt count are how the counter actually behaves The counter begins at 00000000 binary After 1
3. Hardware A Chain Description Files cd f 9h 1 0 Pin State Files Ips to other systems such as embedded processors Quartus II Programmer quartus pgm Quartus Il Assembler quartus asm Programmer Object Files pof SRAM Object Files sof Ph MAX PLUS il JTAG Chaln Files jef or FLEX Chain Files fcf ale Quartus Il Convert Programming Files quartus cpf Flies svf In System Configuration Flies Isc Secondary programming flies including Raw Binary rbf Tabular Text Files cup Raw Programming Data Files rpd Hexadecimal Output Files for EPC 16 hex JTAC indirect Programming Files Jic Flash Loader Hexadecimal Files flex POFs for Local Update or Remote Update Figure 21 Program Design Flow 4 2 2 Case Study 1 Part of initial evaluation was to compile and upload a hello world program which was written by Martin Schoeberl This program makes an LED blink at a certain frequency The instructions that come with the program make mention of an EPIC6Q240C8 and EP1C12Q240C8 FPGA device However the FPGA on the Altera DE2 board is an EP2C35F672C6 The instructions give pin assignments that don t exist with our system The pin assignments are listed in the DE2 Development and Education Board User Manual 8 A search also yielded an Excel file called DE2_pin_assignments csv 10 which listed the needed pin assignments s
4. faster and more reliable they proved very popular with designers A single PLA could replace dozens of 7400 family devices In categorizing FPDs PLAs and PALs are called Simple PLDs SPLDs Industry standard SPLDs are the 16R8 and 22V10 PALs produced by AMD Here 16R8 means 16 inputs and a maximum of 8 outputs R means that the output is registered by a D flip flop 22V10 means 22 inputs 10 outputs and V is for a versatile output with some outputs registered and some not Inputs amp Flip flop feedbacks Outputs Figure 8 Structure of a PAL 11 8 As technology advanced CPLD devices with more capability evolved Essentially multiple SPLDs blocks are integrated onto a chip with programmable interconnections linking these blocks First pioneered by Altera CPLDs provide the logic capacity of up to 50 SPLDs CPLDs are more sophisticated than SPLDs even at the SPLD level An example is the AMD Mach family of CPLDs Central Switch Matrix 348916 PAL 32 A HHHOH ms i id 1 12 clk 4 e t Bd hn bu Fee 32 Figure 9 Structure of AMD Mach 4 CPLD 11 Figure 9 shows the layout of the Mach 4 It consists of multiple 34V16 PAL like blocks and the Central Switch Matrix which connects these blocks together When we say PAL like we mean that the PAL blocks are equivalent to the 34V16 PAL but are designed to give the user more flexibility than a regular PAL All connections between
5. which relied on many small scale integration SSI chips such as the 7400 series designs today consist mainly of high density devices The first use of user programmable logic was realized by Programmable Read Only Memory PROM where address lines are the inputs to the logic circuit and data read from those address locations form the logic circuit output This is a form of look up table LUT where we use the input to look up the output by indexing a table Fig 2 n address lines d 1 memory decoder array 2 words by m bits m data lines Figure 2 Internal Organization of a ROM 14 As an example Figure 3 shows a combinational logic implementation two level canonical form using a PROM with the associated Boolean equations for the outputs FO A BC ABC ABC FI A BC A BC ABC F2 ABC ABC ABC F3 ABC ABC ABC A BCO Fi E3 000 0 1 ROM 0001 1 i1 1 0 8 words x 4 bits word 010 01 0 0 0110 0 1 100 1 1 1 10111 0 1100 0 1 ABC 3 1110 1 0 0 address outputs truth table block diagram Figure 3 Combinational logic implementation using a ROM 14 4 Using PROMs are advantageous when design time is short there is no need to minimize output functions most input combinations are needed such as for code converters and there is little sharing of product terms among output functions There are however several disadvantages One
6. 2 pp 42 57 1996 13 J Van der Spiegel VHDL Tutorial University of Pennsylvania Department of Electrical and Systems Engineering August 6 2006 www seas upenn edu ese201 vhdl vhdl primer html 14 R H Katz UC Berkeley Computer Science 150 Components and Design Technique Digital Systems lecture slides Fall 2000 http bnrg cs berkeley edu randy Courses C S 150 F00 36 Appendix 1 Date Thu 18 Sep 2008 09 28 43 0700 From http www google com search q authorization altera com To lt JIVOELML EAGLE FGCU EDU gt Subject Your Altera Development Tools License Dear JOSEPH VOELMLE Thank you for requesting a license file to enable your Altera Quartus II software Quartus II software delivers the highest average performance for FPGA and CPLD designs KKK K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K Quartus II Software 1 in Performance Details at http www altera com alterazone K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K This email includes the following sections Extensive Learning Resources License File Installation Instructions Support Information EXTENSIVE LEARNING RESOURCES The Quartus II software is the easiest to use software for FPGA CPLD and structured ASIC devices Extensive resources are available to help you become productive immediately including 1 Online video demonstr
7. Licensing lt http www altera com literature an an340 pdf gt Quartus II Installation amp Licensing for PCs Manual lt http www altera com literature manual quartus_install pdf gt Support INFORMATION If you have further questions you may file a Service Request at lt https mysupport altera com gt If you are not yet registered have your licensing information available for an expedited sign up You may sign up as a new user to get the same service Confidentiality Notice This message may contain information that is confidential or otherwise protected from 38 disclosure If you are not the intended recipient you are hereby notified that any use disclosure dissemination distribution or copying of this message or any attachments is strictly prohibited If you have received this message in error please advise the sender by reply e mail and delete the message and any attachments Thank you Attachment 1 0015175C3511__0 672602176048142 dat 421Byte Delete Type application octet stream Encoding 7bit Download 39 Appendix 2 hello world vhd The Hello World example for FPGA programming Author Martin Schoeberl martin jopdesign com 2006 08 04 created library ieee use ieee std logic 1164 a11 use ieee numeric std all entity hello world is port Clk in std logic led out std logic end hello world architecture rtl of hello world i
8. is that the size doubles for each additional input Logic functions rarely require more than a few product terms Since a PROM has a full decoder we can t take advantage of don t cares and have to account for all input combinations PROMs are an inefficient architecture for implementing logic circuits since only a fraction of their capacity is used in any one application For these reasons they are rarely used for this purpose 1 2 Basics of PLAs Programmable Logic Arrays PLAs were specifically developed for implementing programmable logic circuits A PLA contains a programmable AND array or plane followed by a programmable OR plane inputs product terms ML TN Figure 4 Programmable Logic Array 14 Don t cares occur when certain input conditions will never occur or the output will not be changed by those input conditions This can be used to simplify functions by reducing the number of minterms 5 In Figure 4 we can see that the general organization of a PLA is similar to that of a PROM Exploiting the regular structure of two level logic introduced in the previous section PLAs arrange the AND and OR gates into a generalized structure whose connections can be programmed to implement a particular function The AND array is used to compute the particular minterm and the OR array ORs these terms together to form the final product of sums output Figure 5 PLA connections before programmin
9. ndyra Sh EDA heks Winer Ponen Deris Onan Figure 19 Quartus II Graphical User Interface 4 The Quartus II software can be installed in evaluation mode meaning that the software could be used for an evaluation period of 30 days This is because running the software in normal mode requires a full license from Altera The main problem with evaluation mode is that it does 22 not allow the user to generate sof files which are the binary files generated from the VHDL compiler What this means is that the user can write and compile VHDL programs to check for syntax errors but is unable to upload those programs to run on the FPGA board Thus a full license is required in the form of a data file which is used by the software to run in normal mode see Appendix 1 The Altera license incorporates the physical address of each computer in the licensing file To request a license the user must supply to Altera an NIC network interface card ID which is a 12 character hexadecimal string imbedded in the network interface card Altera uses it to uniquely identify the PC where the software is installed To get the NIC ID type ipconfig all from a DOS command line on your computer The NIC ID is the physical address without the dashes as shown in the following printout C MN ipconfig all Windows IP Configuration Host Name i 3x4 amp 5 9 s F doe Primary Dns Suffix c r NodeType o ae ee Oe ow xy
10. processes and components all operating concurrently Referring to the appendix the first few lines are comments denoted by 26 The next three lines library ieee use ieee std logic 1164 all use ieee numeric std all declare libraries needed for simple logic functions These libraries permit use of predefined logic values logic operations like AND OR and arithmetic operations like add etc The following statements entity hello world is port Clk in std logic led out std logic end hello_world give the external view of our device Entity names the device hello_world while port declares any input and output signal Here clk is declared as an input and led is declared as an output The next statement architecture rtl of hello world is begins the architectural description of our device in essence how it is supposed to behave Here rtl is the name of our architecture and associates it with the entity hello world The next statements constant CLK FREQ integer 20000000 constant BLINK FREQ integer 1 constant CNT MAX integer CLK FREQ BLINK FREQ 2 1 signal cnt unsigned 24 downto 0 signal blink std logic 27 declare constants and variables used in our program unsigned defines a bit vector of 25 elements unsigned 24 unsigned 23 unsigned 0 The next statement begin process clk begins what is known as the process constr
11. 0 million clock pulses we increment or decrement our counter by one and load the count value into the Q outputs of the counter This is so that the blinking of the LEDs will be visible the least significant bit blinking off and on every 0 2 seconds Using the procedure described for the hello_world program in Section 2 3 the up down counter vhd program should now be compiled and loaded on the Altera board The pin assignments will be as follows asynch clr PIN G26 clk PIN N2 Q 7 PIN AC21 Q 6 PIN AD21 0 5 PIN AD23 9 4 PIN AD22 Q 3 PIN AC22 Q 2 PIN AB2I Q 1 PIN AF23 Q 0 PIN AE23 and up down PIN N25 This should result in LED 0 through LED 7 blinking in sequence from 00000000 through 11111111 33 3 Conclusion The DE2 board features a Cyclone EP2C35 FPGA The user can control all aspects of the board s operation since all important components on the board are connected to the pins of the Cyclone II The DE2 board includes toggle and push button switches LEDs and 7 segment displays for use in simple experiments SRAM SDRAM and Flash memory chips as well as a 16 x 2 character display can be used in more advanced experiments A design suite to instantiate Altera s Nios If embedded processor is included which would allow for experiments that require a processor and provide a vehicle for learning about topics in computer organization The Nios II IDE should be easy to use for anyone familiar w
12. 1 17 GPIO 1 18 6 1 19 1 20 121 GPIO 1 22 GPIO 1 23 GPIO 1 24 GPIO 1 25 GPIO 1 26 GPIO 1 27 128 PIN H19 PIN K18 PIN K19 PIN K21 PIN 23 PIN 24 PIN L21 PIN L20 PIN 125 PIN 126 PIN 23 PIN 24 PIN 25 PIN L19 K25 PIN K26 PIN M22 PIN M23 PIN M19 PIN M20 PIN N20 PIN M21 PIN M24 PIN M25 PIN N24 PIN P24 PIN R25 PIN R24 PIN R20 PIN T22 PIN T23 PIN T24 PIN T25 PIN T18 PIN T21 PIN T20 PIN U26 PIN 25 PIN U23 PIN U24 PIN R19 PIN T19 PIN 020 51 GPIO 1 29 GPIO 1 30 GPIO 1 31 GPIO 1 32 GPIO 1 33 GPIO 1 34 GPIO 1 35 PIN U21 PIN V26 PIN V25 PIN V24 PIN V23 PIN W25 PIN W23 52
13. 3 12 PIN_AD12 PIN 22 22 PIN W19 PIN V18 PIN 18 PIN U17 PIN AA20 PIN Y18 PIN Y12 PIN D13 PIN N2 PIN P26 PIN D26 PIN C24 PIN C25 PIN B25 PIN K4 PIN K3 PIN 11 PIN 12 PIN H1 PIN H2 PIN 14 PIN 13 PIN H4 PIN H3 PIN L4 PIN K2 PIN 4 PIN AFA PIN AC5 PIN AC6 PIN ADA PIN AD5 46 SRAM ADDR 6 SRAM ADDR 7 5 ADDR 8 SRAM ADDR 9 SRAM ADDR 10 SRAM ADDR 11 SRAM ADDR 12 SRAM ADDR 13 SRAM ADDR 14 SRAM ADDR 15 5 ADDR 16 SRAM_ADDR 17 5 SRAM 1 SRAM_DQI2 SRAM 3 5 4 5 5 SRAM 6 5 7 SRAM 8 SRAM 9 SRAM DO 10 SRAM 11 SRAM 12 SRAM 13 SRAM 14 SRAM 15 SRAM WE N SRAM OE N SRAM UB N SRAM LB N SRAM CE N OTG ADDR O OTG ADDR 1 OTG CS N OTG RD N OTG WR N OTG RST N OTG DATA O OTG DATA 1 OTG 2 OTG DATA 3 PIN 5 AF5 PIN AD6 PIN AD7 PIN V10 PIN V9 PIN AC7 PIN W8 PIN W10 PIN Y10 PIN 8 PIN AC8 PIN AD8 PIN PIN AF6 PIN AA9 PIN AA10 PIN AB10 PIN AA11 PIN Y11 PIN AE7 PIN AF7 PIN AE8 PIN AF8 PIN W11 PIN W12 PIN AC9 PIN AC10 PIN AE10 PIN AD10 PIN AF9 PIN AE9 PIN AC11 PIN K7 PIN F2 PIN F1 PIN G2 PIN G1 PIN G5 PIN F4 PIN D2 PIN D1 PIN F7 47 OTG DATA 4 PIN J5 OTG DATA 5 PIN 18 OTG DATA 6 PIN J7 OTG 7 PIN H6 OTG DATA 8 PIN E2 OT
14. 5 PLL CLK DPCLK and Clock Control Block Locations 7 Notes to Figure 15 1 There are four control blocks on each side 2 Only one of the corner CDPCLK pins in each corner can feed the control block at a time The other CDPCLK pins can be used as general purpose I O 17 The Cyclone II embedded memory consists of columns of M4K memory blocks The M4K memory blocks include input registers that synchronize writes and output registers to pipeline designs and improve system performance The M4K memory blocks support the following features e 4 608 RAM bits e 250 MHz performance e True dual port memory e Simple dual port memory e Single port memory e Byte enable e Parity bits e Shift register e FIFO buffer e ROM e Various clock modes e Address clock enable Figure 16 shows the M4K block to logic array interface C4 Interconnects R4 Interconnects interconnect interconnect mE EET to adjacent LAB Direct link interconnect Byte enable Control Signals from adjacent LAB E address datain M4K RAM Block Local LAB Row Clocks Interconnect Region Figure 16 M4K RAM Block LAB Row Interface 7 Direct link interconnect from adjacent LAB 18 2 Development with the Altera DE2 Evaluation Board 21 H W and S W Configuration This section presents background information regarding the use of the Altera DE2 evaluation board and Quartus II software The idea is to provide flexibility in ru
15. C5 PIN B5 PIN C6 PIN A4 PIN A5 PIN B4 PIN D17 PIN C17 PIN B18 PIN A18 PIN B17 PIN A17 PIN B16 PIN B15 49 8 ENET_DATA 9 ENET_DATA 10 ENET DATA 11 ENET DATA 12 ENET DATA 13 ENET DATA 14 DATA 15 ENET CLK ENET CMD ENET CS N INT ENET RD N ENET WR N RST N IRDA TXD RXD SD DAT SD DAT3 SD CMD SD CLK 6 0 GPIO 01 GPIO O 2 GPIO 0 3 GPIO O 4 GPIO O 5 GPIO O 6 7 GPIO O 8 GPIO O 9 GPIO O 10 GPIO O 11 GPIO 0 12 GPIO 0 13 GPIO O 14 GPIO O 15 GPIO O 16 GPIO 0 17 GPIO O 18 GPIO O 19 GPIO O 20 GPIO 21 PIN B20 PIN A20 PIN C19 PIN D19 PIN B19 PIN A19 PIN E18 PIN D18 PIN B24 PIN A21 PIN A23 PIN B21 PIN A22 PIN B22 B23 PIN AE24 PIN AE25 PIN AD24 PIN AC23 PIN Y21 PIN AD25 PIN D25 PIN 122 PIN E26 PIN E25 PIN F24 PIN F23 PIN 121 120 PIN F25 PIN F26 PIN N18 PIN P18 PIN 623 PIN G24 PIN 22 PIN G25 PIN H23 PIN H24 PIN 123 PIN 124 PIN H25 PIN H26 50 GPIO_0 22 GPIO_0 23 O 24 GPIO 0 25 GPIO_0 26 GPIO 0 27 GPIO_0 28 GPIO_0 29 GPIO 0 30 GPIO 0 31 GPIO 0 32 GPIO 0 33 GPIO_0 34 GPIO 0 35 GPIO_1 0 GPIO_1 1 GPIO_1 2 GPIO 1 3 GPIO 114 1 5 GPIO_1 6 GPIO_1 7 GPIO 1 8 GPIO 1 9 GPIO 1 10 GPIO 1 11 GPIO 1 12 GPIO 1 13 GPIO 1 14 GPIO 1 15 GPIO 1 16 6
16. EPS COMPILE AND UPLOAD HELLO WORLD TO THE BOARD 2 2 22 29 2 4 CASE STUDY 30 3 CONCLUSION CO 34 36 APPENDIX 1 37 APPENDIX 2 dk Dodo Po on dn oda EDD ce 40 APPENDIX 3 oiii o cri possono cune cose adr rao esu e aon UE ada ri Eo rEde nr E adr ruaa 41 APPENDIX P 42 1 Introduction to FPGAs We begin by providing some background on programmable logic and the reasons for the popularity of Field Programmable Devices FPD There are many different types of devices and architectures the designer will encounter and one should be familiar with the different terminology used in the field There are a wide variety of FPDs that the designer can choose In addition to FPDs Programmable Logic Devices PLDs is another name that the designer will encounter for FPDs FPD is a general term while PLDs historically refer to relatively simple devices A Programmable Logic Array PLA is relatively small FPD consisting of two levels of logic an AND plane followed by an OR plane with both levels being programmable A Programmable Array Logic PAL is also a relatively s
17. G DATA 9 PIN OTG DATA 10 PIN K6 OTG DATA 11 PIN K5 OTG DATA 12 PIN G4 OTG DATA 13 PIN G3 OTG DATA 14 PIN J6 OTG DATA 15 PIN K8 OTG INTO PIN B3 OTG INT1 C3 OTG DACKO N PIN C2 OTG DACK1 N PIN B2 OTG DREQO PIN F6 OTG DREO1 PIN E5 OTG FSPEED PIN F3 OTG LSPEED PIN G6 TDI PIN B14 TCS PIN A14 TCK PIN D14 TDO PIN F14 TD RESET PIN C4 VGA PIN C8 VGA_R 1 10 VGA_R 2 PIN 610 VGA R 3 PIN 59 VGA_R 4 PIN C9 VGA 5 PIN A8 VGA R 6 PIN H11 VGA R 7 PIN H12 VGA R 8 PIN F11 VGA R 9 PIN E10 VGA_G 0 PIN B9 VGA G 1 PIN A9 VGA G 2 PIN C10 VGA G 3 PIN D10 VGA_G 4 PIN B10 VGA G 5 PIN A10 VGA G 6 PIN 611 VGA 7 PIN D11 48 VGA_G 8 VGA G 9 VGA_B 0 VGA_B 1 VGA_B 2 VGA_B 3 VGA_B 4 VGA_B 5 VGA_B 6 VGA_B 7 VGA_B 8 VGA_B 9 VGA_CLK VGA_BLANK VGA_HS VGA_VS VGA_SYNC I2C SCLK I2C SDAT TD DATA O TD 1 TD 2 TD DATA 3 TD_DATA 4 TD DATA S5 TD DATA 6 TD DATA 7 TD HS TD VS AUD ADCLRCK AUD ADCDAT AUD DACLRCK AUD DACDAT AUD XCK AUD BCLK ENET DATA O ENET DATA 1 ENET DATA 2 ENET DATA 3 ENET_DATA 4 ENET DATA 5 DATA 6 DATA 7 PIN E12 PIN D12 PIN 113 PIN 114 PIN F12 PIN 612 PIN 110 PIN 111 PIN C11 PIN B11 PIN C12 PIN B12 PIN B8 PIN D6 PIN A7 PIN D8 PIN B7 PIN A6 PIN B6 19 PIN E8 PIN H8 PIN H10 PIN G9 PIN F9 PIN D7 PIN C7 PIN D5 PIN PIN
18. GA or field programmable gate array is a semiconductor device containing basic programmable logic components called logic blocks and wires between those blocks Unlike gate arrays whose wires must be manufactured on to the chip the wires on FPGAs are programmable as well FPGA logic blocks and wires can be programmed in the field hence the name very rapidly which makes it the premier technology for prototyping Logic blocks can be programmed to perform the function of basic logic gates such as AND and XOR or more complex combinational functions such as decoders or mathematical functions In most FPGAs the logic blocks also include memory elements which may be simple flip flops or more complete blocks of memory FPGAs combine the density advantages of gate arrays with the programmability of PALs PLAs The advantages of FPGAs are low start up costs a shorter time to market lower non recurring engineering costs instant manufacturing turnaround low financial risk and ease of design changes due to ability to re program in the field to fix bugs Disadvantages of FPGAs are that they are usually slower than ASICs draw more power and cannot handle as complex a design With a myriad of different FPGAs on the market each with a unique architecture we will focus on Altera Cyclone II which is used in this project The Cyclone II family offers devices with a variety of features The particular device on the DE2 board is the EP2C35 The Cyclone II
19. IN AA24 PIN AA23 PIN AB24 PIN AB23 PIN V22 AC25 PIN AC26 PIN AB26 AB25 PIN Y24 PIN Y23 PIN AA25 PIN AA26 PIN Y26 PIN Y25 PIN U22 44 HEX3 6 HEXA 0 HEXA 1 HEXA 2 HEXA 3 HEX4 4 HEX4 5 HEXA 6 HEX5 0 HEX5 1 HEX5 2 HEX5 3 HEX5 4 HEX5 5 HEX5 6 HEX6 0 HEX6 1 HEX6 2 HEX6 3 HEX6 4 HEX6 5 HEX6 6 HEX7 0 HEX7 1 HEX7 2 HEX7 3 HEX7 4 HEX7 5 HEX7 6 1 KEY 2 KEY 3 LEDR O LEDR 1 LEDR 2 LEDR 3 LEDR 4 LEDR 5 LEDR 6 LEDR 7 LEDR 8 LEDR 9 PIN W24 PIN U9 PIN U1 PIN U2 PIN 4 PIN R7 PIN R6 PIN T3 PIN T2 PIN P6 PIN P7 PIN T9 PIN R5 PIN R4 PIN R3 PIN R2 PIN P4 PIN P3 PIN M2 PIN M3 PIN M5 PIN M4 PIN L3 PIN L2 PIN L9 PIN L6 PIN L7 P9 PIN N9 PIN G26 PIN N23 PIN P23 PIN W26 AE23 PIN AF23 PIN AB21 PIN AC22 PIN AD22 PIN AD23 PIN AD21 PIN AC21 PIN AA14 PIN Y13 45 LEDR 10 LEDR 11 LEDR 12 LEDR 13 LEDR 14 LEDR 15 LEDR 16 LEDR 17 0 LEDG 1 LEDG 2 LEDG 3 LEDG 4 LEDG 5 LEDG 6 LEDG 7 LEDG 8 CLOCK 27 CLOCK 50 EXT CLOCK PS2 CLK PS2 DAT UART RXD UART TXD LCD RW LCD EN LCD RS LCD DATA O LCD DATA 1 LCD DATA 2 LCD DATA 3 LCD DATA 4 LCD DATA 5 LCD DATA 6 LCD DATA 7 LCD ON LCD BLON SRAM ADDR O SRAM ADDR 1 SRAM ADDR SRAM ADDR 3 SRAM_ADDR 4 SRAM_ADDR 5 PIN_AA13 PIN_AC14 PIN_AD15 15 PIN_AF13 PIN_AE1
20. Investigation of Altera DE2 Development and Education Board COP 4902 Independent Study Joseph Voelmle 1 20 2009 1 INTRODUCTION TO FPGAS RR 2 1 1 BASIC THEORY cccccscsescsdesccecscstsesescessoescostsevescassoussessseuesdedseuseestsedesdadevesdesdeedessutiscdadedsaddndsedacddieensaundeedacdiietias 2 1 2 BASICS OF PLAS via cccdvsccccaceveccvedevcvecececcuceccescvescdesevessdesdvcssdeseucndceddsesedeseuenceeddusus eusududucksudusveasuluductsudusvetsuduaiss 5 1 3 OTHER FPDS e M RUPEE 8 1 4 y Milecyodiicf Wm ER 10 2 DEVELOPMENT WITH THE ALTERA DE2 EVALUATION 19 2 1 H W AND S W 19 2 1 1 HARDWARE assa assa nass assa sanas asas esas nsns nna n nnne nnn 19 2 1 2 SOFTWARE DESCRIPTION eese eene eene ssssssssss assa nass erd 5 rvis end asas asas asas asas ases asas ases sss s sense nennen 22 2 1 3 PROGRAM DESIGN FLOW eeeeeeeeeeeeeee 24 2 2 CASE 25 2 3 ST
21. PAL blocks are routed through the Central Switch Matrix which allows the Mach 4 to be viewed not only as a collection of PALs but also as a single device 16 PAL blocks on the chip correspond to approximately 5000 logic gates This is still not sufficient for modern applications that require many thousands of gates on a chip FPGAs seem to solve that problem 1 4 Basics of FPGAs To examine FPGAs we first need to discuss gate arrays Gate arrays are an approach used in the design and manufacture of Application Specific Integrated Circuits ASICs In a gate array transistors or basic logic gates such as NAND or NOR gates or other active devices are placed at regular predefined positions on an integrated circuit Fig 10 A circuit with a specified function is realized when a layer or layers of interconnects between the different logic elements are added to the chip late in the manufacturing process Extending the PLA PAL concept gate arrays allow a general form of programmable wires on a chip This removes the restriction of having gates arranged in a two level AND OR form This is a more expensive and time consuming to manufacture but can achieve gates densities in the millions and speeds much greater than PLAs PALs IO Blocks Interconnect Logic Block Figure 10 General Structure of a Gate Array 14 10 Today most prototypes and many production designs use Field Programmable Devices FPDs and FPGAs in particular An FP
22. any clocks increment decrement count if cnt CNT MAX then cnt lt others gt 0 up down is Toggle Switch 0 up position count up down count down if up down 1 then count lt count 00000001 else count lt count 00000001 end if else cnt lt cnt 1 end if end if end process Q lt count end architecture counter_behavior 4 Appendix 4 Quartus II Version 5 1 Internal Build 160 09 19 2005 TO Full Version File D de2_pins de2_pins csv Generated on Wed Sep 28 09 40 34 2005 Note The column header names should not be changed if you wish to import this csv file into the Quartus II software To Location SW 0 PIN_N25 SW 1 PIN N26 SW 2 PIN P25 SW 3 PIN AE14 SW 4 PIN AF14 SW 5 PIN AD13 SW 6 PIN AC13 SW 7 PIN C13 SW 8 PIN B13 SW 9 PIN A13 SW 10 PIN N1 SW 11 PIN P1 SW 12 PIN P2 SW 13 PIN T7 SW 14 PIN U3 SW 15 PIN U4 SW 16 PIN V1 SW 17 PIN V2 DRAM ADDR O PIN T6 DRAM ADDR 1 PIN V4 DRAM ADDR 2 PIN V3 DRAM ADDR 3 PIN W2 DRAM_ADDR 4 PIN W1 DRAM ADDR 5 PIN U6 DRAM ADDR 6 PIN U7 DRAM ADDR 7 PIN U5 DRAM ADDR 8 PIN W4 DRAM ADDR 9 PIN W3 DRAM ADDR 10 PIN Y1 DRAM ADDR 11 PIN V5 DRAM 0 2 42 DRAM_BA_1 DRAM_CAS_N DRAM_CKE DRAM_CLK DRAM_CS_N DRAM DRAM 1 DRAM 2 DRAM 3 DRAM_DQI4 DRAM_DQI5 DRAM DO 6 DRAM 7 DRAM 8 9 10 11
23. ations at http www altera com quartusdemos 2 Free online training classes at http www altera com etraining 3 Introduction to Quartus Manual Quartus Handbook and Quartus II Scripting Reference Manual at http www altera com literature lit qts jsp 4 Tutorials included in the Quartus II software under the Help menu License File Installation Intructions Your license FEATURE quartus_lite alterad 2009 02 15 feb 2009 uncounted 9CECI28DF1C9 HOSTID 0015175c3511 SIGN 01F5 00E9 D850 DBOC 37 A1C2 AA87 7813 4AF7 FA73 7205 724C CC22 D2EC 4BB5 EE96 0A70 2D1D F8EA 80C3 71C0 4COE 35F9 1F2D 91A6 3503 CAF6 31A6 6323 C9FB 232B INCREMENT alteramtiwe mgcld 2009 02 15 feb 2009 uncounted 7DB92132FD6F375109BB VENDOR_STRING 00F33221 HOSTID 0015175c3511 V SUPERSEDE ISSUER Alterav3 5 Your license file s is also attached to this e mail as a text file PC Instructions 1 Save your license file text to your computer s hard drive Altera recommends saving the file into your c quartus directory with a dat file name extension 2 In the Quartus II software choose License Setup Tools Menu 3 In the License File box type or browse to the full path and file name of the file you saved in step 1 4 If you have problems use AN 340 to troubleshoot your licensing setup ADDITIONAL LICENSING AND INSTALLATION INFORMATION The following documents offer detailed licensing and installation instructions AN 340 Altera Software
24. b Select Chain Description File Click OK Click Add File A Select Programming File 29 window will pop up Then choose the hello_world sof to be added Next remember to check the Program Configure box From the file menu save hello_world cdf file through Save button 13 Next select Processing Start Compilation 14 We are finally able to run the hello world program on our board From Tools Programmer hit Start Our little green LED should blink 2 4 Case Study 2 The next step in this project was to write a VHDL program to implement a simple 8 bit up down counter Figure 23 shows the schematic up down 8 bit Up Down Counter asynch clr clk Q 7 Q 6 Q 1 0 Figure 23 Up Down Counter The counter has three inputs and eight outputs The up down input tells the counter in which direction to count high to count up and low to count down The asynch_clr input resets the resets the counter to zero The counter will count up or down once with each clock at the c1k input The outputs Q 0 through Q 7 are the 8 bit output of the counter so that on each clk pulse the counter will proceed sequentially from or down from 00000000 00000001 00000010 00000011 00000100 up to 11111111 with each clock pulse When it reaches 11111111 it goes to 00000000 on the next clock pulse and start the sequence all over again Appendix 3 contains the listing for the down counter vhd program To implement t
25. contains a two dimensional architecture to implement custom logic Fig 11 Column and row interconnects of varying speeds connect logic array blocks LABs embedded memory blocks and embedded multipliers The logic array consists of LABs with 16 logic elements LEs in each LAB where an LE is the smallest unit of logic providing user logic functions LABs are grouped into rows and columns throughout the device The Cyclone II EP2C35 device contains 11 33 216 LEs The Cyclone II provides a global clock network consisting of up to 16 global clock lines that drive throughout the entire device and four phase locked loops PLLs The global clock network can provide clocks for all resources within the device such as input output elements IOEs LEs embedded multipliers and memory blocks The EP2C35 offers 483 840 kbits of embedded memory The EP2C35 has 105 M4K memory blocks are true dual port memory blocks with 4K bits of memory plus parity 4 608 bits These blocks provide dedicated memory up to 36 bits wide at up to 260 MHz and are arranged in columns across the device in between certain LABs The EP2C35 has 35 embedded multiplier blocks each of which can implement up to either two 9 x 9 bit multipliers or one 18 x 18 bit multiplier with up to 250 MHz performance The embedded multipliers are arranged in columns across the device Each Cyclone II device I O pin is fed by an IOE located at the ends of LAB rows and columns around the periphery
26. device Field programmable gate array Gate array 7400 series 3 DE2 Development and Education Board Altera Corp San Jose CA 2009 www altera com education univ materials boards unv de2 board html 4 Introduction to the Quartus II Software Version 8 0 Altera Corp San Jose CA www altera com literature manual intro to quartus2 pdf 5 Altera Software Licensing AN 340 2 1 Altera Corp San Jose CA November 2008 www altera com literature an an340 pdf 6 USB Blaster Driver for Windows XP Altera Corp San Jose CA 2009 www altera com support software drivers usb blaster dri usb blaster xp html 7 Cyclone II Device Handbook Volume 1 CH5V 13 3 Altera Corp San Jose CA February 2008 www altera com literature hb cyc2 cyc2 cii5vl pdf 8 DE2 Development and Education Board User Manual Version 1 4 Altera Corp San Jose CA 2006 ftp ftp altera com up pub Webdocs DE2 UserManual pdf 9 M Schoeberl The FPGA Hello World Example August 4 2006 www jopdesign com cyclone hello_world pdf 10 DE2 Pin Assignments Cornell University September 28 2005 http courses cit cornell edu ece576 DE2 DE2_pin_assignments csv 11 S Brown and J Rose Architecture of FPGAs and CPLDs A Tutorial University of Toronto Department of Electrical and Computer Engineering 1996 http www eecg toronto edu jayar pubs brown survey pdf 12 S Brown and J Rose FPGA and CPLD Architectures A Tutorial IEEE Design amp Test of Computers Vol 13 No
27. ee Appendix 4 Using this information it was decided to arbitrarily select LEDGO green LED 0 to blink see Fig 22 which corresponded to pin assignment PIN_AE22 and pin PIN_D13 for the clock Using these pin assignments the hello_world program was compiled without errors 25 oS F I e a MAMATA Figure 22 Altera DE2 Developments and Education Board 3 Appendix 2 contains the listing for the hello world vhd program This program is written in VHDL which stands for VHSIC Hardware Descriptive Language VHSIC stands for Very High Speed Integrated Circuits a United States Department of Defense program A digital system can be represented at different levels of abstraction behavioral and structural The behavioral level describes what a system does in terms of input and output signals The structural level is a lower level of abstraction which describes a system as a collection of gates and components that are interconnected and is analogous to a schematic of interconnected logic gates The hello world program represents a behavioral description AII VHDL systems consist of design entities which in turn consist of other entities Each entity is modeled by an entity declaration and an architecture body The entity declaration is the interface to the outside world that defines the input and output signals while the architecture body contains the description of the entity and is composed of interconnected entities
28. ementing adders counters accumulators and comparators Each Logic Array Block consists of the following e 16LEs e LAB control signals LE carry chains e Register chains e Local interconnect 14 The local interconnect transfers signals between LEs in the same LAB Fig 13 Register chain connections Fig 12 transfer the output of one LE s register to the adjacent LEs register within an LAB pr Row Interconnect Column Interconnect a link Direct link interconnec interconnect 1 from adjacent from adjacent block block 7 EE Direct link Direct link interconnect interconnect to adjacent iz to adjacent block block LAB Local interconnect Figure 13 Cyclone II LAB Structure 7 The LAB local interconnect can drive LEs within the same LAB The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB Neighboring LABs PLLs MAK memory blocks and embedded multipliers from the left and right can also drive an LAB s local interconnect through the direct link connection The direct link connection feature minimizes the use of row and column interconnects providing higher performance and flexibility Each LE can drive 48 LEs through fast local and direct link interconnects Fig 14 15 Direct link interconnect from Direct link interconnect from left LAB M4K memory right LAB M4K memor
29. g 14 In order to program the PLA selected connections between wires in a circuit like the one in Fig 5 are open or closed by a programmable switch Suppose we wish to implement the following logic equations FO A BC Fl AC AB F2 B C AB F3 B C A Exploiting the fact that some of the minterms are used more than once we could program a PLA to implement these equations as follows as illustrated in Fig 6 A B C Figure 6 Example of a programmed PLA 14 A short hand notation for describing the topology of array logic shows connection between wires as x s and multiple wires entering gates as single wires as illustrated in Fig 7 AB A B CD C D Figure 7 Short hand notation of a programmed PLA 14 1 3 Other FPDs When first introduced in the early 1970s PLA were expensive and slow due to the programmable AND arrays and OR arrays The programmable logic planes were difficult to manufacture and suffered from significant propagation delays In 1978 Monolithic Memories introduced PALs Like PLAs PALs have a programmable AND array but differ from PLAs in having a fixed OR array Fig 8 To overcome the lack of flexibility in not being able to program the OR array PALs come in a variety of standard dual in line packages DIP with different combinations of inputs and outputs PALs were very important when they were introduced because they overcame many of the problems of the earlier PLAs Being less expensive
30. hain Clock amp Register Output jClock Enable Feedback Select labclkt LL labelk2 j labclkenat labelkena2 pe 4 LAB Carry Out Figure 12 Cyclone II LE 7 13 Each LE s programmable register can be configured for D T JK or SR operation and has data clock clock enable and clear inputs The register s clock and clear control signals can be driven by any signal that use the global clock network general purpose I O pins or by any internal logic The clock enable can be driven by either general purpose I O pins or internal logic For combinational functions the LUT output bypasses the register and drives directly to the LE outputs Each LE has three outputs that drive the local row and column routing resources The LUT or the programmable register output can drive these three outputs independently Two LE outputs drive column or row and direct link routing connections and one drives local interconnect resources allowing the LUT to drive one output while the register drives another output This feature known as register packing allows the device to use the register and the LUT for unrelated functions thereby improving utilization Another special mode allows the register output to feed back into the LUT of the same LE The Cyclone II LE operates in either normal mode or arithmetic mode Normal mode is used for general logic applications and combinational functions while arithmetic mode is for impl
31. his 30 program it was decided to use Q 0 through Q 7 to light LEDR 0 through LEDR 7 See Fig 23 The up down input was connected to toggle switch SW 0 so that SW 0 in the up position would cause the counter to count up and the down position would cause it to count down The asynch clr was connected to push button switch KEY 0 See Fig 23 The 50 MHz clock was used as the input to the counter Figure 24 Case Study 2 3 Referring to Appendix 3 the first few lines are comments followed by the three lines declaring the libraries The next few lines entity up down counter is port clk up down asynch clr in std logic Q out std logic vector 7 downto 0 end up down counter declare our entity as up down counter with the inputs as clk up down and asynch_clr The outputs are Q 7 through Q 0 The next line architecture counter behavior of up down counter is 3l begins the architectural body that specifies how the up_down counter operates and how it is implemented The next few lines constant CLK_FREQ integer 50000000 use PIN_N2 for 50MHz clock constant BLINK_FREQ integer 5 constant CNT_MAX integer CLK_FREQ BLINK_FREQ declare constant values used in the program is used to delay the blinking of the LEDs so that they will be visible to the user The next lines Signal count std_logic_vector 7 downto 0 Signal cnt unsigned 24 downto 0
32. ith the Eclipse IDE since it is based on the Eclipse IDE framework The DE2 s I O interfaces include standards such as RS 232 and PS 2 There are standard connectors for microphone line in line out 24 bit audio CODEC video in TV Decoder and VGA 10 bit DAC These can be used in experiments involving sound or video signals to create CD quality audio applications and professional looking video The DE2 provides USB 2 0 connectivity 10 100 Ethernet an infrared IrDA port and an SD memory card connector for larger design projects For projects requiring more than one board other user defined boards can be connected to the DE2 board by means of two expansion headers In this report we have only scratched the surface of the capabilities of the Altera DE2 Development and Education Board The purpose of the Altera DE2 Development and Education board is to provide a vehicle for learning about digital logic computer organization and FPGAs It uses state of the art technology in both hardware and CAD tools to give users a wide range of topics to explore The board offers features that make it suitable for use for a variety of design projects for university courses as well as for the development of sophisticated digital systems 34 35 References 1 R H Katz and G Borriello Contemporary Logic Design 2 Edition Prentice Hall pp 160 161 2 Wikipedia Complex programmable logic device Programmable Array Logic Programmable logic
33. lays cycled through the numbers 0 to F The LCD display showed Welcome to the Altera DE2 Board Table 1 DE2 Board Information 3 FPGA e Cyclone II EP2C35F672C6 with EPCS16 16 Mbit serial configuration device I O Devices Built in USB Blaster cable for FPGA configuration 10 100 Ethernet RS232 Video Out VGA 10 bit DAC Video In NTSC PAL Multi format USB 2 0 type A and type B PS 2 mouse or keyboard port Line In Out Microphone In 24 bit Audio CODEC Expansion headers 76 signal pins Infrared port Memory e 8 MBytes SDRAM 512K SRAM 4 MBytes Flash e SD memory card slot Displays e 16x 2 LCD display Eight 7 segment displays Switches and LEDs 18 toggle switches 18 red LEDs 9 green LEDs Four debounced pushbutton switches Clocks 50 MHz crystal for FPGA clock input 27 MHz crystal for video applications e External SMA clock input 21 2 1 2 Software Description The Altera software consists of Quartus II Design Suite MegaCore IP Library Nios II Embedded Design Suite ModelSim Altera 6 1g Web Edition Once installation is complete the Quartus II software graphical user interface is used to perform all stages of the design flow Figure 19 shows the Quartus II GUI as it appears when you first start the software By Cyckne V EPIG 7206 m ouem ofa INTERA mm QUARTUS II rsion amp e ris Pie hut p Arenie Uen erde proc ors reng ids Se Oare Tinin
34. le switches 18 red user LEDs 9 green user LEDs e 50 MHz oscillator and 27 MHz oscillator for clock sources 24 bit CD quality audio CODEC with line in line out and microphone in jacks VGA DAC 10 bit high speed triple DACs with VGA out connector TV Decoder NTSC PAL and TV in connector 10 100 Ethernet Controller with a connector USB Host Slave Controller with USB type A and type B connectors RS 232 transceiver and 9 pin connector PS 2 mouse keyboard connector IrDA transceiver Two 40 pin Expansion Headers with diode protection Figure 18 gives the block diagram of the DE2 board and Table 1 gives the DE2 Board information In order to provide maximum flexibility all connections are made through the Cyclone II FPGA device This allows the user to configure the FPGA to implement any system design 50 Mhz 27 Mhz Extin USB 2 0 Host Device 16 bit Audio CODEC 10 100 Ethernet P hy MAC VGA 10 bit Video DAC y on User Green LEDS 9 r ransceiver ser reen s FPGA rese cene 1 2035 SORAM 6 Mbytes SRAM 512 Kbytes PS2 amp RS 232 Ports rr tate USB Blaster Device Figure 18 DE2 Block Diagram 8 20 Before installing software a power up of board was performed by installing the 9V AC adapter in the 9V DC Power Supply Connector see Fig 17 At this point the following was observed as a factory setup All user LEDs were flashing All 7 segment disp
35. mall FPD with a programmable AND plane followed by a fixed OR plane PAL is trademarked by Advanced Micro Devices Simple PLD SPLD is usually a PLA or a PAL A Complex PLD CPLD consists of multiple SPLD like blocks on a chip A Field Programmable Gate Array FPGA is a FPD consisting of a very general structure allowing a very high density 1 1 Basic Theory Combinational digital circuits are based on Boolean algebra A common form of Boolean equations is known as canonical two level product of sums Here a function can be expressed by ANDing terms together first level and ORing these together second level to form an output The advantage of this is that these functions can be readily realized by using AND gates followed by OR gates For example a function F AB C A B BC could be implemented by ABG Figure 1 Circuit implementing formula F AB C A B BC 14 The individual products terms AB C A B and BC are known as minterms For simple designs this technology is sufficient but it was found that more complex designs required other techniques Early digital circuits were designed using discrete logic such as 7400 series of transistor transistor logic TTL integrated circuits This series includes not only devices containing logic gates such as the 7400 which contains four NAND gates but also more complex devices such as flip flops counters decoders and multiplexers Unlike older technologies
36. nning the board both at home and at school 2 1 4 Hardware Description Figure 17 depicts the layout of the board and indicates the location of the connectors and key components USB usa 58 Ethamet Blaster Device Hos Mic Line Line Video VGAVideo 10 100M Pot Por Pot in in Ou In Port Pot RS 232 Pon 9V DC Power ws 141 1 t 27 MHz Oscillator uc i 24 bit Audio Codec n Power ON OFF Switch 1 gt 5512 Keyboard Mouse Port VGA 1 bit DAC Ethernet 10 100M Controller USB Host Slave Controller TV Decoder NTSC PAL Expansion Header 2 JP2 Altera USB Blaster Controller Chipset Expansion Header 1 JP1 Altera EPCS16 Configuration Device Maea LLII Altara Cyclone Il FPGA RUN PROG Switch for JTAG AS Modes 162 LUD Module 6D Card 3i 7 Segment Displays T B3 mere HERA mee 8 Green LEDs 18 Rad LEDs ee 1 KDA Traneceiver BE SMA Extemal Clock 18 Toggle Switches 4 Debounced Pushbutton Switches 50 MHz Occl ator BMB SDRAM 12 SRAM 4 48 Flach Memory Figure 17 The DE2 Board 8 The following hardware is provided on the DE2 board Altera Cyclone II 2C35 FPGA device Altera Serial Configuration device EPCS16 19 USB Blaster on board for programming and user API control both JTAG and Active Serial AS programming modes are supported e 512 Kbyte SRAM 8 Mbyte SDRAM 4 Mbyte Flash memory SD Card socket 4 pushbutton switches 18 togg
37. of the device I O pins support various single ended and differential I O standards and each IOE contains a bidirectional I O buffer and three registers for registering input output and output enable signals The EP2C35 offers up to 475 user I O pins E o e Embedded Multipliers Logic Logic Logic Logic Array Array Array Array ao M4K Blocks M4K Blocks Figure 11 Cyclone II Architecture 7 12 The LE the smallest unit of logic in the Cyclone II architecture provides advanced features with efficient logic utilization Fig 12 Each LE features e A four input look up table LUT which is a function generator that can implement any function of four variables e A programmable register e A carry chain connection e A register chain connection e The ability to drive all types of interconnects local row column register chain and direct link interconnects e Support for register packing e Support for register feedback Register Chain Routing From Previous LE LAB Wide Register Bypass LAB Carry In ore LAB Wide Packed Synchronous Register Select Clear data1 f gt Row Column data2 Look Up Ca Synchronous D B And Direct Link data3 Tabe Chai Load and E Routing LUT Clear Logic data4 CLAN Row Column And Direct Link Routing labciri labelr2 J Asynchronous i Chip Wide Local Routing Reset 3d DEV CLRn Register C
38. pop up saying Directory C altera 70 quartus hello_world does not exist Do you want to create it Select Yes The hello world vhd file listed in Appendix 2 should be placed in this directory 5 The Wizard will next ask you to select design files to include in the project Leave blank and just press next 6 We are now at Family amp Device Settings For Family select Cyclone II For Device select EP2C35F672C6 Press next 7 For EDA tools settings leave fields blank and press next 8 At Summary press finish 9 Next select Processing Start Compilation This should produce the hello world sof file 10 Next we have to select the pins we need Select Assignments Pins This will bring up the Pin Planner For 1ed under Location select PIN AE22 and for clk select PIN D13 11 We can now program our device with the hello world program The board needs to be powered up and connected to the computer via the USB cable A driver needs to be installed for the USB Blaster Refer to Altera web site for directions Select Tools Programmer from the menu If EP2C35F672 is not shown under device select Add Device Under Device Family check Cyclone II Under Device Name check EP2C35F672 Hit OK Check the box under Program Configure Select Hardware Setup Under Available Hardware Items Double click USB Blaster and Click Close 12 Create a cdf file from Quartus II File Menu Choose New from File menu Click the Other Files ta
39. s constant CLK FREQ integer 20000000 constant BLINK FREQ integer 1 constant CNT MAX integer CLK FREQ BLINK FR signal cnt unsigned 24 downto 0 signal blink std logic begin process clk begin if rising_edge clk then if cnt CNT_MAX then cnt lt others gt 0 blink lt not blink else ent lt cnt 1 end if end if end process led lt blink end rtl 40 2 1 Appendix 3 up down counter vhd COP 4908 Independent Studies Joseph Voelml library ieee use ieee std logic 1164 all use ieee std logic arith all use ieee std logic unsigned all entity up down counter is port clk up down asynch clr in std logic Q out std logic vector 7 downto 0 end up down counter architecture counter behavior of up down counter is the following lines are used as a delay to the counter so that the output of the counter could be visible to the user constant CLK FREQ integer 50000000 use PIN N2 for 50MHz clock constant BLINK FREQ integer 5 constant CNT MAX integer CLK FREQ BLINK FREQ signal count std logic vector 7 downto 0 signal cnt unsigned 24 downto 0 begin count is an internal signal to this process process clk asynch clr sensitivity list begin if asynch_clr 0 then asynch clr is Pushbutton 0 count 00000000 elsif rising edge clk then after so m
40. uct A process statement is the main construct in behavioral modeling that allows you describe the behavior of a system In the statement process clk clk describes the signals to which the process is sensitive All signals within the are known as the sensitivity list A block of code is delimited by the begin and end statements The next statements begin if rising_edge clk then if cnt CNT_MAX then cnt lt others gt 0 blink lt not blink else cnt lt cnt 1 end if end if end process are the statements that cause the LED to blink Again the code block is delimited by the begin and end process statements The next statements checks for the rising edge of the clock If we ve counted the maximum number of clock pulses then we set cnt to zero and toggle the variable blink In the statement cnt lt others gt 0 others is a VHDL key word and sets cnt to 0 In VHDL lt is the assignment operator and assigns the value of the expression on the right to the signal on the left The final statement led lt blink assigns the value of blink to led which causes the LED to turn on or off 28 2 3 Steps to compile and upload hello world to the board Start Quartus II and create a new project with 1 File New Project Wizard 2 Enter in for the working directory C altera 70 quartus hello_world 3 Under What is the name of this project type hello_world 4 Press Next button A message box may
41. ww Broadcast IP Routing Enabled No WINS Proxy Enabled a No DNS Suffix Search List gateway 2wire net Ethernet adapter Local Area Connection Connection specific DNS Suffix gateway 2wire net Description Intel R PRO 100 VE Network Connection Physical Address 00 15 17 5C 35 11 Dhcp Enabled Yes Autoconfiguration Enabled Yes IP Address The NIC ID would therefore be 0015175c3511 With this information a license can be requested for at http www altera com support licensing lic university html An email should be received within 24 hours which has the license as an attachment see Appendix 1 For installation the licensing setup procedures as outlined by Altera should be followed 23 2 1 3 Program Design Flow The Quartus II design software provides a design environment that includes sample solutions for all phases of FPGA design Fig 20 Analysis Includes block based design system level design amp software development Power Analysis Debugging Engineering Change Management Timing Closure Programming amp Configuration Figure 20 Quartus II Design Flow 4 Figure 21 shows the Quartus II program design flow with the files that are generated by the compiler and assembler 24 from the Quartus Il Fitter Altera Programming
42. y block embedded multiplier block embedded multiplier PLL or IOE output PLL or IOE output amp Direct link Direct link interconnect interconnect to left to right Local Interconnect LAB Figure 14 Direct Link Connection 7 Dedicated row interconnects route signals to and from LABs PLLs M4K memory blocks and embedded multipliers within the same row while column interconnects perform the same functions with regards to columns The EP2C35 provides 16 global clock networks and four PLLs The Cyclone II clock network features include e 16 global clock networks e four PLLs e Global clock network dynamic clock source selection e Global clock network dynamic enable and disable Each global clock network has a clock control block to select from a number of input clock sources PLL clock outputs dedicated clock CLK pins dual purpose DPCLK pins and internal logic to drive onto the global clock network Fig 14 DPCLK pins function the same 16 as CLK pins but in addition can be used for signals for external memory interfaces In addition to 16 global clock networks and four PLLs the EP2C35 has 16 CLK pins and 20 DPCLK pins DPCLK 11 10 DPCLK 9 8 CDPCLK7 LU CLK 1 8 CDPCLK6 CDPCLKo J CDPCLK5 Clock Control Block 1 DPCLKo J DPCLK7 CLK 3 0 CLK 7 4 DPCLK1 L gt DPCLK6 Clock Control Block 1 GCLK 15 0 CDPCLK1 CDPCLK4 CDPCLK2 CLK 15 12 CDPCLK3 DPCLK 3 2 DPCLK 5 4 Figure 1
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